1 //===-- MipsSEISelDAGToDAG.cpp - A Dag to Dag Inst Selector for MipsSE ----===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // Subclass of MipsDAGToDAGISel specialized for mips32/64.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #include "MipsSEISelDAGToDAG.h"
15 #include "MCTargetDesc/MipsBaseInfo.h"
16 #include "Mips.h"
17 #include "MipsAnalyzeImmediate.h"
18 #include "MipsMachineFunction.h"
19 #include "MipsRegisterInfo.h"
20 #include "llvm/CodeGen/MachineConstantPool.h"
21 #include "llvm/CodeGen/MachineFrameInfo.h"
22 #include "llvm/CodeGen/MachineFunction.h"
23 #include "llvm/CodeGen/MachineInstrBuilder.h"
24 #include "llvm/CodeGen/MachineRegisterInfo.h"
25 #include "llvm/CodeGen/SelectionDAGNodes.h"
26 #include "llvm/IR/CFG.h"
27 #include "llvm/IR/GlobalValue.h"
28 #include "llvm/IR/Instructions.h"
29 #include "llvm/IR/Intrinsics.h"
30 #include "llvm/IR/Type.h"
31 #include "llvm/Support/Debug.h"
32 #include "llvm/Support/ErrorHandling.h"
33 #include "llvm/Support/raw_ostream.h"
34 #include "llvm/Target/TargetMachine.h"
35 using namespace llvm;
36 
37 #define DEBUG_TYPE "mips-isel"
38 
39 bool MipsSEDAGToDAGISel::runOnMachineFunction(MachineFunction &MF) {
40   Subtarget = &static_cast<const MipsSubtarget &>(MF.getSubtarget());
41   if (Subtarget->inMips16Mode())
42     return false;
43   return MipsDAGToDAGISel::runOnMachineFunction(MF);
44 }
45 
46 void MipsSEDAGToDAGISel::addDSPCtrlRegOperands(bool IsDef, MachineInstr &MI,
47                                                MachineFunction &MF) {
48   MachineInstrBuilder MIB(MF, &MI);
49   unsigned Mask = MI.getOperand(1).getImm();
50   unsigned Flag = IsDef ? RegState::ImplicitDefine : RegState::Implicit;
51 
52   if (Mask & 1)
53     MIB.addReg(Mips::DSPPos, Flag);
54 
55   if (Mask & 2)
56     MIB.addReg(Mips::DSPSCount, Flag);
57 
58   if (Mask & 4)
59     MIB.addReg(Mips::DSPCarry, Flag);
60 
61   if (Mask & 8)
62     MIB.addReg(Mips::DSPOutFlag, Flag);
63 
64   if (Mask & 16)
65     MIB.addReg(Mips::DSPCCond, Flag);
66 
67   if (Mask & 32)
68     MIB.addReg(Mips::DSPEFI, Flag);
69 }
70 
71 unsigned MipsSEDAGToDAGISel::getMSACtrlReg(const SDValue RegIdx) const {
72   switch (cast<ConstantSDNode>(RegIdx)->getZExtValue()) {
73   default:
74     llvm_unreachable("Could not map int to register");
75   case 0: return Mips::MSAIR;
76   case 1: return Mips::MSACSR;
77   case 2: return Mips::MSAAccess;
78   case 3: return Mips::MSASave;
79   case 4: return Mips::MSAModify;
80   case 5: return Mips::MSARequest;
81   case 6: return Mips::MSAMap;
82   case 7: return Mips::MSAUnmap;
83   }
84 }
85 
86 bool MipsSEDAGToDAGISel::replaceUsesWithZeroReg(MachineRegisterInfo *MRI,
87                                                 const MachineInstr& MI) {
88   unsigned DstReg = 0, ZeroReg = 0;
89 
90   // Check if MI is "addiu $dst, $zero, 0" or "daddiu $dst, $zero, 0".
91   if ((MI.getOpcode() == Mips::ADDiu) &&
92       (MI.getOperand(1).getReg() == Mips::ZERO) &&
93       (MI.getOperand(2).getImm() == 0)) {
94     DstReg = MI.getOperand(0).getReg();
95     ZeroReg = Mips::ZERO;
96   } else if ((MI.getOpcode() == Mips::DADDiu) &&
97              (MI.getOperand(1).getReg() == Mips::ZERO_64) &&
98              (MI.getOperand(2).getImm() == 0)) {
99     DstReg = MI.getOperand(0).getReg();
100     ZeroReg = Mips::ZERO_64;
101   }
102 
103   if (!DstReg)
104     return false;
105 
106   // Replace uses with ZeroReg.
107   for (MachineRegisterInfo::use_iterator U = MRI->use_begin(DstReg),
108        E = MRI->use_end(); U != E;) {
109     MachineOperand &MO = *U;
110     unsigned OpNo = U.getOperandNo();
111     MachineInstr *MI = MO.getParent();
112     ++U;
113 
114     // Do not replace if it is a phi's operand or is tied to def operand.
115     if (MI->isPHI() || MI->isRegTiedToDefOperand(OpNo) || MI->isPseudo())
116       continue;
117 
118     MO.setReg(ZeroReg);
119   }
120 
121   return true;
122 }
123 
124 void MipsSEDAGToDAGISel::initGlobalBaseReg(MachineFunction &MF) {
125   MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
126 
127   if (!MipsFI->globalBaseRegSet())
128     return;
129 
130   MachineBasicBlock &MBB = MF.front();
131   MachineBasicBlock::iterator I = MBB.begin();
132   MachineRegisterInfo &RegInfo = MF.getRegInfo();
133   const TargetInstrInfo &TII = *Subtarget->getInstrInfo();
134   DebugLoc DL = I != MBB.end() ? I->getDebugLoc() : DebugLoc();
135   unsigned V0, V1, GlobalBaseReg = MipsFI->getGlobalBaseReg();
136   const TargetRegisterClass *RC;
137   const MipsABIInfo &ABI = static_cast<const MipsTargetMachine &>(TM).getABI();
138   RC = (ABI.IsN64()) ? &Mips::GPR64RegClass : &Mips::GPR32RegClass;
139 
140   V0 = RegInfo.createVirtualRegister(RC);
141   V1 = RegInfo.createVirtualRegister(RC);
142 
143   if (ABI.IsN64()) {
144     MF.getRegInfo().addLiveIn(Mips::T9_64);
145     MBB.addLiveIn(Mips::T9_64);
146 
147     // lui $v0, %hi(%neg(%gp_rel(fname)))
148     // daddu $v1, $v0, $t9
149     // daddiu $globalbasereg, $v1, %lo(%neg(%gp_rel(fname)))
150     const GlobalValue *FName = MF.getFunction();
151     BuildMI(MBB, I, DL, TII.get(Mips::LUi64), V0)
152       .addGlobalAddress(FName, 0, MipsII::MO_GPOFF_HI);
153     BuildMI(MBB, I, DL, TII.get(Mips::DADDu), V1).addReg(V0)
154       .addReg(Mips::T9_64);
155     BuildMI(MBB, I, DL, TII.get(Mips::DADDiu), GlobalBaseReg).addReg(V1)
156       .addGlobalAddress(FName, 0, MipsII::MO_GPOFF_LO);
157     return;
158   }
159 
160   if (MF.getTarget().getRelocationModel() == Reloc::Static) {
161     // Set global register to __gnu_local_gp.
162     //
163     // lui   $v0, %hi(__gnu_local_gp)
164     // addiu $globalbasereg, $v0, %lo(__gnu_local_gp)
165     BuildMI(MBB, I, DL, TII.get(Mips::LUi), V0)
166       .addExternalSymbol("__gnu_local_gp", MipsII::MO_ABS_HI);
167     BuildMI(MBB, I, DL, TII.get(Mips::ADDiu), GlobalBaseReg).addReg(V0)
168       .addExternalSymbol("__gnu_local_gp", MipsII::MO_ABS_LO);
169     return;
170   }
171 
172   MF.getRegInfo().addLiveIn(Mips::T9);
173   MBB.addLiveIn(Mips::T9);
174 
175   if (ABI.IsN32()) {
176     // lui $v0, %hi(%neg(%gp_rel(fname)))
177     // addu $v1, $v0, $t9
178     // addiu $globalbasereg, $v1, %lo(%neg(%gp_rel(fname)))
179     const GlobalValue *FName = MF.getFunction();
180     BuildMI(MBB, I, DL, TII.get(Mips::LUi), V0)
181       .addGlobalAddress(FName, 0, MipsII::MO_GPOFF_HI);
182     BuildMI(MBB, I, DL, TII.get(Mips::ADDu), V1).addReg(V0).addReg(Mips::T9);
183     BuildMI(MBB, I, DL, TII.get(Mips::ADDiu), GlobalBaseReg).addReg(V1)
184       .addGlobalAddress(FName, 0, MipsII::MO_GPOFF_LO);
185     return;
186   }
187 
188   assert(ABI.IsO32());
189 
190   // For O32 ABI, the following instruction sequence is emitted to initialize
191   // the global base register:
192   //
193   //  0. lui   $2, %hi(_gp_disp)
194   //  1. addiu $2, $2, %lo(_gp_disp)
195   //  2. addu  $globalbasereg, $2, $t9
196   //
197   // We emit only the last instruction here.
198   //
199   // GNU linker requires that the first two instructions appear at the beginning
200   // of a function and no instructions be inserted before or between them.
201   // The two instructions are emitted during lowering to MC layer in order to
202   // avoid any reordering.
203   //
204   // Register $2 (Mips::V0) is added to the list of live-in registers to ensure
205   // the value instruction 1 (addiu) defines is valid when instruction 2 (addu)
206   // reads it.
207   MF.getRegInfo().addLiveIn(Mips::V0);
208   MBB.addLiveIn(Mips::V0);
209   BuildMI(MBB, I, DL, TII.get(Mips::ADDu), GlobalBaseReg)
210     .addReg(Mips::V0).addReg(Mips::T9);
211 }
212 
213 void MipsSEDAGToDAGISel::processFunctionAfterISel(MachineFunction &MF) {
214   initGlobalBaseReg(MF);
215 
216   MachineRegisterInfo *MRI = &MF.getRegInfo();
217 
218   for (MachineFunction::iterator MFI = MF.begin(), MFE = MF.end(); MFI != MFE;
219        ++MFI)
220     for (MachineBasicBlock::iterator I = MFI->begin(); I != MFI->end(); ++I) {
221       if (I->getOpcode() == Mips::RDDSP)
222         addDSPCtrlRegOperands(false, *I, MF);
223       else if (I->getOpcode() == Mips::WRDSP)
224         addDSPCtrlRegOperands(true, *I, MF);
225       else
226         replaceUsesWithZeroReg(MRI, *I);
227     }
228 }
229 
230 SDNode *MipsSEDAGToDAGISel::selectAddESubE(unsigned MOp, SDValue InFlag,
231                                            SDValue CmpLHS, SDLoc DL,
232                                            SDNode *Node) const {
233   unsigned Opc = InFlag.getOpcode(); (void)Opc;
234 
235   assert(((Opc == ISD::ADDC || Opc == ISD::ADDE) ||
236           (Opc == ISD::SUBC || Opc == ISD::SUBE)) &&
237          "(ADD|SUB)E flag operand must come from (ADD|SUB)C/E insn");
238 
239   unsigned SLTuOp = Mips::SLTu, ADDuOp = Mips::ADDu;
240   if (Subtarget->isGP64bit()) {
241     SLTuOp = Mips::SLTu64;
242     ADDuOp = Mips::DADDu;
243   }
244 
245   SDValue Ops[] = { CmpLHS, InFlag.getOperand(1) };
246   SDValue LHS = Node->getOperand(0), RHS = Node->getOperand(1);
247   EVT VT = LHS.getValueType();
248 
249   SDNode *Carry = CurDAG->getMachineNode(SLTuOp, DL, VT, Ops);
250 
251   if (Subtarget->isGP64bit()) {
252     // On 64-bit targets, sltu produces an i64 but our backend currently says
253     // that SLTu64 produces an i32. We need to fix this in the long run but for
254     // now, just make the DAG type-correct by asserting the upper bits are zero.
255     Carry = CurDAG->getMachineNode(Mips::SUBREG_TO_REG, DL, VT,
256                                    CurDAG->getTargetConstant(0, DL, VT),
257                                    SDValue(Carry, 0),
258                                    CurDAG->getTargetConstant(Mips::sub_32, DL,
259                                                              VT));
260   }
261 
262   // Generate a second addition only if we know that RHS is not a
263   // constant-zero node.
264   SDNode *AddCarry = Carry;
265   ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS);
266   if (!C || C->getZExtValue())
267     AddCarry = CurDAG->getMachineNode(ADDuOp, DL, VT, SDValue(Carry, 0), RHS);
268 
269   return CurDAG->SelectNodeTo(Node, MOp, VT, MVT::Glue, LHS,
270                               SDValue(AddCarry, 0));
271 }
272 
273 /// Match frameindex
274 bool MipsSEDAGToDAGISel::selectAddrFrameIndex(SDValue Addr, SDValue &Base,
275                                               SDValue &Offset) const {
276   if (FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>(Addr)) {
277     EVT ValTy = Addr.getValueType();
278 
279     Base   = CurDAG->getTargetFrameIndex(FIN->getIndex(), ValTy);
280     Offset = CurDAG->getTargetConstant(0, SDLoc(Addr), ValTy);
281     return true;
282   }
283   return false;
284 }
285 
286 /// Match frameindex+offset and frameindex|offset
287 bool MipsSEDAGToDAGISel::selectAddrFrameIndexOffset(SDValue Addr, SDValue &Base,
288                                                     SDValue &Offset,
289                                                     unsigned OffsetBits) const {
290   if (CurDAG->isBaseWithConstantOffset(Addr)) {
291     ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Addr.getOperand(1));
292     if (isIntN(OffsetBits, CN->getSExtValue())) {
293       EVT ValTy = Addr.getValueType();
294 
295       // If the first operand is a FI, get the TargetFI Node
296       if (FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>
297                                   (Addr.getOperand(0)))
298         Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), ValTy);
299       else
300         Base = Addr.getOperand(0);
301 
302       Offset = CurDAG->getTargetConstant(CN->getZExtValue(), SDLoc(Addr),
303                                          ValTy);
304       return true;
305     }
306   }
307   return false;
308 }
309 
310 /// ComplexPattern used on MipsInstrInfo
311 /// Used on Mips Load/Store instructions
312 bool MipsSEDAGToDAGISel::selectAddrRegImm(SDValue Addr, SDValue &Base,
313                                           SDValue &Offset) const {
314   // if Address is FI, get the TargetFrameIndex.
315   if (selectAddrFrameIndex(Addr, Base, Offset))
316     return true;
317 
318   // on PIC code Load GA
319   if (Addr.getOpcode() == MipsISD::Wrapper) {
320     Base   = Addr.getOperand(0);
321     Offset = Addr.getOperand(1);
322     return true;
323   }
324 
325   if (TM.getRelocationModel() != Reloc::PIC_) {
326     if ((Addr.getOpcode() == ISD::TargetExternalSymbol ||
327         Addr.getOpcode() == ISD::TargetGlobalAddress))
328       return false;
329   }
330 
331   // Addresses of the form FI+const or FI|const
332   if (selectAddrFrameIndexOffset(Addr, Base, Offset, 16))
333     return true;
334 
335   // Operand is a result from an ADD.
336   if (Addr.getOpcode() == ISD::ADD) {
337     // When loading from constant pools, load the lower address part in
338     // the instruction itself. Example, instead of:
339     //  lui $2, %hi($CPI1_0)
340     //  addiu $2, $2, %lo($CPI1_0)
341     //  lwc1 $f0, 0($2)
342     // Generate:
343     //  lui $2, %hi($CPI1_0)
344     //  lwc1 $f0, %lo($CPI1_0)($2)
345     if (Addr.getOperand(1).getOpcode() == MipsISD::Lo ||
346         Addr.getOperand(1).getOpcode() == MipsISD::GPRel) {
347       SDValue Opnd0 = Addr.getOperand(1).getOperand(0);
348       if (isa<ConstantPoolSDNode>(Opnd0) || isa<GlobalAddressSDNode>(Opnd0) ||
349           isa<JumpTableSDNode>(Opnd0)) {
350         Base = Addr.getOperand(0);
351         Offset = Opnd0;
352         return true;
353       }
354     }
355   }
356 
357   return false;
358 }
359 
360 /// ComplexPattern used on MipsInstrInfo
361 /// Used on Mips Load/Store instructions
362 bool MipsSEDAGToDAGISel::selectAddrRegReg(SDValue Addr, SDValue &Base,
363                                           SDValue &Offset) const {
364   // Operand is a result from an ADD.
365   if (Addr.getOpcode() == ISD::ADD) {
366     Base = Addr.getOperand(0);
367     Offset = Addr.getOperand(1);
368     return true;
369   }
370 
371   return false;
372 }
373 
374 bool MipsSEDAGToDAGISel::selectAddrDefault(SDValue Addr, SDValue &Base,
375                                            SDValue &Offset) const {
376   Base = Addr;
377   Offset = CurDAG->getTargetConstant(0, SDLoc(Addr), Addr.getValueType());
378   return true;
379 }
380 
381 bool MipsSEDAGToDAGISel::selectIntAddr(SDValue Addr, SDValue &Base,
382                                        SDValue &Offset) const {
383   return selectAddrRegImm(Addr, Base, Offset) ||
384     selectAddrDefault(Addr, Base, Offset);
385 }
386 
387 bool MipsSEDAGToDAGISel::selectAddrRegImm9(SDValue Addr, SDValue &Base,
388                                            SDValue &Offset) const {
389   if (selectAddrFrameIndex(Addr, Base, Offset))
390     return true;
391 
392   if (selectAddrFrameIndexOffset(Addr, Base, Offset, 9))
393     return true;
394 
395   return false;
396 }
397 
398 bool MipsSEDAGToDAGISel::selectAddrRegImm10(SDValue Addr, SDValue &Base,
399                                             SDValue &Offset) const {
400   if (selectAddrFrameIndex(Addr, Base, Offset))
401     return true;
402 
403   if (selectAddrFrameIndexOffset(Addr, Base, Offset, 10))
404     return true;
405 
406   return false;
407 }
408 
409 /// Used on microMIPS Load/Store unaligned instructions (12-bit offset)
410 bool MipsSEDAGToDAGISel::selectAddrRegImm12(SDValue Addr, SDValue &Base,
411                                             SDValue &Offset) const {
412   if (selectAddrFrameIndex(Addr, Base, Offset))
413     return true;
414 
415   if (selectAddrFrameIndexOffset(Addr, Base, Offset, 12))
416     return true;
417 
418   return false;
419 }
420 
421 bool MipsSEDAGToDAGISel::selectAddrRegImm16(SDValue Addr, SDValue &Base,
422                                             SDValue &Offset) const {
423   if (selectAddrFrameIndex(Addr, Base, Offset))
424     return true;
425 
426   if (selectAddrFrameIndexOffset(Addr, Base, Offset, 16))
427     return true;
428 
429   return false;
430 }
431 
432 bool MipsSEDAGToDAGISel::selectIntAddrMM(SDValue Addr, SDValue &Base,
433                                          SDValue &Offset) const {
434   return selectAddrRegImm12(Addr, Base, Offset) ||
435     selectAddrDefault(Addr, Base, Offset);
436 }
437 
438 bool MipsSEDAGToDAGISel::selectIntAddrLSL2MM(SDValue Addr, SDValue &Base,
439                                              SDValue &Offset) const {
440   if (selectAddrFrameIndexOffset(Addr, Base, Offset, 7)) {
441     if (isa<FrameIndexSDNode>(Base))
442       return false;
443 
444     if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Offset)) {
445       unsigned CnstOff = CN->getZExtValue();
446       return (CnstOff == (CnstOff & 0x3c));
447     }
448 
449     return false;
450   }
451 
452   // For all other cases where "lw" would be selected, don't select "lw16"
453   // because it would result in additional instructions to prepare operands.
454   if (selectAddrRegImm(Addr, Base, Offset))
455     return false;
456 
457   return selectAddrDefault(Addr, Base, Offset);
458 }
459 
460 bool MipsSEDAGToDAGISel::selectIntAddrMSA(SDValue Addr, SDValue &Base,
461                                           SDValue &Offset) const {
462   if (selectAddrRegImm10(Addr, Base, Offset))
463     return true;
464 
465   if (selectAddrDefault(Addr, Base, Offset))
466     return true;
467 
468   return false;
469 }
470 
471 // Select constant vector splats.
472 //
473 // Returns true and sets Imm if:
474 // * MSA is enabled
475 // * N is a ISD::BUILD_VECTOR representing a constant splat
476 bool MipsSEDAGToDAGISel::selectVSplat(SDNode *N, APInt &Imm,
477                                       unsigned MinSizeInBits) const {
478   if (!Subtarget->hasMSA())
479     return false;
480 
481   BuildVectorSDNode *Node = dyn_cast<BuildVectorSDNode>(N);
482 
483   if (!Node)
484     return false;
485 
486   APInt SplatValue, SplatUndef;
487   unsigned SplatBitSize;
488   bool HasAnyUndefs;
489 
490   if (!Node->isConstantSplat(SplatValue, SplatUndef, SplatBitSize, HasAnyUndefs,
491                              MinSizeInBits, !Subtarget->isLittle()))
492     return false;
493 
494   Imm = SplatValue;
495 
496   return true;
497 }
498 
499 // Select constant vector splats.
500 //
501 // In addition to the requirements of selectVSplat(), this function returns
502 // true and sets Imm if:
503 // * The splat value is the same width as the elements of the vector
504 // * The splat value fits in an integer with the specified signed-ness and
505 //   width.
506 //
507 // This function looks through ISD::BITCAST nodes.
508 // TODO: This might not be appropriate for big-endian MSA since BITCAST is
509 //       sometimes a shuffle in big-endian mode.
510 //
511 // It's worth noting that this function is not used as part of the selection
512 // of ldi.[bhwd] since it does not permit using the wrong-typed ldi.[bhwd]
513 // instruction to achieve the desired bit pattern. ldi.[bhwd] is selected in
514 // MipsSEDAGToDAGISel::selectNode.
515 bool MipsSEDAGToDAGISel::
516 selectVSplatCommon(SDValue N, SDValue &Imm, bool Signed,
517                    unsigned ImmBitSize) const {
518   APInt ImmValue;
519   EVT EltTy = N->getValueType(0).getVectorElementType();
520 
521   if (N->getOpcode() == ISD::BITCAST)
522     N = N->getOperand(0);
523 
524   if (selectVSplat(N.getNode(), ImmValue, EltTy.getSizeInBits()) &&
525       ImmValue.getBitWidth() == EltTy.getSizeInBits()) {
526 
527     if (( Signed && ImmValue.isSignedIntN(ImmBitSize)) ||
528         (!Signed && ImmValue.isIntN(ImmBitSize))) {
529       Imm = CurDAG->getTargetConstant(ImmValue, SDLoc(N), EltTy);
530       return true;
531     }
532   }
533 
534   return false;
535 }
536 
537 // Select constant vector splats.
538 bool MipsSEDAGToDAGISel::
539 selectVSplatUimm1(SDValue N, SDValue &Imm) const {
540   return selectVSplatCommon(N, Imm, false, 1);
541 }
542 
543 bool MipsSEDAGToDAGISel::
544 selectVSplatUimm2(SDValue N, SDValue &Imm) const {
545   return selectVSplatCommon(N, Imm, false, 2);
546 }
547 
548 bool MipsSEDAGToDAGISel::
549 selectVSplatUimm3(SDValue N, SDValue &Imm) const {
550   return selectVSplatCommon(N, Imm, false, 3);
551 }
552 
553 // Select constant vector splats.
554 bool MipsSEDAGToDAGISel::
555 selectVSplatUimm4(SDValue N, SDValue &Imm) const {
556   return selectVSplatCommon(N, Imm, false, 4);
557 }
558 
559 // Select constant vector splats.
560 bool MipsSEDAGToDAGISel::
561 selectVSplatUimm5(SDValue N, SDValue &Imm) const {
562   return selectVSplatCommon(N, Imm, false, 5);
563 }
564 
565 // Select constant vector splats.
566 bool MipsSEDAGToDAGISel::
567 selectVSplatUimm6(SDValue N, SDValue &Imm) const {
568   return selectVSplatCommon(N, Imm, false, 6);
569 }
570 
571 // Select constant vector splats.
572 bool MipsSEDAGToDAGISel::
573 selectVSplatUimm8(SDValue N, SDValue &Imm) const {
574   return selectVSplatCommon(N, Imm, false, 8);
575 }
576 
577 // Select constant vector splats.
578 bool MipsSEDAGToDAGISel::
579 selectVSplatSimm5(SDValue N, SDValue &Imm) const {
580   return selectVSplatCommon(N, Imm, true, 5);
581 }
582 
583 // Select constant vector splats whose value is a power of 2.
584 //
585 // In addition to the requirements of selectVSplat(), this function returns
586 // true and sets Imm if:
587 // * The splat value is the same width as the elements of the vector
588 // * The splat value is a power of two.
589 //
590 // This function looks through ISD::BITCAST nodes.
591 // TODO: This might not be appropriate for big-endian MSA since BITCAST is
592 //       sometimes a shuffle in big-endian mode.
593 bool MipsSEDAGToDAGISel::selectVSplatUimmPow2(SDValue N, SDValue &Imm) const {
594   APInt ImmValue;
595   EVT EltTy = N->getValueType(0).getVectorElementType();
596 
597   if (N->getOpcode() == ISD::BITCAST)
598     N = N->getOperand(0);
599 
600   if (selectVSplat(N.getNode(), ImmValue, EltTy.getSizeInBits()) &&
601       ImmValue.getBitWidth() == EltTy.getSizeInBits()) {
602     int32_t Log2 = ImmValue.exactLogBase2();
603 
604     if (Log2 != -1) {
605       Imm = CurDAG->getTargetConstant(Log2, SDLoc(N), EltTy);
606       return true;
607     }
608   }
609 
610   return false;
611 }
612 
613 // Select constant vector splats whose value only has a consecutive sequence
614 // of left-most bits set (e.g. 0b11...1100...00).
615 //
616 // In addition to the requirements of selectVSplat(), this function returns
617 // true and sets Imm if:
618 // * The splat value is the same width as the elements of the vector
619 // * The splat value is a consecutive sequence of left-most bits.
620 //
621 // This function looks through ISD::BITCAST nodes.
622 // TODO: This might not be appropriate for big-endian MSA since BITCAST is
623 //       sometimes a shuffle in big-endian mode.
624 bool MipsSEDAGToDAGISel::selectVSplatMaskL(SDValue N, SDValue &Imm) const {
625   APInt ImmValue;
626   EVT EltTy = N->getValueType(0).getVectorElementType();
627 
628   if (N->getOpcode() == ISD::BITCAST)
629     N = N->getOperand(0);
630 
631   if (selectVSplat(N.getNode(), ImmValue, EltTy.getSizeInBits()) &&
632       ImmValue.getBitWidth() == EltTy.getSizeInBits()) {
633     // Extract the run of set bits starting with bit zero from the bitwise
634     // inverse of ImmValue, and test that the inverse of this is the same
635     // as the original value.
636     if (ImmValue == ~(~ImmValue & ~(~ImmValue + 1))) {
637 
638       Imm = CurDAG->getTargetConstant(ImmValue.countPopulation(), SDLoc(N),
639                                       EltTy);
640       return true;
641     }
642   }
643 
644   return false;
645 }
646 
647 // Select constant vector splats whose value only has a consecutive sequence
648 // of right-most bits set (e.g. 0b00...0011...11).
649 //
650 // In addition to the requirements of selectVSplat(), this function returns
651 // true and sets Imm if:
652 // * The splat value is the same width as the elements of the vector
653 // * The splat value is a consecutive sequence of right-most bits.
654 //
655 // This function looks through ISD::BITCAST nodes.
656 // TODO: This might not be appropriate for big-endian MSA since BITCAST is
657 //       sometimes a shuffle in big-endian mode.
658 bool MipsSEDAGToDAGISel::selectVSplatMaskR(SDValue N, SDValue &Imm) const {
659   APInt ImmValue;
660   EVT EltTy = N->getValueType(0).getVectorElementType();
661 
662   if (N->getOpcode() == ISD::BITCAST)
663     N = N->getOperand(0);
664 
665   if (selectVSplat(N.getNode(), ImmValue, EltTy.getSizeInBits()) &&
666       ImmValue.getBitWidth() == EltTy.getSizeInBits()) {
667     // Extract the run of set bits starting with bit zero, and test that the
668     // result is the same as the original value
669     if (ImmValue == (ImmValue & ~(ImmValue + 1))) {
670       Imm = CurDAG->getTargetConstant(ImmValue.countPopulation(), SDLoc(N),
671                                       EltTy);
672       return true;
673     }
674   }
675 
676   return false;
677 }
678 
679 bool MipsSEDAGToDAGISel::selectVSplatUimmInvPow2(SDValue N,
680                                                  SDValue &Imm) const {
681   APInt ImmValue;
682   EVT EltTy = N->getValueType(0).getVectorElementType();
683 
684   if (N->getOpcode() == ISD::BITCAST)
685     N = N->getOperand(0);
686 
687   if (selectVSplat(N.getNode(), ImmValue, EltTy.getSizeInBits()) &&
688       ImmValue.getBitWidth() == EltTy.getSizeInBits()) {
689     int32_t Log2 = (~ImmValue).exactLogBase2();
690 
691     if (Log2 != -1) {
692       Imm = CurDAG->getTargetConstant(Log2, SDLoc(N), EltTy);
693       return true;
694     }
695   }
696 
697   return false;
698 }
699 
700 std::pair<bool, SDNode*> MipsSEDAGToDAGISel::selectNode(SDNode *Node) {
701   unsigned Opcode = Node->getOpcode();
702   SDLoc DL(Node);
703 
704   ///
705   // Instruction Selection not handled by the auto-generated
706   // tablegen selection should be handled here.
707   ///
708   SDNode *Result;
709 
710   switch(Opcode) {
711   default: break;
712 
713   case ISD::SUBE: {
714     SDValue InFlag = Node->getOperand(2);
715     unsigned Opc = Subtarget->isGP64bit() ? Mips::DSUBu : Mips::SUBu;
716     Result = selectAddESubE(Opc, InFlag, InFlag.getOperand(0), DL, Node);
717     return std::make_pair(true, Result);
718   }
719 
720   case ISD::ADDE: {
721     if (Subtarget->hasDSP()) // Select DSP instructions, ADDSC and ADDWC.
722       break;
723     SDValue InFlag = Node->getOperand(2);
724     unsigned Opc = Subtarget->isGP64bit() ? Mips::DADDu : Mips::ADDu;
725     Result = selectAddESubE(Opc, InFlag, InFlag.getValue(0), DL, Node);
726     return std::make_pair(true, Result);
727   }
728 
729   case ISD::ConstantFP: {
730     ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(Node);
731     if (Node->getValueType(0) == MVT::f64 && CN->isExactlyValue(+0.0)) {
732       if (Subtarget->isGP64bit()) {
733         SDValue Zero = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), DL,
734                                               Mips::ZERO_64, MVT::i64);
735         Result = CurDAG->getMachineNode(Mips::DMTC1, DL, MVT::f64, Zero);
736       } else if (Subtarget->isFP64bit()) {
737         SDValue Zero = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), DL,
738                                               Mips::ZERO, MVT::i32);
739         Result = CurDAG->getMachineNode(Mips::BuildPairF64_64, DL, MVT::f64,
740                                         Zero, Zero);
741       } else {
742         SDValue Zero = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), DL,
743                                               Mips::ZERO, MVT::i32);
744         Result = CurDAG->getMachineNode(Mips::BuildPairF64, DL, MVT::f64, Zero,
745                                         Zero);
746       }
747 
748       return std::make_pair(true, Result);
749     }
750     break;
751   }
752 
753   case ISD::Constant: {
754     const ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Node);
755     unsigned Size = CN->getValueSizeInBits(0);
756 
757     if (Size == 32)
758       break;
759 
760     MipsAnalyzeImmediate AnalyzeImm;
761     int64_t Imm = CN->getSExtValue();
762 
763     const MipsAnalyzeImmediate::InstSeq &Seq =
764       AnalyzeImm.Analyze(Imm, Size, false);
765 
766     MipsAnalyzeImmediate::InstSeq::const_iterator Inst = Seq.begin();
767     SDLoc DL(CN);
768     SDNode *RegOpnd;
769     SDValue ImmOpnd = CurDAG->getTargetConstant(SignExtend64<16>(Inst->ImmOpnd),
770                                                 DL, MVT::i64);
771 
772     // The first instruction can be a LUi which is different from other
773     // instructions (ADDiu, ORI and SLL) in that it does not have a register
774     // operand.
775     if (Inst->Opc == Mips::LUi64)
776       RegOpnd = CurDAG->getMachineNode(Inst->Opc, DL, MVT::i64, ImmOpnd);
777     else
778       RegOpnd =
779         CurDAG->getMachineNode(Inst->Opc, DL, MVT::i64,
780                                CurDAG->getRegister(Mips::ZERO_64, MVT::i64),
781                                ImmOpnd);
782 
783     // The remaining instructions in the sequence are handled here.
784     for (++Inst; Inst != Seq.end(); ++Inst) {
785       ImmOpnd = CurDAG->getTargetConstant(SignExtend64<16>(Inst->ImmOpnd), DL,
786                                           MVT::i64);
787       RegOpnd = CurDAG->getMachineNode(Inst->Opc, DL, MVT::i64,
788                                        SDValue(RegOpnd, 0), ImmOpnd);
789     }
790 
791     return std::make_pair(true, RegOpnd);
792   }
793 
794   case ISD::INTRINSIC_W_CHAIN: {
795     switch (cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue()) {
796     default:
797       break;
798 
799     case Intrinsic::mips_cfcmsa: {
800       SDValue ChainIn = Node->getOperand(0);
801       SDValue RegIdx = Node->getOperand(2);
802       SDValue Reg = CurDAG->getCopyFromReg(ChainIn, DL,
803                                            getMSACtrlReg(RegIdx), MVT::i32);
804       return std::make_pair(true, Reg.getNode());
805     }
806     }
807     break;
808   }
809 
810   case ISD::INTRINSIC_WO_CHAIN: {
811     switch (cast<ConstantSDNode>(Node->getOperand(0))->getZExtValue()) {
812     default:
813       break;
814 
815     case Intrinsic::mips_move_v:
816       // Like an assignment but will always produce a move.v even if
817       // unnecessary.
818       return std::make_pair(true,
819                             CurDAG->getMachineNode(Mips::MOVE_V, DL,
820                                                    Node->getValueType(0),
821                                                    Node->getOperand(1)));
822     }
823     break;
824   }
825 
826   case ISD::INTRINSIC_VOID: {
827     switch (cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue()) {
828     default:
829       break;
830 
831     case Intrinsic::mips_ctcmsa: {
832       SDValue ChainIn = Node->getOperand(0);
833       SDValue RegIdx  = Node->getOperand(2);
834       SDValue Value   = Node->getOperand(3);
835       SDValue ChainOut = CurDAG->getCopyToReg(ChainIn, DL,
836                                               getMSACtrlReg(RegIdx), Value);
837       return std::make_pair(true, ChainOut.getNode());
838     }
839     }
840     break;
841   }
842 
843   case MipsISD::ThreadPointer: {
844     EVT PtrVT = getTargetLowering()->getPointerTy(CurDAG->getDataLayout());
845     unsigned RdhwrOpc, DestReg;
846 
847     if (PtrVT == MVT::i32) {
848       RdhwrOpc = Mips::RDHWR;
849       DestReg = Mips::V1;
850     } else {
851       RdhwrOpc = Mips::RDHWR64;
852       DestReg = Mips::V1_64;
853     }
854 
855     SDNode *Rdhwr =
856       CurDAG->getMachineNode(RdhwrOpc, DL,
857                              Node->getValueType(0),
858                              CurDAG->getRegister(Mips::HWR29, MVT::i32));
859     SDValue Chain = CurDAG->getCopyToReg(CurDAG->getEntryNode(), DL, DestReg,
860                                          SDValue(Rdhwr, 0));
861     SDValue ResNode = CurDAG->getCopyFromReg(Chain, DL, DestReg, PtrVT);
862     ReplaceUses(SDValue(Node, 0), ResNode);
863     return std::make_pair(true, ResNode.getNode());
864   }
865 
866   case ISD::BUILD_VECTOR: {
867     // Select appropriate ldi.[bhwd] instructions for constant splats of
868     // 128-bit when MSA is enabled. Fixup any register class mismatches that
869     // occur as a result.
870     //
871     // This allows the compiler to use a wider range of immediates than would
872     // otherwise be allowed. If, for example, v4i32 could only use ldi.h then
873     // it would not be possible to load { 0x01010101, 0x01010101, 0x01010101,
874     // 0x01010101 } without using a constant pool. This would be sub-optimal
875     // when // 'ldi.b wd, 1' is capable of producing that bit-pattern in the
876     // same set/ of registers. Similarly, ldi.h isn't capable of producing {
877     // 0x00000000, 0x00000001, 0x00000000, 0x00000001 } but 'ldi.d wd, 1' can.
878 
879     BuildVectorSDNode *BVN = cast<BuildVectorSDNode>(Node);
880     APInt SplatValue, SplatUndef;
881     unsigned SplatBitSize;
882     bool HasAnyUndefs;
883     unsigned LdiOp;
884     EVT ResVecTy = BVN->getValueType(0);
885     EVT ViaVecTy;
886 
887     if (!Subtarget->hasMSA() || !BVN->getValueType(0).is128BitVector())
888       return std::make_pair(false, nullptr);
889 
890     if (!BVN->isConstantSplat(SplatValue, SplatUndef, SplatBitSize,
891                               HasAnyUndefs, 8,
892                               !Subtarget->isLittle()))
893       return std::make_pair(false, nullptr);
894 
895     switch (SplatBitSize) {
896     default:
897       return std::make_pair(false, nullptr);
898     case 8:
899       LdiOp = Mips::LDI_B;
900       ViaVecTy = MVT::v16i8;
901       break;
902     case 16:
903       LdiOp = Mips::LDI_H;
904       ViaVecTy = MVT::v8i16;
905       break;
906     case 32:
907       LdiOp = Mips::LDI_W;
908       ViaVecTy = MVT::v4i32;
909       break;
910     case 64:
911       LdiOp = Mips::LDI_D;
912       ViaVecTy = MVT::v2i64;
913       break;
914     }
915 
916     if (!SplatValue.isSignedIntN(10))
917       return std::make_pair(false, nullptr);
918 
919     SDValue Imm = CurDAG->getTargetConstant(SplatValue, DL,
920                                             ViaVecTy.getVectorElementType());
921 
922     SDNode *Res = CurDAG->getMachineNode(LdiOp, DL, ViaVecTy, Imm);
923 
924     if (ResVecTy != ViaVecTy) {
925       // If LdiOp is writing to a different register class to ResVecTy, then
926       // fix it up here. This COPY_TO_REGCLASS should never cause a move.v
927       // since the source and destination register sets contain the same
928       // registers.
929       const TargetLowering *TLI = getTargetLowering();
930       MVT ResVecTySimple = ResVecTy.getSimpleVT();
931       const TargetRegisterClass *RC = TLI->getRegClassFor(ResVecTySimple);
932       Res = CurDAG->getMachineNode(Mips::COPY_TO_REGCLASS, DL,
933                                    ResVecTy, SDValue(Res, 0),
934                                    CurDAG->getTargetConstant(RC->getID(), DL,
935                                                              MVT::i32));
936     }
937 
938     return std::make_pair(true, Res);
939   }
940 
941   }
942 
943   return std::make_pair(false, nullptr);
944 }
945 
946 bool MipsSEDAGToDAGISel::
947 SelectInlineAsmMemoryOperand(const SDValue &Op, unsigned ConstraintID,
948                              std::vector<SDValue> &OutOps) {
949   SDValue Base, Offset;
950 
951   switch(ConstraintID) {
952   default:
953     llvm_unreachable("Unexpected asm memory constraint");
954   // All memory constraints can at least accept raw pointers.
955   case InlineAsm::Constraint_i:
956     OutOps.push_back(Op);
957     OutOps.push_back(CurDAG->getTargetConstant(0, SDLoc(Op), MVT::i32));
958     return false;
959   case InlineAsm::Constraint_m:
960     if (selectAddrRegImm16(Op, Base, Offset)) {
961       OutOps.push_back(Base);
962       OutOps.push_back(Offset);
963       return false;
964     }
965     OutOps.push_back(Op);
966     OutOps.push_back(CurDAG->getTargetConstant(0, SDLoc(Op), MVT::i32));
967     return false;
968   case InlineAsm::Constraint_R:
969     // The 'R' constraint is supposed to be much more complicated than this.
970     // However, it's becoming less useful due to architectural changes and
971     // ought to be replaced by other constraints such as 'ZC'.
972     // For now, support 9-bit signed offsets which is supportable by all
973     // subtargets for all instructions.
974     if (selectAddrRegImm9(Op, Base, Offset)) {
975       OutOps.push_back(Base);
976       OutOps.push_back(Offset);
977       return false;
978     }
979     OutOps.push_back(Op);
980     OutOps.push_back(CurDAG->getTargetConstant(0, SDLoc(Op), MVT::i32));
981     return false;
982   case InlineAsm::Constraint_ZC:
983     // ZC matches whatever the pref, ll, and sc instructions can handle for the
984     // given subtarget.
985     if (Subtarget->inMicroMipsMode()) {
986       // On microMIPS, they can handle 12-bit offsets.
987       if (selectAddrRegImm12(Op, Base, Offset)) {
988         OutOps.push_back(Base);
989         OutOps.push_back(Offset);
990         return false;
991       }
992     } else if (Subtarget->hasMips32r6()) {
993       // On MIPS32r6/MIPS64r6, they can only handle 9-bit offsets.
994       if (selectAddrRegImm9(Op, Base, Offset)) {
995         OutOps.push_back(Base);
996         OutOps.push_back(Offset);
997         return false;
998       }
999     } else if (selectAddrRegImm16(Op, Base, Offset)) {
1000       // Prior to MIPS32r6/MIPS64r6, they can handle 16-bit offsets.
1001       OutOps.push_back(Base);
1002       OutOps.push_back(Offset);
1003       return false;
1004     }
1005     // In all cases, 0-bit offsets are acceptable.
1006     OutOps.push_back(Op);
1007     OutOps.push_back(CurDAG->getTargetConstant(0, SDLoc(Op), MVT::i32));
1008     return false;
1009   }
1010   return true;
1011 }
1012 
1013 FunctionPass *llvm::createMipsSEISelDag(MipsTargetMachine &TM) {
1014   return new MipsSEDAGToDAGISel(TM);
1015 }
1016