1 //===-- MipsSEFrameLowering.cpp - Mips32/64 Frame Information -------------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file contains the Mips32/64 implementation of TargetFrameLowering class.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #include "MipsSEFrameLowering.h"
15 #include "MCTargetDesc/MipsBaseInfo.h"
16 #include "MipsAnalyzeImmediate.h"
17 #include "MipsMachineFunction.h"
18 #include "MipsSEInstrInfo.h"
19 #include "llvm/CodeGen/MachineFrameInfo.h"
20 #include "llvm/CodeGen/MachineFunction.h"
21 #include "llvm/CodeGen/MachineInstrBuilder.h"
22 #include "llvm/CodeGen/MachineModuleInfo.h"
23 #include "llvm/CodeGen/MachineRegisterInfo.h"
24 #include "llvm/CodeGen/RegisterScavenging.h"
25 #include "llvm/IR/DataLayout.h"
26 #include "llvm/IR/Function.h"
27 #include "llvm/Support/CommandLine.h"
28 #include "llvm/Target/TargetOptions.h"
29 
30 using namespace llvm;
31 
32 namespace {
33 typedef MachineBasicBlock::iterator Iter;
34 
35 static std::pair<unsigned, unsigned> getMFHiLoOpc(unsigned Src) {
36   if (Mips::ACC64RegClass.contains(Src))
37     return std::make_pair((unsigned)Mips::PseudoMFHI,
38                           (unsigned)Mips::PseudoMFLO);
39 
40   if (Mips::ACC64DSPRegClass.contains(Src))
41     return std::make_pair((unsigned)Mips::MFHI_DSP, (unsigned)Mips::MFLO_DSP);
42 
43   if (Mips::ACC128RegClass.contains(Src))
44     return std::make_pair((unsigned)Mips::PseudoMFHI64,
45                           (unsigned)Mips::PseudoMFLO64);
46 
47   return std::make_pair(0, 0);
48 }
49 
50 /// Helper class to expand pseudos.
51 class ExpandPseudo {
52 public:
53   ExpandPseudo(MachineFunction &MF);
54   bool expand();
55 
56 private:
57   bool expandInstr(MachineBasicBlock &MBB, Iter I);
58   void expandLoadCCond(MachineBasicBlock &MBB, Iter I);
59   void expandStoreCCond(MachineBasicBlock &MBB, Iter I);
60   void expandLoadACC(MachineBasicBlock &MBB, Iter I, unsigned RegSize);
61   void expandStoreACC(MachineBasicBlock &MBB, Iter I, unsigned MFHiOpc,
62                       unsigned MFLoOpc, unsigned RegSize);
63   bool expandCopy(MachineBasicBlock &MBB, Iter I);
64   bool expandCopyACC(MachineBasicBlock &MBB, Iter I, unsigned MFHiOpc,
65                      unsigned MFLoOpc);
66 
67   MachineFunction &MF;
68   MachineRegisterInfo &MRI;
69 };
70 }
71 
72 ExpandPseudo::ExpandPseudo(MachineFunction &MF_)
73   : MF(MF_), MRI(MF.getRegInfo()) {}
74 
75 bool ExpandPseudo::expand() {
76   bool Expanded = false;
77 
78   for (MachineFunction::iterator BB = MF.begin(), BBEnd = MF.end();
79        BB != BBEnd; ++BB)
80     for (Iter I = BB->begin(), End = BB->end(); I != End;)
81       Expanded |= expandInstr(*BB, I++);
82 
83   return Expanded;
84 }
85 
86 bool ExpandPseudo::expandInstr(MachineBasicBlock &MBB, Iter I) {
87   switch(I->getOpcode()) {
88   case Mips::LOAD_CCOND_DSP:
89     expandLoadCCond(MBB, I);
90     break;
91   case Mips::STORE_CCOND_DSP:
92     expandStoreCCond(MBB, I);
93     break;
94   case Mips::LOAD_ACC64:
95   case Mips::LOAD_ACC64DSP:
96     expandLoadACC(MBB, I, 4);
97     break;
98   case Mips::LOAD_ACC128:
99     expandLoadACC(MBB, I, 8);
100     break;
101   case Mips::STORE_ACC64:
102     expandStoreACC(MBB, I, Mips::PseudoMFHI, Mips::PseudoMFLO, 4);
103     break;
104   case Mips::STORE_ACC64DSP:
105     expandStoreACC(MBB, I, Mips::MFHI_DSP, Mips::MFLO_DSP, 4);
106     break;
107   case Mips::STORE_ACC128:
108     expandStoreACC(MBB, I, Mips::PseudoMFHI64, Mips::PseudoMFLO64, 8);
109     break;
110   case TargetOpcode::COPY:
111     if (!expandCopy(MBB, I))
112       return false;
113     break;
114   default:
115     return false;
116   }
117 
118   MBB.erase(I);
119   return true;
120 }
121 
122 void ExpandPseudo::expandLoadCCond(MachineBasicBlock &MBB, Iter I) {
123   //  load $vr, FI
124   //  copy ccond, $vr
125 
126   assert(I->getOperand(0).isReg() && I->getOperand(1).isFI());
127 
128   const MipsSEInstrInfo &TII =
129     *static_cast<const MipsSEInstrInfo*>(MF.getTarget().getInstrInfo());
130   const MipsRegisterInfo &RegInfo =
131     *static_cast<const MipsRegisterInfo*>(MF.getTarget().getRegisterInfo());
132 
133   const TargetRegisterClass *RC = RegInfo.intRegClass(4);
134   unsigned VR = MRI.createVirtualRegister(RC);
135   unsigned Dst = I->getOperand(0).getReg(), FI = I->getOperand(1).getIndex();
136 
137   TII.loadRegFromStack(MBB, I, VR, FI, RC, &RegInfo, 0);
138   BuildMI(MBB, I, I->getDebugLoc(), TII.get(TargetOpcode::COPY), Dst)
139     .addReg(VR, RegState::Kill);
140 }
141 
142 void ExpandPseudo::expandStoreCCond(MachineBasicBlock &MBB, Iter I) {
143   //  copy $vr, ccond
144   //  store $vr, FI
145 
146   assert(I->getOperand(0).isReg() && I->getOperand(1).isFI());
147 
148   const MipsSEInstrInfo &TII =
149     *static_cast<const MipsSEInstrInfo*>(MF.getTarget().getInstrInfo());
150   const MipsRegisterInfo &RegInfo =
151     *static_cast<const MipsRegisterInfo*>(MF.getTarget().getRegisterInfo());
152 
153   const TargetRegisterClass *RC = RegInfo.intRegClass(4);
154   unsigned VR = MRI.createVirtualRegister(RC);
155   unsigned Src = I->getOperand(0).getReg(), FI = I->getOperand(1).getIndex();
156 
157   BuildMI(MBB, I, I->getDebugLoc(), TII.get(TargetOpcode::COPY), VR)
158     .addReg(Src, getKillRegState(I->getOperand(0).isKill()));
159   TII.storeRegToStack(MBB, I, VR, true, FI, RC, &RegInfo, 0);
160 }
161 
162 void ExpandPseudo::expandLoadACC(MachineBasicBlock &MBB, Iter I,
163                                  unsigned RegSize) {
164   //  load $vr0, FI
165   //  copy lo, $vr0
166   //  load $vr1, FI + 4
167   //  copy hi, $vr1
168 
169   assert(I->getOperand(0).isReg() && I->getOperand(1).isFI());
170 
171   const MipsSEInstrInfo &TII =
172     *static_cast<const MipsSEInstrInfo*>(MF.getTarget().getInstrInfo());
173   const MipsRegisterInfo &RegInfo =
174     *static_cast<const MipsRegisterInfo*>(MF.getTarget().getRegisterInfo());
175 
176   const TargetRegisterClass *RC = RegInfo.intRegClass(RegSize);
177   unsigned VR0 = MRI.createVirtualRegister(RC);
178   unsigned VR1 = MRI.createVirtualRegister(RC);
179   unsigned Dst = I->getOperand(0).getReg(), FI = I->getOperand(1).getIndex();
180   unsigned Lo = RegInfo.getSubReg(Dst, Mips::sub_lo);
181   unsigned Hi = RegInfo.getSubReg(Dst, Mips::sub_hi);
182   DebugLoc DL = I->getDebugLoc();
183   const MCInstrDesc &Desc = TII.get(TargetOpcode::COPY);
184 
185   TII.loadRegFromStack(MBB, I, VR0, FI, RC, &RegInfo, 0);
186   BuildMI(MBB, I, DL, Desc, Lo).addReg(VR0, RegState::Kill);
187   TII.loadRegFromStack(MBB, I, VR1, FI, RC, &RegInfo, RegSize);
188   BuildMI(MBB, I, DL, Desc, Hi).addReg(VR1, RegState::Kill);
189 }
190 
191 void ExpandPseudo::expandStoreACC(MachineBasicBlock &MBB, Iter I,
192                                   unsigned MFHiOpc, unsigned MFLoOpc,
193                                   unsigned RegSize) {
194   //  mflo $vr0, src
195   //  store $vr0, FI
196   //  mfhi $vr1, src
197   //  store $vr1, FI + 4
198 
199   assert(I->getOperand(0).isReg() && I->getOperand(1).isFI());
200 
201   const MipsSEInstrInfo &TII =
202     *static_cast<const MipsSEInstrInfo*>(MF.getTarget().getInstrInfo());
203   const MipsRegisterInfo &RegInfo =
204     *static_cast<const MipsRegisterInfo*>(MF.getTarget().getRegisterInfo());
205 
206   const TargetRegisterClass *RC = RegInfo.intRegClass(RegSize);
207   unsigned VR0 = MRI.createVirtualRegister(RC);
208   unsigned VR1 = MRI.createVirtualRegister(RC);
209   unsigned Src = I->getOperand(0).getReg(), FI = I->getOperand(1).getIndex();
210   unsigned SrcKill = getKillRegState(I->getOperand(0).isKill());
211   DebugLoc DL = I->getDebugLoc();
212 
213   BuildMI(MBB, I, DL, TII.get(MFLoOpc), VR0).addReg(Src);
214   TII.storeRegToStack(MBB, I, VR0, true, FI, RC, &RegInfo, 0);
215   BuildMI(MBB, I, DL, TII.get(MFHiOpc), VR1).addReg(Src, SrcKill);
216   TII.storeRegToStack(MBB, I, VR1, true, FI, RC, &RegInfo, RegSize);
217 }
218 
219 bool ExpandPseudo::expandCopy(MachineBasicBlock &MBB, Iter I) {
220   unsigned Src = I->getOperand(1).getReg();
221   std::pair<unsigned, unsigned> Opcodes = getMFHiLoOpc(Src);
222 
223   if (!Opcodes.first)
224     return false;
225 
226   return expandCopyACC(MBB, I, Opcodes.first, Opcodes.second);
227 }
228 
229 bool ExpandPseudo::expandCopyACC(MachineBasicBlock &MBB, Iter I,
230                                  unsigned MFHiOpc, unsigned MFLoOpc) {
231   //  mflo $vr0, src
232   //  copy dst_lo, $vr0
233   //  mfhi $vr1, src
234   //  copy dst_hi, $vr1
235 
236   const MipsSEInstrInfo &TII =
237     *static_cast<const MipsSEInstrInfo*>(MF.getTarget().getInstrInfo());
238   const MipsRegisterInfo &RegInfo =
239     *static_cast<const MipsRegisterInfo*>(MF.getTarget().getRegisterInfo());
240 
241   unsigned Dst = I->getOperand(0).getReg(), Src = I->getOperand(1).getReg();
242   unsigned VRegSize = RegInfo.getMinimalPhysRegClass(Dst)->getSize() / 2;
243   const TargetRegisterClass *RC = RegInfo.intRegClass(VRegSize);
244   unsigned VR0 = MRI.createVirtualRegister(RC);
245   unsigned VR1 = MRI.createVirtualRegister(RC);
246   unsigned SrcKill = getKillRegState(I->getOperand(1).isKill());
247   unsigned DstLo = RegInfo.getSubReg(Dst, Mips::sub_lo);
248   unsigned DstHi = RegInfo.getSubReg(Dst, Mips::sub_hi);
249   DebugLoc DL = I->getDebugLoc();
250 
251   BuildMI(MBB, I, DL, TII.get(MFLoOpc), VR0).addReg(Src);
252   BuildMI(MBB, I, DL, TII.get(TargetOpcode::COPY), DstLo)
253     .addReg(VR0, RegState::Kill);
254   BuildMI(MBB, I, DL, TII.get(MFHiOpc), VR1).addReg(Src, SrcKill);
255   BuildMI(MBB, I, DL, TII.get(TargetOpcode::COPY), DstHi)
256     .addReg(VR1, RegState::Kill);
257   return true;
258 }
259 
260 unsigned MipsSEFrameLowering::ehDataReg(unsigned I) const {
261   static const unsigned EhDataReg[] = {
262     Mips::A0, Mips::A1, Mips::A2, Mips::A3
263   };
264   static const unsigned EhDataReg64[] = {
265     Mips::A0_64, Mips::A1_64, Mips::A2_64, Mips::A3_64
266   };
267 
268   return STI.isABI_N64() ? EhDataReg64[I] : EhDataReg[I];
269 }
270 
271 void MipsSEFrameLowering::emitPrologue(MachineFunction &MF) const {
272   MachineBasicBlock &MBB   = MF.front();
273   MachineFrameInfo *MFI    = MF.getFrameInfo();
274   MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
275 
276   const MipsSEInstrInfo &TII =
277     *static_cast<const MipsSEInstrInfo*>(MF.getTarget().getInstrInfo());
278   const MipsRegisterInfo &RegInfo =
279     *static_cast<const MipsRegisterInfo*>(MF.getTarget().getRegisterInfo());
280 
281   MachineBasicBlock::iterator MBBI = MBB.begin();
282   DebugLoc dl = MBBI != MBB.end() ? MBBI->getDebugLoc() : DebugLoc();
283   unsigned SP = STI.isABI_N64() ? Mips::SP_64 : Mips::SP;
284   unsigned FP = STI.isABI_N64() ? Mips::FP_64 : Mips::FP;
285   unsigned ZERO = STI.isABI_N64() ? Mips::ZERO_64 : Mips::ZERO;
286   unsigned ADDu = STI.isABI_N64() ? Mips::DADDu : Mips::ADDu;
287 
288   // First, compute final stack size.
289   uint64_t StackSize = MFI->getStackSize();
290 
291   // No need to allocate space on the stack.
292   if (StackSize == 0 && !MFI->adjustsStack()) return;
293 
294   MachineModuleInfo &MMI = MF.getMMI();
295   const MCRegisterInfo *MRI = MMI.getContext().getRegisterInfo();
296   MachineLocation DstML, SrcML;
297 
298   // Adjust stack.
299   TII.adjustStackPtr(SP, -StackSize, MBB, MBBI);
300 
301   // emit ".cfi_def_cfa_offset StackSize"
302   unsigned CFIIndex = MMI.addFrameInst(
303       MCCFIInstruction::createDefCfaOffset(nullptr, -StackSize));
304   BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
305       .addCFIIndex(CFIIndex);
306 
307   const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo();
308 
309   if (CSI.size()) {
310     // Find the instruction past the last instruction that saves a callee-saved
311     // register to the stack.
312     for (unsigned i = 0; i < CSI.size(); ++i)
313       ++MBBI;
314 
315     // Iterate over list of callee-saved registers and emit .cfi_offset
316     // directives.
317     for (std::vector<CalleeSavedInfo>::const_iterator I = CSI.begin(),
318            E = CSI.end(); I != E; ++I) {
319       int64_t Offset = MFI->getObjectOffset(I->getFrameIdx());
320       unsigned Reg = I->getReg();
321 
322       // If Reg is a double precision register, emit two cfa_offsets,
323       // one for each of the paired single precision registers.
324       if (Mips::AFGR64RegClass.contains(Reg)) {
325         unsigned Reg0 =
326             MRI->getDwarfRegNum(RegInfo.getSubReg(Reg, Mips::sub_lo), true);
327         unsigned Reg1 =
328             MRI->getDwarfRegNum(RegInfo.getSubReg(Reg, Mips::sub_hi), true);
329 
330         if (!STI.isLittle())
331           std::swap(Reg0, Reg1);
332 
333         unsigned CFIIndex = MMI.addFrameInst(
334             MCCFIInstruction::createOffset(nullptr, Reg0, Offset));
335         BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
336             .addCFIIndex(CFIIndex);
337 
338         CFIIndex = MMI.addFrameInst(
339             MCCFIInstruction::createOffset(nullptr, Reg1, Offset + 4));
340         BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
341             .addCFIIndex(CFIIndex);
342       } else {
343         // Reg is either in GPR32 or FGR32.
344         unsigned CFIIndex = MMI.addFrameInst(MCCFIInstruction::createOffset(
345             nullptr, MRI->getDwarfRegNum(Reg, 1), Offset));
346         BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
347             .addCFIIndex(CFIIndex);
348       }
349     }
350   }
351 
352   if (MipsFI->callsEhReturn()) {
353     const TargetRegisterClass *RC = STI.isABI_N64() ?
354         &Mips::GPR64RegClass : &Mips::GPR32RegClass;
355 
356     // Insert instructions that spill eh data registers.
357     for (int I = 0; I < 4; ++I) {
358       if (!MBB.isLiveIn(ehDataReg(I)))
359         MBB.addLiveIn(ehDataReg(I));
360       TII.storeRegToStackSlot(MBB, MBBI, ehDataReg(I), false,
361                               MipsFI->getEhDataRegFI(I), RC, &RegInfo);
362     }
363 
364     // Emit .cfi_offset directives for eh data registers.
365     for (int I = 0; I < 4; ++I) {
366       int64_t Offset = MFI->getObjectOffset(MipsFI->getEhDataRegFI(I));
367       unsigned Reg = MRI->getDwarfRegNum(ehDataReg(I), true);
368       unsigned CFIIndex = MMI.addFrameInst(
369           MCCFIInstruction::createOffset(nullptr, Reg, Offset));
370       BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
371           .addCFIIndex(CFIIndex);
372     }
373   }
374 
375   // if framepointer enabled, set it to point to the stack pointer.
376   if (hasFP(MF)) {
377     // Insert instruction "move $fp, $sp" at this location.
378     BuildMI(MBB, MBBI, dl, TII.get(ADDu), FP).addReg(SP).addReg(ZERO)
379       .setMIFlag(MachineInstr::FrameSetup);
380 
381     // emit ".cfi_def_cfa_register $fp"
382     unsigned CFIIndex = MMI.addFrameInst(MCCFIInstruction::createDefCfaRegister(
383         nullptr, MRI->getDwarfRegNum(FP, true)));
384     BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
385         .addCFIIndex(CFIIndex);
386   }
387 }
388 
389 void MipsSEFrameLowering::emitEpilogue(MachineFunction &MF,
390                                        MachineBasicBlock &MBB) const {
391   MachineBasicBlock::iterator MBBI = MBB.getLastNonDebugInstr();
392   MachineFrameInfo *MFI            = MF.getFrameInfo();
393   MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
394 
395   const MipsSEInstrInfo &TII =
396     *static_cast<const MipsSEInstrInfo*>(MF.getTarget().getInstrInfo());
397   const MipsRegisterInfo &RegInfo =
398     *static_cast<const MipsRegisterInfo*>(MF.getTarget().getRegisterInfo());
399 
400   DebugLoc dl = MBBI->getDebugLoc();
401   unsigned SP = STI.isABI_N64() ? Mips::SP_64 : Mips::SP;
402   unsigned FP = STI.isABI_N64() ? Mips::FP_64 : Mips::FP;
403   unsigned ZERO = STI.isABI_N64() ? Mips::ZERO_64 : Mips::ZERO;
404   unsigned ADDu = STI.isABI_N64() ? Mips::DADDu : Mips::ADDu;
405 
406   // if framepointer enabled, restore the stack pointer.
407   if (hasFP(MF)) {
408     // Find the first instruction that restores a callee-saved register.
409     MachineBasicBlock::iterator I = MBBI;
410 
411     for (unsigned i = 0; i < MFI->getCalleeSavedInfo().size(); ++i)
412       --I;
413 
414     // Insert instruction "move $sp, $fp" at this location.
415     BuildMI(MBB, I, dl, TII.get(ADDu), SP).addReg(FP).addReg(ZERO);
416   }
417 
418   if (MipsFI->callsEhReturn()) {
419     const TargetRegisterClass *RC = STI.isABI_N64() ?
420         &Mips::GPR64RegClass : &Mips::GPR32RegClass;
421 
422     // Find first instruction that restores a callee-saved register.
423     MachineBasicBlock::iterator I = MBBI;
424     for (unsigned i = 0; i < MFI->getCalleeSavedInfo().size(); ++i)
425       --I;
426 
427     // Insert instructions that restore eh data registers.
428     for (int J = 0; J < 4; ++J) {
429       TII.loadRegFromStackSlot(MBB, I, ehDataReg(J), MipsFI->getEhDataRegFI(J),
430                                RC, &RegInfo);
431     }
432   }
433 
434   // Get the number of bytes from FrameInfo
435   uint64_t StackSize = MFI->getStackSize();
436 
437   if (!StackSize)
438     return;
439 
440   // Adjust stack.
441   TII.adjustStackPtr(SP, StackSize, MBB, MBBI);
442 }
443 
444 bool MipsSEFrameLowering::
445 spillCalleeSavedRegisters(MachineBasicBlock &MBB,
446                           MachineBasicBlock::iterator MI,
447                           const std::vector<CalleeSavedInfo> &CSI,
448                           const TargetRegisterInfo *TRI) const {
449   MachineFunction *MF = MBB.getParent();
450   MachineBasicBlock *EntryBlock = MF->begin();
451   const TargetInstrInfo &TII = *MF->getTarget().getInstrInfo();
452 
453   for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
454     // Add the callee-saved register as live-in. Do not add if the register is
455     // RA and return address is taken, because it has already been added in
456     // method MipsTargetLowering::LowerRETURNADDR.
457     // It's killed at the spill, unless the register is RA and return address
458     // is taken.
459     unsigned Reg = CSI[i].getReg();
460     bool IsRAAndRetAddrIsTaken = (Reg == Mips::RA || Reg == Mips::RA_64)
461         && MF->getFrameInfo()->isReturnAddressTaken();
462     if (!IsRAAndRetAddrIsTaken)
463       EntryBlock->addLiveIn(Reg);
464 
465     // Insert the spill to the stack frame.
466     bool IsKill = !IsRAAndRetAddrIsTaken;
467     const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg);
468     TII.storeRegToStackSlot(*EntryBlock, MI, Reg, IsKill,
469                             CSI[i].getFrameIdx(), RC, TRI);
470   }
471 
472   return true;
473 }
474 
475 bool
476 MipsSEFrameLowering::hasReservedCallFrame(const MachineFunction &MF) const {
477   const MachineFrameInfo *MFI = MF.getFrameInfo();
478 
479   // Reserve call frame if the size of the maximum call frame fits into 16-bit
480   // immediate field and there are no variable sized objects on the stack.
481   // Make sure the second register scavenger spill slot can be accessed with one
482   // instruction.
483   return isInt<16>(MFI->getMaxCallFrameSize() + getStackAlignment()) &&
484     !MFI->hasVarSizedObjects();
485 }
486 
487 // Eliminate ADJCALLSTACKDOWN, ADJCALLSTACKUP pseudo instructions
488 void MipsSEFrameLowering::
489 eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
490                               MachineBasicBlock::iterator I) const {
491   const MipsSEInstrInfo &TII =
492     *static_cast<const MipsSEInstrInfo*>(MF.getTarget().getInstrInfo());
493 
494   if (!hasReservedCallFrame(MF)) {
495     int64_t Amount = I->getOperand(0).getImm();
496 
497     if (I->getOpcode() == Mips::ADJCALLSTACKDOWN)
498       Amount = -Amount;
499 
500     unsigned SP = STI.isABI_N64() ? Mips::SP_64 : Mips::SP;
501     TII.adjustStackPtr(SP, Amount, MBB, I);
502   }
503 
504   MBB.erase(I);
505 }
506 
507 void MipsSEFrameLowering::
508 processFunctionBeforeCalleeSavedScan(MachineFunction &MF,
509                                      RegScavenger *RS) const {
510   MachineRegisterInfo &MRI = MF.getRegInfo();
511   MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
512   unsigned FP = STI.isABI_N64() ? Mips::FP_64 : Mips::FP;
513 
514   // Mark $fp as used if function has dedicated frame pointer.
515   if (hasFP(MF))
516     MRI.setPhysRegUsed(FP);
517 
518   // Create spill slots for eh data registers if function calls eh_return.
519   if (MipsFI->callsEhReturn())
520     MipsFI->createEhDataRegsFI();
521 
522   // Expand pseudo instructions which load, store or copy accumulators.
523   // Add an emergency spill slot if a pseudo was expanded.
524   if (ExpandPseudo(MF).expand()) {
525     // The spill slot should be half the size of the accumulator. If target is
526     // mips64, it should be 64-bit, otherwise it should be 32-bt.
527     const TargetRegisterClass *RC = STI.hasMips64() ?
528       &Mips::GPR64RegClass : &Mips::GPR32RegClass;
529     int FI = MF.getFrameInfo()->CreateStackObject(RC->getSize(),
530                                                   RC->getAlignment(), false);
531     RS->addScavengingFrameIndex(FI);
532   }
533 
534   // Set scavenging frame index if necessary.
535   uint64_t MaxSPOffset = MF.getInfo<MipsFunctionInfo>()->getIncomingArgSize() +
536     estimateStackSize(MF);
537 
538   if (isInt<16>(MaxSPOffset))
539     return;
540 
541   const TargetRegisterClass *RC = STI.isABI_N64() ?
542     &Mips::GPR64RegClass : &Mips::GPR32RegClass;
543   int FI = MF.getFrameInfo()->CreateStackObject(RC->getSize(),
544                                                 RC->getAlignment(), false);
545   RS->addScavengingFrameIndex(FI);
546 }
547 
548 const MipsFrameLowering *
549 llvm::createMipsSEFrameLowering(const MipsSubtarget &ST) {
550   return new MipsSEFrameLowering(ST);
551 }
552