1 //===- MipsRegisterInfo.cpp - MIPS Register Information -------------------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file contains the MIPS implementation of the TargetRegisterInfo class.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #include "MipsRegisterInfo.h"
15 #include "MCTargetDesc/MipsABIInfo.h"
16 #include "Mips.h"
17 #include "MipsMachineFunction.h"
18 #include "MipsSubtarget.h"
19 #include "MipsTargetMachine.h"
20 #include "llvm/ADT/BitVector.h"
21 #include "llvm/ADT/STLExtras.h"
22 #include "llvm/CodeGen/MachineFrameInfo.h"
23 #include "llvm/CodeGen/MachineFunction.h"
24 #include "llvm/CodeGen/MachineInstr.h"
25 #include "llvm/CodeGen/MachineRegisterInfo.h"
26 #include "llvm/CodeGen/TargetFrameLowering.h"
27 #include "llvm/CodeGen/TargetRegisterInfo.h"
28 #include "llvm/CodeGen/TargetSubtargetInfo.h"
29 #include "llvm/IR/Function.h"
30 #include "llvm/MC/MCRegisterInfo.h"
31 #include "llvm/Support/Debug.h"
32 #include "llvm/Support/ErrorHandling.h"
33 #include "llvm/Support/raw_ostream.h"
34 #include <cstdint>
35 
36 using namespace llvm;
37 
38 #define DEBUG_TYPE "mips-reg-info"
39 
40 #define GET_REGINFO_TARGET_DESC
41 #include "MipsGenRegisterInfo.inc"
42 
43 MipsRegisterInfo::MipsRegisterInfo() : MipsGenRegisterInfo(Mips::RA) {}
44 
45 unsigned MipsRegisterInfo::getPICCallReg() { return Mips::T9; }
46 
47 const TargetRegisterClass *
48 MipsRegisterInfo::getPointerRegClass(const MachineFunction &MF,
49                                      unsigned Kind) const {
50   MipsABIInfo ABI = MF.getSubtarget<MipsSubtarget>().getABI();
51   MipsPtrClass PtrClassKind = static_cast<MipsPtrClass>(Kind);
52 
53   switch (PtrClassKind) {
54   case MipsPtrClass::Default:
55     return ABI.ArePtrs64bit() ? &Mips::GPR64RegClass : &Mips::GPR32RegClass;
56   case MipsPtrClass::GPR16MM:
57     return &Mips::GPRMM16RegClass;
58   case MipsPtrClass::StackPointer:
59     return ABI.ArePtrs64bit() ? &Mips::SP64RegClass : &Mips::SP32RegClass;
60   case MipsPtrClass::GlobalPointer:
61     return ABI.ArePtrs64bit() ? &Mips::GP64RegClass : &Mips::GP32RegClass;
62   }
63 
64   llvm_unreachable("Unknown pointer kind");
65 }
66 
67 unsigned
68 MipsRegisterInfo::getRegPressureLimit(const TargetRegisterClass *RC,
69                                       MachineFunction &MF) const {
70   switch (RC->getID()) {
71   default:
72     return 0;
73   case Mips::GPR32RegClassID:
74   case Mips::GPR64RegClassID:
75   case Mips::DSPRRegClassID: {
76     const TargetFrameLowering *TFI = MF.getSubtarget().getFrameLowering();
77     return 28 - TFI->hasFP(MF);
78   }
79   case Mips::FGR32RegClassID:
80     return 32;
81   case Mips::AFGR64RegClassID:
82     return 16;
83   case Mips::FGR64RegClassID:
84     return 32;
85   }
86 }
87 
88 //===----------------------------------------------------------------------===//
89 // Callee Saved Registers methods
90 //===----------------------------------------------------------------------===//
91 
92 /// Mips Callee Saved Registers
93 const MCPhysReg *
94 MipsRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
95   const MipsSubtarget &Subtarget = MF->getSubtarget<MipsSubtarget>();
96   const Function &F = MF->getFunction();
97   if (F.hasFnAttribute("interrupt")) {
98     if (Subtarget.hasMips64())
99       return Subtarget.hasMips64r6() ? CSR_Interrupt_64R6_SaveList
100                                      : CSR_Interrupt_64_SaveList;
101     else
102       return Subtarget.hasMips32r6() ? CSR_Interrupt_32R6_SaveList
103                                      : CSR_Interrupt_32_SaveList;
104   }
105 
106   if (Subtarget.isSingleFloat())
107     return CSR_SingleFloatOnly_SaveList;
108 
109   if (Subtarget.isABI_N64())
110     return CSR_N64_SaveList;
111 
112   if (Subtarget.isABI_N32())
113     return CSR_N32_SaveList;
114 
115   if (Subtarget.isFP64bit())
116     return CSR_O32_FP64_SaveList;
117 
118   if (Subtarget.isFPXX())
119     return CSR_O32_FPXX_SaveList;
120 
121   return CSR_O32_SaveList;
122 }
123 
124 const uint32_t *
125 MipsRegisterInfo::getCallPreservedMask(const MachineFunction &MF,
126                                        CallingConv::ID) const {
127   const MipsSubtarget &Subtarget = MF.getSubtarget<MipsSubtarget>();
128   if (Subtarget.isSingleFloat())
129     return CSR_SingleFloatOnly_RegMask;
130 
131   if (Subtarget.isABI_N64())
132     return CSR_N64_RegMask;
133 
134   if (Subtarget.isABI_N32())
135     return CSR_N32_RegMask;
136 
137   if (Subtarget.isFP64bit())
138     return CSR_O32_FP64_RegMask;
139 
140   if (Subtarget.isFPXX())
141     return CSR_O32_FPXX_RegMask;
142 
143   return CSR_O32_RegMask;
144 }
145 
146 const uint32_t *MipsRegisterInfo::getMips16RetHelperMask() {
147   return CSR_Mips16RetHelper_RegMask;
148 }
149 
150 BitVector MipsRegisterInfo::
151 getReservedRegs(const MachineFunction &MF) const {
152   static const MCPhysReg ReservedGPR32[] = {
153     Mips::ZERO, Mips::K0, Mips::K1, Mips::SP
154   };
155 
156   static const MCPhysReg ReservedGPR64[] = {
157     Mips::ZERO_64, Mips::K0_64, Mips::K1_64, Mips::SP_64
158   };
159 
160   BitVector Reserved(getNumRegs());
161   const MipsSubtarget &Subtarget = MF.getSubtarget<MipsSubtarget>();
162 
163   using RegIter = TargetRegisterClass::const_iterator;
164 
165   for (unsigned I = 0; I < array_lengthof(ReservedGPR32); ++I)
166     Reserved.set(ReservedGPR32[I]);
167 
168   // Reserve registers for the NaCl sandbox.
169   if (Subtarget.isTargetNaCl()) {
170     Reserved.set(Mips::T6);   // Reserved for control flow mask.
171     Reserved.set(Mips::T7);   // Reserved for memory access mask.
172     Reserved.set(Mips::T8);   // Reserved for thread pointer.
173   }
174 
175   for (unsigned I = 0; I < array_lengthof(ReservedGPR64); ++I)
176     Reserved.set(ReservedGPR64[I]);
177 
178   // For mno-abicalls, GP is a program invariant!
179   if (!Subtarget.isABICalls()) {
180     Reserved.set(Mips::GP);
181     Reserved.set(Mips::GP_64);
182   }
183 
184   if (Subtarget.isFP64bit()) {
185     // Reserve all registers in AFGR64.
186     for (RegIter Reg = Mips::AFGR64RegClass.begin(),
187          EReg = Mips::AFGR64RegClass.end(); Reg != EReg; ++Reg)
188       Reserved.set(*Reg);
189   } else {
190     // Reserve all registers in FGR64.
191     for (RegIter Reg = Mips::FGR64RegClass.begin(),
192          EReg = Mips::FGR64RegClass.end(); Reg != EReg; ++Reg)
193       Reserved.set(*Reg);
194   }
195   // Reserve FP if this function should have a dedicated frame pointer register.
196   if (Subtarget.getFrameLowering()->hasFP(MF)) {
197     if (Subtarget.inMips16Mode())
198       Reserved.set(Mips::S0);
199     else {
200       Reserved.set(Mips::FP);
201       Reserved.set(Mips::FP_64);
202 
203       // Reserve the base register if we need to both realign the stack and
204       // allocate variable-sized objects at runtime. This should test the
205       // same conditions as MipsFrameLowering::hasBP().
206       if (needsStackRealignment(MF) &&
207           MF.getFrameInfo().hasVarSizedObjects()) {
208         Reserved.set(Mips::S7);
209         Reserved.set(Mips::S7_64);
210       }
211     }
212   }
213 
214   // Reserve hardware registers.
215   Reserved.set(Mips::HWR29);
216 
217   // Reserve DSP control register.
218   Reserved.set(Mips::DSPPos);
219   Reserved.set(Mips::DSPSCount);
220   Reserved.set(Mips::DSPCarry);
221   Reserved.set(Mips::DSPEFI);
222   Reserved.set(Mips::DSPOutFlag);
223 
224   // Reserve MSA control registers.
225   Reserved.set(Mips::MSAIR);
226   Reserved.set(Mips::MSACSR);
227   Reserved.set(Mips::MSAAccess);
228   Reserved.set(Mips::MSASave);
229   Reserved.set(Mips::MSAModify);
230   Reserved.set(Mips::MSARequest);
231   Reserved.set(Mips::MSAMap);
232   Reserved.set(Mips::MSAUnmap);
233 
234   // Reserve RA if in mips16 mode.
235   if (Subtarget.inMips16Mode()) {
236     const MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
237     Reserved.set(Mips::RA);
238     Reserved.set(Mips::RA_64);
239     Reserved.set(Mips::T0);
240     Reserved.set(Mips::T1);
241     if (MF.getFunction().hasFnAttribute("saveS2") || MipsFI->hasSaveS2())
242       Reserved.set(Mips::S2);
243   }
244 
245   // Reserve GP if small section is used.
246   if (Subtarget.useSmallSection()) {
247     Reserved.set(Mips::GP);
248     Reserved.set(Mips::GP_64);
249   }
250 
251   if (Subtarget.isABI_O32() && !Subtarget.useOddSPReg()) {
252     for (const auto &Reg : Mips::OddSPRegClass)
253       Reserved.set(Reg);
254   }
255 
256   return Reserved;
257 }
258 
259 bool
260 MipsRegisterInfo::requiresRegisterScavenging(const MachineFunction &MF) const {
261   return true;
262 }
263 
264 bool
265 MipsRegisterInfo::trackLivenessAfterRegAlloc(const MachineFunction &MF) const {
266   return true;
267 }
268 
269 // FrameIndex represent objects inside a abstract stack.
270 // We must replace FrameIndex with an stack/frame pointer
271 // direct reference.
272 void MipsRegisterInfo::
273 eliminateFrameIndex(MachineBasicBlock::iterator II, int SPAdj,
274                     unsigned FIOperandNum, RegScavenger *RS) const {
275   MachineInstr &MI = *II;
276   MachineFunction &MF = *MI.getParent()->getParent();
277 
278   LLVM_DEBUG(errs() << "\nFunction : " << MF.getName() << "\n";
279              errs() << "<--------->\n"
280                     << MI);
281 
282   int FrameIndex = MI.getOperand(FIOperandNum).getIndex();
283   uint64_t stackSize = MF.getFrameInfo().getStackSize();
284   int64_t spOffset = MF.getFrameInfo().getObjectOffset(FrameIndex);
285 
286   LLVM_DEBUG(errs() << "FrameIndex : " << FrameIndex << "\n"
287                     << "spOffset   : " << spOffset << "\n"
288                     << "stackSize  : " << stackSize << "\n"
289                     << "alignment  : "
290                     << MF.getFrameInfo().getObjectAlignment(FrameIndex)
291                     << "\n");
292 
293   eliminateFI(MI, FIOperandNum, FrameIndex, stackSize, spOffset);
294 }
295 
296 unsigned MipsRegisterInfo::
297 getFrameRegister(const MachineFunction &MF) const {
298   const MipsSubtarget &Subtarget = MF.getSubtarget<MipsSubtarget>();
299   const TargetFrameLowering *TFI = Subtarget.getFrameLowering();
300   bool IsN64 =
301       static_cast<const MipsTargetMachine &>(MF.getTarget()).getABI().IsN64();
302 
303   if (Subtarget.inMips16Mode())
304     return TFI->hasFP(MF) ? Mips::S0 : Mips::SP;
305   else
306     return TFI->hasFP(MF) ? (IsN64 ? Mips::FP_64 : Mips::FP) :
307                             (IsN64 ? Mips::SP_64 : Mips::SP);
308 }
309 
310 bool MipsRegisterInfo::canRealignStack(const MachineFunction &MF) const {
311   // Avoid realigning functions that explicitly do not want to be realigned.
312   // Normally, we should report an error when a function should be dynamically
313   // realigned but also has the attribute no-realign-stack. Unfortunately,
314   // with this attribute, MachineFrameInfo clamps each new object's alignment
315   // to that of the stack's alignment as specified by the ABI. As a result,
316   // the information of whether we have objects with larger alignment
317   // requirement than the stack's alignment is already lost at this point.
318   if (!TargetRegisterInfo::canRealignStack(MF))
319     return false;
320 
321   const MipsSubtarget &Subtarget = MF.getSubtarget<MipsSubtarget>();
322   unsigned FP = Subtarget.isGP32bit() ? Mips::FP : Mips::FP_64;
323   unsigned BP = Subtarget.isGP32bit() ? Mips::S7 : Mips::S7_64;
324 
325   // Support dynamic stack realignment only for targets with standard encoding.
326   if (!Subtarget.hasStandardEncoding())
327     return false;
328 
329   // We can't perform dynamic stack realignment if we can't reserve the
330   // frame pointer register.
331   if (!MF.getRegInfo().canReserveReg(FP))
332     return false;
333 
334   // We can realign the stack if we know the maximum call frame size and we
335   // don't have variable sized objects.
336   if (Subtarget.getFrameLowering()->hasReservedCallFrame(MF))
337     return true;
338 
339   // We have to reserve the base pointer register in the presence of variable
340   // sized objects.
341   return MF.getRegInfo().canReserveReg(BP);
342 }
343