1 //===-- MipsRegisterInfo.cpp - MIPS Register Information -== --------------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file contains the MIPS implementation of the TargetRegisterInfo class.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #include "MipsRegisterInfo.h"
15 #include "Mips.h"
16 #include "MipsInstrInfo.h"
17 #include "MipsMachineFunction.h"
18 #include "MipsSubtarget.h"
19 #include "MipsTargetMachine.h"
20 #include "llvm/ADT/BitVector.h"
21 #include "llvm/ADT/STLExtras.h"
22 #include "llvm/CodeGen/MachineFrameInfo.h"
23 #include "llvm/CodeGen/MachineFunction.h"
24 #include "llvm/CodeGen/MachineInstrBuilder.h"
25 #include "llvm/CodeGen/MachineRegisterInfo.h"
26 #include "llvm/IR/Constants.h"
27 #include "llvm/IR/DebugInfo.h"
28 #include "llvm/IR/Function.h"
29 #include "llvm/IR/Type.h"
30 #include "llvm/Support/Debug.h"
31 #include "llvm/Support/ErrorHandling.h"
32 #include "llvm/Support/raw_ostream.h"
33 #include "llvm/Target/TargetFrameLowering.h"
34 #include "llvm/Target/TargetInstrInfo.h"
35 #include "llvm/Target/TargetMachine.h"
36 #include "llvm/Target/TargetOptions.h"
37 
38 using namespace llvm;
39 
40 #define DEBUG_TYPE "mips-reg-info"
41 
42 #define GET_REGINFO_TARGET_DESC
43 #include "MipsGenRegisterInfo.inc"
44 
45 MipsRegisterInfo::MipsRegisterInfo() : MipsGenRegisterInfo(Mips::RA) {}
46 
47 unsigned MipsRegisterInfo::getPICCallReg() { return Mips::T9; }
48 
49 const TargetRegisterClass *
50 MipsRegisterInfo::getPointerRegClass(const MachineFunction &MF,
51                                      unsigned Kind) const {
52   MipsABIInfo ABI = MF.getSubtarget<MipsSubtarget>().getABI();
53   bool inMicroMips = MF.getSubtarget<MipsSubtarget>().inMicroMipsMode();
54 
55   return ABI.ArePtrs64bit() ?
56              inMicroMips ?
57                  &Mips::GPRMM16_64RegClass : &Mips::GPR64RegClass
58              : inMicroMips ?
59                  &Mips::GPRMM16RegClass : &Mips::GPR32RegClass;
60 }
61 
62 unsigned
63 MipsRegisterInfo::getRegPressureLimit(const TargetRegisterClass *RC,
64                                       MachineFunction &MF) const {
65   switch (RC->getID()) {
66   default:
67     return 0;
68   case Mips::GPR32RegClassID:
69   case Mips::GPR64RegClassID:
70   case Mips::DSPRRegClassID: {
71     const TargetFrameLowering *TFI = MF.getSubtarget().getFrameLowering();
72     return 28 - TFI->hasFP(MF);
73   }
74   case Mips::FGR32RegClassID:
75     return 32;
76   case Mips::AFGR64RegClassID:
77     return 16;
78   case Mips::FGR64RegClassID:
79     return 32;
80   }
81 }
82 
83 //===----------------------------------------------------------------------===//
84 // Callee Saved Registers methods
85 //===----------------------------------------------------------------------===//
86 
87 /// Mips Callee Saved Registers
88 const MCPhysReg *
89 MipsRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
90   const MipsSubtarget &Subtarget = MF->getSubtarget<MipsSubtarget>();
91   const Function *F = MF->getFunction();
92   if (F->hasFnAttribute("interrupt")) {
93     if (Subtarget.hasMips64())
94       return Subtarget.hasMips64r6() ? CSR_Interrupt_64R6_SaveList
95                                      : CSR_Interrupt_64_SaveList;
96     else
97       return Subtarget.hasMips32r6() ? CSR_Interrupt_32R6_SaveList
98                                      : CSR_Interrupt_32_SaveList;
99   }
100 
101   if (Subtarget.isSingleFloat())
102     return CSR_SingleFloatOnly_SaveList;
103 
104   if (Subtarget.isABI_N64())
105     return CSR_N64_SaveList;
106 
107   if (Subtarget.isABI_N32())
108     return CSR_N32_SaveList;
109 
110   if (Subtarget.isFP64bit())
111     return CSR_O32_FP64_SaveList;
112 
113   if (Subtarget.isFPXX())
114     return CSR_O32_FPXX_SaveList;
115 
116   return CSR_O32_SaveList;
117 }
118 
119 const uint32_t *
120 MipsRegisterInfo::getCallPreservedMask(const MachineFunction &MF,
121                                        CallingConv::ID) const {
122   const MipsSubtarget &Subtarget = MF.getSubtarget<MipsSubtarget>();
123   if (Subtarget.isSingleFloat())
124     return CSR_SingleFloatOnly_RegMask;
125 
126   if (Subtarget.isABI_N64())
127     return CSR_N64_RegMask;
128 
129   if (Subtarget.isABI_N32())
130     return CSR_N32_RegMask;
131 
132   if (Subtarget.isFP64bit())
133     return CSR_O32_FP64_RegMask;
134 
135   if (Subtarget.isFPXX())
136     return CSR_O32_FPXX_RegMask;
137 
138   return CSR_O32_RegMask;
139 }
140 
141 const uint32_t *MipsRegisterInfo::getMips16RetHelperMask() {
142   return CSR_Mips16RetHelper_RegMask;
143 }
144 
145 BitVector MipsRegisterInfo::
146 getReservedRegs(const MachineFunction &MF) const {
147   static const MCPhysReg ReservedGPR32[] = {
148     Mips::ZERO, Mips::K0, Mips::K1, Mips::SP
149   };
150 
151   static const MCPhysReg ReservedGPR64[] = {
152     Mips::ZERO_64, Mips::K0_64, Mips::K1_64, Mips::SP_64
153   };
154 
155   BitVector Reserved(getNumRegs());
156   const MipsSubtarget &Subtarget = MF.getSubtarget<MipsSubtarget>();
157   typedef TargetRegisterClass::const_iterator RegIter;
158 
159   for (unsigned I = 0; I < array_lengthof(ReservedGPR32); ++I)
160     Reserved.set(ReservedGPR32[I]);
161 
162   // Reserve registers for the NaCl sandbox.
163   if (Subtarget.isTargetNaCl()) {
164     Reserved.set(Mips::T6);   // Reserved for control flow mask.
165     Reserved.set(Mips::T7);   // Reserved for memory access mask.
166     Reserved.set(Mips::T8);   // Reserved for thread pointer.
167   }
168 
169   for (unsigned I = 0; I < array_lengthof(ReservedGPR64); ++I)
170     Reserved.set(ReservedGPR64[I]);
171 
172   // For mno-abicalls, GP is a program invariant!
173   if (!Subtarget.isABICalls()) {
174     Reserved.set(Mips::GP);
175     Reserved.set(Mips::GP_64);
176   }
177 
178   if (Subtarget.isFP64bit()) {
179     // Reserve all registers in AFGR64.
180     for (RegIter Reg = Mips::AFGR64RegClass.begin(),
181          EReg = Mips::AFGR64RegClass.end(); Reg != EReg; ++Reg)
182       Reserved.set(*Reg);
183   } else {
184     // Reserve all registers in FGR64.
185     for (RegIter Reg = Mips::FGR64RegClass.begin(),
186          EReg = Mips::FGR64RegClass.end(); Reg != EReg; ++Reg)
187       Reserved.set(*Reg);
188   }
189   // Reserve FP if this function should have a dedicated frame pointer register.
190   if (Subtarget.getFrameLowering()->hasFP(MF)) {
191     if (Subtarget.inMips16Mode())
192       Reserved.set(Mips::S0);
193     else {
194       Reserved.set(Mips::FP);
195       Reserved.set(Mips::FP_64);
196 
197       // Reserve the base register if we need to both realign the stack and
198       // allocate variable-sized objects at runtime. This should test the
199       // same conditions as MipsFrameLowering::hasBP().
200       if (needsStackRealignment(MF) &&
201           MF.getFrameInfo()->hasVarSizedObjects()) {
202         Reserved.set(Mips::S7);
203         Reserved.set(Mips::S7_64);
204       }
205     }
206   }
207 
208   // Reserve hardware registers.
209   Reserved.set(Mips::HWR29);
210 
211   // Reserve DSP control register.
212   Reserved.set(Mips::DSPPos);
213   Reserved.set(Mips::DSPSCount);
214   Reserved.set(Mips::DSPCarry);
215   Reserved.set(Mips::DSPEFI);
216   Reserved.set(Mips::DSPOutFlag);
217 
218   // Reserve MSA control registers.
219   Reserved.set(Mips::MSAIR);
220   Reserved.set(Mips::MSACSR);
221   Reserved.set(Mips::MSAAccess);
222   Reserved.set(Mips::MSASave);
223   Reserved.set(Mips::MSAModify);
224   Reserved.set(Mips::MSARequest);
225   Reserved.set(Mips::MSAMap);
226   Reserved.set(Mips::MSAUnmap);
227 
228   // Reserve RA if in mips16 mode.
229   if (Subtarget.inMips16Mode()) {
230     const MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
231     Reserved.set(Mips::RA);
232     Reserved.set(Mips::RA_64);
233     Reserved.set(Mips::T0);
234     Reserved.set(Mips::T1);
235     if (MF.getFunction()->hasFnAttribute("saveS2") || MipsFI->hasSaveS2())
236       Reserved.set(Mips::S2);
237   }
238 
239   // Reserve GP if small section is used.
240   if (Subtarget.useSmallSection()) {
241     Reserved.set(Mips::GP);
242     Reserved.set(Mips::GP_64);
243   }
244 
245   if (Subtarget.isABI_O32() && !Subtarget.useOddSPReg()) {
246     for (const auto &Reg : Mips::OddSPRegClass)
247       Reserved.set(Reg);
248   }
249 
250   return Reserved;
251 }
252 
253 bool
254 MipsRegisterInfo::requiresRegisterScavenging(const MachineFunction &MF) const {
255   return true;
256 }
257 
258 bool
259 MipsRegisterInfo::trackLivenessAfterRegAlloc(const MachineFunction &MF) const {
260   return true;
261 }
262 
263 // FrameIndex represent objects inside a abstract stack.
264 // We must replace FrameIndex with an stack/frame pointer
265 // direct reference.
266 void MipsRegisterInfo::
267 eliminateFrameIndex(MachineBasicBlock::iterator II, int SPAdj,
268                     unsigned FIOperandNum, RegScavenger *RS) const {
269   MachineInstr &MI = *II;
270   MachineFunction &MF = *MI.getParent()->getParent();
271 
272   DEBUG(errs() << "\nFunction : " << MF.getName() << "\n";
273         errs() << "<--------->\n" << MI);
274 
275   int FrameIndex = MI.getOperand(FIOperandNum).getIndex();
276   uint64_t stackSize = MF.getFrameInfo()->getStackSize();
277   int64_t spOffset = MF.getFrameInfo()->getObjectOffset(FrameIndex);
278 
279   DEBUG(errs() << "FrameIndex : " << FrameIndex << "\n"
280                << "spOffset   : " << spOffset << "\n"
281                << "stackSize  : " << stackSize << "\n");
282 
283   eliminateFI(MI, FIOperandNum, FrameIndex, stackSize, spOffset);
284 }
285 
286 unsigned MipsRegisterInfo::
287 getFrameRegister(const MachineFunction &MF) const {
288   const MipsSubtarget &Subtarget = MF.getSubtarget<MipsSubtarget>();
289   const TargetFrameLowering *TFI = Subtarget.getFrameLowering();
290   bool IsN64 =
291       static_cast<const MipsTargetMachine &>(MF.getTarget()).getABI().IsN64();
292 
293   if (Subtarget.inMips16Mode())
294     return TFI->hasFP(MF) ? Mips::S0 : Mips::SP;
295   else
296     return TFI->hasFP(MF) ? (IsN64 ? Mips::FP_64 : Mips::FP) :
297                             (IsN64 ? Mips::SP_64 : Mips::SP);
298 }
299 
300 bool MipsRegisterInfo::canRealignStack(const MachineFunction &MF) const {
301   // Avoid realigning functions that explicitly do not want to be realigned.
302   // Normally, we should report an error when a function should be dynamically
303   // realigned but also has the attribute no-realign-stack. Unfortunately,
304   // with this attribute, MachineFrameInfo clamps each new object's alignment
305   // to that of the stack's alignment as specified by the ABI. As a result,
306   // the information of whether we have objects with larger alignment
307   // requirement than the stack's alignment is already lost at this point.
308   if (!TargetRegisterInfo::canRealignStack(MF))
309     return false;
310 
311   const MipsSubtarget &Subtarget = MF.getSubtarget<MipsSubtarget>();
312   unsigned FP = Subtarget.isGP32bit() ? Mips::FP : Mips::FP_64;
313   unsigned BP = Subtarget.isGP32bit() ? Mips::S7 : Mips::S7_64;
314 
315   // Support dynamic stack realignment only for targets with standard encoding.
316   if (!Subtarget.hasStandardEncoding())
317     return false;
318 
319   // We can't perform dynamic stack realignment if we can't reserve the
320   // frame pointer register.
321   if (!MF.getRegInfo().canReserveReg(FP))
322     return false;
323 
324   // We can realign the stack if we know the maximum call frame size and we
325   // don't have variable sized objects.
326   if (Subtarget.getFrameLowering()->hasReservedCallFrame(MF))
327     return true;
328 
329   // We have to reserve the base pointer register in the presence of variable
330   // sized objects.
331   return MF.getRegInfo().canReserveReg(BP);
332 }
333