1 //===-- MipsRegisterInfo.cpp - MIPS Register Information -== --------------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file contains the MIPS implementation of the TargetRegisterInfo class.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #include "MipsRegisterInfo.h"
15 #include "Mips.h"
16 #include "MipsInstrInfo.h"
17 #include "MipsMachineFunction.h"
18 #include "MipsSubtarget.h"
19 #include "MipsTargetMachine.h"
20 #include "llvm/ADT/BitVector.h"
21 #include "llvm/ADT/STLExtras.h"
22 #include "llvm/CodeGen/MachineFrameInfo.h"
23 #include "llvm/CodeGen/MachineRegisterInfo.h"
24 #include "llvm/CodeGen/MachineFunction.h"
25 #include "llvm/CodeGen/MachineInstrBuilder.h"
26 #include "llvm/IR/Constants.h"
27 #include "llvm/IR/DebugInfo.h"
28 #include "llvm/IR/Function.h"
29 #include "llvm/IR/Type.h"
30 #include "llvm/Support/CommandLine.h"
31 #include "llvm/Support/Debug.h"
32 #include "llvm/Support/ErrorHandling.h"
33 #include "llvm/Support/raw_ostream.h"
34 #include "llvm/Target/TargetFrameLowering.h"
35 #include "llvm/Target/TargetInstrInfo.h"
36 #include "llvm/Target/TargetMachine.h"
37 #include "llvm/Target/TargetOptions.h"
38 
39 using namespace llvm;
40 
41 #define DEBUG_TYPE "mips-reg-info"
42 
43 #define GET_REGINFO_TARGET_DESC
44 #include "MipsGenRegisterInfo.inc"
45 
46 MipsRegisterInfo::MipsRegisterInfo() : MipsGenRegisterInfo(Mips::RA) {}
47 
48 unsigned MipsRegisterInfo::getPICCallReg() { return Mips::T9; }
49 
50 const TargetRegisterClass *
51 MipsRegisterInfo::getPointerRegClass(const MachineFunction &MF,
52                                      unsigned Kind) const {
53   MipsABIInfo ABI = MF.getSubtarget<MipsSubtarget>().getABI();
54   return ABI.ArePtrs64bit() ? &Mips::GPR64RegClass : &Mips::GPR32RegClass;
55 }
56 
57 unsigned
58 MipsRegisterInfo::getRegPressureLimit(const TargetRegisterClass *RC,
59                                       MachineFunction &MF) const {
60   switch (RC->getID()) {
61   default:
62     return 0;
63   case Mips::GPR32RegClassID:
64   case Mips::GPR64RegClassID:
65   case Mips::DSPRRegClassID: {
66     const TargetFrameLowering *TFI = MF.getSubtarget().getFrameLowering();
67     return 28 - TFI->hasFP(MF);
68   }
69   case Mips::FGR32RegClassID:
70     return 32;
71   case Mips::AFGR64RegClassID:
72     return 16;
73   case Mips::FGR64RegClassID:
74     return 32;
75   }
76 }
77 
78 //===----------------------------------------------------------------------===//
79 // Callee Saved Registers methods
80 //===----------------------------------------------------------------------===//
81 
82 /// Mips Callee Saved Registers
83 const MCPhysReg *
84 MipsRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
85   const MipsSubtarget &Subtarget = MF->getSubtarget<MipsSubtarget>();
86   const Function *F = MF->getFunction();
87   if (F->hasFnAttribute("interrupt")) {
88     if (Subtarget.hasMips64())
89       return Subtarget.hasMips64r6() ? CSR_Interrupt_64R6_SaveList
90                                      : CSR_Interrupt_64_SaveList;
91     else
92       return Subtarget.hasMips32r6() ? CSR_Interrupt_32R6_SaveList
93                                      : CSR_Interrupt_32_SaveList;
94   }
95 
96   if (Subtarget.isSingleFloat())
97     return CSR_SingleFloatOnly_SaveList;
98 
99   if (Subtarget.isABI_N64())
100     return CSR_N64_SaveList;
101 
102   if (Subtarget.isABI_N32())
103     return CSR_N32_SaveList;
104 
105   if (Subtarget.isFP64bit())
106     return CSR_O32_FP64_SaveList;
107 
108   if (Subtarget.isFPXX())
109     return CSR_O32_FPXX_SaveList;
110 
111   return CSR_O32_SaveList;
112 }
113 
114 const uint32_t *
115 MipsRegisterInfo::getCallPreservedMask(const MachineFunction &MF,
116                                        CallingConv::ID) const {
117   const MipsSubtarget &Subtarget = MF.getSubtarget<MipsSubtarget>();
118   if (Subtarget.isSingleFloat())
119     return CSR_SingleFloatOnly_RegMask;
120 
121   if (Subtarget.isABI_N64())
122     return CSR_N64_RegMask;
123 
124   if (Subtarget.isABI_N32())
125     return CSR_N32_RegMask;
126 
127   if (Subtarget.isFP64bit())
128     return CSR_O32_FP64_RegMask;
129 
130   if (Subtarget.isFPXX())
131     return CSR_O32_FPXX_RegMask;
132 
133   return CSR_O32_RegMask;
134 }
135 
136 const uint32_t *MipsRegisterInfo::getMips16RetHelperMask() {
137   return CSR_Mips16RetHelper_RegMask;
138 }
139 
140 BitVector MipsRegisterInfo::
141 getReservedRegs(const MachineFunction &MF) const {
142   static const MCPhysReg ReservedGPR32[] = {
143     Mips::ZERO, Mips::K0, Mips::K1, Mips::SP
144   };
145 
146   static const MCPhysReg ReservedGPR64[] = {
147     Mips::ZERO_64, Mips::K0_64, Mips::K1_64, Mips::SP_64
148   };
149 
150   BitVector Reserved(getNumRegs());
151   const MipsSubtarget &Subtarget = MF.getSubtarget<MipsSubtarget>();
152   typedef TargetRegisterClass::const_iterator RegIter;
153 
154   for (unsigned I = 0; I < array_lengthof(ReservedGPR32); ++I)
155     Reserved.set(ReservedGPR32[I]);
156 
157   // Reserve registers for the NaCl sandbox.
158   if (Subtarget.isTargetNaCl()) {
159     Reserved.set(Mips::T6);   // Reserved for control flow mask.
160     Reserved.set(Mips::T7);   // Reserved for memory access mask.
161     Reserved.set(Mips::T8);   // Reserved for thread pointer.
162   }
163 
164   for (unsigned I = 0; I < array_lengthof(ReservedGPR64); ++I)
165     Reserved.set(ReservedGPR64[I]);
166 
167   // For mno-abicalls, GP is a program invariant!
168   if (!Subtarget.isABICalls()) {
169     Reserved.set(Mips::GP);
170     Reserved.set(Mips::GP_64);
171   }
172 
173   if (Subtarget.isFP64bit()) {
174     // Reserve all registers in AFGR64.
175     for (RegIter Reg = Mips::AFGR64RegClass.begin(),
176          EReg = Mips::AFGR64RegClass.end(); Reg != EReg; ++Reg)
177       Reserved.set(*Reg);
178   } else {
179     // Reserve all registers in FGR64.
180     for (RegIter Reg = Mips::FGR64RegClass.begin(),
181          EReg = Mips::FGR64RegClass.end(); Reg != EReg; ++Reg)
182       Reserved.set(*Reg);
183   }
184   // Reserve FP if this function should have a dedicated frame pointer register.
185   if (Subtarget.getFrameLowering()->hasFP(MF)) {
186     if (Subtarget.inMips16Mode())
187       Reserved.set(Mips::S0);
188     else {
189       Reserved.set(Mips::FP);
190       Reserved.set(Mips::FP_64);
191 
192       // Reserve the base register if we need to both realign the stack and
193       // allocate variable-sized objects at runtime. This should test the
194       // same conditions as MipsFrameLowering::hasBP().
195       if (needsStackRealignment(MF) &&
196           MF.getFrameInfo()->hasVarSizedObjects()) {
197         Reserved.set(Mips::S7);
198         Reserved.set(Mips::S7_64);
199       }
200     }
201   }
202 
203   // Reserve hardware registers.
204   Reserved.set(Mips::HWR29);
205 
206   // Reserve DSP control register.
207   Reserved.set(Mips::DSPPos);
208   Reserved.set(Mips::DSPSCount);
209   Reserved.set(Mips::DSPCarry);
210   Reserved.set(Mips::DSPEFI);
211   Reserved.set(Mips::DSPOutFlag);
212 
213   // Reserve MSA control registers.
214   Reserved.set(Mips::MSAIR);
215   Reserved.set(Mips::MSACSR);
216   Reserved.set(Mips::MSAAccess);
217   Reserved.set(Mips::MSASave);
218   Reserved.set(Mips::MSAModify);
219   Reserved.set(Mips::MSARequest);
220   Reserved.set(Mips::MSAMap);
221   Reserved.set(Mips::MSAUnmap);
222 
223   // Reserve RA if in mips16 mode.
224   if (Subtarget.inMips16Mode()) {
225     const MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
226     Reserved.set(Mips::RA);
227     Reserved.set(Mips::RA_64);
228     Reserved.set(Mips::T0);
229     Reserved.set(Mips::T1);
230     if (MF.getFunction()->hasFnAttribute("saveS2") || MipsFI->hasSaveS2())
231       Reserved.set(Mips::S2);
232   }
233 
234   // Reserve GP if small section is used.
235   if (Subtarget.useSmallSection()) {
236     Reserved.set(Mips::GP);
237     Reserved.set(Mips::GP_64);
238   }
239 
240   if (Subtarget.isABI_O32() && !Subtarget.useOddSPReg()) {
241     for (const auto &Reg : Mips::OddSPRegClass)
242       Reserved.set(Reg);
243   }
244 
245   return Reserved;
246 }
247 
248 bool
249 MipsRegisterInfo::requiresRegisterScavenging(const MachineFunction &MF) const {
250   return true;
251 }
252 
253 bool
254 MipsRegisterInfo::trackLivenessAfterRegAlloc(const MachineFunction &MF) const {
255   return true;
256 }
257 
258 // FrameIndex represent objects inside a abstract stack.
259 // We must replace FrameIndex with an stack/frame pointer
260 // direct reference.
261 void MipsRegisterInfo::
262 eliminateFrameIndex(MachineBasicBlock::iterator II, int SPAdj,
263                     unsigned FIOperandNum, RegScavenger *RS) const {
264   MachineInstr &MI = *II;
265   MachineFunction &MF = *MI.getParent()->getParent();
266 
267   DEBUG(errs() << "\nFunction : " << MF.getName() << "\n";
268         errs() << "<--------->\n" << MI);
269 
270   int FrameIndex = MI.getOperand(FIOperandNum).getIndex();
271   uint64_t stackSize = MF.getFrameInfo()->getStackSize();
272   int64_t spOffset = MF.getFrameInfo()->getObjectOffset(FrameIndex);
273 
274   DEBUG(errs() << "FrameIndex : " << FrameIndex << "\n"
275                << "spOffset   : " << spOffset << "\n"
276                << "stackSize  : " << stackSize << "\n");
277 
278   eliminateFI(MI, FIOperandNum, FrameIndex, stackSize, spOffset);
279 }
280 
281 unsigned MipsRegisterInfo::
282 getFrameRegister(const MachineFunction &MF) const {
283   const MipsSubtarget &Subtarget = MF.getSubtarget<MipsSubtarget>();
284   const TargetFrameLowering *TFI = Subtarget.getFrameLowering();
285   bool IsN64 =
286       static_cast<const MipsTargetMachine &>(MF.getTarget()).getABI().IsN64();
287 
288   if (Subtarget.inMips16Mode())
289     return TFI->hasFP(MF) ? Mips::S0 : Mips::SP;
290   else
291     return TFI->hasFP(MF) ? (IsN64 ? Mips::FP_64 : Mips::FP) :
292                             (IsN64 ? Mips::SP_64 : Mips::SP);
293 }
294 
295 bool MipsRegisterInfo::canRealignStack(const MachineFunction &MF) const {
296   // Avoid realigning functions that explicitly do not want to be realigned.
297   // Normally, we should report an error when a function should be dynamically
298   // realigned but also has the attribute no-realign-stack. Unfortunately,
299   // with this attribute, MachineFrameInfo clamps each new object's alignment
300   // to that of the stack's alignment as specified by the ABI. As a result,
301   // the information of whether we have objects with larger alignment
302   // requirement than the stack's alignment is already lost at this point.
303   if (!TargetRegisterInfo::canRealignStack(MF))
304     return false;
305 
306   const MipsSubtarget &Subtarget = MF.getSubtarget<MipsSubtarget>();
307   unsigned FP = Subtarget.isGP32bit() ? Mips::FP : Mips::FP_64;
308   unsigned BP = Subtarget.isGP32bit() ? Mips::S7 : Mips::S7_64;
309 
310   // Support dynamic stack realignment only for targets with standard encoding.
311   if (!Subtarget.hasStandardEncoding())
312     return false;
313 
314   // We can't perform dynamic stack realignment if we can't reserve the
315   // frame pointer register.
316   if (!MF.getRegInfo().canReserveReg(FP))
317     return false;
318 
319   // We can realign the stack if we know the maximum call frame size and we
320   // don't have variable sized objects.
321   if (Subtarget.getFrameLowering()->hasReservedCallFrame(MF))
322     return true;
323 
324   // We have to reserve the base pointer register in the presence of variable
325   // sized objects.
326   return MF.getRegInfo().canReserveReg(BP);
327 }
328