1 //===-- MipsRegisterInfo.cpp - MIPS Register Information -== --------------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file contains the MIPS implementation of the TargetRegisterInfo class.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #include "MipsRegisterInfo.h"
15 #include "Mips.h"
16 #include "MipsAnalyzeImmediate.h"
17 #include "MipsInstrInfo.h"
18 #include "MipsMachineFunction.h"
19 #include "MipsSubtarget.h"
20 #include "MipsTargetMachine.h"
21 #include "llvm/ADT/BitVector.h"
22 #include "llvm/ADT/STLExtras.h"
23 #include "llvm/CodeGen/MachineFrameInfo.h"
24 #include "llvm/CodeGen/MachineRegisterInfo.h"
25 #include "llvm/CodeGen/MachineFunction.h"
26 #include "llvm/CodeGen/MachineInstrBuilder.h"
27 #include "llvm/IR/Constants.h"
28 #include "llvm/IR/DebugInfo.h"
29 #include "llvm/IR/Function.h"
30 #include "llvm/IR/Type.h"
31 #include "llvm/Support/CommandLine.h"
32 #include "llvm/Support/Debug.h"
33 #include "llvm/Support/ErrorHandling.h"
34 #include "llvm/Support/raw_ostream.h"
35 #include "llvm/Target/TargetFrameLowering.h"
36 #include "llvm/Target/TargetInstrInfo.h"
37 #include "llvm/Target/TargetMachine.h"
38 #include "llvm/Target/TargetOptions.h"
39 
40 using namespace llvm;
41 
42 #define DEBUG_TYPE "mips-reg-info"
43 
44 #define GET_REGINFO_TARGET_DESC
45 #include "MipsGenRegisterInfo.inc"
46 
47 MipsRegisterInfo::MipsRegisterInfo() : MipsGenRegisterInfo(Mips::RA) {}
48 
49 unsigned MipsRegisterInfo::getPICCallReg() { return Mips::T9; }
50 
51 const TargetRegisterClass *
52 MipsRegisterInfo::getPointerRegClass(const MachineFunction &MF,
53                                      unsigned Kind) const {
54   MipsABIInfo ABI = MF.getSubtarget<MipsSubtarget>().getABI();
55   return ABI.ArePtrs64bit() ? &Mips::GPR64RegClass : &Mips::GPR32RegClass;
56 }
57 
58 unsigned
59 MipsRegisterInfo::getRegPressureLimit(const TargetRegisterClass *RC,
60                                       MachineFunction &MF) const {
61   switch (RC->getID()) {
62   default:
63     return 0;
64   case Mips::GPR32RegClassID:
65   case Mips::GPR64RegClassID:
66   case Mips::DSPRRegClassID: {
67     const TargetFrameLowering *TFI = MF.getSubtarget().getFrameLowering();
68     return 28 - TFI->hasFP(MF);
69   }
70   case Mips::FGR32RegClassID:
71     return 32;
72   case Mips::AFGR64RegClassID:
73     return 16;
74   case Mips::FGR64RegClassID:
75     return 32;
76   }
77 }
78 
79 //===----------------------------------------------------------------------===//
80 // Callee Saved Registers methods
81 //===----------------------------------------------------------------------===//
82 
83 /// Mips Callee Saved Registers
84 const MCPhysReg *
85 MipsRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
86   const MipsSubtarget &Subtarget = MF->getSubtarget<MipsSubtarget>();
87   if (Subtarget.isSingleFloat())
88     return CSR_SingleFloatOnly_SaveList;
89 
90   if (Subtarget.isABI_N64())
91     return CSR_N64_SaveList;
92 
93   if (Subtarget.isABI_N32())
94     return CSR_N32_SaveList;
95 
96   if (Subtarget.isFP64bit())
97     return CSR_O32_FP64_SaveList;
98 
99   if (Subtarget.isFPXX())
100     return CSR_O32_FPXX_SaveList;
101 
102   return CSR_O32_SaveList;
103 }
104 
105 const uint32_t *
106 MipsRegisterInfo::getCallPreservedMask(const MachineFunction &MF,
107                                        CallingConv::ID) const {
108   const MipsSubtarget &Subtarget = MF.getSubtarget<MipsSubtarget>();
109   if (Subtarget.isSingleFloat())
110     return CSR_SingleFloatOnly_RegMask;
111 
112   if (Subtarget.isABI_N64())
113     return CSR_N64_RegMask;
114 
115   if (Subtarget.isABI_N32())
116     return CSR_N32_RegMask;
117 
118   if (Subtarget.isFP64bit())
119     return CSR_O32_FP64_RegMask;
120 
121   if (Subtarget.isFPXX())
122     return CSR_O32_FPXX_RegMask;
123 
124   return CSR_O32_RegMask;
125 }
126 
127 const uint32_t *MipsRegisterInfo::getMips16RetHelperMask() {
128   return CSR_Mips16RetHelper_RegMask;
129 }
130 
131 BitVector MipsRegisterInfo::
132 getReservedRegs(const MachineFunction &MF) const {
133   static const MCPhysReg ReservedGPR32[] = {
134     Mips::ZERO, Mips::K0, Mips::K1, Mips::SP
135   };
136 
137   static const MCPhysReg ReservedGPR64[] = {
138     Mips::ZERO_64, Mips::K0_64, Mips::K1_64, Mips::SP_64
139   };
140 
141   BitVector Reserved(getNumRegs());
142   const MipsSubtarget &Subtarget = MF.getSubtarget<MipsSubtarget>();
143   typedef TargetRegisterClass::const_iterator RegIter;
144 
145   for (unsigned I = 0; I < array_lengthof(ReservedGPR32); ++I)
146     Reserved.set(ReservedGPR32[I]);
147 
148   // Reserve registers for the NaCl sandbox.
149   if (Subtarget.isTargetNaCl()) {
150     Reserved.set(Mips::T6);   // Reserved for control flow mask.
151     Reserved.set(Mips::T7);   // Reserved for memory access mask.
152     Reserved.set(Mips::T8);   // Reserved for thread pointer.
153   }
154 
155   for (unsigned I = 0; I < array_lengthof(ReservedGPR64); ++I)
156     Reserved.set(ReservedGPR64[I]);
157 
158   // For mno-abicalls, GP is a program invariant!
159   if (!Subtarget.isABICalls()) {
160     Reserved.set(Mips::GP);
161     Reserved.set(Mips::GP_64);
162   }
163 
164   if (Subtarget.isFP64bit()) {
165     // Reserve all registers in AFGR64.
166     for (RegIter Reg = Mips::AFGR64RegClass.begin(),
167          EReg = Mips::AFGR64RegClass.end(); Reg != EReg; ++Reg)
168       Reserved.set(*Reg);
169   } else {
170     // Reserve all registers in FGR64.
171     for (RegIter Reg = Mips::FGR64RegClass.begin(),
172          EReg = Mips::FGR64RegClass.end(); Reg != EReg; ++Reg)
173       Reserved.set(*Reg);
174   }
175   // Reserve FP if this function should have a dedicated frame pointer register.
176   if (Subtarget.getFrameLowering()->hasFP(MF)) {
177     if (Subtarget.inMips16Mode())
178       Reserved.set(Mips::S0);
179     else {
180       Reserved.set(Mips::FP);
181       Reserved.set(Mips::FP_64);
182 
183       // Reserve the base register if we need to both realign the stack and
184       // allocate variable-sized objects at runtime. This should test the
185       // same conditions as MipsFrameLowering::hasBP().
186       if (needsStackRealignment(MF) &&
187           MF.getFrameInfo()->hasVarSizedObjects()) {
188         Reserved.set(Mips::S7);
189         Reserved.set(Mips::S7_64);
190       }
191     }
192   }
193 
194   // Reserve hardware registers.
195   Reserved.set(Mips::HWR29);
196 
197   // Reserve DSP control register.
198   Reserved.set(Mips::DSPPos);
199   Reserved.set(Mips::DSPSCount);
200   Reserved.set(Mips::DSPCarry);
201   Reserved.set(Mips::DSPEFI);
202   Reserved.set(Mips::DSPOutFlag);
203 
204   // Reserve MSA control registers.
205   Reserved.set(Mips::MSAIR);
206   Reserved.set(Mips::MSACSR);
207   Reserved.set(Mips::MSAAccess);
208   Reserved.set(Mips::MSASave);
209   Reserved.set(Mips::MSAModify);
210   Reserved.set(Mips::MSARequest);
211   Reserved.set(Mips::MSAMap);
212   Reserved.set(Mips::MSAUnmap);
213 
214   // Reserve RA if in mips16 mode.
215   if (Subtarget.inMips16Mode()) {
216     const MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
217     Reserved.set(Mips::RA);
218     Reserved.set(Mips::RA_64);
219     Reserved.set(Mips::T0);
220     Reserved.set(Mips::T1);
221     if (MF.getFunction()->hasFnAttribute("saveS2") || MipsFI->hasSaveS2())
222       Reserved.set(Mips::S2);
223   }
224 
225   // Reserve GP if small section is used.
226   if (Subtarget.useSmallSection()) {
227     Reserved.set(Mips::GP);
228     Reserved.set(Mips::GP_64);
229   }
230 
231   if (Subtarget.isABI_O32() && !Subtarget.useOddSPReg()) {
232     for (const auto &Reg : Mips::OddSPRegClass)
233       Reserved.set(Reg);
234   }
235 
236   return Reserved;
237 }
238 
239 bool
240 MipsRegisterInfo::requiresRegisterScavenging(const MachineFunction &MF) const {
241   return true;
242 }
243 
244 bool
245 MipsRegisterInfo::trackLivenessAfterRegAlloc(const MachineFunction &MF) const {
246   return true;
247 }
248 
249 // FrameIndex represent objects inside a abstract stack.
250 // We must replace FrameIndex with an stack/frame pointer
251 // direct reference.
252 void MipsRegisterInfo::
253 eliminateFrameIndex(MachineBasicBlock::iterator II, int SPAdj,
254                     unsigned FIOperandNum, RegScavenger *RS) const {
255   MachineInstr &MI = *II;
256   MachineFunction &MF = *MI.getParent()->getParent();
257 
258   DEBUG(errs() << "\nFunction : " << MF.getName() << "\n";
259         errs() << "<--------->\n" << MI);
260 
261   int FrameIndex = MI.getOperand(FIOperandNum).getIndex();
262   uint64_t stackSize = MF.getFrameInfo()->getStackSize();
263   int64_t spOffset = MF.getFrameInfo()->getObjectOffset(FrameIndex);
264 
265   DEBUG(errs() << "FrameIndex : " << FrameIndex << "\n"
266                << "spOffset   : " << spOffset << "\n"
267                << "stackSize  : " << stackSize << "\n");
268 
269   eliminateFI(MI, FIOperandNum, FrameIndex, stackSize, spOffset);
270 }
271 
272 unsigned MipsRegisterInfo::
273 getFrameRegister(const MachineFunction &MF) const {
274   const MipsSubtarget &Subtarget = MF.getSubtarget<MipsSubtarget>();
275   const TargetFrameLowering *TFI = Subtarget.getFrameLowering();
276   bool IsN64 =
277       static_cast<const MipsTargetMachine &>(MF.getTarget()).getABI().IsN64();
278 
279   if (Subtarget.inMips16Mode())
280     return TFI->hasFP(MF) ? Mips::S0 : Mips::SP;
281   else
282     return TFI->hasFP(MF) ? (IsN64 ? Mips::FP_64 : Mips::FP) :
283                             (IsN64 ? Mips::SP_64 : Mips::SP);
284 }
285 
286 bool MipsRegisterInfo::canRealignStack(const MachineFunction &MF) const {
287   // Avoid realigning functions that explicitly do not want to be realigned.
288   // Normally, we should report an error when a function should be dynamically
289   // realigned but also has the attribute no-realign-stack. Unfortunately,
290   // with this attribute, MachineFrameInfo clamps each new object's alignment
291   // to that of the stack's alignment as specified by the ABI. As a result,
292   // the information of whether we have objects with larger alignment
293   // requirement than the stack's alignment is already lost at this point.
294   if (!TargetRegisterInfo::canRealignStack(MF))
295     return false;
296 
297   const MipsSubtarget &Subtarget = MF.getSubtarget<MipsSubtarget>();
298   unsigned FP = Subtarget.isGP32bit() ? Mips::FP : Mips::FP_64;
299   unsigned BP = Subtarget.isGP32bit() ? Mips::S7 : Mips::S7_64;
300 
301   // Support dynamic stack realignment only for targets with standard encoding.
302   if (!Subtarget.hasStandardEncoding())
303     return false;
304 
305   // We can't perform dynamic stack realignment if we can't reserve the
306   // frame pointer register.
307   if (!MF.getRegInfo().canReserveReg(FP))
308     return false;
309 
310   // We can realign the stack if we know the maximum call frame size and we
311   // don't have variable sized objects.
312   if (Subtarget.getFrameLowering()->hasReservedCallFrame(MF))
313     return true;
314 
315   // We have to reserve the base pointer register in the presence of variable
316   // sized objects.
317   return MF.getRegInfo().canReserveReg(BP);
318 }
319