1 //===- MipsRegisterInfo.cpp - MIPS Register Information -------------------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file contains the MIPS implementation of the TargetRegisterInfo class.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #include "MipsRegisterInfo.h"
15 #include "MCTargetDesc/MipsABIInfo.h"
16 #include "Mips.h"
17 #include "MipsMachineFunction.h"
18 #include "MipsSubtarget.h"
19 #include "MipsTargetMachine.h"
20 #include "llvm/ADT/BitVector.h"
21 #include "llvm/ADT/STLExtras.h"
22 #include "llvm/CodeGen/MachineFrameInfo.h"
23 #include "llvm/CodeGen/MachineFunction.h"
24 #include "llvm/CodeGen/MachineInstr.h"
25 #include "llvm/CodeGen/MachineRegisterInfo.h"
26 #include "llvm/CodeGen/TargetFrameLowering.h"
27 #include "llvm/CodeGen/TargetRegisterInfo.h"
28 #include "llvm/CodeGen/TargetSubtargetInfo.h"
29 #include "llvm/IR/Function.h"
30 #include "llvm/MC/MCRegisterInfo.h"
31 #include "llvm/Support/Debug.h"
32 #include "llvm/Support/ErrorHandling.h"
33 #include "llvm/Support/raw_ostream.h"
34 #include <cstdint>
35 
36 using namespace llvm;
37 
38 #define DEBUG_TYPE "mips-reg-info"
39 
40 #define GET_REGINFO_TARGET_DESC
41 #include "MipsGenRegisterInfo.inc"
42 
43 MipsRegisterInfo::MipsRegisterInfo() : MipsGenRegisterInfo(Mips::RA) {}
44 
45 unsigned MipsRegisterInfo::getPICCallReg() { return Mips::T9; }
46 
47 const TargetRegisterClass *
48 MipsRegisterInfo::getPointerRegClass(const MachineFunction &MF,
49                                      unsigned Kind) const {
50   MipsABIInfo ABI = MF.getSubtarget<MipsSubtarget>().getABI();
51   MipsPtrClass PtrClassKind = static_cast<MipsPtrClass>(Kind);
52 
53   switch (PtrClassKind) {
54   case MipsPtrClass::Default:
55     return ABI.ArePtrs64bit() ? &Mips::GPR64RegClass : &Mips::GPR32RegClass;
56   case MipsPtrClass::GPR16MM:
57     return ABI.ArePtrs64bit() ? &Mips::GPRMM16_64RegClass
58                               : &Mips::GPRMM16RegClass;
59   case MipsPtrClass::StackPointer:
60     return ABI.ArePtrs64bit() ? &Mips::SP64RegClass : &Mips::SP32RegClass;
61   case MipsPtrClass::GlobalPointer:
62     return ABI.ArePtrs64bit() ? &Mips::GP64RegClass : &Mips::GP32RegClass;
63   }
64 
65   llvm_unreachable("Unknown pointer kind");
66 }
67 
68 unsigned
69 MipsRegisterInfo::getRegPressureLimit(const TargetRegisterClass *RC,
70                                       MachineFunction &MF) const {
71   switch (RC->getID()) {
72   default:
73     return 0;
74   case Mips::GPR32RegClassID:
75   case Mips::GPR64RegClassID:
76   case Mips::DSPRRegClassID: {
77     const TargetFrameLowering *TFI = MF.getSubtarget().getFrameLowering();
78     return 28 - TFI->hasFP(MF);
79   }
80   case Mips::FGR32RegClassID:
81     return 32;
82   case Mips::AFGR64RegClassID:
83     return 16;
84   case Mips::FGR64RegClassID:
85     return 32;
86   }
87 }
88 
89 //===----------------------------------------------------------------------===//
90 // Callee Saved Registers methods
91 //===----------------------------------------------------------------------===//
92 
93 /// Mips Callee Saved Registers
94 const MCPhysReg *
95 MipsRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
96   const MipsSubtarget &Subtarget = MF->getSubtarget<MipsSubtarget>();
97   const Function *F = MF->getFunction();
98   if (F->hasFnAttribute("interrupt")) {
99     if (Subtarget.hasMips64())
100       return Subtarget.hasMips64r6() ? CSR_Interrupt_64R6_SaveList
101                                      : CSR_Interrupt_64_SaveList;
102     else
103       return Subtarget.hasMips32r6() ? CSR_Interrupt_32R6_SaveList
104                                      : CSR_Interrupt_32_SaveList;
105   }
106 
107   if (Subtarget.isSingleFloat())
108     return CSR_SingleFloatOnly_SaveList;
109 
110   if (Subtarget.isABI_N64())
111     return CSR_N64_SaveList;
112 
113   if (Subtarget.isABI_N32())
114     return CSR_N32_SaveList;
115 
116   if (Subtarget.isFP64bit())
117     return CSR_O32_FP64_SaveList;
118 
119   if (Subtarget.isFPXX())
120     return CSR_O32_FPXX_SaveList;
121 
122   return CSR_O32_SaveList;
123 }
124 
125 const uint32_t *
126 MipsRegisterInfo::getCallPreservedMask(const MachineFunction &MF,
127                                        CallingConv::ID) const {
128   const MipsSubtarget &Subtarget = MF.getSubtarget<MipsSubtarget>();
129   if (Subtarget.isSingleFloat())
130     return CSR_SingleFloatOnly_RegMask;
131 
132   if (Subtarget.isABI_N64())
133     return CSR_N64_RegMask;
134 
135   if (Subtarget.isABI_N32())
136     return CSR_N32_RegMask;
137 
138   if (Subtarget.isFP64bit())
139     return CSR_O32_FP64_RegMask;
140 
141   if (Subtarget.isFPXX())
142     return CSR_O32_FPXX_RegMask;
143 
144   return CSR_O32_RegMask;
145 }
146 
147 const uint32_t *MipsRegisterInfo::getMips16RetHelperMask() {
148   return CSR_Mips16RetHelper_RegMask;
149 }
150 
151 BitVector MipsRegisterInfo::
152 getReservedRegs(const MachineFunction &MF) const {
153   static const MCPhysReg ReservedGPR32[] = {
154     Mips::ZERO, Mips::K0, Mips::K1, Mips::SP
155   };
156 
157   static const MCPhysReg ReservedGPR64[] = {
158     Mips::ZERO_64, Mips::K0_64, Mips::K1_64, Mips::SP_64
159   };
160 
161   BitVector Reserved(getNumRegs());
162   const MipsSubtarget &Subtarget = MF.getSubtarget<MipsSubtarget>();
163 
164   using RegIter = TargetRegisterClass::const_iterator;
165 
166   for (unsigned I = 0; I < array_lengthof(ReservedGPR32); ++I)
167     Reserved.set(ReservedGPR32[I]);
168 
169   // Reserve registers for the NaCl sandbox.
170   if (Subtarget.isTargetNaCl()) {
171     Reserved.set(Mips::T6);   // Reserved for control flow mask.
172     Reserved.set(Mips::T7);   // Reserved for memory access mask.
173     Reserved.set(Mips::T8);   // Reserved for thread pointer.
174   }
175 
176   for (unsigned I = 0; I < array_lengthof(ReservedGPR64); ++I)
177     Reserved.set(ReservedGPR64[I]);
178 
179   // For mno-abicalls, GP is a program invariant!
180   if (!Subtarget.isABICalls()) {
181     Reserved.set(Mips::GP);
182     Reserved.set(Mips::GP_64);
183   }
184 
185   if (Subtarget.isFP64bit()) {
186     // Reserve all registers in AFGR64.
187     for (RegIter Reg = Mips::AFGR64RegClass.begin(),
188          EReg = Mips::AFGR64RegClass.end(); Reg != EReg; ++Reg)
189       Reserved.set(*Reg);
190   } else {
191     // Reserve all registers in FGR64.
192     for (RegIter Reg = Mips::FGR64RegClass.begin(),
193          EReg = Mips::FGR64RegClass.end(); Reg != EReg; ++Reg)
194       Reserved.set(*Reg);
195   }
196   // Reserve FP if this function should have a dedicated frame pointer register.
197   if (Subtarget.getFrameLowering()->hasFP(MF)) {
198     if (Subtarget.inMips16Mode())
199       Reserved.set(Mips::S0);
200     else {
201       Reserved.set(Mips::FP);
202       Reserved.set(Mips::FP_64);
203 
204       // Reserve the base register if we need to both realign the stack and
205       // allocate variable-sized objects at runtime. This should test the
206       // same conditions as MipsFrameLowering::hasBP().
207       if (needsStackRealignment(MF) &&
208           MF.getFrameInfo().hasVarSizedObjects()) {
209         Reserved.set(Mips::S7);
210         Reserved.set(Mips::S7_64);
211       }
212     }
213   }
214 
215   // Reserve hardware registers.
216   Reserved.set(Mips::HWR29);
217 
218   // Reserve DSP control register.
219   Reserved.set(Mips::DSPPos);
220   Reserved.set(Mips::DSPSCount);
221   Reserved.set(Mips::DSPCarry);
222   Reserved.set(Mips::DSPEFI);
223   Reserved.set(Mips::DSPOutFlag);
224 
225   // Reserve MSA control registers.
226   Reserved.set(Mips::MSAIR);
227   Reserved.set(Mips::MSACSR);
228   Reserved.set(Mips::MSAAccess);
229   Reserved.set(Mips::MSASave);
230   Reserved.set(Mips::MSAModify);
231   Reserved.set(Mips::MSARequest);
232   Reserved.set(Mips::MSAMap);
233   Reserved.set(Mips::MSAUnmap);
234 
235   // Reserve RA if in mips16 mode.
236   if (Subtarget.inMips16Mode()) {
237     const MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
238     Reserved.set(Mips::RA);
239     Reserved.set(Mips::RA_64);
240     Reserved.set(Mips::T0);
241     Reserved.set(Mips::T1);
242     if (MF.getFunction()->hasFnAttribute("saveS2") || MipsFI->hasSaveS2())
243       Reserved.set(Mips::S2);
244   }
245 
246   // Reserve GP if small section is used.
247   if (Subtarget.useSmallSection()) {
248     Reserved.set(Mips::GP);
249     Reserved.set(Mips::GP_64);
250   }
251 
252   if (Subtarget.isABI_O32() && !Subtarget.useOddSPReg()) {
253     for (const auto &Reg : Mips::OddSPRegClass)
254       Reserved.set(Reg);
255   }
256 
257   return Reserved;
258 }
259 
260 bool
261 MipsRegisterInfo::requiresRegisterScavenging(const MachineFunction &MF) const {
262   return true;
263 }
264 
265 bool
266 MipsRegisterInfo::trackLivenessAfterRegAlloc(const MachineFunction &MF) const {
267   return true;
268 }
269 
270 // FrameIndex represent objects inside a abstract stack.
271 // We must replace FrameIndex with an stack/frame pointer
272 // direct reference.
273 void MipsRegisterInfo::
274 eliminateFrameIndex(MachineBasicBlock::iterator II, int SPAdj,
275                     unsigned FIOperandNum, RegScavenger *RS) const {
276   MachineInstr &MI = *II;
277   MachineFunction &MF = *MI.getParent()->getParent();
278 
279   DEBUG(errs() << "\nFunction : " << MF.getName() << "\n";
280         errs() << "<--------->\n" << MI);
281 
282   int FrameIndex = MI.getOperand(FIOperandNum).getIndex();
283   uint64_t stackSize = MF.getFrameInfo().getStackSize();
284   int64_t spOffset = MF.getFrameInfo().getObjectOffset(FrameIndex);
285 
286   DEBUG(errs() << "FrameIndex : " << FrameIndex << "\n"
287                << "spOffset   : " << spOffset << "\n"
288                << "stackSize  : " << stackSize << "\n"
289                << "alignment  : "
290                << MF.getFrameInfo().getObjectAlignment(FrameIndex) << "\n");
291 
292   eliminateFI(MI, FIOperandNum, FrameIndex, stackSize, spOffset);
293 }
294 
295 unsigned MipsRegisterInfo::
296 getFrameRegister(const MachineFunction &MF) const {
297   const MipsSubtarget &Subtarget = MF.getSubtarget<MipsSubtarget>();
298   const TargetFrameLowering *TFI = Subtarget.getFrameLowering();
299   bool IsN64 =
300       static_cast<const MipsTargetMachine &>(MF.getTarget()).getABI().IsN64();
301 
302   if (Subtarget.inMips16Mode())
303     return TFI->hasFP(MF) ? Mips::S0 : Mips::SP;
304   else
305     return TFI->hasFP(MF) ? (IsN64 ? Mips::FP_64 : Mips::FP) :
306                             (IsN64 ? Mips::SP_64 : Mips::SP);
307 }
308 
309 bool MipsRegisterInfo::canRealignStack(const MachineFunction &MF) const {
310   // Avoid realigning functions that explicitly do not want to be realigned.
311   // Normally, we should report an error when a function should be dynamically
312   // realigned but also has the attribute no-realign-stack. Unfortunately,
313   // with this attribute, MachineFrameInfo clamps each new object's alignment
314   // to that of the stack's alignment as specified by the ABI. As a result,
315   // the information of whether we have objects with larger alignment
316   // requirement than the stack's alignment is already lost at this point.
317   if (!TargetRegisterInfo::canRealignStack(MF))
318     return false;
319 
320   const MipsSubtarget &Subtarget = MF.getSubtarget<MipsSubtarget>();
321   unsigned FP = Subtarget.isGP32bit() ? Mips::FP : Mips::FP_64;
322   unsigned BP = Subtarget.isGP32bit() ? Mips::S7 : Mips::S7_64;
323 
324   // Support dynamic stack realignment only for targets with standard encoding.
325   if (!Subtarget.hasStandardEncoding())
326     return false;
327 
328   // We can't perform dynamic stack realignment if we can't reserve the
329   // frame pointer register.
330   if (!MF.getRegInfo().canReserveReg(FP))
331     return false;
332 
333   // We can realign the stack if we know the maximum call frame size and we
334   // don't have variable sized objects.
335   if (Subtarget.getFrameLowering()->hasReservedCallFrame(MF))
336     return true;
337 
338   // We have to reserve the base pointer register in the presence of variable
339   // sized objects.
340   return MF.getRegInfo().canReserveReg(BP);
341 }
342