1 //===-- MipsRegisterInfo.cpp - MIPS Register Information -== --------------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file contains the MIPS implementation of the TargetRegisterInfo class.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #define DEBUG_TYPE "mips-reg-info"
15 
16 #include "MipsRegisterInfo.h"
17 #include "Mips.h"
18 #include "MipsAnalyzeImmediate.h"
19 #include "MipsInstrInfo.h"
20 #include "MipsMachineFunction.h"
21 #include "MipsSubtarget.h"
22 #include "llvm/ADT/BitVector.h"
23 #include "llvm/ADT/STLExtras.h"
24 #include "llvm/CodeGen/MachineFrameInfo.h"
25 #include "llvm/CodeGen/MachineFunction.h"
26 #include "llvm/CodeGen/MachineInstrBuilder.h"
27 #include "llvm/CodeGen/ValueTypes.h"
28 #include "llvm/DebugInfo.h"
29 #include "llvm/IR/Constants.h"
30 #include "llvm/IR/Function.h"
31 #include "llvm/IR/Type.h"
32 #include "llvm/Support/CommandLine.h"
33 #include "llvm/Support/Debug.h"
34 #include "llvm/Support/ErrorHandling.h"
35 #include "llvm/Support/raw_ostream.h"
36 #include "llvm/Target/TargetFrameLowering.h"
37 #include "llvm/Target/TargetInstrInfo.h"
38 #include "llvm/Target/TargetMachine.h"
39 #include "llvm/Target/TargetOptions.h"
40 
41 #define GET_REGINFO_TARGET_DESC
42 #include "MipsGenRegisterInfo.inc"
43 
44 using namespace llvm;
45 
46 MipsRegisterInfo::MipsRegisterInfo(const MipsSubtarget &ST)
47   : MipsGenRegisterInfo(Mips::RA), Subtarget(ST) {}
48 
49 unsigned MipsRegisterInfo::getPICCallReg() { return Mips::T9; }
50 
51 const TargetRegisterClass *
52 MipsRegisterInfo::getPointerRegClass(const MachineFunction &MF,
53                                      unsigned Kind) const {
54   return Subtarget.isABI_N64() ? &Mips::GPR64RegClass : &Mips::GPR32RegClass;
55 }
56 
57 unsigned
58 MipsRegisterInfo::getRegPressureLimit(const TargetRegisterClass *RC,
59                                       MachineFunction &MF) const {
60   switch (RC->getID()) {
61   default:
62     return 0;
63   case Mips::GPR32RegClassID:
64   case Mips::GPR64RegClassID:
65   case Mips::DSPRRegClassID: {
66     const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
67     return 28 - TFI->hasFP(MF);
68   }
69   case Mips::FGR32RegClassID:
70     return 32;
71   case Mips::AFGR64RegClassID:
72     return 16;
73   case Mips::FGR64RegClassID:
74     return 32;
75   }
76 }
77 
78 //===----------------------------------------------------------------------===//
79 // Callee Saved Registers methods
80 //===----------------------------------------------------------------------===//
81 
82 /// Mips Callee Saved Registers
83 const uint16_t* MipsRegisterInfo::
84 getCalleeSavedRegs(const MachineFunction *MF) const {
85   if (Subtarget.isSingleFloat())
86     return CSR_SingleFloatOnly_SaveList;
87 
88   if (Subtarget.isABI_N64())
89     return CSR_N64_SaveList;
90 
91   if (Subtarget.isABI_N32())
92     return CSR_N32_SaveList;
93 
94   if (Subtarget.isFP64bit())
95     return CSR_O32_FP64_SaveList;
96 
97   return CSR_O32_SaveList;
98 }
99 
100 const uint32_t*
101 MipsRegisterInfo::getCallPreservedMask(CallingConv::ID) const {
102   if (Subtarget.isSingleFloat())
103     return CSR_SingleFloatOnly_RegMask;
104 
105   if (Subtarget.isABI_N64())
106     return CSR_N64_RegMask;
107 
108   if (Subtarget.isABI_N32())
109     return CSR_N32_RegMask;
110 
111   if (Subtarget.isFP64bit())
112     return CSR_O32_FP64_RegMask;
113 
114   return CSR_O32_RegMask;
115 }
116 
117 const uint32_t *MipsRegisterInfo::getMips16RetHelperMask() {
118   return CSR_Mips16RetHelper_RegMask;
119 }
120 
121 BitVector MipsRegisterInfo::
122 getReservedRegs(const MachineFunction &MF) const {
123   static const uint16_t ReservedGPR32[] = {
124     Mips::ZERO, Mips::K0, Mips::K1, Mips::SP
125   };
126 
127   static const uint16_t ReservedGPR64[] = {
128     Mips::ZERO_64, Mips::K0_64, Mips::K1_64, Mips::SP_64
129   };
130 
131   BitVector Reserved(getNumRegs());
132   typedef TargetRegisterClass::const_iterator RegIter;
133 
134   for (unsigned I = 0; I < array_lengthof(ReservedGPR32); ++I)
135     Reserved.set(ReservedGPR32[I]);
136 
137   for (unsigned I = 0; I < array_lengthof(ReservedGPR64); ++I)
138     Reserved.set(ReservedGPR64[I]);
139 
140   if (Subtarget.isFP64bit()) {
141     // Reserve all registers in AFGR64.
142     for (RegIter Reg = Mips::AFGR64RegClass.begin(),
143          EReg = Mips::AFGR64RegClass.end(); Reg != EReg; ++Reg)
144       Reserved.set(*Reg);
145   } else {
146     // Reserve all registers in FGR64.
147     for (RegIter Reg = Mips::FGR64RegClass.begin(),
148          EReg = Mips::FGR64RegClass.end(); Reg != EReg; ++Reg)
149       Reserved.set(*Reg);
150   }
151   // Reserve FP if this function should have a dedicated frame pointer register.
152   if (MF.getTarget().getFrameLowering()->hasFP(MF)) {
153     if (Subtarget.inMips16Mode())
154       Reserved.set(Mips::S0);
155     else {
156       Reserved.set(Mips::FP);
157       Reserved.set(Mips::FP_64);
158     }
159   }
160 
161   // Reserve hardware registers.
162   Reserved.set(Mips::HWR29);
163 
164   // Reserve DSP control register.
165   Reserved.set(Mips::DSPPos);
166   Reserved.set(Mips::DSPSCount);
167   Reserved.set(Mips::DSPCarry);
168   Reserved.set(Mips::DSPEFI);
169   Reserved.set(Mips::DSPOutFlag);
170 
171   // Reserve MSA control registers.
172   Reserved.set(Mips::MSAIR);
173   Reserved.set(Mips::MSACSR);
174   Reserved.set(Mips::MSAAccess);
175   Reserved.set(Mips::MSASave);
176   Reserved.set(Mips::MSAModify);
177   Reserved.set(Mips::MSARequest);
178   Reserved.set(Mips::MSAMap);
179   Reserved.set(Mips::MSAUnmap);
180 
181   // Reserve RA if in mips16 mode.
182   if (Subtarget.inMips16Mode()) {
183     Reserved.set(Mips::RA);
184     Reserved.set(Mips::RA_64);
185     Reserved.set(Mips::T0);
186     Reserved.set(Mips::T1);
187     if (MF.getFunction()->hasFnAttribute("saveS2"))
188       Reserved.set(Mips::S2);
189   }
190 
191   // Reserve GP if small section is used.
192   if (Subtarget.useSmallSection()) {
193     Reserved.set(Mips::GP);
194     Reserved.set(Mips::GP_64);
195   }
196 
197   return Reserved;
198 }
199 
200 bool
201 MipsRegisterInfo::requiresRegisterScavenging(const MachineFunction &MF) const {
202   return true;
203 }
204 
205 bool
206 MipsRegisterInfo::trackLivenessAfterRegAlloc(const MachineFunction &MF) const {
207   return true;
208 }
209 
210 // FrameIndex represent objects inside a abstract stack.
211 // We must replace FrameIndex with an stack/frame pointer
212 // direct reference.
213 void MipsRegisterInfo::
214 eliminateFrameIndex(MachineBasicBlock::iterator II, int SPAdj,
215                     unsigned FIOperandNum, RegScavenger *RS) const {
216   MachineInstr &MI = *II;
217   MachineFunction &MF = *MI.getParent()->getParent();
218 
219   DEBUG(errs() << "\nFunction : " << MF.getName() << "\n";
220         errs() << "<--------->\n" << MI);
221 
222   int FrameIndex = MI.getOperand(FIOperandNum).getIndex();
223   uint64_t stackSize = MF.getFrameInfo()->getStackSize();
224   int64_t spOffset = MF.getFrameInfo()->getObjectOffset(FrameIndex);
225 
226   DEBUG(errs() << "FrameIndex : " << FrameIndex << "\n"
227                << "spOffset   : " << spOffset << "\n"
228                << "stackSize  : " << stackSize << "\n");
229 
230   eliminateFI(MI, FIOperandNum, FrameIndex, stackSize, spOffset);
231 }
232 
233 unsigned MipsRegisterInfo::
234 getFrameRegister(const MachineFunction &MF) const {
235   const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
236   bool IsN64 = Subtarget.isABI_N64();
237 
238   if (Subtarget.inMips16Mode())
239     return TFI->hasFP(MF) ? Mips::S0 : Mips::SP;
240   else
241     return TFI->hasFP(MF) ? (IsN64 ? Mips::FP_64 : Mips::FP) :
242                             (IsN64 ? Mips::SP_64 : Mips::SP);
243 
244 }
245 
246