1 //===-- MipsRegisterInfo.cpp - MIPS Register Information -== --------------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file contains the MIPS implementation of the TargetRegisterInfo class.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #include "MipsRegisterInfo.h"
15 #include "Mips.h"
16 #include "MipsAnalyzeImmediate.h"
17 #include "MipsInstrInfo.h"
18 #include "MipsMachineFunction.h"
19 #include "MipsSubtarget.h"
20 #include "llvm/ADT/BitVector.h"
21 #include "llvm/ADT/STLExtras.h"
22 #include "llvm/CodeGen/MachineFrameInfo.h"
23 #include "llvm/CodeGen/MachineFunction.h"
24 #include "llvm/CodeGen/MachineInstrBuilder.h"
25 #include "llvm/IR/Constants.h"
26 #include "llvm/IR/DebugInfo.h"
27 #include "llvm/IR/Function.h"
28 #include "llvm/IR/Type.h"
29 #include "llvm/Support/CommandLine.h"
30 #include "llvm/Support/Debug.h"
31 #include "llvm/Support/ErrorHandling.h"
32 #include "llvm/Support/raw_ostream.h"
33 #include "llvm/Target/TargetFrameLowering.h"
34 #include "llvm/Target/TargetInstrInfo.h"
35 #include "llvm/Target/TargetMachine.h"
36 #include "llvm/Target/TargetOptions.h"
37 
38 using namespace llvm;
39 
40 #define DEBUG_TYPE "mips-reg-info"
41 
42 #define GET_REGINFO_TARGET_DESC
43 #include "MipsGenRegisterInfo.inc"
44 
45 MipsRegisterInfo::MipsRegisterInfo(const MipsSubtarget &ST)
46   : MipsGenRegisterInfo(Mips::RA), Subtarget(ST) {}
47 
48 unsigned MipsRegisterInfo::getPICCallReg() { return Mips::T9; }
49 
50 const TargetRegisterClass *
51 MipsRegisterInfo::getPointerRegClass(const MachineFunction &MF,
52                                      unsigned Kind) const {
53   return Subtarget.isABI_N64() ? &Mips::GPR64RegClass : &Mips::GPR32RegClass;
54 }
55 
56 unsigned
57 MipsRegisterInfo::getRegPressureLimit(const TargetRegisterClass *RC,
58                                       MachineFunction &MF) const {
59   switch (RC->getID()) {
60   default:
61     return 0;
62   case Mips::GPR32RegClassID:
63   case Mips::GPR64RegClassID:
64   case Mips::DSPRRegClassID: {
65     const TargetFrameLowering *TFI = MF.getSubtarget().getFrameLowering();
66     return 28 - TFI->hasFP(MF);
67   }
68   case Mips::FGR32RegClassID:
69     return 32;
70   case Mips::AFGR64RegClassID:
71     return 16;
72   case Mips::FGR64RegClassID:
73     return 32;
74   }
75 }
76 
77 //===----------------------------------------------------------------------===//
78 // Callee Saved Registers methods
79 //===----------------------------------------------------------------------===//
80 
81 /// Mips Callee Saved Registers
82 const MCPhysReg *
83 MipsRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
84   if (Subtarget.isSingleFloat())
85     return CSR_SingleFloatOnly_SaveList;
86 
87   if (Subtarget.isABI_N64())
88     return CSR_N64_SaveList;
89 
90   if (Subtarget.isABI_N32())
91     return CSR_N32_SaveList;
92 
93   if (Subtarget.isFP64bit())
94     return CSR_O32_FP64_SaveList;
95 
96   if (Subtarget.isFPXX())
97     return CSR_O32_FPXX_SaveList;
98 
99   return CSR_O32_SaveList;
100 }
101 
102 const uint32_t*
103 MipsRegisterInfo::getCallPreservedMask(CallingConv::ID) const {
104   if (Subtarget.isSingleFloat())
105     return CSR_SingleFloatOnly_RegMask;
106 
107   if (Subtarget.isABI_N64())
108     return CSR_N64_RegMask;
109 
110   if (Subtarget.isABI_N32())
111     return CSR_N32_RegMask;
112 
113   if (Subtarget.isFP64bit())
114     return CSR_O32_FP64_RegMask;
115 
116   if (Subtarget.isFPXX())
117     return CSR_O32_FPXX_RegMask;
118 
119   return CSR_O32_RegMask;
120 }
121 
122 const uint32_t *MipsRegisterInfo::getMips16RetHelperMask() {
123   return CSR_Mips16RetHelper_RegMask;
124 }
125 
126 BitVector MipsRegisterInfo::
127 getReservedRegs(const MachineFunction &MF) const {
128   static const MCPhysReg ReservedGPR32[] = {
129     Mips::ZERO, Mips::K0, Mips::K1, Mips::SP
130   };
131 
132   static const MCPhysReg ReservedGPR64[] = {
133     Mips::ZERO_64, Mips::K0_64, Mips::K1_64, Mips::SP_64
134   };
135 
136   BitVector Reserved(getNumRegs());
137   typedef TargetRegisterClass::const_iterator RegIter;
138 
139   for (unsigned I = 0; I < array_lengthof(ReservedGPR32); ++I)
140     Reserved.set(ReservedGPR32[I]);
141 
142   // Reserve registers for the NaCl sandbox.
143   if (Subtarget.isTargetNaCl()) {
144     Reserved.set(Mips::T6);   // Reserved for control flow mask.
145     Reserved.set(Mips::T7);   // Reserved for memory access mask.
146     Reserved.set(Mips::T8);   // Reserved for thread pointer.
147   }
148 
149   for (unsigned I = 0; I < array_lengthof(ReservedGPR64); ++I)
150     Reserved.set(ReservedGPR64[I]);
151 
152   // For mno-abicalls, GP is a program invariant!
153   if (!Subtarget.isABICalls()) {
154     Reserved.set(Mips::GP);
155     Reserved.set(Mips::GP_64);
156   }
157 
158   if (Subtarget.isFP64bit()) {
159     // Reserve all registers in AFGR64.
160     for (RegIter Reg = Mips::AFGR64RegClass.begin(),
161          EReg = Mips::AFGR64RegClass.end(); Reg != EReg; ++Reg)
162       Reserved.set(*Reg);
163   } else {
164     // Reserve all registers in FGR64.
165     for (RegIter Reg = Mips::FGR64RegClass.begin(),
166          EReg = Mips::FGR64RegClass.end(); Reg != EReg; ++Reg)
167       Reserved.set(*Reg);
168   }
169   // Reserve FP if this function should have a dedicated frame pointer register.
170   if (MF.getSubtarget().getFrameLowering()->hasFP(MF)) {
171     if (Subtarget.inMips16Mode())
172       Reserved.set(Mips::S0);
173     else {
174       Reserved.set(Mips::FP);
175       Reserved.set(Mips::FP_64);
176     }
177   }
178 
179   // Reserve hardware registers.
180   Reserved.set(Mips::HWR29);
181 
182   // Reserve DSP control register.
183   Reserved.set(Mips::DSPPos);
184   Reserved.set(Mips::DSPSCount);
185   Reserved.set(Mips::DSPCarry);
186   Reserved.set(Mips::DSPEFI);
187   Reserved.set(Mips::DSPOutFlag);
188 
189   // Reserve MSA control registers.
190   Reserved.set(Mips::MSAIR);
191   Reserved.set(Mips::MSACSR);
192   Reserved.set(Mips::MSAAccess);
193   Reserved.set(Mips::MSASave);
194   Reserved.set(Mips::MSAModify);
195   Reserved.set(Mips::MSARequest);
196   Reserved.set(Mips::MSAMap);
197   Reserved.set(Mips::MSAUnmap);
198 
199   // Reserve RA if in mips16 mode.
200   if (Subtarget.inMips16Mode()) {
201     const MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
202     Reserved.set(Mips::RA);
203     Reserved.set(Mips::RA_64);
204     Reserved.set(Mips::T0);
205     Reserved.set(Mips::T1);
206     if (MF.getFunction()->hasFnAttribute("saveS2") || MipsFI->hasSaveS2())
207       Reserved.set(Mips::S2);
208   }
209 
210   // Reserve GP if small section is used.
211   if (Subtarget.useSmallSection()) {
212     Reserved.set(Mips::GP);
213     Reserved.set(Mips::GP_64);
214   }
215 
216   if (Subtarget.isABI_O32() && !Subtarget.useOddSPReg()) {
217     for (const auto &Reg : Mips::OddSPRegClass)
218       Reserved.set(Reg);
219   }
220 
221   return Reserved;
222 }
223 
224 bool
225 MipsRegisterInfo::requiresRegisterScavenging(const MachineFunction &MF) const {
226   return true;
227 }
228 
229 bool
230 MipsRegisterInfo::trackLivenessAfterRegAlloc(const MachineFunction &MF) const {
231   return true;
232 }
233 
234 // FrameIndex represent objects inside a abstract stack.
235 // We must replace FrameIndex with an stack/frame pointer
236 // direct reference.
237 void MipsRegisterInfo::
238 eliminateFrameIndex(MachineBasicBlock::iterator II, int SPAdj,
239                     unsigned FIOperandNum, RegScavenger *RS) const {
240   MachineInstr &MI = *II;
241   MachineFunction &MF = *MI.getParent()->getParent();
242 
243   DEBUG(errs() << "\nFunction : " << MF.getName() << "\n";
244         errs() << "<--------->\n" << MI);
245 
246   int FrameIndex = MI.getOperand(FIOperandNum).getIndex();
247   uint64_t stackSize = MF.getFrameInfo()->getStackSize();
248   int64_t spOffset = MF.getFrameInfo()->getObjectOffset(FrameIndex);
249 
250   DEBUG(errs() << "FrameIndex : " << FrameIndex << "\n"
251                << "spOffset   : " << spOffset << "\n"
252                << "stackSize  : " << stackSize << "\n");
253 
254   eliminateFI(MI, FIOperandNum, FrameIndex, stackSize, spOffset);
255 }
256 
257 unsigned MipsRegisterInfo::
258 getFrameRegister(const MachineFunction &MF) const {
259   const TargetFrameLowering *TFI = MF.getSubtarget().getFrameLowering();
260   bool IsN64 = Subtarget.isABI_N64();
261 
262   if (Subtarget.inMips16Mode())
263     return TFI->hasFP(MF) ? Mips::S0 : Mips::SP;
264   else
265     return TFI->hasFP(MF) ? (IsN64 ? Mips::FP_64 : Mips::FP) :
266                             (IsN64 ? Mips::SP_64 : Mips::SP);
267 
268 }
269 
270