1 //===-- MipsRegisterInfo.cpp - MIPS Register Information -== --------------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file contains the MIPS implementation of the TargetRegisterInfo class.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #include "MipsRegisterInfo.h"
15 #include "Mips.h"
16 #include "MipsInstrInfo.h"
17 #include "MipsMachineFunction.h"
18 #include "MipsSubtarget.h"
19 #include "MipsTargetMachine.h"
20 #include "llvm/ADT/BitVector.h"
21 #include "llvm/ADT/STLExtras.h"
22 #include "llvm/CodeGen/MachineFrameInfo.h"
23 #include "llvm/CodeGen/MachineRegisterInfo.h"
24 #include "llvm/CodeGen/MachineFunction.h"
25 #include "llvm/CodeGen/MachineInstrBuilder.h"
26 #include "llvm/IR/Constants.h"
27 #include "llvm/IR/DebugInfo.h"
28 #include "llvm/IR/Function.h"
29 #include "llvm/IR/Type.h"
30 #include "llvm/Support/CommandLine.h"
31 #include "llvm/Support/Debug.h"
32 #include "llvm/Support/ErrorHandling.h"
33 #include "llvm/Support/raw_ostream.h"
34 #include "llvm/Target/TargetFrameLowering.h"
35 #include "llvm/Target/TargetInstrInfo.h"
36 #include "llvm/Target/TargetMachine.h"
37 #include "llvm/Target/TargetOptions.h"
38 
39 using namespace llvm;
40 
41 #define DEBUG_TYPE "mips-reg-info"
42 
43 #define GET_REGINFO_TARGET_DESC
44 #include "MipsGenRegisterInfo.inc"
45 
46 MipsRegisterInfo::MipsRegisterInfo() : MipsGenRegisterInfo(Mips::RA) {}
47 
48 unsigned MipsRegisterInfo::getPICCallReg() { return Mips::T9; }
49 
50 const TargetRegisterClass *
51 MipsRegisterInfo::getPointerRegClass(const MachineFunction &MF,
52                                      unsigned Kind) const {
53   MipsABIInfo ABI = MF.getSubtarget<MipsSubtarget>().getABI();
54   bool inMicroMips = MF.getSubtarget<MipsSubtarget>().inMicroMipsMode();
55 
56   return ABI.ArePtrs64bit() ?
57              inMicroMips ?
58                  &Mips::GPRMM16_64RegClass : &Mips::GPR64RegClass
59              : inMicroMips ?
60                  &Mips::GPRMM16RegClass : &Mips::GPR32RegClass;
61 }
62 
63 unsigned
64 MipsRegisterInfo::getRegPressureLimit(const TargetRegisterClass *RC,
65                                       MachineFunction &MF) const {
66   switch (RC->getID()) {
67   default:
68     return 0;
69   case Mips::GPR32RegClassID:
70   case Mips::GPR64RegClassID:
71   case Mips::DSPRRegClassID: {
72     const TargetFrameLowering *TFI = MF.getSubtarget().getFrameLowering();
73     return 28 - TFI->hasFP(MF);
74   }
75   case Mips::FGR32RegClassID:
76     return 32;
77   case Mips::AFGR64RegClassID:
78     return 16;
79   case Mips::FGR64RegClassID:
80     return 32;
81   }
82 }
83 
84 //===----------------------------------------------------------------------===//
85 // Callee Saved Registers methods
86 //===----------------------------------------------------------------------===//
87 
88 /// Mips Callee Saved Registers
89 const MCPhysReg *
90 MipsRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
91   const MipsSubtarget &Subtarget = MF->getSubtarget<MipsSubtarget>();
92   const Function *F = MF->getFunction();
93   if (F->hasFnAttribute("interrupt")) {
94     if (Subtarget.hasMips64())
95       return Subtarget.hasMips64r6() ? CSR_Interrupt_64R6_SaveList
96                                      : CSR_Interrupt_64_SaveList;
97     else
98       return Subtarget.hasMips32r6() ? CSR_Interrupt_32R6_SaveList
99                                      : CSR_Interrupt_32_SaveList;
100   }
101 
102   if (Subtarget.isSingleFloat())
103     return CSR_SingleFloatOnly_SaveList;
104 
105   if (Subtarget.isABI_N64())
106     return CSR_N64_SaveList;
107 
108   if (Subtarget.isABI_N32())
109     return CSR_N32_SaveList;
110 
111   if (Subtarget.isFP64bit())
112     return CSR_O32_FP64_SaveList;
113 
114   if (Subtarget.isFPXX())
115     return CSR_O32_FPXX_SaveList;
116 
117   return CSR_O32_SaveList;
118 }
119 
120 const uint32_t *
121 MipsRegisterInfo::getCallPreservedMask(const MachineFunction &MF,
122                                        CallingConv::ID) const {
123   const MipsSubtarget &Subtarget = MF.getSubtarget<MipsSubtarget>();
124   if (Subtarget.isSingleFloat())
125     return CSR_SingleFloatOnly_RegMask;
126 
127   if (Subtarget.isABI_N64())
128     return CSR_N64_RegMask;
129 
130   if (Subtarget.isABI_N32())
131     return CSR_N32_RegMask;
132 
133   if (Subtarget.isFP64bit())
134     return CSR_O32_FP64_RegMask;
135 
136   if (Subtarget.isFPXX())
137     return CSR_O32_FPXX_RegMask;
138 
139   return CSR_O32_RegMask;
140 }
141 
142 const uint32_t *MipsRegisterInfo::getMips16RetHelperMask() {
143   return CSR_Mips16RetHelper_RegMask;
144 }
145 
146 BitVector MipsRegisterInfo::
147 getReservedRegs(const MachineFunction &MF) const {
148   static const MCPhysReg ReservedGPR32[] = {
149     Mips::ZERO, Mips::K0, Mips::K1, Mips::SP
150   };
151 
152   static const MCPhysReg ReservedGPR64[] = {
153     Mips::ZERO_64, Mips::K0_64, Mips::K1_64, Mips::SP_64
154   };
155 
156   BitVector Reserved(getNumRegs());
157   const MipsSubtarget &Subtarget = MF.getSubtarget<MipsSubtarget>();
158   typedef TargetRegisterClass::const_iterator RegIter;
159 
160   for (unsigned I = 0; I < array_lengthof(ReservedGPR32); ++I)
161     Reserved.set(ReservedGPR32[I]);
162 
163   // Reserve registers for the NaCl sandbox.
164   if (Subtarget.isTargetNaCl()) {
165     Reserved.set(Mips::T6);   // Reserved for control flow mask.
166     Reserved.set(Mips::T7);   // Reserved for memory access mask.
167     Reserved.set(Mips::T8);   // Reserved for thread pointer.
168   }
169 
170   for (unsigned I = 0; I < array_lengthof(ReservedGPR64); ++I)
171     Reserved.set(ReservedGPR64[I]);
172 
173   // For mno-abicalls, GP is a program invariant!
174   if (!Subtarget.isABICalls()) {
175     Reserved.set(Mips::GP);
176     Reserved.set(Mips::GP_64);
177   }
178 
179   if (Subtarget.isFP64bit()) {
180     // Reserve all registers in AFGR64.
181     for (RegIter Reg = Mips::AFGR64RegClass.begin(),
182          EReg = Mips::AFGR64RegClass.end(); Reg != EReg; ++Reg)
183       Reserved.set(*Reg);
184   } else {
185     // Reserve all registers in FGR64.
186     for (RegIter Reg = Mips::FGR64RegClass.begin(),
187          EReg = Mips::FGR64RegClass.end(); Reg != EReg; ++Reg)
188       Reserved.set(*Reg);
189   }
190   // Reserve FP if this function should have a dedicated frame pointer register.
191   if (Subtarget.getFrameLowering()->hasFP(MF)) {
192     if (Subtarget.inMips16Mode())
193       Reserved.set(Mips::S0);
194     else {
195       Reserved.set(Mips::FP);
196       Reserved.set(Mips::FP_64);
197 
198       // Reserve the base register if we need to both realign the stack and
199       // allocate variable-sized objects at runtime. This should test the
200       // same conditions as MipsFrameLowering::hasBP().
201       if (needsStackRealignment(MF) &&
202           MF.getFrameInfo()->hasVarSizedObjects()) {
203         Reserved.set(Mips::S7);
204         Reserved.set(Mips::S7_64);
205       }
206     }
207   }
208 
209   // Reserve hardware registers.
210   Reserved.set(Mips::HWR29);
211 
212   // Reserve DSP control register.
213   Reserved.set(Mips::DSPPos);
214   Reserved.set(Mips::DSPSCount);
215   Reserved.set(Mips::DSPCarry);
216   Reserved.set(Mips::DSPEFI);
217   Reserved.set(Mips::DSPOutFlag);
218 
219   // Reserve MSA control registers.
220   Reserved.set(Mips::MSAIR);
221   Reserved.set(Mips::MSACSR);
222   Reserved.set(Mips::MSAAccess);
223   Reserved.set(Mips::MSASave);
224   Reserved.set(Mips::MSAModify);
225   Reserved.set(Mips::MSARequest);
226   Reserved.set(Mips::MSAMap);
227   Reserved.set(Mips::MSAUnmap);
228 
229   // Reserve RA if in mips16 mode.
230   if (Subtarget.inMips16Mode()) {
231     const MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
232     Reserved.set(Mips::RA);
233     Reserved.set(Mips::RA_64);
234     Reserved.set(Mips::T0);
235     Reserved.set(Mips::T1);
236     if (MF.getFunction()->hasFnAttribute("saveS2") || MipsFI->hasSaveS2())
237       Reserved.set(Mips::S2);
238   }
239 
240   // Reserve GP if small section is used.
241   if (Subtarget.useSmallSection()) {
242     Reserved.set(Mips::GP);
243     Reserved.set(Mips::GP_64);
244   }
245 
246   if (Subtarget.isABI_O32() && !Subtarget.useOddSPReg()) {
247     for (const auto &Reg : Mips::OddSPRegClass)
248       Reserved.set(Reg);
249   }
250 
251   return Reserved;
252 }
253 
254 bool
255 MipsRegisterInfo::requiresRegisterScavenging(const MachineFunction &MF) const {
256   return true;
257 }
258 
259 bool
260 MipsRegisterInfo::trackLivenessAfterRegAlloc(const MachineFunction &MF) const {
261   return true;
262 }
263 
264 // FrameIndex represent objects inside a abstract stack.
265 // We must replace FrameIndex with an stack/frame pointer
266 // direct reference.
267 void MipsRegisterInfo::
268 eliminateFrameIndex(MachineBasicBlock::iterator II, int SPAdj,
269                     unsigned FIOperandNum, RegScavenger *RS) const {
270   MachineInstr &MI = *II;
271   MachineFunction &MF = *MI.getParent()->getParent();
272 
273   DEBUG(errs() << "\nFunction : " << MF.getName() << "\n";
274         errs() << "<--------->\n" << MI);
275 
276   int FrameIndex = MI.getOperand(FIOperandNum).getIndex();
277   uint64_t stackSize = MF.getFrameInfo()->getStackSize();
278   int64_t spOffset = MF.getFrameInfo()->getObjectOffset(FrameIndex);
279 
280   DEBUG(errs() << "FrameIndex : " << FrameIndex << "\n"
281                << "spOffset   : " << spOffset << "\n"
282                << "stackSize  : " << stackSize << "\n");
283 
284   eliminateFI(MI, FIOperandNum, FrameIndex, stackSize, spOffset);
285 }
286 
287 unsigned MipsRegisterInfo::
288 getFrameRegister(const MachineFunction &MF) const {
289   const MipsSubtarget &Subtarget = MF.getSubtarget<MipsSubtarget>();
290   const TargetFrameLowering *TFI = Subtarget.getFrameLowering();
291   bool IsN64 =
292       static_cast<const MipsTargetMachine &>(MF.getTarget()).getABI().IsN64();
293 
294   if (Subtarget.inMips16Mode())
295     return TFI->hasFP(MF) ? Mips::S0 : Mips::SP;
296   else
297     return TFI->hasFP(MF) ? (IsN64 ? Mips::FP_64 : Mips::FP) :
298                             (IsN64 ? Mips::SP_64 : Mips::SP);
299 }
300 
301 bool MipsRegisterInfo::canRealignStack(const MachineFunction &MF) const {
302   // Avoid realigning functions that explicitly do not want to be realigned.
303   // Normally, we should report an error when a function should be dynamically
304   // realigned but also has the attribute no-realign-stack. Unfortunately,
305   // with this attribute, MachineFrameInfo clamps each new object's alignment
306   // to that of the stack's alignment as specified by the ABI. As a result,
307   // the information of whether we have objects with larger alignment
308   // requirement than the stack's alignment is already lost at this point.
309   if (!TargetRegisterInfo::canRealignStack(MF))
310     return false;
311 
312   const MipsSubtarget &Subtarget = MF.getSubtarget<MipsSubtarget>();
313   unsigned FP = Subtarget.isGP32bit() ? Mips::FP : Mips::FP_64;
314   unsigned BP = Subtarget.isGP32bit() ? Mips::S7 : Mips::S7_64;
315 
316   // Support dynamic stack realignment only for targets with standard encoding.
317   if (!Subtarget.hasStandardEncoding())
318     return false;
319 
320   // We can't perform dynamic stack realignment if we can't reserve the
321   // frame pointer register.
322   if (!MF.getRegInfo().canReserveReg(FP))
323     return false;
324 
325   // We can realign the stack if we know the maximum call frame size and we
326   // don't have variable sized objects.
327   if (Subtarget.getFrameLowering()->hasReservedCallFrame(MF))
328     return true;
329 
330   // We have to reserve the base pointer register in the presence of variable
331   // sized objects.
332   return MF.getRegInfo().canReserveReg(BP);
333 }
334