1 //===- MipsRegisterInfo.cpp - MIPS Register Information -------------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file contains the MIPS implementation of the TargetRegisterInfo class.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #include "MipsRegisterInfo.h"
14 #include "MCTargetDesc/MipsABIInfo.h"
15 #include "Mips.h"
16 #include "MipsMachineFunction.h"
17 #include "MipsSubtarget.h"
18 #include "MipsTargetMachine.h"
19 #include "llvm/ADT/BitVector.h"
20 #include "llvm/ADT/STLExtras.h"
21 #include "llvm/CodeGen/MachineFrameInfo.h"
22 #include "llvm/CodeGen/MachineFunction.h"
23 #include "llvm/CodeGen/MachineInstr.h"
24 #include "llvm/CodeGen/MachineRegisterInfo.h"
25 #include "llvm/CodeGen/TargetFrameLowering.h"
26 #include "llvm/CodeGen/TargetRegisterInfo.h"
27 #include "llvm/CodeGen/TargetSubtargetInfo.h"
28 #include "llvm/IR/Function.h"
29 #include "llvm/MC/MCRegisterInfo.h"
30 #include "llvm/Support/Debug.h"
31 #include "llvm/Support/ErrorHandling.h"
32 #include "llvm/Support/raw_ostream.h"
33 #include <cstdint>
34 
35 using namespace llvm;
36 
37 #define DEBUG_TYPE "mips-reg-info"
38 
39 #define GET_REGINFO_TARGET_DESC
40 #include "MipsGenRegisterInfo.inc"
41 
42 MipsRegisterInfo::MipsRegisterInfo() : MipsGenRegisterInfo(Mips::RA) {}
43 
44 unsigned MipsRegisterInfo::getPICCallReg() { return Mips::T9; }
45 
46 const TargetRegisterClass *
47 MipsRegisterInfo::getPointerRegClass(const MachineFunction &MF,
48                                      unsigned Kind) const {
49   MipsABIInfo ABI = MF.getSubtarget<MipsSubtarget>().getABI();
50   MipsPtrClass PtrClassKind = static_cast<MipsPtrClass>(Kind);
51 
52   switch (PtrClassKind) {
53   case MipsPtrClass::Default:
54     return ABI.ArePtrs64bit() ? &Mips::GPR64RegClass : &Mips::GPR32RegClass;
55   case MipsPtrClass::GPR16MM:
56     return &Mips::GPRMM16RegClass;
57   case MipsPtrClass::StackPointer:
58     return ABI.ArePtrs64bit() ? &Mips::SP64RegClass : &Mips::SP32RegClass;
59   case MipsPtrClass::GlobalPointer:
60     return ABI.ArePtrs64bit() ? &Mips::GP64RegClass : &Mips::GP32RegClass;
61   }
62 
63   llvm_unreachable("Unknown pointer kind");
64 }
65 
66 unsigned
67 MipsRegisterInfo::getRegPressureLimit(const TargetRegisterClass *RC,
68                                       MachineFunction &MF) const {
69   switch (RC->getID()) {
70   default:
71     return 0;
72   case Mips::GPR32RegClassID:
73   case Mips::GPR64RegClassID:
74   case Mips::DSPRRegClassID: {
75     const TargetFrameLowering *TFI = MF.getSubtarget().getFrameLowering();
76     return 28 - TFI->hasFP(MF);
77   }
78   case Mips::FGR32RegClassID:
79     return 32;
80   case Mips::AFGR64RegClassID:
81     return 16;
82   case Mips::FGR64RegClassID:
83     return 32;
84   }
85 }
86 
87 //===----------------------------------------------------------------------===//
88 // Callee Saved Registers methods
89 //===----------------------------------------------------------------------===//
90 
91 /// Mips Callee Saved Registers
92 const MCPhysReg *
93 MipsRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
94   const MipsSubtarget &Subtarget = MF->getSubtarget<MipsSubtarget>();
95   const Function &F = MF->getFunction();
96   if (F.hasFnAttribute("interrupt")) {
97     if (Subtarget.hasMips64())
98       return Subtarget.hasMips64r6() ? CSR_Interrupt_64R6_SaveList
99                                      : CSR_Interrupt_64_SaveList;
100     else
101       return Subtarget.hasMips32r6() ? CSR_Interrupt_32R6_SaveList
102                                      : CSR_Interrupt_32_SaveList;
103   }
104 
105   if (Subtarget.isSingleFloat())
106     return CSR_SingleFloatOnly_SaveList;
107 
108   if (Subtarget.isABI_N64())
109     return CSR_N64_SaveList;
110 
111   if (Subtarget.isABI_N32())
112     return CSR_N32_SaveList;
113 
114   if (Subtarget.isFP64bit())
115     return CSR_O32_FP64_SaveList;
116 
117   if (Subtarget.isFPXX())
118     return CSR_O32_FPXX_SaveList;
119 
120   return CSR_O32_SaveList;
121 }
122 
123 const uint32_t *
124 MipsRegisterInfo::getCallPreservedMask(const MachineFunction &MF,
125                                        CallingConv::ID) const {
126   const MipsSubtarget &Subtarget = MF.getSubtarget<MipsSubtarget>();
127   if (Subtarget.isSingleFloat())
128     return CSR_SingleFloatOnly_RegMask;
129 
130   if (Subtarget.isABI_N64())
131     return CSR_N64_RegMask;
132 
133   if (Subtarget.isABI_N32())
134     return CSR_N32_RegMask;
135 
136   if (Subtarget.isFP64bit())
137     return CSR_O32_FP64_RegMask;
138 
139   if (Subtarget.isFPXX())
140     return CSR_O32_FPXX_RegMask;
141 
142   return CSR_O32_RegMask;
143 }
144 
145 const uint32_t *MipsRegisterInfo::getMips16RetHelperMask() {
146   return CSR_Mips16RetHelper_RegMask;
147 }
148 
149 BitVector MipsRegisterInfo::
150 getReservedRegs(const MachineFunction &MF) const {
151   static const MCPhysReg ReservedGPR32[] = {
152     Mips::ZERO, Mips::K0, Mips::K1, Mips::SP
153   };
154 
155   static const MCPhysReg ReservedGPR64[] = {
156     Mips::ZERO_64, Mips::K0_64, Mips::K1_64, Mips::SP_64
157   };
158 
159   BitVector Reserved(getNumRegs());
160   const MipsSubtarget &Subtarget = MF.getSubtarget<MipsSubtarget>();
161 
162   using RegIter = TargetRegisterClass::const_iterator;
163 
164   for (unsigned I = 0; I < array_lengthof(ReservedGPR32); ++I)
165     Reserved.set(ReservedGPR32[I]);
166 
167   // Reserve registers for the NaCl sandbox.
168   if (Subtarget.isTargetNaCl()) {
169     Reserved.set(Mips::T6);   // Reserved for control flow mask.
170     Reserved.set(Mips::T7);   // Reserved for memory access mask.
171     Reserved.set(Mips::T8);   // Reserved for thread pointer.
172   }
173 
174   for (unsigned I = 0; I < array_lengthof(ReservedGPR64); ++I)
175     Reserved.set(ReservedGPR64[I]);
176 
177   // For mno-abicalls, GP is a program invariant!
178   if (!Subtarget.isABICalls()) {
179     Reserved.set(Mips::GP);
180     Reserved.set(Mips::GP_64);
181   }
182 
183   if (Subtarget.isFP64bit()) {
184     // Reserve all registers in AFGR64.
185     for (RegIter Reg = Mips::AFGR64RegClass.begin(),
186          EReg = Mips::AFGR64RegClass.end(); Reg != EReg; ++Reg)
187       Reserved.set(*Reg);
188   } else {
189     // Reserve all registers in FGR64.
190     for (RegIter Reg = Mips::FGR64RegClass.begin(),
191          EReg = Mips::FGR64RegClass.end(); Reg != EReg; ++Reg)
192       Reserved.set(*Reg);
193   }
194   // Reserve FP if this function should have a dedicated frame pointer register.
195   if (Subtarget.getFrameLowering()->hasFP(MF)) {
196     if (Subtarget.inMips16Mode())
197       Reserved.set(Mips::S0);
198     else {
199       Reserved.set(Mips::FP);
200       Reserved.set(Mips::FP_64);
201 
202       // Reserve the base register if we need to both realign the stack and
203       // allocate variable-sized objects at runtime. This should test the
204       // same conditions as MipsFrameLowering::hasBP().
205       if (needsStackRealignment(MF) &&
206           MF.getFrameInfo().hasVarSizedObjects()) {
207         Reserved.set(Mips::S7);
208         Reserved.set(Mips::S7_64);
209       }
210     }
211   }
212 
213   // Reserve hardware registers.
214   Reserved.set(Mips::HWR29);
215 
216   // Reserve DSP control register.
217   Reserved.set(Mips::DSPPos);
218   Reserved.set(Mips::DSPSCount);
219   Reserved.set(Mips::DSPCarry);
220   Reserved.set(Mips::DSPEFI);
221   Reserved.set(Mips::DSPOutFlag);
222 
223   // Reserve MSA control registers.
224   Reserved.set(Mips::MSAIR);
225   Reserved.set(Mips::MSACSR);
226   Reserved.set(Mips::MSAAccess);
227   Reserved.set(Mips::MSASave);
228   Reserved.set(Mips::MSAModify);
229   Reserved.set(Mips::MSARequest);
230   Reserved.set(Mips::MSAMap);
231   Reserved.set(Mips::MSAUnmap);
232 
233   // Reserve RA if in mips16 mode.
234   if (Subtarget.inMips16Mode()) {
235     const MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
236     Reserved.set(Mips::RA);
237     Reserved.set(Mips::RA_64);
238     Reserved.set(Mips::T0);
239     Reserved.set(Mips::T1);
240     if (MF.getFunction().hasFnAttribute("saveS2") || MipsFI->hasSaveS2())
241       Reserved.set(Mips::S2);
242   }
243 
244   // Reserve GP if small section is used.
245   if (Subtarget.useSmallSection()) {
246     Reserved.set(Mips::GP);
247     Reserved.set(Mips::GP_64);
248   }
249 
250   return Reserved;
251 }
252 
253 bool
254 MipsRegisterInfo::requiresRegisterScavenging(const MachineFunction &MF) const {
255   return true;
256 }
257 
258 bool
259 MipsRegisterInfo::trackLivenessAfterRegAlloc(const MachineFunction &MF) const {
260   return true;
261 }
262 
263 // FrameIndex represent objects inside a abstract stack.
264 // We must replace FrameIndex with an stack/frame pointer
265 // direct reference.
266 void MipsRegisterInfo::
267 eliminateFrameIndex(MachineBasicBlock::iterator II, int SPAdj,
268                     unsigned FIOperandNum, RegScavenger *RS) const {
269   MachineInstr &MI = *II;
270   MachineFunction &MF = *MI.getParent()->getParent();
271 
272   LLVM_DEBUG(errs() << "\nFunction : " << MF.getName() << "\n";
273              errs() << "<--------->\n"
274                     << MI);
275 
276   int FrameIndex = MI.getOperand(FIOperandNum).getIndex();
277   uint64_t stackSize = MF.getFrameInfo().getStackSize();
278   int64_t spOffset = MF.getFrameInfo().getObjectOffset(FrameIndex);
279 
280   LLVM_DEBUG(errs() << "FrameIndex : " << FrameIndex << "\n"
281                     << "spOffset   : " << spOffset << "\n"
282                     << "stackSize  : " << stackSize << "\n"
283                     << "alignment  : "
284                     << MF.getFrameInfo().getObjectAlignment(FrameIndex)
285                     << "\n");
286 
287   eliminateFI(MI, FIOperandNum, FrameIndex, stackSize, spOffset);
288 }
289 
290 unsigned MipsRegisterInfo::
291 getFrameRegister(const MachineFunction &MF) const {
292   const MipsSubtarget &Subtarget = MF.getSubtarget<MipsSubtarget>();
293   const TargetFrameLowering *TFI = Subtarget.getFrameLowering();
294   bool IsN64 =
295       static_cast<const MipsTargetMachine &>(MF.getTarget()).getABI().IsN64();
296 
297   if (Subtarget.inMips16Mode())
298     return TFI->hasFP(MF) ? Mips::S0 : Mips::SP;
299   else
300     return TFI->hasFP(MF) ? (IsN64 ? Mips::FP_64 : Mips::FP) :
301                             (IsN64 ? Mips::SP_64 : Mips::SP);
302 }
303 
304 bool MipsRegisterInfo::canRealignStack(const MachineFunction &MF) const {
305   // Avoid realigning functions that explicitly do not want to be realigned.
306   // Normally, we should report an error when a function should be dynamically
307   // realigned but also has the attribute no-realign-stack. Unfortunately,
308   // with this attribute, MachineFrameInfo clamps each new object's alignment
309   // to that of the stack's alignment as specified by the ABI. As a result,
310   // the information of whether we have objects with larger alignment
311   // requirement than the stack's alignment is already lost at this point.
312   if (!TargetRegisterInfo::canRealignStack(MF))
313     return false;
314 
315   const MipsSubtarget &Subtarget = MF.getSubtarget<MipsSubtarget>();
316   unsigned FP = Subtarget.isGP32bit() ? Mips::FP : Mips::FP_64;
317   unsigned BP = Subtarget.isGP32bit() ? Mips::S7 : Mips::S7_64;
318 
319   // Support dynamic stack realignment for all targets except Mips16.
320   if (Subtarget.inMips16Mode())
321     return false;
322 
323   // We can't perform dynamic stack realignment if we can't reserve the
324   // frame pointer register.
325   if (!MF.getRegInfo().canReserveReg(FP))
326     return false;
327 
328   // We can realign the stack if we know the maximum call frame size and we
329   // don't have variable sized objects.
330   if (Subtarget.getFrameLowering()->hasReservedCallFrame(MF))
331     return true;
332 
333   // We have to reserve the base pointer register in the presence of variable
334   // sized objects.
335   return MF.getRegInfo().canReserveReg(BP);
336 }
337