1 //===-- MipsRegisterInfo.cpp - MIPS Register Information -== --------------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file contains the MIPS implementation of the TargetRegisterInfo class.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #define DEBUG_TYPE "mips-reg-info"
15 
16 #include "MipsRegisterInfo.h"
17 #include "Mips.h"
18 #include "MipsAnalyzeImmediate.h"
19 #include "MipsInstrInfo.h"
20 #include "MipsSubtarget.h"
21 #include "MipsMachineFunction.h"
22 #include "llvm/Constants.h"
23 #include "llvm/DebugInfo.h"
24 #include "llvm/Type.h"
25 #include "llvm/CodeGen/ValueTypes.h"
26 #include "llvm/CodeGen/MachineInstrBuilder.h"
27 #include "llvm/CodeGen/MachineFunction.h"
28 #include "llvm/CodeGen/MachineFrameInfo.h"
29 #include "llvm/Target/TargetFrameLowering.h"
30 #include "llvm/Target/TargetMachine.h"
31 #include "llvm/Target/TargetOptions.h"
32 #include "llvm/Target/TargetInstrInfo.h"
33 #include "llvm/Support/CommandLine.h"
34 #include "llvm/Support/Debug.h"
35 #include "llvm/Support/ErrorHandling.h"
36 #include "llvm/Support/raw_ostream.h"
37 #include "llvm/ADT/BitVector.h"
38 #include "llvm/ADT/STLExtras.h"
39 
40 #define GET_REGINFO_TARGET_DESC
41 #include "MipsGenRegisterInfo.inc"
42 
43 using namespace llvm;
44 
45 MipsRegisterInfo::MipsRegisterInfo(const MipsSubtarget &ST)
46   : MipsGenRegisterInfo(Mips::RA), Subtarget(ST) {}
47 
48 unsigned MipsRegisterInfo::getPICCallReg() { return Mips::T9; }
49 
50 //===----------------------------------------------------------------------===//
51 // Callee Saved Registers methods
52 //===----------------------------------------------------------------------===//
53 
54 /// Mips Callee Saved Registers
55 const uint16_t* MipsRegisterInfo::
56 getCalleeSavedRegs(const MachineFunction *MF) const {
57   if (Subtarget.isSingleFloat())
58     return CSR_SingleFloatOnly_SaveList;
59   else if (!Subtarget.hasMips64())
60     return CSR_O32_SaveList;
61   else if (Subtarget.isABI_N32())
62     return CSR_N32_SaveList;
63 
64   assert(Subtarget.isABI_N64());
65   return CSR_N64_SaveList;
66 }
67 
68 const uint32_t*
69 MipsRegisterInfo::getCallPreservedMask(CallingConv::ID) const {
70   if (Subtarget.isSingleFloat())
71     return CSR_SingleFloatOnly_RegMask;
72   else if (!Subtarget.hasMips64())
73     return CSR_O32_RegMask;
74   else if (Subtarget.isABI_N32())
75     return CSR_N32_RegMask;
76 
77   assert(Subtarget.isABI_N64());
78   return CSR_N64_RegMask;
79 }
80 
81 BitVector MipsRegisterInfo::
82 getReservedRegs(const MachineFunction &MF) const {
83   static const uint16_t ReservedCPURegs[] = {
84     Mips::ZERO, Mips::K0, Mips::K1, Mips::SP
85   };
86 
87   static const uint16_t ReservedCPU64Regs[] = {
88     Mips::ZERO_64, Mips::K0_64, Mips::K1_64, Mips::SP_64
89   };
90 
91   BitVector Reserved(getNumRegs());
92   typedef TargetRegisterClass::const_iterator RegIter;
93 
94   for (unsigned I = 0; I < array_lengthof(ReservedCPURegs); ++I)
95     Reserved.set(ReservedCPURegs[I]);
96 
97   for (unsigned I = 0; I < array_lengthof(ReservedCPU64Regs); ++I)
98     Reserved.set(ReservedCPU64Regs[I]);
99 
100   if (Subtarget.hasMips64()) {
101     // Reserve all registers in AFGR64.
102     for (RegIter Reg = Mips::AFGR64RegClass.begin(),
103          EReg = Mips::AFGR64RegClass.end(); Reg != EReg; ++Reg)
104       Reserved.set(*Reg);
105   } else {
106     // Reserve all registers in FGR64.
107     for (RegIter Reg = Mips::FGR64RegClass.begin(),
108          EReg = Mips::FGR64RegClass.end(); Reg != EReg; ++Reg)
109       Reserved.set(*Reg);
110   }
111   // Reserve FP if this function should have a dedicated frame pointer register.
112   if (MF.getTarget().getFrameLowering()->hasFP(MF)) {
113     if (Subtarget.inMips16Mode())
114       Reserved.set(Mips::S0);
115     else {
116       Reserved.set(Mips::FP);
117       Reserved.set(Mips::FP_64);
118     }
119   }
120 
121   // Reserve hardware registers.
122   Reserved.set(Mips::HWR29);
123   Reserved.set(Mips::HWR29_64);
124 
125   // Reserve DSP control register.
126   Reserved.set(Mips::DSPCtrl);
127 
128   // Reserve RA if in mips16 mode.
129   if (Subtarget.inMips16Mode()) {
130     Reserved.set(Mips::RA);
131     Reserved.set(Mips::RA_64);
132   }
133 
134   // Reserve GP if small section is used.
135   if (Subtarget.useSmallSection()) {
136     Reserved.set(Mips::GP);
137     Reserved.set(Mips::GP_64);
138   }
139 
140   return Reserved;
141 }
142 
143 bool
144 MipsRegisterInfo::requiresRegisterScavenging(const MachineFunction &MF) const {
145   return true;
146 }
147 
148 bool
149 MipsRegisterInfo::trackLivenessAfterRegAlloc(const MachineFunction &MF) const {
150   return true;
151 }
152 
153 // FrameIndex represent objects inside a abstract stack.
154 // We must replace FrameIndex with an stack/frame pointer
155 // direct reference.
156 void MipsRegisterInfo::
157 eliminateFrameIndex(MachineBasicBlock::iterator II, int SPAdj,
158                     RegScavenger *RS) const {
159   MachineInstr &MI = *II;
160   MachineFunction &MF = *MI.getParent()->getParent();
161 
162   unsigned i = 0;
163   while (!MI.getOperand(i).isFI()) {
164     ++i;
165     assert(i < MI.getNumOperands() &&
166            "Instr doesn't have FrameIndex operand!");
167   }
168 
169   DEBUG(errs() << "\nFunction : " << MF.getName() << "\n";
170         errs() << "<--------->\n" << MI);
171 
172   int FrameIndex = MI.getOperand(i).getIndex();
173   uint64_t stackSize = MF.getFrameInfo()->getStackSize();
174   int64_t spOffset = MF.getFrameInfo()->getObjectOffset(FrameIndex);
175 
176   DEBUG(errs() << "FrameIndex : " << FrameIndex << "\n"
177                << "spOffset   : " << spOffset << "\n"
178                << "stackSize  : " << stackSize << "\n");
179 
180   eliminateFI(MI, i, FrameIndex, stackSize, spOffset);
181 }
182 
183 unsigned MipsRegisterInfo::
184 getFrameRegister(const MachineFunction &MF) const {
185   const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
186   bool IsN64 = Subtarget.isABI_N64();
187 
188   if (Subtarget.inMips16Mode())
189     return TFI->hasFP(MF) ? Mips::S0 : Mips::SP;
190   else
191     return TFI->hasFP(MF) ? (IsN64 ? Mips::FP_64 : Mips::FP) :
192                             (IsN64 ? Mips::SP_64 : Mips::SP);
193 
194 }
195 
196 unsigned MipsRegisterInfo::
197 getEHExceptionRegister() const {
198   llvm_unreachable("What is the exception register");
199 }
200 
201 unsigned MipsRegisterInfo::
202 getEHHandlerRegister() const {
203   llvm_unreachable("What is the exception handler register");
204 }
205