1 //===- MipsRegisterInfo.cpp - MIPS Register Information -== -----*- C++ -*-===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file contains the MIPS implementation of the TargetRegisterInfo class.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #define DEBUG_TYPE "mips-reg-info"
15 
16 #include "Mips.h"
17 #include "MipsSubtarget.h"
18 #include "MipsRegisterInfo.h"
19 #include "MipsMachineFunction.h"
20 #include "llvm/Constants.h"
21 #include "llvm/Type.h"
22 #include "llvm/Function.h"
23 #include "llvm/CodeGen/ValueTypes.h"
24 #include "llvm/CodeGen/MachineInstrBuilder.h"
25 #include "llvm/CodeGen/MachineFunction.h"
26 #include "llvm/CodeGen/MachineFrameInfo.h"
27 #include "llvm/Target/TargetFrameLowering.h"
28 #include "llvm/Target/TargetMachine.h"
29 #include "llvm/Target/TargetOptions.h"
30 #include "llvm/Target/TargetInstrInfo.h"
31 #include "llvm/Support/CommandLine.h"
32 #include "llvm/Support/Debug.h"
33 #include "llvm/Support/ErrorHandling.h"
34 #include "llvm/Support/raw_ostream.h"
35 #include "llvm/ADT/BitVector.h"
36 #include "llvm/ADT/STLExtras.h"
37 #include "llvm/Analysis/DebugInfo.h"
38 
39 #define GET_REGINFO_TARGET_DESC
40 #include "MipsGenRegisterInfo.inc"
41 
42 using namespace llvm;
43 
44 MipsRegisterInfo::MipsRegisterInfo(const MipsSubtarget &ST,
45                                    const TargetInstrInfo &tii)
46   : MipsGenRegisterInfo(Mips::RA), Subtarget(ST), TII(tii) {}
47 
48 unsigned MipsRegisterInfo::getPICCallReg() { return Mips::T9; }
49 
50 //===----------------------------------------------------------------------===//
51 // Callee Saved Registers methods
52 //===----------------------------------------------------------------------===//
53 
54 /// Mips Callee Saved Registers
55 const unsigned* MipsRegisterInfo::
56 getCalleeSavedRegs(const MachineFunction *MF) const
57 {
58   // Mips callee-save register range is $16-$23, $f20-$f30
59   static const unsigned SingleFloatOnlyCalleeSavedRegs[] = {
60     Mips::F31, Mips::F30, Mips::F29, Mips::F28, Mips::F27, Mips::F26,
61     Mips::F25, Mips::F24, Mips::F23, Mips::F22, Mips::F21, Mips::F20,
62     Mips::RA, Mips::FP, Mips::S7, Mips::S6, Mips::S5, Mips::S4,
63     Mips::S3, Mips::S2, Mips::S1, Mips::S0, 0
64   };
65 
66   static const unsigned Mips32CalleeSavedRegs[] = {
67     Mips::D15, Mips::D14, Mips::D13, Mips::D12, Mips::D11, Mips::D10,
68     Mips::RA, Mips::FP, Mips::S7, Mips::S6, Mips::S5, Mips::S4,
69     Mips::S3, Mips::S2, Mips::S1, Mips::S0, 0
70   };
71 
72   static const unsigned N32CalleeSavedRegs[] = {
73     Mips::D31_64, Mips::D29_64, Mips::D27_64, Mips::D25_64, Mips::D23_64,
74     Mips::D21_64,
75     Mips::RA_64, Mips::FP_64, Mips::GP_64, Mips::S7_64, Mips::S6_64,
76     Mips::S5_64, Mips::S4_64, Mips::S3_64, Mips::S2_64, Mips::S1_64,
77     Mips::S0_64, 0
78   };
79 
80   static const unsigned N64CalleeSavedRegs[] = {
81     Mips::D31_64, Mips::D30_64, Mips::D29_64, Mips::D28_64, Mips::D27_64,
82     Mips::D26_64, Mips::D25_64, Mips::D24_64,
83     Mips::RA_64, Mips::FP_64, Mips::GP_64, Mips::S7_64, Mips::S6_64,
84     Mips::S5_64, Mips::S4_64, Mips::S3_64, Mips::S2_64, Mips::S1_64,
85     Mips::S0_64, 0
86   };
87 
88   if (Subtarget.isSingleFloat())
89     return SingleFloatOnlyCalleeSavedRegs;
90   else if (!Subtarget.hasMips64())
91     return Mips32CalleeSavedRegs;
92   else if (Subtarget.isABI_N32())
93     return N32CalleeSavedRegs;
94 
95   assert(Subtarget.isABI_N64());
96   return N64CalleeSavedRegs;
97 }
98 
99 BitVector MipsRegisterInfo::
100 getReservedRegs(const MachineFunction &MF) const {
101   static const unsigned ReservedCPURegs[] = {
102     Mips::ZERO, Mips::AT, Mips::K0, Mips::K1,
103     Mips::GP, Mips::SP, Mips::FP, Mips::RA
104   };
105 
106   static const unsigned ReservedCPU64Regs[] = {
107     Mips::ZERO_64, Mips::AT_64, Mips::K0_64, Mips::K1_64,
108     Mips::GP_64, Mips::SP_64, Mips::FP_64, Mips::RA_64
109   };
110 
111   BitVector Reserved(getNumRegs());
112   typedef TargetRegisterClass::iterator RegIter;
113 
114   for (unsigned I = 0; I < array_lengthof(ReservedCPURegs); ++I)
115     Reserved.set(ReservedCPURegs[I]);
116 
117   if (Subtarget.hasMips64()) {
118     for (unsigned I = 0; I < array_lengthof(ReservedCPU64Regs); ++I)
119       Reserved.set(ReservedCPU64Regs[I]);
120 
121     // Reserve all registers in AFGR64.
122     for (RegIter Reg = Mips::AFGR64RegisterClass->begin();
123          Reg != Mips::AFGR64RegisterClass->end(); ++Reg)
124       Reserved.set(*Reg);
125   }
126   else {
127     // Reserve all registers in CPU64Regs & FGR64.
128     for (RegIter Reg = Mips::CPU64RegsRegisterClass->begin();
129          Reg != Mips::CPU64RegsRegisterClass->end(); ++Reg)
130       Reserved.set(*Reg);
131 
132     for (RegIter Reg = Mips::FGR64RegisterClass->begin();
133          Reg != Mips::FGR64RegisterClass->end(); ++Reg)
134       Reserved.set(*Reg);
135   }
136 
137   return Reserved;
138 }
139 
140 // This function eliminate ADJCALLSTACKDOWN,
141 // ADJCALLSTACKUP pseudo instructions
142 void MipsRegisterInfo::
143 eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
144                               MachineBasicBlock::iterator I) const {
145   // Simply discard ADJCALLSTACKDOWN, ADJCALLSTACKUP instructions.
146   MBB.erase(I);
147 }
148 
149 // FrameIndex represent objects inside a abstract stack.
150 // We must replace FrameIndex with an stack/frame pointer
151 // direct reference.
152 void MipsRegisterInfo::
153 eliminateFrameIndex(MachineBasicBlock::iterator II, int SPAdj,
154                     RegScavenger *RS) const {
155   MachineInstr &MI = *II;
156   MachineFunction &MF = *MI.getParent()->getParent();
157   MachineFrameInfo *MFI = MF.getFrameInfo();
158   MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
159 
160   unsigned i = 0;
161   while (!MI.getOperand(i).isFI()) {
162     ++i;
163     assert(i < MI.getNumOperands() &&
164            "Instr doesn't have FrameIndex operand!");
165   }
166 
167   DEBUG(errs() << "\nFunction : " << MF.getFunction()->getName() << "\n";
168         errs() << "<--------->\n" << MI);
169 
170   int FrameIndex = MI.getOperand(i).getIndex();
171   int stackSize  = MF.getFrameInfo()->getStackSize();
172   int spOffset   = MF.getFrameInfo()->getObjectOffset(FrameIndex);
173 
174   DEBUG(errs() << "FrameIndex : " << FrameIndex << "\n"
175                << "spOffset   : " << spOffset << "\n"
176                << "stackSize  : " << stackSize << "\n");
177 
178   const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo();
179   int MinCSFI = 0;
180   int MaxCSFI = -1;
181 
182   if (CSI.size()) {
183     MinCSFI = CSI[0].getFrameIdx();
184     MaxCSFI = CSI[CSI.size() - 1].getFrameIdx();
185   }
186 
187   // The following stack frame objects are always referenced relative to $sp:
188   //  1. Outgoing arguments.
189   //  2. Pointer to dynamically allocated stack space.
190   //  3. Locations for callee-saved registers.
191   // Everything else is referenced relative to whatever register
192   // getFrameRegister() returns.
193   unsigned FrameReg;
194 
195   if (MipsFI->isOutArgFI(FrameIndex) || MipsFI->isDynAllocFI(FrameIndex) ||
196       (FrameIndex >= MinCSFI && FrameIndex <= MaxCSFI))
197     FrameReg = Subtarget.isABI_N64() ? Mips::SP_64 : Mips::SP;
198   else
199     FrameReg = getFrameRegister(MF);
200 
201   // Calculate final offset.
202   // - There is no need to change the offset if the frame object is one of the
203   //   following: an outgoing argument, pointer to a dynamically allocated
204   //   stack space or a $gp restore location,
205   // - If the frame object is any of the following, its offset must be adjusted
206   //   by adding the size of the stack:
207   //   incoming argument, callee-saved register location or local variable.
208   int Offset;
209 
210   if (MipsFI->isOutArgFI(FrameIndex) || MipsFI->isGPFI(FrameIndex) ||
211       MipsFI->isDynAllocFI(FrameIndex))
212     Offset = spOffset;
213   else
214     Offset = spOffset + stackSize;
215 
216   Offset    += MI.getOperand(i+1).getImm();
217 
218   DEBUG(errs() << "Offset     : " << Offset << "\n" << "<--------->\n");
219 
220   // If MI is not a debug value, make sure Offset fits in the 16-bit immediate
221   // field.
222   if (!MI.isDebugValue() && (Offset >= 0x8000 || Offset < -0x8000)) {
223     MachineBasicBlock &MBB = *MI.getParent();
224     DebugLoc DL = II->getDebugLoc();
225     int ImmHi = (((unsigned)Offset & 0xffff0000) >> 16) +
226                 ((Offset & 0x8000) != 0);
227 
228     // FIXME: change this when mips goes MC".
229     BuildMI(MBB, II, DL, TII.get(Mips::NOAT));
230     BuildMI(MBB, II, DL, TII.get(Mips::LUi), Mips::AT).addImm(ImmHi);
231     BuildMI(MBB, II, DL, TII.get(Mips::ADDu), Mips::AT).addReg(FrameReg)
232                                                        .addReg(Mips::AT);
233     FrameReg = Mips::AT;
234     Offset = (short)(Offset & 0xffff);
235 
236     BuildMI(MBB, ++II, MI.getDebugLoc(), TII.get(Mips::ATMACRO));
237   }
238 
239   MI.getOperand(i).ChangeToRegister(FrameReg, false);
240   MI.getOperand(i+1).ChangeToImmediate(Offset);
241 }
242 
243 unsigned MipsRegisterInfo::
244 getFrameRegister(const MachineFunction &MF) const {
245   const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
246   bool IsN64 = Subtarget.isABI_N64();
247 
248   return TFI->hasFP(MF) ? (IsN64 ? Mips::FP_64 : Mips::FP) :
249                           (IsN64 ? Mips::SP_64 : Mips::SP);
250 }
251 
252 unsigned MipsRegisterInfo::
253 getEHExceptionRegister() const {
254   llvm_unreachable("What is the exception register");
255   return 0;
256 }
257 
258 unsigned MipsRegisterInfo::
259 getEHHandlerRegister() const {
260   llvm_unreachable("What is the exception handler register");
261   return 0;
262 }
263