1 //===- MipsRegisterInfo.cpp - MIPS Register Information -== -----*- C++ -*-===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file contains the MIPS implementation of the TargetRegisterInfo class.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #define DEBUG_TYPE "mips-reg-info"
15 
16 #include "Mips.h"
17 #include "MipsSubtarget.h"
18 #include "MipsRegisterInfo.h"
19 #include "MipsMachineFunction.h"
20 #include "llvm/Constants.h"
21 #include "llvm/Type.h"
22 #include "llvm/Function.h"
23 #include "llvm/CodeGen/ValueTypes.h"
24 #include "llvm/CodeGen/MachineInstrBuilder.h"
25 #include "llvm/CodeGen/MachineFunction.h"
26 #include "llvm/CodeGen/MachineFrameInfo.h"
27 #include "llvm/CodeGen/MachineLocation.h"
28 #include "llvm/Target/TargetFrameLowering.h"
29 #include "llvm/Target/TargetMachine.h"
30 #include "llvm/Target/TargetOptions.h"
31 #include "llvm/Target/TargetInstrInfo.h"
32 #include "llvm/Support/CommandLine.h"
33 #include "llvm/Support/Debug.h"
34 #include "llvm/Support/ErrorHandling.h"
35 #include "llvm/Support/raw_ostream.h"
36 #include "llvm/ADT/BitVector.h"
37 #include "llvm/ADT/STLExtras.h"
38 
39 using namespace llvm;
40 
41 MipsRegisterInfo::MipsRegisterInfo(const MipsSubtarget &ST,
42                                    const TargetInstrInfo &tii)
43   : MipsGenRegisterInfo(Mips::ADJCALLSTACKDOWN, Mips::ADJCALLSTACKUP),
44     Subtarget(ST), TII(tii) {}
45 
46 /// getRegisterNumbering - Given the enum value for some register, e.g.
47 /// Mips::RA, return the number that it corresponds to (e.g. 31).
48 unsigned MipsRegisterInfo::
49 getRegisterNumbering(unsigned RegEnum)
50 {
51   switch (RegEnum) {
52     case Mips::ZERO : case Mips::F0 : case Mips::D0 : return 0;
53     case Mips::AT   : case Mips::F1 : return 1;
54     case Mips::V0   : case Mips::F2 : case Mips::D1 : return 2;
55     case Mips::V1   : case Mips::F3 : return 3;
56     case Mips::A0   : case Mips::F4 : case Mips::D2 : return 4;
57     case Mips::A1   : case Mips::F5 : return 5;
58     case Mips::A2   : case Mips::F6 : case Mips::D3 : return 6;
59     case Mips::A3   : case Mips::F7 : return 7;
60     case Mips::T0   : case Mips::F8 : case Mips::D4 : return 8;
61     case Mips::T1   : case Mips::F9 : return 9;
62     case Mips::T2   : case Mips::F10: case Mips::D5: return 10;
63     case Mips::T3   : case Mips::F11: return 11;
64     case Mips::T4   : case Mips::F12: case Mips::D6: return 12;
65     case Mips::T5   : case Mips::F13: return 13;
66     case Mips::T6   : case Mips::F14: case Mips::D7: return 14;
67     case Mips::T7   : case Mips::F15: return 15;
68     case Mips::T8   : case Mips::F16: case Mips::D8: return 16;
69     case Mips::T9   : case Mips::F17: return 17;
70     case Mips::S0   : case Mips::F18: case Mips::D9: return 18;
71     case Mips::S1   : case Mips::F19: return 19;
72     case Mips::S2   : case Mips::F20: case Mips::D10: return 20;
73     case Mips::S3   : case Mips::F21: return 21;
74     case Mips::S4   : case Mips::F22: case Mips::D11: return 22;
75     case Mips::S5   : case Mips::F23: return 23;
76     case Mips::S6   : case Mips::F24: case Mips::D12: return 24;
77     case Mips::S7   : case Mips::F25: return 25;
78     case Mips::K0   : case Mips::F26: case Mips::D13: return 26;
79     case Mips::K1   : case Mips::F27: return 27;
80     case Mips::GP   : case Mips::F28: case Mips::D14: return 28;
81     case Mips::SP   : case Mips::F29: return 29;
82     case Mips::FP   : case Mips::F30: case Mips::D15: return 30;
83     case Mips::RA   : case Mips::F31: return 31;
84     default: llvm_unreachable("Unknown register number!");
85   }
86   return 0; // Not reached
87 }
88 
89 unsigned MipsRegisterInfo::getPICCallReg() { return Mips::T9; }
90 
91 //===----------------------------------------------------------------------===//
92 // Callee Saved Registers methods
93 //===----------------------------------------------------------------------===//
94 
95 /// Mips Callee Saved Registers
96 const unsigned* MipsRegisterInfo::
97 getCalleeSavedRegs(const MachineFunction *MF) const
98 {
99   // Mips callee-save register range is $16-$23, $f20-$f30
100   static const unsigned SingleFloatOnlyCalleeSavedRegs[] = {
101     Mips::S0, Mips::S1, Mips::S2, Mips::S3,
102     Mips::S4, Mips::S5, Mips::S6, Mips::S7,
103     Mips::F20, Mips::F21, Mips::F22, Mips::F23, Mips::F24, Mips::F25,
104     Mips::F26, Mips::F27, Mips::F28, Mips::F29, Mips::F30, 0
105   };
106 
107   static const unsigned BitMode32CalleeSavedRegs[] = {
108     Mips::S0, Mips::S1, Mips::S2, Mips::S3,
109     Mips::S4, Mips::S5, Mips::S6, Mips::S7,
110     Mips::F20, Mips::F22, Mips::F24, Mips::F26, Mips::F28, Mips::F30, 0
111   };
112 
113   if (Subtarget.isSingleFloat())
114     return SingleFloatOnlyCalleeSavedRegs;
115   else
116     return BitMode32CalleeSavedRegs;
117 }
118 
119 BitVector MipsRegisterInfo::
120 getReservedRegs(const MachineFunction &MF) const {
121   BitVector Reserved(getNumRegs());
122   Reserved.set(Mips::ZERO);
123   Reserved.set(Mips::AT);
124   Reserved.set(Mips::K0);
125   Reserved.set(Mips::K1);
126   Reserved.set(Mips::GP);
127   Reserved.set(Mips::SP);
128   Reserved.set(Mips::FP);
129   Reserved.set(Mips::RA);
130 
131   // SRV4 requires that odd register can't be used.
132   if (!Subtarget.isSingleFloat())
133     for (unsigned FReg=(Mips::F0)+1; FReg < Mips::F30; FReg+=2)
134       Reserved.set(FReg);
135 
136   return Reserved;
137 }
138 
139 // This function eliminate ADJCALLSTACKDOWN,
140 // ADJCALLSTACKUP pseudo instructions
141 void MipsRegisterInfo::
142 eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
143                               MachineBasicBlock::iterator I) const {
144   // Simply discard ADJCALLSTACKDOWN, ADJCALLSTACKUP instructions.
145   MBB.erase(I);
146 }
147 
148 // FrameIndex represent objects inside a abstract stack.
149 // We must replace FrameIndex with an stack/frame pointer
150 // direct reference.
151 void MipsRegisterInfo::
152 eliminateFrameIndex(MachineBasicBlock::iterator II, int SPAdj,
153                     RegScavenger *RS) const {
154   MachineInstr &MI = *II;
155   MachineFunction &MF = *MI.getParent()->getParent();
156 
157   unsigned i = 0;
158   while (!MI.getOperand(i).isFI()) {
159     ++i;
160     assert(i < MI.getNumOperands() &&
161            "Instr doesn't have FrameIndex operand!");
162   }
163 
164   DEBUG(errs() << "\nFunction : " << MF.getFunction()->getName() << "\n";
165         errs() << "<--------->\n" << MI);
166 
167   int FrameIndex = MI.getOperand(i).getIndex();
168   int stackSize  = MF.getFrameInfo()->getStackSize();
169   int spOffset   = MF.getFrameInfo()->getObjectOffset(FrameIndex);
170 
171   DEBUG(errs() << "FrameIndex : " << FrameIndex << "\n"
172                << "spOffset   : " << spOffset << "\n"
173                << "stackSize  : " << stackSize << "\n");
174 
175   // as explained on LowerFormalArguments, detect negative offsets
176   // and adjust SPOffsets considering the final stack size.
177   int Offset = ((spOffset < 0) ? (stackSize + (-(spOffset+4))) : (spOffset));
178   Offset    += MI.getOperand(i-1).getImm();
179 
180   DEBUG(errs() << "Offset     : " << Offset << "\n" << "<--------->\n");
181 
182   unsigned NewReg = 0;
183   int NewImm = 0;
184   MachineBasicBlock &MBB = *MI.getParent();
185   bool ATUsed;
186   unsigned OrigReg = getFrameRegister(MF);
187   int OrigImm = Offset;
188 
189 // OrigImm fits in the 16-bit field
190   if (OrigImm < 0x8000 && OrigImm >= -0x8000) {
191     NewReg = OrigReg;
192     NewImm = OrigImm;
193     ATUsed = false;
194   }
195   else {
196     const TargetInstrInfo *TII = MF.getTarget().getInstrInfo();
197     DebugLoc DL = II->getDebugLoc();
198     int ImmLo = OrigImm & 0xffff;
199     int ImmHi = (((unsigned)OrigImm & 0xffff0000) >> 16) + ((OrigImm & 0x8000) != 0);
200 
201     // FIXME: change this when mips goes MC".
202     BuildMI(MBB, II, DL, TII->get(Mips::NOAT));
203     BuildMI(MBB, II, DL, TII->get(Mips::LUi), Mips::AT).addImm(ImmHi);
204     BuildMI(MBB, II, DL, TII->get(Mips::ADDu), Mips::AT).addReg(OrigReg).addReg(Mips::AT);
205     NewReg = Mips::AT;
206     NewImm = ImmLo;
207 
208     ATUsed = true;
209   }
210 
211   // FIXME: change this when mips goes MC".
212   if (ATUsed)
213     BuildMI(MBB, ++II, MI.getDebugLoc(), TII.get(Mips::ATMACRO));
214 
215   MI.getOperand(i).ChangeToRegister(NewReg, false);
216   MI.getOperand(i-1).ChangeToImmediate(NewImm);
217 }
218 
219 void MipsRegisterInfo::
220 processFunctionBeforeFrameFinalized(MachineFunction &MF) const {
221   // Set the stack offset where GP must be saved/loaded from.
222   MachineFrameInfo *MFI = MF.getFrameInfo();
223   MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
224   if (MipsFI->needGPSaveRestore())
225     MFI->setObjectOffset(MipsFI->getGPFI(), MipsFI->getGPStackOffset());
226 }
227 
228 unsigned MipsRegisterInfo::
229 getRARegister() const {
230   return Mips::RA;
231 }
232 
233 unsigned MipsRegisterInfo::
234 getFrameRegister(const MachineFunction &MF) const {
235   const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
236 
237   return TFI->hasFP(MF) ? Mips::FP : Mips::SP;
238 }
239 
240 unsigned MipsRegisterInfo::
241 getEHExceptionRegister() const {
242   llvm_unreachable("What is the exception register");
243   return 0;
244 }
245 
246 unsigned MipsRegisterInfo::
247 getEHHandlerRegister() const {
248   llvm_unreachable("What is the exception handler register");
249   return 0;
250 }
251 
252 int MipsRegisterInfo::
253 getDwarfRegNum(unsigned RegNum, bool isEH) const {
254   llvm_unreachable("What is the dwarf register number");
255   return -1;
256 }
257 
258 #include "MipsGenRegisterInfo.inc"
259