1 //===-- MipsRegisterInfo.cpp - MIPS Register Information -== --------------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file contains the MIPS implementation of the TargetRegisterInfo class.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #define DEBUG_TYPE "mips-reg-info"
15 
16 #include "MipsRegisterInfo.h"
17 #include "Mips.h"
18 #include "MipsAnalyzeImmediate.h"
19 #include "MipsSubtarget.h"
20 #include "MipsMachineFunction.h"
21 #include "llvm/Constants.h"
22 #include "llvm/Type.h"
23 #include "llvm/Function.h"
24 #include "llvm/CodeGen/ValueTypes.h"
25 #include "llvm/CodeGen/MachineInstrBuilder.h"
26 #include "llvm/CodeGen/MachineFunction.h"
27 #include "llvm/CodeGen/MachineFrameInfo.h"
28 #include "llvm/Target/TargetFrameLowering.h"
29 #include "llvm/Target/TargetMachine.h"
30 #include "llvm/Target/TargetOptions.h"
31 #include "llvm/Target/TargetInstrInfo.h"
32 #include "llvm/Support/CommandLine.h"
33 #include "llvm/Support/Debug.h"
34 #include "llvm/Support/ErrorHandling.h"
35 #include "llvm/Support/raw_ostream.h"
36 #include "llvm/ADT/BitVector.h"
37 #include "llvm/ADT/STLExtras.h"
38 #include "llvm/Analysis/DebugInfo.h"
39 
40 #define GET_REGINFO_TARGET_DESC
41 #include "MipsGenRegisterInfo.inc"
42 
43 using namespace llvm;
44 
45 MipsRegisterInfo::MipsRegisterInfo(const MipsSubtarget &ST,
46                                    const TargetInstrInfo &tii)
47   : MipsGenRegisterInfo(Mips::RA), Subtarget(ST), TII(tii) {}
48 
49 unsigned MipsRegisterInfo::getPICCallReg() { return Mips::T9; }
50 
51 //===----------------------------------------------------------------------===//
52 // Callee Saved Registers methods
53 //===----------------------------------------------------------------------===//
54 
55 /// Mips Callee Saved Registers
56 const uint16_t* MipsRegisterInfo::
57 getCalleeSavedRegs(const MachineFunction *MF) const
58 {
59   if (Subtarget.isSingleFloat())
60     return CSR_SingleFloatOnly_SaveList;
61   else if (!Subtarget.hasMips64())
62     return CSR_O32_SaveList;
63   else if (Subtarget.isABI_N32())
64     return CSR_N32_SaveList;
65 
66   assert(Subtarget.isABI_N64());
67   return CSR_N64_SaveList;
68 }
69 
70 const uint32_t*
71 MipsRegisterInfo::getCallPreservedMask(CallingConv::ID) const
72 {
73   if (Subtarget.isSingleFloat())
74     return CSR_SingleFloatOnly_RegMask;
75   else if (!Subtarget.hasMips64())
76     return CSR_O32_RegMask;
77   else if (Subtarget.isABI_N32())
78     return CSR_N32_RegMask;
79 
80   assert(Subtarget.isABI_N64());
81   return CSR_N64_RegMask;
82 }
83 
84 BitVector MipsRegisterInfo::
85 getReservedRegs(const MachineFunction &MF) const {
86   static const uint16_t ReservedCPURegs[] = {
87     Mips::ZERO, Mips::AT, Mips::K0, Mips::K1,
88     Mips::SP, Mips::FP, Mips::RA
89   };
90 
91   static const uint16_t ReservedCPU64Regs[] = {
92     Mips::ZERO_64, Mips::AT_64, Mips::K0_64, Mips::K1_64,
93     Mips::SP_64, Mips::FP_64, Mips::RA_64
94   };
95 
96   BitVector Reserved(getNumRegs());
97   typedef TargetRegisterClass::const_iterator RegIter;
98 
99   for (unsigned I = 0; I < array_lengthof(ReservedCPURegs); ++I)
100     Reserved.set(ReservedCPURegs[I]);
101 
102   if (Subtarget.hasMips64()) {
103     for (unsigned I = 0; I < array_lengthof(ReservedCPU64Regs); ++I)
104       Reserved.set(ReservedCPU64Regs[I]);
105 
106     // Reserve all registers in AFGR64.
107     for (RegIter Reg = Mips::AFGR64RegClass.begin(),
108          EReg = Mips::AFGR64RegClass.end(); Reg != EReg; ++Reg)
109       Reserved.set(*Reg);
110   } else {
111     // Reserve all registers in CPU64Regs & FGR64.
112     for (RegIter Reg = Mips::CPU64RegsRegClass.begin(),
113          EReg = Mips::CPU64RegsRegClass.end(); Reg != EReg; ++Reg)
114       Reserved.set(*Reg);
115 
116     for (RegIter Reg = Mips::FGR64RegClass.begin(),
117          EReg = Mips::FGR64RegClass.end(); Reg != EReg; ++Reg)
118       Reserved.set(*Reg);
119   }
120 
121   // If GP is dedicated as a global base register, reserve it.
122   if (MF.getInfo<MipsFunctionInfo>()->globalBaseRegFixed()) {
123     Reserved.set(Mips::GP);
124     Reserved.set(Mips::GP_64);
125   }
126 
127   // Reserve hardware registers.
128   Reserved.set(Mips::HWR29);
129   Reserved.set(Mips::HWR29_64);
130 
131   return Reserved;
132 }
133 
134 bool
135 MipsRegisterInfo::requiresRegisterScavenging(const MachineFunction &MF) const {
136   return true;
137 }
138 
139 bool
140 MipsRegisterInfo::trackLivenessAfterRegAlloc(const MachineFunction &MF) const {
141   return true;
142 }
143 
144 // This function eliminate ADJCALLSTACKDOWN,
145 // ADJCALLSTACKUP pseudo instructions
146 void MipsRegisterInfo::
147 eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
148                               MachineBasicBlock::iterator I) const {
149   // Simply discard ADJCALLSTACKDOWN, ADJCALLSTACKUP instructions.
150   MBB.erase(I);
151 }
152 
153 // FrameIndex represent objects inside a abstract stack.
154 // We must replace FrameIndex with an stack/frame pointer
155 // direct reference.
156 void MipsRegisterInfo::
157 eliminateFrameIndex(MachineBasicBlock::iterator II, int SPAdj,
158                     RegScavenger *RS) const {
159   MachineInstr &MI = *II;
160   MachineFunction &MF = *MI.getParent()->getParent();
161   MachineFrameInfo *MFI = MF.getFrameInfo();
162   MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
163 
164   unsigned i = 0;
165   while (!MI.getOperand(i).isFI()) {
166     ++i;
167     assert(i < MI.getNumOperands() &&
168            "Instr doesn't have FrameIndex operand!");
169   }
170 
171   DEBUG(errs() << "\nFunction : " << MF.getFunction()->getName() << "\n";
172         errs() << "<--------->\n" << MI);
173 
174   int FrameIndex = MI.getOperand(i).getIndex();
175   uint64_t stackSize = MF.getFrameInfo()->getStackSize();
176   int64_t spOffset = MF.getFrameInfo()->getObjectOffset(FrameIndex);
177 
178   DEBUG(errs() << "FrameIndex : " << FrameIndex << "\n"
179                << "spOffset   : " << spOffset << "\n"
180                << "stackSize  : " << stackSize << "\n");
181 
182   const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo();
183   int MinCSFI = 0;
184   int MaxCSFI = -1;
185 
186   if (CSI.size()) {
187     MinCSFI = CSI[0].getFrameIdx();
188     MaxCSFI = CSI[CSI.size() - 1].getFrameIdx();
189   }
190 
191   // The following stack frame objects are always referenced relative to $sp:
192   //  1. Outgoing arguments.
193   //  2. Pointer to dynamically allocated stack space.
194   //  3. Locations for callee-saved registers.
195   // Everything else is referenced relative to whatever register
196   // getFrameRegister() returns.
197   unsigned FrameReg;
198 
199   if (MipsFI->isOutArgFI(FrameIndex) || MipsFI->isDynAllocFI(FrameIndex) ||
200       (FrameIndex >= MinCSFI && FrameIndex <= MaxCSFI))
201     FrameReg = Subtarget.isABI_N64() ? Mips::SP_64 : Mips::SP;
202   else
203     FrameReg = getFrameRegister(MF);
204 
205   // Calculate final offset.
206   // - There is no need to change the offset if the frame object is one of the
207   //   following: an outgoing argument, pointer to a dynamically allocated
208   //   stack space or a $gp restore location,
209   // - If the frame object is any of the following, its offset must be adjusted
210   //   by adding the size of the stack:
211   //   incoming argument, callee-saved register location or local variable.
212   int64_t Offset;
213 
214   if (MipsFI->isOutArgFI(FrameIndex) || MipsFI->isGPFI(FrameIndex) ||
215       MipsFI->isDynAllocFI(FrameIndex))
216     Offset = spOffset;
217   else
218     Offset = spOffset + (int64_t)stackSize;
219 
220   Offset    += MI.getOperand(i+1).getImm();
221 
222   DEBUG(errs() << "Offset     : " << Offset << "\n" << "<--------->\n");
223 
224   // If MI is not a debug value, make sure Offset fits in the 16-bit immediate
225   // field.
226   if (!MI.isDebugValue() && !isInt<16>(Offset)) {
227     MachineBasicBlock &MBB = *MI.getParent();
228     DebugLoc DL = II->getDebugLoc();
229     MipsAnalyzeImmediate AnalyzeImm;
230     unsigned Size = Subtarget.isABI_N64() ? 64 : 32;
231     unsigned LUi = Subtarget.isABI_N64() ? Mips::LUi64 : Mips::LUi;
232     unsigned ADDu = Subtarget.isABI_N64() ? Mips::DADDu : Mips::ADDu;
233     unsigned ZEROReg = Subtarget.isABI_N64() ? Mips::ZERO_64 : Mips::ZERO;
234     unsigned ATReg = Subtarget.isABI_N64() ? Mips::AT_64 : Mips::AT;
235     const MipsAnalyzeImmediate::InstSeq &Seq =
236       AnalyzeImm.Analyze(Offset, Size, true /* LastInstrIsADDiu */);
237     MipsAnalyzeImmediate::InstSeq::const_iterator Inst = Seq.begin();
238 
239     MipsFI->setEmitNOAT();
240 
241     // The first instruction can be a LUi, which is different from other
242     // instructions (ADDiu, ORI and SLL) in that it does not have a register
243     // operand.
244     if (Inst->Opc == LUi)
245       BuildMI(MBB, II, DL, TII.get(LUi), ATReg)
246         .addImm(SignExtend64<16>(Inst->ImmOpnd));
247     else
248       BuildMI(MBB, II, DL, TII.get(Inst->Opc), ATReg).addReg(ZEROReg)
249         .addImm(SignExtend64<16>(Inst->ImmOpnd));
250 
251     // Build the remaining instructions in Seq except for the last one.
252     for (++Inst; Inst != Seq.end() - 1; ++Inst)
253       BuildMI(MBB, II, DL, TII.get(Inst->Opc), ATReg).addReg(ATReg)
254         .addImm(SignExtend64<16>(Inst->ImmOpnd));
255 
256     BuildMI(MBB, II, DL, TII.get(ADDu), ATReg).addReg(FrameReg).addReg(ATReg);
257 
258     FrameReg = ATReg;
259     Offset = SignExtend64<16>(Inst->ImmOpnd);
260   }
261 
262   MI.getOperand(i).ChangeToRegister(FrameReg, false);
263   MI.getOperand(i+1).ChangeToImmediate(Offset);
264 }
265 
266 unsigned MipsRegisterInfo::
267 getFrameRegister(const MachineFunction &MF) const {
268   const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
269   bool IsN64 = Subtarget.isABI_N64();
270 
271   return TFI->hasFP(MF) ? (IsN64 ? Mips::FP_64 : Mips::FP) :
272                           (IsN64 ? Mips::SP_64 : Mips::SP);
273 }
274 
275 unsigned MipsRegisterInfo::
276 getEHExceptionRegister() const {
277   llvm_unreachable("What is the exception register");
278 }
279 
280 unsigned MipsRegisterInfo::
281 getEHHandlerRegister() const {
282   llvm_unreachable("What is the exception handler register");
283 }
284