1 //===- MipsRegisterBankInfo.cpp ---------------------------------*- C++ -*-===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 /// \file
10 /// This file implements the targeting of the RegisterBankInfo class for Mips.
11 /// \todo This should be generated by TableGen.
12 //===----------------------------------------------------------------------===//
13 
14 #include "MipsInstrInfo.h"
15 #include "MipsRegisterBankInfo.h"
16 #include "llvm/CodeGen/MachineRegisterInfo.h"
17 
18 #define GET_TARGET_REGBANK_IMPL
19 
20 #define DEBUG_TYPE "registerbankinfo"
21 
22 #include "MipsGenRegisterBank.inc"
23 
24 namespace llvm {
25 namespace Mips {
26 enum PartialMappingIdx {
27   PMI_GPR,
28   PMI_Min = PMI_GPR,
29 };
30 
31 RegisterBankInfo::PartialMapping PartMappings[]{
32     {0, 32, GPRBRegBank}
33 };
34 
35 enum ValueMappingIdx { InvalidIdx = 0, GPRIdx = 1 };
36 
37 RegisterBankInfo::ValueMapping ValueMappings[] = {
38     // invalid
39     {nullptr, 0},
40     // 3 operands in GPRs
41     {&PartMappings[PMI_GPR - PMI_Min], 1},
42     {&PartMappings[PMI_GPR - PMI_Min], 1},
43     {&PartMappings[PMI_GPR - PMI_Min], 1}};
44 
45 } // end namespace Mips
46 } // end namespace llvm
47 
48 using namespace llvm;
49 
50 MipsRegisterBankInfo::MipsRegisterBankInfo(const TargetRegisterInfo &TRI)
51     : MipsGenRegisterBankInfo() {}
52 
53 const RegisterBank &MipsRegisterBankInfo::getRegBankFromRegClass(
54     const TargetRegisterClass &RC) const {
55   using namespace Mips;
56 
57   switch (RC.getID()) {
58   case Mips::GPR32RegClassID:
59   case Mips::CPU16Regs_and_GPRMM16ZeroRegClassID:
60   case Mips::GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroRegClassID:
61     return getRegBank(Mips::GPRBRegBankID);
62   default:
63     llvm_unreachable("Register class not supported");
64   }
65 }
66 
67 const RegisterBankInfo::InstructionMapping &
68 MipsRegisterBankInfo::getInstrMapping(const MachineInstr &MI) const {
69 
70   unsigned Opc = MI.getOpcode();
71 
72   const RegisterBankInfo::InstructionMapping &Mapping = getInstrMappingImpl(MI);
73   if (Mapping.isValid())
74     return Mapping;
75 
76   using namespace TargetOpcode;
77 
78   unsigned NumOperands = MI.getNumOperands();
79   const ValueMapping *OperandsMapping = &Mips::ValueMappings[Mips::GPRIdx];
80 
81   switch (Opc) {
82   case G_ADD:
83     OperandsMapping = &Mips::ValueMappings[Mips::GPRIdx];
84     break;
85   default:
86     return getInvalidInstructionMapping();
87   }
88 
89   return getInstructionMapping(DefaultMappingID, /*Cost=*/1, OperandsMapping,
90                                NumOperands);
91 }
92