1//===- MipsMSAInstrInfo.td - MSA ASE instructions -*- tablegen ------------*-=// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file describes Mips MSA ASE instructions. 11// 12//===----------------------------------------------------------------------===// 13 14def SDT_MipsVecCond : SDTypeProfile<1, 1, [SDTCisInt<0>, SDTCisVec<1>]>; 15def SDT_VSetCC : SDTypeProfile<1, 3, [SDTCisInt<0>, 16 SDTCisInt<1>, 17 SDTCisSameAs<1, 2>, 18 SDTCisVT<3, OtherVT>]>; 19def SDT_VFSetCC : SDTypeProfile<1, 3, [SDTCisInt<0>, 20 SDTCisFP<1>, 21 SDTCisSameAs<1, 2>, 22 SDTCisVT<3, OtherVT>]>; 23def SDT_VSHF : SDTypeProfile<1, 3, [SDTCisInt<0>, SDTCisVec<0>, 24 SDTCisInt<1>, SDTCisVec<1>, 25 SDTCisSameAs<0, 2>, SDTCisSameAs<2, 3>]>; 26def SDT_SHF : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisVec<0>, 27 SDTCisVT<1, i32>, SDTCisSameAs<0, 2>]>; 28def SDT_ILV : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisVec<0>, 29 SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>]>; 30def SDT_INSVE : SDTypeProfile<1, 4, [SDTCisVec<0>, SDTCisSameAs<0, 1>, 31 SDTCisVT<2, i32>, SDTCisSameAs<0, 3>, 32 SDTCisVT<4, i32>]>; 33 34def MipsVAllNonZero : SDNode<"MipsISD::VALL_NONZERO", SDT_MipsVecCond>; 35def MipsVAnyNonZero : SDNode<"MipsISD::VANY_NONZERO", SDT_MipsVecCond>; 36def MipsVAllZero : SDNode<"MipsISD::VALL_ZERO", SDT_MipsVecCond>; 37def MipsVAnyZero : SDNode<"MipsISD::VANY_ZERO", SDT_MipsVecCond>; 38def MipsVSMax : SDNode<"MipsISD::VSMAX", SDTIntBinOp, 39 [SDNPCommutative, SDNPAssociative]>; 40def MipsVSMin : SDNode<"MipsISD::VSMIN", SDTIntBinOp, 41 [SDNPCommutative, SDNPAssociative]>; 42def MipsVUMax : SDNode<"MipsISD::VUMAX", SDTIntBinOp, 43 [SDNPCommutative, SDNPAssociative]>; 44def MipsVUMin : SDNode<"MipsISD::VUMIN", SDTIntBinOp, 45 [SDNPCommutative, SDNPAssociative]>; 46def MipsVNOR : SDNode<"MipsISD::VNOR", SDTIntBinOp, 47 [SDNPCommutative, SDNPAssociative]>; 48def MipsVSHF : SDNode<"MipsISD::VSHF", SDT_VSHF>; 49def MipsSHF : SDNode<"MipsISD::SHF", SDT_SHF>; 50def MipsILVEV : SDNode<"MipsISD::ILVEV", SDT_ILV>; 51def MipsILVOD : SDNode<"MipsISD::ILVOD", SDT_ILV>; 52def MipsILVL : SDNode<"MipsISD::ILVL", SDT_ILV>; 53def MipsILVR : SDNode<"MipsISD::ILVR", SDT_ILV>; 54def MipsPCKEV : SDNode<"MipsISD::PCKEV", SDT_ILV>; 55def MipsPCKOD : SDNode<"MipsISD::PCKOD", SDT_ILV>; 56def MipsINSVE : SDNode<"MipsISD::INSVE", SDT_INSVE>; 57 58def vsetcc : SDNode<"ISD::SETCC", SDT_VSetCC>; 59def vfsetcc : SDNode<"ISD::SETCC", SDT_VFSetCC>; 60 61def MipsVExtractSExt : SDNode<"MipsISD::VEXTRACT_SEXT_ELT", 62 SDTypeProfile<1, 3, [SDTCisPtrTy<2>]>, []>; 63def MipsVExtractZExt : SDNode<"MipsISD::VEXTRACT_ZEXT_ELT", 64 SDTypeProfile<1, 3, [SDTCisPtrTy<2>]>, []>; 65 66def immZExt1Ptr : ImmLeaf<iPTR, [{return isUInt<1>(Imm);}]>; 67def immZExt2Ptr : ImmLeaf<iPTR, [{return isUInt<2>(Imm);}]>; 68def immZExt3Ptr : ImmLeaf<iPTR, [{return isUInt<3>(Imm);}]>; 69def immZExt4Ptr : ImmLeaf<iPTR, [{return isUInt<4>(Imm);}]>; 70 71// Operands 72 73def immZExt2Lsa : ImmLeaf<i32, [{return isUInt<2>(Imm - 1);}]>; 74 75// Pattern fragments 76def vextract_sext_i8 : PatFrag<(ops node:$vec, node:$idx), 77 (MipsVExtractSExt node:$vec, node:$idx, i8)>; 78def vextract_sext_i16 : PatFrag<(ops node:$vec, node:$idx), 79 (MipsVExtractSExt node:$vec, node:$idx, i16)>; 80def vextract_sext_i32 : PatFrag<(ops node:$vec, node:$idx), 81 (MipsVExtractSExt node:$vec, node:$idx, i32)>; 82def vextract_sext_i64 : PatFrag<(ops node:$vec, node:$idx), 83 (MipsVExtractSExt node:$vec, node:$idx, i64)>; 84 85def vextract_zext_i8 : PatFrag<(ops node:$vec, node:$idx), 86 (MipsVExtractZExt node:$vec, node:$idx, i8)>; 87def vextract_zext_i16 : PatFrag<(ops node:$vec, node:$idx), 88 (MipsVExtractZExt node:$vec, node:$idx, i16)>; 89def vextract_zext_i32 : PatFrag<(ops node:$vec, node:$idx), 90 (MipsVExtractZExt node:$vec, node:$idx, i32)>; 91def vextract_zext_i64 : PatFrag<(ops node:$vec, node:$idx), 92 (MipsVExtractZExt node:$vec, node:$idx, i64)>; 93 94def vinsert_v16i8 : PatFrag<(ops node:$vec, node:$val, node:$idx), 95 (v16i8 (vector_insert node:$vec, node:$val, node:$idx))>; 96def vinsert_v8i16 : PatFrag<(ops node:$vec, node:$val, node:$idx), 97 (v8i16 (vector_insert node:$vec, node:$val, node:$idx))>; 98def vinsert_v4i32 : PatFrag<(ops node:$vec, node:$val, node:$idx), 99 (v4i32 (vector_insert node:$vec, node:$val, node:$idx))>; 100def vinsert_v2i64 : PatFrag<(ops node:$vec, node:$val, node:$idx), 101 (v2i64 (vector_insert node:$vec, node:$val, node:$idx))>; 102 103def insve_v16i8 : PatFrag<(ops node:$v1, node:$i1, node:$v2, node:$i2), 104 (v16i8 (MipsINSVE node:$v1, node:$i1, node:$v2, node:$i2))>; 105def insve_v8i16 : PatFrag<(ops node:$v1, node:$i1, node:$v2, node:$i2), 106 (v8i16 (MipsINSVE node:$v1, node:$i1, node:$v2, node:$i2))>; 107def insve_v4i32 : PatFrag<(ops node:$v1, node:$i1, node:$v2, node:$i2), 108 (v4i32 (MipsINSVE node:$v1, node:$i1, node:$v2, node:$i2))>; 109def insve_v2i64 : PatFrag<(ops node:$v1, node:$i1, node:$v2, node:$i2), 110 (v2i64 (MipsINSVE node:$v1, node:$i1, node:$v2, node:$i2))>; 111 112class vfsetcc_type<ValueType ResTy, ValueType OpTy, CondCode CC> : 113 PatFrag<(ops node:$lhs, node:$rhs), 114 (ResTy (vfsetcc (OpTy node:$lhs), (OpTy node:$rhs), CC))>; 115 116// ISD::SETFALSE cannot occur 117def vfsetoeq_v4f32 : vfsetcc_type<v4i32, v4f32, SETOEQ>; 118def vfsetoeq_v2f64 : vfsetcc_type<v2i64, v2f64, SETOEQ>; 119def vfsetoge_v4f32 : vfsetcc_type<v4i32, v4f32, SETOGE>; 120def vfsetoge_v2f64 : vfsetcc_type<v2i64, v2f64, SETOGE>; 121def vfsetogt_v4f32 : vfsetcc_type<v4i32, v4f32, SETOGT>; 122def vfsetogt_v2f64 : vfsetcc_type<v2i64, v2f64, SETOGT>; 123def vfsetole_v4f32 : vfsetcc_type<v4i32, v4f32, SETOLE>; 124def vfsetole_v2f64 : vfsetcc_type<v2i64, v2f64, SETOLE>; 125def vfsetolt_v4f32 : vfsetcc_type<v4i32, v4f32, SETOLT>; 126def vfsetolt_v2f64 : vfsetcc_type<v2i64, v2f64, SETOLT>; 127def vfsetone_v4f32 : vfsetcc_type<v4i32, v4f32, SETONE>; 128def vfsetone_v2f64 : vfsetcc_type<v2i64, v2f64, SETONE>; 129def vfsetord_v4f32 : vfsetcc_type<v4i32, v4f32, SETO>; 130def vfsetord_v2f64 : vfsetcc_type<v2i64, v2f64, SETO>; 131def vfsetun_v4f32 : vfsetcc_type<v4i32, v4f32, SETUO>; 132def vfsetun_v2f64 : vfsetcc_type<v2i64, v2f64, SETUO>; 133def vfsetueq_v4f32 : vfsetcc_type<v4i32, v4f32, SETUEQ>; 134def vfsetueq_v2f64 : vfsetcc_type<v2i64, v2f64, SETUEQ>; 135def vfsetuge_v4f32 : vfsetcc_type<v4i32, v4f32, SETUGE>; 136def vfsetuge_v2f64 : vfsetcc_type<v2i64, v2f64, SETUGE>; 137def vfsetugt_v4f32 : vfsetcc_type<v4i32, v4f32, SETUGT>; 138def vfsetugt_v2f64 : vfsetcc_type<v2i64, v2f64, SETUGT>; 139def vfsetule_v4f32 : vfsetcc_type<v4i32, v4f32, SETULE>; 140def vfsetule_v2f64 : vfsetcc_type<v2i64, v2f64, SETULE>; 141def vfsetult_v4f32 : vfsetcc_type<v4i32, v4f32, SETULT>; 142def vfsetult_v2f64 : vfsetcc_type<v2i64, v2f64, SETULT>; 143def vfsetune_v4f32 : vfsetcc_type<v4i32, v4f32, SETUNE>; 144def vfsetune_v2f64 : vfsetcc_type<v2i64, v2f64, SETUNE>; 145// ISD::SETTRUE cannot occur 146// ISD::SETFALSE2 cannot occur 147// ISD::SETTRUE2 cannot occur 148 149class vsetcc_type<ValueType ResTy, CondCode CC> : 150 PatFrag<(ops node:$lhs, node:$rhs), 151 (ResTy (vsetcc node:$lhs, node:$rhs, CC))>; 152 153def vseteq_v16i8 : vsetcc_type<v16i8, SETEQ>; 154def vseteq_v8i16 : vsetcc_type<v8i16, SETEQ>; 155def vseteq_v4i32 : vsetcc_type<v4i32, SETEQ>; 156def vseteq_v2i64 : vsetcc_type<v2i64, SETEQ>; 157def vsetle_v16i8 : vsetcc_type<v16i8, SETLE>; 158def vsetle_v8i16 : vsetcc_type<v8i16, SETLE>; 159def vsetle_v4i32 : vsetcc_type<v4i32, SETLE>; 160def vsetle_v2i64 : vsetcc_type<v2i64, SETLE>; 161def vsetlt_v16i8 : vsetcc_type<v16i8, SETLT>; 162def vsetlt_v8i16 : vsetcc_type<v8i16, SETLT>; 163def vsetlt_v4i32 : vsetcc_type<v4i32, SETLT>; 164def vsetlt_v2i64 : vsetcc_type<v2i64, SETLT>; 165def vsetule_v16i8 : vsetcc_type<v16i8, SETULE>; 166def vsetule_v8i16 : vsetcc_type<v8i16, SETULE>; 167def vsetule_v4i32 : vsetcc_type<v4i32, SETULE>; 168def vsetule_v2i64 : vsetcc_type<v2i64, SETULE>; 169def vsetult_v16i8 : vsetcc_type<v16i8, SETULT>; 170def vsetult_v8i16 : vsetcc_type<v8i16, SETULT>; 171def vsetult_v4i32 : vsetcc_type<v4i32, SETULT>; 172def vsetult_v2i64 : vsetcc_type<v2i64, SETULT>; 173 174def vsplati8 : PatFrag<(ops node:$e0), 175 (v16i8 (build_vector node:$e0, node:$e0, 176 node:$e0, node:$e0, 177 node:$e0, node:$e0, 178 node:$e0, node:$e0, 179 node:$e0, node:$e0, 180 node:$e0, node:$e0, 181 node:$e0, node:$e0, 182 node:$e0, node:$e0))>; 183def vsplati16 : PatFrag<(ops node:$e0), 184 (v8i16 (build_vector node:$e0, node:$e0, 185 node:$e0, node:$e0, 186 node:$e0, node:$e0, 187 node:$e0, node:$e0))>; 188def vsplati32 : PatFrag<(ops node:$e0), 189 (v4i32 (build_vector node:$e0, node:$e0, 190 node:$e0, node:$e0))>; 191def vsplati64 : PatFrag<(ops node:$e0), 192 (v2i64 (build_vector node:$e0, node:$e0))>; 193def vsplatf32 : PatFrag<(ops node:$e0), 194 (v4f32 (build_vector node:$e0, node:$e0, 195 node:$e0, node:$e0))>; 196def vsplatf64 : PatFrag<(ops node:$e0), 197 (v2f64 (build_vector node:$e0, node:$e0))>; 198 199def vsplati8_elt : PatFrag<(ops node:$v, node:$i), 200 (MipsVSHF (vsplati8 node:$i), node:$v, node:$v)>; 201def vsplati16_elt : PatFrag<(ops node:$v, node:$i), 202 (MipsVSHF (vsplati16 node:$i), node:$v, node:$v)>; 203def vsplati32_elt : PatFrag<(ops node:$v, node:$i), 204 (MipsVSHF (vsplati32 node:$i), node:$v, node:$v)>; 205def vsplati64_elt : PatFrag<(ops node:$v, node:$i), 206 (MipsVSHF (vsplati64 node:$i), node:$v, node:$v)>; 207 208class SplatPatLeaf<Operand opclass, dag frag, code pred = [{}], 209 SDNodeXForm xform = NOOP_SDNodeXForm> 210 : PatLeaf<frag, pred, xform> { 211 Operand OpClass = opclass; 212} 213 214class SplatComplexPattern<Operand opclass, ValueType ty, int numops, string fn, 215 list<SDNode> roots = [], 216 list<SDNodeProperty> props = []> : 217 ComplexPattern<ty, numops, fn, roots, props> { 218 Operand OpClass = opclass; 219} 220 221def vsplati8_uimm3 : SplatComplexPattern<vsplat_uimm3, v16i8, 1, 222 "selectVSplatUimm3", 223 [build_vector, bitconvert]>; 224 225def vsplati8_uimm4 : SplatComplexPattern<vsplat_uimm4, v16i8, 1, 226 "selectVSplatUimm4", 227 [build_vector, bitconvert]>; 228 229def vsplati8_uimm5 : SplatComplexPattern<vsplat_uimm5, v16i8, 1, 230 "selectVSplatUimm5", 231 [build_vector, bitconvert]>; 232 233def vsplati8_uimm8 : SplatComplexPattern<vsplat_uimm8, v16i8, 1, 234 "selectVSplatUimm8", 235 [build_vector, bitconvert]>; 236 237def vsplati8_simm5 : SplatComplexPattern<vsplat_simm5, v16i8, 1, 238 "selectVSplatSimm5", 239 [build_vector, bitconvert]>; 240 241def vsplati16_uimm3 : SplatComplexPattern<vsplat_uimm3, v8i16, 1, 242 "selectVSplatUimm3", 243 [build_vector, bitconvert]>; 244 245def vsplati16_uimm4 : SplatComplexPattern<vsplat_uimm4, v8i16, 1, 246 "selectVSplatUimm4", 247 [build_vector, bitconvert]>; 248 249def vsplati16_uimm5 : SplatComplexPattern<vsplat_uimm5, v8i16, 1, 250 "selectVSplatUimm5", 251 [build_vector, bitconvert]>; 252 253def vsplati16_simm5 : SplatComplexPattern<vsplat_simm5, v8i16, 1, 254 "selectVSplatSimm5", 255 [build_vector, bitconvert]>; 256 257def vsplati32_uimm2 : SplatComplexPattern<vsplat_uimm2, v4i32, 1, 258 "selectVSplatUimm2", 259 [build_vector, bitconvert]>; 260 261def vsplati32_uimm5 : SplatComplexPattern<vsplat_uimm5, v4i32, 1, 262 "selectVSplatUimm5", 263 [build_vector, bitconvert]>; 264 265def vsplati32_simm5 : SplatComplexPattern<vsplat_simm5, v4i32, 1, 266 "selectVSplatSimm5", 267 [build_vector, bitconvert]>; 268 269def vsplati64_uimm1 : SplatComplexPattern<vsplat_uimm1, v2i64, 1, 270 "selectVSplatUimm1", 271 [build_vector, bitconvert]>; 272 273def vsplati64_uimm5 : SplatComplexPattern<vsplat_uimm5, v2i64, 1, 274 "selectVSplatUimm5", 275 [build_vector, bitconvert]>; 276 277def vsplati64_uimm6 : SplatComplexPattern<vsplat_uimm6, v2i64, 1, 278 "selectVSplatUimm6", 279 [build_vector, bitconvert]>; 280 281def vsplati64_simm5 : SplatComplexPattern<vsplat_simm5, v2i64, 1, 282 "selectVSplatSimm5", 283 [build_vector, bitconvert]>; 284 285// Any build_vector that is a constant splat with a value that is an exact 286// power of 2 287def vsplat_uimm_pow2 : ComplexPattern<vAny, 1, "selectVSplatUimmPow2", 288 [build_vector, bitconvert]>; 289 290// Any build_vector that is a constant splat with a value that is the bitwise 291// inverse of an exact power of 2 292def vsplat_uimm_inv_pow2 : ComplexPattern<vAny, 1, "selectVSplatUimmInvPow2", 293 [build_vector, bitconvert]>; 294 295// Any build_vector that is a constant splat with only a consecutive sequence 296// of left-most bits set. 297def vsplat_maskl_bits_uimm3 298 : SplatComplexPattern<vsplat_uimm3, vAny, 1, "selectVSplatMaskL", 299 [build_vector, bitconvert]>; 300def vsplat_maskl_bits_uimm4 301 : SplatComplexPattern<vsplat_uimm4, vAny, 1, "selectVSplatMaskL", 302 [build_vector, bitconvert]>; 303def vsplat_maskl_bits_uimm5 304 : SplatComplexPattern<vsplat_uimm5, vAny, 1, "selectVSplatMaskL", 305 [build_vector, bitconvert]>; 306def vsplat_maskl_bits_uimm6 307 : SplatComplexPattern<vsplat_uimm6, vAny, 1, "selectVSplatMaskL", 308 [build_vector, bitconvert]>; 309 310// Any build_vector that is a constant splat with only a consecutive sequence 311// of right-most bits set. 312def vsplat_maskr_bits_uimm3 313 : SplatComplexPattern<vsplat_uimm3, vAny, 1, "selectVSplatMaskR", 314 [build_vector, bitconvert]>; 315def vsplat_maskr_bits_uimm4 316 : SplatComplexPattern<vsplat_uimm4, vAny, 1, "selectVSplatMaskR", 317 [build_vector, bitconvert]>; 318def vsplat_maskr_bits_uimm5 319 : SplatComplexPattern<vsplat_uimm5, vAny, 1, "selectVSplatMaskR", 320 [build_vector, bitconvert]>; 321def vsplat_maskr_bits_uimm6 322 : SplatComplexPattern<vsplat_uimm6, vAny, 1, "selectVSplatMaskR", 323 [build_vector, bitconvert]>; 324 325// Any build_vector that is a constant splat with a value that equals 1 326// FIXME: These should be a ComplexPattern but we can't use them because the 327// ISel generator requires the uses to have a name, but providing a name 328// causes other errors ("used in pattern but not operand list") 329def vsplat_imm_eq_1 : PatLeaf<(build_vector), [{ 330 APInt Imm; 331 EVT EltTy = N->getValueType(0).getVectorElementType(); 332 333 return selectVSplat(N, Imm, EltTy.getSizeInBits()) && 334 Imm.getBitWidth() == EltTy.getSizeInBits() && Imm == 1; 335}]>; 336 337def vsplati64_imm_eq_1 : PatLeaf<(bitconvert (v4i32 (build_vector))), [{ 338 APInt Imm; 339 SDNode *BV = N->getOperand(0).getNode(); 340 EVT EltTy = N->getValueType(0).getVectorElementType(); 341 342 return selectVSplat(BV, Imm, EltTy.getSizeInBits()) && 343 Imm.getBitWidth() == EltTy.getSizeInBits() && Imm == 1; 344}]>; 345 346def vbclr_b : PatFrag<(ops node:$ws, node:$wt), 347 (and node:$ws, (xor (shl vsplat_imm_eq_1, node:$wt), 348 immAllOnesV))>; 349def vbclr_h : PatFrag<(ops node:$ws, node:$wt), 350 (and node:$ws, (xor (shl vsplat_imm_eq_1, node:$wt), 351 immAllOnesV))>; 352def vbclr_w : PatFrag<(ops node:$ws, node:$wt), 353 (and node:$ws, (xor (shl vsplat_imm_eq_1, node:$wt), 354 immAllOnesV))>; 355def vbclr_d : PatFrag<(ops node:$ws, node:$wt), 356 (and node:$ws, (xor (shl (v2i64 vsplati64_imm_eq_1), 357 node:$wt), 358 (bitconvert (v4i32 immAllOnesV))))>; 359 360def vbneg_b : PatFrag<(ops node:$ws, node:$wt), 361 (xor node:$ws, (shl vsplat_imm_eq_1, node:$wt))>; 362def vbneg_h : PatFrag<(ops node:$ws, node:$wt), 363 (xor node:$ws, (shl vsplat_imm_eq_1, node:$wt))>; 364def vbneg_w : PatFrag<(ops node:$ws, node:$wt), 365 (xor node:$ws, (shl vsplat_imm_eq_1, node:$wt))>; 366def vbneg_d : PatFrag<(ops node:$ws, node:$wt), 367 (xor node:$ws, (shl (v2i64 vsplati64_imm_eq_1), 368 node:$wt))>; 369 370def vbset_b : PatFrag<(ops node:$ws, node:$wt), 371 (or node:$ws, (shl vsplat_imm_eq_1, node:$wt))>; 372def vbset_h : PatFrag<(ops node:$ws, node:$wt), 373 (or node:$ws, (shl vsplat_imm_eq_1, node:$wt))>; 374def vbset_w : PatFrag<(ops node:$ws, node:$wt), 375 (or node:$ws, (shl vsplat_imm_eq_1, node:$wt))>; 376def vbset_d : PatFrag<(ops node:$ws, node:$wt), 377 (or node:$ws, (shl (v2i64 vsplati64_imm_eq_1), 378 node:$wt))>; 379 380def fms : PatFrag<(ops node:$wd, node:$ws, node:$wt), 381 (fsub node:$wd, (fmul node:$ws, node:$wt))>; 382 383def muladd : PatFrag<(ops node:$wd, node:$ws, node:$wt), 384 (add node:$wd, (mul node:$ws, node:$wt))>; 385 386def mulsub : PatFrag<(ops node:$wd, node:$ws, node:$wt), 387 (sub node:$wd, (mul node:$ws, node:$wt))>; 388 389def mul_fexp2 : PatFrag<(ops node:$ws, node:$wt), 390 (fmul node:$ws, (fexp2 node:$wt))>; 391 392// Instruction encoding. 393class ADD_A_B_ENC : MSA_3R_FMT<0b000, 0b00, 0b010000>; 394class ADD_A_H_ENC : MSA_3R_FMT<0b000, 0b01, 0b010000>; 395class ADD_A_W_ENC : MSA_3R_FMT<0b000, 0b10, 0b010000>; 396class ADD_A_D_ENC : MSA_3R_FMT<0b000, 0b11, 0b010000>; 397 398class ADDS_A_B_ENC : MSA_3R_FMT<0b001, 0b00, 0b010000>; 399class ADDS_A_H_ENC : MSA_3R_FMT<0b001, 0b01, 0b010000>; 400class ADDS_A_W_ENC : MSA_3R_FMT<0b001, 0b10, 0b010000>; 401class ADDS_A_D_ENC : MSA_3R_FMT<0b001, 0b11, 0b010000>; 402 403class ADDS_S_B_ENC : MSA_3R_FMT<0b010, 0b00, 0b010000>; 404class ADDS_S_H_ENC : MSA_3R_FMT<0b010, 0b01, 0b010000>; 405class ADDS_S_W_ENC : MSA_3R_FMT<0b010, 0b10, 0b010000>; 406class ADDS_S_D_ENC : MSA_3R_FMT<0b010, 0b11, 0b010000>; 407 408class ADDS_U_B_ENC : MSA_3R_FMT<0b011, 0b00, 0b010000>; 409class ADDS_U_H_ENC : MSA_3R_FMT<0b011, 0b01, 0b010000>; 410class ADDS_U_W_ENC : MSA_3R_FMT<0b011, 0b10, 0b010000>; 411class ADDS_U_D_ENC : MSA_3R_FMT<0b011, 0b11, 0b010000>; 412 413class ADDV_B_ENC : MSA_3R_FMT<0b000, 0b00, 0b001110>; 414class ADDV_H_ENC : MSA_3R_FMT<0b000, 0b01, 0b001110>; 415class ADDV_W_ENC : MSA_3R_FMT<0b000, 0b10, 0b001110>; 416class ADDV_D_ENC : MSA_3R_FMT<0b000, 0b11, 0b001110>; 417 418class ADDVI_B_ENC : MSA_I5_FMT<0b000, 0b00, 0b000110>; 419class ADDVI_H_ENC : MSA_I5_FMT<0b000, 0b01, 0b000110>; 420class ADDVI_W_ENC : MSA_I5_FMT<0b000, 0b10, 0b000110>; 421class ADDVI_D_ENC : MSA_I5_FMT<0b000, 0b11, 0b000110>; 422 423class AND_V_ENC : MSA_VEC_FMT<0b00000, 0b011110>; 424 425class ANDI_B_ENC : MSA_I8_FMT<0b00, 0b000000>; 426 427class ASUB_S_B_ENC : MSA_3R_FMT<0b100, 0b00, 0b010001>; 428class ASUB_S_H_ENC : MSA_3R_FMT<0b100, 0b01, 0b010001>; 429class ASUB_S_W_ENC : MSA_3R_FMT<0b100, 0b10, 0b010001>; 430class ASUB_S_D_ENC : MSA_3R_FMT<0b100, 0b11, 0b010001>; 431 432class ASUB_U_B_ENC : MSA_3R_FMT<0b101, 0b00, 0b010001>; 433class ASUB_U_H_ENC : MSA_3R_FMT<0b101, 0b01, 0b010001>; 434class ASUB_U_W_ENC : MSA_3R_FMT<0b101, 0b10, 0b010001>; 435class ASUB_U_D_ENC : MSA_3R_FMT<0b101, 0b11, 0b010001>; 436 437class AVE_S_B_ENC : MSA_3R_FMT<0b100, 0b00, 0b010000>; 438class AVE_S_H_ENC : MSA_3R_FMT<0b100, 0b01, 0b010000>; 439class AVE_S_W_ENC : MSA_3R_FMT<0b100, 0b10, 0b010000>; 440class AVE_S_D_ENC : MSA_3R_FMT<0b100, 0b11, 0b010000>; 441 442class AVE_U_B_ENC : MSA_3R_FMT<0b101, 0b00, 0b010000>; 443class AVE_U_H_ENC : MSA_3R_FMT<0b101, 0b01, 0b010000>; 444class AVE_U_W_ENC : MSA_3R_FMT<0b101, 0b10, 0b010000>; 445class AVE_U_D_ENC : MSA_3R_FMT<0b101, 0b11, 0b010000>; 446 447class AVER_S_B_ENC : MSA_3R_FMT<0b110, 0b00, 0b010000>; 448class AVER_S_H_ENC : MSA_3R_FMT<0b110, 0b01, 0b010000>; 449class AVER_S_W_ENC : MSA_3R_FMT<0b110, 0b10, 0b010000>; 450class AVER_S_D_ENC : MSA_3R_FMT<0b110, 0b11, 0b010000>; 451 452class AVER_U_B_ENC : MSA_3R_FMT<0b111, 0b00, 0b010000>; 453class AVER_U_H_ENC : MSA_3R_FMT<0b111, 0b01, 0b010000>; 454class AVER_U_W_ENC : MSA_3R_FMT<0b111, 0b10, 0b010000>; 455class AVER_U_D_ENC : MSA_3R_FMT<0b111, 0b11, 0b010000>; 456 457class BCLR_B_ENC : MSA_3R_FMT<0b011, 0b00, 0b001101>; 458class BCLR_H_ENC : MSA_3R_FMT<0b011, 0b01, 0b001101>; 459class BCLR_W_ENC : MSA_3R_FMT<0b011, 0b10, 0b001101>; 460class BCLR_D_ENC : MSA_3R_FMT<0b011, 0b11, 0b001101>; 461 462class BCLRI_B_ENC : MSA_BIT_B_FMT<0b011, 0b001001>; 463class BCLRI_H_ENC : MSA_BIT_H_FMT<0b011, 0b001001>; 464class BCLRI_W_ENC : MSA_BIT_W_FMT<0b011, 0b001001>; 465class BCLRI_D_ENC : MSA_BIT_D_FMT<0b011, 0b001001>; 466 467class BINSL_B_ENC : MSA_3R_FMT<0b110, 0b00, 0b001101>; 468class BINSL_H_ENC : MSA_3R_FMT<0b110, 0b01, 0b001101>; 469class BINSL_W_ENC : MSA_3R_FMT<0b110, 0b10, 0b001101>; 470class BINSL_D_ENC : MSA_3R_FMT<0b110, 0b11, 0b001101>; 471 472class BINSLI_B_ENC : MSA_BIT_B_FMT<0b110, 0b001001>; 473class BINSLI_H_ENC : MSA_BIT_H_FMT<0b110, 0b001001>; 474class BINSLI_W_ENC : MSA_BIT_W_FMT<0b110, 0b001001>; 475class BINSLI_D_ENC : MSA_BIT_D_FMT<0b110, 0b001001>; 476 477class BINSR_B_ENC : MSA_3R_FMT<0b111, 0b00, 0b001101>; 478class BINSR_H_ENC : MSA_3R_FMT<0b111, 0b01, 0b001101>; 479class BINSR_W_ENC : MSA_3R_FMT<0b111, 0b10, 0b001101>; 480class BINSR_D_ENC : MSA_3R_FMT<0b111, 0b11, 0b001101>; 481 482class BINSRI_B_ENC : MSA_BIT_B_FMT<0b111, 0b001001>; 483class BINSRI_H_ENC : MSA_BIT_H_FMT<0b111, 0b001001>; 484class BINSRI_W_ENC : MSA_BIT_W_FMT<0b111, 0b001001>; 485class BINSRI_D_ENC : MSA_BIT_D_FMT<0b111, 0b001001>; 486 487class BMNZ_V_ENC : MSA_VEC_FMT<0b00100, 0b011110>; 488 489class BMNZI_B_ENC : MSA_I8_FMT<0b00, 0b000001>; 490 491class BMZ_V_ENC : MSA_VEC_FMT<0b00101, 0b011110>; 492 493class BMZI_B_ENC : MSA_I8_FMT<0b01, 0b000001>; 494 495class BNEG_B_ENC : MSA_3R_FMT<0b101, 0b00, 0b001101>; 496class BNEG_H_ENC : MSA_3R_FMT<0b101, 0b01, 0b001101>; 497class BNEG_W_ENC : MSA_3R_FMT<0b101, 0b10, 0b001101>; 498class BNEG_D_ENC : MSA_3R_FMT<0b101, 0b11, 0b001101>; 499 500class BNEGI_B_ENC : MSA_BIT_B_FMT<0b101, 0b001001>; 501class BNEGI_H_ENC : MSA_BIT_H_FMT<0b101, 0b001001>; 502class BNEGI_W_ENC : MSA_BIT_W_FMT<0b101, 0b001001>; 503class BNEGI_D_ENC : MSA_BIT_D_FMT<0b101, 0b001001>; 504 505class BNZ_B_ENC : MSA_CBRANCH_FMT<0b111, 0b00>; 506class BNZ_H_ENC : MSA_CBRANCH_FMT<0b111, 0b01>; 507class BNZ_W_ENC : MSA_CBRANCH_FMT<0b111, 0b10>; 508class BNZ_D_ENC : MSA_CBRANCH_FMT<0b111, 0b11>; 509 510class BNZ_V_ENC : MSA_CBRANCH_V_FMT<0b01111>; 511 512class BSEL_V_ENC : MSA_VEC_FMT<0b00110, 0b011110>; 513 514class BSELI_B_ENC : MSA_I8_FMT<0b10, 0b000001>; 515 516class BSET_B_ENC : MSA_3R_FMT<0b100, 0b00, 0b001101>; 517class BSET_H_ENC : MSA_3R_FMT<0b100, 0b01, 0b001101>; 518class BSET_W_ENC : MSA_3R_FMT<0b100, 0b10, 0b001101>; 519class BSET_D_ENC : MSA_3R_FMT<0b100, 0b11, 0b001101>; 520 521class BSETI_B_ENC : MSA_BIT_B_FMT<0b100, 0b001001>; 522class BSETI_H_ENC : MSA_BIT_H_FMT<0b100, 0b001001>; 523class BSETI_W_ENC : MSA_BIT_W_FMT<0b100, 0b001001>; 524class BSETI_D_ENC : MSA_BIT_D_FMT<0b100, 0b001001>; 525 526class BZ_B_ENC : MSA_CBRANCH_FMT<0b110, 0b00>; 527class BZ_H_ENC : MSA_CBRANCH_FMT<0b110, 0b01>; 528class BZ_W_ENC : MSA_CBRANCH_FMT<0b110, 0b10>; 529class BZ_D_ENC : MSA_CBRANCH_FMT<0b110, 0b11>; 530 531class BZ_V_ENC : MSA_CBRANCH_V_FMT<0b01011>; 532 533class CEQ_B_ENC : MSA_3R_FMT<0b000, 0b00, 0b001111>; 534class CEQ_H_ENC : MSA_3R_FMT<0b000, 0b01, 0b001111>; 535class CEQ_W_ENC : MSA_3R_FMT<0b000, 0b10, 0b001111>; 536class CEQ_D_ENC : MSA_3R_FMT<0b000, 0b11, 0b001111>; 537 538class CEQI_B_ENC : MSA_I5_FMT<0b000, 0b00, 0b000111>; 539class CEQI_H_ENC : MSA_I5_FMT<0b000, 0b01, 0b000111>; 540class CEQI_W_ENC : MSA_I5_FMT<0b000, 0b10, 0b000111>; 541class CEQI_D_ENC : MSA_I5_FMT<0b000, 0b11, 0b000111>; 542 543class CFCMSA_ENC : MSA_ELM_CFCMSA_FMT<0b0001111110, 0b011001>; 544 545class CLE_S_B_ENC : MSA_3R_FMT<0b100, 0b00, 0b001111>; 546class CLE_S_H_ENC : MSA_3R_FMT<0b100, 0b01, 0b001111>; 547class CLE_S_W_ENC : MSA_3R_FMT<0b100, 0b10, 0b001111>; 548class CLE_S_D_ENC : MSA_3R_FMT<0b100, 0b11, 0b001111>; 549 550class CLE_U_B_ENC : MSA_3R_FMT<0b101, 0b00, 0b001111>; 551class CLE_U_H_ENC : MSA_3R_FMT<0b101, 0b01, 0b001111>; 552class CLE_U_W_ENC : MSA_3R_FMT<0b101, 0b10, 0b001111>; 553class CLE_U_D_ENC : MSA_3R_FMT<0b101, 0b11, 0b001111>; 554 555class CLEI_S_B_ENC : MSA_I5_FMT<0b100, 0b00, 0b000111>; 556class CLEI_S_H_ENC : MSA_I5_FMT<0b100, 0b01, 0b000111>; 557class CLEI_S_W_ENC : MSA_I5_FMT<0b100, 0b10, 0b000111>; 558class CLEI_S_D_ENC : MSA_I5_FMT<0b100, 0b11, 0b000111>; 559 560class CLEI_U_B_ENC : MSA_I5_FMT<0b101, 0b00, 0b000111>; 561class CLEI_U_H_ENC : MSA_I5_FMT<0b101, 0b01, 0b000111>; 562class CLEI_U_W_ENC : MSA_I5_FMT<0b101, 0b10, 0b000111>; 563class CLEI_U_D_ENC : MSA_I5_FMT<0b101, 0b11, 0b000111>; 564 565class CLT_S_B_ENC : MSA_3R_FMT<0b010, 0b00, 0b001111>; 566class CLT_S_H_ENC : MSA_3R_FMT<0b010, 0b01, 0b001111>; 567class CLT_S_W_ENC : MSA_3R_FMT<0b010, 0b10, 0b001111>; 568class CLT_S_D_ENC : MSA_3R_FMT<0b010, 0b11, 0b001111>; 569 570class CLT_U_B_ENC : MSA_3R_FMT<0b011, 0b00, 0b001111>; 571class CLT_U_H_ENC : MSA_3R_FMT<0b011, 0b01, 0b001111>; 572class CLT_U_W_ENC : MSA_3R_FMT<0b011, 0b10, 0b001111>; 573class CLT_U_D_ENC : MSA_3R_FMT<0b011, 0b11, 0b001111>; 574 575class CLTI_S_B_ENC : MSA_I5_FMT<0b010, 0b00, 0b000111>; 576class CLTI_S_H_ENC : MSA_I5_FMT<0b010, 0b01, 0b000111>; 577class CLTI_S_W_ENC : MSA_I5_FMT<0b010, 0b10, 0b000111>; 578class CLTI_S_D_ENC : MSA_I5_FMT<0b010, 0b11, 0b000111>; 579 580class CLTI_U_B_ENC : MSA_I5_FMT<0b011, 0b00, 0b000111>; 581class CLTI_U_H_ENC : MSA_I5_FMT<0b011, 0b01, 0b000111>; 582class CLTI_U_W_ENC : MSA_I5_FMT<0b011, 0b10, 0b000111>; 583class CLTI_U_D_ENC : MSA_I5_FMT<0b011, 0b11, 0b000111>; 584 585class COPY_S_B_ENC : MSA_ELM_COPY_B_FMT<0b0010, 0b011001>; 586class COPY_S_H_ENC : MSA_ELM_COPY_H_FMT<0b0010, 0b011001>; 587class COPY_S_W_ENC : MSA_ELM_COPY_W_FMT<0b0010, 0b011001>; 588class COPY_S_D_ENC : MSA_ELM_COPY_D_FMT<0b0010, 0b011001>; 589 590class COPY_U_B_ENC : MSA_ELM_COPY_B_FMT<0b0011, 0b011001>; 591class COPY_U_H_ENC : MSA_ELM_COPY_H_FMT<0b0011, 0b011001>; 592class COPY_U_W_ENC : MSA_ELM_COPY_W_FMT<0b0011, 0b011001>; 593 594class CTCMSA_ENC : MSA_ELM_CTCMSA_FMT<0b0000111110, 0b011001>; 595 596class DIV_S_B_ENC : MSA_3R_FMT<0b100, 0b00, 0b010010>; 597class DIV_S_H_ENC : MSA_3R_FMT<0b100, 0b01, 0b010010>; 598class DIV_S_W_ENC : MSA_3R_FMT<0b100, 0b10, 0b010010>; 599class DIV_S_D_ENC : MSA_3R_FMT<0b100, 0b11, 0b010010>; 600 601class DIV_U_B_ENC : MSA_3R_FMT<0b101, 0b00, 0b010010>; 602class DIV_U_H_ENC : MSA_3R_FMT<0b101, 0b01, 0b010010>; 603class DIV_U_W_ENC : MSA_3R_FMT<0b101, 0b10, 0b010010>; 604class DIV_U_D_ENC : MSA_3R_FMT<0b101, 0b11, 0b010010>; 605 606class DOTP_S_H_ENC : MSA_3R_FMT<0b000, 0b01, 0b010011>; 607class DOTP_S_W_ENC : MSA_3R_FMT<0b000, 0b10, 0b010011>; 608class DOTP_S_D_ENC : MSA_3R_FMT<0b000, 0b11, 0b010011>; 609 610class DOTP_U_H_ENC : MSA_3R_FMT<0b001, 0b01, 0b010011>; 611class DOTP_U_W_ENC : MSA_3R_FMT<0b001, 0b10, 0b010011>; 612class DOTP_U_D_ENC : MSA_3R_FMT<0b001, 0b11, 0b010011>; 613 614class DPADD_S_H_ENC : MSA_3R_FMT<0b010, 0b01, 0b010011>; 615class DPADD_S_W_ENC : MSA_3R_FMT<0b010, 0b10, 0b010011>; 616class DPADD_S_D_ENC : MSA_3R_FMT<0b010, 0b11, 0b010011>; 617 618class DPADD_U_H_ENC : MSA_3R_FMT<0b011, 0b01, 0b010011>; 619class DPADD_U_W_ENC : MSA_3R_FMT<0b011, 0b10, 0b010011>; 620class DPADD_U_D_ENC : MSA_3R_FMT<0b011, 0b11, 0b010011>; 621 622class DPSUB_S_H_ENC : MSA_3R_FMT<0b100, 0b01, 0b010011>; 623class DPSUB_S_W_ENC : MSA_3R_FMT<0b100, 0b10, 0b010011>; 624class DPSUB_S_D_ENC : MSA_3R_FMT<0b100, 0b11, 0b010011>; 625 626class DPSUB_U_H_ENC : MSA_3R_FMT<0b101, 0b01, 0b010011>; 627class DPSUB_U_W_ENC : MSA_3R_FMT<0b101, 0b10, 0b010011>; 628class DPSUB_U_D_ENC : MSA_3R_FMT<0b101, 0b11, 0b010011>; 629 630class FADD_W_ENC : MSA_3RF_FMT<0b0000, 0b0, 0b011011>; 631class FADD_D_ENC : MSA_3RF_FMT<0b0000, 0b1, 0b011011>; 632 633class FCAF_W_ENC : MSA_3RF_FMT<0b0000, 0b0, 0b011010>; 634class FCAF_D_ENC : MSA_3RF_FMT<0b0000, 0b1, 0b011010>; 635 636class FCEQ_W_ENC : MSA_3RF_FMT<0b0010, 0b0, 0b011010>; 637class FCEQ_D_ENC : MSA_3RF_FMT<0b0010, 0b1, 0b011010>; 638 639class FCLASS_W_ENC : MSA_2RF_FMT<0b110010000, 0b0, 0b011110>; 640class FCLASS_D_ENC : MSA_2RF_FMT<0b110010000, 0b1, 0b011110>; 641 642class FCLE_W_ENC : MSA_3RF_FMT<0b0110, 0b0, 0b011010>; 643class FCLE_D_ENC : MSA_3RF_FMT<0b0110, 0b1, 0b011010>; 644 645class FCLT_W_ENC : MSA_3RF_FMT<0b0100, 0b0, 0b011010>; 646class FCLT_D_ENC : MSA_3RF_FMT<0b0100, 0b1, 0b011010>; 647 648class FCNE_W_ENC : MSA_3RF_FMT<0b0011, 0b0, 0b011100>; 649class FCNE_D_ENC : MSA_3RF_FMT<0b0011, 0b1, 0b011100>; 650 651class FCOR_W_ENC : MSA_3RF_FMT<0b0001, 0b0, 0b011100>; 652class FCOR_D_ENC : MSA_3RF_FMT<0b0001, 0b1, 0b011100>; 653 654class FCUEQ_W_ENC : MSA_3RF_FMT<0b0011, 0b0, 0b011010>; 655class FCUEQ_D_ENC : MSA_3RF_FMT<0b0011, 0b1, 0b011010>; 656 657class FCULE_W_ENC : MSA_3RF_FMT<0b0111, 0b0, 0b011010>; 658class FCULE_D_ENC : MSA_3RF_FMT<0b0111, 0b1, 0b011010>; 659 660class FCULT_W_ENC : MSA_3RF_FMT<0b0101, 0b0, 0b011010>; 661class FCULT_D_ENC : MSA_3RF_FMT<0b0101, 0b1, 0b011010>; 662 663class FCUN_W_ENC : MSA_3RF_FMT<0b0001, 0b0, 0b011010>; 664class FCUN_D_ENC : MSA_3RF_FMT<0b0001, 0b1, 0b011010>; 665 666class FCUNE_W_ENC : MSA_3RF_FMT<0b0010, 0b0, 0b011100>; 667class FCUNE_D_ENC : MSA_3RF_FMT<0b0010, 0b1, 0b011100>; 668 669class FDIV_W_ENC : MSA_3RF_FMT<0b0011, 0b0, 0b011011>; 670class FDIV_D_ENC : MSA_3RF_FMT<0b0011, 0b1, 0b011011>; 671 672class FEXDO_H_ENC : MSA_3RF_FMT<0b1000, 0b0, 0b011011>; 673class FEXDO_W_ENC : MSA_3RF_FMT<0b1000, 0b1, 0b011011>; 674 675class FEXP2_W_ENC : MSA_3RF_FMT<0b0111, 0b0, 0b011011>; 676class FEXP2_D_ENC : MSA_3RF_FMT<0b0111, 0b1, 0b011011>; 677 678class FEXUPL_W_ENC : MSA_2RF_FMT<0b110011000, 0b0, 0b011110>; 679class FEXUPL_D_ENC : MSA_2RF_FMT<0b110011000, 0b1, 0b011110>; 680 681class FEXUPR_W_ENC : MSA_2RF_FMT<0b110011001, 0b0, 0b011110>; 682class FEXUPR_D_ENC : MSA_2RF_FMT<0b110011001, 0b1, 0b011110>; 683 684class FFINT_S_W_ENC : MSA_2RF_FMT<0b110011110, 0b0, 0b011110>; 685class FFINT_S_D_ENC : MSA_2RF_FMT<0b110011110, 0b1, 0b011110>; 686 687class FFINT_U_W_ENC : MSA_2RF_FMT<0b110011111, 0b0, 0b011110>; 688class FFINT_U_D_ENC : MSA_2RF_FMT<0b110011111, 0b1, 0b011110>; 689 690class FFQL_W_ENC : MSA_2RF_FMT<0b110011010, 0b0, 0b011110>; 691class FFQL_D_ENC : MSA_2RF_FMT<0b110011010, 0b1, 0b011110>; 692 693class FFQR_W_ENC : MSA_2RF_FMT<0b110011011, 0b0, 0b011110>; 694class FFQR_D_ENC : MSA_2RF_FMT<0b110011011, 0b1, 0b011110>; 695 696class FILL_B_ENC : MSA_2R_FILL_FMT<0b11000000, 0b00, 0b011110>; 697class FILL_H_ENC : MSA_2R_FILL_FMT<0b11000000, 0b01, 0b011110>; 698class FILL_W_ENC : MSA_2R_FILL_FMT<0b11000000, 0b10, 0b011110>; 699class FILL_D_ENC : MSA_2R_FILL_D_FMT<0b11000000, 0b11, 0b011110>; 700 701class FLOG2_W_ENC : MSA_2RF_FMT<0b110010111, 0b0, 0b011110>; 702class FLOG2_D_ENC : MSA_2RF_FMT<0b110010111, 0b1, 0b011110>; 703 704class FMADD_W_ENC : MSA_3RF_FMT<0b0100, 0b0, 0b011011>; 705class FMADD_D_ENC : MSA_3RF_FMT<0b0100, 0b1, 0b011011>; 706 707class FMAX_W_ENC : MSA_3RF_FMT<0b1110, 0b0, 0b011011>; 708class FMAX_D_ENC : MSA_3RF_FMT<0b1110, 0b1, 0b011011>; 709 710class FMAX_A_W_ENC : MSA_3RF_FMT<0b1111, 0b0, 0b011011>; 711class FMAX_A_D_ENC : MSA_3RF_FMT<0b1111, 0b1, 0b011011>; 712 713class FMIN_W_ENC : MSA_3RF_FMT<0b1100, 0b0, 0b011011>; 714class FMIN_D_ENC : MSA_3RF_FMT<0b1100, 0b1, 0b011011>; 715 716class FMIN_A_W_ENC : MSA_3RF_FMT<0b1101, 0b0, 0b011011>; 717class FMIN_A_D_ENC : MSA_3RF_FMT<0b1101, 0b1, 0b011011>; 718 719class FMSUB_W_ENC : MSA_3RF_FMT<0b0101, 0b0, 0b011011>; 720class FMSUB_D_ENC : MSA_3RF_FMT<0b0101, 0b1, 0b011011>; 721 722class FMUL_W_ENC : MSA_3RF_FMT<0b0010, 0b0, 0b011011>; 723class FMUL_D_ENC : MSA_3RF_FMT<0b0010, 0b1, 0b011011>; 724 725class FRINT_W_ENC : MSA_2RF_FMT<0b110010110, 0b0, 0b011110>; 726class FRINT_D_ENC : MSA_2RF_FMT<0b110010110, 0b1, 0b011110>; 727 728class FRCP_W_ENC : MSA_2RF_FMT<0b110010101, 0b0, 0b011110>; 729class FRCP_D_ENC : MSA_2RF_FMT<0b110010101, 0b1, 0b011110>; 730 731class FRSQRT_W_ENC : MSA_2RF_FMT<0b110010100, 0b0, 0b011110>; 732class FRSQRT_D_ENC : MSA_2RF_FMT<0b110010100, 0b1, 0b011110>; 733 734class FSAF_W_ENC : MSA_3RF_FMT<0b1000, 0b0, 0b011010>; 735class FSAF_D_ENC : MSA_3RF_FMT<0b1000, 0b1, 0b011010>; 736 737class FSEQ_W_ENC : MSA_3RF_FMT<0b1010, 0b0, 0b011010>; 738class FSEQ_D_ENC : MSA_3RF_FMT<0b1010, 0b1, 0b011010>; 739 740class FSLE_W_ENC : MSA_3RF_FMT<0b1110, 0b0, 0b011010>; 741class FSLE_D_ENC : MSA_3RF_FMT<0b1110, 0b1, 0b011010>; 742 743class FSLT_W_ENC : MSA_3RF_FMT<0b1100, 0b0, 0b011010>; 744class FSLT_D_ENC : MSA_3RF_FMT<0b1100, 0b1, 0b011010>; 745 746class FSNE_W_ENC : MSA_3RF_FMT<0b1011, 0b0, 0b011100>; 747class FSNE_D_ENC : MSA_3RF_FMT<0b1011, 0b1, 0b011100>; 748 749class FSOR_W_ENC : MSA_3RF_FMT<0b1001, 0b0, 0b011100>; 750class FSOR_D_ENC : MSA_3RF_FMT<0b1001, 0b1, 0b011100>; 751 752class FSQRT_W_ENC : MSA_2RF_FMT<0b110010011, 0b0, 0b011110>; 753class FSQRT_D_ENC : MSA_2RF_FMT<0b110010011, 0b1, 0b011110>; 754 755class FSUB_W_ENC : MSA_3RF_FMT<0b0001, 0b0, 0b011011>; 756class FSUB_D_ENC : MSA_3RF_FMT<0b0001, 0b1, 0b011011>; 757 758class FSUEQ_W_ENC : MSA_3RF_FMT<0b1011, 0b0, 0b011010>; 759class FSUEQ_D_ENC : MSA_3RF_FMT<0b1011, 0b1, 0b011010>; 760 761class FSULE_W_ENC : MSA_3RF_FMT<0b1111, 0b0, 0b011010>; 762class FSULE_D_ENC : MSA_3RF_FMT<0b1111, 0b1, 0b011010>; 763 764class FSULT_W_ENC : MSA_3RF_FMT<0b1101, 0b0, 0b011010>; 765class FSULT_D_ENC : MSA_3RF_FMT<0b1101, 0b1, 0b011010>; 766 767class FSUN_W_ENC : MSA_3RF_FMT<0b1001, 0b0, 0b011010>; 768class FSUN_D_ENC : MSA_3RF_FMT<0b1001, 0b1, 0b011010>; 769 770class FSUNE_W_ENC : MSA_3RF_FMT<0b1010, 0b0, 0b011100>; 771class FSUNE_D_ENC : MSA_3RF_FMT<0b1010, 0b1, 0b011100>; 772 773class FTINT_S_W_ENC : MSA_2RF_FMT<0b110011100, 0b0, 0b011110>; 774class FTINT_S_D_ENC : MSA_2RF_FMT<0b110011100, 0b1, 0b011110>; 775 776class FTINT_U_W_ENC : MSA_2RF_FMT<0b110011101, 0b0, 0b011110>; 777class FTINT_U_D_ENC : MSA_2RF_FMT<0b110011101, 0b1, 0b011110>; 778 779class FTQ_H_ENC : MSA_3RF_FMT<0b1010, 0b0, 0b011011>; 780class FTQ_W_ENC : MSA_3RF_FMT<0b1010, 0b1, 0b011011>; 781 782class FTRUNC_S_W_ENC : MSA_2RF_FMT<0b110010001, 0b0, 0b011110>; 783class FTRUNC_S_D_ENC : MSA_2RF_FMT<0b110010001, 0b1, 0b011110>; 784 785class FTRUNC_U_W_ENC : MSA_2RF_FMT<0b110010010, 0b0, 0b011110>; 786class FTRUNC_U_D_ENC : MSA_2RF_FMT<0b110010010, 0b1, 0b011110>; 787 788class HADD_S_H_ENC : MSA_3R_FMT<0b100, 0b01, 0b010101>; 789class HADD_S_W_ENC : MSA_3R_FMT<0b100, 0b10, 0b010101>; 790class HADD_S_D_ENC : MSA_3R_FMT<0b100, 0b11, 0b010101>; 791 792class HADD_U_H_ENC : MSA_3R_FMT<0b101, 0b01, 0b010101>; 793class HADD_U_W_ENC : MSA_3R_FMT<0b101, 0b10, 0b010101>; 794class HADD_U_D_ENC : MSA_3R_FMT<0b101, 0b11, 0b010101>; 795 796class HSUB_S_H_ENC : MSA_3R_FMT<0b110, 0b01, 0b010101>; 797class HSUB_S_W_ENC : MSA_3R_FMT<0b110, 0b10, 0b010101>; 798class HSUB_S_D_ENC : MSA_3R_FMT<0b110, 0b11, 0b010101>; 799 800class HSUB_U_H_ENC : MSA_3R_FMT<0b111, 0b01, 0b010101>; 801class HSUB_U_W_ENC : MSA_3R_FMT<0b111, 0b10, 0b010101>; 802class HSUB_U_D_ENC : MSA_3R_FMT<0b111, 0b11, 0b010101>; 803 804class ILVEV_B_ENC : MSA_3R_FMT<0b110, 0b00, 0b010100>; 805class ILVEV_H_ENC : MSA_3R_FMT<0b110, 0b01, 0b010100>; 806class ILVEV_W_ENC : MSA_3R_FMT<0b110, 0b10, 0b010100>; 807class ILVEV_D_ENC : MSA_3R_FMT<0b110, 0b11, 0b010100>; 808 809class ILVL_B_ENC : MSA_3R_FMT<0b100, 0b00, 0b010100>; 810class ILVL_H_ENC : MSA_3R_FMT<0b100, 0b01, 0b010100>; 811class ILVL_W_ENC : MSA_3R_FMT<0b100, 0b10, 0b010100>; 812class ILVL_D_ENC : MSA_3R_FMT<0b100, 0b11, 0b010100>; 813 814class ILVOD_B_ENC : MSA_3R_FMT<0b111, 0b00, 0b010100>; 815class ILVOD_H_ENC : MSA_3R_FMT<0b111, 0b01, 0b010100>; 816class ILVOD_W_ENC : MSA_3R_FMT<0b111, 0b10, 0b010100>; 817class ILVOD_D_ENC : MSA_3R_FMT<0b111, 0b11, 0b010100>; 818 819class ILVR_B_ENC : MSA_3R_FMT<0b101, 0b00, 0b010100>; 820class ILVR_H_ENC : MSA_3R_FMT<0b101, 0b01, 0b010100>; 821class ILVR_W_ENC : MSA_3R_FMT<0b101, 0b10, 0b010100>; 822class ILVR_D_ENC : MSA_3R_FMT<0b101, 0b11, 0b010100>; 823 824class INSERT_B_ENC : MSA_ELM_INSERT_B_FMT<0b0100, 0b011001>; 825class INSERT_H_ENC : MSA_ELM_INSERT_H_FMT<0b0100, 0b011001>; 826class INSERT_W_ENC : MSA_ELM_INSERT_W_FMT<0b0100, 0b011001>; 827class INSERT_D_ENC : MSA_ELM_INSERT_D_FMT<0b0100, 0b011001>; 828 829class INSVE_B_ENC : MSA_ELM_B_FMT<0b0101, 0b011001>; 830class INSVE_H_ENC : MSA_ELM_H_FMT<0b0101, 0b011001>; 831class INSVE_W_ENC : MSA_ELM_W_FMT<0b0101, 0b011001>; 832class INSVE_D_ENC : MSA_ELM_D_FMT<0b0101, 0b011001>; 833 834class LD_B_ENC : MSA_MI10_FMT<0b00, 0b1000>; 835class LD_H_ENC : MSA_MI10_FMT<0b01, 0b1000>; 836class LD_W_ENC : MSA_MI10_FMT<0b10, 0b1000>; 837class LD_D_ENC : MSA_MI10_FMT<0b11, 0b1000>; 838 839class LDI_B_ENC : MSA_I10_FMT<0b110, 0b00, 0b000111>; 840class LDI_H_ENC : MSA_I10_FMT<0b110, 0b01, 0b000111>; 841class LDI_W_ENC : MSA_I10_FMT<0b110, 0b10, 0b000111>; 842class LDI_D_ENC : MSA_I10_FMT<0b110, 0b11, 0b000111>; 843 844class LSA_ENC : SPECIAL_LSA_FMT<0b000101>; 845class DLSA_ENC : SPECIAL_DLSA_FMT<0b010101>; 846 847class MADD_Q_H_ENC : MSA_3RF_FMT<0b0101, 0b0, 0b011100>; 848class MADD_Q_W_ENC : MSA_3RF_FMT<0b0101, 0b1, 0b011100>; 849 850class MADDR_Q_H_ENC : MSA_3RF_FMT<0b1101, 0b0, 0b011100>; 851class MADDR_Q_W_ENC : MSA_3RF_FMT<0b1101, 0b1, 0b011100>; 852 853class MADDV_B_ENC : MSA_3R_FMT<0b001, 0b00, 0b010010>; 854class MADDV_H_ENC : MSA_3R_FMT<0b001, 0b01, 0b010010>; 855class MADDV_W_ENC : MSA_3R_FMT<0b001, 0b10, 0b010010>; 856class MADDV_D_ENC : MSA_3R_FMT<0b001, 0b11, 0b010010>; 857 858class MAX_A_B_ENC : MSA_3R_FMT<0b110, 0b00, 0b001110>; 859class MAX_A_H_ENC : MSA_3R_FMT<0b110, 0b01, 0b001110>; 860class MAX_A_W_ENC : MSA_3R_FMT<0b110, 0b10, 0b001110>; 861class MAX_A_D_ENC : MSA_3R_FMT<0b110, 0b11, 0b001110>; 862 863class MAX_S_B_ENC : MSA_3R_FMT<0b010, 0b00, 0b001110>; 864class MAX_S_H_ENC : MSA_3R_FMT<0b010, 0b01, 0b001110>; 865class MAX_S_W_ENC : MSA_3R_FMT<0b010, 0b10, 0b001110>; 866class MAX_S_D_ENC : MSA_3R_FMT<0b010, 0b11, 0b001110>; 867 868class MAX_U_B_ENC : MSA_3R_FMT<0b011, 0b00, 0b001110>; 869class MAX_U_H_ENC : MSA_3R_FMT<0b011, 0b01, 0b001110>; 870class MAX_U_W_ENC : MSA_3R_FMT<0b011, 0b10, 0b001110>; 871class MAX_U_D_ENC : MSA_3R_FMT<0b011, 0b11, 0b001110>; 872 873class MAXI_S_B_ENC : MSA_I5_FMT<0b010, 0b00, 0b000110>; 874class MAXI_S_H_ENC : MSA_I5_FMT<0b010, 0b01, 0b000110>; 875class MAXI_S_W_ENC : MSA_I5_FMT<0b010, 0b10, 0b000110>; 876class MAXI_S_D_ENC : MSA_I5_FMT<0b010, 0b11, 0b000110>; 877 878class MAXI_U_B_ENC : MSA_I5_FMT<0b011, 0b00, 0b000110>; 879class MAXI_U_H_ENC : MSA_I5_FMT<0b011, 0b01, 0b000110>; 880class MAXI_U_W_ENC : MSA_I5_FMT<0b011, 0b10, 0b000110>; 881class MAXI_U_D_ENC : MSA_I5_FMT<0b011, 0b11, 0b000110>; 882 883class MIN_A_B_ENC : MSA_3R_FMT<0b111, 0b00, 0b001110>; 884class MIN_A_H_ENC : MSA_3R_FMT<0b111, 0b01, 0b001110>; 885class MIN_A_W_ENC : MSA_3R_FMT<0b111, 0b10, 0b001110>; 886class MIN_A_D_ENC : MSA_3R_FMT<0b111, 0b11, 0b001110>; 887 888class MIN_S_B_ENC : MSA_3R_FMT<0b100, 0b00, 0b001110>; 889class MIN_S_H_ENC : MSA_3R_FMT<0b100, 0b01, 0b001110>; 890class MIN_S_W_ENC : MSA_3R_FMT<0b100, 0b10, 0b001110>; 891class MIN_S_D_ENC : MSA_3R_FMT<0b100, 0b11, 0b001110>; 892 893class MIN_U_B_ENC : MSA_3R_FMT<0b101, 0b00, 0b001110>; 894class MIN_U_H_ENC : MSA_3R_FMT<0b101, 0b01, 0b001110>; 895class MIN_U_W_ENC : MSA_3R_FMT<0b101, 0b10, 0b001110>; 896class MIN_U_D_ENC : MSA_3R_FMT<0b101, 0b11, 0b001110>; 897 898class MINI_S_B_ENC : MSA_I5_FMT<0b100, 0b00, 0b000110>; 899class MINI_S_H_ENC : MSA_I5_FMT<0b100, 0b01, 0b000110>; 900class MINI_S_W_ENC : MSA_I5_FMT<0b100, 0b10, 0b000110>; 901class MINI_S_D_ENC : MSA_I5_FMT<0b100, 0b11, 0b000110>; 902 903class MINI_U_B_ENC : MSA_I5_FMT<0b101, 0b00, 0b000110>; 904class MINI_U_H_ENC : MSA_I5_FMT<0b101, 0b01, 0b000110>; 905class MINI_U_W_ENC : MSA_I5_FMT<0b101, 0b10, 0b000110>; 906class MINI_U_D_ENC : MSA_I5_FMT<0b101, 0b11, 0b000110>; 907 908class MOD_S_B_ENC : MSA_3R_FMT<0b110, 0b00, 0b010010>; 909class MOD_S_H_ENC : MSA_3R_FMT<0b110, 0b01, 0b010010>; 910class MOD_S_W_ENC : MSA_3R_FMT<0b110, 0b10, 0b010010>; 911class MOD_S_D_ENC : MSA_3R_FMT<0b110, 0b11, 0b010010>; 912 913class MOD_U_B_ENC : MSA_3R_FMT<0b111, 0b00, 0b010010>; 914class MOD_U_H_ENC : MSA_3R_FMT<0b111, 0b01, 0b010010>; 915class MOD_U_W_ENC : MSA_3R_FMT<0b111, 0b10, 0b010010>; 916class MOD_U_D_ENC : MSA_3R_FMT<0b111, 0b11, 0b010010>; 917 918class MOVE_V_ENC : MSA_ELM_FMT<0b0010111110, 0b011001>; 919 920class MSUB_Q_H_ENC : MSA_3RF_FMT<0b0110, 0b0, 0b011100>; 921class MSUB_Q_W_ENC : MSA_3RF_FMT<0b0110, 0b1, 0b011100>; 922 923class MSUBR_Q_H_ENC : MSA_3RF_FMT<0b1110, 0b0, 0b011100>; 924class MSUBR_Q_W_ENC : MSA_3RF_FMT<0b1110, 0b1, 0b011100>; 925 926class MSUBV_B_ENC : MSA_3R_FMT<0b010, 0b00, 0b010010>; 927class MSUBV_H_ENC : MSA_3R_FMT<0b010, 0b01, 0b010010>; 928class MSUBV_W_ENC : MSA_3R_FMT<0b010, 0b10, 0b010010>; 929class MSUBV_D_ENC : MSA_3R_FMT<0b010, 0b11, 0b010010>; 930 931class MUL_Q_H_ENC : MSA_3RF_FMT<0b0100, 0b0, 0b011100>; 932class MUL_Q_W_ENC : MSA_3RF_FMT<0b0100, 0b1, 0b011100>; 933 934class MULR_Q_H_ENC : MSA_3RF_FMT<0b1100, 0b0, 0b011100>; 935class MULR_Q_W_ENC : MSA_3RF_FMT<0b1100, 0b1, 0b011100>; 936 937class MULV_B_ENC : MSA_3R_FMT<0b000, 0b00, 0b010010>; 938class MULV_H_ENC : MSA_3R_FMT<0b000, 0b01, 0b010010>; 939class MULV_W_ENC : MSA_3R_FMT<0b000, 0b10, 0b010010>; 940class MULV_D_ENC : MSA_3R_FMT<0b000, 0b11, 0b010010>; 941 942class NLOC_B_ENC : MSA_2R_FMT<0b11000010, 0b00, 0b011110>; 943class NLOC_H_ENC : MSA_2R_FMT<0b11000010, 0b01, 0b011110>; 944class NLOC_W_ENC : MSA_2R_FMT<0b11000010, 0b10, 0b011110>; 945class NLOC_D_ENC : MSA_2R_FMT<0b11000010, 0b11, 0b011110>; 946 947class NLZC_B_ENC : MSA_2R_FMT<0b11000011, 0b00, 0b011110>; 948class NLZC_H_ENC : MSA_2R_FMT<0b11000011, 0b01, 0b011110>; 949class NLZC_W_ENC : MSA_2R_FMT<0b11000011, 0b10, 0b011110>; 950class NLZC_D_ENC : MSA_2R_FMT<0b11000011, 0b11, 0b011110>; 951 952class NOR_V_ENC : MSA_VEC_FMT<0b00010, 0b011110>; 953 954class NORI_B_ENC : MSA_I8_FMT<0b10, 0b000000>; 955 956class OR_V_ENC : MSA_VEC_FMT<0b00001, 0b011110>; 957 958class ORI_B_ENC : MSA_I8_FMT<0b01, 0b000000>; 959 960class PCKEV_B_ENC : MSA_3R_FMT<0b010, 0b00, 0b010100>; 961class PCKEV_H_ENC : MSA_3R_FMT<0b010, 0b01, 0b010100>; 962class PCKEV_W_ENC : MSA_3R_FMT<0b010, 0b10, 0b010100>; 963class PCKEV_D_ENC : MSA_3R_FMT<0b010, 0b11, 0b010100>; 964 965class PCKOD_B_ENC : MSA_3R_FMT<0b011, 0b00, 0b010100>; 966class PCKOD_H_ENC : MSA_3R_FMT<0b011, 0b01, 0b010100>; 967class PCKOD_W_ENC : MSA_3R_FMT<0b011, 0b10, 0b010100>; 968class PCKOD_D_ENC : MSA_3R_FMT<0b011, 0b11, 0b010100>; 969 970class PCNT_B_ENC : MSA_2R_FMT<0b11000001, 0b00, 0b011110>; 971class PCNT_H_ENC : MSA_2R_FMT<0b11000001, 0b01, 0b011110>; 972class PCNT_W_ENC : MSA_2R_FMT<0b11000001, 0b10, 0b011110>; 973class PCNT_D_ENC : MSA_2R_FMT<0b11000001, 0b11, 0b011110>; 974 975class SAT_S_B_ENC : MSA_BIT_B_FMT<0b000, 0b001010>; 976class SAT_S_H_ENC : MSA_BIT_H_FMT<0b000, 0b001010>; 977class SAT_S_W_ENC : MSA_BIT_W_FMT<0b000, 0b001010>; 978class SAT_S_D_ENC : MSA_BIT_D_FMT<0b000, 0b001010>; 979 980class SAT_U_B_ENC : MSA_BIT_B_FMT<0b001, 0b001010>; 981class SAT_U_H_ENC : MSA_BIT_H_FMT<0b001, 0b001010>; 982class SAT_U_W_ENC : MSA_BIT_W_FMT<0b001, 0b001010>; 983class SAT_U_D_ENC : MSA_BIT_D_FMT<0b001, 0b001010>; 984 985class SHF_B_ENC : MSA_I8_FMT<0b00, 0b000010>; 986class SHF_H_ENC : MSA_I8_FMT<0b01, 0b000010>; 987class SHF_W_ENC : MSA_I8_FMT<0b10, 0b000010>; 988 989class SLD_B_ENC : MSA_3R_INDEX_FMT<0b000, 0b00, 0b010100>; 990class SLD_H_ENC : MSA_3R_INDEX_FMT<0b000, 0b01, 0b010100>; 991class SLD_W_ENC : MSA_3R_INDEX_FMT<0b000, 0b10, 0b010100>; 992class SLD_D_ENC : MSA_3R_INDEX_FMT<0b000, 0b11, 0b010100>; 993 994class SLDI_B_ENC : MSA_ELM_B_FMT<0b0000, 0b011001>; 995class SLDI_H_ENC : MSA_ELM_H_FMT<0b0000, 0b011001>; 996class SLDI_W_ENC : MSA_ELM_W_FMT<0b0000, 0b011001>; 997class SLDI_D_ENC : MSA_ELM_D_FMT<0b0000, 0b011001>; 998 999class SLL_B_ENC : MSA_3R_FMT<0b000, 0b00, 0b001101>; 1000class SLL_H_ENC : MSA_3R_FMT<0b000, 0b01, 0b001101>; 1001class SLL_W_ENC : MSA_3R_FMT<0b000, 0b10, 0b001101>; 1002class SLL_D_ENC : MSA_3R_FMT<0b000, 0b11, 0b001101>; 1003 1004class SLLI_B_ENC : MSA_BIT_B_FMT<0b000, 0b001001>; 1005class SLLI_H_ENC : MSA_BIT_H_FMT<0b000, 0b001001>; 1006class SLLI_W_ENC : MSA_BIT_W_FMT<0b000, 0b001001>; 1007class SLLI_D_ENC : MSA_BIT_D_FMT<0b000, 0b001001>; 1008 1009class SPLAT_B_ENC : MSA_3R_INDEX_FMT<0b001, 0b00, 0b010100>; 1010class SPLAT_H_ENC : MSA_3R_INDEX_FMT<0b001, 0b01, 0b010100>; 1011class SPLAT_W_ENC : MSA_3R_INDEX_FMT<0b001, 0b10, 0b010100>; 1012class SPLAT_D_ENC : MSA_3R_INDEX_FMT<0b001, 0b11, 0b010100>; 1013 1014class SPLATI_B_ENC : MSA_ELM_B_FMT<0b0001, 0b011001>; 1015class SPLATI_H_ENC : MSA_ELM_H_FMT<0b0001, 0b011001>; 1016class SPLATI_W_ENC : MSA_ELM_W_FMT<0b0001, 0b011001>; 1017class SPLATI_D_ENC : MSA_ELM_D_FMT<0b0001, 0b011001>; 1018 1019class SRA_B_ENC : MSA_3R_FMT<0b001, 0b00, 0b001101>; 1020class SRA_H_ENC : MSA_3R_FMT<0b001, 0b01, 0b001101>; 1021class SRA_W_ENC : MSA_3R_FMT<0b001, 0b10, 0b001101>; 1022class SRA_D_ENC : MSA_3R_FMT<0b001, 0b11, 0b001101>; 1023 1024class SRAI_B_ENC : MSA_BIT_B_FMT<0b001, 0b001001>; 1025class SRAI_H_ENC : MSA_BIT_H_FMT<0b001, 0b001001>; 1026class SRAI_W_ENC : MSA_BIT_W_FMT<0b001, 0b001001>; 1027class SRAI_D_ENC : MSA_BIT_D_FMT<0b001, 0b001001>; 1028 1029class SRAR_B_ENC : MSA_3R_FMT<0b001, 0b00, 0b010101>; 1030class SRAR_H_ENC : MSA_3R_FMT<0b001, 0b01, 0b010101>; 1031class SRAR_W_ENC : MSA_3R_FMT<0b001, 0b10, 0b010101>; 1032class SRAR_D_ENC : MSA_3R_FMT<0b001, 0b11, 0b010101>; 1033 1034class SRARI_B_ENC : MSA_BIT_B_FMT<0b010, 0b001010>; 1035class SRARI_H_ENC : MSA_BIT_H_FMT<0b010, 0b001010>; 1036class SRARI_W_ENC : MSA_BIT_W_FMT<0b010, 0b001010>; 1037class SRARI_D_ENC : MSA_BIT_D_FMT<0b010, 0b001010>; 1038 1039class SRL_B_ENC : MSA_3R_FMT<0b010, 0b00, 0b001101>; 1040class SRL_H_ENC : MSA_3R_FMT<0b010, 0b01, 0b001101>; 1041class SRL_W_ENC : MSA_3R_FMT<0b010, 0b10, 0b001101>; 1042class SRL_D_ENC : MSA_3R_FMT<0b010, 0b11, 0b001101>; 1043 1044class SRLI_B_ENC : MSA_BIT_B_FMT<0b010, 0b001001>; 1045class SRLI_H_ENC : MSA_BIT_H_FMT<0b010, 0b001001>; 1046class SRLI_W_ENC : MSA_BIT_W_FMT<0b010, 0b001001>; 1047class SRLI_D_ENC : MSA_BIT_D_FMT<0b010, 0b001001>; 1048 1049class SRLR_B_ENC : MSA_3R_FMT<0b010, 0b00, 0b010101>; 1050class SRLR_H_ENC : MSA_3R_FMT<0b010, 0b01, 0b010101>; 1051class SRLR_W_ENC : MSA_3R_FMT<0b010, 0b10, 0b010101>; 1052class SRLR_D_ENC : MSA_3R_FMT<0b010, 0b11, 0b010101>; 1053 1054class SRLRI_B_ENC : MSA_BIT_B_FMT<0b011, 0b001010>; 1055class SRLRI_H_ENC : MSA_BIT_H_FMT<0b011, 0b001010>; 1056class SRLRI_W_ENC : MSA_BIT_W_FMT<0b011, 0b001010>; 1057class SRLRI_D_ENC : MSA_BIT_D_FMT<0b011, 0b001010>; 1058 1059class ST_B_ENC : MSA_MI10_FMT<0b00, 0b1001>; 1060class ST_H_ENC : MSA_MI10_FMT<0b01, 0b1001>; 1061class ST_W_ENC : MSA_MI10_FMT<0b10, 0b1001>; 1062class ST_D_ENC : MSA_MI10_FMT<0b11, 0b1001>; 1063 1064class SUBS_S_B_ENC : MSA_3R_FMT<0b000, 0b00, 0b010001>; 1065class SUBS_S_H_ENC : MSA_3R_FMT<0b000, 0b01, 0b010001>; 1066class SUBS_S_W_ENC : MSA_3R_FMT<0b000, 0b10, 0b010001>; 1067class SUBS_S_D_ENC : MSA_3R_FMT<0b000, 0b11, 0b010001>; 1068 1069class SUBS_U_B_ENC : MSA_3R_FMT<0b001, 0b00, 0b010001>; 1070class SUBS_U_H_ENC : MSA_3R_FMT<0b001, 0b01, 0b010001>; 1071class SUBS_U_W_ENC : MSA_3R_FMT<0b001, 0b10, 0b010001>; 1072class SUBS_U_D_ENC : MSA_3R_FMT<0b001, 0b11, 0b010001>; 1073 1074class SUBSUS_U_B_ENC : MSA_3R_FMT<0b010, 0b00, 0b010001>; 1075class SUBSUS_U_H_ENC : MSA_3R_FMT<0b010, 0b01, 0b010001>; 1076class SUBSUS_U_W_ENC : MSA_3R_FMT<0b010, 0b10, 0b010001>; 1077class SUBSUS_U_D_ENC : MSA_3R_FMT<0b010, 0b11, 0b010001>; 1078 1079class SUBSUU_S_B_ENC : MSA_3R_FMT<0b011, 0b00, 0b010001>; 1080class SUBSUU_S_H_ENC : MSA_3R_FMT<0b011, 0b01, 0b010001>; 1081class SUBSUU_S_W_ENC : MSA_3R_FMT<0b011, 0b10, 0b010001>; 1082class SUBSUU_S_D_ENC : MSA_3R_FMT<0b011, 0b11, 0b010001>; 1083 1084class SUBV_B_ENC : MSA_3R_FMT<0b001, 0b00, 0b001110>; 1085class SUBV_H_ENC : MSA_3R_FMT<0b001, 0b01, 0b001110>; 1086class SUBV_W_ENC : MSA_3R_FMT<0b001, 0b10, 0b001110>; 1087class SUBV_D_ENC : MSA_3R_FMT<0b001, 0b11, 0b001110>; 1088 1089class SUBVI_B_ENC : MSA_I5_FMT<0b001, 0b00, 0b000110>; 1090class SUBVI_H_ENC : MSA_I5_FMT<0b001, 0b01, 0b000110>; 1091class SUBVI_W_ENC : MSA_I5_FMT<0b001, 0b10, 0b000110>; 1092class SUBVI_D_ENC : MSA_I5_FMT<0b001, 0b11, 0b000110>; 1093 1094class VSHF_B_ENC : MSA_3R_FMT<0b000, 0b00, 0b010101>; 1095class VSHF_H_ENC : MSA_3R_FMT<0b000, 0b01, 0b010101>; 1096class VSHF_W_ENC : MSA_3R_FMT<0b000, 0b10, 0b010101>; 1097class VSHF_D_ENC : MSA_3R_FMT<0b000, 0b11, 0b010101>; 1098 1099class XOR_V_ENC : MSA_VEC_FMT<0b00011, 0b011110>; 1100 1101class XORI_B_ENC : MSA_I8_FMT<0b11, 0b000000>; 1102 1103// Instruction desc. 1104class MSA_BIT_B_DESC_BASE<string instr_asm, SDPatternOperator OpNode, 1105 ComplexPattern Imm, RegisterOperand ROWD, 1106 RegisterOperand ROWS = ROWD, 1107 InstrItinClass itin = NoItinerary> { 1108 dag OutOperandList = (outs ROWD:$wd); 1109 dag InOperandList = (ins ROWS:$ws, vsplat_uimm3:$m); 1110 string AsmString = !strconcat(instr_asm, "\t$wd, $ws, $m"); 1111 list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWS:$ws, Imm:$m))]; 1112 InstrItinClass Itinerary = itin; 1113} 1114 1115class MSA_BIT_H_DESC_BASE<string instr_asm, SDPatternOperator OpNode, 1116 ComplexPattern Imm, RegisterOperand ROWD, 1117 RegisterOperand ROWS = ROWD, 1118 InstrItinClass itin = NoItinerary> { 1119 dag OutOperandList = (outs ROWD:$wd); 1120 dag InOperandList = (ins ROWS:$ws, vsplat_uimm4:$m); 1121 string AsmString = !strconcat(instr_asm, "\t$wd, $ws, $m"); 1122 list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWS:$ws, Imm:$m))]; 1123 InstrItinClass Itinerary = itin; 1124} 1125 1126class MSA_BIT_W_DESC_BASE<string instr_asm, SDPatternOperator OpNode, 1127 ComplexPattern Imm, RegisterOperand ROWD, 1128 RegisterOperand ROWS = ROWD, 1129 InstrItinClass itin = NoItinerary> { 1130 dag OutOperandList = (outs ROWD:$wd); 1131 dag InOperandList = (ins ROWS:$ws, vsplat_uimm5:$m); 1132 string AsmString = !strconcat(instr_asm, "\t$wd, $ws, $m"); 1133 list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWS:$ws, Imm:$m))]; 1134 InstrItinClass Itinerary = itin; 1135} 1136 1137class MSA_BIT_D_DESC_BASE<string instr_asm, SDPatternOperator OpNode, 1138 ComplexPattern Imm, RegisterOperand ROWD, 1139 RegisterOperand ROWS = ROWD, 1140 InstrItinClass itin = NoItinerary> { 1141 dag OutOperandList = (outs ROWD:$wd); 1142 dag InOperandList = (ins ROWS:$ws, vsplat_uimm6:$m); 1143 string AsmString = !strconcat(instr_asm, "\t$wd, $ws, $m"); 1144 list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWS:$ws, Imm:$m))]; 1145 InstrItinClass Itinerary = itin; 1146} 1147 1148class MSA_BIT_X_DESC_BASE<string instr_asm, SDPatternOperator OpNode, 1149 Operand ImmOp, ImmLeaf Imm, RegisterOperand ROWD, 1150 RegisterOperand ROWS = ROWD, 1151 InstrItinClass itin = NoItinerary> { 1152 dag OutOperandList = (outs ROWD:$wd); 1153 dag InOperandList = (ins ROWS:$ws, ImmOp:$m); 1154 string AsmString = !strconcat(instr_asm, "\t$wd, $ws, $m"); 1155 list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWS:$ws, Imm:$m))]; 1156 InstrItinClass Itinerary = itin; 1157} 1158 1159class MSA_BIT_BINSXI_DESC_BASE<string instr_asm, ValueType Ty, 1160 SplatComplexPattern Mask, RegisterOperand ROWD, 1161 RegisterOperand ROWS = ROWD, 1162 InstrItinClass itin = NoItinerary> { 1163 dag OutOperandList = (outs ROWD:$wd); 1164 dag InOperandList = (ins ROWD:$wd_in, ROWS:$ws, Mask.OpClass:$m); 1165 string AsmString = !strconcat(instr_asm, "\t$wd, $ws, $m"); 1166 // Note that binsxi and vselect treat the condition operand the opposite 1167 // way to each other. 1168 // (vselect cond, if_set, if_clear) 1169 // (BSEL_V cond, if_clear, if_set) 1170 list<dag> Pattern = [(set ROWD:$wd, (vselect (Ty Mask:$m), (Ty ROWD:$ws), 1171 ROWS:$wd_in))]; 1172 InstrItinClass Itinerary = itin; 1173 string Constraints = "$wd = $wd_in"; 1174} 1175 1176class MSA_BIT_BINSLI_DESC_BASE<string instr_asm, ValueType Ty, 1177 SplatComplexPattern ImmOp, RegisterOperand ROWD, 1178 RegisterOperand ROWS = ROWD, 1179 InstrItinClass itin = NoItinerary> : 1180 MSA_BIT_BINSXI_DESC_BASE<instr_asm, Ty, ImmOp, ROWD, ROWS, itin>; 1181 1182class MSA_BIT_BINSRI_DESC_BASE<string instr_asm, ValueType Ty, 1183 SplatComplexPattern ImmOp, RegisterOperand ROWD, 1184 RegisterOperand ROWS = ROWD, 1185 InstrItinClass itin = NoItinerary> : 1186 MSA_BIT_BINSXI_DESC_BASE<instr_asm, Ty, ImmOp, ROWD, ROWS, itin>; 1187 1188class MSA_BIT_SPLAT_DESC_BASE<string instr_asm, SDPatternOperator OpNode, 1189 SplatComplexPattern SplatImm, 1190 RegisterOperand ROWD, RegisterOperand ROWS = ROWD, 1191 InstrItinClass itin = NoItinerary> { 1192 dag OutOperandList = (outs ROWD:$wd); 1193 dag InOperandList = (ins ROWS:$ws, SplatImm.OpClass:$m); 1194 string AsmString = !strconcat(instr_asm, "\t$wd, $ws, $m"); 1195 list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWS:$ws, SplatImm:$m))]; 1196 InstrItinClass Itinerary = itin; 1197} 1198 1199class MSA_COPY_DESC_BASE<string instr_asm, SDPatternOperator OpNode, 1200 ValueType VecTy, Operand ImmOp, ImmLeaf Imm, 1201 RegisterOperand ROD, RegisterOperand ROWS, 1202 InstrItinClass itin = NoItinerary> { 1203 dag OutOperandList = (outs ROD:$rd); 1204 dag InOperandList = (ins ROWS:$ws, ImmOp:$n); 1205 string AsmString = !strconcat(instr_asm, "\t$rd, $ws[$n]"); 1206 list<dag> Pattern = [(set ROD:$rd, (OpNode (VecTy ROWS:$ws), Imm:$n))]; 1207 InstrItinClass Itinerary = itin; 1208} 1209 1210class MSA_ELM_SLD_DESC_BASE<string instr_asm, SDPatternOperator OpNode, 1211 RegisterOperand ROWD, RegisterOperand ROWS, 1212 Operand ImmOp, ImmLeaf Imm, 1213 InstrItinClass itin = NoItinerary> { 1214 dag OutOperandList = (outs ROWD:$wd); 1215 dag InOperandList = (ins ROWD:$wd_in, ROWS:$ws, ImmOp:$n); 1216 string AsmString = !strconcat(instr_asm, "\t$wd, $ws[$n]"); 1217 list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWD:$wd_in, ROWS:$ws, 1218 Imm:$n))]; 1219 string Constraints = "$wd = $wd_in"; 1220 InstrItinClass Itinerary = itin; 1221} 1222 1223class MSA_COPY_PSEUDO_BASE<SDPatternOperator OpNode, ValueType VecTy, 1224 Operand ImmOp, ImmLeaf Imm, RegisterClass RCD, 1225 RegisterClass RCWS> : 1226 MSAPseudo<(outs RCD:$wd), (ins RCWS:$ws, ImmOp:$n), 1227 [(set RCD:$wd, (OpNode (VecTy RCWS:$ws), Imm:$n))]> { 1228 bit usesCustomInserter = 1; 1229} 1230 1231class MSA_I5_DESC_BASE<string instr_asm, SDPatternOperator OpNode, 1232 SplatComplexPattern SplatImm, RegisterOperand ROWD, 1233 RegisterOperand ROWS = ROWD, 1234 InstrItinClass itin = NoItinerary> { 1235 dag OutOperandList = (outs ROWD:$wd); 1236 dag InOperandList = (ins ROWS:$ws, SplatImm.OpClass:$imm); 1237 string AsmString = !strconcat(instr_asm, "\t$wd, $ws, $imm"); 1238 list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWS:$ws, SplatImm:$imm))]; 1239 InstrItinClass Itinerary = itin; 1240} 1241 1242class MSA_I8_DESC_BASE<string instr_asm, SDPatternOperator OpNode, 1243 SplatComplexPattern SplatImm, RegisterOperand ROWD, 1244 RegisterOperand ROWS = ROWD, 1245 InstrItinClass itin = NoItinerary> { 1246 dag OutOperandList = (outs ROWD:$wd); 1247 dag InOperandList = (ins ROWS:$ws, SplatImm.OpClass:$u8); 1248 string AsmString = !strconcat(instr_asm, "\t$wd, $ws, $u8"); 1249 list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWS:$ws, SplatImm:$u8))]; 1250 InstrItinClass Itinerary = itin; 1251} 1252 1253class MSA_I8_SHF_DESC_BASE<string instr_asm, RegisterOperand ROWD, 1254 RegisterOperand ROWS = ROWD, 1255 InstrItinClass itin = NoItinerary> { 1256 dag OutOperandList = (outs ROWD:$wd); 1257 dag InOperandList = (ins ROWS:$ws, uimm8:$u8); 1258 string AsmString = !strconcat(instr_asm, "\t$wd, $ws, $u8"); 1259 list<dag> Pattern = [(set ROWD:$wd, (MipsSHF immZExt8:$u8, ROWS:$ws))]; 1260 InstrItinClass Itinerary = itin; 1261} 1262 1263class MSA_I10_LDI_DESC_BASE<string instr_asm, RegisterOperand ROWD, 1264 InstrItinClass itin = NoItinerary> { 1265 dag OutOperandList = (outs ROWD:$wd); 1266 dag InOperandList = (ins vsplat_simm10:$s10); 1267 string AsmString = !strconcat(instr_asm, "\t$wd, $s10"); 1268 // LDI is matched using custom matching code in MipsSEISelDAGToDAG.cpp 1269 list<dag> Pattern = []; 1270 bit hasSideEffects = 0; 1271 InstrItinClass Itinerary = itin; 1272} 1273 1274class MSA_2R_DESC_BASE<string instr_asm, SDPatternOperator OpNode, 1275 RegisterOperand ROWD, RegisterOperand ROWS = ROWD, 1276 InstrItinClass itin = NoItinerary> { 1277 dag OutOperandList = (outs ROWD:$wd); 1278 dag InOperandList = (ins ROWS:$ws); 1279 string AsmString = !strconcat(instr_asm, "\t$wd, $ws"); 1280 list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWS:$ws))]; 1281 InstrItinClass Itinerary = itin; 1282} 1283 1284class MSA_2R_FILL_DESC_BASE<string instr_asm, ValueType VT, 1285 SDPatternOperator OpNode, RegisterOperand ROWD, 1286 RegisterOperand ROS = ROWD, 1287 InstrItinClass itin = NoItinerary> { 1288 dag OutOperandList = (outs ROWD:$wd); 1289 dag InOperandList = (ins ROS:$rs); 1290 string AsmString = !strconcat(instr_asm, "\t$wd, $rs"); 1291 list<dag> Pattern = [(set ROWD:$wd, (VT (OpNode ROS:$rs)))]; 1292 InstrItinClass Itinerary = itin; 1293} 1294 1295class MSA_2R_FILL_PSEUDO_BASE<ValueType VT, SDPatternOperator OpNode, 1296 RegisterClass RCWD, RegisterClass RCWS = RCWD> : 1297 MSAPseudo<(outs RCWD:$wd), (ins RCWS:$fs), 1298 [(set RCWD:$wd, (OpNode RCWS:$fs))]> { 1299 let usesCustomInserter = 1; 1300} 1301 1302class MSA_2RF_DESC_BASE<string instr_asm, SDPatternOperator OpNode, 1303 RegisterOperand ROWD, RegisterOperand ROWS = ROWD, 1304 InstrItinClass itin = NoItinerary> { 1305 dag OutOperandList = (outs ROWD:$wd); 1306 dag InOperandList = (ins ROWS:$ws); 1307 string AsmString = !strconcat(instr_asm, "\t$wd, $ws"); 1308 list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWS:$ws))]; 1309 InstrItinClass Itinerary = itin; 1310} 1311 1312class MSA_3R_DESC_BASE<string instr_asm, SDPatternOperator OpNode, 1313 RegisterOperand ROWD, RegisterOperand ROWS = ROWD, 1314 RegisterOperand ROWT = ROWD, 1315 InstrItinClass itin = NoItinerary> { 1316 dag OutOperandList = (outs ROWD:$wd); 1317 dag InOperandList = (ins ROWS:$ws, ROWT:$wt); 1318 string AsmString = !strconcat(instr_asm, "\t$wd, $ws, $wt"); 1319 list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWS:$ws, ROWT:$wt))]; 1320 InstrItinClass Itinerary = itin; 1321} 1322 1323class MSA_3R_BINSX_DESC_BASE<string instr_asm, SDPatternOperator OpNode, 1324 RegisterOperand ROWD, RegisterOperand ROWS = ROWD, 1325 RegisterOperand ROWT = ROWD, 1326 InstrItinClass itin = NoItinerary> { 1327 dag OutOperandList = (outs ROWD:$wd); 1328 dag InOperandList = (ins ROWD:$wd_in, ROWS:$ws, ROWT:$wt); 1329 string AsmString = !strconcat(instr_asm, "\t$wd, $ws, $wt"); 1330 list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWD:$wd_in, ROWS:$ws, 1331 ROWT:$wt))]; 1332 string Constraints = "$wd = $wd_in"; 1333 InstrItinClass Itinerary = itin; 1334} 1335 1336class MSA_3R_SPLAT_DESC_BASE<string instr_asm, SDPatternOperator OpNode, 1337 RegisterOperand ROWD, RegisterOperand ROWS = ROWD, 1338 InstrItinClass itin = NoItinerary> { 1339 dag OutOperandList = (outs ROWD:$wd); 1340 dag InOperandList = (ins ROWS:$ws, GPR32Opnd:$rt); 1341 string AsmString = !strconcat(instr_asm, "\t$wd, $ws[$rt]"); 1342 list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWS:$ws, GPR32Opnd:$rt))]; 1343 InstrItinClass Itinerary = itin; 1344} 1345 1346class MSA_3R_VSHF_DESC_BASE<string instr_asm, RegisterOperand ROWD, 1347 RegisterOperand ROWS = ROWD, 1348 RegisterOperand ROWT = ROWD, 1349 InstrItinClass itin = NoItinerary> { 1350 dag OutOperandList = (outs ROWD:$wd); 1351 dag InOperandList = (ins ROWD:$wd_in, ROWS:$ws, ROWT:$wt); 1352 string AsmString = !strconcat(instr_asm, "\t$wd, $ws, $wt"); 1353 list<dag> Pattern = [(set ROWD:$wd, (MipsVSHF ROWD:$wd_in, ROWS:$ws, 1354 ROWT:$wt))]; 1355 string Constraints = "$wd = $wd_in"; 1356 InstrItinClass Itinerary = itin; 1357} 1358 1359class MSA_3R_SLD_DESC_BASE<string instr_asm, SDPatternOperator OpNode, 1360 RegisterOperand ROWD, RegisterOperand ROWS = ROWD, 1361 InstrItinClass itin = NoItinerary> { 1362 dag OutOperandList = (outs ROWD:$wd); 1363 dag InOperandList = (ins ROWD:$wd_in, ROWS:$ws, GPR32Opnd:$rt); 1364 string AsmString = !strconcat(instr_asm, "\t$wd, $ws[$rt]"); 1365 list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWD:$wd_in, ROWS:$ws, 1366 GPR32Opnd:$rt))]; 1367 InstrItinClass Itinerary = itin; 1368 string Constraints = "$wd = $wd_in"; 1369} 1370 1371class MSA_3R_4R_DESC_BASE<string instr_asm, SDPatternOperator OpNode, 1372 RegisterOperand ROWD, RegisterOperand ROWS = ROWD, 1373 RegisterOperand ROWT = ROWD, 1374 InstrItinClass itin = NoItinerary> { 1375 dag OutOperandList = (outs ROWD:$wd); 1376 dag InOperandList = (ins ROWD:$wd_in, ROWS:$ws, ROWT:$wt); 1377 string AsmString = !strconcat(instr_asm, "\t$wd, $ws, $wt"); 1378 list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWD:$wd_in, ROWS:$ws, 1379 ROWT:$wt))]; 1380 InstrItinClass Itinerary = itin; 1381 string Constraints = "$wd = $wd_in"; 1382} 1383 1384class MSA_3RF_DESC_BASE<string instr_asm, SDPatternOperator OpNode, 1385 RegisterOperand ROWD, RegisterOperand ROWS = ROWD, 1386 RegisterOperand ROWT = ROWD, 1387 InstrItinClass itin = NoItinerary> : 1388 MSA_3R_DESC_BASE<instr_asm, OpNode, ROWD, ROWS, ROWT, itin>; 1389 1390class MSA_3RF_4RF_DESC_BASE<string instr_asm, SDPatternOperator OpNode, 1391 RegisterOperand ROWD, RegisterOperand ROWS = ROWD, 1392 RegisterOperand ROWT = ROWD, 1393 InstrItinClass itin = NoItinerary> : 1394 MSA_3R_4R_DESC_BASE<instr_asm, OpNode, ROWD, ROWS, ROWT, itin>; 1395 1396class MSA_CBRANCH_DESC_BASE<string instr_asm, RegisterOperand ROWD> { 1397 dag OutOperandList = (outs); 1398 dag InOperandList = (ins ROWD:$wt, brtarget:$offset); 1399 string AsmString = !strconcat(instr_asm, "\t$wt, $offset"); 1400 list<dag> Pattern = []; 1401 InstrItinClass Itinerary = NoItinerary; 1402 bit isBranch = 1; 1403 bit isTerminator = 1; 1404 bit hasDelaySlot = 1; 1405 list<Register> Defs = [AT]; 1406} 1407 1408class MSA_INSERT_DESC_BASE<string instr_asm, SDPatternOperator OpNode, 1409 Operand ImmOp, ImmLeaf Imm, RegisterOperand ROWD, 1410 RegisterOperand ROS, 1411 InstrItinClass itin = NoItinerary> { 1412 dag OutOperandList = (outs ROWD:$wd); 1413 dag InOperandList = (ins ROWD:$wd_in, ROS:$rs, ImmOp:$n); 1414 string AsmString = !strconcat(instr_asm, "\t$wd[$n], $rs"); 1415 list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWD:$wd_in, ROS:$rs, Imm:$n))]; 1416 InstrItinClass Itinerary = itin; 1417 string Constraints = "$wd = $wd_in"; 1418} 1419 1420class MSA_INSERT_PSEUDO_BASE<SDPatternOperator OpNode, ValueType Ty, 1421 Operand ImmOp, ImmLeaf Imm, RegisterOperand ROWD, 1422 RegisterOperand ROFS> : 1423 MSAPseudo<(outs ROWD:$wd), (ins ROWD:$wd_in, ImmOp:$n, ROFS:$fs), 1424 [(set ROWD:$wd, (OpNode (Ty ROWD:$wd_in), ROFS:$fs, Imm:$n))]> { 1425 bit usesCustomInserter = 1; 1426 string Constraints = "$wd = $wd_in"; 1427} 1428 1429class MSA_INSERT_VIDX_PSEUDO_BASE<SDPatternOperator OpNode, ValueType Ty, 1430 RegisterOperand ROWD, RegisterOperand ROFS, 1431 RegisterOperand ROIdx> : 1432 MSAPseudo<(outs ROWD:$wd), (ins ROWD:$wd_in, ROIdx:$n, ROFS:$fs), 1433 [(set ROWD:$wd, (OpNode (Ty ROWD:$wd_in), ROFS:$fs, 1434 ROIdx:$n))]> { 1435 bit usesCustomInserter = 1; 1436 string Constraints = "$wd = $wd_in"; 1437} 1438 1439class MSA_INSVE_DESC_BASE<string instr_asm, SDPatternOperator OpNode, 1440 Operand ImmOp, ImmLeaf Imm, RegisterOperand ROWD, 1441 RegisterOperand ROWS = ROWD, 1442 InstrItinClass itin = NoItinerary> { 1443 dag OutOperandList = (outs ROWD:$wd); 1444 dag InOperandList = (ins ROWD:$wd_in, ImmOp:$n, ROWS:$ws, uimmz:$n2); 1445 string AsmString = !strconcat(instr_asm, "\t$wd[$n], $ws[$n2]"); 1446 list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWD:$wd_in, 1447 Imm:$n, 1448 ROWS:$ws, 1449 immz:$n2))]; 1450 InstrItinClass Itinerary = itin; 1451 string Constraints = "$wd = $wd_in"; 1452} 1453 1454class MSA_VEC_DESC_BASE<string instr_asm, SDPatternOperator OpNode, 1455 RegisterOperand ROWD, RegisterOperand ROWS = ROWD, 1456 RegisterOperand ROWT = ROWD, 1457 InstrItinClass itin = NoItinerary> { 1458 dag OutOperandList = (outs ROWD:$wd); 1459 dag InOperandList = (ins ROWS:$ws, ROWT:$wt); 1460 string AsmString = !strconcat(instr_asm, "\t$wd, $ws, $wt"); 1461 list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWS:$ws, ROWT:$wt))]; 1462 InstrItinClass Itinerary = itin; 1463} 1464 1465class MSA_ELM_SPLAT_DESC_BASE<string instr_asm, SplatComplexPattern SplatImm, 1466 RegisterOperand ROWD, 1467 RegisterOperand ROWS = ROWD, 1468 InstrItinClass itin = NoItinerary> { 1469 dag OutOperandList = (outs ROWD:$wd); 1470 dag InOperandList = (ins ROWS:$ws, SplatImm.OpClass:$n); 1471 string AsmString = !strconcat(instr_asm, "\t$wd, $ws[$n]"); 1472 list<dag> Pattern = [(set ROWD:$wd, (MipsVSHF SplatImm:$n, ROWS:$ws, 1473 ROWS:$ws))]; 1474 InstrItinClass Itinerary = itin; 1475} 1476 1477class MSA_VEC_PSEUDO_BASE<SDPatternOperator OpNode, RegisterOperand ROWD, 1478 RegisterOperand ROWS = ROWD, 1479 RegisterOperand ROWT = ROWD> : 1480 MSAPseudo<(outs ROWD:$wd), (ins ROWS:$ws, ROWT:$wt), 1481 [(set ROWD:$wd, (OpNode ROWS:$ws, ROWT:$wt))]>; 1482 1483class ADD_A_B_DESC : MSA_3R_DESC_BASE<"add_a.b", int_mips_add_a_b, MSA128BOpnd>, 1484 IsCommutable; 1485class ADD_A_H_DESC : MSA_3R_DESC_BASE<"add_a.h", int_mips_add_a_h, MSA128HOpnd>, 1486 IsCommutable; 1487class ADD_A_W_DESC : MSA_3R_DESC_BASE<"add_a.w", int_mips_add_a_w, MSA128WOpnd>, 1488 IsCommutable; 1489class ADD_A_D_DESC : MSA_3R_DESC_BASE<"add_a.d", int_mips_add_a_d, MSA128DOpnd>, 1490 IsCommutable; 1491 1492class ADDS_A_B_DESC : MSA_3R_DESC_BASE<"adds_a.b", int_mips_adds_a_b, 1493 MSA128BOpnd>, IsCommutable; 1494class ADDS_A_H_DESC : MSA_3R_DESC_BASE<"adds_a.h", int_mips_adds_a_h, 1495 MSA128HOpnd>, IsCommutable; 1496class ADDS_A_W_DESC : MSA_3R_DESC_BASE<"adds_a.w", int_mips_adds_a_w, 1497 MSA128WOpnd>, IsCommutable; 1498class ADDS_A_D_DESC : MSA_3R_DESC_BASE<"adds_a.d", int_mips_adds_a_d, 1499 MSA128DOpnd>, IsCommutable; 1500 1501class ADDS_S_B_DESC : MSA_3R_DESC_BASE<"adds_s.b", int_mips_adds_s_b, 1502 MSA128BOpnd>, IsCommutable; 1503class ADDS_S_H_DESC : MSA_3R_DESC_BASE<"adds_s.h", int_mips_adds_s_h, 1504 MSA128HOpnd>, IsCommutable; 1505class ADDS_S_W_DESC : MSA_3R_DESC_BASE<"adds_s.w", int_mips_adds_s_w, 1506 MSA128WOpnd>, IsCommutable; 1507class ADDS_S_D_DESC : MSA_3R_DESC_BASE<"adds_s.d", int_mips_adds_s_d, 1508 MSA128DOpnd>, IsCommutable; 1509 1510class ADDS_U_B_DESC : MSA_3R_DESC_BASE<"adds_u.b", int_mips_adds_u_b, 1511 MSA128BOpnd>, IsCommutable; 1512class ADDS_U_H_DESC : MSA_3R_DESC_BASE<"adds_u.h", int_mips_adds_u_h, 1513 MSA128HOpnd>, IsCommutable; 1514class ADDS_U_W_DESC : MSA_3R_DESC_BASE<"adds_u.w", int_mips_adds_u_w, 1515 MSA128WOpnd>, IsCommutable; 1516class ADDS_U_D_DESC : MSA_3R_DESC_BASE<"adds_u.d", int_mips_adds_u_d, 1517 MSA128DOpnd>, IsCommutable; 1518 1519class ADDV_B_DESC : MSA_3R_DESC_BASE<"addv.b", add, MSA128BOpnd>, IsCommutable; 1520class ADDV_H_DESC : MSA_3R_DESC_BASE<"addv.h", add, MSA128HOpnd>, IsCommutable; 1521class ADDV_W_DESC : MSA_3R_DESC_BASE<"addv.w", add, MSA128WOpnd>, IsCommutable; 1522class ADDV_D_DESC : MSA_3R_DESC_BASE<"addv.d", add, MSA128DOpnd>, IsCommutable; 1523 1524class ADDVI_B_DESC : MSA_I5_DESC_BASE<"addvi.b", add, vsplati8_uimm5, 1525 MSA128BOpnd>; 1526class ADDVI_H_DESC : MSA_I5_DESC_BASE<"addvi.h", add, vsplati16_uimm5, 1527 MSA128HOpnd>; 1528class ADDVI_W_DESC : MSA_I5_DESC_BASE<"addvi.w", add, vsplati32_uimm5, 1529 MSA128WOpnd>; 1530class ADDVI_D_DESC : MSA_I5_DESC_BASE<"addvi.d", add, vsplati64_uimm5, 1531 MSA128DOpnd>; 1532 1533class AND_V_DESC : MSA_VEC_DESC_BASE<"and.v", and, MSA128BOpnd>; 1534class AND_V_H_PSEUDO_DESC : MSA_VEC_PSEUDO_BASE<and, MSA128HOpnd>; 1535class AND_V_W_PSEUDO_DESC : MSA_VEC_PSEUDO_BASE<and, MSA128WOpnd>; 1536class AND_V_D_PSEUDO_DESC : MSA_VEC_PSEUDO_BASE<and, MSA128DOpnd>; 1537 1538class ANDI_B_DESC : MSA_I8_DESC_BASE<"andi.b", and, vsplati8_uimm8, 1539 MSA128BOpnd>; 1540 1541class ASUB_S_B_DESC : MSA_3R_DESC_BASE<"asub_s.b", int_mips_asub_s_b, 1542 MSA128BOpnd>; 1543class ASUB_S_H_DESC : MSA_3R_DESC_BASE<"asub_s.h", int_mips_asub_s_h, 1544 MSA128HOpnd>; 1545class ASUB_S_W_DESC : MSA_3R_DESC_BASE<"asub_s.w", int_mips_asub_s_w, 1546 MSA128WOpnd>; 1547class ASUB_S_D_DESC : MSA_3R_DESC_BASE<"asub_s.d", int_mips_asub_s_d, 1548 MSA128DOpnd>; 1549 1550class ASUB_U_B_DESC : MSA_3R_DESC_BASE<"asub_u.b", int_mips_asub_u_b, 1551 MSA128BOpnd>; 1552class ASUB_U_H_DESC : MSA_3R_DESC_BASE<"asub_u.h", int_mips_asub_u_h, 1553 MSA128HOpnd>; 1554class ASUB_U_W_DESC : MSA_3R_DESC_BASE<"asub_u.w", int_mips_asub_u_w, 1555 MSA128WOpnd>; 1556class ASUB_U_D_DESC : MSA_3R_DESC_BASE<"asub_u.d", int_mips_asub_u_d, 1557 MSA128DOpnd>; 1558 1559class AVE_S_B_DESC : MSA_3R_DESC_BASE<"ave_s.b", int_mips_ave_s_b, MSA128BOpnd>, 1560 IsCommutable; 1561class AVE_S_H_DESC : MSA_3R_DESC_BASE<"ave_s.h", int_mips_ave_s_h, MSA128HOpnd>, 1562 IsCommutable; 1563class AVE_S_W_DESC : MSA_3R_DESC_BASE<"ave_s.w", int_mips_ave_s_w, MSA128WOpnd>, 1564 IsCommutable; 1565class AVE_S_D_DESC : MSA_3R_DESC_BASE<"ave_s.d", int_mips_ave_s_d, MSA128DOpnd>, 1566 IsCommutable; 1567 1568class AVE_U_B_DESC : MSA_3R_DESC_BASE<"ave_u.b", int_mips_ave_u_b, MSA128BOpnd>, 1569 IsCommutable; 1570class AVE_U_H_DESC : MSA_3R_DESC_BASE<"ave_u.h", int_mips_ave_u_h, MSA128HOpnd>, 1571 IsCommutable; 1572class AVE_U_W_DESC : MSA_3R_DESC_BASE<"ave_u.w", int_mips_ave_u_w, MSA128WOpnd>, 1573 IsCommutable; 1574class AVE_U_D_DESC : MSA_3R_DESC_BASE<"ave_u.d", int_mips_ave_u_d, MSA128DOpnd>, 1575 IsCommutable; 1576 1577class AVER_S_B_DESC : MSA_3R_DESC_BASE<"aver_s.b", int_mips_aver_s_b, 1578 MSA128BOpnd>, IsCommutable; 1579class AVER_S_H_DESC : MSA_3R_DESC_BASE<"aver_s.h", int_mips_aver_s_h, 1580 MSA128HOpnd>, IsCommutable; 1581class AVER_S_W_DESC : MSA_3R_DESC_BASE<"aver_s.w", int_mips_aver_s_w, 1582 MSA128WOpnd>, IsCommutable; 1583class AVER_S_D_DESC : MSA_3R_DESC_BASE<"aver_s.d", int_mips_aver_s_d, 1584 MSA128DOpnd>, IsCommutable; 1585 1586class AVER_U_B_DESC : MSA_3R_DESC_BASE<"aver_u.b", int_mips_aver_u_b, 1587 MSA128BOpnd>, IsCommutable; 1588class AVER_U_H_DESC : MSA_3R_DESC_BASE<"aver_u.h", int_mips_aver_u_h, 1589 MSA128HOpnd>, IsCommutable; 1590class AVER_U_W_DESC : MSA_3R_DESC_BASE<"aver_u.w", int_mips_aver_u_w, 1591 MSA128WOpnd>, IsCommutable; 1592class AVER_U_D_DESC : MSA_3R_DESC_BASE<"aver_u.d", int_mips_aver_u_d, 1593 MSA128DOpnd>, IsCommutable; 1594 1595class BCLR_B_DESC : MSA_3R_DESC_BASE<"bclr.b", vbclr_b, MSA128BOpnd>; 1596class BCLR_H_DESC : MSA_3R_DESC_BASE<"bclr.h", vbclr_h, MSA128HOpnd>; 1597class BCLR_W_DESC : MSA_3R_DESC_BASE<"bclr.w", vbclr_w, MSA128WOpnd>; 1598class BCLR_D_DESC : MSA_3R_DESC_BASE<"bclr.d", vbclr_d, MSA128DOpnd>; 1599 1600class BCLRI_B_DESC : MSA_BIT_B_DESC_BASE<"bclri.b", and, vsplat_uimm_inv_pow2, 1601 MSA128BOpnd>; 1602class BCLRI_H_DESC : MSA_BIT_H_DESC_BASE<"bclri.h", and, vsplat_uimm_inv_pow2, 1603 MSA128HOpnd>; 1604class BCLRI_W_DESC : MSA_BIT_W_DESC_BASE<"bclri.w", and, vsplat_uimm_inv_pow2, 1605 MSA128WOpnd>; 1606class BCLRI_D_DESC : MSA_BIT_D_DESC_BASE<"bclri.d", and, vsplat_uimm_inv_pow2, 1607 MSA128DOpnd>; 1608 1609class BINSL_B_DESC : MSA_3R_BINSX_DESC_BASE<"binsl.b", int_mips_binsl_b, 1610 MSA128BOpnd>; 1611class BINSL_H_DESC : MSA_3R_BINSX_DESC_BASE<"binsl.h", int_mips_binsl_h, 1612 MSA128HOpnd>; 1613class BINSL_W_DESC : MSA_3R_BINSX_DESC_BASE<"binsl.w", int_mips_binsl_w, 1614 MSA128WOpnd>; 1615class BINSL_D_DESC : MSA_3R_BINSX_DESC_BASE<"binsl.d", int_mips_binsl_d, 1616 MSA128DOpnd>; 1617 1618class BINSLI_B_DESC : MSA_BIT_BINSLI_DESC_BASE<"binsli.b", v16i8, vsplat_maskl_bits_uimm3, MSA128BOpnd>; 1619class BINSLI_H_DESC : MSA_BIT_BINSLI_DESC_BASE<"binsli.h", v8i16, vsplat_maskl_bits_uimm4, MSA128HOpnd>; 1620class BINSLI_W_DESC : MSA_BIT_BINSLI_DESC_BASE<"binsli.w", v4i32, vsplat_maskl_bits_uimm5, MSA128WOpnd>; 1621class BINSLI_D_DESC : MSA_BIT_BINSLI_DESC_BASE<"binsli.d", v2i64, vsplat_maskl_bits_uimm6, MSA128DOpnd>; 1622 1623class BINSR_B_DESC : MSA_3R_BINSX_DESC_BASE<"binsr.b", int_mips_binsr_b, 1624 MSA128BOpnd>; 1625class BINSR_H_DESC : MSA_3R_BINSX_DESC_BASE<"binsr.h", int_mips_binsr_h, 1626 MSA128HOpnd>; 1627class BINSR_W_DESC : MSA_3R_BINSX_DESC_BASE<"binsr.w", int_mips_binsr_w, 1628 MSA128WOpnd>; 1629class BINSR_D_DESC : MSA_3R_BINSX_DESC_BASE<"binsr.d", int_mips_binsr_d, 1630 MSA128DOpnd>; 1631 1632class BINSRI_B_DESC 1633 : MSA_BIT_BINSRI_DESC_BASE<"binsri.b", v16i8, vsplat_maskr_bits_uimm3, 1634 MSA128BOpnd>; 1635class BINSRI_H_DESC 1636 : MSA_BIT_BINSRI_DESC_BASE<"binsri.h", v8i16, vsplat_maskr_bits_uimm4, 1637 MSA128HOpnd>; 1638class BINSRI_W_DESC 1639 : MSA_BIT_BINSRI_DESC_BASE<"binsri.w", v4i32, vsplat_maskr_bits_uimm5, 1640 MSA128WOpnd>; 1641class BINSRI_D_DESC 1642 : MSA_BIT_BINSRI_DESC_BASE<"binsri.d", v2i64, vsplat_maskr_bits_uimm6, 1643 MSA128DOpnd>; 1644 1645class BMNZ_V_DESC { 1646 dag OutOperandList = (outs MSA128BOpnd:$wd); 1647 dag InOperandList = (ins MSA128BOpnd:$wd_in, MSA128BOpnd:$ws, 1648 MSA128BOpnd:$wt); 1649 string AsmString = "bmnz.v\t$wd, $ws, $wt"; 1650 list<dag> Pattern = [(set MSA128BOpnd:$wd, (vselect MSA128BOpnd:$wt, 1651 MSA128BOpnd:$ws, 1652 MSA128BOpnd:$wd_in))]; 1653 InstrItinClass Itinerary = NoItinerary; 1654 string Constraints = "$wd = $wd_in"; 1655} 1656 1657class BMNZI_B_DESC { 1658 dag OutOperandList = (outs MSA128BOpnd:$wd); 1659 dag InOperandList = (ins MSA128BOpnd:$wd_in, MSA128BOpnd:$ws, 1660 vsplat_uimm8:$u8); 1661 string AsmString = "bmnzi.b\t$wd, $ws, $u8"; 1662 list<dag> Pattern = [(set MSA128BOpnd:$wd, (vselect vsplati8_uimm8:$u8, 1663 MSA128BOpnd:$ws, 1664 MSA128BOpnd:$wd_in))]; 1665 InstrItinClass Itinerary = NoItinerary; 1666 string Constraints = "$wd = $wd_in"; 1667} 1668 1669class BMZ_V_DESC { 1670 dag OutOperandList = (outs MSA128BOpnd:$wd); 1671 dag InOperandList = (ins MSA128BOpnd:$wd_in, MSA128BOpnd:$ws, 1672 MSA128BOpnd:$wt); 1673 string AsmString = "bmz.v\t$wd, $ws, $wt"; 1674 list<dag> Pattern = [(set MSA128BOpnd:$wd, (vselect MSA128BOpnd:$wt, 1675 MSA128BOpnd:$wd_in, 1676 MSA128BOpnd:$ws))]; 1677 InstrItinClass Itinerary = NoItinerary; 1678 string Constraints = "$wd = $wd_in"; 1679} 1680 1681class BMZI_B_DESC { 1682 dag OutOperandList = (outs MSA128BOpnd:$wd); 1683 dag InOperandList = (ins MSA128BOpnd:$wd_in, MSA128BOpnd:$ws, 1684 vsplat_uimm8:$u8); 1685 string AsmString = "bmzi.b\t$wd, $ws, $u8"; 1686 list<dag> Pattern = [(set MSA128BOpnd:$wd, (vselect vsplati8_uimm8:$u8, 1687 MSA128BOpnd:$wd_in, 1688 MSA128BOpnd:$ws))]; 1689 InstrItinClass Itinerary = NoItinerary; 1690 string Constraints = "$wd = $wd_in"; 1691} 1692 1693class BNEG_B_DESC : MSA_3R_DESC_BASE<"bneg.b", vbneg_b, MSA128BOpnd>; 1694class BNEG_H_DESC : MSA_3R_DESC_BASE<"bneg.h", vbneg_h, MSA128HOpnd>; 1695class BNEG_W_DESC : MSA_3R_DESC_BASE<"bneg.w", vbneg_w, MSA128WOpnd>; 1696class BNEG_D_DESC : MSA_3R_DESC_BASE<"bneg.d", vbneg_d, MSA128DOpnd>; 1697 1698class BNEGI_B_DESC : MSA_BIT_B_DESC_BASE<"bnegi.b", xor, vsplat_uimm_pow2, 1699 MSA128BOpnd>; 1700class BNEGI_H_DESC : MSA_BIT_H_DESC_BASE<"bnegi.h", xor, vsplat_uimm_pow2, 1701 MSA128HOpnd>; 1702class BNEGI_W_DESC : MSA_BIT_W_DESC_BASE<"bnegi.w", xor, vsplat_uimm_pow2, 1703 MSA128WOpnd>; 1704class BNEGI_D_DESC : MSA_BIT_D_DESC_BASE<"bnegi.d", xor, vsplat_uimm_pow2, 1705 MSA128DOpnd>; 1706 1707class BNZ_B_DESC : MSA_CBRANCH_DESC_BASE<"bnz.b", MSA128BOpnd>; 1708class BNZ_H_DESC : MSA_CBRANCH_DESC_BASE<"bnz.h", MSA128HOpnd>; 1709class BNZ_W_DESC : MSA_CBRANCH_DESC_BASE<"bnz.w", MSA128WOpnd>; 1710class BNZ_D_DESC : MSA_CBRANCH_DESC_BASE<"bnz.d", MSA128DOpnd>; 1711 1712class BNZ_V_DESC : MSA_CBRANCH_DESC_BASE<"bnz.v", MSA128BOpnd>; 1713 1714class BSEL_V_DESC { 1715 dag OutOperandList = (outs MSA128BOpnd:$wd); 1716 dag InOperandList = (ins MSA128BOpnd:$wd_in, MSA128BOpnd:$ws, 1717 MSA128BOpnd:$wt); 1718 string AsmString = "bsel.v\t$wd, $ws, $wt"; 1719 // Note that vselect and BSEL_V treat the condition operand the opposite way 1720 // from each other. 1721 // (vselect cond, if_set, if_clear) 1722 // (BSEL_V cond, if_clear, if_set) 1723 list<dag> Pattern = [(set MSA128BOpnd:$wd, 1724 (vselect MSA128BOpnd:$wd_in, MSA128BOpnd:$wt, 1725 MSA128BOpnd:$ws))]; 1726 InstrItinClass Itinerary = NoItinerary; 1727 string Constraints = "$wd = $wd_in"; 1728} 1729 1730class BSELI_B_DESC { 1731 dag OutOperandList = (outs MSA128BOpnd:$wd); 1732 dag InOperandList = (ins MSA128BOpnd:$wd_in, MSA128BOpnd:$ws, 1733 vsplat_uimm8:$u8); 1734 string AsmString = "bseli.b\t$wd, $ws, $u8"; 1735 // Note that vselect and BSEL_V treat the condition operand the opposite way 1736 // from each other. 1737 // (vselect cond, if_set, if_clear) 1738 // (BSEL_V cond, if_clear, if_set) 1739 list<dag> Pattern = [(set MSA128BOpnd:$wd, (vselect MSA128BOpnd:$wd_in, 1740 vsplati8_uimm8:$u8, 1741 MSA128BOpnd:$ws))]; 1742 InstrItinClass Itinerary = NoItinerary; 1743 string Constraints = "$wd = $wd_in"; 1744} 1745 1746class BSET_B_DESC : MSA_3R_DESC_BASE<"bset.b", vbset_b, MSA128BOpnd>; 1747class BSET_H_DESC : MSA_3R_DESC_BASE<"bset.h", vbset_h, MSA128HOpnd>; 1748class BSET_W_DESC : MSA_3R_DESC_BASE<"bset.w", vbset_w, MSA128WOpnd>; 1749class BSET_D_DESC : MSA_3R_DESC_BASE<"bset.d", vbset_d, MSA128DOpnd>; 1750 1751class BSETI_B_DESC : MSA_BIT_B_DESC_BASE<"bseti.b", or, vsplat_uimm_pow2, 1752 MSA128BOpnd>; 1753class BSETI_H_DESC : MSA_BIT_H_DESC_BASE<"bseti.h", or, vsplat_uimm_pow2, 1754 MSA128HOpnd>; 1755class BSETI_W_DESC : MSA_BIT_W_DESC_BASE<"bseti.w", or, vsplat_uimm_pow2, 1756 MSA128WOpnd>; 1757class BSETI_D_DESC : MSA_BIT_D_DESC_BASE<"bseti.d", or, vsplat_uimm_pow2, 1758 MSA128DOpnd>; 1759 1760class BZ_B_DESC : MSA_CBRANCH_DESC_BASE<"bz.b", MSA128BOpnd>; 1761class BZ_H_DESC : MSA_CBRANCH_DESC_BASE<"bz.h", MSA128HOpnd>; 1762class BZ_W_DESC : MSA_CBRANCH_DESC_BASE<"bz.w", MSA128WOpnd>; 1763class BZ_D_DESC : MSA_CBRANCH_DESC_BASE<"bz.d", MSA128DOpnd>; 1764 1765class BZ_V_DESC : MSA_CBRANCH_DESC_BASE<"bz.v", MSA128BOpnd>; 1766 1767class CEQ_B_DESC : MSA_3R_DESC_BASE<"ceq.b", vseteq_v16i8, MSA128BOpnd>, 1768 IsCommutable; 1769class CEQ_H_DESC : MSA_3R_DESC_BASE<"ceq.h", vseteq_v8i16, MSA128HOpnd>, 1770 IsCommutable; 1771class CEQ_W_DESC : MSA_3R_DESC_BASE<"ceq.w", vseteq_v4i32, MSA128WOpnd>, 1772 IsCommutable; 1773class CEQ_D_DESC : MSA_3R_DESC_BASE<"ceq.d", vseteq_v2i64, MSA128DOpnd>, 1774 IsCommutable; 1775 1776class CEQI_B_DESC : MSA_I5_DESC_BASE<"ceqi.b", vseteq_v16i8, vsplati8_simm5, 1777 MSA128BOpnd>; 1778class CEQI_H_DESC : MSA_I5_DESC_BASE<"ceqi.h", vseteq_v8i16, vsplati16_simm5, 1779 MSA128HOpnd>; 1780class CEQI_W_DESC : MSA_I5_DESC_BASE<"ceqi.w", vseteq_v4i32, vsplati32_simm5, 1781 MSA128WOpnd>; 1782class CEQI_D_DESC : MSA_I5_DESC_BASE<"ceqi.d", vseteq_v2i64, vsplati64_simm5, 1783 MSA128DOpnd>; 1784 1785class CFCMSA_DESC { 1786 dag OutOperandList = (outs GPR32Opnd:$rd); 1787 dag InOperandList = (ins MSA128CROpnd:$cs); 1788 string AsmString = "cfcmsa\t$rd, $cs"; 1789 InstrItinClass Itinerary = NoItinerary; 1790 bit hasSideEffects = 1; 1791} 1792 1793class CLE_S_B_DESC : MSA_3R_DESC_BASE<"cle_s.b", vsetle_v16i8, MSA128BOpnd>; 1794class CLE_S_H_DESC : MSA_3R_DESC_BASE<"cle_s.h", vsetle_v8i16, MSA128HOpnd>; 1795class CLE_S_W_DESC : MSA_3R_DESC_BASE<"cle_s.w", vsetle_v4i32, MSA128WOpnd>; 1796class CLE_S_D_DESC : MSA_3R_DESC_BASE<"cle_s.d", vsetle_v2i64, MSA128DOpnd>; 1797 1798class CLE_U_B_DESC : MSA_3R_DESC_BASE<"cle_u.b", vsetule_v16i8, MSA128BOpnd>; 1799class CLE_U_H_DESC : MSA_3R_DESC_BASE<"cle_u.h", vsetule_v8i16, MSA128HOpnd>; 1800class CLE_U_W_DESC : MSA_3R_DESC_BASE<"cle_u.w", vsetule_v4i32, MSA128WOpnd>; 1801class CLE_U_D_DESC : MSA_3R_DESC_BASE<"cle_u.d", vsetule_v2i64, MSA128DOpnd>; 1802 1803class CLEI_S_B_DESC : MSA_I5_DESC_BASE<"clei_s.b", vsetle_v16i8, 1804 vsplati8_simm5, MSA128BOpnd>; 1805class CLEI_S_H_DESC : MSA_I5_DESC_BASE<"clei_s.h", vsetle_v8i16, 1806 vsplati16_simm5, MSA128HOpnd>; 1807class CLEI_S_W_DESC : MSA_I5_DESC_BASE<"clei_s.w", vsetle_v4i32, 1808 vsplati32_simm5, MSA128WOpnd>; 1809class CLEI_S_D_DESC : MSA_I5_DESC_BASE<"clei_s.d", vsetle_v2i64, 1810 vsplati64_simm5, MSA128DOpnd>; 1811 1812class CLEI_U_B_DESC : MSA_I5_DESC_BASE<"clei_u.b", vsetule_v16i8, 1813 vsplati8_uimm5, MSA128BOpnd>; 1814class CLEI_U_H_DESC : MSA_I5_DESC_BASE<"clei_u.h", vsetule_v8i16, 1815 vsplati16_uimm5, MSA128HOpnd>; 1816class CLEI_U_W_DESC : MSA_I5_DESC_BASE<"clei_u.w", vsetule_v4i32, 1817 vsplati32_uimm5, MSA128WOpnd>; 1818class CLEI_U_D_DESC : MSA_I5_DESC_BASE<"clei_u.d", vsetule_v2i64, 1819 vsplati64_uimm5, MSA128DOpnd>; 1820 1821class CLT_S_B_DESC : MSA_3R_DESC_BASE<"clt_s.b", vsetlt_v16i8, MSA128BOpnd>; 1822class CLT_S_H_DESC : MSA_3R_DESC_BASE<"clt_s.h", vsetlt_v8i16, MSA128HOpnd>; 1823class CLT_S_W_DESC : MSA_3R_DESC_BASE<"clt_s.w", vsetlt_v4i32, MSA128WOpnd>; 1824class CLT_S_D_DESC : MSA_3R_DESC_BASE<"clt_s.d", vsetlt_v2i64, MSA128DOpnd>; 1825 1826class CLT_U_B_DESC : MSA_3R_DESC_BASE<"clt_u.b", vsetult_v16i8, MSA128BOpnd>; 1827class CLT_U_H_DESC : MSA_3R_DESC_BASE<"clt_u.h", vsetult_v8i16, MSA128HOpnd>; 1828class CLT_U_W_DESC : MSA_3R_DESC_BASE<"clt_u.w", vsetult_v4i32, MSA128WOpnd>; 1829class CLT_U_D_DESC : MSA_3R_DESC_BASE<"clt_u.d", vsetult_v2i64, MSA128DOpnd>; 1830 1831class CLTI_S_B_DESC : MSA_I5_DESC_BASE<"clti_s.b", vsetlt_v16i8, 1832 vsplati8_simm5, MSA128BOpnd>; 1833class CLTI_S_H_DESC : MSA_I5_DESC_BASE<"clti_s.h", vsetlt_v8i16, 1834 vsplati16_simm5, MSA128HOpnd>; 1835class CLTI_S_W_DESC : MSA_I5_DESC_BASE<"clti_s.w", vsetlt_v4i32, 1836 vsplati32_simm5, MSA128WOpnd>; 1837class CLTI_S_D_DESC : MSA_I5_DESC_BASE<"clti_s.d", vsetlt_v2i64, 1838 vsplati64_simm5, MSA128DOpnd>; 1839 1840class CLTI_U_B_DESC : MSA_I5_DESC_BASE<"clti_u.b", vsetult_v16i8, 1841 vsplati8_uimm5, MSA128BOpnd>; 1842class CLTI_U_H_DESC : MSA_I5_DESC_BASE<"clti_u.h", vsetult_v8i16, 1843 vsplati16_uimm5, MSA128HOpnd>; 1844class CLTI_U_W_DESC : MSA_I5_DESC_BASE<"clti_u.w", vsetult_v4i32, 1845 vsplati32_uimm5, MSA128WOpnd>; 1846class CLTI_U_D_DESC : MSA_I5_DESC_BASE<"clti_u.d", vsetult_v2i64, 1847 vsplati64_uimm5, MSA128DOpnd>; 1848 1849class COPY_S_B_DESC : MSA_COPY_DESC_BASE<"copy_s.b", vextract_sext_i8, v16i8, 1850 uimm4_ptr, immZExt4Ptr, GPR32Opnd, 1851 MSA128BOpnd>; 1852class COPY_S_H_DESC : MSA_COPY_DESC_BASE<"copy_s.h", vextract_sext_i16, v8i16, 1853 uimm3_ptr, immZExt3Ptr, GPR32Opnd, 1854 MSA128HOpnd>; 1855class COPY_S_W_DESC : MSA_COPY_DESC_BASE<"copy_s.w", vextract_sext_i32, v4i32, 1856 uimm2_ptr, immZExt2Ptr, GPR32Opnd, 1857 MSA128WOpnd>; 1858class COPY_S_D_DESC : MSA_COPY_DESC_BASE<"copy_s.d", vextract_sext_i64, v2i64, 1859 uimm1_ptr, immZExt1Ptr, GPR64Opnd, 1860 MSA128DOpnd>; 1861 1862class COPY_U_B_DESC : MSA_COPY_DESC_BASE<"copy_u.b", vextract_zext_i8, v16i8, 1863 uimm4_ptr, immZExt4Ptr, GPR32Opnd, 1864 MSA128BOpnd>; 1865class COPY_U_H_DESC : MSA_COPY_DESC_BASE<"copy_u.h", vextract_zext_i16, v8i16, 1866 uimm3_ptr, immZExt3Ptr, GPR32Opnd, 1867 MSA128HOpnd>; 1868class COPY_U_W_DESC : MSA_COPY_DESC_BASE<"copy_u.w", vextract_zext_i32, v4i32, 1869 uimm2_ptr, immZExt2Ptr, GPR32Opnd, 1870 MSA128WOpnd>; 1871 1872class COPY_FW_PSEUDO_DESC : MSA_COPY_PSEUDO_BASE<vector_extract, v4f32, 1873 uimm2_ptr, immZExt2Ptr, FGR32, 1874 MSA128W>; 1875class COPY_FD_PSEUDO_DESC : MSA_COPY_PSEUDO_BASE<vector_extract, v2f64, 1876 uimm1_ptr, immZExt1Ptr, FGR64, 1877 MSA128D>; 1878 1879class CTCMSA_DESC { 1880 dag OutOperandList = (outs); 1881 dag InOperandList = (ins MSA128CROpnd:$cd, GPR32Opnd:$rs); 1882 string AsmString = "ctcmsa\t$cd, $rs"; 1883 InstrItinClass Itinerary = NoItinerary; 1884 bit hasSideEffects = 1; 1885} 1886 1887class DIV_S_B_DESC : MSA_3R_DESC_BASE<"div_s.b", sdiv, MSA128BOpnd>; 1888class DIV_S_H_DESC : MSA_3R_DESC_BASE<"div_s.h", sdiv, MSA128HOpnd>; 1889class DIV_S_W_DESC : MSA_3R_DESC_BASE<"div_s.w", sdiv, MSA128WOpnd>; 1890class DIV_S_D_DESC : MSA_3R_DESC_BASE<"div_s.d", sdiv, MSA128DOpnd>; 1891 1892class DIV_U_B_DESC : MSA_3R_DESC_BASE<"div_u.b", udiv, MSA128BOpnd>; 1893class DIV_U_H_DESC : MSA_3R_DESC_BASE<"div_u.h", udiv, MSA128HOpnd>; 1894class DIV_U_W_DESC : MSA_3R_DESC_BASE<"div_u.w", udiv, MSA128WOpnd>; 1895class DIV_U_D_DESC : MSA_3R_DESC_BASE<"div_u.d", udiv, MSA128DOpnd>; 1896 1897class DOTP_S_H_DESC : MSA_3R_DESC_BASE<"dotp_s.h", int_mips_dotp_s_h, 1898 MSA128HOpnd, MSA128BOpnd, MSA128BOpnd>, 1899 IsCommutable; 1900class DOTP_S_W_DESC : MSA_3R_DESC_BASE<"dotp_s.w", int_mips_dotp_s_w, 1901 MSA128WOpnd, MSA128HOpnd, MSA128HOpnd>, 1902 IsCommutable; 1903class DOTP_S_D_DESC : MSA_3R_DESC_BASE<"dotp_s.d", int_mips_dotp_s_d, 1904 MSA128DOpnd, MSA128WOpnd, MSA128WOpnd>, 1905 IsCommutable; 1906 1907class DOTP_U_H_DESC : MSA_3R_DESC_BASE<"dotp_u.h", int_mips_dotp_u_h, 1908 MSA128HOpnd, MSA128BOpnd, MSA128BOpnd>, 1909 IsCommutable; 1910class DOTP_U_W_DESC : MSA_3R_DESC_BASE<"dotp_u.w", int_mips_dotp_u_w, 1911 MSA128WOpnd, MSA128HOpnd, MSA128HOpnd>, 1912 IsCommutable; 1913class DOTP_U_D_DESC : MSA_3R_DESC_BASE<"dotp_u.d", int_mips_dotp_u_d, 1914 MSA128DOpnd, MSA128WOpnd, MSA128WOpnd>, 1915 IsCommutable; 1916 1917class DPADD_S_H_DESC : MSA_3R_4R_DESC_BASE<"dpadd_s.h", int_mips_dpadd_s_h, 1918 MSA128HOpnd, MSA128BOpnd, 1919 MSA128BOpnd>, IsCommutable; 1920class DPADD_S_W_DESC : MSA_3R_4R_DESC_BASE<"dpadd_s.w", int_mips_dpadd_s_w, 1921 MSA128WOpnd, MSA128HOpnd, 1922 MSA128HOpnd>, IsCommutable; 1923class DPADD_S_D_DESC : MSA_3R_4R_DESC_BASE<"dpadd_s.d", int_mips_dpadd_s_d, 1924 MSA128DOpnd, MSA128WOpnd, 1925 MSA128WOpnd>, IsCommutable; 1926 1927class DPADD_U_H_DESC : MSA_3R_4R_DESC_BASE<"dpadd_u.h", int_mips_dpadd_u_h, 1928 MSA128HOpnd, MSA128BOpnd, 1929 MSA128BOpnd>, IsCommutable; 1930class DPADD_U_W_DESC : MSA_3R_4R_DESC_BASE<"dpadd_u.w", int_mips_dpadd_u_w, 1931 MSA128WOpnd, MSA128HOpnd, 1932 MSA128HOpnd>, IsCommutable; 1933class DPADD_U_D_DESC : MSA_3R_4R_DESC_BASE<"dpadd_u.d", int_mips_dpadd_u_d, 1934 MSA128DOpnd, MSA128WOpnd, 1935 MSA128WOpnd>, IsCommutable; 1936 1937class DPSUB_S_H_DESC : MSA_3R_4R_DESC_BASE<"dpsub_s.h", int_mips_dpsub_s_h, 1938 MSA128HOpnd, MSA128BOpnd, 1939 MSA128BOpnd>; 1940class DPSUB_S_W_DESC : MSA_3R_4R_DESC_BASE<"dpsub_s.w", int_mips_dpsub_s_w, 1941 MSA128WOpnd, MSA128HOpnd, 1942 MSA128HOpnd>; 1943class DPSUB_S_D_DESC : MSA_3R_4R_DESC_BASE<"dpsub_s.d", int_mips_dpsub_s_d, 1944 MSA128DOpnd, MSA128WOpnd, 1945 MSA128WOpnd>; 1946 1947class DPSUB_U_H_DESC : MSA_3R_4R_DESC_BASE<"dpsub_u.h", int_mips_dpsub_u_h, 1948 MSA128HOpnd, MSA128BOpnd, 1949 MSA128BOpnd>; 1950class DPSUB_U_W_DESC : MSA_3R_4R_DESC_BASE<"dpsub_u.w", int_mips_dpsub_u_w, 1951 MSA128WOpnd, MSA128HOpnd, 1952 MSA128HOpnd>; 1953class DPSUB_U_D_DESC : MSA_3R_4R_DESC_BASE<"dpsub_u.d", int_mips_dpsub_u_d, 1954 MSA128DOpnd, MSA128WOpnd, 1955 MSA128WOpnd>; 1956 1957class FADD_W_DESC : MSA_3RF_DESC_BASE<"fadd.w", fadd, MSA128WOpnd>, 1958 IsCommutable; 1959class FADD_D_DESC : MSA_3RF_DESC_BASE<"fadd.d", fadd, MSA128DOpnd>, 1960 IsCommutable; 1961 1962class FCAF_W_DESC : MSA_3RF_DESC_BASE<"fcaf.w", int_mips_fcaf_w, MSA128WOpnd>, 1963 IsCommutable; 1964class FCAF_D_DESC : MSA_3RF_DESC_BASE<"fcaf.d", int_mips_fcaf_d, MSA128DOpnd>, 1965 IsCommutable; 1966 1967class FCEQ_W_DESC : MSA_3RF_DESC_BASE<"fceq.w", vfsetoeq_v4f32, MSA128WOpnd>, 1968 IsCommutable; 1969class FCEQ_D_DESC : MSA_3RF_DESC_BASE<"fceq.d", vfsetoeq_v2f64, MSA128DOpnd>, 1970 IsCommutable; 1971 1972class FCLASS_W_DESC : MSA_2RF_DESC_BASE<"fclass.w", int_mips_fclass_w, 1973 MSA128WOpnd>; 1974class FCLASS_D_DESC : MSA_2RF_DESC_BASE<"fclass.d", int_mips_fclass_d, 1975 MSA128DOpnd>; 1976 1977class FCLE_W_DESC : MSA_3RF_DESC_BASE<"fcle.w", vfsetole_v4f32, MSA128WOpnd>; 1978class FCLE_D_DESC : MSA_3RF_DESC_BASE<"fcle.d", vfsetole_v2f64, MSA128DOpnd>; 1979 1980class FCLT_W_DESC : MSA_3RF_DESC_BASE<"fclt.w", vfsetolt_v4f32, MSA128WOpnd>; 1981class FCLT_D_DESC : MSA_3RF_DESC_BASE<"fclt.d", vfsetolt_v2f64, MSA128DOpnd>; 1982 1983class FCNE_W_DESC : MSA_3RF_DESC_BASE<"fcne.w", vfsetone_v4f32, MSA128WOpnd>, 1984 IsCommutable; 1985class FCNE_D_DESC : MSA_3RF_DESC_BASE<"fcne.d", vfsetone_v2f64, MSA128DOpnd>, 1986 IsCommutable; 1987 1988class FCOR_W_DESC : MSA_3RF_DESC_BASE<"fcor.w", vfsetord_v4f32, MSA128WOpnd>, 1989 IsCommutable; 1990class FCOR_D_DESC : MSA_3RF_DESC_BASE<"fcor.d", vfsetord_v2f64, MSA128DOpnd>, 1991 IsCommutable; 1992 1993class FCUEQ_W_DESC : MSA_3RF_DESC_BASE<"fcueq.w", vfsetueq_v4f32, MSA128WOpnd>, 1994 IsCommutable; 1995class FCUEQ_D_DESC : MSA_3RF_DESC_BASE<"fcueq.d", vfsetueq_v2f64, MSA128DOpnd>, 1996 IsCommutable; 1997 1998class FCULE_W_DESC : MSA_3RF_DESC_BASE<"fcule.w", vfsetule_v4f32, MSA128WOpnd>, 1999 IsCommutable; 2000class FCULE_D_DESC : MSA_3RF_DESC_BASE<"fcule.d", vfsetule_v2f64, MSA128DOpnd>, 2001 IsCommutable; 2002 2003class FCULT_W_DESC : MSA_3RF_DESC_BASE<"fcult.w", vfsetult_v4f32, MSA128WOpnd>, 2004 IsCommutable; 2005class FCULT_D_DESC : MSA_3RF_DESC_BASE<"fcult.d", vfsetult_v2f64, MSA128DOpnd>, 2006 IsCommutable; 2007 2008class FCUN_W_DESC : MSA_3RF_DESC_BASE<"fcun.w", vfsetun_v4f32, MSA128WOpnd>, 2009 IsCommutable; 2010class FCUN_D_DESC : MSA_3RF_DESC_BASE<"fcun.d", vfsetun_v2f64, MSA128DOpnd>, 2011 IsCommutable; 2012 2013class FCUNE_W_DESC : MSA_3RF_DESC_BASE<"fcune.w", vfsetune_v4f32, MSA128WOpnd>, 2014 IsCommutable; 2015class FCUNE_D_DESC : MSA_3RF_DESC_BASE<"fcune.d", vfsetune_v2f64, MSA128DOpnd>, 2016 IsCommutable; 2017 2018class FDIV_W_DESC : MSA_3RF_DESC_BASE<"fdiv.w", fdiv, MSA128WOpnd>; 2019class FDIV_D_DESC : MSA_3RF_DESC_BASE<"fdiv.d", fdiv, MSA128DOpnd>; 2020 2021class FEXDO_H_DESC : MSA_3RF_DESC_BASE<"fexdo.h", int_mips_fexdo_h, 2022 MSA128HOpnd, MSA128WOpnd, MSA128WOpnd>; 2023class FEXDO_W_DESC : MSA_3RF_DESC_BASE<"fexdo.w", int_mips_fexdo_w, 2024 MSA128WOpnd, MSA128DOpnd, MSA128DOpnd>; 2025 2026// The fexp2.df instruction multiplies the first operand by 2 to the power of 2027// the second operand. We therefore need a pseudo-insn in order to invent the 2028// 1.0 when we only need to match ISD::FEXP2. 2029class FEXP2_W_DESC : MSA_3RF_DESC_BASE<"fexp2.w", mul_fexp2, MSA128WOpnd>; 2030class FEXP2_D_DESC : MSA_3RF_DESC_BASE<"fexp2.d", mul_fexp2, MSA128DOpnd>; 2031let usesCustomInserter = 1 in { 2032 class FEXP2_W_1_PSEUDO_DESC : 2033 MSAPseudo<(outs MSA128W:$wd), (ins MSA128W:$ws), 2034 [(set MSA128W:$wd, (fexp2 MSA128W:$ws))]>; 2035 class FEXP2_D_1_PSEUDO_DESC : 2036 MSAPseudo<(outs MSA128D:$wd), (ins MSA128D:$ws), 2037 [(set MSA128D:$wd, (fexp2 MSA128D:$ws))]>; 2038} 2039 2040class FEXUPL_W_DESC : MSA_2RF_DESC_BASE<"fexupl.w", int_mips_fexupl_w, 2041 MSA128WOpnd, MSA128HOpnd>; 2042class FEXUPL_D_DESC : MSA_2RF_DESC_BASE<"fexupl.d", int_mips_fexupl_d, 2043 MSA128DOpnd, MSA128WOpnd>; 2044 2045class FEXUPR_W_DESC : MSA_2RF_DESC_BASE<"fexupr.w", int_mips_fexupr_w, 2046 MSA128WOpnd, MSA128HOpnd>; 2047class FEXUPR_D_DESC : MSA_2RF_DESC_BASE<"fexupr.d", int_mips_fexupr_d, 2048 MSA128DOpnd, MSA128WOpnd>; 2049 2050class FFINT_S_W_DESC : MSA_2RF_DESC_BASE<"ffint_s.w", sint_to_fp, MSA128WOpnd>; 2051class FFINT_S_D_DESC : MSA_2RF_DESC_BASE<"ffint_s.d", sint_to_fp, MSA128DOpnd>; 2052 2053class FFINT_U_W_DESC : MSA_2RF_DESC_BASE<"ffint_u.w", uint_to_fp, MSA128WOpnd>; 2054class FFINT_U_D_DESC : MSA_2RF_DESC_BASE<"ffint_u.d", uint_to_fp, MSA128DOpnd>; 2055 2056class FFQL_W_DESC : MSA_2RF_DESC_BASE<"ffql.w", int_mips_ffql_w, 2057 MSA128WOpnd, MSA128HOpnd>; 2058class FFQL_D_DESC : MSA_2RF_DESC_BASE<"ffql.d", int_mips_ffql_d, 2059 MSA128DOpnd, MSA128WOpnd>; 2060 2061class FFQR_W_DESC : MSA_2RF_DESC_BASE<"ffqr.w", int_mips_ffqr_w, 2062 MSA128WOpnd, MSA128HOpnd>; 2063class FFQR_D_DESC : MSA_2RF_DESC_BASE<"ffqr.d", int_mips_ffqr_d, 2064 MSA128DOpnd, MSA128WOpnd>; 2065 2066class FILL_B_DESC : MSA_2R_FILL_DESC_BASE<"fill.b", v16i8, vsplati8, 2067 MSA128BOpnd, GPR32Opnd>; 2068class FILL_H_DESC : MSA_2R_FILL_DESC_BASE<"fill.h", v8i16, vsplati16, 2069 MSA128HOpnd, GPR32Opnd>; 2070class FILL_W_DESC : MSA_2R_FILL_DESC_BASE<"fill.w", v4i32, vsplati32, 2071 MSA128WOpnd, GPR32Opnd>; 2072class FILL_D_DESC : MSA_2R_FILL_DESC_BASE<"fill.d", v2i64, vsplati64, 2073 MSA128DOpnd, GPR64Opnd>; 2074 2075class FILL_FW_PSEUDO_DESC : MSA_2R_FILL_PSEUDO_BASE<v4f32, vsplatf32, MSA128W, 2076 FGR32>; 2077class FILL_FD_PSEUDO_DESC : MSA_2R_FILL_PSEUDO_BASE<v2f64, vsplatf64, MSA128D, 2078 FGR64>; 2079 2080class FLOG2_W_DESC : MSA_2RF_DESC_BASE<"flog2.w", flog2, MSA128WOpnd>; 2081class FLOG2_D_DESC : MSA_2RF_DESC_BASE<"flog2.d", flog2, MSA128DOpnd>; 2082 2083class FMADD_W_DESC : MSA_3RF_4RF_DESC_BASE<"fmadd.w", fma, MSA128WOpnd>; 2084class FMADD_D_DESC : MSA_3RF_4RF_DESC_BASE<"fmadd.d", fma, MSA128DOpnd>; 2085 2086class FMAX_W_DESC : MSA_3RF_DESC_BASE<"fmax.w", int_mips_fmax_w, MSA128WOpnd>; 2087class FMAX_D_DESC : MSA_3RF_DESC_BASE<"fmax.d", int_mips_fmax_d, MSA128DOpnd>; 2088 2089class FMAX_A_W_DESC : MSA_3RF_DESC_BASE<"fmax_a.w", int_mips_fmax_a_w, 2090 MSA128WOpnd>; 2091class FMAX_A_D_DESC : MSA_3RF_DESC_BASE<"fmax_a.d", int_mips_fmax_a_d, 2092 MSA128DOpnd>; 2093 2094class FMIN_W_DESC : MSA_3RF_DESC_BASE<"fmin.w", int_mips_fmin_w, MSA128WOpnd>; 2095class FMIN_D_DESC : MSA_3RF_DESC_BASE<"fmin.d", int_mips_fmin_d, MSA128DOpnd>; 2096 2097class FMIN_A_W_DESC : MSA_3RF_DESC_BASE<"fmin_a.w", int_mips_fmin_a_w, 2098 MSA128WOpnd>; 2099class FMIN_A_D_DESC : MSA_3RF_DESC_BASE<"fmin_a.d", int_mips_fmin_a_d, 2100 MSA128DOpnd>; 2101 2102class FMSUB_W_DESC : MSA_3RF_4RF_DESC_BASE<"fmsub.w", fms, MSA128WOpnd>; 2103class FMSUB_D_DESC : MSA_3RF_4RF_DESC_BASE<"fmsub.d", fms, MSA128DOpnd>; 2104 2105class FMUL_W_DESC : MSA_3RF_DESC_BASE<"fmul.w", fmul, MSA128WOpnd>; 2106class FMUL_D_DESC : MSA_3RF_DESC_BASE<"fmul.d", fmul, MSA128DOpnd>; 2107 2108class FRINT_W_DESC : MSA_2RF_DESC_BASE<"frint.w", frint, MSA128WOpnd>; 2109class FRINT_D_DESC : MSA_2RF_DESC_BASE<"frint.d", frint, MSA128DOpnd>; 2110 2111class FRCP_W_DESC : MSA_2RF_DESC_BASE<"frcp.w", int_mips_frcp_w, MSA128WOpnd>; 2112class FRCP_D_DESC : MSA_2RF_DESC_BASE<"frcp.d", int_mips_frcp_d, MSA128DOpnd>; 2113 2114class FRSQRT_W_DESC : MSA_2RF_DESC_BASE<"frsqrt.w", int_mips_frsqrt_w, 2115 MSA128WOpnd>; 2116class FRSQRT_D_DESC : MSA_2RF_DESC_BASE<"frsqrt.d", int_mips_frsqrt_d, 2117 MSA128DOpnd>; 2118 2119class FSAF_W_DESC : MSA_3RF_DESC_BASE<"fsaf.w", int_mips_fsaf_w, MSA128WOpnd>; 2120class FSAF_D_DESC : MSA_3RF_DESC_BASE<"fsaf.d", int_mips_fsaf_d, MSA128DOpnd>; 2121 2122class FSEQ_W_DESC : MSA_3RF_DESC_BASE<"fseq.w", int_mips_fseq_w, MSA128WOpnd>; 2123class FSEQ_D_DESC : MSA_3RF_DESC_BASE<"fseq.d", int_mips_fseq_d, MSA128DOpnd>; 2124 2125class FSLE_W_DESC : MSA_3RF_DESC_BASE<"fsle.w", int_mips_fsle_w, MSA128WOpnd>; 2126class FSLE_D_DESC : MSA_3RF_DESC_BASE<"fsle.d", int_mips_fsle_d, MSA128DOpnd>; 2127 2128class FSLT_W_DESC : MSA_3RF_DESC_BASE<"fslt.w", int_mips_fslt_w, MSA128WOpnd>; 2129class FSLT_D_DESC : MSA_3RF_DESC_BASE<"fslt.d", int_mips_fslt_d, MSA128DOpnd>; 2130 2131class FSNE_W_DESC : MSA_3RF_DESC_BASE<"fsne.w", int_mips_fsne_w, MSA128WOpnd>; 2132class FSNE_D_DESC : MSA_3RF_DESC_BASE<"fsne.d", int_mips_fsne_d, MSA128DOpnd>; 2133 2134class FSOR_W_DESC : MSA_3RF_DESC_BASE<"fsor.w", int_mips_fsor_w, MSA128WOpnd>; 2135class FSOR_D_DESC : MSA_3RF_DESC_BASE<"fsor.d", int_mips_fsor_d, MSA128DOpnd>; 2136 2137class FSQRT_W_DESC : MSA_2RF_DESC_BASE<"fsqrt.w", fsqrt, MSA128WOpnd>; 2138class FSQRT_D_DESC : MSA_2RF_DESC_BASE<"fsqrt.d", fsqrt, MSA128DOpnd>; 2139 2140class FSUB_W_DESC : MSA_3RF_DESC_BASE<"fsub.w", fsub, MSA128WOpnd>; 2141class FSUB_D_DESC : MSA_3RF_DESC_BASE<"fsub.d", fsub, MSA128DOpnd>; 2142 2143class FSUEQ_W_DESC : MSA_3RF_DESC_BASE<"fsueq.w", int_mips_fsueq_w, 2144 MSA128WOpnd>; 2145class FSUEQ_D_DESC : MSA_3RF_DESC_BASE<"fsueq.d", int_mips_fsueq_d, 2146 MSA128DOpnd>; 2147 2148class FSULE_W_DESC : MSA_3RF_DESC_BASE<"fsule.w", int_mips_fsule_w, 2149 MSA128WOpnd>; 2150class FSULE_D_DESC : MSA_3RF_DESC_BASE<"fsule.d", int_mips_fsule_d, 2151 MSA128DOpnd>; 2152 2153class FSULT_W_DESC : MSA_3RF_DESC_BASE<"fsult.w", int_mips_fsult_w, 2154 MSA128WOpnd>; 2155class FSULT_D_DESC : MSA_3RF_DESC_BASE<"fsult.d", int_mips_fsult_d, 2156 MSA128DOpnd>; 2157 2158class FSUN_W_DESC : MSA_3RF_DESC_BASE<"fsun.w", int_mips_fsun_w, 2159 MSA128WOpnd>; 2160class FSUN_D_DESC : MSA_3RF_DESC_BASE<"fsun.d", int_mips_fsun_d, 2161 MSA128DOpnd>; 2162 2163class FSUNE_W_DESC : MSA_3RF_DESC_BASE<"fsune.w", int_mips_fsune_w, 2164 MSA128WOpnd>; 2165class FSUNE_D_DESC : MSA_3RF_DESC_BASE<"fsune.d", int_mips_fsune_d, 2166 MSA128DOpnd>; 2167 2168class FTINT_S_W_DESC : MSA_2RF_DESC_BASE<"ftint_s.w", int_mips_ftint_s_w, 2169 MSA128WOpnd>; 2170class FTINT_S_D_DESC : MSA_2RF_DESC_BASE<"ftint_s.d", int_mips_ftint_s_d, 2171 MSA128DOpnd>; 2172 2173class FTINT_U_W_DESC : MSA_2RF_DESC_BASE<"ftint_u.w", int_mips_ftint_u_w, 2174 MSA128WOpnd>; 2175class FTINT_U_D_DESC : MSA_2RF_DESC_BASE<"ftint_u.d", int_mips_ftint_u_d, 2176 MSA128DOpnd>; 2177 2178class FTQ_H_DESC : MSA_3RF_DESC_BASE<"ftq.h", int_mips_ftq_h, 2179 MSA128HOpnd, MSA128WOpnd, MSA128WOpnd>; 2180class FTQ_W_DESC : MSA_3RF_DESC_BASE<"ftq.w", int_mips_ftq_w, 2181 MSA128WOpnd, MSA128DOpnd, MSA128DOpnd>; 2182 2183class FTRUNC_S_W_DESC : MSA_2RF_DESC_BASE<"ftrunc_s.w", fp_to_sint, 2184 MSA128WOpnd>; 2185class FTRUNC_S_D_DESC : MSA_2RF_DESC_BASE<"ftrunc_s.d", fp_to_sint, 2186 MSA128DOpnd>; 2187 2188class FTRUNC_U_W_DESC : MSA_2RF_DESC_BASE<"ftrunc_u.w", fp_to_uint, 2189 MSA128WOpnd>; 2190class FTRUNC_U_D_DESC : MSA_2RF_DESC_BASE<"ftrunc_u.d", fp_to_uint, 2191 MSA128DOpnd>; 2192 2193class HADD_S_H_DESC : MSA_3R_DESC_BASE<"hadd_s.h", int_mips_hadd_s_h, 2194 MSA128HOpnd, MSA128BOpnd, MSA128BOpnd>; 2195class HADD_S_W_DESC : MSA_3R_DESC_BASE<"hadd_s.w", int_mips_hadd_s_w, 2196 MSA128WOpnd, MSA128HOpnd, MSA128HOpnd>; 2197class HADD_S_D_DESC : MSA_3R_DESC_BASE<"hadd_s.d", int_mips_hadd_s_d, 2198 MSA128DOpnd, MSA128WOpnd, MSA128WOpnd>; 2199 2200class HADD_U_H_DESC : MSA_3R_DESC_BASE<"hadd_u.h", int_mips_hadd_u_h, 2201 MSA128HOpnd, MSA128BOpnd, MSA128BOpnd>; 2202class HADD_U_W_DESC : MSA_3R_DESC_BASE<"hadd_u.w", int_mips_hadd_u_w, 2203 MSA128WOpnd, MSA128HOpnd, MSA128HOpnd>; 2204class HADD_U_D_DESC : MSA_3R_DESC_BASE<"hadd_u.d", int_mips_hadd_u_d, 2205 MSA128DOpnd, MSA128WOpnd, MSA128WOpnd>; 2206 2207class HSUB_S_H_DESC : MSA_3R_DESC_BASE<"hsub_s.h", int_mips_hsub_s_h, 2208 MSA128HOpnd, MSA128BOpnd, MSA128BOpnd>; 2209class HSUB_S_W_DESC : MSA_3R_DESC_BASE<"hsub_s.w", int_mips_hsub_s_w, 2210 MSA128WOpnd, MSA128HOpnd, MSA128HOpnd>; 2211class HSUB_S_D_DESC : MSA_3R_DESC_BASE<"hsub_s.d", int_mips_hsub_s_d, 2212 MSA128DOpnd, MSA128WOpnd, MSA128WOpnd>; 2213 2214class HSUB_U_H_DESC : MSA_3R_DESC_BASE<"hsub_u.h", int_mips_hsub_u_h, 2215 MSA128HOpnd, MSA128BOpnd, MSA128BOpnd>; 2216class HSUB_U_W_DESC : MSA_3R_DESC_BASE<"hsub_u.w", int_mips_hsub_u_w, 2217 MSA128WOpnd, MSA128HOpnd, MSA128HOpnd>; 2218class HSUB_U_D_DESC : MSA_3R_DESC_BASE<"hsub_u.d", int_mips_hsub_u_d, 2219 MSA128DOpnd, MSA128WOpnd, MSA128WOpnd>; 2220 2221class ILVEV_B_DESC : MSA_3R_DESC_BASE<"ilvev.b", MipsILVEV, MSA128BOpnd>; 2222class ILVEV_H_DESC : MSA_3R_DESC_BASE<"ilvev.h", MipsILVEV, MSA128HOpnd>; 2223class ILVEV_W_DESC : MSA_3R_DESC_BASE<"ilvev.w", MipsILVEV, MSA128WOpnd>; 2224class ILVEV_D_DESC : MSA_3R_DESC_BASE<"ilvev.d", MipsILVEV, MSA128DOpnd>; 2225 2226class ILVL_B_DESC : MSA_3R_DESC_BASE<"ilvl.b", MipsILVL, MSA128BOpnd>; 2227class ILVL_H_DESC : MSA_3R_DESC_BASE<"ilvl.h", MipsILVL, MSA128HOpnd>; 2228class ILVL_W_DESC : MSA_3R_DESC_BASE<"ilvl.w", MipsILVL, MSA128WOpnd>; 2229class ILVL_D_DESC : MSA_3R_DESC_BASE<"ilvl.d", MipsILVL, MSA128DOpnd>; 2230 2231class ILVOD_B_DESC : MSA_3R_DESC_BASE<"ilvod.b", MipsILVOD, MSA128BOpnd>; 2232class ILVOD_H_DESC : MSA_3R_DESC_BASE<"ilvod.h", MipsILVOD, MSA128HOpnd>; 2233class ILVOD_W_DESC : MSA_3R_DESC_BASE<"ilvod.w", MipsILVOD, MSA128WOpnd>; 2234class ILVOD_D_DESC : MSA_3R_DESC_BASE<"ilvod.d", MipsILVOD, MSA128DOpnd>; 2235 2236class ILVR_B_DESC : MSA_3R_DESC_BASE<"ilvr.b", MipsILVR, MSA128BOpnd>; 2237class ILVR_H_DESC : MSA_3R_DESC_BASE<"ilvr.h", MipsILVR, MSA128HOpnd>; 2238class ILVR_W_DESC : MSA_3R_DESC_BASE<"ilvr.w", MipsILVR, MSA128WOpnd>; 2239class ILVR_D_DESC : MSA_3R_DESC_BASE<"ilvr.d", MipsILVR, MSA128DOpnd>; 2240 2241class INSERT_B_DESC : MSA_INSERT_DESC_BASE<"insert.b", vinsert_v16i8, uimm4, 2242 immZExt4Ptr, MSA128BOpnd, GPR32Opnd>; 2243class INSERT_H_DESC : MSA_INSERT_DESC_BASE<"insert.h", vinsert_v8i16, uimm3, 2244 immZExt3Ptr, MSA128HOpnd, GPR32Opnd>; 2245class INSERT_W_DESC : MSA_INSERT_DESC_BASE<"insert.w", vinsert_v4i32, uimm2, 2246 immZExt2Ptr, MSA128WOpnd, GPR32Opnd>; 2247class INSERT_D_DESC : MSA_INSERT_DESC_BASE<"insert.d", vinsert_v2i64, uimm1, 2248 immZExt1Ptr, MSA128DOpnd, GPR64Opnd>; 2249 2250class INSERT_B_VIDX_PSEUDO_DESC : 2251 MSA_INSERT_VIDX_PSEUDO_BASE<vector_insert, v16i8, MSA128BOpnd, GPR32Opnd, GPR32Opnd>; 2252class INSERT_H_VIDX_PSEUDO_DESC : 2253 MSA_INSERT_VIDX_PSEUDO_BASE<vector_insert, v8i16, MSA128HOpnd, GPR32Opnd, GPR32Opnd>; 2254class INSERT_W_VIDX_PSEUDO_DESC : 2255 MSA_INSERT_VIDX_PSEUDO_BASE<vector_insert, v4i32, MSA128WOpnd, GPR32Opnd, GPR32Opnd>; 2256class INSERT_D_VIDX_PSEUDO_DESC : 2257 MSA_INSERT_VIDX_PSEUDO_BASE<vector_insert, v2i64, MSA128DOpnd, GPR64Opnd, GPR32Opnd>; 2258 2259class INSERT_FW_PSEUDO_DESC : MSA_INSERT_PSEUDO_BASE<vector_insert, v4f32, 2260 uimm2, immZExt2Ptr, 2261 MSA128WOpnd, FGR32Opnd>; 2262class INSERT_FD_PSEUDO_DESC : MSA_INSERT_PSEUDO_BASE<vector_insert, v2f64, 2263 uimm1, immZExt1Ptr, 2264 MSA128DOpnd, FGR64Opnd>; 2265 2266class INSERT_FW_VIDX_PSEUDO_DESC : 2267 MSA_INSERT_VIDX_PSEUDO_BASE<vector_insert, v4f32, MSA128WOpnd, FGR32Opnd, GPR32Opnd>; 2268class INSERT_FD_VIDX_PSEUDO_DESC : 2269 MSA_INSERT_VIDX_PSEUDO_BASE<vector_insert, v2f64, MSA128DOpnd, FGR64Opnd, GPR32Opnd>; 2270 2271class INSERT_B_VIDX64_PSEUDO_DESC : 2272 MSA_INSERT_VIDX_PSEUDO_BASE<vector_insert, v16i8, MSA128BOpnd, GPR32Opnd, GPR64Opnd>; 2273class INSERT_H_VIDX64_PSEUDO_DESC : 2274 MSA_INSERT_VIDX_PSEUDO_BASE<vector_insert, v8i16, MSA128HOpnd, GPR32Opnd, GPR64Opnd>; 2275class INSERT_W_VIDX64_PSEUDO_DESC : 2276 MSA_INSERT_VIDX_PSEUDO_BASE<vector_insert, v4i32, MSA128WOpnd, GPR32Opnd, GPR64Opnd>; 2277class INSERT_D_VIDX64_PSEUDO_DESC : 2278 MSA_INSERT_VIDX_PSEUDO_BASE<vector_insert, v2i64, MSA128DOpnd, GPR64Opnd, GPR64Opnd>; 2279 2280class INSERT_FW_VIDX64_PSEUDO_DESC : 2281 MSA_INSERT_VIDX_PSEUDO_BASE<vector_insert, v4f32, MSA128WOpnd, FGR32Opnd, GPR64Opnd>; 2282class INSERT_FD_VIDX64_PSEUDO_DESC : 2283 MSA_INSERT_VIDX_PSEUDO_BASE<vector_insert, v2f64, MSA128DOpnd, FGR64Opnd, GPR64Opnd>; 2284 2285class INSVE_B_DESC : MSA_INSVE_DESC_BASE<"insve.b", insve_v16i8, uimm4, immZExt4, 2286 MSA128BOpnd>; 2287class INSVE_H_DESC : MSA_INSVE_DESC_BASE<"insve.h", insve_v8i16, uimm3, immZExt3, 2288 MSA128HOpnd>; 2289class INSVE_W_DESC : MSA_INSVE_DESC_BASE<"insve.w", insve_v4i32, uimm2, immZExt2, 2290 MSA128WOpnd>; 2291class INSVE_D_DESC : MSA_INSVE_DESC_BASE<"insve.d", insve_v2i64, uimm1, immZExt1, 2292 MSA128DOpnd>; 2293 2294class LD_DESC_BASE<string instr_asm, SDPatternOperator OpNode, 2295 ValueType TyNode, RegisterOperand ROWD, 2296 Operand MemOpnd, ComplexPattern Addr = addrimm10, 2297 InstrItinClass itin = NoItinerary> { 2298 dag OutOperandList = (outs ROWD:$wd); 2299 dag InOperandList = (ins MemOpnd:$addr); 2300 string AsmString = !strconcat(instr_asm, "\t$wd, $addr"); 2301 list<dag> Pattern = [(set ROWD:$wd, (TyNode (OpNode Addr:$addr)))]; 2302 InstrItinClass Itinerary = itin; 2303 string DecoderMethod = "DecodeMSA128Mem"; 2304} 2305 2306class LD_B_DESC : LD_DESC_BASE<"ld.b", load, v16i8, MSA128BOpnd, mem_simm10>; 2307class LD_H_DESC : LD_DESC_BASE<"ld.h", load, v8i16, MSA128HOpnd, 2308 mem_simm10_lsl1, addrimm10lsl1>; 2309class LD_W_DESC : LD_DESC_BASE<"ld.w", load, v4i32, MSA128WOpnd, 2310 mem_simm10_lsl2, addrimm10lsl2>; 2311class LD_D_DESC : LD_DESC_BASE<"ld.d", load, v2i64, MSA128DOpnd, 2312 mem_simm10_lsl3, addrimm10lsl3>; 2313 2314class LDI_B_DESC : MSA_I10_LDI_DESC_BASE<"ldi.b", MSA128BOpnd>; 2315class LDI_H_DESC : MSA_I10_LDI_DESC_BASE<"ldi.h", MSA128HOpnd>; 2316class LDI_W_DESC : MSA_I10_LDI_DESC_BASE<"ldi.w", MSA128WOpnd>; 2317class LDI_D_DESC : MSA_I10_LDI_DESC_BASE<"ldi.d", MSA128DOpnd>; 2318 2319class LSA_DESC_BASE<string instr_asm, RegisterOperand RORD, 2320 InstrItinClass itin = NoItinerary> { 2321 dag OutOperandList = (outs RORD:$rd); 2322 dag InOperandList = (ins RORD:$rs, RORD:$rt, uimm2_plus1:$sa); 2323 string AsmString = !strconcat(instr_asm, "\t$rd, $rs, $rt, $sa"); 2324 list<dag> Pattern = [(set RORD:$rd, (add RORD:$rt, 2325 (shl RORD:$rs, 2326 immZExt2Lsa:$sa)))]; 2327 InstrItinClass Itinerary = itin; 2328} 2329 2330class LSA_DESC : LSA_DESC_BASE<"lsa", GPR32Opnd, II_LSA>; 2331class DLSA_DESC : LSA_DESC_BASE<"dlsa", GPR64Opnd, II_DLSA>; 2332 2333class MADD_Q_H_DESC : MSA_3RF_4RF_DESC_BASE<"madd_q.h", int_mips_madd_q_h, 2334 MSA128HOpnd>; 2335class MADD_Q_W_DESC : MSA_3RF_4RF_DESC_BASE<"madd_q.w", int_mips_madd_q_w, 2336 MSA128WOpnd>; 2337 2338class MADDR_Q_H_DESC : MSA_3RF_4RF_DESC_BASE<"maddr_q.h", int_mips_maddr_q_h, 2339 MSA128HOpnd>; 2340class MADDR_Q_W_DESC : MSA_3RF_4RF_DESC_BASE<"maddr_q.w", int_mips_maddr_q_w, 2341 MSA128WOpnd>; 2342 2343class MADDV_B_DESC : MSA_3R_4R_DESC_BASE<"maddv.b", muladd, MSA128BOpnd>; 2344class MADDV_H_DESC : MSA_3R_4R_DESC_BASE<"maddv.h", muladd, MSA128HOpnd>; 2345class MADDV_W_DESC : MSA_3R_4R_DESC_BASE<"maddv.w", muladd, MSA128WOpnd>; 2346class MADDV_D_DESC : MSA_3R_4R_DESC_BASE<"maddv.d", muladd, MSA128DOpnd>; 2347 2348class MAX_A_B_DESC : MSA_3R_DESC_BASE<"max_a.b", int_mips_max_a_b, MSA128BOpnd>; 2349class MAX_A_H_DESC : MSA_3R_DESC_BASE<"max_a.h", int_mips_max_a_h, MSA128HOpnd>; 2350class MAX_A_W_DESC : MSA_3R_DESC_BASE<"max_a.w", int_mips_max_a_w, MSA128WOpnd>; 2351class MAX_A_D_DESC : MSA_3R_DESC_BASE<"max_a.d", int_mips_max_a_d, MSA128DOpnd>; 2352 2353class MAX_S_B_DESC : MSA_3R_DESC_BASE<"max_s.b", MipsVSMax, MSA128BOpnd>; 2354class MAX_S_H_DESC : MSA_3R_DESC_BASE<"max_s.h", MipsVSMax, MSA128HOpnd>; 2355class MAX_S_W_DESC : MSA_3R_DESC_BASE<"max_s.w", MipsVSMax, MSA128WOpnd>; 2356class MAX_S_D_DESC : MSA_3R_DESC_BASE<"max_s.d", MipsVSMax, MSA128DOpnd>; 2357 2358class MAX_U_B_DESC : MSA_3R_DESC_BASE<"max_u.b", MipsVUMax, MSA128BOpnd>; 2359class MAX_U_H_DESC : MSA_3R_DESC_BASE<"max_u.h", MipsVUMax, MSA128HOpnd>; 2360class MAX_U_W_DESC : MSA_3R_DESC_BASE<"max_u.w", MipsVUMax, MSA128WOpnd>; 2361class MAX_U_D_DESC : MSA_3R_DESC_BASE<"max_u.d", MipsVUMax, MSA128DOpnd>; 2362 2363class MAXI_S_B_DESC : MSA_I5_DESC_BASE<"maxi_s.b", MipsVSMax, vsplati8_simm5, 2364 MSA128BOpnd>; 2365class MAXI_S_H_DESC : MSA_I5_DESC_BASE<"maxi_s.h", MipsVSMax, vsplati16_simm5, 2366 MSA128HOpnd>; 2367class MAXI_S_W_DESC : MSA_I5_DESC_BASE<"maxi_s.w", MipsVSMax, vsplati32_simm5, 2368 MSA128WOpnd>; 2369class MAXI_S_D_DESC : MSA_I5_DESC_BASE<"maxi_s.d", MipsVSMax, vsplati64_simm5, 2370 MSA128DOpnd>; 2371 2372class MAXI_U_B_DESC : MSA_I5_DESC_BASE<"maxi_u.b", MipsVUMax, vsplati8_uimm5, 2373 MSA128BOpnd>; 2374class MAXI_U_H_DESC : MSA_I5_DESC_BASE<"maxi_u.h", MipsVUMax, vsplati16_uimm5, 2375 MSA128HOpnd>; 2376class MAXI_U_W_DESC : MSA_I5_DESC_BASE<"maxi_u.w", MipsVUMax, vsplati32_uimm5, 2377 MSA128WOpnd>; 2378class MAXI_U_D_DESC : MSA_I5_DESC_BASE<"maxi_u.d", MipsVUMax, vsplati64_uimm5, 2379 MSA128DOpnd>; 2380 2381class MIN_A_B_DESC : MSA_3R_DESC_BASE<"min_a.b", int_mips_min_a_b, MSA128BOpnd>; 2382class MIN_A_H_DESC : MSA_3R_DESC_BASE<"min_a.h", int_mips_min_a_h, MSA128HOpnd>; 2383class MIN_A_W_DESC : MSA_3R_DESC_BASE<"min_a.w", int_mips_min_a_w, MSA128WOpnd>; 2384class MIN_A_D_DESC : MSA_3R_DESC_BASE<"min_a.d", int_mips_min_a_d, MSA128DOpnd>; 2385 2386class MIN_S_B_DESC : MSA_3R_DESC_BASE<"min_s.b", MipsVSMin, MSA128BOpnd>; 2387class MIN_S_H_DESC : MSA_3R_DESC_BASE<"min_s.h", MipsVSMin, MSA128HOpnd>; 2388class MIN_S_W_DESC : MSA_3R_DESC_BASE<"min_s.w", MipsVSMin, MSA128WOpnd>; 2389class MIN_S_D_DESC : MSA_3R_DESC_BASE<"min_s.d", MipsVSMin, MSA128DOpnd>; 2390 2391class MIN_U_B_DESC : MSA_3R_DESC_BASE<"min_u.b", MipsVUMin, MSA128BOpnd>; 2392class MIN_U_H_DESC : MSA_3R_DESC_BASE<"min_u.h", MipsVUMin, MSA128HOpnd>; 2393class MIN_U_W_DESC : MSA_3R_DESC_BASE<"min_u.w", MipsVUMin, MSA128WOpnd>; 2394class MIN_U_D_DESC : MSA_3R_DESC_BASE<"min_u.d", MipsVUMin, MSA128DOpnd>; 2395 2396class MINI_S_B_DESC : MSA_I5_DESC_BASE<"mini_s.b", MipsVSMin, vsplati8_simm5, 2397 MSA128BOpnd>; 2398class MINI_S_H_DESC : MSA_I5_DESC_BASE<"mini_s.h", MipsVSMin, vsplati16_simm5, 2399 MSA128HOpnd>; 2400class MINI_S_W_DESC : MSA_I5_DESC_BASE<"mini_s.w", MipsVSMin, vsplati32_simm5, 2401 MSA128WOpnd>; 2402class MINI_S_D_DESC : MSA_I5_DESC_BASE<"mini_s.d", MipsVSMin, vsplati64_simm5, 2403 MSA128DOpnd>; 2404 2405class MINI_U_B_DESC : MSA_I5_DESC_BASE<"mini_u.b", MipsVUMin, vsplati8_uimm5, 2406 MSA128BOpnd>; 2407class MINI_U_H_DESC : MSA_I5_DESC_BASE<"mini_u.h", MipsVUMin, vsplati16_uimm5, 2408 MSA128HOpnd>; 2409class MINI_U_W_DESC : MSA_I5_DESC_BASE<"mini_u.w", MipsVUMin, vsplati32_uimm5, 2410 MSA128WOpnd>; 2411class MINI_U_D_DESC : MSA_I5_DESC_BASE<"mini_u.d", MipsVUMin, vsplati64_uimm5, 2412 MSA128DOpnd>; 2413 2414class MOD_S_B_DESC : MSA_3R_DESC_BASE<"mod_s.b", srem, MSA128BOpnd>; 2415class MOD_S_H_DESC : MSA_3R_DESC_BASE<"mod_s.h", srem, MSA128HOpnd>; 2416class MOD_S_W_DESC : MSA_3R_DESC_BASE<"mod_s.w", srem, MSA128WOpnd>; 2417class MOD_S_D_DESC : MSA_3R_DESC_BASE<"mod_s.d", srem, MSA128DOpnd>; 2418 2419class MOD_U_B_DESC : MSA_3R_DESC_BASE<"mod_u.b", urem, MSA128BOpnd>; 2420class MOD_U_H_DESC : MSA_3R_DESC_BASE<"mod_u.h", urem, MSA128HOpnd>; 2421class MOD_U_W_DESC : MSA_3R_DESC_BASE<"mod_u.w", urem, MSA128WOpnd>; 2422class MOD_U_D_DESC : MSA_3R_DESC_BASE<"mod_u.d", urem, MSA128DOpnd>; 2423 2424class MOVE_V_DESC { 2425 dag OutOperandList = (outs MSA128BOpnd:$wd); 2426 dag InOperandList = (ins MSA128BOpnd:$ws); 2427 string AsmString = "move.v\t$wd, $ws"; 2428 list<dag> Pattern = []; 2429 InstrItinClass Itinerary = NoItinerary; 2430} 2431 2432class MSUB_Q_H_DESC : MSA_3RF_4RF_DESC_BASE<"msub_q.h", int_mips_msub_q_h, 2433 MSA128HOpnd>; 2434class MSUB_Q_W_DESC : MSA_3RF_4RF_DESC_BASE<"msub_q.w", int_mips_msub_q_w, 2435 MSA128WOpnd>; 2436 2437class MSUBR_Q_H_DESC : MSA_3RF_4RF_DESC_BASE<"msubr_q.h", int_mips_msubr_q_h, 2438 MSA128HOpnd>; 2439class MSUBR_Q_W_DESC : MSA_3RF_4RF_DESC_BASE<"msubr_q.w", int_mips_msubr_q_w, 2440 MSA128WOpnd>; 2441 2442class MSUBV_B_DESC : MSA_3R_4R_DESC_BASE<"msubv.b", mulsub, MSA128BOpnd>; 2443class MSUBV_H_DESC : MSA_3R_4R_DESC_BASE<"msubv.h", mulsub, MSA128HOpnd>; 2444class MSUBV_W_DESC : MSA_3R_4R_DESC_BASE<"msubv.w", mulsub, MSA128WOpnd>; 2445class MSUBV_D_DESC : MSA_3R_4R_DESC_BASE<"msubv.d", mulsub, MSA128DOpnd>; 2446 2447class MUL_Q_H_DESC : MSA_3RF_DESC_BASE<"mul_q.h", int_mips_mul_q_h, 2448 MSA128HOpnd>; 2449class MUL_Q_W_DESC : MSA_3RF_DESC_BASE<"mul_q.w", int_mips_mul_q_w, 2450 MSA128WOpnd>; 2451 2452class MULR_Q_H_DESC : MSA_3RF_DESC_BASE<"mulr_q.h", int_mips_mulr_q_h, 2453 MSA128HOpnd>; 2454class MULR_Q_W_DESC : MSA_3RF_DESC_BASE<"mulr_q.w", int_mips_mulr_q_w, 2455 MSA128WOpnd>; 2456 2457class MULV_B_DESC : MSA_3R_DESC_BASE<"mulv.b", mul, MSA128BOpnd>; 2458class MULV_H_DESC : MSA_3R_DESC_BASE<"mulv.h", mul, MSA128HOpnd>; 2459class MULV_W_DESC : MSA_3R_DESC_BASE<"mulv.w", mul, MSA128WOpnd>; 2460class MULV_D_DESC : MSA_3R_DESC_BASE<"mulv.d", mul, MSA128DOpnd>; 2461 2462class NLOC_B_DESC : MSA_2R_DESC_BASE<"nloc.b", int_mips_nloc_b, MSA128BOpnd>; 2463class NLOC_H_DESC : MSA_2R_DESC_BASE<"nloc.h", int_mips_nloc_h, MSA128HOpnd>; 2464class NLOC_W_DESC : MSA_2R_DESC_BASE<"nloc.w", int_mips_nloc_w, MSA128WOpnd>; 2465class NLOC_D_DESC : MSA_2R_DESC_BASE<"nloc.d", int_mips_nloc_d, MSA128DOpnd>; 2466 2467class NLZC_B_DESC : MSA_2R_DESC_BASE<"nlzc.b", ctlz, MSA128BOpnd>; 2468class NLZC_H_DESC : MSA_2R_DESC_BASE<"nlzc.h", ctlz, MSA128HOpnd>; 2469class NLZC_W_DESC : MSA_2R_DESC_BASE<"nlzc.w", ctlz, MSA128WOpnd>; 2470class NLZC_D_DESC : MSA_2R_DESC_BASE<"nlzc.d", ctlz, MSA128DOpnd>; 2471 2472class NOR_V_DESC : MSA_VEC_DESC_BASE<"nor.v", MipsVNOR, MSA128BOpnd>; 2473class NOR_V_H_PSEUDO_DESC : MSA_VEC_PSEUDO_BASE<MipsVNOR, MSA128HOpnd>; 2474class NOR_V_W_PSEUDO_DESC : MSA_VEC_PSEUDO_BASE<MipsVNOR, MSA128WOpnd>; 2475class NOR_V_D_PSEUDO_DESC : MSA_VEC_PSEUDO_BASE<MipsVNOR, MSA128DOpnd>; 2476 2477class NORI_B_DESC : MSA_I8_DESC_BASE<"nori.b", MipsVNOR, vsplati8_uimm8, 2478 MSA128BOpnd>; 2479 2480class OR_V_DESC : MSA_VEC_DESC_BASE<"or.v", or, MSA128BOpnd>; 2481class OR_V_H_PSEUDO_DESC : MSA_VEC_PSEUDO_BASE<or, MSA128HOpnd>; 2482class OR_V_W_PSEUDO_DESC : MSA_VEC_PSEUDO_BASE<or, MSA128WOpnd>; 2483class OR_V_D_PSEUDO_DESC : MSA_VEC_PSEUDO_BASE<or, MSA128DOpnd>; 2484 2485class ORI_B_DESC : MSA_I8_DESC_BASE<"ori.b", or, vsplati8_uimm8, MSA128BOpnd>; 2486 2487class PCKEV_B_DESC : MSA_3R_DESC_BASE<"pckev.b", MipsPCKEV, MSA128BOpnd>; 2488class PCKEV_H_DESC : MSA_3R_DESC_BASE<"pckev.h", MipsPCKEV, MSA128HOpnd>; 2489class PCKEV_W_DESC : MSA_3R_DESC_BASE<"pckev.w", MipsPCKEV, MSA128WOpnd>; 2490class PCKEV_D_DESC : MSA_3R_DESC_BASE<"pckev.d", MipsPCKEV, MSA128DOpnd>; 2491 2492class PCKOD_B_DESC : MSA_3R_DESC_BASE<"pckod.b", MipsPCKOD, MSA128BOpnd>; 2493class PCKOD_H_DESC : MSA_3R_DESC_BASE<"pckod.h", MipsPCKOD, MSA128HOpnd>; 2494class PCKOD_W_DESC : MSA_3R_DESC_BASE<"pckod.w", MipsPCKOD, MSA128WOpnd>; 2495class PCKOD_D_DESC : MSA_3R_DESC_BASE<"pckod.d", MipsPCKOD, MSA128DOpnd>; 2496 2497class PCNT_B_DESC : MSA_2R_DESC_BASE<"pcnt.b", ctpop, MSA128BOpnd>; 2498class PCNT_H_DESC : MSA_2R_DESC_BASE<"pcnt.h", ctpop, MSA128HOpnd>; 2499class PCNT_W_DESC : MSA_2R_DESC_BASE<"pcnt.w", ctpop, MSA128WOpnd>; 2500class PCNT_D_DESC : MSA_2R_DESC_BASE<"pcnt.d", ctpop, MSA128DOpnd>; 2501 2502class SAT_S_B_DESC : MSA_BIT_X_DESC_BASE<"sat_s.b", int_mips_sat_s_b, uimm3, 2503 immZExt3, MSA128BOpnd>; 2504class SAT_S_H_DESC : MSA_BIT_X_DESC_BASE<"sat_s.h", int_mips_sat_s_h, uimm4, 2505 immZExt4, MSA128HOpnd>; 2506class SAT_S_W_DESC : MSA_BIT_X_DESC_BASE<"sat_s.w", int_mips_sat_s_w, uimm5, 2507 immZExt5, MSA128WOpnd>; 2508class SAT_S_D_DESC : MSA_BIT_X_DESC_BASE<"sat_s.d", int_mips_sat_s_d, uimm6, 2509 immZExt6, MSA128DOpnd>; 2510 2511class SAT_U_B_DESC : MSA_BIT_X_DESC_BASE<"sat_u.b", int_mips_sat_u_b, uimm3, 2512 immZExt3, MSA128BOpnd>; 2513class SAT_U_H_DESC : MSA_BIT_X_DESC_BASE<"sat_u.h", int_mips_sat_u_h, uimm4, 2514 immZExt4, MSA128HOpnd>; 2515class SAT_U_W_DESC : MSA_BIT_X_DESC_BASE<"sat_u.w", int_mips_sat_u_w, uimm5, 2516 immZExt5, MSA128WOpnd>; 2517class SAT_U_D_DESC : MSA_BIT_X_DESC_BASE<"sat_u.d", int_mips_sat_u_d, uimm6, 2518 immZExt6, MSA128DOpnd>; 2519 2520class SHF_B_DESC : MSA_I8_SHF_DESC_BASE<"shf.b", MSA128BOpnd>; 2521class SHF_H_DESC : MSA_I8_SHF_DESC_BASE<"shf.h", MSA128HOpnd>; 2522class SHF_W_DESC : MSA_I8_SHF_DESC_BASE<"shf.w", MSA128WOpnd>; 2523 2524class SLD_B_DESC : MSA_3R_SLD_DESC_BASE<"sld.b", int_mips_sld_b, MSA128BOpnd>; 2525class SLD_H_DESC : MSA_3R_SLD_DESC_BASE<"sld.h", int_mips_sld_h, MSA128HOpnd>; 2526class SLD_W_DESC : MSA_3R_SLD_DESC_BASE<"sld.w", int_mips_sld_w, MSA128WOpnd>; 2527class SLD_D_DESC : MSA_3R_SLD_DESC_BASE<"sld.d", int_mips_sld_d, MSA128DOpnd>; 2528 2529class SLDI_B_DESC : MSA_ELM_SLD_DESC_BASE<"sldi.b", int_mips_sldi_b, 2530 MSA128BOpnd, MSA128BOpnd, uimm4, 2531 immZExt4>; 2532class SLDI_H_DESC : MSA_ELM_SLD_DESC_BASE<"sldi.h", int_mips_sldi_h, 2533 MSA128HOpnd, MSA128HOpnd, uimm3, 2534 immZExt3>; 2535class SLDI_W_DESC : MSA_ELM_SLD_DESC_BASE<"sldi.w", int_mips_sldi_w, 2536 MSA128WOpnd, MSA128WOpnd, uimm2, 2537 immZExt2>; 2538class SLDI_D_DESC : MSA_ELM_SLD_DESC_BASE<"sldi.d", int_mips_sldi_d, 2539 MSA128DOpnd, MSA128DOpnd, uimm1, 2540 immZExt1>; 2541 2542class SLL_B_DESC : MSA_3R_DESC_BASE<"sll.b", shl, MSA128BOpnd>; 2543class SLL_H_DESC : MSA_3R_DESC_BASE<"sll.h", shl, MSA128HOpnd>; 2544class SLL_W_DESC : MSA_3R_DESC_BASE<"sll.w", shl, MSA128WOpnd>; 2545class SLL_D_DESC : MSA_3R_DESC_BASE<"sll.d", shl, MSA128DOpnd>; 2546 2547class SLLI_B_DESC : MSA_BIT_SPLAT_DESC_BASE<"slli.b", shl, vsplati8_uimm3, 2548 MSA128BOpnd>; 2549class SLLI_H_DESC : MSA_BIT_SPLAT_DESC_BASE<"slli.h", shl, vsplati16_uimm4, 2550 MSA128HOpnd>; 2551class SLLI_W_DESC : MSA_BIT_SPLAT_DESC_BASE<"slli.w", shl, vsplati32_uimm5, 2552 MSA128WOpnd>; 2553class SLLI_D_DESC : MSA_BIT_SPLAT_DESC_BASE<"slli.d", shl, vsplati64_uimm6, 2554 MSA128DOpnd>; 2555 2556class SPLAT_B_DESC : MSA_3R_SPLAT_DESC_BASE<"splat.b", vsplati8_elt, 2557 MSA128BOpnd>; 2558class SPLAT_H_DESC : MSA_3R_SPLAT_DESC_BASE<"splat.h", vsplati16_elt, 2559 MSA128HOpnd>; 2560class SPLAT_W_DESC : MSA_3R_SPLAT_DESC_BASE<"splat.w", vsplati32_elt, 2561 MSA128WOpnd>; 2562class SPLAT_D_DESC : MSA_3R_SPLAT_DESC_BASE<"splat.d", vsplati64_elt, 2563 MSA128DOpnd>; 2564 2565class SPLATI_B_DESC : MSA_ELM_SPLAT_DESC_BASE<"splati.b", vsplati8_uimm4, 2566 MSA128BOpnd>; 2567class SPLATI_H_DESC : MSA_ELM_SPLAT_DESC_BASE<"splati.h", vsplati16_uimm3, 2568 MSA128HOpnd>; 2569class SPLATI_W_DESC : MSA_ELM_SPLAT_DESC_BASE<"splati.w", vsplati32_uimm2, 2570 MSA128WOpnd>; 2571class SPLATI_D_DESC : MSA_ELM_SPLAT_DESC_BASE<"splati.d", vsplati64_uimm1, 2572 MSA128DOpnd>; 2573 2574class SRA_B_DESC : MSA_3R_DESC_BASE<"sra.b", sra, MSA128BOpnd>; 2575class SRA_H_DESC : MSA_3R_DESC_BASE<"sra.h", sra, MSA128HOpnd>; 2576class SRA_W_DESC : MSA_3R_DESC_BASE<"sra.w", sra, MSA128WOpnd>; 2577class SRA_D_DESC : MSA_3R_DESC_BASE<"sra.d", sra, MSA128DOpnd>; 2578 2579class SRAI_B_DESC : MSA_BIT_SPLAT_DESC_BASE<"srai.b", sra, vsplati8_uimm3, 2580 MSA128BOpnd>; 2581class SRAI_H_DESC : MSA_BIT_SPLAT_DESC_BASE<"srai.h", sra, vsplati16_uimm4, 2582 MSA128HOpnd>; 2583class SRAI_W_DESC : MSA_BIT_SPLAT_DESC_BASE<"srai.w", sra, vsplati32_uimm5, 2584 MSA128WOpnd>; 2585class SRAI_D_DESC : MSA_BIT_SPLAT_DESC_BASE<"srai.d", sra, vsplati64_uimm6, 2586 MSA128DOpnd>; 2587 2588class SRAR_B_DESC : MSA_3R_DESC_BASE<"srar.b", int_mips_srar_b, MSA128BOpnd>; 2589class SRAR_H_DESC : MSA_3R_DESC_BASE<"srar.h", int_mips_srar_h, MSA128HOpnd>; 2590class SRAR_W_DESC : MSA_3R_DESC_BASE<"srar.w", int_mips_srar_w, MSA128WOpnd>; 2591class SRAR_D_DESC : MSA_3R_DESC_BASE<"srar.d", int_mips_srar_d, MSA128DOpnd>; 2592 2593class SRARI_B_DESC : MSA_BIT_X_DESC_BASE<"srari.b", int_mips_srari_b, uimm3, 2594 immZExt3, MSA128BOpnd>; 2595class SRARI_H_DESC : MSA_BIT_X_DESC_BASE<"srari.h", int_mips_srari_h, uimm4, 2596 immZExt4, MSA128HOpnd>; 2597class SRARI_W_DESC : MSA_BIT_X_DESC_BASE<"srari.w", int_mips_srari_w, uimm5, 2598 immZExt5, MSA128WOpnd>; 2599class SRARI_D_DESC : MSA_BIT_X_DESC_BASE<"srari.d", int_mips_srari_d, uimm6, 2600 immZExt6, MSA128DOpnd>; 2601 2602class SRL_B_DESC : MSA_3R_DESC_BASE<"srl.b", srl, MSA128BOpnd>; 2603class SRL_H_DESC : MSA_3R_DESC_BASE<"srl.h", srl, MSA128HOpnd>; 2604class SRL_W_DESC : MSA_3R_DESC_BASE<"srl.w", srl, MSA128WOpnd>; 2605class SRL_D_DESC : MSA_3R_DESC_BASE<"srl.d", srl, MSA128DOpnd>; 2606 2607class SRLI_B_DESC : MSA_BIT_SPLAT_DESC_BASE<"srli.b", srl, vsplati8_uimm3, 2608 MSA128BOpnd>; 2609class SRLI_H_DESC : MSA_BIT_SPLAT_DESC_BASE<"srli.h", srl, vsplati16_uimm4, 2610 MSA128HOpnd>; 2611class SRLI_W_DESC : MSA_BIT_SPLAT_DESC_BASE<"srli.w", srl, vsplati32_uimm5, 2612 MSA128WOpnd>; 2613class SRLI_D_DESC : MSA_BIT_SPLAT_DESC_BASE<"srli.d", srl, vsplati64_uimm6, 2614 MSA128DOpnd>; 2615 2616class SRLR_B_DESC : MSA_3R_DESC_BASE<"srlr.b", int_mips_srlr_b, MSA128BOpnd>; 2617class SRLR_H_DESC : MSA_3R_DESC_BASE<"srlr.h", int_mips_srlr_h, MSA128HOpnd>; 2618class SRLR_W_DESC : MSA_3R_DESC_BASE<"srlr.w", int_mips_srlr_w, MSA128WOpnd>; 2619class SRLR_D_DESC : MSA_3R_DESC_BASE<"srlr.d", int_mips_srlr_d, MSA128DOpnd>; 2620 2621class SRLRI_B_DESC : MSA_BIT_X_DESC_BASE<"srlri.b", int_mips_srlri_b, uimm3, 2622 immZExt3, MSA128BOpnd>; 2623class SRLRI_H_DESC : MSA_BIT_X_DESC_BASE<"srlri.h", int_mips_srlri_h, uimm4, 2624 immZExt4, MSA128HOpnd>; 2625class SRLRI_W_DESC : MSA_BIT_X_DESC_BASE<"srlri.w", int_mips_srlri_w, uimm5, 2626 immZExt5, MSA128WOpnd>; 2627class SRLRI_D_DESC : MSA_BIT_X_DESC_BASE<"srlri.d", int_mips_srlri_d, uimm6, 2628 immZExt6, MSA128DOpnd>; 2629 2630class ST_DESC_BASE<string instr_asm, SDPatternOperator OpNode, 2631 ValueType TyNode, RegisterOperand ROWD, 2632 Operand MemOpnd, ComplexPattern Addr = addrimm10, 2633 InstrItinClass itin = NoItinerary> { 2634 dag OutOperandList = (outs); 2635 dag InOperandList = (ins ROWD:$wd, MemOpnd:$addr); 2636 string AsmString = !strconcat(instr_asm, "\t$wd, $addr"); 2637 list<dag> Pattern = [(OpNode (TyNode ROWD:$wd), Addr:$addr)]; 2638 InstrItinClass Itinerary = itin; 2639 string DecoderMethod = "DecodeMSA128Mem"; 2640} 2641 2642class ST_B_DESC : ST_DESC_BASE<"st.b", store, v16i8, MSA128BOpnd, mem_simm10>; 2643class ST_H_DESC : ST_DESC_BASE<"st.h", store, v8i16, MSA128HOpnd, 2644 mem_simm10_lsl1, addrimm10lsl1>; 2645class ST_W_DESC : ST_DESC_BASE<"st.w", store, v4i32, MSA128WOpnd, 2646 mem_simm10_lsl2, addrimm10lsl2>; 2647class ST_D_DESC : ST_DESC_BASE<"st.d", store, v2i64, MSA128DOpnd, 2648 mem_simm10_lsl3, addrimm10lsl3>; 2649 2650class SUBS_S_B_DESC : MSA_3R_DESC_BASE<"subs_s.b", int_mips_subs_s_b, 2651 MSA128BOpnd>; 2652class SUBS_S_H_DESC : MSA_3R_DESC_BASE<"subs_s.h", int_mips_subs_s_h, 2653 MSA128HOpnd>; 2654class SUBS_S_W_DESC : MSA_3R_DESC_BASE<"subs_s.w", int_mips_subs_s_w, 2655 MSA128WOpnd>; 2656class SUBS_S_D_DESC : MSA_3R_DESC_BASE<"subs_s.d", int_mips_subs_s_d, 2657 MSA128DOpnd>; 2658 2659class SUBS_U_B_DESC : MSA_3R_DESC_BASE<"subs_u.b", int_mips_subs_u_b, 2660 MSA128BOpnd>; 2661class SUBS_U_H_DESC : MSA_3R_DESC_BASE<"subs_u.h", int_mips_subs_u_h, 2662 MSA128HOpnd>; 2663class SUBS_U_W_DESC : MSA_3R_DESC_BASE<"subs_u.w", int_mips_subs_u_w, 2664 MSA128WOpnd>; 2665class SUBS_U_D_DESC : MSA_3R_DESC_BASE<"subs_u.d", int_mips_subs_u_d, 2666 MSA128DOpnd>; 2667 2668class SUBSUS_U_B_DESC : MSA_3R_DESC_BASE<"subsus_u.b", int_mips_subsus_u_b, 2669 MSA128BOpnd>; 2670class SUBSUS_U_H_DESC : MSA_3R_DESC_BASE<"subsus_u.h", int_mips_subsus_u_h, 2671 MSA128HOpnd>; 2672class SUBSUS_U_W_DESC : MSA_3R_DESC_BASE<"subsus_u.w", int_mips_subsus_u_w, 2673 MSA128WOpnd>; 2674class SUBSUS_U_D_DESC : MSA_3R_DESC_BASE<"subsus_u.d", int_mips_subsus_u_d, 2675 MSA128DOpnd>; 2676 2677class SUBSUU_S_B_DESC : MSA_3R_DESC_BASE<"subsuu_s.b", int_mips_subsuu_s_b, 2678 MSA128BOpnd>; 2679class SUBSUU_S_H_DESC : MSA_3R_DESC_BASE<"subsuu_s.h", int_mips_subsuu_s_h, 2680 MSA128HOpnd>; 2681class SUBSUU_S_W_DESC : MSA_3R_DESC_BASE<"subsuu_s.w", int_mips_subsuu_s_w, 2682 MSA128WOpnd>; 2683class SUBSUU_S_D_DESC : MSA_3R_DESC_BASE<"subsuu_s.d", int_mips_subsuu_s_d, 2684 MSA128DOpnd>; 2685 2686class SUBV_B_DESC : MSA_3R_DESC_BASE<"subv.b", sub, MSA128BOpnd>; 2687class SUBV_H_DESC : MSA_3R_DESC_BASE<"subv.h", sub, MSA128HOpnd>; 2688class SUBV_W_DESC : MSA_3R_DESC_BASE<"subv.w", sub, MSA128WOpnd>; 2689class SUBV_D_DESC : MSA_3R_DESC_BASE<"subv.d", sub, MSA128DOpnd>; 2690 2691class SUBVI_B_DESC : MSA_I5_DESC_BASE<"subvi.b", sub, vsplati8_uimm5, 2692 MSA128BOpnd>; 2693class SUBVI_H_DESC : MSA_I5_DESC_BASE<"subvi.h", sub, vsplati16_uimm5, 2694 MSA128HOpnd>; 2695class SUBVI_W_DESC : MSA_I5_DESC_BASE<"subvi.w", sub, vsplati32_uimm5, 2696 MSA128WOpnd>; 2697class SUBVI_D_DESC : MSA_I5_DESC_BASE<"subvi.d", sub, vsplati64_uimm5, 2698 MSA128DOpnd>; 2699 2700class VSHF_B_DESC : MSA_3R_VSHF_DESC_BASE<"vshf.b", MSA128BOpnd>; 2701class VSHF_H_DESC : MSA_3R_VSHF_DESC_BASE<"vshf.h", MSA128HOpnd>; 2702class VSHF_W_DESC : MSA_3R_VSHF_DESC_BASE<"vshf.w", MSA128WOpnd>; 2703class VSHF_D_DESC : MSA_3R_VSHF_DESC_BASE<"vshf.d", MSA128DOpnd>; 2704 2705class XOR_V_DESC : MSA_VEC_DESC_BASE<"xor.v", xor, MSA128BOpnd>; 2706class XOR_V_H_PSEUDO_DESC : MSA_VEC_PSEUDO_BASE<xor, MSA128HOpnd>; 2707class XOR_V_W_PSEUDO_DESC : MSA_VEC_PSEUDO_BASE<xor, MSA128WOpnd>; 2708class XOR_V_D_PSEUDO_DESC : MSA_VEC_PSEUDO_BASE<xor, MSA128DOpnd>; 2709 2710class XORI_B_DESC : MSA_I8_DESC_BASE<"xori.b", xor, vsplati8_uimm8, 2711 MSA128BOpnd>; 2712 2713// Instruction defs. 2714def ADD_A_B : ADD_A_B_ENC, ADD_A_B_DESC; 2715def ADD_A_H : ADD_A_H_ENC, ADD_A_H_DESC; 2716def ADD_A_W : ADD_A_W_ENC, ADD_A_W_DESC; 2717def ADD_A_D : ADD_A_D_ENC, ADD_A_D_DESC; 2718 2719def ADDS_A_B : ADDS_A_B_ENC, ADDS_A_B_DESC; 2720def ADDS_A_H : ADDS_A_H_ENC, ADDS_A_H_DESC; 2721def ADDS_A_W : ADDS_A_W_ENC, ADDS_A_W_DESC; 2722def ADDS_A_D : ADDS_A_D_ENC, ADDS_A_D_DESC; 2723 2724def ADDS_S_B : ADDS_S_B_ENC, ADDS_S_B_DESC; 2725def ADDS_S_H : ADDS_S_H_ENC, ADDS_S_H_DESC; 2726def ADDS_S_W : ADDS_S_W_ENC, ADDS_S_W_DESC; 2727def ADDS_S_D : ADDS_S_D_ENC, ADDS_S_D_DESC; 2728 2729def ADDS_U_B : ADDS_U_B_ENC, ADDS_U_B_DESC; 2730def ADDS_U_H : ADDS_U_H_ENC, ADDS_U_H_DESC; 2731def ADDS_U_W : ADDS_U_W_ENC, ADDS_U_W_DESC; 2732def ADDS_U_D : ADDS_U_D_ENC, ADDS_U_D_DESC; 2733 2734def ADDV_B : ADDV_B_ENC, ADDV_B_DESC; 2735def ADDV_H : ADDV_H_ENC, ADDV_H_DESC; 2736def ADDV_W : ADDV_W_ENC, ADDV_W_DESC; 2737def ADDV_D : ADDV_D_ENC, ADDV_D_DESC; 2738 2739def ADDVI_B : ADDVI_B_ENC, ADDVI_B_DESC; 2740def ADDVI_H : ADDVI_H_ENC, ADDVI_H_DESC; 2741def ADDVI_W : ADDVI_W_ENC, ADDVI_W_DESC; 2742def ADDVI_D : ADDVI_D_ENC, ADDVI_D_DESC; 2743 2744def AND_V : AND_V_ENC, AND_V_DESC; 2745def AND_V_H_PSEUDO : AND_V_H_PSEUDO_DESC, 2746 PseudoInstExpansion<(AND_V MSA128BOpnd:$wd, 2747 MSA128BOpnd:$ws, 2748 MSA128BOpnd:$wt)>; 2749def AND_V_W_PSEUDO : AND_V_W_PSEUDO_DESC, 2750 PseudoInstExpansion<(AND_V MSA128BOpnd:$wd, 2751 MSA128BOpnd:$ws, 2752 MSA128BOpnd:$wt)>; 2753def AND_V_D_PSEUDO : AND_V_D_PSEUDO_DESC, 2754 PseudoInstExpansion<(AND_V MSA128BOpnd:$wd, 2755 MSA128BOpnd:$ws, 2756 MSA128BOpnd:$wt)>; 2757 2758def ANDI_B : ANDI_B_ENC, ANDI_B_DESC; 2759 2760def ASUB_S_B : ASUB_S_B_ENC, ASUB_S_B_DESC; 2761def ASUB_S_H : ASUB_S_H_ENC, ASUB_S_H_DESC; 2762def ASUB_S_W : ASUB_S_W_ENC, ASUB_S_W_DESC; 2763def ASUB_S_D : ASUB_S_D_ENC, ASUB_S_D_DESC; 2764 2765def ASUB_U_B : ASUB_U_B_ENC, ASUB_U_B_DESC; 2766def ASUB_U_H : ASUB_U_H_ENC, ASUB_U_H_DESC; 2767def ASUB_U_W : ASUB_U_W_ENC, ASUB_U_W_DESC; 2768def ASUB_U_D : ASUB_U_D_ENC, ASUB_U_D_DESC; 2769 2770def AVE_S_B : AVE_S_B_ENC, AVE_S_B_DESC; 2771def AVE_S_H : AVE_S_H_ENC, AVE_S_H_DESC; 2772def AVE_S_W : AVE_S_W_ENC, AVE_S_W_DESC; 2773def AVE_S_D : AVE_S_D_ENC, AVE_S_D_DESC; 2774 2775def AVE_U_B : AVE_U_B_ENC, AVE_U_B_DESC; 2776def AVE_U_H : AVE_U_H_ENC, AVE_U_H_DESC; 2777def AVE_U_W : AVE_U_W_ENC, AVE_U_W_DESC; 2778def AVE_U_D : AVE_U_D_ENC, AVE_U_D_DESC; 2779 2780def AVER_S_B : AVER_S_B_ENC, AVER_S_B_DESC; 2781def AVER_S_H : AVER_S_H_ENC, AVER_S_H_DESC; 2782def AVER_S_W : AVER_S_W_ENC, AVER_S_W_DESC; 2783def AVER_S_D : AVER_S_D_ENC, AVER_S_D_DESC; 2784 2785def AVER_U_B : AVER_U_B_ENC, AVER_U_B_DESC; 2786def AVER_U_H : AVER_U_H_ENC, AVER_U_H_DESC; 2787def AVER_U_W : AVER_U_W_ENC, AVER_U_W_DESC; 2788def AVER_U_D : AVER_U_D_ENC, AVER_U_D_DESC; 2789 2790def BCLR_B : BCLR_B_ENC, BCLR_B_DESC; 2791def BCLR_H : BCLR_H_ENC, BCLR_H_DESC; 2792def BCLR_W : BCLR_W_ENC, BCLR_W_DESC; 2793def BCLR_D : BCLR_D_ENC, BCLR_D_DESC; 2794 2795def BCLRI_B : BCLRI_B_ENC, BCLRI_B_DESC; 2796def BCLRI_H : BCLRI_H_ENC, BCLRI_H_DESC; 2797def BCLRI_W : BCLRI_W_ENC, BCLRI_W_DESC; 2798def BCLRI_D : BCLRI_D_ENC, BCLRI_D_DESC; 2799 2800def BINSL_B : BINSL_B_ENC, BINSL_B_DESC; 2801def BINSL_H : BINSL_H_ENC, BINSL_H_DESC; 2802def BINSL_W : BINSL_W_ENC, BINSL_W_DESC; 2803def BINSL_D : BINSL_D_ENC, BINSL_D_DESC; 2804 2805def BINSLI_B : BINSLI_B_ENC, BINSLI_B_DESC; 2806def BINSLI_H : BINSLI_H_ENC, BINSLI_H_DESC; 2807def BINSLI_W : BINSLI_W_ENC, BINSLI_W_DESC; 2808def BINSLI_D : BINSLI_D_ENC, BINSLI_D_DESC; 2809 2810def BINSR_B : BINSR_B_ENC, BINSR_B_DESC; 2811def BINSR_H : BINSR_H_ENC, BINSR_H_DESC; 2812def BINSR_W : BINSR_W_ENC, BINSR_W_DESC; 2813def BINSR_D : BINSR_D_ENC, BINSR_D_DESC; 2814 2815def BINSRI_B : BINSRI_B_ENC, BINSRI_B_DESC; 2816def BINSRI_H : BINSRI_H_ENC, BINSRI_H_DESC; 2817def BINSRI_W : BINSRI_W_ENC, BINSRI_W_DESC; 2818def BINSRI_D : BINSRI_D_ENC, BINSRI_D_DESC; 2819 2820def BMNZ_V : BMNZ_V_ENC, BMNZ_V_DESC; 2821 2822def BMNZI_B : BMNZI_B_ENC, BMNZI_B_DESC; 2823 2824def BMZ_V : BMZ_V_ENC, BMZ_V_DESC; 2825 2826def BMZI_B : BMZI_B_ENC, BMZI_B_DESC; 2827 2828def BNEG_B : BNEG_B_ENC, BNEG_B_DESC; 2829def BNEG_H : BNEG_H_ENC, BNEG_H_DESC; 2830def BNEG_W : BNEG_W_ENC, BNEG_W_DESC; 2831def BNEG_D : BNEG_D_ENC, BNEG_D_DESC; 2832 2833def BNEGI_B : BNEGI_B_ENC, BNEGI_B_DESC; 2834def BNEGI_H : BNEGI_H_ENC, BNEGI_H_DESC; 2835def BNEGI_W : BNEGI_W_ENC, BNEGI_W_DESC; 2836def BNEGI_D : BNEGI_D_ENC, BNEGI_D_DESC; 2837 2838def BNZ_B : BNZ_B_ENC, BNZ_B_DESC; 2839def BNZ_H : BNZ_H_ENC, BNZ_H_DESC; 2840def BNZ_W : BNZ_W_ENC, BNZ_W_DESC; 2841def BNZ_D : BNZ_D_ENC, BNZ_D_DESC; 2842 2843def BNZ_V : BNZ_V_ENC, BNZ_V_DESC; 2844 2845def BSEL_V : BSEL_V_ENC, BSEL_V_DESC; 2846 2847class MSA_BSEL_PSEUDO_BASE<RegisterOperand RO, ValueType Ty> : 2848 MSAPseudo<(outs RO:$wd), (ins RO:$wd_in, RO:$ws, RO:$wt), 2849 [(set RO:$wd, (Ty (vselect RO:$wd_in, RO:$wt, RO:$ws)))]>, 2850 // Note that vselect and BSEL_V treat the condition operand the opposite way 2851 // from each other. 2852 // (vselect cond, if_set, if_clear) 2853 // (BSEL_V cond, if_clear, if_set) 2854 PseudoInstExpansion<(BSEL_V MSA128BOpnd:$wd, MSA128BOpnd:$wd_in, 2855 MSA128BOpnd:$ws, MSA128BOpnd:$wt)> { 2856 let Constraints = "$wd_in = $wd"; 2857} 2858 2859def BSEL_H_PSEUDO : MSA_BSEL_PSEUDO_BASE<MSA128HOpnd, v8i16>; 2860def BSEL_W_PSEUDO : MSA_BSEL_PSEUDO_BASE<MSA128WOpnd, v4i32>; 2861def BSEL_D_PSEUDO : MSA_BSEL_PSEUDO_BASE<MSA128DOpnd, v2i64>; 2862def BSEL_FW_PSEUDO : MSA_BSEL_PSEUDO_BASE<MSA128WOpnd, v4f32>; 2863def BSEL_FD_PSEUDO : MSA_BSEL_PSEUDO_BASE<MSA128DOpnd, v2f64>; 2864 2865def BSELI_B : BSELI_B_ENC, BSELI_B_DESC; 2866 2867def BSET_B : BSET_B_ENC, BSET_B_DESC; 2868def BSET_H : BSET_H_ENC, BSET_H_DESC; 2869def BSET_W : BSET_W_ENC, BSET_W_DESC; 2870def BSET_D : BSET_D_ENC, BSET_D_DESC; 2871 2872def BSETI_B : BSETI_B_ENC, BSETI_B_DESC; 2873def BSETI_H : BSETI_H_ENC, BSETI_H_DESC; 2874def BSETI_W : BSETI_W_ENC, BSETI_W_DESC; 2875def BSETI_D : BSETI_D_ENC, BSETI_D_DESC; 2876 2877def BZ_B : BZ_B_ENC, BZ_B_DESC; 2878def BZ_H : BZ_H_ENC, BZ_H_DESC; 2879def BZ_W : BZ_W_ENC, BZ_W_DESC; 2880def BZ_D : BZ_D_ENC, BZ_D_DESC; 2881 2882def BZ_V : BZ_V_ENC, BZ_V_DESC; 2883 2884def CEQ_B : CEQ_B_ENC, CEQ_B_DESC; 2885def CEQ_H : CEQ_H_ENC, CEQ_H_DESC; 2886def CEQ_W : CEQ_W_ENC, CEQ_W_DESC; 2887def CEQ_D : CEQ_D_ENC, CEQ_D_DESC; 2888 2889def CEQI_B : CEQI_B_ENC, CEQI_B_DESC; 2890def CEQI_H : CEQI_H_ENC, CEQI_H_DESC; 2891def CEQI_W : CEQI_W_ENC, CEQI_W_DESC; 2892def CEQI_D : CEQI_D_ENC, CEQI_D_DESC; 2893 2894def CFCMSA : CFCMSA_ENC, CFCMSA_DESC; 2895 2896def CLE_S_B : CLE_S_B_ENC, CLE_S_B_DESC; 2897def CLE_S_H : CLE_S_H_ENC, CLE_S_H_DESC; 2898def CLE_S_W : CLE_S_W_ENC, CLE_S_W_DESC; 2899def CLE_S_D : CLE_S_D_ENC, CLE_S_D_DESC; 2900 2901def CLE_U_B : CLE_U_B_ENC, CLE_U_B_DESC; 2902def CLE_U_H : CLE_U_H_ENC, CLE_U_H_DESC; 2903def CLE_U_W : CLE_U_W_ENC, CLE_U_W_DESC; 2904def CLE_U_D : CLE_U_D_ENC, CLE_U_D_DESC; 2905 2906def CLEI_S_B : CLEI_S_B_ENC, CLEI_S_B_DESC; 2907def CLEI_S_H : CLEI_S_H_ENC, CLEI_S_H_DESC; 2908def CLEI_S_W : CLEI_S_W_ENC, CLEI_S_W_DESC; 2909def CLEI_S_D : CLEI_S_D_ENC, CLEI_S_D_DESC; 2910 2911def CLEI_U_B : CLEI_U_B_ENC, CLEI_U_B_DESC; 2912def CLEI_U_H : CLEI_U_H_ENC, CLEI_U_H_DESC; 2913def CLEI_U_W : CLEI_U_W_ENC, CLEI_U_W_DESC; 2914def CLEI_U_D : CLEI_U_D_ENC, CLEI_U_D_DESC; 2915 2916def CLT_S_B : CLT_S_B_ENC, CLT_S_B_DESC; 2917def CLT_S_H : CLT_S_H_ENC, CLT_S_H_DESC; 2918def CLT_S_W : CLT_S_W_ENC, CLT_S_W_DESC; 2919def CLT_S_D : CLT_S_D_ENC, CLT_S_D_DESC; 2920 2921def CLT_U_B : CLT_U_B_ENC, CLT_U_B_DESC; 2922def CLT_U_H : CLT_U_H_ENC, CLT_U_H_DESC; 2923def CLT_U_W : CLT_U_W_ENC, CLT_U_W_DESC; 2924def CLT_U_D : CLT_U_D_ENC, CLT_U_D_DESC; 2925 2926def CLTI_S_B : CLTI_S_B_ENC, CLTI_S_B_DESC; 2927def CLTI_S_H : CLTI_S_H_ENC, CLTI_S_H_DESC; 2928def CLTI_S_W : CLTI_S_W_ENC, CLTI_S_W_DESC; 2929def CLTI_S_D : CLTI_S_D_ENC, CLTI_S_D_DESC; 2930 2931def CLTI_U_B : CLTI_U_B_ENC, CLTI_U_B_DESC; 2932def CLTI_U_H : CLTI_U_H_ENC, CLTI_U_H_DESC; 2933def CLTI_U_W : CLTI_U_W_ENC, CLTI_U_W_DESC; 2934def CLTI_U_D : CLTI_U_D_ENC, CLTI_U_D_DESC; 2935 2936def COPY_S_B : COPY_S_B_ENC, COPY_S_B_DESC; 2937def COPY_S_H : COPY_S_H_ENC, COPY_S_H_DESC; 2938def COPY_S_W : COPY_S_W_ENC, COPY_S_W_DESC; 2939def COPY_S_D : COPY_S_D_ENC, COPY_S_D_DESC, ASE_MSA64; 2940 2941def COPY_U_B : COPY_U_B_ENC, COPY_U_B_DESC; 2942def COPY_U_H : COPY_U_H_ENC, COPY_U_H_DESC; 2943def COPY_U_W : COPY_U_W_ENC, COPY_U_W_DESC, ASE_MSA64; 2944 2945def COPY_FW_PSEUDO : COPY_FW_PSEUDO_DESC; 2946def COPY_FD_PSEUDO : COPY_FD_PSEUDO_DESC; 2947 2948def CTCMSA : CTCMSA_ENC, CTCMSA_DESC; 2949 2950def DIV_S_B : DIV_S_B_ENC, DIV_S_B_DESC; 2951def DIV_S_H : DIV_S_H_ENC, DIV_S_H_DESC; 2952def DIV_S_W : DIV_S_W_ENC, DIV_S_W_DESC; 2953def DIV_S_D : DIV_S_D_ENC, DIV_S_D_DESC; 2954 2955def DIV_U_B : DIV_U_B_ENC, DIV_U_B_DESC; 2956def DIV_U_H : DIV_U_H_ENC, DIV_U_H_DESC; 2957def DIV_U_W : DIV_U_W_ENC, DIV_U_W_DESC; 2958def DIV_U_D : DIV_U_D_ENC, DIV_U_D_DESC; 2959 2960def DOTP_S_H : DOTP_S_H_ENC, DOTP_S_H_DESC; 2961def DOTP_S_W : DOTP_S_W_ENC, DOTP_S_W_DESC; 2962def DOTP_S_D : DOTP_S_D_ENC, DOTP_S_D_DESC; 2963 2964def DOTP_U_H : DOTP_U_H_ENC, DOTP_U_H_DESC; 2965def DOTP_U_W : DOTP_U_W_ENC, DOTP_U_W_DESC; 2966def DOTP_U_D : DOTP_U_D_ENC, DOTP_U_D_DESC; 2967 2968def DPADD_S_H : DPADD_S_H_ENC, DPADD_S_H_DESC; 2969def DPADD_S_W : DPADD_S_W_ENC, DPADD_S_W_DESC; 2970def DPADD_S_D : DPADD_S_D_ENC, DPADD_S_D_DESC; 2971 2972def DPADD_U_H : DPADD_U_H_ENC, DPADD_U_H_DESC; 2973def DPADD_U_W : DPADD_U_W_ENC, DPADD_U_W_DESC; 2974def DPADD_U_D : DPADD_U_D_ENC, DPADD_U_D_DESC; 2975 2976def DPSUB_S_H : DPSUB_S_H_ENC, DPSUB_S_H_DESC; 2977def DPSUB_S_W : DPSUB_S_W_ENC, DPSUB_S_W_DESC; 2978def DPSUB_S_D : DPSUB_S_D_ENC, DPSUB_S_D_DESC; 2979 2980def DPSUB_U_H : DPSUB_U_H_ENC, DPSUB_U_H_DESC; 2981def DPSUB_U_W : DPSUB_U_W_ENC, DPSUB_U_W_DESC; 2982def DPSUB_U_D : DPSUB_U_D_ENC, DPSUB_U_D_DESC; 2983 2984def FADD_W : FADD_W_ENC, FADD_W_DESC; 2985def FADD_D : FADD_D_ENC, FADD_D_DESC; 2986 2987def FCAF_W : FCAF_W_ENC, FCAF_W_DESC; 2988def FCAF_D : FCAF_D_ENC, FCAF_D_DESC; 2989 2990def FCEQ_W : FCEQ_W_ENC, FCEQ_W_DESC; 2991def FCEQ_D : FCEQ_D_ENC, FCEQ_D_DESC; 2992 2993def FCLE_W : FCLE_W_ENC, FCLE_W_DESC; 2994def FCLE_D : FCLE_D_ENC, FCLE_D_DESC; 2995 2996def FCLT_W : FCLT_W_ENC, FCLT_W_DESC; 2997def FCLT_D : FCLT_D_ENC, FCLT_D_DESC; 2998 2999def FCLASS_W : FCLASS_W_ENC, FCLASS_W_DESC; 3000def FCLASS_D : FCLASS_D_ENC, FCLASS_D_DESC; 3001 3002def FCNE_W : FCNE_W_ENC, FCNE_W_DESC; 3003def FCNE_D : FCNE_D_ENC, FCNE_D_DESC; 3004 3005def FCOR_W : FCOR_W_ENC, FCOR_W_DESC; 3006def FCOR_D : FCOR_D_ENC, FCOR_D_DESC; 3007 3008def FCUEQ_W : FCUEQ_W_ENC, FCUEQ_W_DESC; 3009def FCUEQ_D : FCUEQ_D_ENC, FCUEQ_D_DESC; 3010 3011def FCULE_W : FCULE_W_ENC, FCULE_W_DESC; 3012def FCULE_D : FCULE_D_ENC, FCULE_D_DESC; 3013 3014def FCULT_W : FCULT_W_ENC, FCULT_W_DESC; 3015def FCULT_D : FCULT_D_ENC, FCULT_D_DESC; 3016 3017def FCUN_W : FCUN_W_ENC, FCUN_W_DESC; 3018def FCUN_D : FCUN_D_ENC, FCUN_D_DESC; 3019 3020def FCUNE_W : FCUNE_W_ENC, FCUNE_W_DESC; 3021def FCUNE_D : FCUNE_D_ENC, FCUNE_D_DESC; 3022 3023def FDIV_W : FDIV_W_ENC, FDIV_W_DESC; 3024def FDIV_D : FDIV_D_ENC, FDIV_D_DESC; 3025 3026def FEXDO_H : FEXDO_H_ENC, FEXDO_H_DESC; 3027def FEXDO_W : FEXDO_W_ENC, FEXDO_W_DESC; 3028 3029def FEXP2_W : FEXP2_W_ENC, FEXP2_W_DESC; 3030def FEXP2_D : FEXP2_D_ENC, FEXP2_D_DESC; 3031def FEXP2_W_1_PSEUDO : FEXP2_W_1_PSEUDO_DESC; 3032def FEXP2_D_1_PSEUDO : FEXP2_D_1_PSEUDO_DESC; 3033 3034def FEXUPL_W : FEXUPL_W_ENC, FEXUPL_W_DESC; 3035def FEXUPL_D : FEXUPL_D_ENC, FEXUPL_D_DESC; 3036 3037def FEXUPR_W : FEXUPR_W_ENC, FEXUPR_W_DESC; 3038def FEXUPR_D : FEXUPR_D_ENC, FEXUPR_D_DESC; 3039 3040def FFINT_S_W : FFINT_S_W_ENC, FFINT_S_W_DESC; 3041def FFINT_S_D : FFINT_S_D_ENC, FFINT_S_D_DESC; 3042 3043def FFINT_U_W : FFINT_U_W_ENC, FFINT_U_W_DESC; 3044def FFINT_U_D : FFINT_U_D_ENC, FFINT_U_D_DESC; 3045 3046def FFQL_W : FFQL_W_ENC, FFQL_W_DESC; 3047def FFQL_D : FFQL_D_ENC, FFQL_D_DESC; 3048 3049def FFQR_W : FFQR_W_ENC, FFQR_W_DESC; 3050def FFQR_D : FFQR_D_ENC, FFQR_D_DESC; 3051 3052def FILL_B : FILL_B_ENC, FILL_B_DESC; 3053def FILL_H : FILL_H_ENC, FILL_H_DESC; 3054def FILL_W : FILL_W_ENC, FILL_W_DESC; 3055def FILL_D : FILL_D_ENC, FILL_D_DESC, ASE_MSA64; 3056def FILL_FW_PSEUDO : FILL_FW_PSEUDO_DESC; 3057def FILL_FD_PSEUDO : FILL_FD_PSEUDO_DESC; 3058 3059def FLOG2_W : FLOG2_W_ENC, FLOG2_W_DESC; 3060def FLOG2_D : FLOG2_D_ENC, FLOG2_D_DESC; 3061 3062def FMADD_W : FMADD_W_ENC, FMADD_W_DESC; 3063def FMADD_D : FMADD_D_ENC, FMADD_D_DESC; 3064 3065def FMAX_W : FMAX_W_ENC, FMAX_W_DESC; 3066def FMAX_D : FMAX_D_ENC, FMAX_D_DESC; 3067 3068def FMAX_A_W : FMAX_A_W_ENC, FMAX_A_W_DESC; 3069def FMAX_A_D : FMAX_A_D_ENC, FMAX_A_D_DESC; 3070 3071def FMIN_W : FMIN_W_ENC, FMIN_W_DESC; 3072def FMIN_D : FMIN_D_ENC, FMIN_D_DESC; 3073 3074def FMIN_A_W : FMIN_A_W_ENC, FMIN_A_W_DESC; 3075def FMIN_A_D : FMIN_A_D_ENC, FMIN_A_D_DESC; 3076 3077def FMSUB_W : FMSUB_W_ENC, FMSUB_W_DESC; 3078def FMSUB_D : FMSUB_D_ENC, FMSUB_D_DESC; 3079 3080def FMUL_W : FMUL_W_ENC, FMUL_W_DESC; 3081def FMUL_D : FMUL_D_ENC, FMUL_D_DESC; 3082 3083def FRINT_W : FRINT_W_ENC, FRINT_W_DESC; 3084def FRINT_D : FRINT_D_ENC, FRINT_D_DESC; 3085 3086def FRCP_W : FRCP_W_ENC, FRCP_W_DESC; 3087def FRCP_D : FRCP_D_ENC, FRCP_D_DESC; 3088 3089def FRSQRT_W : FRSQRT_W_ENC, FRSQRT_W_DESC; 3090def FRSQRT_D : FRSQRT_D_ENC, FRSQRT_D_DESC; 3091 3092def FSAF_W : FSAF_W_ENC, FSAF_W_DESC; 3093def FSAF_D : FSAF_D_ENC, FSAF_D_DESC; 3094 3095def FSEQ_W : FSEQ_W_ENC, FSEQ_W_DESC; 3096def FSEQ_D : FSEQ_D_ENC, FSEQ_D_DESC; 3097 3098def FSLE_W : FSLE_W_ENC, FSLE_W_DESC; 3099def FSLE_D : FSLE_D_ENC, FSLE_D_DESC; 3100 3101def FSLT_W : FSLT_W_ENC, FSLT_W_DESC; 3102def FSLT_D : FSLT_D_ENC, FSLT_D_DESC; 3103 3104def FSNE_W : FSNE_W_ENC, FSNE_W_DESC; 3105def FSNE_D : FSNE_D_ENC, FSNE_D_DESC; 3106 3107def FSOR_W : FSOR_W_ENC, FSOR_W_DESC; 3108def FSOR_D : FSOR_D_ENC, FSOR_D_DESC; 3109 3110def FSQRT_W : FSQRT_W_ENC, FSQRT_W_DESC; 3111def FSQRT_D : FSQRT_D_ENC, FSQRT_D_DESC; 3112 3113def FSUB_W : FSUB_W_ENC, FSUB_W_DESC; 3114def FSUB_D : FSUB_D_ENC, FSUB_D_DESC; 3115 3116def FSUEQ_W : FSUEQ_W_ENC, FSUEQ_W_DESC; 3117def FSUEQ_D : FSUEQ_D_ENC, FSUEQ_D_DESC; 3118 3119def FSULE_W : FSULE_W_ENC, FSULE_W_DESC; 3120def FSULE_D : FSULE_D_ENC, FSULE_D_DESC; 3121 3122def FSULT_W : FSULT_W_ENC, FSULT_W_DESC; 3123def FSULT_D : FSULT_D_ENC, FSULT_D_DESC; 3124 3125def FSUN_W : FSUN_W_ENC, FSUN_W_DESC; 3126def FSUN_D : FSUN_D_ENC, FSUN_D_DESC; 3127 3128def FSUNE_W : FSUNE_W_ENC, FSUNE_W_DESC; 3129def FSUNE_D : FSUNE_D_ENC, FSUNE_D_DESC; 3130 3131def FTINT_S_W : FTINT_S_W_ENC, FTINT_S_W_DESC; 3132def FTINT_S_D : FTINT_S_D_ENC, FTINT_S_D_DESC; 3133 3134def FTINT_U_W : FTINT_U_W_ENC, FTINT_U_W_DESC; 3135def FTINT_U_D : FTINT_U_D_ENC, FTINT_U_D_DESC; 3136 3137def FTQ_H : FTQ_H_ENC, FTQ_H_DESC; 3138def FTQ_W : FTQ_W_ENC, FTQ_W_DESC; 3139 3140def FTRUNC_S_W : FTRUNC_S_W_ENC, FTRUNC_S_W_DESC; 3141def FTRUNC_S_D : FTRUNC_S_D_ENC, FTRUNC_S_D_DESC; 3142 3143def FTRUNC_U_W : FTRUNC_U_W_ENC, FTRUNC_U_W_DESC; 3144def FTRUNC_U_D : FTRUNC_U_D_ENC, FTRUNC_U_D_DESC; 3145 3146def HADD_S_H : HADD_S_H_ENC, HADD_S_H_DESC; 3147def HADD_S_W : HADD_S_W_ENC, HADD_S_W_DESC; 3148def HADD_S_D : HADD_S_D_ENC, HADD_S_D_DESC; 3149 3150def HADD_U_H : HADD_U_H_ENC, HADD_U_H_DESC; 3151def HADD_U_W : HADD_U_W_ENC, HADD_U_W_DESC; 3152def HADD_U_D : HADD_U_D_ENC, HADD_U_D_DESC; 3153 3154def HSUB_S_H : HSUB_S_H_ENC, HSUB_S_H_DESC; 3155def HSUB_S_W : HSUB_S_W_ENC, HSUB_S_W_DESC; 3156def HSUB_S_D : HSUB_S_D_ENC, HSUB_S_D_DESC; 3157 3158def HSUB_U_H : HSUB_U_H_ENC, HSUB_U_H_DESC; 3159def HSUB_U_W : HSUB_U_W_ENC, HSUB_U_W_DESC; 3160def HSUB_U_D : HSUB_U_D_ENC, HSUB_U_D_DESC; 3161 3162def ILVEV_B : ILVEV_B_ENC, ILVEV_B_DESC; 3163def ILVEV_H : ILVEV_H_ENC, ILVEV_H_DESC; 3164def ILVEV_W : ILVEV_W_ENC, ILVEV_W_DESC; 3165def ILVEV_D : ILVEV_D_ENC, ILVEV_D_DESC; 3166 3167def ILVL_B : ILVL_B_ENC, ILVL_B_DESC; 3168def ILVL_H : ILVL_H_ENC, ILVL_H_DESC; 3169def ILVL_W : ILVL_W_ENC, ILVL_W_DESC; 3170def ILVL_D : ILVL_D_ENC, ILVL_D_DESC; 3171 3172def ILVOD_B : ILVOD_B_ENC, ILVOD_B_DESC; 3173def ILVOD_H : ILVOD_H_ENC, ILVOD_H_DESC; 3174def ILVOD_W : ILVOD_W_ENC, ILVOD_W_DESC; 3175def ILVOD_D : ILVOD_D_ENC, ILVOD_D_DESC; 3176 3177def ILVR_B : ILVR_B_ENC, ILVR_B_DESC; 3178def ILVR_H : ILVR_H_ENC, ILVR_H_DESC; 3179def ILVR_W : ILVR_W_ENC, ILVR_W_DESC; 3180def ILVR_D : ILVR_D_ENC, ILVR_D_DESC; 3181 3182def INSERT_B : INSERT_B_ENC, INSERT_B_DESC; 3183def INSERT_H : INSERT_H_ENC, INSERT_H_DESC; 3184def INSERT_W : INSERT_W_ENC, INSERT_W_DESC; 3185def INSERT_D : INSERT_D_ENC, INSERT_D_DESC, ASE_MSA64; 3186 3187// INSERT_FW_PSEUDO defined after INSVE_W 3188// INSERT_FD_PSEUDO defined after INSVE_D 3189 3190// There is a fourth operand that is not present in the encoding. Use a 3191// custom decoder to get a chance to add it. 3192let DecoderMethod = "DecodeINSVE_DF" in { 3193 def INSVE_B : INSVE_B_ENC, INSVE_B_DESC; 3194 def INSVE_H : INSVE_H_ENC, INSVE_H_DESC; 3195 def INSVE_W : INSVE_W_ENC, INSVE_W_DESC; 3196 def INSVE_D : INSVE_D_ENC, INSVE_D_DESC; 3197} 3198 3199def INSERT_FW_PSEUDO : INSERT_FW_PSEUDO_DESC; 3200def INSERT_FD_PSEUDO : INSERT_FD_PSEUDO_DESC; 3201 3202def INSERT_B_VIDX_PSEUDO : INSERT_B_VIDX_PSEUDO_DESC; 3203def INSERT_H_VIDX_PSEUDO : INSERT_H_VIDX_PSEUDO_DESC; 3204def INSERT_W_VIDX_PSEUDO : INSERT_W_VIDX_PSEUDO_DESC; 3205def INSERT_D_VIDX_PSEUDO : INSERT_D_VIDX_PSEUDO_DESC; 3206def INSERT_FW_VIDX_PSEUDO : INSERT_FW_VIDX_PSEUDO_DESC; 3207def INSERT_FD_VIDX_PSEUDO : INSERT_FD_VIDX_PSEUDO_DESC; 3208 3209def INSERT_B_VIDX64_PSEUDO : INSERT_B_VIDX64_PSEUDO_DESC; 3210def INSERT_H_VIDX64_PSEUDO : INSERT_H_VIDX64_PSEUDO_DESC; 3211def INSERT_W_VIDX64_PSEUDO : INSERT_W_VIDX64_PSEUDO_DESC; 3212def INSERT_D_VIDX64_PSEUDO : INSERT_D_VIDX64_PSEUDO_DESC; 3213def INSERT_FW_VIDX64_PSEUDO : INSERT_FW_VIDX64_PSEUDO_DESC; 3214def INSERT_FD_VIDX64_PSEUDO : INSERT_FD_VIDX64_PSEUDO_DESC; 3215 3216def LD_B: LD_B_ENC, LD_B_DESC; 3217def LD_H: LD_H_ENC, LD_H_DESC; 3218def LD_W: LD_W_ENC, LD_W_DESC; 3219def LD_D: LD_D_ENC, LD_D_DESC; 3220 3221def LDI_B : LDI_B_ENC, LDI_B_DESC; 3222def LDI_H : LDI_H_ENC, LDI_H_DESC; 3223def LDI_W : LDI_W_ENC, LDI_W_DESC; 3224def LDI_D : LDI_D_ENC, LDI_D_DESC; 3225 3226def LSA : LSA_ENC, LSA_DESC; 3227def DLSA : DLSA_ENC, DLSA_DESC, ASE_MSA64; 3228 3229def MADD_Q_H : MADD_Q_H_ENC, MADD_Q_H_DESC; 3230def MADD_Q_W : MADD_Q_W_ENC, MADD_Q_W_DESC; 3231 3232def MADDR_Q_H : MADDR_Q_H_ENC, MADDR_Q_H_DESC; 3233def MADDR_Q_W : MADDR_Q_W_ENC, MADDR_Q_W_DESC; 3234 3235def MADDV_B : MADDV_B_ENC, MADDV_B_DESC; 3236def MADDV_H : MADDV_H_ENC, MADDV_H_DESC; 3237def MADDV_W : MADDV_W_ENC, MADDV_W_DESC; 3238def MADDV_D : MADDV_D_ENC, MADDV_D_DESC; 3239 3240def MAX_A_B : MAX_A_B_ENC, MAX_A_B_DESC; 3241def MAX_A_H : MAX_A_H_ENC, MAX_A_H_DESC; 3242def MAX_A_W : MAX_A_W_ENC, MAX_A_W_DESC; 3243def MAX_A_D : MAX_A_D_ENC, MAX_A_D_DESC; 3244 3245def MAX_S_B : MAX_S_B_ENC, MAX_S_B_DESC; 3246def MAX_S_H : MAX_S_H_ENC, MAX_S_H_DESC; 3247def MAX_S_W : MAX_S_W_ENC, MAX_S_W_DESC; 3248def MAX_S_D : MAX_S_D_ENC, MAX_S_D_DESC; 3249 3250def MAX_U_B : MAX_U_B_ENC, MAX_U_B_DESC; 3251def MAX_U_H : MAX_U_H_ENC, MAX_U_H_DESC; 3252def MAX_U_W : MAX_U_W_ENC, MAX_U_W_DESC; 3253def MAX_U_D : MAX_U_D_ENC, MAX_U_D_DESC; 3254 3255def MAXI_S_B : MAXI_S_B_ENC, MAXI_S_B_DESC; 3256def MAXI_S_H : MAXI_S_H_ENC, MAXI_S_H_DESC; 3257def MAXI_S_W : MAXI_S_W_ENC, MAXI_S_W_DESC; 3258def MAXI_S_D : MAXI_S_D_ENC, MAXI_S_D_DESC; 3259 3260def MAXI_U_B : MAXI_U_B_ENC, MAXI_U_B_DESC; 3261def MAXI_U_H : MAXI_U_H_ENC, MAXI_U_H_DESC; 3262def MAXI_U_W : MAXI_U_W_ENC, MAXI_U_W_DESC; 3263def MAXI_U_D : MAXI_U_D_ENC, MAXI_U_D_DESC; 3264 3265def MIN_A_B : MIN_A_B_ENC, MIN_A_B_DESC; 3266def MIN_A_H : MIN_A_H_ENC, MIN_A_H_DESC; 3267def MIN_A_W : MIN_A_W_ENC, MIN_A_W_DESC; 3268def MIN_A_D : MIN_A_D_ENC, MIN_A_D_DESC; 3269 3270def MIN_S_B : MIN_S_B_ENC, MIN_S_B_DESC; 3271def MIN_S_H : MIN_S_H_ENC, MIN_S_H_DESC; 3272def MIN_S_W : MIN_S_W_ENC, MIN_S_W_DESC; 3273def MIN_S_D : MIN_S_D_ENC, MIN_S_D_DESC; 3274 3275def MIN_U_B : MIN_U_B_ENC, MIN_U_B_DESC; 3276def MIN_U_H : MIN_U_H_ENC, MIN_U_H_DESC; 3277def MIN_U_W : MIN_U_W_ENC, MIN_U_W_DESC; 3278def MIN_U_D : MIN_U_D_ENC, MIN_U_D_DESC; 3279 3280def MINI_S_B : MINI_S_B_ENC, MINI_S_B_DESC; 3281def MINI_S_H : MINI_S_H_ENC, MINI_S_H_DESC; 3282def MINI_S_W : MINI_S_W_ENC, MINI_S_W_DESC; 3283def MINI_S_D : MINI_S_D_ENC, MINI_S_D_DESC; 3284 3285def MINI_U_B : MINI_U_B_ENC, MINI_U_B_DESC; 3286def MINI_U_H : MINI_U_H_ENC, MINI_U_H_DESC; 3287def MINI_U_W : MINI_U_W_ENC, MINI_U_W_DESC; 3288def MINI_U_D : MINI_U_D_ENC, MINI_U_D_DESC; 3289 3290def MOD_S_B : MOD_S_B_ENC, MOD_S_B_DESC; 3291def MOD_S_H : MOD_S_H_ENC, MOD_S_H_DESC; 3292def MOD_S_W : MOD_S_W_ENC, MOD_S_W_DESC; 3293def MOD_S_D : MOD_S_D_ENC, MOD_S_D_DESC; 3294 3295def MOD_U_B : MOD_U_B_ENC, MOD_U_B_DESC; 3296def MOD_U_H : MOD_U_H_ENC, MOD_U_H_DESC; 3297def MOD_U_W : MOD_U_W_ENC, MOD_U_W_DESC; 3298def MOD_U_D : MOD_U_D_ENC, MOD_U_D_DESC; 3299 3300def MOVE_V : MOVE_V_ENC, MOVE_V_DESC; 3301 3302def MSUB_Q_H : MSUB_Q_H_ENC, MSUB_Q_H_DESC; 3303def MSUB_Q_W : MSUB_Q_W_ENC, MSUB_Q_W_DESC; 3304 3305def MSUBR_Q_H : MSUBR_Q_H_ENC, MSUBR_Q_H_DESC; 3306def MSUBR_Q_W : MSUBR_Q_W_ENC, MSUBR_Q_W_DESC; 3307 3308def MSUBV_B : MSUBV_B_ENC, MSUBV_B_DESC; 3309def MSUBV_H : MSUBV_H_ENC, MSUBV_H_DESC; 3310def MSUBV_W : MSUBV_W_ENC, MSUBV_W_DESC; 3311def MSUBV_D : MSUBV_D_ENC, MSUBV_D_DESC; 3312 3313def MUL_Q_H : MUL_Q_H_ENC, MUL_Q_H_DESC; 3314def MUL_Q_W : MUL_Q_W_ENC, MUL_Q_W_DESC; 3315 3316def MULR_Q_H : MULR_Q_H_ENC, MULR_Q_H_DESC; 3317def MULR_Q_W : MULR_Q_W_ENC, MULR_Q_W_DESC; 3318 3319def MULV_B : MULV_B_ENC, MULV_B_DESC; 3320def MULV_H : MULV_H_ENC, MULV_H_DESC; 3321def MULV_W : MULV_W_ENC, MULV_W_DESC; 3322def MULV_D : MULV_D_ENC, MULV_D_DESC; 3323 3324def NLOC_B : NLOC_B_ENC, NLOC_B_DESC; 3325def NLOC_H : NLOC_H_ENC, NLOC_H_DESC; 3326def NLOC_W : NLOC_W_ENC, NLOC_W_DESC; 3327def NLOC_D : NLOC_D_ENC, NLOC_D_DESC; 3328 3329def NLZC_B : NLZC_B_ENC, NLZC_B_DESC; 3330def NLZC_H : NLZC_H_ENC, NLZC_H_DESC; 3331def NLZC_W : NLZC_W_ENC, NLZC_W_DESC; 3332def NLZC_D : NLZC_D_ENC, NLZC_D_DESC; 3333 3334def NOR_V : NOR_V_ENC, NOR_V_DESC; 3335def NOR_V_H_PSEUDO : NOR_V_H_PSEUDO_DESC, 3336 PseudoInstExpansion<(NOR_V MSA128BOpnd:$wd, 3337 MSA128BOpnd:$ws, 3338 MSA128BOpnd:$wt)>; 3339def NOR_V_W_PSEUDO : NOR_V_W_PSEUDO_DESC, 3340 PseudoInstExpansion<(NOR_V MSA128BOpnd:$wd, 3341 MSA128BOpnd:$ws, 3342 MSA128BOpnd:$wt)>; 3343def NOR_V_D_PSEUDO : NOR_V_D_PSEUDO_DESC, 3344 PseudoInstExpansion<(NOR_V MSA128BOpnd:$wd, 3345 MSA128BOpnd:$ws, 3346 MSA128BOpnd:$wt)>; 3347 3348def NORI_B : NORI_B_ENC, NORI_B_DESC; 3349 3350def OR_V : OR_V_ENC, OR_V_DESC; 3351def OR_V_H_PSEUDO : OR_V_H_PSEUDO_DESC, 3352 PseudoInstExpansion<(OR_V MSA128BOpnd:$wd, 3353 MSA128BOpnd:$ws, 3354 MSA128BOpnd:$wt)>; 3355def OR_V_W_PSEUDO : OR_V_W_PSEUDO_DESC, 3356 PseudoInstExpansion<(OR_V MSA128BOpnd:$wd, 3357 MSA128BOpnd:$ws, 3358 MSA128BOpnd:$wt)>; 3359def OR_V_D_PSEUDO : OR_V_D_PSEUDO_DESC, 3360 PseudoInstExpansion<(OR_V MSA128BOpnd:$wd, 3361 MSA128BOpnd:$ws, 3362 MSA128BOpnd:$wt)>; 3363 3364def ORI_B : ORI_B_ENC, ORI_B_DESC; 3365 3366def PCKEV_B : PCKEV_B_ENC, PCKEV_B_DESC; 3367def PCKEV_H : PCKEV_H_ENC, PCKEV_H_DESC; 3368def PCKEV_W : PCKEV_W_ENC, PCKEV_W_DESC; 3369def PCKEV_D : PCKEV_D_ENC, PCKEV_D_DESC; 3370 3371def PCKOD_B : PCKOD_B_ENC, PCKOD_B_DESC; 3372def PCKOD_H : PCKOD_H_ENC, PCKOD_H_DESC; 3373def PCKOD_W : PCKOD_W_ENC, PCKOD_W_DESC; 3374def PCKOD_D : PCKOD_D_ENC, PCKOD_D_DESC; 3375 3376def PCNT_B : PCNT_B_ENC, PCNT_B_DESC; 3377def PCNT_H : PCNT_H_ENC, PCNT_H_DESC; 3378def PCNT_W : PCNT_W_ENC, PCNT_W_DESC; 3379def PCNT_D : PCNT_D_ENC, PCNT_D_DESC; 3380 3381def SAT_S_B : SAT_S_B_ENC, SAT_S_B_DESC; 3382def SAT_S_H : SAT_S_H_ENC, SAT_S_H_DESC; 3383def SAT_S_W : SAT_S_W_ENC, SAT_S_W_DESC; 3384def SAT_S_D : SAT_S_D_ENC, SAT_S_D_DESC; 3385 3386def SAT_U_B : SAT_U_B_ENC, SAT_U_B_DESC; 3387def SAT_U_H : SAT_U_H_ENC, SAT_U_H_DESC; 3388def SAT_U_W : SAT_U_W_ENC, SAT_U_W_DESC; 3389def SAT_U_D : SAT_U_D_ENC, SAT_U_D_DESC; 3390 3391def SHF_B : SHF_B_ENC, SHF_B_DESC; 3392def SHF_H : SHF_H_ENC, SHF_H_DESC; 3393def SHF_W : SHF_W_ENC, SHF_W_DESC; 3394 3395def SLD_B : SLD_B_ENC, SLD_B_DESC; 3396def SLD_H : SLD_H_ENC, SLD_H_DESC; 3397def SLD_W : SLD_W_ENC, SLD_W_DESC; 3398def SLD_D : SLD_D_ENC, SLD_D_DESC; 3399 3400def SLDI_B : SLDI_B_ENC, SLDI_B_DESC; 3401def SLDI_H : SLDI_H_ENC, SLDI_H_DESC; 3402def SLDI_W : SLDI_W_ENC, SLDI_W_DESC; 3403def SLDI_D : SLDI_D_ENC, SLDI_D_DESC; 3404 3405def SLL_B : SLL_B_ENC, SLL_B_DESC; 3406def SLL_H : SLL_H_ENC, SLL_H_DESC; 3407def SLL_W : SLL_W_ENC, SLL_W_DESC; 3408def SLL_D : SLL_D_ENC, SLL_D_DESC; 3409 3410def SLLI_B : SLLI_B_ENC, SLLI_B_DESC; 3411def SLLI_H : SLLI_H_ENC, SLLI_H_DESC; 3412def SLLI_W : SLLI_W_ENC, SLLI_W_DESC; 3413def SLLI_D : SLLI_D_ENC, SLLI_D_DESC; 3414 3415def SPLAT_B : SPLAT_B_ENC, SPLAT_B_DESC; 3416def SPLAT_H : SPLAT_H_ENC, SPLAT_H_DESC; 3417def SPLAT_W : SPLAT_W_ENC, SPLAT_W_DESC; 3418def SPLAT_D : SPLAT_D_ENC, SPLAT_D_DESC; 3419 3420def SPLATI_B : SPLATI_B_ENC, SPLATI_B_DESC; 3421def SPLATI_H : SPLATI_H_ENC, SPLATI_H_DESC; 3422def SPLATI_W : SPLATI_W_ENC, SPLATI_W_DESC; 3423def SPLATI_D : SPLATI_D_ENC, SPLATI_D_DESC; 3424 3425def SRA_B : SRA_B_ENC, SRA_B_DESC; 3426def SRA_H : SRA_H_ENC, SRA_H_DESC; 3427def SRA_W : SRA_W_ENC, SRA_W_DESC; 3428def SRA_D : SRA_D_ENC, SRA_D_DESC; 3429 3430def SRAI_B : SRAI_B_ENC, SRAI_B_DESC; 3431def SRAI_H : SRAI_H_ENC, SRAI_H_DESC; 3432def SRAI_W : SRAI_W_ENC, SRAI_W_DESC; 3433def SRAI_D : SRAI_D_ENC, SRAI_D_DESC; 3434 3435def SRAR_B : SRAR_B_ENC, SRAR_B_DESC; 3436def SRAR_H : SRAR_H_ENC, SRAR_H_DESC; 3437def SRAR_W : SRAR_W_ENC, SRAR_W_DESC; 3438def SRAR_D : SRAR_D_ENC, SRAR_D_DESC; 3439 3440def SRARI_B : SRARI_B_ENC, SRARI_B_DESC; 3441def SRARI_H : SRARI_H_ENC, SRARI_H_DESC; 3442def SRARI_W : SRARI_W_ENC, SRARI_W_DESC; 3443def SRARI_D : SRARI_D_ENC, SRARI_D_DESC; 3444 3445def SRL_B : SRL_B_ENC, SRL_B_DESC; 3446def SRL_H : SRL_H_ENC, SRL_H_DESC; 3447def SRL_W : SRL_W_ENC, SRL_W_DESC; 3448def SRL_D : SRL_D_ENC, SRL_D_DESC; 3449 3450def SRLI_B : SRLI_B_ENC, SRLI_B_DESC; 3451def SRLI_H : SRLI_H_ENC, SRLI_H_DESC; 3452def SRLI_W : SRLI_W_ENC, SRLI_W_DESC; 3453def SRLI_D : SRLI_D_ENC, SRLI_D_DESC; 3454 3455def SRLR_B : SRLR_B_ENC, SRLR_B_DESC; 3456def SRLR_H : SRLR_H_ENC, SRLR_H_DESC; 3457def SRLR_W : SRLR_W_ENC, SRLR_W_DESC; 3458def SRLR_D : SRLR_D_ENC, SRLR_D_DESC; 3459 3460def SRLRI_B : SRLRI_B_ENC, SRLRI_B_DESC; 3461def SRLRI_H : SRLRI_H_ENC, SRLRI_H_DESC; 3462def SRLRI_W : SRLRI_W_ENC, SRLRI_W_DESC; 3463def SRLRI_D : SRLRI_D_ENC, SRLRI_D_DESC; 3464 3465def ST_B: ST_B_ENC, ST_B_DESC; 3466def ST_H: ST_H_ENC, ST_H_DESC; 3467def ST_W: ST_W_ENC, ST_W_DESC; 3468def ST_D: ST_D_ENC, ST_D_DESC; 3469 3470def SUBS_S_B : SUBS_S_B_ENC, SUBS_S_B_DESC; 3471def SUBS_S_H : SUBS_S_H_ENC, SUBS_S_H_DESC; 3472def SUBS_S_W : SUBS_S_W_ENC, SUBS_S_W_DESC; 3473def SUBS_S_D : SUBS_S_D_ENC, SUBS_S_D_DESC; 3474 3475def SUBS_U_B : SUBS_U_B_ENC, SUBS_U_B_DESC; 3476def SUBS_U_H : SUBS_U_H_ENC, SUBS_U_H_DESC; 3477def SUBS_U_W : SUBS_U_W_ENC, SUBS_U_W_DESC; 3478def SUBS_U_D : SUBS_U_D_ENC, SUBS_U_D_DESC; 3479 3480def SUBSUS_U_B : SUBSUS_U_B_ENC, SUBSUS_U_B_DESC; 3481def SUBSUS_U_H : SUBSUS_U_H_ENC, SUBSUS_U_H_DESC; 3482def SUBSUS_U_W : SUBSUS_U_W_ENC, SUBSUS_U_W_DESC; 3483def SUBSUS_U_D : SUBSUS_U_D_ENC, SUBSUS_U_D_DESC; 3484 3485def SUBSUU_S_B : SUBSUU_S_B_ENC, SUBSUU_S_B_DESC; 3486def SUBSUU_S_H : SUBSUU_S_H_ENC, SUBSUU_S_H_DESC; 3487def SUBSUU_S_W : SUBSUU_S_W_ENC, SUBSUU_S_W_DESC; 3488def SUBSUU_S_D : SUBSUU_S_D_ENC, SUBSUU_S_D_DESC; 3489 3490def SUBV_B : SUBV_B_ENC, SUBV_B_DESC; 3491def SUBV_H : SUBV_H_ENC, SUBV_H_DESC; 3492def SUBV_W : SUBV_W_ENC, SUBV_W_DESC; 3493def SUBV_D : SUBV_D_ENC, SUBV_D_DESC; 3494 3495def SUBVI_B : SUBVI_B_ENC, SUBVI_B_DESC; 3496def SUBVI_H : SUBVI_H_ENC, SUBVI_H_DESC; 3497def SUBVI_W : SUBVI_W_ENC, SUBVI_W_DESC; 3498def SUBVI_D : SUBVI_D_ENC, SUBVI_D_DESC; 3499 3500def VSHF_B : VSHF_B_ENC, VSHF_B_DESC; 3501def VSHF_H : VSHF_H_ENC, VSHF_H_DESC; 3502def VSHF_W : VSHF_W_ENC, VSHF_W_DESC; 3503def VSHF_D : VSHF_D_ENC, VSHF_D_DESC; 3504 3505def XOR_V : XOR_V_ENC, XOR_V_DESC; 3506def XOR_V_H_PSEUDO : XOR_V_H_PSEUDO_DESC, 3507 PseudoInstExpansion<(XOR_V MSA128BOpnd:$wd, 3508 MSA128BOpnd:$ws, 3509 MSA128BOpnd:$wt)>; 3510def XOR_V_W_PSEUDO : XOR_V_W_PSEUDO_DESC, 3511 PseudoInstExpansion<(XOR_V MSA128BOpnd:$wd, 3512 MSA128BOpnd:$ws, 3513 MSA128BOpnd:$wt)>; 3514def XOR_V_D_PSEUDO : XOR_V_D_PSEUDO_DESC, 3515 PseudoInstExpansion<(XOR_V MSA128BOpnd:$wd, 3516 MSA128BOpnd:$ws, 3517 MSA128BOpnd:$wt)>; 3518 3519def XORI_B : XORI_B_ENC, XORI_B_DESC; 3520 3521// Patterns. 3522class MSAPat<dag pattern, dag result, list<Predicate> pred = [HasMSA]> : 3523 Pat<pattern, result>, Requires<pred>; 3524 3525def : MSAPat<(extractelt (v4i32 MSA128W:$ws), immZExt4:$idx), 3526 (COPY_S_W MSA128W:$ws, immZExt4:$idx)>; 3527 3528def : MSAPat<(v8f16 (load addrimm10lsl1:$addr)), (LD_H addrimm10lsl1:$addr)>; 3529def : MSAPat<(v4f32 (load addrimm10lsl2:$addr)), (LD_W addrimm10lsl2:$addr)>; 3530def : MSAPat<(v2f64 (load addrimm10lsl3:$addr)), (LD_D addrimm10lsl3:$addr)>; 3531 3532def ST_FH : MSAPat<(store (v8f16 MSA128H:$ws), addrimm10lsl1:$addr), 3533 (ST_H MSA128H:$ws, addrimm10lsl1:$addr)>; 3534def ST_FW : MSAPat<(store (v4f32 MSA128W:$ws), addrimm10lsl2:$addr), 3535 (ST_W MSA128W:$ws, addrimm10lsl2:$addr)>; 3536def ST_FD : MSAPat<(store (v2f64 MSA128D:$ws), addrimm10lsl3:$addr), 3537 (ST_D MSA128D:$ws, addrimm10lsl3:$addr)>; 3538 3539class MSA_FABS_PSEUDO_DESC_BASE<RegisterOperand ROWD, 3540 RegisterOperand ROWS = ROWD, 3541 InstrItinClass itin = NoItinerary> : 3542 MSAPseudo<(outs ROWD:$wd), 3543 (ins ROWS:$ws), 3544 [(set ROWD:$wd, (fabs ROWS:$ws))]> { 3545 InstrItinClass Itinerary = itin; 3546} 3547def FABS_W : MSA_FABS_PSEUDO_DESC_BASE<MSA128WOpnd>, 3548 PseudoInstExpansion<(FMAX_A_W MSA128WOpnd:$wd, MSA128WOpnd:$ws, 3549 MSA128WOpnd:$ws)>; 3550def FABS_D : MSA_FABS_PSEUDO_DESC_BASE<MSA128DOpnd>, 3551 PseudoInstExpansion<(FMAX_A_D MSA128DOpnd:$wd, MSA128DOpnd:$ws, 3552 MSA128DOpnd:$ws)>; 3553 3554class MSABitconvertPat<ValueType DstVT, ValueType SrcVT, 3555 RegisterClass DstRC, list<Predicate> preds = [HasMSA]> : 3556 MSAPat<(DstVT (bitconvert SrcVT:$src)), 3557 (COPY_TO_REGCLASS SrcVT:$src, DstRC), preds>; 3558 3559// These are endian-independent because the element size doesnt change 3560def : MSABitconvertPat<v8i16, v8f16, MSA128H>; 3561def : MSABitconvertPat<v4i32, v4f32, MSA128W>; 3562def : MSABitconvertPat<v2i64, v2f64, MSA128D>; 3563def : MSABitconvertPat<v8f16, v8i16, MSA128H>; 3564def : MSABitconvertPat<v4f32, v4i32, MSA128W>; 3565def : MSABitconvertPat<v2f64, v2i64, MSA128D>; 3566 3567// Little endian bitcasts are always no-ops 3568def : MSABitconvertPat<v16i8, v8i16, MSA128B, [HasMSA, IsLE]>; 3569def : MSABitconvertPat<v16i8, v4i32, MSA128B, [HasMSA, IsLE]>; 3570def : MSABitconvertPat<v16i8, v2i64, MSA128B, [HasMSA, IsLE]>; 3571def : MSABitconvertPat<v16i8, v8f16, MSA128B, [HasMSA, IsLE]>; 3572def : MSABitconvertPat<v16i8, v4f32, MSA128B, [HasMSA, IsLE]>; 3573def : MSABitconvertPat<v16i8, v2f64, MSA128B, [HasMSA, IsLE]>; 3574 3575def : MSABitconvertPat<v8i16, v16i8, MSA128H, [HasMSA, IsLE]>; 3576def : MSABitconvertPat<v8i16, v4i32, MSA128H, [HasMSA, IsLE]>; 3577def : MSABitconvertPat<v8i16, v2i64, MSA128H, [HasMSA, IsLE]>; 3578def : MSABitconvertPat<v8i16, v4f32, MSA128H, [HasMSA, IsLE]>; 3579def : MSABitconvertPat<v8i16, v2f64, MSA128H, [HasMSA, IsLE]>; 3580 3581def : MSABitconvertPat<v4i32, v16i8, MSA128W, [HasMSA, IsLE]>; 3582def : MSABitconvertPat<v4i32, v8i16, MSA128W, [HasMSA, IsLE]>; 3583def : MSABitconvertPat<v4i32, v2i64, MSA128W, [HasMSA, IsLE]>; 3584def : MSABitconvertPat<v4i32, v8f16, MSA128W, [HasMSA, IsLE]>; 3585def : MSABitconvertPat<v4i32, v2f64, MSA128W, [HasMSA, IsLE]>; 3586 3587def : MSABitconvertPat<v2i64, v16i8, MSA128D, [HasMSA, IsLE]>; 3588def : MSABitconvertPat<v2i64, v8i16, MSA128D, [HasMSA, IsLE]>; 3589def : MSABitconvertPat<v2i64, v4i32, MSA128D, [HasMSA, IsLE]>; 3590def : MSABitconvertPat<v2i64, v8f16, MSA128D, [HasMSA, IsLE]>; 3591def : MSABitconvertPat<v2i64, v4f32, MSA128D, [HasMSA, IsLE]>; 3592 3593def : MSABitconvertPat<v4f32, v16i8, MSA128W, [HasMSA, IsLE]>; 3594def : MSABitconvertPat<v4f32, v8i16, MSA128W, [HasMSA, IsLE]>; 3595def : MSABitconvertPat<v4f32, v2i64, MSA128W, [HasMSA, IsLE]>; 3596def : MSABitconvertPat<v4f32, v8f16, MSA128W, [HasMSA, IsLE]>; 3597def : MSABitconvertPat<v4f32, v2f64, MSA128W, [HasMSA, IsLE]>; 3598 3599def : MSABitconvertPat<v2f64, v16i8, MSA128D, [HasMSA, IsLE]>; 3600def : MSABitconvertPat<v2f64, v8i16, MSA128D, [HasMSA, IsLE]>; 3601def : MSABitconvertPat<v2f64, v4i32, MSA128D, [HasMSA, IsLE]>; 3602def : MSABitconvertPat<v2f64, v8f16, MSA128D, [HasMSA, IsLE]>; 3603def : MSABitconvertPat<v2f64, v4f32, MSA128D, [HasMSA, IsLE]>; 3604 3605// Big endian bitcasts expand to shuffle instructions. 3606// This is because bitcast is defined to be a store/load sequence and the 3607// vector store/load instructions are mixed-endian with respect to the vector 3608// as a whole (little endian with respect to element order, but big endian 3609// elements). 3610 3611class MSABitconvertReverseQuartersPat<ValueType DstVT, ValueType SrcVT, 3612 RegisterClass DstRC, MSAInst Insn, 3613 RegisterClass ViaRC> : 3614 MSAPat<(DstVT (bitconvert SrcVT:$src)), 3615 (COPY_TO_REGCLASS (Insn (COPY_TO_REGCLASS SrcVT:$src, ViaRC), 27), 3616 DstRC), 3617 [HasMSA, IsBE]>; 3618 3619class MSABitconvertReverseHalvesPat<ValueType DstVT, ValueType SrcVT, 3620 RegisterClass DstRC, MSAInst Insn, 3621 RegisterClass ViaRC> : 3622 MSAPat<(DstVT (bitconvert SrcVT:$src)), 3623 (COPY_TO_REGCLASS (Insn (COPY_TO_REGCLASS SrcVT:$src, ViaRC), 177), 3624 DstRC), 3625 [HasMSA, IsBE]>; 3626 3627class MSABitconvertReverseBInHPat<ValueType DstVT, ValueType SrcVT, 3628 RegisterClass DstRC> : 3629 MSABitconvertReverseHalvesPat<DstVT, SrcVT, DstRC, SHF_B, MSA128B>; 3630 3631class MSABitconvertReverseBInWPat<ValueType DstVT, ValueType SrcVT, 3632 RegisterClass DstRC> : 3633 MSABitconvertReverseQuartersPat<DstVT, SrcVT, DstRC, SHF_B, MSA128B>; 3634 3635class MSABitconvertReverseBInDPat<ValueType DstVT, ValueType SrcVT, 3636 RegisterClass DstRC> : 3637 MSAPat<(DstVT (bitconvert SrcVT:$src)), 3638 (COPY_TO_REGCLASS 3639 (SHF_W 3640 (COPY_TO_REGCLASS 3641 (SHF_B (COPY_TO_REGCLASS SrcVT:$src, MSA128B), 27), 3642 MSA128W), 177), 3643 DstRC), 3644 [HasMSA, IsBE]>; 3645 3646class MSABitconvertReverseHInWPat<ValueType DstVT, ValueType SrcVT, 3647 RegisterClass DstRC> : 3648 MSABitconvertReverseHalvesPat<DstVT, SrcVT, DstRC, SHF_H, MSA128H>; 3649 3650class MSABitconvertReverseHInDPat<ValueType DstVT, ValueType SrcVT, 3651 RegisterClass DstRC> : 3652 MSABitconvertReverseQuartersPat<DstVT, SrcVT, DstRC, SHF_H, MSA128H>; 3653 3654class MSABitconvertReverseWInDPat<ValueType DstVT, ValueType SrcVT, 3655 RegisterClass DstRC> : 3656 MSABitconvertReverseHalvesPat<DstVT, SrcVT, DstRC, SHF_W, MSA128W>; 3657 3658def : MSABitconvertReverseBInHPat<v8i16, v16i8, MSA128H>; 3659def : MSABitconvertReverseBInHPat<v8f16, v16i8, MSA128H>; 3660def : MSABitconvertReverseBInWPat<v4i32, v16i8, MSA128W>; 3661def : MSABitconvertReverseBInWPat<v4f32, v16i8, MSA128W>; 3662def : MSABitconvertReverseBInDPat<v2i64, v16i8, MSA128D>; 3663def : MSABitconvertReverseBInDPat<v2f64, v16i8, MSA128D>; 3664 3665def : MSABitconvertReverseBInHPat<v16i8, v8i16, MSA128B>; 3666def : MSABitconvertReverseHInWPat<v4i32, v8i16, MSA128W>; 3667def : MSABitconvertReverseHInWPat<v4f32, v8i16, MSA128W>; 3668def : MSABitconvertReverseHInDPat<v2i64, v8i16, MSA128D>; 3669def : MSABitconvertReverseHInDPat<v2f64, v8i16, MSA128D>; 3670 3671def : MSABitconvertReverseBInHPat<v16i8, v8f16, MSA128B>; 3672def : MSABitconvertReverseHInWPat<v4i32, v8f16, MSA128W>; 3673def : MSABitconvertReverseHInWPat<v4f32, v8f16, MSA128W>; 3674def : MSABitconvertReverseHInDPat<v2i64, v8f16, MSA128D>; 3675def : MSABitconvertReverseHInDPat<v2f64, v8f16, MSA128D>; 3676 3677def : MSABitconvertReverseBInWPat<v16i8, v4i32, MSA128B>; 3678def : MSABitconvertReverseHInWPat<v8i16, v4i32, MSA128H>; 3679def : MSABitconvertReverseHInWPat<v8f16, v4i32, MSA128H>; 3680def : MSABitconvertReverseWInDPat<v2i64, v4i32, MSA128D>; 3681def : MSABitconvertReverseWInDPat<v2f64, v4i32, MSA128D>; 3682 3683def : MSABitconvertReverseBInWPat<v16i8, v4f32, MSA128B>; 3684def : MSABitconvertReverseHInWPat<v8i16, v4f32, MSA128H>; 3685def : MSABitconvertReverseHInWPat<v8f16, v4f32, MSA128H>; 3686def : MSABitconvertReverseWInDPat<v2i64, v4f32, MSA128D>; 3687def : MSABitconvertReverseWInDPat<v2f64, v4f32, MSA128D>; 3688 3689def : MSABitconvertReverseBInDPat<v16i8, v2i64, MSA128B>; 3690def : MSABitconvertReverseHInDPat<v8i16, v2i64, MSA128H>; 3691def : MSABitconvertReverseHInDPat<v8f16, v2i64, MSA128H>; 3692def : MSABitconvertReverseWInDPat<v4i32, v2i64, MSA128W>; 3693def : MSABitconvertReverseWInDPat<v4f32, v2i64, MSA128W>; 3694 3695def : MSABitconvertReverseBInDPat<v16i8, v2f64, MSA128B>; 3696def : MSABitconvertReverseHInDPat<v8i16, v2f64, MSA128H>; 3697def : MSABitconvertReverseHInDPat<v8f16, v2f64, MSA128H>; 3698def : MSABitconvertReverseWInDPat<v4i32, v2f64, MSA128W>; 3699def : MSABitconvertReverseWInDPat<v4f32, v2f64, MSA128W>; 3700 3701// Pseudos used to implement BNZ.df, and BZ.df 3702 3703class MSA_CBRANCH_PSEUDO_DESC_BASE<SDPatternOperator OpNode, ValueType TyNode, 3704 RegisterClass RCWS, 3705 InstrItinClass itin = NoItinerary> : 3706 MipsPseudo<(outs GPR32:$dst), 3707 (ins RCWS:$ws), 3708 [(set GPR32:$dst, (OpNode (TyNode RCWS:$ws)))]> { 3709 bit usesCustomInserter = 1; 3710} 3711 3712def SNZ_B_PSEUDO : MSA_CBRANCH_PSEUDO_DESC_BASE<MipsVAllNonZero, v16i8, 3713 MSA128B, NoItinerary>; 3714def SNZ_H_PSEUDO : MSA_CBRANCH_PSEUDO_DESC_BASE<MipsVAllNonZero, v8i16, 3715 MSA128H, NoItinerary>; 3716def SNZ_W_PSEUDO : MSA_CBRANCH_PSEUDO_DESC_BASE<MipsVAllNonZero, v4i32, 3717 MSA128W, NoItinerary>; 3718def SNZ_D_PSEUDO : MSA_CBRANCH_PSEUDO_DESC_BASE<MipsVAllNonZero, v2i64, 3719 MSA128D, NoItinerary>; 3720def SNZ_V_PSEUDO : MSA_CBRANCH_PSEUDO_DESC_BASE<MipsVAnyNonZero, v16i8, 3721 MSA128B, NoItinerary>; 3722 3723def SZ_B_PSEUDO : MSA_CBRANCH_PSEUDO_DESC_BASE<MipsVAllZero, v16i8, 3724 MSA128B, NoItinerary>; 3725def SZ_H_PSEUDO : MSA_CBRANCH_PSEUDO_DESC_BASE<MipsVAllZero, v8i16, 3726 MSA128H, NoItinerary>; 3727def SZ_W_PSEUDO : MSA_CBRANCH_PSEUDO_DESC_BASE<MipsVAllZero, v4i32, 3728 MSA128W, NoItinerary>; 3729def SZ_D_PSEUDO : MSA_CBRANCH_PSEUDO_DESC_BASE<MipsVAllZero, v2i64, 3730 MSA128D, NoItinerary>; 3731def SZ_V_PSEUDO : MSA_CBRANCH_PSEUDO_DESC_BASE<MipsVAnyZero, v16i8, 3732 MSA128B, NoItinerary>; 3733 3734// Pseudoes used to implement transparent fp16 support. 3735 3736let Predicates = [HasMSA] in { 3737 def ST_F16 : MipsPseudo<(outs), (ins MSA128F16:$ws, mem_simm10:$addr), 3738 [(store (f16 MSA128F16:$ws), (addrimm10:$addr))]> { 3739 let usesCustomInserter = 1; 3740 } 3741 3742 def LD_F16 : MipsPseudo<(outs MSA128F16:$ws), (ins mem_simm10:$addr), 3743 [(set MSA128F16:$ws, (f16 (load addrimm10:$addr)))]> { 3744 let usesCustomInserter = 1; 3745 } 3746 3747 def MSA_FP_EXTEND_W_PSEUDO : MipsPseudo<(outs FGR32Opnd:$fd), 3748 (ins MSA128F16:$ws), 3749 [(set FGR32Opnd:$fd, 3750 (f32 (fpextend MSA128F16:$ws)))]> { 3751 let usesCustomInserter = 1; 3752 } 3753 3754 def MSA_FP_ROUND_W_PSEUDO : MipsPseudo<(outs MSA128F16:$wd), 3755 (ins FGR32Opnd:$fs), 3756 [(set MSA128F16:$wd, 3757 (f16 (fpround FGR32Opnd:$fs)))]> { 3758 let usesCustomInserter = 1; 3759 } 3760 3761 def MSA_FP_EXTEND_D_PSEUDO : MipsPseudo<(outs FGR64Opnd:$fd), 3762 (ins MSA128F16:$ws), 3763 [(set FGR64Opnd:$fd, 3764 (f64 (fpextend MSA128F16:$ws)))]> { 3765 let usesCustomInserter = 1; 3766 } 3767 3768 def MSA_FP_ROUND_D_PSEUDO : MipsPseudo<(outs MSA128F16:$wd), 3769 (ins FGR64Opnd:$fs), 3770 [(set MSA128F16:$wd, 3771 (f16 (fpround FGR64Opnd:$fs)))]> { 3772 let usesCustomInserter = 1; 3773 } 3774 3775 def : MipsPat<(MipsTruncIntFP MSA128F16:$ws), 3776 (TRUNC_W_D64 (MSA_FP_EXTEND_D_PSEUDO MSA128F16:$ws))>; 3777 3778 def : MipsPat<(MipsFPCmp MSA128F16:$ws, MSA128F16:$wt, imm:$cond), 3779 (FCMP_S32 (MSA_FP_EXTEND_W_PSEUDO MSA128F16:$ws), 3780 (MSA_FP_EXTEND_W_PSEUDO MSA128F16:$wt), imm:$cond)>, 3781 ISA_MIPS1_NOT_32R6_64R6; 3782} 3783 3784// Vector extraction with fixed index. 3785// 3786// Extracting 32-bit values on MSA32 should always use COPY_S_W rather than 3787// COPY_U_W, even for the zero-extended case. This is because our forward 3788// compatibility strategy is to consider registers to be infinitely 3789// sign-extended so that a MIPS64 can execute MIPS32 code without getting 3790// different register values. 3791def : MSAPat<(vextract_zext_i32 (v4i32 MSA128W:$ws), immZExt2Ptr:$idx), 3792 (COPY_S_W MSA128W:$ws, immZExt2:$idx)>, ASE_MSA_NOT_MSA64; 3793def : MSAPat<(vextract_zext_i32 (v4f32 MSA128W:$ws), immZExt2Ptr:$idx), 3794 (COPY_S_W MSA128W:$ws, immZExt2:$idx)>, ASE_MSA_NOT_MSA64; 3795 3796// Extracting 64-bit values on MSA64 should always use COPY_S_D rather than 3797// COPY_U_D, even for the zero-extended case. This is because our forward 3798// compatibility strategy is to consider registers to be infinitely 3799// sign-extended so that a hypothetical MIPS128 would be able to execute MIPS64 3800// code without getting different register values. 3801def : MSAPat<(vextract_zext_i64 (v2i64 MSA128D:$ws), immZExt1Ptr:$idx), 3802 (COPY_S_D MSA128D:$ws, immZExt1:$idx)>, ASE_MSA64; 3803def : MSAPat<(vextract_zext_i64 (v2f64 MSA128D:$ws), immZExt1Ptr:$idx), 3804 (COPY_S_D MSA128D:$ws, immZExt1:$idx)>, ASE_MSA64; 3805 3806// Vector extraction with variable index 3807def : MSAPat<(i32 (vextract_sext_i8 v16i8:$ws, i32:$idx)), 3808 (SRA (COPY_TO_REGCLASS (i32 (EXTRACT_SUBREG (SPLAT_B v16i8:$ws, 3809 i32:$idx), 3810 sub_lo)), 3811 GPR32), (i32 24))>; 3812def : MSAPat<(i32 (vextract_sext_i16 v8i16:$ws, i32:$idx)), 3813 (SRA (COPY_TO_REGCLASS (i32 (EXTRACT_SUBREG (SPLAT_H v8i16:$ws, 3814 i32:$idx), 3815 sub_lo)), 3816 GPR32), (i32 16))>; 3817def : MSAPat<(i32 (vextract_sext_i32 v4i32:$ws, i32:$idx)), 3818 (COPY_TO_REGCLASS (i32 (EXTRACT_SUBREG (SPLAT_W v4i32:$ws, 3819 i32:$idx), 3820 sub_lo)), 3821 GPR32)>; 3822def : MSAPat<(i64 (vextract_sext_i64 v2i64:$ws, i32:$idx)), 3823 (COPY_TO_REGCLASS (i64 (EXTRACT_SUBREG (SPLAT_D v2i64:$ws, 3824 i32:$idx), 3825 sub_64)), 3826 GPR64), [HasMSA, IsGP64bit]>; 3827 3828def : MSAPat<(i32 (vextract_zext_i8 v16i8:$ws, i32:$idx)), 3829 (SRL (COPY_TO_REGCLASS (i32 (EXTRACT_SUBREG (SPLAT_B v16i8:$ws, 3830 i32:$idx), 3831 sub_lo)), 3832 GPR32), (i32 24))>; 3833def : MSAPat<(i32 (vextract_zext_i16 v8i16:$ws, i32:$idx)), 3834 (SRL (COPY_TO_REGCLASS (i32 (EXTRACT_SUBREG (SPLAT_H v8i16:$ws, 3835 i32:$idx), 3836 sub_lo)), 3837 GPR32), (i32 16))>; 3838def : MSAPat<(i32 (vextract_zext_i32 v4i32:$ws, i32:$idx)), 3839 (COPY_TO_REGCLASS (i32 (EXTRACT_SUBREG (SPLAT_W v4i32:$ws, 3840 i32:$idx), 3841 sub_lo)), 3842 GPR32)>; 3843def : MSAPat<(i64 (vextract_zext_i64 v2i64:$ws, i32:$idx)), 3844 (COPY_TO_REGCLASS (i64 (EXTRACT_SUBREG (SPLAT_D v2i64:$ws, 3845 i32:$idx), 3846 sub_64)), 3847 GPR64), [HasMSA, IsGP64bit]>; 3848 3849def : MSAPat<(f32 (vector_extract v4f32:$ws, i32:$idx)), 3850 (f32 (EXTRACT_SUBREG (SPLAT_W v4f32:$ws, 3851 i32:$idx), 3852 sub_lo))>; 3853def : MSAPat<(f64 (vector_extract v2f64:$ws, i32:$idx)), 3854 (f64 (EXTRACT_SUBREG (SPLAT_D v2f64:$ws, 3855 i32:$idx), 3856 sub_64))>; 3857 3858// Vector extraction with variable index (N64 ABI) 3859def : MSAPat< 3860 (i32 (vextract_sext_i8 v16i8:$ws, i64:$idx)), 3861 (SRA (COPY_TO_REGCLASS 3862 (i32 (EXTRACT_SUBREG 3863 (SPLAT_B v16i8:$ws, 3864 (COPY_TO_REGCLASS 3865 (i32 (EXTRACT_SUBREG i64:$idx, sub_32)), GPR32)), 3866 sub_lo)), 3867 GPR32), 3868 (i32 24))>; 3869def : MSAPat< 3870 (i32 (vextract_sext_i16 v8i16:$ws, i64:$idx)), 3871 (SRA (COPY_TO_REGCLASS 3872 (i32 (EXTRACT_SUBREG 3873 (SPLAT_H v8i16:$ws, 3874 (COPY_TO_REGCLASS 3875 (i32 (EXTRACT_SUBREG i64:$idx, sub_32)), GPR32)), 3876 sub_lo)), 3877 GPR32), 3878 (i32 16))>; 3879def : MSAPat< 3880 (i32 (vextract_sext_i32 v4i32:$ws, i64:$idx)), 3881 (COPY_TO_REGCLASS 3882 (i32 (EXTRACT_SUBREG 3883 (SPLAT_W v4i32:$ws, 3884 (COPY_TO_REGCLASS 3885 (i32 (EXTRACT_SUBREG i64:$idx, sub_32)), GPR32)), 3886 sub_lo)), 3887 GPR32)>; 3888def : MSAPat< 3889 (i64 (vextract_sext_i64 v2i64:$ws, i64:$idx)), 3890 (COPY_TO_REGCLASS 3891 (i64 (EXTRACT_SUBREG 3892 (SPLAT_D v2i64:$ws, 3893 (COPY_TO_REGCLASS (i32 (EXTRACT_SUBREG i64:$idx, sub_32)), GPR32)), 3894 sub_64)), 3895 GPR64), [HasMSA, IsGP64bit]>; 3896 3897def : MSAPat< 3898 (i32 (vextract_zext_i8 v16i8:$ws, i64:$idx)), 3899 (SRL (COPY_TO_REGCLASS 3900 (i32 (EXTRACT_SUBREG 3901 (SPLAT_B v16i8:$ws, 3902 (COPY_TO_REGCLASS 3903 (i32 (EXTRACT_SUBREG i64:$idx, sub_32)), GPR32)), 3904 sub_lo)), 3905 GPR32), 3906 (i32 24))>; 3907def : MSAPat< 3908 (i32 (vextract_zext_i16 v8i16:$ws, i64:$idx)), 3909 (SRL (COPY_TO_REGCLASS 3910 (i32 (EXTRACT_SUBREG 3911 (SPLAT_H v8i16:$ws, 3912 (COPY_TO_REGCLASS 3913 (i32 (EXTRACT_SUBREG i64:$idx, sub_32)), GPR32)), 3914 sub_lo)), 3915 GPR32), 3916 (i32 16))>; 3917def : MSAPat< 3918 (i32 (vextract_zext_i32 v4i32:$ws, i64:$idx)), 3919 (COPY_TO_REGCLASS 3920 (i32 (EXTRACT_SUBREG 3921 (SPLAT_W v4i32:$ws, 3922 (COPY_TO_REGCLASS (i32 (EXTRACT_SUBREG i64:$idx, sub_32)), GPR32)), 3923 sub_lo)), 3924 GPR32)>; 3925def : MSAPat< 3926 (i64 (vextract_zext_i64 v2i64:$ws, i64:$idx)), 3927 (COPY_TO_REGCLASS 3928 (i64 (EXTRACT_SUBREG 3929 (SPLAT_D v2i64:$ws, 3930 (COPY_TO_REGCLASS (i32 (EXTRACT_SUBREG i64:$idx, sub_32)), GPR32)), 3931 sub_64)), 3932 GPR64), 3933 [HasMSA, IsGP64bit]>; 3934 3935def : MSAPat< 3936 (f32 (vector_extract v4f32:$ws, i64:$idx)), 3937 (f32 (EXTRACT_SUBREG 3938 (SPLAT_W v4f32:$ws, 3939 (COPY_TO_REGCLASS (i32 (EXTRACT_SUBREG i64:$idx, sub_32)), GPR32)), 3940 sub_lo))>; 3941def : MSAPat< 3942 (f64 (vector_extract v2f64:$ws, i64:$idx)), 3943 (f64 (EXTRACT_SUBREG 3944 (SPLAT_D v2f64:$ws, 3945 (COPY_TO_REGCLASS (i32 (EXTRACT_SUBREG i64:$idx, sub_32)), GPR32)), 3946 sub_64))>; 3947