1 //===- MipsLegalizerInfo.cpp ------------------------------------*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 /// \file
9 /// This file implements the targeting of the Machinelegalizer class for Mips.
10 /// \todo This should be generated by TableGen.
11 //===----------------------------------------------------------------------===//
12 
13 #include "MipsLegalizerInfo.h"
14 #include "MipsTargetMachine.h"
15 #include "llvm/CodeGen/GlobalISel/LegalizerHelper.h"
16 #include "llvm/IR/IntrinsicsMips.h"
17 
18 using namespace llvm;
19 
20 struct TypesAndMemOps {
21   LLT ValTy;
22   LLT PtrTy;
23   unsigned MemSize;
24   bool MustBeNaturallyAligned;
25 };
26 
27 static bool
28 CheckTy0Ty1MemSizeAlign(const LegalityQuery &Query,
29                         std::initializer_list<TypesAndMemOps> SupportedValues) {
30   for (auto &Val : SupportedValues) {
31     if (Val.ValTy != Query.Types[0])
32       continue;
33     if (Val.PtrTy != Query.Types[1])
34       continue;
35     if (Val.MemSize != Query.MMODescrs[0].SizeInBits)
36       continue;
37     if (Val.MustBeNaturallyAligned &&
38         Query.MMODescrs[0].SizeInBits % Query.MMODescrs[0].AlignInBits != 0)
39       continue;
40     return true;
41   }
42   return false;
43 }
44 
45 static bool CheckTyN(unsigned N, const LegalityQuery &Query,
46                      std::initializer_list<LLT> SupportedValues) {
47   for (auto &Val : SupportedValues)
48     if (Val == Query.Types[N])
49       return true;
50   return false;
51 }
52 
53 MipsLegalizerInfo::MipsLegalizerInfo(const MipsSubtarget &ST) {
54   using namespace TargetOpcode;
55 
56   const LLT s1 = LLT::scalar(1);
57   const LLT s32 = LLT::scalar(32);
58   const LLT s64 = LLT::scalar(64);
59   const LLT v16s8 = LLT::vector(16, 8);
60   const LLT v8s16 = LLT::vector(8, 16);
61   const LLT v4s32 = LLT::vector(4, 32);
62   const LLT v2s64 = LLT::vector(2, 64);
63   const LLT p0 = LLT::pointer(0, 32);
64 
65   getActionDefinitionsBuilder({G_ADD, G_SUB, G_MUL})
66       .legalIf([=, &ST](const LegalityQuery &Query) {
67         if (CheckTyN(0, Query, {s32}))
68           return true;
69         if (ST.hasMSA() && CheckTyN(0, Query, {v16s8, v8s16, v4s32, v2s64}))
70           return true;
71         return false;
72       })
73       .clampScalar(0, s32, s32);
74 
75   getActionDefinitionsBuilder({G_UADDO, G_UADDE, G_USUBO, G_USUBE, G_UMULO})
76       .lowerFor({{s32, s1}});
77 
78   getActionDefinitionsBuilder(G_UMULH)
79       .legalFor({s32})
80       .maxScalar(0, s32);
81 
82   getActionDefinitionsBuilder({G_LOAD, G_STORE})
83       .legalIf([=, &ST](const LegalityQuery &Query) {
84         if (CheckTy0Ty1MemSizeAlign(Query, {{s32, p0, 8, ST.hasMips32r6()},
85                                             {s32, p0, 16, ST.hasMips32r6()},
86                                             {s32, p0, 32, ST.hasMips32r6()},
87                                             {p0, p0, 32, ST.hasMips32r6()},
88                                             {s64, p0, 64, ST.hasMips32r6()}}))
89           return true;
90         if (ST.hasMSA() &&
91             CheckTy0Ty1MemSizeAlign(Query, {{v16s8, p0, 128, false},
92                                             {v8s16, p0, 128, false},
93                                             {v4s32, p0, 128, false},
94                                             {v2s64, p0, 128, false}}))
95           return true;
96         return false;
97       })
98       .minScalar(0, s32);
99 
100   getActionDefinitionsBuilder(G_IMPLICIT_DEF)
101       .legalFor({s32, s64});
102 
103   getActionDefinitionsBuilder(G_UNMERGE_VALUES)
104      .legalFor({{s32, s64}});
105 
106   getActionDefinitionsBuilder(G_MERGE_VALUES)
107      .legalFor({{s64, s32}});
108 
109   getActionDefinitionsBuilder({G_ZEXTLOAD, G_SEXTLOAD})
110       .legalForTypesWithMemDesc({{s32, p0, 8, 8},
111                                  {s32, p0, 16, 8}})
112       .clampScalar(0, s32, s32);
113 
114   getActionDefinitionsBuilder({G_ZEXT, G_SEXT})
115       .legalIf([](const LegalityQuery &Query) { return false; })
116       .maxScalar(0, s32);
117 
118   getActionDefinitionsBuilder(G_TRUNC)
119       .legalIf([](const LegalityQuery &Query) { return false; })
120       .maxScalar(1, s32);
121 
122   getActionDefinitionsBuilder(G_SELECT)
123       .legalForCartesianProduct({p0, s32, s64}, {s32})
124       .minScalar(0, s32)
125       .minScalar(1, s32);
126 
127   getActionDefinitionsBuilder(G_BRCOND)
128       .legalFor({s32})
129       .minScalar(0, s32);
130 
131   getActionDefinitionsBuilder(G_BRJT)
132       .legalFor({{p0, s32}});
133 
134   getActionDefinitionsBuilder(G_BRINDIRECT)
135       .legalFor({p0});
136 
137   getActionDefinitionsBuilder(G_PHI)
138       .legalFor({p0, s32, s64})
139       .minScalar(0, s32);
140 
141   getActionDefinitionsBuilder({G_AND, G_OR, G_XOR})
142       .legalFor({s32})
143       .clampScalar(0, s32, s32);
144 
145   getActionDefinitionsBuilder({G_SDIV, G_SREM, G_UDIV, G_UREM})
146       .legalIf([=, &ST](const LegalityQuery &Query) {
147         if (CheckTyN(0, Query, {s32}))
148           return true;
149         if (ST.hasMSA() && CheckTyN(0, Query, {v16s8, v8s16, v4s32, v2s64}))
150           return true;
151         return false;
152       })
153       .minScalar(0, s32)
154       .libcallFor({s64});
155 
156   getActionDefinitionsBuilder({G_SHL, G_ASHR, G_LSHR})
157       .legalFor({{s32, s32}})
158       .clampScalar(1, s32, s32)
159       .clampScalar(0, s32, s32);
160 
161   getActionDefinitionsBuilder(G_ICMP)
162       .legalForCartesianProduct({s32}, {s32, p0})
163       .clampScalar(1, s32, s32)
164       .minScalar(0, s32);
165 
166   getActionDefinitionsBuilder(G_CONSTANT)
167       .legalFor({s32})
168       .clampScalar(0, s32, s32);
169 
170   getActionDefinitionsBuilder({G_PTR_ADD, G_INTTOPTR})
171       .legalFor({{p0, s32}});
172 
173   getActionDefinitionsBuilder(G_PTRTOINT)
174       .legalFor({{s32, p0}});
175 
176   getActionDefinitionsBuilder(G_FRAME_INDEX)
177       .legalFor({p0});
178 
179   getActionDefinitionsBuilder({G_GLOBAL_VALUE, G_JUMP_TABLE})
180       .legalFor({p0});
181 
182   getActionDefinitionsBuilder(G_DYN_STACKALLOC)
183       .lowerFor({{p0, s32}});
184 
185   getActionDefinitionsBuilder(G_VASTART)
186      .legalFor({p0});
187 
188   // FP instructions
189   getActionDefinitionsBuilder(G_FCONSTANT)
190       .legalFor({s32, s64});
191 
192   getActionDefinitionsBuilder({G_FADD, G_FSUB, G_FMUL, G_FDIV, G_FABS, G_FSQRT})
193       .legalIf([=, &ST](const LegalityQuery &Query) {
194         if (CheckTyN(0, Query, {s32, s64}))
195           return true;
196         if (ST.hasMSA() && CheckTyN(0, Query, {v16s8, v8s16, v4s32, v2s64}))
197           return true;
198         return false;
199       });
200 
201   getActionDefinitionsBuilder(G_FCMP)
202       .legalFor({{s32, s32}, {s32, s64}})
203       .minScalar(0, s32);
204 
205   getActionDefinitionsBuilder({G_FCEIL, G_FFLOOR})
206       .libcallFor({s32, s64});
207 
208   getActionDefinitionsBuilder(G_FPEXT)
209       .legalFor({{s64, s32}});
210 
211   getActionDefinitionsBuilder(G_FPTRUNC)
212       .legalFor({{s32, s64}});
213 
214   // FP to int conversion instructions
215   getActionDefinitionsBuilder(G_FPTOSI)
216       .legalForCartesianProduct({s32}, {s64, s32})
217       .libcallForCartesianProduct({s64}, {s64, s32})
218       .minScalar(0, s32);
219 
220   getActionDefinitionsBuilder(G_FPTOUI)
221       .libcallForCartesianProduct({s64}, {s64, s32})
222       .lowerForCartesianProduct({s32}, {s64, s32})
223       .minScalar(0, s32);
224 
225   // Int to FP conversion instructions
226   getActionDefinitionsBuilder(G_SITOFP)
227       .legalForCartesianProduct({s64, s32}, {s32})
228       .libcallForCartesianProduct({s64, s32}, {s64})
229       .minScalar(1, s32);
230 
231   getActionDefinitionsBuilder(G_UITOFP)
232       .libcallForCartesianProduct({s64, s32}, {s64})
233       .customForCartesianProduct({s64, s32}, {s32})
234       .minScalar(1, s32);
235 
236   getActionDefinitionsBuilder(G_SEXT_INREG).lower();
237 
238   computeTables();
239   verify(*ST.getInstrInfo());
240 }
241 
242 bool MipsLegalizerInfo::legalizeCustom(MachineInstr &MI,
243                                        MachineRegisterInfo &MRI,
244                                        MachineIRBuilder &MIRBuilder,
245                                        GISelChangeObserver &Observer) const {
246 
247   using namespace TargetOpcode;
248 
249   MIRBuilder.setInstr(MI);
250   const MipsSubtarget &STI =
251       static_cast<const MipsSubtarget &>(MIRBuilder.getMF().getSubtarget());
252   const LLT s32 = LLT::scalar(32);
253   const LLT s64 = LLT::scalar(64);
254 
255   switch (MI.getOpcode()) {
256   case G_UITOFP: {
257     Register Dst = MI.getOperand(0).getReg();
258     Register Src = MI.getOperand(1).getReg();
259     LLT DstTy = MRI.getType(Dst);
260     LLT SrcTy = MRI.getType(Src);
261 
262     if (SrcTy != s32)
263       return false;
264     if (DstTy != s32 && DstTy != s64)
265       return false;
266 
267     // Let 0xABCDEFGH be given unsigned in MI.getOperand(1). First let's convert
268     // unsigned to double. Mantissa has 52 bits so we use following trick:
269     // First make floating point bit mask 0x43300000ABCDEFGH.
270     // Mask represents 2^52 * 0x1.00000ABCDEFGH i.e. 0x100000ABCDEFGH.0 .
271     // Next, subtract  2^52 * 0x1.0000000000000 i.e. 0x10000000000000.0 from it.
272     // Done. Trunc double to float if needed.
273 
274     MachineInstrBuilder Bitcast = MIRBuilder.buildInstr(
275         STI.isFP64bit() ? Mips::BuildPairF64_64 : Mips::BuildPairF64, {s64},
276         {Src, MIRBuilder.buildConstant(s32, UINT32_C(0x43300000))});
277     Bitcast.constrainAllUses(MIRBuilder.getTII(), *STI.getRegisterInfo(),
278                              *STI.getRegBankInfo());
279 
280     MachineInstrBuilder TwoP52FP = MIRBuilder.buildFConstant(
281         s64, BitsToDouble(UINT64_C(0x4330000000000000)));
282 
283     if (DstTy == s64)
284       MIRBuilder.buildFSub(Dst, Bitcast, TwoP52FP);
285     else {
286       MachineInstrBuilder ResF64 = MIRBuilder.buildFSub(s64, Bitcast, TwoP52FP);
287       MIRBuilder.buildFPTrunc(Dst, ResF64);
288     }
289 
290     MI.eraseFromParent();
291     break;
292   }
293   default:
294     return false;
295   }
296 
297   return true;
298 }
299 
300 static bool SelectMSA3OpIntrinsic(MachineInstr &MI, unsigned Opcode,
301                                   MachineIRBuilder &MIRBuilder,
302                                   const MipsSubtarget &ST) {
303   assert(ST.hasMSA() && "MSA intrinsic not supported on target without MSA.");
304   if (!MIRBuilder.buildInstr(Opcode)
305            .add(MI.getOperand(0))
306            .add(MI.getOperand(2))
307            .add(MI.getOperand(3))
308            .constrainAllUses(MIRBuilder.getTII(), *ST.getRegisterInfo(),
309                              *ST.getRegBankInfo()))
310     return false;
311   MI.eraseFromParent();
312   return true;
313 }
314 
315 static bool MSA3OpIntrinsicToGeneric(MachineInstr &MI, unsigned Opcode,
316                                      MachineIRBuilder &MIRBuilder,
317                                      const MipsSubtarget &ST) {
318   assert(ST.hasMSA() && "MSA intrinsic not supported on target without MSA.");
319   MIRBuilder.buildInstr(Opcode)
320       .add(MI.getOperand(0))
321       .add(MI.getOperand(2))
322       .add(MI.getOperand(3));
323   MI.eraseFromParent();
324   return true;
325 }
326 
327 bool MSA2OpIntrinsicToGeneric(MachineInstr &MI, unsigned Opcode,
328                               MachineIRBuilder &MIRBuilder,
329                               const MipsSubtarget &ST) {
330   assert(ST.hasMSA() && "MSA intrinsic not supported on target without MSA.");
331   MIRBuilder.buildInstr(Opcode)
332       .add(MI.getOperand(0))
333       .add(MI.getOperand(2));
334   MI.eraseFromParent();
335   return true;
336 }
337 
338 bool MipsLegalizerInfo::legalizeIntrinsic(MachineInstr &MI,
339                                           MachineRegisterInfo &MRI,
340                                           MachineIRBuilder &MIRBuilder) const {
341   const MipsSubtarget &ST =
342       static_cast<const MipsSubtarget &>(MI.getMF()->getSubtarget());
343   const MipsInstrInfo &TII = *ST.getInstrInfo();
344   const MipsRegisterInfo &TRI = *ST.getRegisterInfo();
345   const RegisterBankInfo &RBI = *ST.getRegBankInfo();
346   MIRBuilder.setInstr(MI);
347 
348   switch (MI.getIntrinsicID()) {
349   case Intrinsic::memcpy:
350   case Intrinsic::memset:
351   case Intrinsic::memmove:
352     if (createMemLibcall(MIRBuilder, MRI, MI) ==
353         LegalizerHelper::UnableToLegalize)
354       return false;
355     MI.eraseFromParent();
356     return true;
357   case Intrinsic::trap: {
358     MachineInstr *Trap = MIRBuilder.buildInstr(Mips::TRAP);
359     MI.eraseFromParent();
360     return constrainSelectedInstRegOperands(*Trap, TII, TRI, RBI);
361   }
362   case Intrinsic::vacopy: {
363     Register Tmp = MRI.createGenericVirtualRegister(LLT::pointer(0, 32));
364     MachinePointerInfo MPO;
365     MIRBuilder.buildLoad(Tmp, MI.getOperand(2),
366                          *MI.getMF()->getMachineMemOperand(
367                              MPO, MachineMemOperand::MOLoad, 4, 4));
368     MIRBuilder.buildStore(Tmp, MI.getOperand(1),
369                           *MI.getMF()->getMachineMemOperand(
370                               MPO, MachineMemOperand::MOStore, 4, 4));
371     MI.eraseFromParent();
372     return true;
373   }
374   case Intrinsic::mips_addv_b:
375   case Intrinsic::mips_addv_h:
376   case Intrinsic::mips_addv_w:
377   case Intrinsic::mips_addv_d:
378     return MSA3OpIntrinsicToGeneric(MI, TargetOpcode::G_ADD, MIRBuilder, ST);
379   case Intrinsic::mips_addvi_b:
380     return SelectMSA3OpIntrinsic(MI, Mips::ADDVI_B, MIRBuilder, ST);
381   case Intrinsic::mips_addvi_h:
382     return SelectMSA3OpIntrinsic(MI, Mips::ADDVI_H, MIRBuilder, ST);
383   case Intrinsic::mips_addvi_w:
384     return SelectMSA3OpIntrinsic(MI, Mips::ADDVI_W, MIRBuilder, ST);
385   case Intrinsic::mips_addvi_d:
386     return SelectMSA3OpIntrinsic(MI, Mips::ADDVI_D, MIRBuilder, ST);
387   case Intrinsic::mips_subv_b:
388   case Intrinsic::mips_subv_h:
389   case Intrinsic::mips_subv_w:
390   case Intrinsic::mips_subv_d:
391     return MSA3OpIntrinsicToGeneric(MI, TargetOpcode::G_SUB, MIRBuilder, ST);
392   case Intrinsic::mips_subvi_b:
393     return SelectMSA3OpIntrinsic(MI, Mips::SUBVI_B, MIRBuilder, ST);
394   case Intrinsic::mips_subvi_h:
395     return SelectMSA3OpIntrinsic(MI, Mips::SUBVI_H, MIRBuilder, ST);
396   case Intrinsic::mips_subvi_w:
397     return SelectMSA3OpIntrinsic(MI, Mips::SUBVI_W, MIRBuilder, ST);
398   case Intrinsic::mips_subvi_d:
399     return SelectMSA3OpIntrinsic(MI, Mips::SUBVI_D, MIRBuilder, ST);
400   case Intrinsic::mips_mulv_b:
401   case Intrinsic::mips_mulv_h:
402   case Intrinsic::mips_mulv_w:
403   case Intrinsic::mips_mulv_d:
404     return MSA3OpIntrinsicToGeneric(MI, TargetOpcode::G_MUL, MIRBuilder, ST);
405   case Intrinsic::mips_div_s_b:
406   case Intrinsic::mips_div_s_h:
407   case Intrinsic::mips_div_s_w:
408   case Intrinsic::mips_div_s_d:
409     return MSA3OpIntrinsicToGeneric(MI, TargetOpcode::G_SDIV, MIRBuilder, ST);
410   case Intrinsic::mips_mod_s_b:
411   case Intrinsic::mips_mod_s_h:
412   case Intrinsic::mips_mod_s_w:
413   case Intrinsic::mips_mod_s_d:
414     return MSA3OpIntrinsicToGeneric(MI, TargetOpcode::G_SREM, MIRBuilder, ST);
415   case Intrinsic::mips_div_u_b:
416   case Intrinsic::mips_div_u_h:
417   case Intrinsic::mips_div_u_w:
418   case Intrinsic::mips_div_u_d:
419     return MSA3OpIntrinsicToGeneric(MI, TargetOpcode::G_UDIV, MIRBuilder, ST);
420   case Intrinsic::mips_mod_u_b:
421   case Intrinsic::mips_mod_u_h:
422   case Intrinsic::mips_mod_u_w:
423   case Intrinsic::mips_mod_u_d:
424     return MSA3OpIntrinsicToGeneric(MI, TargetOpcode::G_UREM, MIRBuilder, ST);
425   case Intrinsic::mips_fadd_w:
426   case Intrinsic::mips_fadd_d:
427     return MSA3OpIntrinsicToGeneric(MI, TargetOpcode::G_FADD, MIRBuilder, ST);
428   case Intrinsic::mips_fsub_w:
429   case Intrinsic::mips_fsub_d:
430     return MSA3OpIntrinsicToGeneric(MI, TargetOpcode::G_FSUB, MIRBuilder, ST);
431   case Intrinsic::mips_fmul_w:
432   case Intrinsic::mips_fmul_d:
433     return MSA3OpIntrinsicToGeneric(MI, TargetOpcode::G_FMUL, MIRBuilder, ST);
434   case Intrinsic::mips_fdiv_w:
435   case Intrinsic::mips_fdiv_d:
436     return MSA3OpIntrinsicToGeneric(MI, TargetOpcode::G_FDIV, MIRBuilder, ST);
437   case Intrinsic::mips_fmax_a_w:
438     return SelectMSA3OpIntrinsic(MI, Mips::FMAX_A_W, MIRBuilder, ST);
439   case Intrinsic::mips_fmax_a_d:
440     return SelectMSA3OpIntrinsic(MI, Mips::FMAX_A_D, MIRBuilder, ST);
441   case Intrinsic::mips_fsqrt_w:
442     return MSA2OpIntrinsicToGeneric(MI, TargetOpcode::G_FSQRT, MIRBuilder, ST);
443   case Intrinsic::mips_fsqrt_d:
444     return MSA2OpIntrinsicToGeneric(MI, TargetOpcode::G_FSQRT, MIRBuilder, ST);
445   default:
446     break;
447   }
448   return true;
449 }
450