1 //===- MipsLegalizerInfo.cpp ------------------------------------*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 /// \file
9 /// This file implements the targeting of the Machinelegalizer class for Mips.
10 /// \todo This should be generated by TableGen.
11 //===----------------------------------------------------------------------===//
12 
13 #include "MipsLegalizerInfo.h"
14 #include "MipsTargetMachine.h"
15 #include "llvm/CodeGen/GlobalISel/LegalizerHelper.h"
16 #include "llvm/IR/IntrinsicsMips.h"
17 
18 using namespace llvm;
19 
20 struct TypesAndMemOps {
21   LLT ValTy;
22   LLT PtrTy;
23   unsigned MemSize;
24   bool MustBeNaturallyAligned;
25 };
26 
27 static bool
28 CheckTy0Ty1MemSizeAlign(const LegalityQuery &Query,
29                         std::initializer_list<TypesAndMemOps> SupportedValues) {
30   for (auto &Val : SupportedValues) {
31     if (Val.ValTy != Query.Types[0])
32       continue;
33     if (Val.PtrTy != Query.Types[1])
34       continue;
35     if (Val.MemSize != Query.MMODescrs[0].SizeInBits)
36       continue;
37     if (Val.MustBeNaturallyAligned &&
38         Query.MMODescrs[0].SizeInBits % Query.MMODescrs[0].AlignInBits != 0)
39       continue;
40     return true;
41   }
42   return false;
43 }
44 
45 static bool CheckTyN(unsigned N, const LegalityQuery &Query,
46                      std::initializer_list<LLT> SupportedValues) {
47   for (auto &Val : SupportedValues)
48     if (Val == Query.Types[N])
49       return true;
50   return false;
51 }
52 
53 MipsLegalizerInfo::MipsLegalizerInfo(const MipsSubtarget &ST) {
54   using namespace TargetOpcode;
55 
56   const LLT s1 = LLT::scalar(1);
57   const LLT s32 = LLT::scalar(32);
58   const LLT s64 = LLT::scalar(64);
59   const LLT v16s8 = LLT::vector(16, 8);
60   const LLT v8s16 = LLT::vector(8, 16);
61   const LLT v4s32 = LLT::vector(4, 32);
62   const LLT v2s64 = LLT::vector(2, 64);
63   const LLT p0 = LLT::pointer(0, 32);
64 
65   getActionDefinitionsBuilder({G_ADD, G_SUB, G_MUL})
66       .legalIf([=, &ST](const LegalityQuery &Query) {
67         if (CheckTyN(0, Query, {s32}))
68           return true;
69         if (ST.hasMSA() && CheckTyN(0, Query, {v16s8, v8s16, v4s32, v2s64}))
70           return true;
71         return false;
72       })
73       .clampScalar(0, s32, s32);
74 
75   getActionDefinitionsBuilder({G_UADDO, G_UADDE, G_USUBO, G_USUBE, G_UMULO})
76       .lowerFor({{s32, s1}});
77 
78   getActionDefinitionsBuilder(G_UMULH)
79       .legalFor({s32})
80       .maxScalar(0, s32);
81 
82   getActionDefinitionsBuilder({G_LOAD, G_STORE})
83       .legalIf([=, &ST](const LegalityQuery &Query) {
84         if (CheckTy0Ty1MemSizeAlign(Query, {{s32, p0, 8, ST.hasMips32r6()},
85                                             {s32, p0, 16, ST.hasMips32r6()},
86                                             {s32, p0, 32, ST.hasMips32r6()},
87                                             {p0, p0, 32, ST.hasMips32r6()},
88                                             {s64, p0, 64, ST.hasMips32r6()}}))
89           return true;
90         if (ST.hasMSA() &&
91             CheckTy0Ty1MemSizeAlign(Query, {{v16s8, p0, 128, false},
92                                             {v8s16, p0, 128, false},
93                                             {v4s32, p0, 128, false},
94                                             {v2s64, p0, 128, false}}))
95           return true;
96         return false;
97       })
98       .minScalar(0, s32);
99 
100   getActionDefinitionsBuilder(G_IMPLICIT_DEF)
101       .legalFor({s32, s64});
102 
103   getActionDefinitionsBuilder(G_UNMERGE_VALUES)
104      .legalFor({{s32, s64}});
105 
106   getActionDefinitionsBuilder(G_MERGE_VALUES)
107      .legalFor({{s64, s32}});
108 
109   getActionDefinitionsBuilder({G_ZEXTLOAD, G_SEXTLOAD})
110       .legalForTypesWithMemDesc({{s32, p0, 8, 8},
111                                  {s32, p0, 16, 8}})
112       .clampScalar(0, s32, s32);
113 
114   getActionDefinitionsBuilder({G_ZEXT, G_SEXT})
115       .legalIf([](const LegalityQuery &Query) { return false; })
116       .maxScalar(0, s32);
117 
118   getActionDefinitionsBuilder(G_TRUNC)
119       .legalIf([](const LegalityQuery &Query) { return false; })
120       .maxScalar(1, s32);
121 
122   getActionDefinitionsBuilder(G_SELECT)
123       .legalForCartesianProduct({p0, s32, s64}, {s32})
124       .minScalar(0, s32)
125       .minScalar(1, s32);
126 
127   getActionDefinitionsBuilder(G_BRCOND)
128       .legalFor({s32})
129       .minScalar(0, s32);
130 
131   getActionDefinitionsBuilder(G_BRJT)
132       .legalFor({{p0, s32}});
133 
134   getActionDefinitionsBuilder(G_BRINDIRECT)
135       .legalFor({p0});
136 
137   getActionDefinitionsBuilder(G_PHI)
138       .legalFor({p0, s32, s64})
139       .minScalar(0, s32);
140 
141   getActionDefinitionsBuilder({G_AND, G_OR, G_XOR})
142       .legalFor({s32})
143       .clampScalar(0, s32, s32);
144 
145   getActionDefinitionsBuilder({G_SDIV, G_SREM, G_UDIV, G_UREM})
146       .legalIf([=, &ST](const LegalityQuery &Query) {
147         if (CheckTyN(0, Query, {s32}))
148           return true;
149         if (ST.hasMSA() && CheckTyN(0, Query, {v16s8, v8s16, v4s32, v2s64}))
150           return true;
151         return false;
152       })
153       .minScalar(0, s32)
154       .libcallFor({s64});
155 
156   getActionDefinitionsBuilder({G_SHL, G_ASHR, G_LSHR})
157       .legalFor({{s32, s32}})
158       .clampScalar(1, s32, s32)
159       .clampScalar(0, s32, s32);
160 
161   getActionDefinitionsBuilder(G_ICMP)
162       .legalForCartesianProduct({s32}, {s32, p0})
163       .clampScalar(1, s32, s32)
164       .minScalar(0, s32);
165 
166   getActionDefinitionsBuilder(G_CONSTANT)
167       .legalFor({s32})
168       .clampScalar(0, s32, s32);
169 
170   getActionDefinitionsBuilder({G_PTR_ADD, G_INTTOPTR})
171       .legalFor({{p0, s32}});
172 
173   getActionDefinitionsBuilder(G_PTRTOINT)
174       .legalFor({{s32, p0}});
175 
176   getActionDefinitionsBuilder(G_FRAME_INDEX)
177       .legalFor({p0});
178 
179   getActionDefinitionsBuilder({G_GLOBAL_VALUE, G_JUMP_TABLE})
180       .legalFor({p0});
181 
182   getActionDefinitionsBuilder(G_DYN_STACKALLOC)
183       .lowerFor({{p0, s32}});
184 
185   getActionDefinitionsBuilder(G_VASTART)
186      .legalFor({p0});
187 
188   getActionDefinitionsBuilder(G_BSWAP)
189       .legalIf([=, &ST](const LegalityQuery &Query) {
190         if (ST.hasMips32r2() && CheckTyN(0, Query, {s32}))
191           return true;
192         return false;
193       })
194       .lowerIf([=, &ST](const LegalityQuery &Query) {
195         if (!ST.hasMips32r2() && CheckTyN(0, Query, {s32}))
196           return true;
197         return false;
198       })
199       .maxScalar(0, s32);
200 
201   getActionDefinitionsBuilder(G_BITREVERSE)
202       .lowerFor({s32})
203       .maxScalar(0, s32);
204 
205   getActionDefinitionsBuilder(G_CTLZ)
206       .legalFor({{s32, s32}})
207       .maxScalar(1, s32);
208   getActionDefinitionsBuilder(G_CTLZ_ZERO_UNDEF)
209       .lowerFor({{s32, s32}});
210 
211   getActionDefinitionsBuilder(G_CTTZ)
212       .lowerFor({{s32, s32}})
213       .maxScalar(1, s32);
214   getActionDefinitionsBuilder(G_CTTZ_ZERO_UNDEF)
215       .lowerFor({{s32, s32}, {s64, s64}});
216 
217   getActionDefinitionsBuilder(G_CTPOP)
218       .lowerFor({{s32, s32}})
219       .clampScalar(1, s32, s32);
220 
221   // FP instructions
222   getActionDefinitionsBuilder(G_FCONSTANT)
223       .legalFor({s32, s64});
224 
225   getActionDefinitionsBuilder({G_FADD, G_FSUB, G_FMUL, G_FDIV, G_FABS, G_FSQRT})
226       .legalIf([=, &ST](const LegalityQuery &Query) {
227         if (CheckTyN(0, Query, {s32, s64}))
228           return true;
229         if (ST.hasMSA() && CheckTyN(0, Query, {v16s8, v8s16, v4s32, v2s64}))
230           return true;
231         return false;
232       });
233 
234   getActionDefinitionsBuilder(G_FCMP)
235       .legalFor({{s32, s32}, {s32, s64}})
236       .minScalar(0, s32);
237 
238   getActionDefinitionsBuilder({G_FCEIL, G_FFLOOR})
239       .libcallFor({s32, s64});
240 
241   getActionDefinitionsBuilder(G_FPEXT)
242       .legalFor({{s64, s32}});
243 
244   getActionDefinitionsBuilder(G_FPTRUNC)
245       .legalFor({{s32, s64}});
246 
247   // FP to int conversion instructions
248   getActionDefinitionsBuilder(G_FPTOSI)
249       .legalForCartesianProduct({s32}, {s64, s32})
250       .libcallForCartesianProduct({s64}, {s64, s32})
251       .minScalar(0, s32);
252 
253   getActionDefinitionsBuilder(G_FPTOUI)
254       .libcallForCartesianProduct({s64}, {s64, s32})
255       .lowerForCartesianProduct({s32}, {s64, s32})
256       .minScalar(0, s32);
257 
258   // Int to FP conversion instructions
259   getActionDefinitionsBuilder(G_SITOFP)
260       .legalForCartesianProduct({s64, s32}, {s32})
261       .libcallForCartesianProduct({s64, s32}, {s64})
262       .minScalar(1, s32);
263 
264   getActionDefinitionsBuilder(G_UITOFP)
265       .libcallForCartesianProduct({s64, s32}, {s64})
266       .customForCartesianProduct({s64, s32}, {s32})
267       .minScalar(1, s32);
268 
269   getActionDefinitionsBuilder(G_SEXT_INREG).lower();
270 
271   computeTables();
272   verify(*ST.getInstrInfo());
273 }
274 
275 bool MipsLegalizerInfo::legalizeCustom(MachineInstr &MI,
276                                        MachineRegisterInfo &MRI,
277                                        MachineIRBuilder &MIRBuilder,
278                                        GISelChangeObserver &Observer) const {
279 
280   using namespace TargetOpcode;
281 
282   MIRBuilder.setInstr(MI);
283   const MipsSubtarget &STI =
284       static_cast<const MipsSubtarget &>(MIRBuilder.getMF().getSubtarget());
285   const LLT s32 = LLT::scalar(32);
286   const LLT s64 = LLT::scalar(64);
287 
288   switch (MI.getOpcode()) {
289   case G_UITOFP: {
290     Register Dst = MI.getOperand(0).getReg();
291     Register Src = MI.getOperand(1).getReg();
292     LLT DstTy = MRI.getType(Dst);
293     LLT SrcTy = MRI.getType(Src);
294 
295     if (SrcTy != s32)
296       return false;
297     if (DstTy != s32 && DstTy != s64)
298       return false;
299 
300     // Let 0xABCDEFGH be given unsigned in MI.getOperand(1). First let's convert
301     // unsigned to double. Mantissa has 52 bits so we use following trick:
302     // First make floating point bit mask 0x43300000ABCDEFGH.
303     // Mask represents 2^52 * 0x1.00000ABCDEFGH i.e. 0x100000ABCDEFGH.0 .
304     // Next, subtract  2^52 * 0x1.0000000000000 i.e. 0x10000000000000.0 from it.
305     // Done. Trunc double to float if needed.
306 
307     MachineInstrBuilder Bitcast = MIRBuilder.buildInstr(
308         STI.isFP64bit() ? Mips::BuildPairF64_64 : Mips::BuildPairF64, {s64},
309         {Src, MIRBuilder.buildConstant(s32, UINT32_C(0x43300000))});
310     Bitcast.constrainAllUses(MIRBuilder.getTII(), *STI.getRegisterInfo(),
311                              *STI.getRegBankInfo());
312 
313     MachineInstrBuilder TwoP52FP = MIRBuilder.buildFConstant(
314         s64, BitsToDouble(UINT64_C(0x4330000000000000)));
315 
316     if (DstTy == s64)
317       MIRBuilder.buildFSub(Dst, Bitcast, TwoP52FP);
318     else {
319       MachineInstrBuilder ResF64 = MIRBuilder.buildFSub(s64, Bitcast, TwoP52FP);
320       MIRBuilder.buildFPTrunc(Dst, ResF64);
321     }
322 
323     MI.eraseFromParent();
324     break;
325   }
326   default:
327     return false;
328   }
329 
330   return true;
331 }
332 
333 static bool SelectMSA3OpIntrinsic(MachineInstr &MI, unsigned Opcode,
334                                   MachineIRBuilder &MIRBuilder,
335                                   const MipsSubtarget &ST) {
336   assert(ST.hasMSA() && "MSA intrinsic not supported on target without MSA.");
337   if (!MIRBuilder.buildInstr(Opcode)
338            .add(MI.getOperand(0))
339            .add(MI.getOperand(2))
340            .add(MI.getOperand(3))
341            .constrainAllUses(MIRBuilder.getTII(), *ST.getRegisterInfo(),
342                              *ST.getRegBankInfo()))
343     return false;
344   MI.eraseFromParent();
345   return true;
346 }
347 
348 static bool MSA3OpIntrinsicToGeneric(MachineInstr &MI, unsigned Opcode,
349                                      MachineIRBuilder &MIRBuilder,
350                                      const MipsSubtarget &ST) {
351   assert(ST.hasMSA() && "MSA intrinsic not supported on target without MSA.");
352   MIRBuilder.buildInstr(Opcode)
353       .add(MI.getOperand(0))
354       .add(MI.getOperand(2))
355       .add(MI.getOperand(3));
356   MI.eraseFromParent();
357   return true;
358 }
359 
360 static bool MSA2OpIntrinsicToGeneric(MachineInstr &MI, unsigned Opcode,
361                                      MachineIRBuilder &MIRBuilder,
362                                      const MipsSubtarget &ST) {
363   assert(ST.hasMSA() && "MSA intrinsic not supported on target without MSA.");
364   MIRBuilder.buildInstr(Opcode)
365       .add(MI.getOperand(0))
366       .add(MI.getOperand(2));
367   MI.eraseFromParent();
368   return true;
369 }
370 
371 bool MipsLegalizerInfo::legalizeIntrinsic(MachineInstr &MI,
372                                           MachineIRBuilder &MIRBuilder,
373                                           GISelChangeObserver &Observer) const {
374   MachineRegisterInfo &MRI = *MIRBuilder.getMRI();
375   const MipsSubtarget &ST =
376       static_cast<const MipsSubtarget &>(MI.getMF()->getSubtarget());
377   const MipsInstrInfo &TII = *ST.getInstrInfo();
378   const MipsRegisterInfo &TRI = *ST.getRegisterInfo();
379   const RegisterBankInfo &RBI = *ST.getRegBankInfo();
380   MIRBuilder.setInstr(MI);
381 
382   switch (MI.getIntrinsicID()) {
383   case Intrinsic::memcpy:
384   case Intrinsic::memset:
385   case Intrinsic::memmove:
386     if (createMemLibcall(MIRBuilder, MRI, MI) ==
387         LegalizerHelper::UnableToLegalize)
388       return false;
389     MI.eraseFromParent();
390     return true;
391   case Intrinsic::trap: {
392     MachineInstr *Trap = MIRBuilder.buildInstr(Mips::TRAP);
393     MI.eraseFromParent();
394     return constrainSelectedInstRegOperands(*Trap, TII, TRI, RBI);
395   }
396   case Intrinsic::vacopy: {
397     MachinePointerInfo MPO;
398     auto Tmp = MIRBuilder.buildLoad(LLT::pointer(0, 32), MI.getOperand(2),
399                                     *MI.getMF()->getMachineMemOperand(
400                                         MPO, MachineMemOperand::MOLoad, 4, 4));
401     MIRBuilder.buildStore(Tmp, MI.getOperand(1),
402                           *MI.getMF()->getMachineMemOperand(
403                               MPO, MachineMemOperand::MOStore, 4, 4));
404     MI.eraseFromParent();
405     return true;
406   }
407   case Intrinsic::mips_addv_b:
408   case Intrinsic::mips_addv_h:
409   case Intrinsic::mips_addv_w:
410   case Intrinsic::mips_addv_d:
411     return MSA3OpIntrinsicToGeneric(MI, TargetOpcode::G_ADD, MIRBuilder, ST);
412   case Intrinsic::mips_addvi_b:
413     return SelectMSA3OpIntrinsic(MI, Mips::ADDVI_B, MIRBuilder, ST);
414   case Intrinsic::mips_addvi_h:
415     return SelectMSA3OpIntrinsic(MI, Mips::ADDVI_H, MIRBuilder, ST);
416   case Intrinsic::mips_addvi_w:
417     return SelectMSA3OpIntrinsic(MI, Mips::ADDVI_W, MIRBuilder, ST);
418   case Intrinsic::mips_addvi_d:
419     return SelectMSA3OpIntrinsic(MI, Mips::ADDVI_D, MIRBuilder, ST);
420   case Intrinsic::mips_subv_b:
421   case Intrinsic::mips_subv_h:
422   case Intrinsic::mips_subv_w:
423   case Intrinsic::mips_subv_d:
424     return MSA3OpIntrinsicToGeneric(MI, TargetOpcode::G_SUB, MIRBuilder, ST);
425   case Intrinsic::mips_subvi_b:
426     return SelectMSA3OpIntrinsic(MI, Mips::SUBVI_B, MIRBuilder, ST);
427   case Intrinsic::mips_subvi_h:
428     return SelectMSA3OpIntrinsic(MI, Mips::SUBVI_H, MIRBuilder, ST);
429   case Intrinsic::mips_subvi_w:
430     return SelectMSA3OpIntrinsic(MI, Mips::SUBVI_W, MIRBuilder, ST);
431   case Intrinsic::mips_subvi_d:
432     return SelectMSA3OpIntrinsic(MI, Mips::SUBVI_D, MIRBuilder, ST);
433   case Intrinsic::mips_mulv_b:
434   case Intrinsic::mips_mulv_h:
435   case Intrinsic::mips_mulv_w:
436   case Intrinsic::mips_mulv_d:
437     return MSA3OpIntrinsicToGeneric(MI, TargetOpcode::G_MUL, MIRBuilder, ST);
438   case Intrinsic::mips_div_s_b:
439   case Intrinsic::mips_div_s_h:
440   case Intrinsic::mips_div_s_w:
441   case Intrinsic::mips_div_s_d:
442     return MSA3OpIntrinsicToGeneric(MI, TargetOpcode::G_SDIV, MIRBuilder, ST);
443   case Intrinsic::mips_mod_s_b:
444   case Intrinsic::mips_mod_s_h:
445   case Intrinsic::mips_mod_s_w:
446   case Intrinsic::mips_mod_s_d:
447     return MSA3OpIntrinsicToGeneric(MI, TargetOpcode::G_SREM, MIRBuilder, ST);
448   case Intrinsic::mips_div_u_b:
449   case Intrinsic::mips_div_u_h:
450   case Intrinsic::mips_div_u_w:
451   case Intrinsic::mips_div_u_d:
452     return MSA3OpIntrinsicToGeneric(MI, TargetOpcode::G_UDIV, MIRBuilder, ST);
453   case Intrinsic::mips_mod_u_b:
454   case Intrinsic::mips_mod_u_h:
455   case Intrinsic::mips_mod_u_w:
456   case Intrinsic::mips_mod_u_d:
457     return MSA3OpIntrinsicToGeneric(MI, TargetOpcode::G_UREM, MIRBuilder, ST);
458   case Intrinsic::mips_fadd_w:
459   case Intrinsic::mips_fadd_d:
460     return MSA3OpIntrinsicToGeneric(MI, TargetOpcode::G_FADD, MIRBuilder, ST);
461   case Intrinsic::mips_fsub_w:
462   case Intrinsic::mips_fsub_d:
463     return MSA3OpIntrinsicToGeneric(MI, TargetOpcode::G_FSUB, MIRBuilder, ST);
464   case Intrinsic::mips_fmul_w:
465   case Intrinsic::mips_fmul_d:
466     return MSA3OpIntrinsicToGeneric(MI, TargetOpcode::G_FMUL, MIRBuilder, ST);
467   case Intrinsic::mips_fdiv_w:
468   case Intrinsic::mips_fdiv_d:
469     return MSA3OpIntrinsicToGeneric(MI, TargetOpcode::G_FDIV, MIRBuilder, ST);
470   case Intrinsic::mips_fmax_a_w:
471     return SelectMSA3OpIntrinsic(MI, Mips::FMAX_A_W, MIRBuilder, ST);
472   case Intrinsic::mips_fmax_a_d:
473     return SelectMSA3OpIntrinsic(MI, Mips::FMAX_A_D, MIRBuilder, ST);
474   case Intrinsic::mips_fsqrt_w:
475     return MSA2OpIntrinsicToGeneric(MI, TargetOpcode::G_FSQRT, MIRBuilder, ST);
476   case Intrinsic::mips_fsqrt_d:
477     return MSA2OpIntrinsicToGeneric(MI, TargetOpcode::G_FSQRT, MIRBuilder, ST);
478   default:
479     break;
480   }
481   return true;
482 }
483