1 //===- MipsLegalizerInfo.cpp ------------------------------------*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 /// \file
9 /// This file implements the targeting of the Machinelegalizer class for Mips.
10 /// \todo This should be generated by TableGen.
11 //===----------------------------------------------------------------------===//
12 
13 #include "MipsLegalizerInfo.h"
14 #include "MipsTargetMachine.h"
15 #include "llvm/CodeGen/GlobalISel/LegalizerHelper.h"
16 
17 using namespace llvm;
18 
19 struct TypesAndMemOps {
20   LLT ValTy;
21   LLT PtrTy;
22   unsigned MemSize;
23   bool MustBeNaturallyAligned;
24 };
25 
26 static bool
27 CheckTy0Ty1MemSizeAlign(const LegalityQuery &Query,
28                         std::initializer_list<TypesAndMemOps> SupportedValues) {
29   for (auto &Val : SupportedValues) {
30     if (Val.ValTy != Query.Types[0])
31       continue;
32     if (Val.PtrTy != Query.Types[1])
33       continue;
34     if (Val.MemSize != Query.MMODescrs[0].SizeInBits)
35       continue;
36     if (Val.MustBeNaturallyAligned &&
37         Query.MMODescrs[0].SizeInBits % Query.MMODescrs[0].AlignInBits != 0)
38       continue;
39     return true;
40   }
41   return false;
42 }
43 
44 static bool CheckTyN(unsigned N, const LegalityQuery &Query,
45                      std::initializer_list<LLT> SupportedValues) {
46   for (auto &Val : SupportedValues)
47     if (Val == Query.Types[N])
48       return true;
49   return false;
50 }
51 
52 MipsLegalizerInfo::MipsLegalizerInfo(const MipsSubtarget &ST) {
53   using namespace TargetOpcode;
54 
55   const LLT s1 = LLT::scalar(1);
56   const LLT s32 = LLT::scalar(32);
57   const LLT s64 = LLT::scalar(64);
58   const LLT v16s8 = LLT::vector(16, 8);
59   const LLT v8s16 = LLT::vector(8, 16);
60   const LLT v4s32 = LLT::vector(4, 32);
61   const LLT v2s64 = LLT::vector(2, 64);
62   const LLT p0 = LLT::pointer(0, 32);
63 
64   getActionDefinitionsBuilder({G_ADD, G_SUB, G_MUL})
65       .legalIf([=, &ST](const LegalityQuery &Query) {
66         if (CheckTyN(0, Query, {s32}))
67           return true;
68         if (ST.hasMSA() && CheckTyN(0, Query, {v16s8, v8s16, v4s32, v2s64}))
69           return true;
70         return false;
71       })
72       .clampScalar(0, s32, s32);
73 
74   getActionDefinitionsBuilder({G_UADDO, G_UADDE, G_USUBO, G_USUBE, G_UMULO})
75       .lowerFor({{s32, s1}});
76 
77   getActionDefinitionsBuilder(G_UMULH)
78       .legalFor({s32})
79       .maxScalar(0, s32);
80 
81   getActionDefinitionsBuilder({G_LOAD, G_STORE})
82       .legalIf([=, &ST](const LegalityQuery &Query) {
83         if (CheckTy0Ty1MemSizeAlign(Query, {{s32, p0, 8, ST.hasMips32r6()},
84                                             {s32, p0, 16, ST.hasMips32r6()},
85                                             {s32, p0, 32, ST.hasMips32r6()},
86                                             {p0, p0, 32, ST.hasMips32r6()},
87                                             {s64, p0, 64, ST.hasMips32r6()}}))
88           return true;
89         if (ST.hasMSA() &&
90             CheckTy0Ty1MemSizeAlign(Query, {{v16s8, p0, 128, false},
91                                             {v8s16, p0, 128, false},
92                                             {v4s32, p0, 128, false},
93                                             {v2s64, p0, 128, false}}))
94           return true;
95         return false;
96       })
97       .minScalar(0, s32);
98 
99   getActionDefinitionsBuilder(G_IMPLICIT_DEF)
100       .legalFor({s32, s64});
101 
102   getActionDefinitionsBuilder(G_UNMERGE_VALUES)
103      .legalFor({{s32, s64}});
104 
105   getActionDefinitionsBuilder(G_MERGE_VALUES)
106      .legalFor({{s64, s32}});
107 
108   getActionDefinitionsBuilder({G_ZEXTLOAD, G_SEXTLOAD})
109       .legalForTypesWithMemDesc({{s32, p0, 8, 8},
110                                  {s32, p0, 16, 8}})
111       .clampScalar(0, s32, s32);
112 
113   getActionDefinitionsBuilder({G_ZEXT, G_SEXT})
114       .legalIf([](const LegalityQuery &Query) { return false; })
115       .maxScalar(0, s32);
116 
117   getActionDefinitionsBuilder(G_TRUNC)
118       .legalIf([](const LegalityQuery &Query) { return false; })
119       .maxScalar(1, s32);
120 
121   getActionDefinitionsBuilder(G_SELECT)
122       .legalForCartesianProduct({p0, s32, s64}, {s32})
123       .minScalar(0, s32)
124       .minScalar(1, s32);
125 
126   getActionDefinitionsBuilder(G_BRCOND)
127       .legalFor({s32})
128       .minScalar(0, s32);
129 
130   getActionDefinitionsBuilder(G_BRJT)
131       .legalFor({{p0, s32}});
132 
133   getActionDefinitionsBuilder(G_BRINDIRECT)
134       .legalFor({p0});
135 
136   getActionDefinitionsBuilder(G_PHI)
137       .legalFor({p0, s32, s64})
138       .minScalar(0, s32);
139 
140   getActionDefinitionsBuilder({G_AND, G_OR, G_XOR})
141       .legalFor({s32})
142       .clampScalar(0, s32, s32);
143 
144   getActionDefinitionsBuilder({G_SDIV, G_SREM, G_UREM, G_UDIV})
145       .legalFor({s32})
146       .minScalar(0, s32)
147       .libcallFor({s64});
148 
149   getActionDefinitionsBuilder({G_SHL, G_ASHR, G_LSHR})
150       .legalFor({{s32, s32}})
151       .clampScalar(1, s32, s32)
152       .clampScalar(0, s32, s32);
153 
154   getActionDefinitionsBuilder(G_ICMP)
155       .legalForCartesianProduct({s32}, {s32, p0})
156       .clampScalar(1, s32, s32)
157       .minScalar(0, s32);
158 
159   getActionDefinitionsBuilder(G_CONSTANT)
160       .legalFor({s32})
161       .clampScalar(0, s32, s32);
162 
163   getActionDefinitionsBuilder({G_GEP, G_INTTOPTR})
164       .legalFor({{p0, s32}});
165 
166   getActionDefinitionsBuilder(G_PTRTOINT)
167       .legalFor({{s32, p0}});
168 
169   getActionDefinitionsBuilder(G_FRAME_INDEX)
170       .legalFor({p0});
171 
172   getActionDefinitionsBuilder({G_GLOBAL_VALUE, G_JUMP_TABLE})
173       .legalFor({p0});
174 
175   getActionDefinitionsBuilder(G_DYN_STACKALLOC)
176       .lowerFor({{p0, s32}});
177 
178   getActionDefinitionsBuilder(G_VASTART)
179      .legalFor({p0});
180 
181   // FP instructions
182   getActionDefinitionsBuilder(G_FCONSTANT)
183       .legalFor({s32, s64});
184 
185   getActionDefinitionsBuilder({G_FADD, G_FSUB, G_FMUL, G_FDIV, G_FABS, G_FSQRT})
186       .legalFor({s32, s64});
187 
188   getActionDefinitionsBuilder(G_FCMP)
189       .legalFor({{s32, s32}, {s32, s64}})
190       .minScalar(0, s32);
191 
192   getActionDefinitionsBuilder({G_FCEIL, G_FFLOOR})
193       .libcallFor({s32, s64});
194 
195   getActionDefinitionsBuilder(G_FPEXT)
196       .legalFor({{s64, s32}});
197 
198   getActionDefinitionsBuilder(G_FPTRUNC)
199       .legalFor({{s32, s64}});
200 
201   // FP to int conversion instructions
202   getActionDefinitionsBuilder(G_FPTOSI)
203       .legalForCartesianProduct({s32}, {s64, s32})
204       .libcallForCartesianProduct({s64}, {s64, s32})
205       .minScalar(0, s32);
206 
207   getActionDefinitionsBuilder(G_FPTOUI)
208       .libcallForCartesianProduct({s64}, {s64, s32})
209       .lowerForCartesianProduct({s32}, {s64, s32})
210       .minScalar(0, s32);
211 
212   // Int to FP conversion instructions
213   getActionDefinitionsBuilder(G_SITOFP)
214       .legalForCartesianProduct({s64, s32}, {s32})
215       .libcallForCartesianProduct({s64, s32}, {s64})
216       .minScalar(1, s32);
217 
218   getActionDefinitionsBuilder(G_UITOFP)
219       .libcallForCartesianProduct({s64, s32}, {s64})
220       .customForCartesianProduct({s64, s32}, {s32})
221       .minScalar(1, s32);
222 
223   getActionDefinitionsBuilder(G_SEXT_INREG).lower();
224 
225   computeTables();
226   verify(*ST.getInstrInfo());
227 }
228 
229 bool MipsLegalizerInfo::legalizeCustom(MachineInstr &MI,
230                                        MachineRegisterInfo &MRI,
231                                        MachineIRBuilder &MIRBuilder,
232                                        GISelChangeObserver &Observer) const {
233 
234   using namespace TargetOpcode;
235 
236   MIRBuilder.setInstr(MI);
237   const MipsSubtarget &STI =
238       static_cast<const MipsSubtarget &>(MIRBuilder.getMF().getSubtarget());
239   const LLT s32 = LLT::scalar(32);
240   const LLT s64 = LLT::scalar(64);
241 
242   switch (MI.getOpcode()) {
243   case G_UITOFP: {
244     Register Dst = MI.getOperand(0).getReg();
245     Register Src = MI.getOperand(1).getReg();
246     LLT DstTy = MRI.getType(Dst);
247     LLT SrcTy = MRI.getType(Src);
248 
249     if (SrcTy != s32)
250       return false;
251     if (DstTy != s32 && DstTy != s64)
252       return false;
253 
254     // Let 0xABCDEFGH be given unsigned in MI.getOperand(1). First let's convert
255     // unsigned to double. Mantissa has 52 bits so we use following trick:
256     // First make floating point bit mask 0x43300000ABCDEFGH.
257     // Mask represents 2^52 * 0x1.00000ABCDEFGH i.e. 0x100000ABCDEFGH.0 .
258     // Next, subtract  2^52 * 0x1.0000000000000 i.e. 0x10000000000000.0 from it.
259     // Done. Trunc double to float if needed.
260 
261     MachineInstrBuilder Bitcast = MIRBuilder.buildInstr(
262         STI.isFP64bit() ? Mips::BuildPairF64_64 : Mips::BuildPairF64, {s64},
263         {Src, MIRBuilder.buildConstant(s32, UINT32_C(0x43300000))});
264     Bitcast.constrainAllUses(MIRBuilder.getTII(), *STI.getRegisterInfo(),
265                              *STI.getRegBankInfo());
266 
267     MachineInstrBuilder TwoP52FP = MIRBuilder.buildFConstant(
268         s64, BitsToDouble(UINT64_C(0x4330000000000000)));
269 
270     if (DstTy == s64)
271       MIRBuilder.buildFSub(Dst, Bitcast, TwoP52FP);
272     else {
273       MachineInstrBuilder ResF64 = MIRBuilder.buildFSub(s64, Bitcast, TwoP52FP);
274       MIRBuilder.buildFPTrunc(Dst, ResF64);
275     }
276 
277     MI.eraseFromParent();
278     break;
279   }
280   default:
281     return false;
282   }
283 
284   return true;
285 }
286 
287 static bool SelectMSA3OpIntrinsic(MachineInstr &MI, unsigned Opcode,
288                                   MachineIRBuilder &MIRBuilder,
289                                   const MipsSubtarget &ST) {
290   assert(ST.hasMSA() && "MSA intrinsic not supported on target without MSA.");
291   if (!MIRBuilder.buildInstr(Opcode)
292            .add(MI.getOperand(0))
293            .add(MI.getOperand(2))
294            .add(MI.getOperand(3))
295            .constrainAllUses(MIRBuilder.getTII(), *ST.getRegisterInfo(),
296                              *ST.getRegBankInfo()))
297     return false;
298   MI.eraseFromParent();
299   return true;
300 }
301 
302 static bool MSA3OpIntrinsicToGeneric(MachineInstr &MI, unsigned Opcode,
303                                      MachineIRBuilder &MIRBuilder,
304                                      const MipsSubtarget &ST) {
305   assert(ST.hasMSA() && "MSA intrinsic not supported on target without MSA.");
306   MIRBuilder.buildInstr(Opcode)
307       .add(MI.getOperand(0))
308       .add(MI.getOperand(2))
309       .add(MI.getOperand(3));
310   MI.eraseFromParent();
311   return true;
312 }
313 
314 bool MipsLegalizerInfo::legalizeIntrinsic(MachineInstr &MI,
315                                           MachineRegisterInfo &MRI,
316                                           MachineIRBuilder &MIRBuilder) const {
317   const MipsSubtarget &ST =
318       static_cast<const MipsSubtarget &>(MI.getMF()->getSubtarget());
319   const MipsInstrInfo &TII = *ST.getInstrInfo();
320   const MipsRegisterInfo &TRI = *ST.getRegisterInfo();
321   const RegisterBankInfo &RBI = *ST.getRegBankInfo();
322   MIRBuilder.setInstr(MI);
323 
324   switch (MI.getIntrinsicID()) {
325   case Intrinsic::memcpy:
326   case Intrinsic::memset:
327   case Intrinsic::memmove:
328     if (createMemLibcall(MIRBuilder, MRI, MI) ==
329         LegalizerHelper::UnableToLegalize)
330       return false;
331     MI.eraseFromParent();
332     return true;
333   case Intrinsic::trap: {
334     MachineInstr *Trap = MIRBuilder.buildInstr(Mips::TRAP);
335     MI.eraseFromParent();
336     return constrainSelectedInstRegOperands(*Trap, TII, TRI, RBI);
337   }
338   case Intrinsic::vacopy: {
339     Register Tmp = MRI.createGenericVirtualRegister(LLT::pointer(0, 32));
340     MachinePointerInfo MPO;
341     MIRBuilder.buildLoad(Tmp, MI.getOperand(2),
342                          *MI.getMF()->getMachineMemOperand(
343                              MPO, MachineMemOperand::MOLoad, 4, 4));
344     MIRBuilder.buildStore(Tmp, MI.getOperand(1),
345                           *MI.getMF()->getMachineMemOperand(
346                               MPO, MachineMemOperand::MOStore, 4, 4));
347     MI.eraseFromParent();
348     return true;
349   }
350   case Intrinsic::mips_addv_b:
351   case Intrinsic::mips_addv_h:
352   case Intrinsic::mips_addv_w:
353   case Intrinsic::mips_addv_d:
354     return MSA3OpIntrinsicToGeneric(MI, TargetOpcode::G_ADD, MIRBuilder, ST);
355   case Intrinsic::mips_addvi_b:
356     return SelectMSA3OpIntrinsic(MI, Mips::ADDVI_B, MIRBuilder, ST);
357   case Intrinsic::mips_addvi_h:
358     return SelectMSA3OpIntrinsic(MI, Mips::ADDVI_H, MIRBuilder, ST);
359   case Intrinsic::mips_addvi_w:
360     return SelectMSA3OpIntrinsic(MI, Mips::ADDVI_W, MIRBuilder, ST);
361   case Intrinsic::mips_addvi_d:
362     return SelectMSA3OpIntrinsic(MI, Mips::ADDVI_D, MIRBuilder, ST);
363   case Intrinsic::mips_subv_b:
364   case Intrinsic::mips_subv_h:
365   case Intrinsic::mips_subv_w:
366   case Intrinsic::mips_subv_d:
367     return MSA3OpIntrinsicToGeneric(MI, TargetOpcode::G_SUB, MIRBuilder, ST);
368   case Intrinsic::mips_subvi_b:
369     return SelectMSA3OpIntrinsic(MI, Mips::SUBVI_B, MIRBuilder, ST);
370   case Intrinsic::mips_subvi_h:
371     return SelectMSA3OpIntrinsic(MI, Mips::SUBVI_H, MIRBuilder, ST);
372   case Intrinsic::mips_subvi_w:
373     return SelectMSA3OpIntrinsic(MI, Mips::SUBVI_W, MIRBuilder, ST);
374   case Intrinsic::mips_subvi_d:
375     return SelectMSA3OpIntrinsic(MI, Mips::SUBVI_D, MIRBuilder, ST);
376   case Intrinsic::mips_mulv_b:
377   case Intrinsic::mips_mulv_h:
378   case Intrinsic::mips_mulv_w:
379   case Intrinsic::mips_mulv_d:
380     return MSA3OpIntrinsicToGeneric(MI, TargetOpcode::G_MUL, MIRBuilder, ST);
381   default:
382     break;
383   }
384   return true;
385 }
386