1 //===- MipsInstructionSelector.cpp ------------------------------*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 /// \file
9 /// This file implements the targeting of the InstructionSelector class for
10 /// Mips.
11 /// \todo This should be generated by TableGen.
12 //===----------------------------------------------------------------------===//
13 
14 #include "MipsRegisterBankInfo.h"
15 #include "MipsTargetMachine.h"
16 #include "llvm/CodeGen/GlobalISel/InstructionSelectorImpl.h"
17 #include "llvm/CodeGen/GlobalISel/MachineIRBuilder.h"
18 
19 #define DEBUG_TYPE "mips-isel"
20 
21 using namespace llvm;
22 
23 namespace {
24 
25 #define GET_GLOBALISEL_PREDICATE_BITSET
26 #include "MipsGenGlobalISel.inc"
27 #undef GET_GLOBALISEL_PREDICATE_BITSET
28 
29 class MipsInstructionSelector : public InstructionSelector {
30 public:
31   MipsInstructionSelector(const MipsTargetMachine &TM, const MipsSubtarget &STI,
32                           const MipsRegisterBankInfo &RBI);
33 
34   bool select(MachineInstr &I, CodeGenCoverage &CoverageInfo) const override;
35   static const char *getName() { return DEBUG_TYPE; }
36 
37 private:
38   bool selectImpl(MachineInstr &I, CodeGenCoverage &CoverageInfo) const;
39 
40   const MipsTargetMachine &TM;
41   const MipsSubtarget &STI;
42   const MipsInstrInfo &TII;
43   const MipsRegisterInfo &TRI;
44   const MipsRegisterBankInfo &RBI;
45 
46 #define GET_GLOBALISEL_PREDICATES_DECL
47 #include "MipsGenGlobalISel.inc"
48 #undef GET_GLOBALISEL_PREDICATES_DECL
49 
50 #define GET_GLOBALISEL_TEMPORARIES_DECL
51 #include "MipsGenGlobalISel.inc"
52 #undef GET_GLOBALISEL_TEMPORARIES_DECL
53 };
54 
55 } // end anonymous namespace
56 
57 #define GET_GLOBALISEL_IMPL
58 #include "MipsGenGlobalISel.inc"
59 #undef GET_GLOBALISEL_IMPL
60 
61 MipsInstructionSelector::MipsInstructionSelector(
62     const MipsTargetMachine &TM, const MipsSubtarget &STI,
63     const MipsRegisterBankInfo &RBI)
64     : InstructionSelector(), TM(TM), STI(STI), TII(*STI.getInstrInfo()),
65       TRI(*STI.getRegisterInfo()), RBI(RBI),
66 
67 #define GET_GLOBALISEL_PREDICATES_INIT
68 #include "MipsGenGlobalISel.inc"
69 #undef GET_GLOBALISEL_PREDICATES_INIT
70 #define GET_GLOBALISEL_TEMPORARIES_INIT
71 #include "MipsGenGlobalISel.inc"
72 #undef GET_GLOBALISEL_TEMPORARIES_INIT
73 {
74 }
75 
76 static bool selectCopy(MachineInstr &I, const TargetInstrInfo &TII,
77                        MachineRegisterInfo &MRI, const TargetRegisterInfo &TRI,
78                        const RegisterBankInfo &RBI) {
79   unsigned DstReg = I.getOperand(0).getReg();
80   if (TargetRegisterInfo::isPhysicalRegister(DstReg))
81     return true;
82 
83   const TargetRegisterClass *RC = &Mips::GPR32RegClass;
84 
85   if (!RBI.constrainGenericRegister(DstReg, *RC, MRI)) {
86     LLVM_DEBUG(dbgs() << "Failed to constrain " << TII.getName(I.getOpcode())
87                       << " operand\n");
88     return false;
89   }
90   return true;
91 }
92 
93 /// Returning Opc indicates that we failed to select MIPS instruction opcode.
94 static unsigned selectLoadStoreOpCode(unsigned Opc, unsigned MemSizeInBytes) {
95   if (Opc == TargetOpcode::G_STORE)
96     switch (MemSizeInBytes) {
97     case 4:
98       return Mips::SW;
99     case 2:
100       return Mips::SH;
101     case 1:
102       return Mips::SB;
103     default:
104       return Opc;
105     }
106   else
107     // Unspecified extending load is selected into zeroExtending load.
108     switch (MemSizeInBytes) {
109     case 4:
110       return Mips::LW;
111     case 2:
112       return Opc == TargetOpcode::G_SEXTLOAD ? Mips::LH : Mips::LHu;
113     case 1:
114       return Opc == TargetOpcode::G_SEXTLOAD ? Mips::LB : Mips::LBu;
115     default:
116       return Opc;
117     }
118 }
119 
120 bool MipsInstructionSelector::select(MachineInstr &I,
121                                      CodeGenCoverage &CoverageInfo) const {
122 
123   MachineBasicBlock &MBB = *I.getParent();
124   MachineFunction &MF = *MBB.getParent();
125   MachineRegisterInfo &MRI = MF.getRegInfo();
126 
127   if (!isPreISelGenericOpcode(I.getOpcode())) {
128     if (I.isCopy())
129       return selectCopy(I, TII, MRI, TRI, RBI);
130 
131     return true;
132   }
133 
134   if (selectImpl(I, CoverageInfo)) {
135     return true;
136   }
137 
138   MachineInstr *MI = nullptr;
139   using namespace TargetOpcode;
140 
141   switch (I.getOpcode()) {
142   case G_UMULH: {
143     unsigned PseudoMULTuReg = MRI.createVirtualRegister(&Mips::ACC64RegClass);
144     MachineInstr *PseudoMULTu, *PseudoMove;
145 
146     PseudoMULTu = BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::PseudoMULTu))
147                       .addDef(PseudoMULTuReg)
148                       .add(I.getOperand(1))
149                       .add(I.getOperand(2));
150     if (!constrainSelectedInstRegOperands(*PseudoMULTu, TII, TRI, RBI))
151       return false;
152 
153     PseudoMove = BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::PseudoMFHI))
154                      .addDef(I.getOperand(0).getReg())
155                      .addUse(PseudoMULTuReg);
156     if (!constrainSelectedInstRegOperands(*PseudoMove, TII, TRI, RBI))
157       return false;
158 
159     I.eraseFromParent();
160     return true;
161   }
162   case G_GEP: {
163     MI = BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::ADDu))
164              .add(I.getOperand(0))
165              .add(I.getOperand(1))
166              .add(I.getOperand(2));
167     break;
168   }
169   case G_FRAME_INDEX: {
170     MI = BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::ADDiu))
171              .add(I.getOperand(0))
172              .add(I.getOperand(1))
173              .addImm(0);
174     break;
175   }
176   case G_BRCOND: {
177     MI = BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::BNE))
178              .add(I.getOperand(0))
179              .addUse(Mips::ZERO)
180              .add(I.getOperand(1));
181     break;
182   }
183   case G_PHI: {
184     const unsigned DestReg = I.getOperand(0).getReg();
185     const unsigned DestRegBank = RBI.getRegBank(DestReg, MRI, TRI)->getID();
186     const unsigned OpSize = MRI.getType(DestReg).getSizeInBits();
187 
188     if (DestRegBank != Mips::GPRBRegBankID || OpSize != 32)
189       return false;
190 
191     const TargetRegisterClass *DefRC = &Mips::GPR32RegClass;
192     I.setDesc(TII.get(TargetOpcode::PHI));
193     return RBI.constrainGenericRegister(DestReg, *DefRC, MRI);
194   }
195   case G_STORE:
196   case G_LOAD:
197   case G_ZEXTLOAD:
198   case G_SEXTLOAD: {
199     const unsigned DestReg = I.getOperand(0).getReg();
200     const unsigned DestRegBank = RBI.getRegBank(DestReg, MRI, TRI)->getID();
201     const unsigned OpSize = MRI.getType(DestReg).getSizeInBits();
202     const unsigned OpMemSizeInBytes = (*I.memoperands_begin())->getSize();
203 
204     if (DestRegBank != Mips::GPRBRegBankID || OpSize != 32)
205       return false;
206 
207     const unsigned NewOpc =
208         selectLoadStoreOpCode(I.getOpcode(), OpMemSizeInBytes);
209     if (NewOpc == I.getOpcode())
210       return false;
211 
212     MI = BuildMI(MBB, I, I.getDebugLoc(), TII.get(NewOpc))
213              .add(I.getOperand(0))
214              .add(I.getOperand(1))
215              .addImm(0)
216              .addMemOperand(*I.memoperands_begin());
217     break;
218   }
219   case G_UDIV:
220   case G_UREM:
221   case G_SDIV:
222   case G_SREM: {
223     unsigned HILOReg = MRI.createVirtualRegister(&Mips::ACC64RegClass);
224     bool IsSigned = I.getOpcode() == G_SREM || I.getOpcode() == G_SDIV;
225     bool IsDiv = I.getOpcode() == G_UDIV || I.getOpcode() == G_SDIV;
226 
227     MachineInstr *PseudoDIV, *PseudoMove;
228     PseudoDIV = BuildMI(MBB, I, I.getDebugLoc(),
229                         TII.get(IsSigned ? Mips::PseudoSDIV : Mips::PseudoUDIV))
230                     .addDef(HILOReg)
231                     .add(I.getOperand(1))
232                     .add(I.getOperand(2));
233     if (!constrainSelectedInstRegOperands(*PseudoDIV, TII, TRI, RBI))
234       return false;
235 
236     PseudoMove = BuildMI(MBB, I, I.getDebugLoc(),
237                          TII.get(IsDiv ? Mips::PseudoMFLO : Mips::PseudoMFHI))
238                      .addDef(I.getOperand(0).getReg())
239                      .addUse(HILOReg);
240     if (!constrainSelectedInstRegOperands(*PseudoMove, TII, TRI, RBI))
241       return false;
242 
243     I.eraseFromParent();
244     return true;
245   }
246   case G_SELECT: {
247     // Handle operands with pointer type.
248     MI = BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::MOVN_I_I))
249              .add(I.getOperand(0))
250              .add(I.getOperand(2))
251              .add(I.getOperand(1))
252              .add(I.getOperand(3));
253     break;
254   }
255   case G_CONSTANT: {
256     int Imm = I.getOperand(1).getCImm()->getValue().getLimitedValue();
257     unsigned LUiReg = MRI.createVirtualRegister(&Mips::GPR32RegClass);
258     MachineInstr *LUi, *ORi;
259 
260     LUi = BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::LUi))
261               .addDef(LUiReg)
262               .addImm(Imm >> 16);
263 
264     ORi = BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::ORi))
265               .addDef(I.getOperand(0).getReg())
266               .addUse(LUiReg)
267               .addImm(Imm & 0xFFFF);
268 
269     if (!constrainSelectedInstRegOperands(*LUi, TII, TRI, RBI))
270       return false;
271     if (!constrainSelectedInstRegOperands(*ORi, TII, TRI, RBI))
272       return false;
273 
274     I.eraseFromParent();
275     return true;
276   }
277   case G_GLOBAL_VALUE: {
278     if (MF.getTarget().isPositionIndependent())
279       return false;
280 
281     const llvm::GlobalValue *GVal = I.getOperand(1).getGlobal();
282     unsigned LUiReg = MRI.createVirtualRegister(&Mips::GPR32RegClass);
283     MachineInstr *LUi, *ADDiu;
284 
285     LUi = BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::LUi))
286               .addDef(LUiReg)
287               .addGlobalAddress(GVal);
288     LUi->getOperand(1).setTargetFlags(MipsII::MO_ABS_HI);
289 
290     ADDiu = BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::ADDiu))
291                 .addDef(I.getOperand(0).getReg())
292                 .addUse(LUiReg)
293                 .addGlobalAddress(GVal);
294     ADDiu->getOperand(2).setTargetFlags(MipsII::MO_ABS_LO);
295 
296     if (!constrainSelectedInstRegOperands(*LUi, TII, TRI, RBI))
297       return false;
298     if (!constrainSelectedInstRegOperands(*ADDiu, TII, TRI, RBI))
299       return false;
300 
301     I.eraseFromParent();
302     return true;
303   }
304   case G_ICMP: {
305     struct Instr {
306       unsigned Opcode, Def, LHS, RHS;
307       Instr(unsigned Opcode, unsigned Def, unsigned LHS, unsigned RHS)
308           : Opcode(Opcode), Def(Def), LHS(LHS), RHS(RHS){};
309 
310       bool hasImm() const {
311         if (Opcode == Mips::SLTiu || Opcode == Mips::XORi)
312           return true;
313         return false;
314       }
315     };
316 
317     SmallVector<struct Instr, 2> Instructions;
318     unsigned ICMPReg = I.getOperand(0).getReg();
319     unsigned Temp = MRI.createVirtualRegister(&Mips::GPR32RegClass);
320     unsigned LHS = I.getOperand(2).getReg();
321     unsigned RHS = I.getOperand(3).getReg();
322     CmpInst::Predicate Cond =
323         static_cast<CmpInst::Predicate>(I.getOperand(1).getPredicate());
324 
325     switch (Cond) {
326     case CmpInst::ICMP_EQ: // LHS == RHS -> (LHS ^ RHS) < 1
327       Instructions.emplace_back(Mips::XOR, Temp, LHS, RHS);
328       Instructions.emplace_back(Mips::SLTiu, ICMPReg, Temp, 1);
329       break;
330     case CmpInst::ICMP_NE: // LHS != RHS -> 0 < (LHS ^ RHS)
331       Instructions.emplace_back(Mips::XOR, Temp, LHS, RHS);
332       Instructions.emplace_back(Mips::SLTu, ICMPReg, Mips::ZERO, Temp);
333       break;
334     case CmpInst::ICMP_UGT: // LHS >  RHS -> RHS < LHS
335       Instructions.emplace_back(Mips::SLTu, ICMPReg, RHS, LHS);
336       break;
337     case CmpInst::ICMP_UGE: // LHS >= RHS -> !(LHS < RHS)
338       Instructions.emplace_back(Mips::SLTu, Temp, LHS, RHS);
339       Instructions.emplace_back(Mips::XORi, ICMPReg, Temp, 1);
340       break;
341     case CmpInst::ICMP_ULT: // LHS <  RHS -> LHS < RHS
342       Instructions.emplace_back(Mips::SLTu, ICMPReg, LHS, RHS);
343       break;
344     case CmpInst::ICMP_ULE: // LHS <= RHS -> !(RHS < LHS)
345       Instructions.emplace_back(Mips::SLTu, Temp, RHS, LHS);
346       Instructions.emplace_back(Mips::XORi, ICMPReg, Temp, 1);
347       break;
348     case CmpInst::ICMP_SGT: // LHS >  RHS -> RHS < LHS
349       Instructions.emplace_back(Mips::SLT, ICMPReg, RHS, LHS);
350       break;
351     case CmpInst::ICMP_SGE: // LHS >= RHS -> !(LHS < RHS)
352       Instructions.emplace_back(Mips::SLT, Temp, LHS, RHS);
353       Instructions.emplace_back(Mips::XORi, ICMPReg, Temp, 1);
354       break;
355     case CmpInst::ICMP_SLT: // LHS <  RHS -> LHS < RHS
356       Instructions.emplace_back(Mips::SLT, ICMPReg, LHS, RHS);
357       break;
358     case CmpInst::ICMP_SLE: // LHS <= RHS -> !(RHS < LHS)
359       Instructions.emplace_back(Mips::SLT, Temp, RHS, LHS);
360       Instructions.emplace_back(Mips::XORi, ICMPReg, Temp, 1);
361       break;
362     default:
363       return false;
364     }
365 
366     MachineIRBuilder B(I);
367     for (const struct Instr &Instruction : Instructions) {
368       MachineInstrBuilder MIB = B.buildInstr(
369           Instruction.Opcode, {Instruction.Def}, {Instruction.LHS});
370 
371       if (Instruction.hasImm())
372         MIB.addImm(Instruction.RHS);
373       else
374         MIB.addUse(Instruction.RHS);
375 
376       if (!MIB.constrainAllUses(TII, TRI, RBI))
377         return false;
378     }
379 
380     I.eraseFromParent();
381     return true;
382   }
383   default:
384     return false;
385   }
386 
387   I.eraseFromParent();
388   return constrainSelectedInstRegOperands(*MI, TII, TRI, RBI);
389 }
390 
391 namespace llvm {
392 InstructionSelector *createMipsInstructionSelector(const MipsTargetMachine &TM,
393                                                    MipsSubtarget &Subtarget,
394                                                    MipsRegisterBankInfo &RBI) {
395   return new MipsInstructionSelector(TM, Subtarget, RBI);
396 }
397 } // end namespace llvm
398