1 //===- MipsInstructionSelector.cpp ------------------------------*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 /// \file
9 /// This file implements the targeting of the InstructionSelector class for
10 /// Mips.
11 /// \todo This should be generated by TableGen.
12 //===----------------------------------------------------------------------===//
13 
14 #include "MipsRegisterBankInfo.h"
15 #include "MipsTargetMachine.h"
16 #include "llvm/CodeGen/GlobalISel/InstructionSelectorImpl.h"
17 #include "llvm/CodeGen/GlobalISel/MachineIRBuilder.h"
18 
19 #define DEBUG_TYPE "mips-isel"
20 
21 using namespace llvm;
22 
23 namespace {
24 
25 #define GET_GLOBALISEL_PREDICATE_BITSET
26 #include "MipsGenGlobalISel.inc"
27 #undef GET_GLOBALISEL_PREDICATE_BITSET
28 
29 class MipsInstructionSelector : public InstructionSelector {
30 public:
31   MipsInstructionSelector(const MipsTargetMachine &TM, const MipsSubtarget &STI,
32                           const MipsRegisterBankInfo &RBI);
33 
34   bool select(MachineInstr &I, CodeGenCoverage &CoverageInfo) const override;
35   static const char *getName() { return DEBUG_TYPE; }
36 
37 private:
38   bool selectImpl(MachineInstr &I, CodeGenCoverage &CoverageInfo) const;
39 
40   const MipsTargetMachine &TM;
41   const MipsSubtarget &STI;
42   const MipsInstrInfo &TII;
43   const MipsRegisterInfo &TRI;
44   const MipsRegisterBankInfo &RBI;
45 
46 #define GET_GLOBALISEL_PREDICATES_DECL
47 #include "MipsGenGlobalISel.inc"
48 #undef GET_GLOBALISEL_PREDICATES_DECL
49 
50 #define GET_GLOBALISEL_TEMPORARIES_DECL
51 #include "MipsGenGlobalISel.inc"
52 #undef GET_GLOBALISEL_TEMPORARIES_DECL
53 };
54 
55 } // end anonymous namespace
56 
57 #define GET_GLOBALISEL_IMPL
58 #include "MipsGenGlobalISel.inc"
59 #undef GET_GLOBALISEL_IMPL
60 
61 MipsInstructionSelector::MipsInstructionSelector(
62     const MipsTargetMachine &TM, const MipsSubtarget &STI,
63     const MipsRegisterBankInfo &RBI)
64     : InstructionSelector(), TM(TM), STI(STI), TII(*STI.getInstrInfo()),
65       TRI(*STI.getRegisterInfo()), RBI(RBI),
66 
67 #define GET_GLOBALISEL_PREDICATES_INIT
68 #include "MipsGenGlobalISel.inc"
69 #undef GET_GLOBALISEL_PREDICATES_INIT
70 #define GET_GLOBALISEL_TEMPORARIES_INIT
71 #include "MipsGenGlobalISel.inc"
72 #undef GET_GLOBALISEL_TEMPORARIES_INIT
73 {
74 }
75 
76 static bool selectCopy(MachineInstr &I, const TargetInstrInfo &TII,
77                        MachineRegisterInfo &MRI, const TargetRegisterInfo &TRI,
78                        const RegisterBankInfo &RBI) {
79   unsigned DstReg = I.getOperand(0).getReg();
80   if (TargetRegisterInfo::isPhysicalRegister(DstReg))
81     return true;
82 
83   const TargetRegisterClass *RC = &Mips::GPR32RegClass;
84 
85   if (!RBI.constrainGenericRegister(DstReg, *RC, MRI)) {
86     LLVM_DEBUG(dbgs() << "Failed to constrain " << TII.getName(I.getOpcode())
87                       << " operand\n");
88     return false;
89   }
90   return true;
91 }
92 
93 /// Returning Opc indicates that we failed to select MIPS instruction opcode.
94 static unsigned selectLoadStoreOpCode(unsigned Opc, unsigned MemSizeInBytes) {
95   if (Opc == TargetOpcode::G_STORE)
96     switch (MemSizeInBytes) {
97     case 4:
98       return Mips::SW;
99     case 2:
100       return Mips::SH;
101     case 1:
102       return Mips::SB;
103     default:
104       return Opc;
105     }
106   else
107     // Unspecified extending load is selected into zeroExtending load.
108     switch (MemSizeInBytes) {
109     case 4:
110       return Mips::LW;
111     case 2:
112       return Opc == TargetOpcode::G_SEXTLOAD ? Mips::LH : Mips::LHu;
113     case 1:
114       return Opc == TargetOpcode::G_SEXTLOAD ? Mips::LB : Mips::LBu;
115     default:
116       return Opc;
117     }
118 }
119 
120 bool MipsInstructionSelector::select(MachineInstr &I,
121                                      CodeGenCoverage &CoverageInfo) const {
122 
123   MachineBasicBlock &MBB = *I.getParent();
124   MachineFunction &MF = *MBB.getParent();
125   MachineRegisterInfo &MRI = MF.getRegInfo();
126 
127   if (!isPreISelGenericOpcode(I.getOpcode())) {
128     if (I.isCopy())
129       return selectCopy(I, TII, MRI, TRI, RBI);
130 
131     return true;
132   }
133 
134   if (selectImpl(I, CoverageInfo)) {
135     return true;
136   }
137 
138   MachineInstr *MI = nullptr;
139   using namespace TargetOpcode;
140 
141   switch (I.getOpcode()) {
142   case G_GEP: {
143     MI = BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::ADDu))
144              .add(I.getOperand(0))
145              .add(I.getOperand(1))
146              .add(I.getOperand(2));
147     break;
148   }
149   case G_FRAME_INDEX: {
150     MI = BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::ADDiu))
151              .add(I.getOperand(0))
152              .add(I.getOperand(1))
153              .addImm(0);
154     break;
155   }
156   case G_STORE:
157   case G_LOAD:
158   case G_ZEXTLOAD:
159   case G_SEXTLOAD: {
160     const unsigned DestReg = I.getOperand(0).getReg();
161     const unsigned DestRegBank = RBI.getRegBank(DestReg, MRI, TRI)->getID();
162     const unsigned OpSize = MRI.getType(DestReg).getSizeInBits();
163     const unsigned OpMemSizeInBytes = (*I.memoperands_begin())->getSize();
164 
165     if (DestRegBank != Mips::GPRBRegBankID || OpSize != 32)
166       return false;
167 
168     const unsigned NewOpc =
169         selectLoadStoreOpCode(I.getOpcode(), OpMemSizeInBytes);
170     if (NewOpc == I.getOpcode())
171       return false;
172 
173     MI = BuildMI(MBB, I, I.getDebugLoc(), TII.get(NewOpc))
174              .add(I.getOperand(0))
175              .add(I.getOperand(1))
176              .addImm(0)
177              .addMemOperand(*I.memoperands_begin());
178     break;
179   }
180   case G_UDIV:
181   case G_UREM:
182   case G_SDIV:
183   case G_SREM: {
184     unsigned HILOReg = MRI.createVirtualRegister(&Mips::ACC64RegClass);
185     bool IsSigned = I.getOpcode() == G_SREM || I.getOpcode() == G_SDIV;
186     bool IsDiv = I.getOpcode() == G_UDIV || I.getOpcode() == G_SDIV;
187 
188     MachineInstr *PseudoDIV, *PseudoMove;
189     PseudoDIV = BuildMI(MBB, I, I.getDebugLoc(),
190                         TII.get(IsSigned ? Mips::PseudoSDIV : Mips::PseudoUDIV))
191                     .addDef(HILOReg)
192                     .add(I.getOperand(1))
193                     .add(I.getOperand(2));
194     if (!constrainSelectedInstRegOperands(*PseudoDIV, TII, TRI, RBI))
195       return false;
196 
197     PseudoMove = BuildMI(MBB, I, I.getDebugLoc(),
198                          TII.get(IsDiv ? Mips::PseudoMFLO : Mips::PseudoMFHI))
199                      .addDef(I.getOperand(0).getReg())
200                      .addUse(HILOReg);
201     if (!constrainSelectedInstRegOperands(*PseudoMove, TII, TRI, RBI))
202       return false;
203 
204     I.eraseFromParent();
205     return true;
206   }
207   case G_SELECT: {
208     // Handle operands with pointer type.
209     MI = BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::MOVN_I_I))
210              .add(I.getOperand(0))
211              .add(I.getOperand(2))
212              .add(I.getOperand(1))
213              .add(I.getOperand(3));
214     break;
215   }
216   case G_CONSTANT: {
217     int Imm = I.getOperand(1).getCImm()->getValue().getLimitedValue();
218     unsigned LUiReg = MRI.createVirtualRegister(&Mips::GPR32RegClass);
219     MachineInstr *LUi, *ORi;
220 
221     LUi = BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::LUi))
222               .addDef(LUiReg)
223               .addImm(Imm >> 16);
224 
225     ORi = BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::ORi))
226               .addDef(I.getOperand(0).getReg())
227               .addUse(LUiReg)
228               .addImm(Imm & 0xFFFF);
229 
230     if (!constrainSelectedInstRegOperands(*LUi, TII, TRI, RBI))
231       return false;
232     if (!constrainSelectedInstRegOperands(*ORi, TII, TRI, RBI))
233       return false;
234 
235     I.eraseFromParent();
236     return true;
237   }
238   case G_GLOBAL_VALUE: {
239     if (MF.getTarget().isPositionIndependent())
240       return false;
241 
242     const llvm::GlobalValue *GVal = I.getOperand(1).getGlobal();
243     unsigned LUiReg = MRI.createVirtualRegister(&Mips::GPR32RegClass);
244     MachineInstr *LUi, *ADDiu;
245 
246     LUi = BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::LUi))
247               .addDef(LUiReg)
248               .addGlobalAddress(GVal);
249     LUi->getOperand(1).setTargetFlags(MipsII::MO_ABS_HI);
250 
251     ADDiu = BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::ADDiu))
252                 .addDef(I.getOperand(0).getReg())
253                 .addUse(LUiReg)
254                 .addGlobalAddress(GVal);
255     ADDiu->getOperand(2).setTargetFlags(MipsII::MO_ABS_LO);
256 
257     if (!constrainSelectedInstRegOperands(*LUi, TII, TRI, RBI))
258       return false;
259     if (!constrainSelectedInstRegOperands(*ADDiu, TII, TRI, RBI))
260       return false;
261 
262     I.eraseFromParent();
263     return true;
264   }
265   case G_ICMP: {
266     struct Instr {
267       unsigned Opcode, Def, LHS, RHS;
268       Instr(unsigned Opcode, unsigned Def, unsigned LHS, unsigned RHS)
269           : Opcode(Opcode), Def(Def), LHS(LHS), RHS(RHS){};
270 
271       bool hasImm() const {
272         if (Opcode == Mips::SLTiu || Opcode == Mips::XORi)
273           return true;
274         return false;
275       }
276     };
277 
278     SmallVector<struct Instr, 2> Instructions;
279     unsigned ICMPReg = I.getOperand(0).getReg();
280     unsigned Temp = MRI.createVirtualRegister(&Mips::GPR32RegClass);
281     unsigned LHS = I.getOperand(2).getReg();
282     unsigned RHS = I.getOperand(3).getReg();
283     CmpInst::Predicate Cond =
284         static_cast<CmpInst::Predicate>(I.getOperand(1).getPredicate());
285 
286     switch (Cond) {
287     case CmpInst::ICMP_EQ: // LHS == RHS -> (LHS ^ RHS) < 1
288       Instructions.emplace_back(Mips::XOR, Temp, LHS, RHS);
289       Instructions.emplace_back(Mips::SLTiu, ICMPReg, Temp, 1);
290       break;
291     case CmpInst::ICMP_NE: // LHS != RHS -> 0 < (LHS ^ RHS)
292       Instructions.emplace_back(Mips::XOR, Temp, LHS, RHS);
293       Instructions.emplace_back(Mips::SLTu, ICMPReg, Mips::ZERO, Temp);
294       break;
295     case CmpInst::ICMP_UGT: // LHS >  RHS -> RHS < LHS
296       Instructions.emplace_back(Mips::SLTu, ICMPReg, RHS, LHS);
297       break;
298     case CmpInst::ICMP_UGE: // LHS >= RHS -> !(LHS < RHS)
299       Instructions.emplace_back(Mips::SLTu, Temp, LHS, RHS);
300       Instructions.emplace_back(Mips::XORi, ICMPReg, Temp, 1);
301       break;
302     case CmpInst::ICMP_ULT: // LHS <  RHS -> LHS < RHS
303       Instructions.emplace_back(Mips::SLTu, ICMPReg, LHS, RHS);
304       break;
305     case CmpInst::ICMP_ULE: // LHS <= RHS -> !(RHS < LHS)
306       Instructions.emplace_back(Mips::SLTu, Temp, RHS, LHS);
307       Instructions.emplace_back(Mips::XORi, ICMPReg, Temp, 1);
308       break;
309     case CmpInst::ICMP_SGT: // LHS >  RHS -> RHS < LHS
310       Instructions.emplace_back(Mips::SLT, ICMPReg, RHS, LHS);
311       break;
312     case CmpInst::ICMP_SGE: // LHS >= RHS -> !(LHS < RHS)
313       Instructions.emplace_back(Mips::SLT, Temp, LHS, RHS);
314       Instructions.emplace_back(Mips::XORi, ICMPReg, Temp, 1);
315       break;
316     case CmpInst::ICMP_SLT: // LHS <  RHS -> LHS < RHS
317       Instructions.emplace_back(Mips::SLT, ICMPReg, LHS, RHS);
318       break;
319     case CmpInst::ICMP_SLE: // LHS <= RHS -> !(RHS < LHS)
320       Instructions.emplace_back(Mips::SLT, Temp, RHS, LHS);
321       Instructions.emplace_back(Mips::XORi, ICMPReg, Temp, 1);
322       break;
323     default:
324       return false;
325     }
326 
327     MachineIRBuilder B(I);
328     for (const struct Instr &Instruction : Instructions) {
329       MachineInstrBuilder MIB = B.buildInstr(
330           Instruction.Opcode, {Instruction.Def}, {Instruction.LHS});
331 
332       if (Instruction.hasImm())
333         MIB.addImm(Instruction.RHS);
334       else
335         MIB.addUse(Instruction.RHS);
336 
337       if (!MIB.constrainAllUses(TII, TRI, RBI))
338         return false;
339     }
340 
341     I.eraseFromParent();
342     return true;
343   }
344   default:
345     return false;
346   }
347 
348   I.eraseFromParent();
349   return constrainSelectedInstRegOperands(*MI, TII, TRI, RBI);
350 }
351 
352 namespace llvm {
353 InstructionSelector *createMipsInstructionSelector(const MipsTargetMachine &TM,
354                                                    MipsSubtarget &Subtarget,
355                                                    MipsRegisterBankInfo &RBI) {
356   return new MipsInstructionSelector(TM, Subtarget, RBI);
357 }
358 } // end namespace llvm
359