1 //===-- MipsInstrInfo.h - Mips Instruction Information ----------*- C++ -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file contains the Mips implementation of the TargetInstrInfo class. 11 // 12 // FIXME: We need to override TargetInstrInfo::getInlineAsmLength method in 13 // order for MipsLongBranch pass to work correctly when the code has inline 14 // assembly. The returned value doesn't have to be the asm instruction's exact 15 // size in bytes; MipsLongBranch only expects it to be the correct upper bound. 16 //===----------------------------------------------------------------------===// 17 18 #ifndef LLVM_LIB_TARGET_MIPS_MIPSINSTRINFO_H 19 #define LLVM_LIB_TARGET_MIPS_MIPSINSTRINFO_H 20 21 #include "Mips.h" 22 #include "MipsRegisterInfo.h" 23 #include "llvm/CodeGen/MachineInstrBuilder.h" 24 #include "llvm/Support/ErrorHandling.h" 25 #include "llvm/Target/TargetInstrInfo.h" 26 27 #define GET_INSTRINFO_HEADER 28 #include "MipsGenInstrInfo.inc" 29 30 namespace llvm { 31 class MipsSubtarget; 32 class MipsInstrInfo : public MipsGenInstrInfo { 33 virtual void anchor(); 34 protected: 35 const MipsSubtarget &Subtarget; 36 unsigned UncondBrOpc; 37 38 public: 39 enum BranchType { 40 BT_None, // Couldn't analyze branch. 41 BT_NoBranch, // No branches found. 42 BT_Uncond, // One unconditional branch. 43 BT_Cond, // One conditional branch. 44 BT_CondUncond, // A conditional branch followed by an unconditional branch. 45 BT_Indirect // One indirct branch. 46 }; 47 48 explicit MipsInstrInfo(const MipsSubtarget &STI, unsigned UncondBrOpc); 49 50 static const MipsInstrInfo *create(MipsSubtarget &STI); 51 52 /// Branch Analysis 53 bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, 54 MachineBasicBlock *&FBB, 55 SmallVectorImpl<MachineOperand> &Cond, 56 bool AllowModify) const override; 57 58 unsigned RemoveBranch(MachineBasicBlock &MBB) const override; 59 60 unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, 61 MachineBasicBlock *FBB, ArrayRef<MachineOperand> Cond, 62 DebugLoc DL) const override; 63 64 bool 65 ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const override; 66 67 BranchType AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, 68 MachineBasicBlock *&FBB, 69 SmallVectorImpl<MachineOperand> &Cond, 70 bool AllowModify, 71 SmallVectorImpl<MachineInstr*> &BranchInstrs) const; 72 73 /// Insert nop instruction when hazard condition is found 74 void insertNoop(MachineBasicBlock &MBB, 75 MachineBasicBlock::iterator MI) const override; 76 77 /// getRegisterInfo - TargetInstrInfo is a superset of MRegister info. As 78 /// such, whenever a client has an instance of instruction info, it should 79 /// always be able to get register info as well (through this method). 80 /// 81 virtual const MipsRegisterInfo &getRegisterInfo() const = 0; 82 83 virtual unsigned getOppositeBranchOpc(unsigned Opc) const = 0; 84 85 /// Return the number of bytes of code the specified instruction may be. 86 unsigned GetInstSizeInBytes(const MachineInstr *MI) const; 87 88 void storeRegToStackSlot(MachineBasicBlock &MBB, 89 MachineBasicBlock::iterator MBBI, 90 unsigned SrcReg, bool isKill, int FrameIndex, 91 const TargetRegisterClass *RC, 92 const TargetRegisterInfo *TRI) const override { 93 storeRegToStack(MBB, MBBI, SrcReg, isKill, FrameIndex, RC, TRI, 0); 94 } 95 96 void loadRegFromStackSlot(MachineBasicBlock &MBB, 97 MachineBasicBlock::iterator MBBI, 98 unsigned DestReg, int FrameIndex, 99 const TargetRegisterClass *RC, 100 const TargetRegisterInfo *TRI) const override { 101 loadRegFromStack(MBB, MBBI, DestReg, FrameIndex, RC, TRI, 0); 102 } 103 104 virtual void storeRegToStack(MachineBasicBlock &MBB, 105 MachineBasicBlock::iterator MI, 106 unsigned SrcReg, bool isKill, int FrameIndex, 107 const TargetRegisterClass *RC, 108 const TargetRegisterInfo *TRI, 109 int64_t Offset) const = 0; 110 111 virtual void loadRegFromStack(MachineBasicBlock &MBB, 112 MachineBasicBlock::iterator MI, 113 unsigned DestReg, int FrameIndex, 114 const TargetRegisterClass *RC, 115 const TargetRegisterInfo *TRI, 116 int64_t Offset) const = 0; 117 118 virtual void adjustStackPtr(unsigned SP, int64_t Amount, 119 MachineBasicBlock &MBB, 120 MachineBasicBlock::iterator I) const = 0; 121 122 /// Create an instruction which has the same operands and memory operands 123 /// as MI but has a new opcode. 124 MachineInstrBuilder genInstrWithNewOpc(unsigned NewOpc, 125 MachineBasicBlock::iterator I) const; 126 127 protected: 128 bool isZeroImm(const MachineOperand &op) const; 129 130 MachineMemOperand *GetMemOperand(MachineBasicBlock &MBB, int FI, 131 unsigned Flag) const; 132 133 private: 134 virtual unsigned getAnalyzableBrOpc(unsigned Opc) const = 0; 135 136 void AnalyzeCondBr(const MachineInstr *Inst, unsigned Opc, 137 MachineBasicBlock *&BB, 138 SmallVectorImpl<MachineOperand> &Cond) const; 139 140 void BuildCondBr(MachineBasicBlock &MBB, MachineBasicBlock *TBB, DebugLoc DL, 141 ArrayRef<MachineOperand> Cond) const; 142 }; 143 144 /// Create MipsInstrInfo objects. 145 const MipsInstrInfo *createMips16InstrInfo(const MipsSubtarget &STI); 146 const MipsInstrInfo *createMipsSEInstrInfo(const MipsSubtarget &STI); 147 148 } 149 150 #endif 151