1 //===- MipsInstrInfo.cpp - Mips Instruction Information -------------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file contains the Mips implementation of the TargetInstrInfo class.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #include "MipsInstrInfo.h"
14 #include "MCTargetDesc/MipsBaseInfo.h"
15 #include "MCTargetDesc/MipsMCTargetDesc.h"
16 #include "MipsSubtarget.h"
17 #include "llvm/ADT/SmallVector.h"
18 #include "llvm/CodeGen/MachineBasicBlock.h"
19 #include "llvm/CodeGen/MachineFrameInfo.h"
20 #include "llvm/CodeGen/MachineFunction.h"
21 #include "llvm/CodeGen/MachineInstr.h"
22 #include "llvm/CodeGen/MachineInstrBuilder.h"
23 #include "llvm/CodeGen/MachineOperand.h"
24 #include "llvm/CodeGen/TargetOpcodes.h"
25 #include "llvm/CodeGen/TargetSubtargetInfo.h"
26 #include "llvm/IR/DebugInfoMetadata.h"
27 #include "llvm/IR/DebugLoc.h"
28 #include "llvm/MC/MCInstrDesc.h"
29 #include "llvm/Target/TargetMachine.h"
30 #include <cassert>
31 
32 using namespace llvm;
33 
34 #define GET_INSTRINFO_CTOR_DTOR
35 #include "MipsGenInstrInfo.inc"
36 
37 // Pin the vtable to this file.
38 void MipsInstrInfo::anchor() {}
39 
40 MipsInstrInfo::MipsInstrInfo(const MipsSubtarget &STI, unsigned UncondBr)
41     : MipsGenInstrInfo(Mips::ADJCALLSTACKDOWN, Mips::ADJCALLSTACKUP),
42       Subtarget(STI), UncondBrOpc(UncondBr) {}
43 
44 const MipsInstrInfo *MipsInstrInfo::create(MipsSubtarget &STI) {
45   if (STI.inMips16Mode())
46     return createMips16InstrInfo(STI);
47 
48   return createMipsSEInstrInfo(STI);
49 }
50 
51 bool MipsInstrInfo::isZeroImm(const MachineOperand &op) const {
52   return op.isImm() && op.getImm() == 0;
53 }
54 
55 /// insertNoop - If data hazard condition is found insert the target nop
56 /// instruction.
57 void MipsInstrInfo::
58 insertNoop(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI) const
59 {
60   DebugLoc DL;
61   BuildMI(MBB, MI, DL, get(Mips::NOP));
62 }
63 
64 MachineMemOperand *
65 MipsInstrInfo::GetMemOperand(MachineBasicBlock &MBB, int FI,
66                              MachineMemOperand::Flags Flags) const {
67   MachineFunction &MF = *MBB.getParent();
68   MachineFrameInfo &MFI = MF.getFrameInfo();
69 
70   return MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(MF, FI),
71                                  Flags, MFI.getObjectSize(FI),
72                                  MFI.getObjectAlign(FI));
73 }
74 
75 //===----------------------------------------------------------------------===//
76 // Branch Analysis
77 //===----------------------------------------------------------------------===//
78 
79 void MipsInstrInfo::AnalyzeCondBr(const MachineInstr *Inst, unsigned Opc,
80                                   MachineBasicBlock *&BB,
81                                   SmallVectorImpl<MachineOperand> &Cond) const {
82   assert(getAnalyzableBrOpc(Opc) && "Not an analyzable branch");
83   int NumOp = Inst->getNumExplicitOperands();
84 
85   // for both int and fp branches, the last explicit operand is the
86   // MBB.
87   BB = Inst->getOperand(NumOp-1).getMBB();
88   Cond.push_back(MachineOperand::CreateImm(Opc));
89 
90   for (int i = 0; i < NumOp-1; i++)
91     Cond.push_back(Inst->getOperand(i));
92 }
93 
94 bool MipsInstrInfo::analyzeBranch(MachineBasicBlock &MBB,
95                                   MachineBasicBlock *&TBB,
96                                   MachineBasicBlock *&FBB,
97                                   SmallVectorImpl<MachineOperand> &Cond,
98                                   bool AllowModify) const {
99   SmallVector<MachineInstr*, 2> BranchInstrs;
100   BranchType BT = analyzeBranch(MBB, TBB, FBB, Cond, AllowModify, BranchInstrs);
101 
102   return (BT == BT_None) || (BT == BT_Indirect);
103 }
104 
105 void MipsInstrInfo::BuildCondBr(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
106                                 const DebugLoc &DL,
107                                 ArrayRef<MachineOperand> Cond) const {
108   unsigned Opc = Cond[0].getImm();
109   const MCInstrDesc &MCID = get(Opc);
110   MachineInstrBuilder MIB = BuildMI(&MBB, DL, MCID);
111 
112   for (unsigned i = 1; i < Cond.size(); ++i) {
113     assert((Cond[i].isImm() || Cond[i].isReg()) &&
114            "Cannot copy operand for conditional branch!");
115     MIB.add(Cond[i]);
116   }
117   MIB.addMBB(TBB);
118 }
119 
120 unsigned MipsInstrInfo::insertBranch(MachineBasicBlock &MBB,
121                                      MachineBasicBlock *TBB,
122                                      MachineBasicBlock *FBB,
123                                      ArrayRef<MachineOperand> Cond,
124                                      const DebugLoc &DL,
125                                      int *BytesAdded) const {
126   // Shouldn't be a fall through.
127   assert(TBB && "insertBranch must not be told to insert a fallthrough");
128   assert(!BytesAdded && "code size not handled");
129 
130   // # of condition operands:
131   //  Unconditional branches: 0
132   //  Floating point branches: 1 (opc)
133   //  Int BranchZero: 2 (opc, reg)
134   //  Int Branch: 3 (opc, reg0, reg1)
135   assert((Cond.size() <= 3) &&
136          "# of Mips branch conditions must be <= 3!");
137 
138   // Two-way Conditional branch.
139   if (FBB) {
140     BuildCondBr(MBB, TBB, DL, Cond);
141     BuildMI(&MBB, DL, get(UncondBrOpc)).addMBB(FBB);
142     return 2;
143   }
144 
145   // One way branch.
146   // Unconditional branch.
147   if (Cond.empty())
148     BuildMI(&MBB, DL, get(UncondBrOpc)).addMBB(TBB);
149   else // Conditional branch.
150     BuildCondBr(MBB, TBB, DL, Cond);
151   return 1;
152 }
153 
154 unsigned MipsInstrInfo::removeBranch(MachineBasicBlock &MBB,
155                                      int *BytesRemoved) const {
156   assert(!BytesRemoved && "code size not handled");
157 
158   MachineBasicBlock::reverse_iterator I = MBB.rbegin(), REnd = MBB.rend();
159   unsigned removed = 0;
160 
161   // Up to 2 branches are removed.
162   // Note that indirect branches are not removed.
163   while (I != REnd && removed < 2) {
164     // Skip past debug instructions.
165     if (I->isDebugInstr()) {
166       ++I;
167       continue;
168     }
169     if (!getAnalyzableBrOpc(I->getOpcode()))
170       break;
171     // Remove the branch.
172     I->eraseFromParent();
173     I = MBB.rbegin();
174     ++removed;
175   }
176 
177   return removed;
178 }
179 
180 /// reverseBranchCondition - Return the inverse opcode of the
181 /// specified Branch instruction.
182 bool MipsInstrInfo::reverseBranchCondition(
183     SmallVectorImpl<MachineOperand> &Cond) const {
184   assert( (Cond.size() && Cond.size() <= 3) &&
185           "Invalid Mips branch condition!");
186   Cond[0].setImm(getOppositeBranchOpc(Cond[0].getImm()));
187   return false;
188 }
189 
190 MipsInstrInfo::BranchType MipsInstrInfo::analyzeBranch(
191     MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB,
192     SmallVectorImpl<MachineOperand> &Cond, bool AllowModify,
193     SmallVectorImpl<MachineInstr *> &BranchInstrs) const {
194   MachineBasicBlock::reverse_iterator I = MBB.rbegin(), REnd = MBB.rend();
195 
196   // Skip all the debug instructions.
197   while (I != REnd && I->isDebugInstr())
198     ++I;
199 
200   if (I == REnd || !isUnpredicatedTerminator(*I)) {
201     // This block ends with no branches (it just falls through to its succ).
202     // Leave TBB/FBB null.
203     TBB = FBB = nullptr;
204     return BT_NoBranch;
205   }
206 
207   MachineInstr *LastInst = &*I;
208   unsigned LastOpc = LastInst->getOpcode();
209   BranchInstrs.push_back(LastInst);
210 
211   // Not an analyzable branch (e.g., indirect jump).
212   if (!getAnalyzableBrOpc(LastOpc))
213     return LastInst->isIndirectBranch() ? BT_Indirect : BT_None;
214 
215   // Get the second to last instruction in the block.
216   unsigned SecondLastOpc = 0;
217   MachineInstr *SecondLastInst = nullptr;
218 
219   // Skip past any debug instruction to see if the second last actual
220   // is a branch.
221   ++I;
222   while (I != REnd && I->isDebugInstr())
223     ++I;
224 
225   if (I != REnd) {
226     SecondLastInst = &*I;
227     SecondLastOpc = getAnalyzableBrOpc(SecondLastInst->getOpcode());
228 
229     // Not an analyzable branch (must be an indirect jump).
230     if (isUnpredicatedTerminator(*SecondLastInst) && !SecondLastOpc)
231       return BT_None;
232   }
233 
234   // If there is only one terminator instruction, process it.
235   if (!SecondLastOpc) {
236     // Unconditional branch.
237     if (LastInst->isUnconditionalBranch()) {
238       TBB = LastInst->getOperand(0).getMBB();
239       return BT_Uncond;
240     }
241 
242     // Conditional branch
243     AnalyzeCondBr(LastInst, LastOpc, TBB, Cond);
244     return BT_Cond;
245   }
246 
247   // If we reached here, there are two branches.
248   // If there are three terminators, we don't know what sort of block this is.
249   if (++I != REnd && isUnpredicatedTerminator(*I))
250     return BT_None;
251 
252   BranchInstrs.insert(BranchInstrs.begin(), SecondLastInst);
253 
254   // If second to last instruction is an unconditional branch,
255   // analyze it and remove the last instruction.
256   if (SecondLastInst->isUnconditionalBranch()) {
257     // Return if the last instruction cannot be removed.
258     if (!AllowModify)
259       return BT_None;
260 
261     TBB = SecondLastInst->getOperand(0).getMBB();
262     LastInst->eraseFromParent();
263     BranchInstrs.pop_back();
264     return BT_Uncond;
265   }
266 
267   // Conditional branch followed by an unconditional branch.
268   // The last one must be unconditional.
269   if (!LastInst->isUnconditionalBranch())
270     return BT_None;
271 
272   AnalyzeCondBr(SecondLastInst, SecondLastOpc, TBB, Cond);
273   FBB = LastInst->getOperand(0).getMBB();
274 
275   return BT_CondUncond;
276 }
277 
278 bool MipsInstrInfo::isBranchOffsetInRange(unsigned BranchOpc,
279                                           int64_t BrOffset) const {
280   switch (BranchOpc) {
281   case Mips::B:
282   case Mips::BAL:
283   case Mips::BAL_BR:
284   case Mips::BAL_BR_MM:
285   case Mips::BC1F:
286   case Mips::BC1FL:
287   case Mips::BC1T:
288   case Mips::BC1TL:
289   case Mips::BEQ:     case Mips::BEQ64:
290   case Mips::BEQL:
291   case Mips::BGEZ:    case Mips::BGEZ64:
292   case Mips::BGEZL:
293   case Mips::BGEZAL:
294   case Mips::BGEZALL:
295   case Mips::BGTZ:    case Mips::BGTZ64:
296   case Mips::BGTZL:
297   case Mips::BLEZ:    case Mips::BLEZ64:
298   case Mips::BLEZL:
299   case Mips::BLTZ:    case Mips::BLTZ64:
300   case Mips::BLTZL:
301   case Mips::BLTZAL:
302   case Mips::BLTZALL:
303   case Mips::BNE:     case Mips::BNE64:
304   case Mips::BNEL:
305     return isInt<18>(BrOffset);
306 
307   // microMIPSr3 branches
308   case Mips::B_MM:
309   case Mips::BC1F_MM:
310   case Mips::BC1T_MM:
311   case Mips::BEQ_MM:
312   case Mips::BGEZ_MM:
313   case Mips::BGEZAL_MM:
314   case Mips::BGTZ_MM:
315   case Mips::BLEZ_MM:
316   case Mips::BLTZ_MM:
317   case Mips::BLTZAL_MM:
318   case Mips::BNE_MM:
319   case Mips::BEQZC_MM:
320   case Mips::BNEZC_MM:
321     return isInt<17>(BrOffset);
322 
323   // microMIPSR3 short branches.
324   case Mips::B16_MM:
325     return isInt<11>(BrOffset);
326 
327   case Mips::BEQZ16_MM:
328   case Mips::BNEZ16_MM:
329     return isInt<8>(BrOffset);
330 
331   // MIPSR6 branches.
332   case Mips::BALC:
333   case Mips::BC:
334     return isInt<28>(BrOffset);
335 
336   case Mips::BC1EQZ:
337   case Mips::BC1NEZ:
338   case Mips::BC2EQZ:
339   case Mips::BC2NEZ:
340   case Mips::BEQC:   case Mips::BEQC64:
341   case Mips::BNEC:   case Mips::BNEC64:
342   case Mips::BGEC:   case Mips::BGEC64:
343   case Mips::BGEUC:  case Mips::BGEUC64:
344   case Mips::BGEZC:  case Mips::BGEZC64:
345   case Mips::BGTZC:  case Mips::BGTZC64:
346   case Mips::BLEZC:  case Mips::BLEZC64:
347   case Mips::BLTC:   case Mips::BLTC64:
348   case Mips::BLTUC:  case Mips::BLTUC64:
349   case Mips::BLTZC:  case Mips::BLTZC64:
350   case Mips::BNVC:
351   case Mips::BOVC:
352   case Mips::BGEZALC:
353   case Mips::BEQZALC:
354   case Mips::BGTZALC:
355   case Mips::BLEZALC:
356   case Mips::BLTZALC:
357   case Mips::BNEZALC:
358     return isInt<18>(BrOffset);
359 
360   case Mips::BEQZC:  case Mips::BEQZC64:
361   case Mips::BNEZC:  case Mips::BNEZC64:
362     return isInt<23>(BrOffset);
363 
364   // microMIPSR6 branches
365   case Mips::BC16_MMR6:
366     return isInt<11>(BrOffset);
367 
368   case Mips::BEQZC16_MMR6:
369   case Mips::BNEZC16_MMR6:
370     return isInt<8>(BrOffset);
371 
372   case Mips::BALC_MMR6:
373   case Mips::BC_MMR6:
374     return isInt<27>(BrOffset);
375 
376   case Mips::BC1EQZC_MMR6:
377   case Mips::BC1NEZC_MMR6:
378   case Mips::BC2EQZC_MMR6:
379   case Mips::BC2NEZC_MMR6:
380   case Mips::BGEZALC_MMR6:
381   case Mips::BEQZALC_MMR6:
382   case Mips::BGTZALC_MMR6:
383   case Mips::BLEZALC_MMR6:
384   case Mips::BLTZALC_MMR6:
385   case Mips::BNEZALC_MMR6:
386   case Mips::BNVC_MMR6:
387   case Mips::BOVC_MMR6:
388     return isInt<17>(BrOffset);
389 
390   case Mips::BEQC_MMR6:
391   case Mips::BNEC_MMR6:
392   case Mips::BGEC_MMR6:
393   case Mips::BGEUC_MMR6:
394   case Mips::BGEZC_MMR6:
395   case Mips::BGTZC_MMR6:
396   case Mips::BLEZC_MMR6:
397   case Mips::BLTC_MMR6:
398   case Mips::BLTUC_MMR6:
399   case Mips::BLTZC_MMR6:
400     return isInt<18>(BrOffset);
401 
402   case Mips::BEQZC_MMR6:
403   case Mips::BNEZC_MMR6:
404     return isInt<23>(BrOffset);
405 
406   // DSP branches.
407   case Mips::BPOSGE32:
408     return isInt<18>(BrOffset);
409   case Mips::BPOSGE32_MM:
410   case Mips::BPOSGE32C_MMR3:
411     return isInt<17>(BrOffset);
412 
413   // cnMIPS branches.
414   case Mips::BBIT0:
415   case Mips::BBIT032:
416   case Mips::BBIT1:
417   case Mips::BBIT132:
418     return isInt<18>(BrOffset);
419 
420   // MSA branches.
421   case Mips::BZ_B:
422   case Mips::BZ_H:
423   case Mips::BZ_W:
424   case Mips::BZ_D:
425   case Mips::BZ_V:
426   case Mips::BNZ_B:
427   case Mips::BNZ_H:
428   case Mips::BNZ_W:
429   case Mips::BNZ_D:
430   case Mips::BNZ_V:
431     return isInt<18>(BrOffset);
432   }
433 
434   llvm_unreachable("Unknown branch instruction!");
435 }
436 
437 /// Return the corresponding compact (no delay slot) form of a branch.
438 unsigned MipsInstrInfo::getEquivalentCompactForm(
439     const MachineBasicBlock::iterator I) const {
440   unsigned Opcode = I->getOpcode();
441   bool canUseShortMicroMipsCTI = false;
442 
443   if (Subtarget.inMicroMipsMode()) {
444     switch (Opcode) {
445     case Mips::BNE:
446     case Mips::BNE_MM:
447     case Mips::BEQ:
448     case Mips::BEQ_MM:
449     // microMIPS has NE,EQ branches that do not have delay slots provided one
450     // of the operands is zero.
451       if (I->getOperand(1).getReg() == Subtarget.getABI().GetZeroReg())
452         canUseShortMicroMipsCTI = true;
453       break;
454     // For microMIPS the PseudoReturn and PseudoIndirectBranch are always
455     // expanded to JR_MM, so they can be replaced with JRC16_MM.
456     case Mips::JR:
457     case Mips::PseudoReturn:
458     case Mips::PseudoIndirectBranch:
459       canUseShortMicroMipsCTI = true;
460       break;
461     }
462   }
463 
464   // MIPSR6 forbids both operands being the zero register.
465   if (Subtarget.hasMips32r6() && (I->getNumOperands() > 1) &&
466       (I->getOperand(0).isReg() &&
467        (I->getOperand(0).getReg() == Mips::ZERO ||
468         I->getOperand(0).getReg() == Mips::ZERO_64)) &&
469       (I->getOperand(1).isReg() &&
470        (I->getOperand(1).getReg() == Mips::ZERO ||
471         I->getOperand(1).getReg() == Mips::ZERO_64)))
472     return 0;
473 
474   if (Subtarget.hasMips32r6() || canUseShortMicroMipsCTI) {
475     switch (Opcode) {
476     case Mips::B:
477       return Mips::BC;
478     case Mips::BAL:
479       return Mips::BALC;
480     case Mips::BEQ:
481     case Mips::BEQ_MM:
482       if (canUseShortMicroMipsCTI)
483         return Mips::BEQZC_MM;
484       else if (I->getOperand(0).getReg() == I->getOperand(1).getReg())
485         return 0;
486       return Mips::BEQC;
487     case Mips::BNE:
488     case Mips::BNE_MM:
489       if (canUseShortMicroMipsCTI)
490         return Mips::BNEZC_MM;
491       else if (I->getOperand(0).getReg() == I->getOperand(1).getReg())
492         return 0;
493       return Mips::BNEC;
494     case Mips::BGE:
495       if (I->getOperand(0).getReg() == I->getOperand(1).getReg())
496         return 0;
497       return Mips::BGEC;
498     case Mips::BGEU:
499       if (I->getOperand(0).getReg() == I->getOperand(1).getReg())
500         return 0;
501       return Mips::BGEUC;
502     case Mips::BGEZ:
503       return Mips::BGEZC;
504     case Mips::BGTZ:
505       return Mips::BGTZC;
506     case Mips::BLEZ:
507       return Mips::BLEZC;
508     case Mips::BLT:
509       if (I->getOperand(0).getReg() == I->getOperand(1).getReg())
510         return 0;
511       return Mips::BLTC;
512     case Mips::BLTU:
513       if (I->getOperand(0).getReg() == I->getOperand(1).getReg())
514         return 0;
515       return Mips::BLTUC;
516     case Mips::BLTZ:
517       return Mips::BLTZC;
518     case Mips::BEQ64:
519       if (I->getOperand(0).getReg() == I->getOperand(1).getReg())
520         return 0;
521       return Mips::BEQC64;
522     case Mips::BNE64:
523       if (I->getOperand(0).getReg() == I->getOperand(1).getReg())
524         return 0;
525       return Mips::BNEC64;
526     case Mips::BGTZ64:
527       return Mips::BGTZC64;
528     case Mips::BGEZ64:
529       return Mips::BGEZC64;
530     case Mips::BLTZ64:
531       return Mips::BLTZC64;
532     case Mips::BLEZ64:
533       return Mips::BLEZC64;
534     // For MIPSR6, the instruction 'jic' can be used for these cases. Some
535     // tools will accept 'jrc reg' as an alias for 'jic 0, $reg'.
536     case Mips::JR:
537     case Mips::PseudoIndirectBranchR6:
538     case Mips::PseudoReturn:
539     case Mips::TAILCALLR6REG:
540       if (canUseShortMicroMipsCTI)
541         return Mips::JRC16_MM;
542       return Mips::JIC;
543     case Mips::JALRPseudo:
544       return Mips::JIALC;
545     case Mips::JR64:
546     case Mips::PseudoIndirectBranch64R6:
547     case Mips::PseudoReturn64:
548     case Mips::TAILCALL64R6REG:
549       return Mips::JIC64;
550     case Mips::JALR64Pseudo:
551       return Mips::JIALC64;
552     default:
553       return 0;
554     }
555   }
556 
557   return 0;
558 }
559 
560 /// Predicate for distingushing between control transfer instructions and all
561 /// other instructions for handling forbidden slots. Consider inline assembly
562 /// as unsafe as well.
563 bool MipsInstrInfo::SafeInForbiddenSlot(const MachineInstr &MI) const {
564   if (MI.isInlineAsm())
565     return false;
566 
567   return (MI.getDesc().TSFlags & MipsII::IsCTI) == 0;
568 }
569 
570 bool MipsInstrInfo::SafeInFPUDelaySlot(const MachineInstr &MIInSlot,
571                                        const MachineInstr &FPUMI) const {
572   if (MIInSlot.isInlineAsm())
573     return false;
574 
575   if (HasFPUDelaySlot(MIInSlot))
576     return false;
577 
578   switch (MIInSlot.getOpcode()) {
579   case Mips::BC1F:
580   case Mips::BC1FL:
581   case Mips::BC1T:
582   case Mips::BC1TL:
583     return false;
584   }
585 
586   for (const MachineOperand &Op : FPUMI.defs()) {
587     if (!Op.isReg())
588       continue;
589 
590     bool Reads, Writes;
591     std::tie(Reads, Writes) = MIInSlot.readsWritesVirtualRegister(Op.getReg());
592 
593     if (Reads || Writes)
594       return false;
595   }
596 
597   return true;
598 }
599 
600 /// Predicate for distinguishing instructions that are hazardous in a load delay
601 /// slot. Consider inline assembly as unsafe as well.
602 bool MipsInstrInfo::SafeInLoadDelaySlot(const MachineInstr &MIInSlot,
603                                         const MachineInstr &LoadMI) const {
604   if (MIInSlot.isInlineAsm())
605     return false;
606 
607   return !llvm::any_of(LoadMI.defs(), [&](const MachineOperand &Op) {
608     return Op.isReg() && MIInSlot.readsRegister(Op.getReg());
609   });
610 }
611 
612 /// Predicate for distingushing instructions that have forbidden slots.
613 bool MipsInstrInfo::HasForbiddenSlot(const MachineInstr &MI) const {
614   return (MI.getDesc().TSFlags & MipsII::HasForbiddenSlot) != 0;
615 }
616 
617 /// Predicate for distingushing instructions that have FPU delay slots.
618 bool MipsInstrInfo::HasFPUDelaySlot(const MachineInstr &MI) const {
619   switch (MI.getOpcode()) {
620   case Mips::MTC1:
621   case Mips::MFC1:
622   case Mips::MTC1_D64:
623   case Mips::MFC1_D64:
624   case Mips::DMTC1:
625   case Mips::DMFC1:
626   case Mips::FCMP_S32:
627   case Mips::FCMP_D32:
628   case Mips::FCMP_D64:
629     return true;
630 
631   default:
632     return false;
633   }
634 }
635 
636 /// Predicate for distingushing instructions that have load delay slots.
637 bool MipsInstrInfo::HasLoadDelaySlot(const MachineInstr &MI) const {
638   switch (MI.getOpcode()) {
639   case Mips::LB:
640   case Mips::LBu:
641   case Mips::LH:
642   case Mips::LHu:
643   case Mips::LW:
644   case Mips::LWR:
645   case Mips::LWL:
646     return true;
647   default:
648     return false;
649   }
650 }
651 
652 /// Return the number of bytes of code the specified instruction may be.
653 unsigned MipsInstrInfo::getInstSizeInBytes(const MachineInstr &MI) const {
654   switch (MI.getOpcode()) {
655   default:
656     return MI.getDesc().getSize();
657   case  TargetOpcode::INLINEASM:
658   case  TargetOpcode::INLINEASM_BR: {       // Inline Asm: Variable size.
659     const MachineFunction *MF = MI.getParent()->getParent();
660     const char *AsmStr = MI.getOperand(0).getSymbolName();
661     return getInlineAsmLength(AsmStr, *MF->getTarget().getMCAsmInfo());
662   }
663   case Mips::CONSTPOOL_ENTRY:
664     // If this machine instr is a constant pool entry, its size is recorded as
665     // operand #2.
666     return MI.getOperand(2).getImm();
667   }
668 }
669 
670 MachineInstrBuilder
671 MipsInstrInfo::genInstrWithNewOpc(unsigned NewOpc,
672                                   MachineBasicBlock::iterator I) const {
673   MachineInstrBuilder MIB;
674 
675   // Certain branches have two forms: e.g beq $1, $zero, dest vs beqz $1, dest
676   // Pick the zero form of the branch for readable assembly and for greater
677   // branch distance in non-microMIPS mode.
678   // Additional MIPSR6 does not permit the use of register $zero for compact
679   // branches.
680   // FIXME: Certain atomic sequences on mips64 generate 32bit references to
681   // Mips::ZERO, which is incorrect. This test should be updated to use
682   // Subtarget.getABI().GetZeroReg() when those atomic sequences and others
683   // are fixed.
684   int ZeroOperandPosition = -1;
685   bool BranchWithZeroOperand = false;
686   if (I->isBranch() && !I->isPseudo()) {
687     auto TRI = I->getParent()->getParent()->getSubtarget().getRegisterInfo();
688     ZeroOperandPosition = I->findRegisterUseOperandIdx(Mips::ZERO, false, TRI);
689     BranchWithZeroOperand = ZeroOperandPosition != -1;
690   }
691 
692   if (BranchWithZeroOperand) {
693     switch (NewOpc) {
694     case Mips::BEQC:
695       NewOpc = Mips::BEQZC;
696       break;
697     case Mips::BNEC:
698       NewOpc = Mips::BNEZC;
699       break;
700     case Mips::BGEC:
701       NewOpc = Mips::BGEZC;
702       break;
703     case Mips::BLTC:
704       NewOpc = Mips::BLTZC;
705       break;
706     case Mips::BEQC64:
707       NewOpc = Mips::BEQZC64;
708       break;
709     case Mips::BNEC64:
710       NewOpc = Mips::BNEZC64;
711       break;
712     }
713   }
714 
715   MIB = BuildMI(*I->getParent(), I, I->getDebugLoc(), get(NewOpc));
716 
717   // For MIPSR6 JI*C requires an immediate 0 as an operand, JIALC(64) an
718   // immediate 0 as an operand and requires the removal of it's implicit-def %ra
719   // implicit operand as copying the implicit operations of the instructio we're
720   // looking at will give us the correct flags.
721   if (NewOpc == Mips::JIC || NewOpc == Mips::JIALC || NewOpc == Mips::JIC64 ||
722       NewOpc == Mips::JIALC64) {
723 
724     if (NewOpc == Mips::JIALC || NewOpc == Mips::JIALC64)
725       MIB->removeOperand(0);
726 
727     for (unsigned J = 0, E = I->getDesc().getNumOperands(); J < E; ++J) {
728       MIB.add(I->getOperand(J));
729     }
730 
731     MIB.addImm(0);
732 
733     // If I has an MCSymbol operand (used by asm printer, to emit R_MIPS_JALR),
734     // add it to the new instruction.
735     for (unsigned J = I->getDesc().getNumOperands(), E = I->getNumOperands();
736          J < E; ++J) {
737       const MachineOperand &MO = I->getOperand(J);
738       if (MO.isMCSymbol() && (MO.getTargetFlags() & MipsII::MO_JALR))
739         MIB.addSym(MO.getMCSymbol(), MipsII::MO_JALR);
740     }
741 
742 
743   } else {
744     for (unsigned J = 0, E = I->getDesc().getNumOperands(); J < E; ++J) {
745       if (BranchWithZeroOperand && (unsigned)ZeroOperandPosition == J)
746         continue;
747 
748       MIB.add(I->getOperand(J));
749     }
750   }
751 
752   MIB.copyImplicitOps(*I);
753   MIB.cloneMemRefs(*I);
754   return MIB;
755 }
756 
757 bool MipsInstrInfo::findCommutedOpIndices(const MachineInstr &MI,
758                                           unsigned &SrcOpIdx1,
759                                           unsigned &SrcOpIdx2) const {
760   assert(!MI.isBundle() &&
761          "TargetInstrInfo::findCommutedOpIndices() can't handle bundles");
762 
763   const MCInstrDesc &MCID = MI.getDesc();
764   if (!MCID.isCommutable())
765     return false;
766 
767   switch (MI.getOpcode()) {
768   case Mips::DPADD_U_H:
769   case Mips::DPADD_U_W:
770   case Mips::DPADD_U_D:
771   case Mips::DPADD_S_H:
772   case Mips::DPADD_S_W:
773   case Mips::DPADD_S_D:
774     // The first operand is both input and output, so it should not commute
775     if (!fixCommutedOpIndices(SrcOpIdx1, SrcOpIdx2, 2, 3))
776       return false;
777 
778     if (!MI.getOperand(SrcOpIdx1).isReg() || !MI.getOperand(SrcOpIdx2).isReg())
779       return false;
780     return true;
781   }
782   return TargetInstrInfo::findCommutedOpIndices(MI, SrcOpIdx1, SrcOpIdx2);
783 }
784 
785 // ins, ext, dext*, dins have the following constraints:
786 // X <= pos      <  Y
787 // X <  size     <= Y
788 // X <  pos+size <= Y
789 //
790 // dinsm and dinsu have the following constraints:
791 // X <= pos      <  Y
792 // X <= size     <= Y
793 // X <  pos+size <= Y
794 //
795 // The callee of verifyInsExtInstruction however gives the bounds of
796 // dins[um] like the other (d)ins (d)ext(um) instructions, so that this
797 // function doesn't have to vary it's behaviour based on the instruction
798 // being checked.
799 static bool verifyInsExtInstruction(const MachineInstr &MI, StringRef &ErrInfo,
800                                     const int64_t PosLow, const int64_t PosHigh,
801                                     const int64_t SizeLow,
802                                     const int64_t SizeHigh,
803                                     const int64_t BothLow,
804                                     const int64_t BothHigh) {
805   MachineOperand MOPos = MI.getOperand(2);
806   if (!MOPos.isImm()) {
807     ErrInfo = "Position is not an immediate!";
808     return false;
809   }
810   int64_t Pos = MOPos.getImm();
811   if (!((PosLow <= Pos) && (Pos < PosHigh))) {
812     ErrInfo = "Position operand is out of range!";
813     return false;
814   }
815 
816   MachineOperand MOSize = MI.getOperand(3);
817   if (!MOSize.isImm()) {
818     ErrInfo = "Size operand is not an immediate!";
819     return false;
820   }
821   int64_t Size = MOSize.getImm();
822   if (!((SizeLow < Size) && (Size <= SizeHigh))) {
823     ErrInfo = "Size operand is out of range!";
824     return false;
825   }
826 
827   if (!((BothLow < (Pos + Size)) && ((Pos + Size) <= BothHigh))) {
828     ErrInfo = "Position + Size is out of range!";
829     return false;
830   }
831 
832   return true;
833 }
834 
835 //  Perform target specific instruction verification.
836 bool MipsInstrInfo::verifyInstruction(const MachineInstr &MI,
837                                       StringRef &ErrInfo) const {
838   // Verify that ins and ext instructions are well formed.
839   switch (MI.getOpcode()) {
840     case Mips::EXT:
841     case Mips::EXT_MM:
842     case Mips::INS:
843     case Mips::INS_MM:
844     case Mips::DINS:
845       return verifyInsExtInstruction(MI, ErrInfo, 0, 32, 0, 32, 0, 32);
846     case Mips::DINSM:
847       // The ISA spec has a subtle difference between dinsm and dextm
848       // in that it says:
849       // 2 <= size <= 64 for 'dinsm' but 'dextm' has 32 < size <= 64.
850       // To make the bounds checks similar, the range 1 < size <= 64 is checked
851       // for 'dinsm'.
852       return verifyInsExtInstruction(MI, ErrInfo, 0, 32, 1, 64, 32, 64);
853     case Mips::DINSU:
854       // The ISA spec has a subtle difference between dinsu and dextu in that
855       // the size range of dinsu is specified as 1 <= size <= 32 whereas size
856       // for dextu is 0 < size <= 32. The range checked for dinsu here is
857       // 0 < size <= 32, which is equivalent and similar to dextu.
858       return verifyInsExtInstruction(MI, ErrInfo, 32, 64, 0, 32, 32, 64);
859     case Mips::DEXT:
860       return verifyInsExtInstruction(MI, ErrInfo, 0, 32, 0, 32, 0, 63);
861     case Mips::DEXTM:
862       return verifyInsExtInstruction(MI, ErrInfo, 0, 32, 32, 64, 32, 64);
863     case Mips::DEXTU:
864       return verifyInsExtInstruction(MI, ErrInfo, 32, 64, 0, 32, 32, 64);
865     case Mips::TAILCALLREG:
866     case Mips::PseudoIndirectBranch:
867     case Mips::JR:
868     case Mips::JR64:
869     case Mips::JALR:
870     case Mips::JALR64:
871     case Mips::JALRPseudo:
872       if (!Subtarget.useIndirectJumpsHazard())
873         return true;
874 
875       ErrInfo = "invalid instruction when using jump guards!";
876       return false;
877     default:
878       return true;
879   }
880 
881   return true;
882 }
883 
884 std::pair<unsigned, unsigned>
885 MipsInstrInfo::decomposeMachineOperandsTargetFlags(unsigned TF) const {
886   return std::make_pair(TF, 0u);
887 }
888 
889 ArrayRef<std::pair<unsigned, const char*>>
890 MipsInstrInfo::getSerializableDirectMachineOperandTargetFlags() const {
891  using namespace MipsII;
892 
893  static const std::pair<unsigned, const char*> Flags[] = {
894     {MO_GOT,          "mips-got"},
895     {MO_GOT_CALL,     "mips-got-call"},
896     {MO_GPREL,        "mips-gprel"},
897     {MO_ABS_HI,       "mips-abs-hi"},
898     {MO_ABS_LO,       "mips-abs-lo"},
899     {MO_TLSGD,        "mips-tlsgd"},
900     {MO_TLSLDM,       "mips-tlsldm"},
901     {MO_DTPREL_HI,    "mips-dtprel-hi"},
902     {MO_DTPREL_LO,    "mips-dtprel-lo"},
903     {MO_GOTTPREL,     "mips-gottprel"},
904     {MO_TPREL_HI,     "mips-tprel-hi"},
905     {MO_TPREL_LO,     "mips-tprel-lo"},
906     {MO_GPOFF_HI,     "mips-gpoff-hi"},
907     {MO_GPOFF_LO,     "mips-gpoff-lo"},
908     {MO_GOT_DISP,     "mips-got-disp"},
909     {MO_GOT_PAGE,     "mips-got-page"},
910     {MO_GOT_OFST,     "mips-got-ofst"},
911     {MO_HIGHER,       "mips-higher"},
912     {MO_HIGHEST,      "mips-highest"},
913     {MO_GOT_HI16,     "mips-got-hi16"},
914     {MO_GOT_LO16,     "mips-got-lo16"},
915     {MO_CALL_HI16,    "mips-call-hi16"},
916     {MO_CALL_LO16,    "mips-call-lo16"},
917     {MO_JALR,         "mips-jalr"}
918   };
919   return makeArrayRef(Flags);
920 }
921 
922 Optional<ParamLoadedValue>
923 MipsInstrInfo::describeLoadedValue(const MachineInstr &MI, Register Reg) const {
924   DIExpression *Expr =
925       DIExpression::get(MI.getMF()->getFunction().getContext(), {});
926 
927   // TODO: Special MIPS instructions that need to be described separately.
928   if (auto RegImm = isAddImmediate(MI, Reg)) {
929     Register SrcReg = RegImm->Reg;
930     int64_t Offset = RegImm->Imm;
931     // When SrcReg is $zero, treat loaded value as immediate only.
932     // Ex. $a2 = ADDiu $zero, 10
933     if (SrcReg == Mips::ZERO || SrcReg == Mips::ZERO_64) {
934       return ParamLoadedValue(MI.getOperand(2), Expr);
935     }
936     Expr = DIExpression::prepend(Expr, DIExpression::ApplyOffset, Offset);
937     return ParamLoadedValue(MachineOperand::CreateReg(SrcReg, false), Expr);
938   } else if (auto DestSrc = isCopyInstr(MI)) {
939     const MachineFunction *MF = MI.getMF();
940     const TargetRegisterInfo *TRI = MF->getSubtarget().getRegisterInfo();
941     Register DestReg = DestSrc->Destination->getReg();
942     // TODO: Handle cases where the Reg is sub- or super-register of the
943     // DestReg.
944     if (TRI->isSuperRegister(Reg, DestReg) || TRI->isSubRegister(Reg, DestReg))
945       return None;
946   }
947 
948   return TargetInstrInfo::describeLoadedValue(MI, Reg);
949 }
950 
951 Optional<RegImmPair> MipsInstrInfo::isAddImmediate(const MachineInstr &MI,
952                                                    Register Reg) const {
953   // TODO: Handle cases where Reg is a super- or sub-register of the
954   // destination register.
955   const MachineOperand &Op0 = MI.getOperand(0);
956   if (!Op0.isReg() || Reg != Op0.getReg())
957     return None;
958 
959   switch (MI.getOpcode()) {
960   case Mips::ADDiu:
961   case Mips::DADDiu: {
962     const MachineOperand &Dop = MI.getOperand(0);
963     const MachineOperand &Sop1 = MI.getOperand(1);
964     const MachineOperand &Sop2 = MI.getOperand(2);
965     // Value is sum of register and immediate. Immediate value could be
966     // global string address which is not supported.
967     if (Dop.isReg() && Sop1.isReg() && Sop2.isImm())
968       return RegImmPair{Sop1.getReg(), Sop2.getImm()};
969     // TODO: Handle case where Sop1 is a frame-index.
970   }
971   }
972   return None;
973 }
974