1 //===-- MipsInstrInfo.cpp - Mips Instruction Information ------------------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file contains the Mips implementation of the TargetInstrInfo class.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #include "MipsInstrInfo.h"
15 #include "MipsTargetMachine.h"
16 #include "MipsMachineFunction.h"
17 #include "InstPrinter/MipsInstPrinter.h"
18 #include "llvm/CodeGen/MachineInstrBuilder.h"
19 #include "llvm/CodeGen/MachineRegisterInfo.h"
20 #include "llvm/Support/ErrorHandling.h"
21 #include "llvm/Support/TargetRegistry.h"
22 #include "llvm/ADT/STLExtras.h"
23 
24 #define GET_INSTRINFO_CTOR
25 #include "MipsGenInstrInfo.inc"
26 
27 using namespace llvm;
28 
29 MipsInstrInfo::MipsInstrInfo(MipsTargetMachine &tm)
30   : MipsGenInstrInfo(Mips::ADJCALLSTACKDOWN, Mips::ADJCALLSTACKUP),
31     TM(tm), IsN64(TM.getSubtarget<MipsSubtarget>().isABI_N64()),
32     RI(*TM.getSubtargetImpl(), *this),
33     UncondBrOpc(TM.getRelocationModel() == Reloc::PIC_ ? Mips::B : Mips::J) {}
34 
35 const MipsRegisterInfo &MipsInstrInfo::getRegisterInfo() const {
36   return RI;
37 }
38 
39 static bool isZeroImm(const MachineOperand &op) {
40   return op.isImm() && op.getImm() == 0;
41 }
42 
43 /// isLoadFromStackSlot - If the specified machine instruction is a direct
44 /// load from a stack slot, return the virtual or physical register number of
45 /// the destination along with the FrameIndex of the loaded stack slot.  If
46 /// not, return 0.  This predicate must return 0 if the instruction has
47 /// any side effects other than loading from the stack slot.
48 unsigned MipsInstrInfo::
49 isLoadFromStackSlot(const MachineInstr *MI, int &FrameIndex) const
50 {
51   unsigned Opc = MI->getOpcode();
52 
53   if ((Opc == Mips::LW)    || (Opc == Mips::LW_P8)  || (Opc == Mips::LD) ||
54       (Opc == Mips::LD_P8) || (Opc == Mips::LWC1)   || (Opc == Mips::LWC1_P8) ||
55       (Opc == Mips::LDC1)  || (Opc == Mips::LDC164) ||
56       (Opc == Mips::LDC164_P8)) {
57     if ((MI->getOperand(1).isFI()) && // is a stack slot
58         (MI->getOperand(2).isImm()) &&  // the imm is zero
59         (isZeroImm(MI->getOperand(2)))) {
60       FrameIndex = MI->getOperand(1).getIndex();
61       return MI->getOperand(0).getReg();
62     }
63   }
64 
65   return 0;
66 }
67 
68 /// isStoreToStackSlot - If the specified machine instruction is a direct
69 /// store to a stack slot, return the virtual or physical register number of
70 /// the source reg along with the FrameIndex of the loaded stack slot.  If
71 /// not, return 0.  This predicate must return 0 if the instruction has
72 /// any side effects other than storing to the stack slot.
73 unsigned MipsInstrInfo::
74 isStoreToStackSlot(const MachineInstr *MI, int &FrameIndex) const
75 {
76   unsigned Opc = MI->getOpcode();
77 
78   if ((Opc == Mips::SW)    || (Opc == Mips::SW_P8)  || (Opc == Mips::SD) ||
79       (Opc == Mips::SD_P8) || (Opc == Mips::SWC1)   || (Opc == Mips::SWC1_P8) ||
80       (Opc == Mips::SDC1)  || (Opc == Mips::SDC164) ||
81       (Opc == Mips::SDC164_P8)) {
82     if ((MI->getOperand(1).isFI()) && // is a stack slot
83         (MI->getOperand(2).isImm()) &&  // the imm is zero
84         (isZeroImm(MI->getOperand(2)))) {
85       FrameIndex = MI->getOperand(1).getIndex();
86       return MI->getOperand(0).getReg();
87     }
88   }
89   return 0;
90 }
91 
92 /// insertNoop - If data hazard condition is found insert the target nop
93 /// instruction.
94 void MipsInstrInfo::
95 insertNoop(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI) const
96 {
97   DebugLoc DL;
98   BuildMI(MBB, MI, DL, get(Mips::NOP));
99 }
100 
101 void MipsInstrInfo::
102 copyPhysReg(MachineBasicBlock &MBB,
103             MachineBasicBlock::iterator I, DebugLoc DL,
104             unsigned DestReg, unsigned SrcReg,
105             bool KillSrc) const {
106   unsigned Opc = 0, ZeroReg = 0;
107 
108   if (Mips::CPURegsRegClass.contains(DestReg)) { // Copy to CPU Reg.
109     if (Mips::CPURegsRegClass.contains(SrcReg))
110       Opc = Mips::ADDu, ZeroReg = Mips::ZERO;
111     else if (Mips::CCRRegClass.contains(SrcReg))
112       Opc = Mips::CFC1;
113     else if (Mips::FGR32RegClass.contains(SrcReg))
114       Opc = Mips::MFC1;
115     else if (SrcReg == Mips::HI)
116       Opc = Mips::MFHI, SrcReg = 0;
117     else if (SrcReg == Mips::LO)
118       Opc = Mips::MFLO, SrcReg = 0;
119   }
120   else if (Mips::CPURegsRegClass.contains(SrcReg)) { // Copy from CPU Reg.
121     if (Mips::CCRRegClass.contains(DestReg))
122       Opc = Mips::CTC1;
123     else if (Mips::FGR32RegClass.contains(DestReg))
124       Opc = Mips::MTC1;
125     else if (DestReg == Mips::HI)
126       Opc = Mips::MTHI, DestReg = 0;
127     else if (DestReg == Mips::LO)
128       Opc = Mips::MTLO, DestReg = 0;
129   }
130   else if (Mips::FGR32RegClass.contains(DestReg, SrcReg))
131     Opc = Mips::FMOV_S;
132   else if (Mips::AFGR64RegClass.contains(DestReg, SrcReg))
133     Opc = Mips::FMOV_D32;
134   else if (Mips::FGR64RegClass.contains(DestReg, SrcReg))
135     Opc = Mips::FMOV_D64;
136   else if (Mips::CCRRegClass.contains(DestReg, SrcReg))
137     Opc = Mips::MOVCCRToCCR;
138   else if (Mips::CPU64RegsRegClass.contains(DestReg)) { // Copy to CPU64 Reg.
139     if (Mips::CPU64RegsRegClass.contains(SrcReg))
140       Opc = Mips::DADDu, ZeroReg = Mips::ZERO_64;
141     else if (SrcReg == Mips::HI64)
142       Opc = Mips::MFHI64, SrcReg = 0;
143     else if (SrcReg == Mips::LO64)
144       Opc = Mips::MFLO64, SrcReg = 0;
145     else if (Mips::FGR64RegClass.contains(SrcReg))
146       Opc = Mips::DMFC1;
147   }
148   else if (Mips::CPU64RegsRegClass.contains(SrcReg)) { // Copy from CPU64 Reg.
149     if (DestReg == Mips::HI64)
150       Opc = Mips::MTHI64, DestReg = 0;
151     else if (DestReg == Mips::LO64)
152       Opc = Mips::MTLO64, DestReg = 0;
153     else if (Mips::FGR64RegClass.contains(DestReg))
154       Opc = Mips::DMTC1;
155   }
156 
157   assert(Opc && "Cannot copy registers");
158 
159   MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(Opc));
160 
161   if (DestReg)
162     MIB.addReg(DestReg, RegState::Define);
163 
164   if (ZeroReg)
165     MIB.addReg(ZeroReg);
166 
167   if (SrcReg)
168     MIB.addReg(SrcReg, getKillRegState(KillSrc));
169 }
170 
171 static MachineMemOperand* GetMemOperand(MachineBasicBlock &MBB, int FI,
172                                         unsigned Flag) {
173   MachineFunction &MF = *MBB.getParent();
174   MachineFrameInfo &MFI = *MF.getFrameInfo();
175   unsigned Align = MFI.getObjectAlignment(FI);
176 
177   return MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(FI), Flag,
178                                  MFI.getObjectSize(FI), Align);
179 }
180 
181 void MipsInstrInfo::
182 storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
183                     unsigned SrcReg, bool isKill, int FI,
184                     const TargetRegisterClass *RC,
185                     const TargetRegisterInfo *TRI) const {
186   DebugLoc DL;
187   if (I != MBB.end()) DL = I->getDebugLoc();
188   MachineMemOperand *MMO = GetMemOperand(MBB, FI, MachineMemOperand::MOStore);
189 
190   unsigned Opc = 0;
191 
192   if (Mips::CPURegsRegClass.hasSubClassEq(RC))
193     Opc = IsN64 ? Mips::SW_P8 : Mips::SW;
194   else if (Mips::CPU64RegsRegClass.hasSubClassEq(RC))
195     Opc = IsN64 ? Mips::SD_P8 : Mips::SD;
196   else if (Mips::FGR32RegClass.hasSubClassEq(RC))
197     Opc = IsN64 ? Mips::SWC1_P8 : Mips::SWC1;
198   else if (Mips::AFGR64RegClass.hasSubClassEq(RC))
199     Opc = Mips::SDC1;
200   else if (Mips::FGR64RegClass.hasSubClassEq(RC))
201     Opc = IsN64 ? Mips::SDC164_P8 : Mips::SDC164;
202 
203   assert(Opc && "Register class not handled!");
204   BuildMI(MBB, I, DL, get(Opc)).addReg(SrcReg, getKillRegState(isKill))
205     .addFrameIndex(FI).addImm(0).addMemOperand(MMO);
206 }
207 
208 void MipsInstrInfo::
209 loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
210                      unsigned DestReg, int FI,
211                      const TargetRegisterClass *RC,
212                      const TargetRegisterInfo *TRI) const
213 {
214   DebugLoc DL;
215   if (I != MBB.end()) DL = I->getDebugLoc();
216   MachineMemOperand *MMO = GetMemOperand(MBB, FI, MachineMemOperand::MOLoad);
217   unsigned Opc = 0;
218 
219   if (Mips::CPURegsRegClass.hasSubClassEq(RC))
220     Opc = IsN64 ? Mips::LW_P8 : Mips::LW;
221   else if (Mips::CPU64RegsRegClass.hasSubClassEq(RC))
222     Opc = IsN64 ? Mips::LD_P8 : Mips::LD;
223   else if (Mips::FGR32RegClass.hasSubClassEq(RC))
224     Opc = IsN64 ? Mips::LWC1_P8 : Mips::LWC1;
225   else if (Mips::AFGR64RegClass.hasSubClassEq(RC))
226     Opc = Mips::LDC1;
227   else if (Mips::FGR64RegClass.hasSubClassEq(RC))
228     Opc = IsN64 ? Mips::LDC164_P8 : Mips::LDC164;
229 
230   assert(Opc && "Register class not handled!");
231   BuildMI(MBB, I, DL, get(Opc), DestReg).addFrameIndex(FI).addImm(0)
232     .addMemOperand(MMO);
233 }
234 
235 void MipsInstrInfo::ExpandExtractElementF64(MachineBasicBlock &MBB,
236                                           MachineBasicBlock::iterator I) const {
237   const TargetInstrInfo *TII = TM.getInstrInfo();
238   unsigned DstReg = I->getOperand(0).getReg();
239   unsigned SrcReg = I->getOperand(1).getReg();
240   unsigned N = I->getOperand(2).getImm();
241   const MCInstrDesc& Mfc1Tdd = TII->get(Mips::MFC1);
242   DebugLoc dl = I->getDebugLoc();
243 
244   assert(N < 2 && "Invalid immediate");
245   unsigned SubIdx = N ? Mips::sub_fpodd : Mips::sub_fpeven;
246   unsigned SubReg = TM.getRegisterInfo()->getSubReg(SrcReg, SubIdx);
247 
248   BuildMI(MBB, I, dl, Mfc1Tdd, DstReg).addReg(SubReg);
249 }
250 
251 void MipsInstrInfo::ExpandBuildPairF64(MachineBasicBlock &MBB,
252                                        MachineBasicBlock::iterator I) const {
253   const TargetInstrInfo *TII = TM.getInstrInfo();
254   unsigned DstReg = I->getOperand(0).getReg();
255   unsigned LoReg = I->getOperand(1).getReg(), HiReg = I->getOperand(2).getReg();
256   const MCInstrDesc& Mtc1Tdd = TII->get(Mips::MTC1);
257   DebugLoc dl = I->getDebugLoc();
258   const TargetRegisterInfo *TRI = TM.getRegisterInfo();
259 
260   // mtc1 Lo, $fp
261   // mtc1 Hi, $fp + 1
262   BuildMI(MBB, I, dl, Mtc1Tdd, TRI->getSubReg(DstReg, Mips::sub_fpeven))
263     .addReg(LoReg);
264   BuildMI(MBB, I, dl, Mtc1Tdd, TRI->getSubReg(DstReg, Mips::sub_fpodd))
265     .addReg(HiReg);
266 }
267 
268 bool MipsInstrInfo::expandPostRAPseudo(MachineBasicBlock::iterator MI) const {
269   MachineBasicBlock &MBB = *MI->getParent();
270 
271   switch(MI->getDesc().getOpcode()) {
272   default:
273     return false;
274   case Mips::BuildPairF64:
275     ExpandBuildPairF64(MBB, MI);
276     break;
277   case Mips::ExtractElementF64:
278     ExpandExtractElementF64(MBB, MI);
279     break;
280   }
281 
282   MBB.erase(MI);
283   return true;
284 }
285 
286 MachineInstr*
287 MipsInstrInfo::emitFrameIndexDebugValue(MachineFunction &MF, int FrameIx,
288                                         uint64_t Offset, const MDNode *MDPtr,
289                                         DebugLoc DL) const {
290   MachineInstrBuilder MIB = BuildMI(MF, DL, get(Mips::DBG_VALUE))
291     .addFrameIndex(FrameIx).addImm(0).addImm(Offset).addMetadata(MDPtr);
292   return &*MIB;
293 }
294 
295 //===----------------------------------------------------------------------===//
296 // Branch Analysis
297 //===----------------------------------------------------------------------===//
298 
299 static unsigned GetAnalyzableBrOpc(unsigned Opc) {
300   return (Opc == Mips::BEQ    || Opc == Mips::BNE    || Opc == Mips::BGTZ   ||
301           Opc == Mips::BGEZ   || Opc == Mips::BLTZ   || Opc == Mips::BLEZ   ||
302           Opc == Mips::BEQ64  || Opc == Mips::BNE64  || Opc == Mips::BGTZ64 ||
303           Opc == Mips::BGEZ64 || Opc == Mips::BLTZ64 || Opc == Mips::BLEZ64 ||
304           Opc == Mips::BC1T   || Opc == Mips::BC1F   || Opc == Mips::B      ||
305           Opc == Mips::J) ?
306          Opc : 0;
307 }
308 
309 /// GetOppositeBranchOpc - Return the inverse of the specified
310 /// opcode, e.g. turning BEQ to BNE.
311 unsigned Mips::GetOppositeBranchOpc(unsigned Opc)
312 {
313   switch (Opc) {
314   default:           llvm_unreachable("Illegal opcode!");
315   case Mips::BEQ:    return Mips::BNE;
316   case Mips::BNE:    return Mips::BEQ;
317   case Mips::BGTZ:   return Mips::BLEZ;
318   case Mips::BGEZ:   return Mips::BLTZ;
319   case Mips::BLTZ:   return Mips::BGEZ;
320   case Mips::BLEZ:   return Mips::BGTZ;
321   case Mips::BEQ64:  return Mips::BNE64;
322   case Mips::BNE64:  return Mips::BEQ64;
323   case Mips::BGTZ64: return Mips::BLEZ64;
324   case Mips::BGEZ64: return Mips::BLTZ64;
325   case Mips::BLTZ64: return Mips::BGEZ64;
326   case Mips::BLEZ64: return Mips::BGTZ64;
327   case Mips::BC1T:   return Mips::BC1F;
328   case Mips::BC1F:   return Mips::BC1T;
329   }
330 }
331 
332 static void AnalyzeCondBr(const MachineInstr* Inst, unsigned Opc,
333                           MachineBasicBlock *&BB,
334                           SmallVectorImpl<MachineOperand>& Cond) {
335   assert(GetAnalyzableBrOpc(Opc) && "Not an analyzable branch");
336   int NumOp = Inst->getNumExplicitOperands();
337 
338   // for both int and fp branches, the last explicit operand is the
339   // MBB.
340   BB = Inst->getOperand(NumOp-1).getMBB();
341   Cond.push_back(MachineOperand::CreateImm(Opc));
342 
343   for (int i=0; i<NumOp-1; i++)
344     Cond.push_back(Inst->getOperand(i));
345 }
346 
347 bool MipsInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,
348                                   MachineBasicBlock *&TBB,
349                                   MachineBasicBlock *&FBB,
350                                   SmallVectorImpl<MachineOperand> &Cond,
351                                   bool AllowModify) const
352 {
353   MachineBasicBlock::reverse_iterator I = MBB.rbegin(), REnd = MBB.rend();
354 
355   // Skip all the debug instructions.
356   while (I != REnd && I->isDebugValue())
357     ++I;
358 
359   if (I == REnd || !isUnpredicatedTerminator(&*I)) {
360     // If this block ends with no branches (it just falls through to its succ)
361     // just return false, leaving TBB/FBB null.
362     TBB = FBB = NULL;
363     return false;
364   }
365 
366   MachineInstr *LastInst = &*I;
367   unsigned LastOpc = LastInst->getOpcode();
368 
369   // Not an analyzable branch (must be an indirect jump).
370   if (!GetAnalyzableBrOpc(LastOpc))
371     return true;
372 
373   // Get the second to last instruction in the block.
374   unsigned SecondLastOpc = 0;
375   MachineInstr *SecondLastInst = NULL;
376 
377   if (++I != REnd) {
378     SecondLastInst = &*I;
379     SecondLastOpc = GetAnalyzableBrOpc(SecondLastInst->getOpcode());
380 
381     // Not an analyzable branch (must be an indirect jump).
382     if (isUnpredicatedTerminator(SecondLastInst) && !SecondLastOpc)
383       return true;
384   }
385 
386   // If there is only one terminator instruction, process it.
387   if (!SecondLastOpc) {
388     // Unconditional branch
389     if (LastOpc == UncondBrOpc) {
390       TBB = LastInst->getOperand(0).getMBB();
391       return false;
392     }
393 
394     // Conditional branch
395     AnalyzeCondBr(LastInst, LastOpc, TBB, Cond);
396     return false;
397   }
398 
399   // If we reached here, there are two branches.
400   // If there are three terminators, we don't know what sort of block this is.
401   if (++I != REnd && isUnpredicatedTerminator(&*I))
402     return true;
403 
404   // If second to last instruction is an unconditional branch,
405   // analyze it and remove the last instruction.
406   if (SecondLastOpc == UncondBrOpc) {
407     // Return if the last instruction cannot be removed.
408     if (!AllowModify)
409       return true;
410 
411     TBB = SecondLastInst->getOperand(0).getMBB();
412     LastInst->eraseFromParent();
413     return false;
414   }
415 
416   // Conditional branch followed by an unconditional branch.
417   // The last one must be unconditional.
418   if (LastOpc != UncondBrOpc)
419     return true;
420 
421   AnalyzeCondBr(SecondLastInst, SecondLastOpc, TBB, Cond);
422   FBB = LastInst->getOperand(0).getMBB();
423 
424   return false;
425 }
426 
427 void MipsInstrInfo::BuildCondBr(MachineBasicBlock &MBB,
428                                 MachineBasicBlock *TBB, DebugLoc DL,
429                                 const SmallVectorImpl<MachineOperand>& Cond)
430   const {
431   unsigned Opc = Cond[0].getImm();
432   const MCInstrDesc &MCID = get(Opc);
433   MachineInstrBuilder MIB = BuildMI(&MBB, DL, MCID);
434 
435   for (unsigned i = 1; i < Cond.size(); ++i)
436     MIB.addReg(Cond[i].getReg());
437 
438   MIB.addMBB(TBB);
439 }
440 
441 unsigned MipsInstrInfo::
442 InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
443              MachineBasicBlock *FBB,
444              const SmallVectorImpl<MachineOperand> &Cond,
445              DebugLoc DL) const {
446   // Shouldn't be a fall through.
447   assert(TBB && "InsertBranch must not be told to insert a fallthrough");
448 
449   // # of condition operands:
450   //  Unconditional branches: 0
451   //  Floating point branches: 1 (opc)
452   //  Int BranchZero: 2 (opc, reg)
453   //  Int Branch: 3 (opc, reg0, reg1)
454   assert((Cond.size() <= 3) &&
455          "# of Mips branch conditions must be <= 3!");
456 
457   // Two-way Conditional branch.
458   if (FBB) {
459     BuildCondBr(MBB, TBB, DL, Cond);
460     BuildMI(&MBB, DL, get(UncondBrOpc)).addMBB(FBB);
461     return 2;
462   }
463 
464   // One way branch.
465   // Unconditional branch.
466   if (Cond.empty())
467     BuildMI(&MBB, DL, get(UncondBrOpc)).addMBB(TBB);
468   else // Conditional branch.
469     BuildCondBr(MBB, TBB, DL, Cond);
470   return 1;
471 }
472 
473 unsigned MipsInstrInfo::
474 RemoveBranch(MachineBasicBlock &MBB) const
475 {
476   MachineBasicBlock::reverse_iterator I = MBB.rbegin(), REnd = MBB.rend();
477   MachineBasicBlock::reverse_iterator FirstBr;
478   unsigned removed;
479 
480   // Skip all the debug instructions.
481   while (I != REnd && I->isDebugValue())
482     ++I;
483 
484   FirstBr = I;
485 
486   // Up to 2 branches are removed.
487   // Note that indirect branches are not removed.
488   for(removed = 0; I != REnd && removed < 2; ++I, ++removed)
489     if (!GetAnalyzableBrOpc(I->getOpcode()))
490       break;
491 
492   MBB.erase(I.base(), FirstBr.base());
493 
494   return removed;
495 }
496 
497 /// ReverseBranchCondition - Return the inverse opcode of the
498 /// specified Branch instruction.
499 bool MipsInstrInfo::
500 ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const
501 {
502   assert( (Cond.size() && Cond.size() <= 3) &&
503           "Invalid Mips branch condition!");
504   Cond[0].setImm(Mips::GetOppositeBranchOpc(Cond[0].getImm()));
505   return false;
506 }
507 
508