1 //===- MipsInstrInfo.cpp - Mips Instruction Information ---------*- C++ -*-===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file contains the Mips implementation of the TargetInstrInfo class.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #include "MipsInstrInfo.h"
15 #include "MipsTargetMachine.h"
16 #include "MipsMachineFunction.h"
17 #include "llvm/ADT/STLExtras.h"
18 #include "llvm/CodeGen/MachineInstrBuilder.h"
19 #include "llvm/CodeGen/MachineRegisterInfo.h"
20 #include "MipsGenInstrInfo.inc"
21 
22 using namespace llvm;
23 
24 MipsInstrInfo::MipsInstrInfo(MipsTargetMachine &tm)
25   : TargetInstrInfoImpl(MipsInsts, array_lengthof(MipsInsts)),
26     TM(tm), RI(*TM.getSubtargetImpl(), *this) {}
27 
28 static bool isZeroImm(const MachineOperand &op) {
29   return op.isImm() && op.getImm() == 0;
30 }
31 
32 /// Return true if the instruction is a register to register move and
33 /// leave the source and dest operands in the passed parameters.
34 bool MipsInstrInfo::
35 isMoveInstr(const MachineInstr &MI, unsigned &SrcReg, unsigned &DstReg,
36             unsigned &SrcSubIdx, unsigned &DstSubIdx) const
37 {
38   SrcSubIdx = DstSubIdx = 0; // No sub-registers.
39 
40   // addu $dst, $src, $zero || addu $dst, $zero, $src
41   // or   $dst, $src, $zero || or   $dst, $zero, $src
42   if ((MI.getOpcode() == Mips::ADDu) || (MI.getOpcode() == Mips::OR)) {
43     if (MI.getOperand(1).getReg() == Mips::ZERO) {
44       DstReg = MI.getOperand(0).getReg();
45       SrcReg = MI.getOperand(2).getReg();
46       return true;
47     } else if (MI.getOperand(2).getReg() == Mips::ZERO) {
48       DstReg = MI.getOperand(0).getReg();
49       SrcReg = MI.getOperand(1).getReg();
50       return true;
51     }
52   }
53 
54   // mov $fpDst, $fpSrc
55   // mfc $gpDst, $fpSrc
56   // mtc $fpDst, $gpSrc
57   if (MI.getOpcode() == Mips::FMOV_S32 ||
58       MI.getOpcode() == Mips::FMOV_D32 ||
59       MI.getOpcode() == Mips::MFC1 ||
60       MI.getOpcode() == Mips::MTC1 ||
61       MI.getOpcode() == Mips::MOVCCRToCCR) {
62     DstReg = MI.getOperand(0).getReg();
63     SrcReg = MI.getOperand(1).getReg();
64     return true;
65   }
66 
67   // addiu $dst, $src, 0
68   if (MI.getOpcode() == Mips::ADDiu) {
69     if ((MI.getOperand(1).isReg()) && (isZeroImm(MI.getOperand(2)))) {
70       DstReg = MI.getOperand(0).getReg();
71       SrcReg = MI.getOperand(1).getReg();
72       return true;
73     }
74   }
75 
76   return false;
77 }
78 
79 /// isLoadFromStackSlot - If the specified machine instruction is a direct
80 /// load from a stack slot, return the virtual or physical register number of
81 /// the destination along with the FrameIndex of the loaded stack slot.  If
82 /// not, return 0.  This predicate must return 0 if the instruction has
83 /// any side effects other than loading from the stack slot.
84 unsigned MipsInstrInfo::
85 isLoadFromStackSlot(const MachineInstr *MI, int &FrameIndex) const
86 {
87   if ((MI->getOpcode() == Mips::LW) || (MI->getOpcode() == Mips::LWC1) ||
88       (MI->getOpcode() == Mips::LDC1)) {
89     if ((MI->getOperand(2).isFI()) && // is a stack slot
90         (MI->getOperand(1).isImm()) &&  // the imm is zero
91         (isZeroImm(MI->getOperand(1)))) {
92       FrameIndex = MI->getOperand(2).getIndex();
93       return MI->getOperand(0).getReg();
94     }
95   }
96 
97   return 0;
98 }
99 
100 /// isStoreToStackSlot - If the specified machine instruction is a direct
101 /// store to a stack slot, return the virtual or physical register number of
102 /// the source reg along with the FrameIndex of the loaded stack slot.  If
103 /// not, return 0.  This predicate must return 0 if the instruction has
104 /// any side effects other than storing to the stack slot.
105 unsigned MipsInstrInfo::
106 isStoreToStackSlot(const MachineInstr *MI, int &FrameIndex) const
107 {
108   if ((MI->getOpcode() == Mips::SW) || (MI->getOpcode() == Mips::SWC1) ||
109       (MI->getOpcode() == Mips::SDC1)) {
110     if ((MI->getOperand(2).isFI()) && // is a stack slot
111         (MI->getOperand(1).isImm()) &&  // the imm is zero
112         (isZeroImm(MI->getOperand(1)))) {
113       FrameIndex = MI->getOperand(2).getIndex();
114       return MI->getOperand(0).getReg();
115     }
116   }
117   return 0;
118 }
119 
120 /// insertNoop - If data hazard condition is found insert the target nop
121 /// instruction.
122 void MipsInstrInfo::
123 insertNoop(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI) const
124 {
125   DebugLoc DL = DebugLoc::getUnknownLoc();
126   if (MI != MBB.end()) DL = MI->getDebugLoc();
127   BuildMI(MBB, MI, DL, get(Mips::NOP));
128 }
129 
130 bool MipsInstrInfo::
131 copyRegToReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
132              unsigned DestReg, unsigned SrcReg,
133              const TargetRegisterClass *DestRC,
134              const TargetRegisterClass *SrcRC) const {
135   DebugLoc DL = DebugLoc::getUnknownLoc();
136   if (I != MBB.end()) DL = I->getDebugLoc();
137 
138   if (DestRC != SrcRC) {
139 
140     // Copy to/from FCR31 condition register
141     if ((DestRC == Mips::CPURegsRegisterClass) &&
142         (SrcRC == Mips::CCRRegisterClass))
143       BuildMI(MBB, I, DL, get(Mips::CFC1), DestReg).addReg(SrcReg);
144     else if ((DestRC == Mips::CCRRegisterClass) &&
145         (SrcRC == Mips::CPURegsRegisterClass))
146       BuildMI(MBB, I, DL, get(Mips::CTC1), DestReg).addReg(SrcReg);
147 
148     // Moves between coprocessors and cpu
149     else if ((DestRC == Mips::CPURegsRegisterClass) &&
150         (SrcRC == Mips::FGR32RegisterClass))
151       BuildMI(MBB, I, DL, get(Mips::MFC1), DestReg).addReg(SrcReg);
152     else if ((DestRC == Mips::FGR32RegisterClass) &&
153              (SrcRC == Mips::CPURegsRegisterClass))
154       BuildMI(MBB, I, DL, get(Mips::MTC1), DestReg).addReg(SrcReg);
155 
156     // Move from/to Hi/Lo registers
157     else if ((DestRC == Mips::HILORegisterClass) &&
158              (SrcRC == Mips::CPURegsRegisterClass)) {
159       unsigned Opc = (DestReg == Mips::HI) ? Mips::MTHI : Mips::MTLO;
160       BuildMI(MBB, I, DL, get(Opc), DestReg);
161     } else if ((SrcRC == Mips::HILORegisterClass) &&
162                (DestRC == Mips::CPURegsRegisterClass)) {
163       unsigned Opc = (SrcReg == Mips::HI) ? Mips::MFHI : Mips::MFLO;
164       BuildMI(MBB, I, DL, get(Opc), DestReg);
165 
166     // Can't copy this register
167     } else
168       return false;
169 
170     return true;
171   }
172 
173   if (DestRC == Mips::CPURegsRegisterClass)
174     BuildMI(MBB, I, DL, get(Mips::ADDu), DestReg).addReg(Mips::ZERO)
175       .addReg(SrcReg);
176   else if (DestRC == Mips::FGR32RegisterClass)
177     BuildMI(MBB, I, DL, get(Mips::FMOV_S32), DestReg).addReg(SrcReg);
178   else if (DestRC == Mips::AFGR64RegisterClass)
179     BuildMI(MBB, I, DL, get(Mips::FMOV_D32), DestReg).addReg(SrcReg);
180   else if (DestRC == Mips::CCRRegisterClass)
181     BuildMI(MBB, I, DL, get(Mips::MOVCCRToCCR), DestReg).addReg(SrcReg);
182   else
183     // Can't copy this register
184     return false;
185 
186   return true;
187 }
188 
189 void MipsInstrInfo::
190 storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
191                     unsigned SrcReg, bool isKill, int FI,
192                     const TargetRegisterClass *RC) const {
193   unsigned Opc;
194 
195   DebugLoc DL = DebugLoc::getUnknownLoc();
196   if (I != MBB.end()) DL = I->getDebugLoc();
197 
198   if (RC == Mips::CPURegsRegisterClass)
199     Opc = Mips::SW;
200   else if (RC == Mips::FGR32RegisterClass)
201     Opc = Mips::SWC1;
202   else {
203     assert(RC == Mips::AFGR64RegisterClass);
204     Opc = Mips::SDC1;
205   }
206 
207   BuildMI(MBB, I, DL, get(Opc)).addReg(SrcReg, getKillRegState(isKill))
208           .addImm(0).addFrameIndex(FI);
209 }
210 
211 void MipsInstrInfo::storeRegToAddr(MachineFunction &MF, unsigned SrcReg,
212   bool isKill, SmallVectorImpl<MachineOperand> &Addr,
213   const TargetRegisterClass *RC, SmallVectorImpl<MachineInstr*> &NewMIs) const
214 {
215   unsigned Opc;
216   if (RC == Mips::CPURegsRegisterClass)
217     Opc = Mips::SW;
218   else if (RC == Mips::FGR32RegisterClass)
219     Opc = Mips::SWC1;
220   else {
221     assert(RC == Mips::AFGR64RegisterClass);
222     Opc = Mips::SDC1;
223   }
224 
225   DebugLoc DL = DebugLoc::getUnknownLoc();
226   MachineInstrBuilder MIB = BuildMI(MF, DL, get(Opc))
227     .addReg(SrcReg, getKillRegState(isKill));
228   for (unsigned i = 0, e = Addr.size(); i != e; ++i)
229     MIB.addOperand(Addr[i]);
230   NewMIs.push_back(MIB);
231   return;
232 }
233 
234 void MipsInstrInfo::
235 loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
236                      unsigned DestReg, int FI,
237                      const TargetRegisterClass *RC) const
238 {
239   unsigned Opc;
240   if (RC == Mips::CPURegsRegisterClass)
241     Opc = Mips::LW;
242   else if (RC == Mips::FGR32RegisterClass)
243     Opc = Mips::LWC1;
244   else {
245     assert(RC == Mips::AFGR64RegisterClass);
246     Opc = Mips::LDC1;
247   }
248 
249   DebugLoc DL = DebugLoc::getUnknownLoc();
250   if (I != MBB.end()) DL = I->getDebugLoc();
251   BuildMI(MBB, I, DL, get(Opc), DestReg).addImm(0).addFrameIndex(FI);
252 }
253 
254 void MipsInstrInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
255                                     SmallVectorImpl<MachineOperand> &Addr,
256                                     const TargetRegisterClass *RC,
257                                  SmallVectorImpl<MachineInstr*> &NewMIs) const {
258   unsigned Opc;
259   if (RC == Mips::CPURegsRegisterClass)
260     Opc = Mips::LW;
261   else if (RC == Mips::FGR32RegisterClass)
262     Opc = Mips::LWC1;
263   else {
264     assert(RC == Mips::AFGR64RegisterClass);
265     Opc = Mips::LDC1;
266   }
267 
268   DebugLoc DL = DebugLoc::getUnknownLoc();
269   MachineInstrBuilder MIB = BuildMI(MF, DL, get(Opc), DestReg);
270   for (unsigned i = 0, e = Addr.size(); i != e; ++i)
271     MIB.addOperand(Addr[i]);
272   NewMIs.push_back(MIB);
273   return;
274 }
275 
276 MachineInstr *MipsInstrInfo::
277 foldMemoryOperandImpl(MachineFunction &MF,
278                       MachineInstr* MI,
279                       const SmallVectorImpl<unsigned> &Ops, int FI) const
280 {
281   if (Ops.size() != 1) return NULL;
282 
283   MachineInstr *NewMI = NULL;
284 
285   switch (MI->getOpcode()) {
286   case Mips::ADDu:
287     if ((MI->getOperand(0).isReg()) &&
288         (MI->getOperand(1).isReg()) &&
289         (MI->getOperand(1).getReg() == Mips::ZERO) &&
290         (MI->getOperand(2).isReg())) {
291       if (Ops[0] == 0) {    // COPY -> STORE
292         unsigned SrcReg = MI->getOperand(2).getReg();
293         bool isKill = MI->getOperand(2).isKill();
294         bool isUndef = MI->getOperand(2).isUndef();
295         NewMI = BuildMI(MF, MI->getDebugLoc(), get(Mips::SW))
296           .addReg(SrcReg, getKillRegState(isKill) | getUndefRegState(isUndef))
297           .addImm(0).addFrameIndex(FI);
298       } else {              // COPY -> LOAD
299         unsigned DstReg = MI->getOperand(0).getReg();
300         bool isDead = MI->getOperand(0).isDead();
301         bool isUndef = MI->getOperand(0).isUndef();
302         NewMI = BuildMI(MF, MI->getDebugLoc(), get(Mips::LW))
303           .addReg(DstReg, RegState::Define | getDeadRegState(isDead) |
304                   getUndefRegState(isUndef))
305           .addImm(0).addFrameIndex(FI);
306       }
307     }
308     break;
309   case Mips::FMOV_S32:
310   case Mips::FMOV_D32:
311     if ((MI->getOperand(0).isReg()) &&
312         (MI->getOperand(1).isReg())) {
313       const TargetRegisterClass
314         *RC = RI.getRegClass(MI->getOperand(0).getReg());
315       unsigned StoreOpc, LoadOpc;
316 
317       if (RC == Mips::FGR32RegisterClass) {
318         LoadOpc = Mips::LWC1; StoreOpc = Mips::SWC1;
319       } else {
320         assert(RC == Mips::AFGR64RegisterClass);
321         LoadOpc = Mips::LDC1; StoreOpc = Mips::SDC1;
322       }
323 
324       if (Ops[0] == 0) {    // COPY -> STORE
325         unsigned SrcReg = MI->getOperand(1).getReg();
326         bool isKill = MI->getOperand(1).isKill();
327         bool isUndef = MI->getOperand(2).isUndef();
328         NewMI = BuildMI(MF, MI->getDebugLoc(), get(StoreOpc))
329           .addReg(SrcReg, getKillRegState(isKill) | getUndefRegState(isUndef))
330           .addImm(0).addFrameIndex(FI) ;
331       } else {              // COPY -> LOAD
332         unsigned DstReg = MI->getOperand(0).getReg();
333         bool isDead = MI->getOperand(0).isDead();
334         bool isUndef = MI->getOperand(0).isUndef();
335         NewMI = BuildMI(MF, MI->getDebugLoc(), get(LoadOpc))
336           .addReg(DstReg, RegState::Define | getDeadRegState(isDead) |
337                   getUndefRegState(isUndef))
338           .addImm(0).addFrameIndex(FI);
339       }
340     }
341     break;
342   }
343 
344   return NewMI;
345 }
346 
347 //===----------------------------------------------------------------------===//
348 // Branch Analysis
349 //===----------------------------------------------------------------------===//
350 
351 /// GetCondFromBranchOpc - Return the Mips CC that matches
352 /// the correspondent Branch instruction opcode.
353 static Mips::CondCode GetCondFromBranchOpc(unsigned BrOpc)
354 {
355   switch (BrOpc) {
356   default: return Mips::COND_INVALID;
357   case Mips::BEQ  : return Mips::COND_E;
358   case Mips::BNE  : return Mips::COND_NE;
359   case Mips::BGTZ : return Mips::COND_GZ;
360   case Mips::BGEZ : return Mips::COND_GEZ;
361   case Mips::BLTZ : return Mips::COND_LZ;
362   case Mips::BLEZ : return Mips::COND_LEZ;
363 
364   // We dont do fp branch analysis yet!
365   case Mips::BC1T :
366   case Mips::BC1F : return Mips::COND_INVALID;
367   }
368 }
369 
370 /// GetCondBranchFromCond - Return the Branch instruction
371 /// opcode that matches the cc.
372 unsigned Mips::GetCondBranchFromCond(Mips::CondCode CC)
373 {
374   switch (CC) {
375   default: assert(0 && "Illegal condition code!");
376   case Mips::COND_E   : return Mips::BEQ;
377   case Mips::COND_NE  : return Mips::BNE;
378   case Mips::COND_GZ  : return Mips::BGTZ;
379   case Mips::COND_GEZ : return Mips::BGEZ;
380   case Mips::COND_LZ  : return Mips::BLTZ;
381   case Mips::COND_LEZ : return Mips::BLEZ;
382 
383   case Mips::FCOND_F:
384   case Mips::FCOND_UN:
385   case Mips::FCOND_EQ:
386   case Mips::FCOND_UEQ:
387   case Mips::FCOND_OLT:
388   case Mips::FCOND_ULT:
389   case Mips::FCOND_OLE:
390   case Mips::FCOND_ULE:
391   case Mips::FCOND_SF:
392   case Mips::FCOND_NGLE:
393   case Mips::FCOND_SEQ:
394   case Mips::FCOND_NGL:
395   case Mips::FCOND_LT:
396   case Mips::FCOND_NGE:
397   case Mips::FCOND_LE:
398   case Mips::FCOND_NGT: return Mips::BC1T;
399 
400   case Mips::FCOND_T:
401   case Mips::FCOND_OR:
402   case Mips::FCOND_NEQ:
403   case Mips::FCOND_OGL:
404   case Mips::FCOND_UGE:
405   case Mips::FCOND_OGE:
406   case Mips::FCOND_UGT:
407   case Mips::FCOND_OGT:
408   case Mips::FCOND_ST:
409   case Mips::FCOND_GLE:
410   case Mips::FCOND_SNE:
411   case Mips::FCOND_GL:
412   case Mips::FCOND_NLT:
413   case Mips::FCOND_GE:
414   case Mips::FCOND_NLE:
415   case Mips::FCOND_GT: return Mips::BC1F;
416   }
417 }
418 
419 /// GetOppositeBranchCondition - Return the inverse of the specified
420 /// condition, e.g. turning COND_E to COND_NE.
421 Mips::CondCode Mips::GetOppositeBranchCondition(Mips::CondCode CC)
422 {
423   switch (CC) {
424   default: assert(0 && "Illegal condition code!");
425   case Mips::COND_E   : return Mips::COND_NE;
426   case Mips::COND_NE  : return Mips::COND_E;
427   case Mips::COND_GZ  : return Mips::COND_LEZ;
428   case Mips::COND_GEZ : return Mips::COND_LZ;
429   case Mips::COND_LZ  : return Mips::COND_GEZ;
430   case Mips::COND_LEZ : return Mips::COND_GZ;
431   case Mips::FCOND_F  : return Mips::FCOND_T;
432   case Mips::FCOND_UN : return Mips::FCOND_OR;
433   case Mips::FCOND_EQ : return Mips::FCOND_NEQ;
434   case Mips::FCOND_UEQ: return Mips::FCOND_OGL;
435   case Mips::FCOND_OLT: return Mips::FCOND_UGE;
436   case Mips::FCOND_ULT: return Mips::FCOND_OGE;
437   case Mips::FCOND_OLE: return Mips::FCOND_UGT;
438   case Mips::FCOND_ULE: return Mips::FCOND_OGT;
439   case Mips::FCOND_SF:  return Mips::FCOND_ST;
440   case Mips::FCOND_NGLE:return Mips::FCOND_GLE;
441   case Mips::FCOND_SEQ: return Mips::FCOND_SNE;
442   case Mips::FCOND_NGL: return Mips::FCOND_GL;
443   case Mips::FCOND_LT:  return Mips::FCOND_NLT;
444   case Mips::FCOND_NGE: return Mips::FCOND_GE;
445   case Mips::FCOND_LE:  return Mips::FCOND_NLE;
446   case Mips::FCOND_NGT: return Mips::FCOND_GT;
447   }
448 }
449 
450 bool MipsInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,
451                                   MachineBasicBlock *&TBB,
452                                   MachineBasicBlock *&FBB,
453                                   SmallVectorImpl<MachineOperand> &Cond,
454                                   bool AllowModify) const
455 {
456   // If the block has no terminators, it just falls into the block after it.
457   MachineBasicBlock::iterator I = MBB.end();
458   if (I == MBB.begin() || !isUnpredicatedTerminator(--I))
459     return false;
460 
461   // Get the last instruction in the block.
462   MachineInstr *LastInst = I;
463 
464   // If there is only one terminator instruction, process it.
465   unsigned LastOpc = LastInst->getOpcode();
466   if (I == MBB.begin() || !isUnpredicatedTerminator(--I)) {
467     if (!LastInst->getDesc().isBranch())
468       return true;
469 
470     // Unconditional branch
471     if (LastOpc == Mips::J) {
472       TBB = LastInst->getOperand(0).getMBB();
473       return false;
474     }
475 
476     Mips::CondCode BranchCode = GetCondFromBranchOpc(LastInst->getOpcode());
477     if (BranchCode == Mips::COND_INVALID)
478       return true;  // Can't handle indirect branch.
479 
480     // Conditional branch
481     // Block ends with fall-through condbranch.
482     if (LastOpc != Mips::COND_INVALID) {
483       int LastNumOp = LastInst->getNumOperands();
484 
485       TBB = LastInst->getOperand(LastNumOp-1).getMBB();
486       Cond.push_back(MachineOperand::CreateImm(BranchCode));
487 
488       for (int i=0; i<LastNumOp-1; i++) {
489         Cond.push_back(LastInst->getOperand(i));
490       }
491 
492       return false;
493     }
494   }
495 
496   // Get the instruction before it if it is a terminator.
497   MachineInstr *SecondLastInst = I;
498 
499   // If there are three terminators, we don't know what sort of block this is.
500   if (SecondLastInst && I != MBB.begin() && isUnpredicatedTerminator(--I))
501     return true;
502 
503   // If the block ends with Mips::J and a Mips::BNE/Mips::BEQ, handle it.
504   unsigned SecondLastOpc    = SecondLastInst->getOpcode();
505   Mips::CondCode BranchCode = GetCondFromBranchOpc(SecondLastOpc);
506 
507   if (BranchCode != Mips::COND_INVALID && LastOpc == Mips::J) {
508     int SecondNumOp = SecondLastInst->getNumOperands();
509 
510     TBB = SecondLastInst->getOperand(SecondNumOp-1).getMBB();
511     Cond.push_back(MachineOperand::CreateImm(BranchCode));
512 
513     for (int i=0; i<SecondNumOp-1; i++) {
514       Cond.push_back(SecondLastInst->getOperand(i));
515     }
516 
517     FBB = LastInst->getOperand(0).getMBB();
518     return false;
519   }
520 
521   // If the block ends with two unconditional branches, handle it. The last
522   // one is not executed, so remove it.
523   if ((SecondLastOpc == Mips::J) && (LastOpc == Mips::J)) {
524     TBB = SecondLastInst->getOperand(0).getMBB();
525     I = LastInst;
526     if (AllowModify)
527       I->eraseFromParent();
528     return false;
529   }
530 
531   // Otherwise, can't handle this.
532   return true;
533 }
534 
535 unsigned MipsInstrInfo::
536 InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
537              MachineBasicBlock *FBB,
538              const SmallVectorImpl<MachineOperand> &Cond) const {
539   // FIXME this should probably have a DebugLoc argument
540   DebugLoc dl = DebugLoc::getUnknownLoc();
541   // Shouldn't be a fall through.
542   assert(TBB && "InsertBranch must not be told to insert a fallthrough");
543   assert((Cond.size() == 3 || Cond.size() == 2 || Cond.size() == 0) &&
544          "Mips branch conditions can have two|three components!");
545 
546   if (FBB == 0) { // One way branch.
547     if (Cond.empty()) {
548       // Unconditional branch?
549       BuildMI(&MBB, dl, get(Mips::J)).addMBB(TBB);
550     } else {
551       // Conditional branch.
552       unsigned Opc = GetCondBranchFromCond((Mips::CondCode)Cond[0].getImm());
553       const TargetInstrDesc &TID = get(Opc);
554 
555       if (TID.getNumOperands() == 3)
556         BuildMI(&MBB, dl, TID).addReg(Cond[1].getReg())
557                           .addReg(Cond[2].getReg())
558                           .addMBB(TBB);
559       else
560         BuildMI(&MBB, dl, TID).addReg(Cond[1].getReg())
561                           .addMBB(TBB);
562 
563     }
564     return 1;
565   }
566 
567   // Two-way Conditional branch.
568   unsigned Opc = GetCondBranchFromCond((Mips::CondCode)Cond[0].getImm());
569   const TargetInstrDesc &TID = get(Opc);
570 
571   if (TID.getNumOperands() == 3)
572     BuildMI(&MBB, dl, TID).addReg(Cond[1].getReg()).addReg(Cond[2].getReg())
573                       .addMBB(TBB);
574   else
575     BuildMI(&MBB, dl, TID).addReg(Cond[1].getReg()).addMBB(TBB);
576 
577   BuildMI(&MBB, dl, get(Mips::J)).addMBB(FBB);
578   return 2;
579 }
580 
581 unsigned MipsInstrInfo::
582 RemoveBranch(MachineBasicBlock &MBB) const
583 {
584   MachineBasicBlock::iterator I = MBB.end();
585   if (I == MBB.begin()) return 0;
586   --I;
587   if (I->getOpcode() != Mips::J &&
588       GetCondFromBranchOpc(I->getOpcode()) == Mips::COND_INVALID)
589     return 0;
590 
591   // Remove the branch.
592   I->eraseFromParent();
593 
594   I = MBB.end();
595 
596   if (I == MBB.begin()) return 1;
597   --I;
598   if (GetCondFromBranchOpc(I->getOpcode()) == Mips::COND_INVALID)
599     return 1;
600 
601   // Remove the branch.
602   I->eraseFromParent();
603   return 2;
604 }
605 
606 /// BlockHasNoFallThrough - Analyze if MachineBasicBlock does not
607 /// fall-through into its successor block.
608 bool MipsInstrInfo::
609 BlockHasNoFallThrough(const MachineBasicBlock &MBB) const
610 {
611   if (MBB.empty()) return false;
612 
613   switch (MBB.back().getOpcode()) {
614   case Mips::RET:     // Return.
615   case Mips::JR:      // Indirect branch.
616   case Mips::J:       // Uncond branch.
617     return true;
618   default: return false;
619   }
620 }
621 
622 /// ReverseBranchCondition - Return the inverse opcode of the
623 /// specified Branch instruction.
624 bool MipsInstrInfo::
625 ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const
626 {
627   assert( (Cond.size() == 3 || Cond.size() == 2) &&
628           "Invalid Mips branch condition!");
629   Cond[0].setImm(GetOppositeBranchCondition((Mips::CondCode)Cond[0].getImm()));
630   return false;
631 }
632 
633 /// getGlobalBaseReg - Return a virtual register initialized with the
634 /// the global base register value. Output instructions required to
635 /// initialize the register in the function entry block, if necessary.
636 ///
637 unsigned MipsInstrInfo::getGlobalBaseReg(MachineFunction *MF) const {
638   MipsFunctionInfo *MipsFI = MF->getInfo<MipsFunctionInfo>();
639   unsigned GlobalBaseReg = MipsFI->getGlobalBaseReg();
640   if (GlobalBaseReg != 0)
641     return GlobalBaseReg;
642 
643   // Insert the set of GlobalBaseReg into the first MBB of the function
644   MachineBasicBlock &FirstMBB = MF->front();
645   MachineBasicBlock::iterator MBBI = FirstMBB.begin();
646   MachineRegisterInfo &RegInfo = MF->getRegInfo();
647   const TargetInstrInfo *TII = MF->getTarget().getInstrInfo();
648 
649   GlobalBaseReg = RegInfo.createVirtualRegister(Mips::CPURegsRegisterClass);
650   bool Ok = TII->copyRegToReg(FirstMBB, MBBI, GlobalBaseReg, Mips::GP,
651                               Mips::CPURegsRegisterClass,
652                               Mips::CPURegsRegisterClass);
653   assert(Ok && "Couldn't assign to global base register!");
654   RegInfo.addLiveIn(Mips::GP);
655 
656   MipsFI->setGlobalBaseReg(GlobalBaseReg);
657   return GlobalBaseReg;
658 }
659