1 //===- MipsInstrInfo.cpp - Mips Instruction Information -------------------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file contains the Mips implementation of the TargetInstrInfo class.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #include "MipsInstrInfo.h"
15 #include "MCTargetDesc/MipsBaseInfo.h"
16 #include "MCTargetDesc/MipsMCTargetDesc.h"
17 #include "MipsSubtarget.h"
18 #include "llvm/ADT/SmallVector.h"
19 #include "llvm/CodeGen/MachineBasicBlock.h"
20 #include "llvm/CodeGen/MachineFrameInfo.h"
21 #include "llvm/CodeGen/MachineFunction.h"
22 #include "llvm/CodeGen/MachineInstr.h"
23 #include "llvm/CodeGen/MachineInstrBuilder.h"
24 #include "llvm/CodeGen/MachineOperand.h"
25 #include "llvm/IR/DebugLoc.h"
26 #include "llvm/MC/MCInstrDesc.h"
27 #include "llvm/Target/TargetMachine.h"
28 #include "llvm/Target/TargetOpcodes.h"
29 #include "llvm/Target/TargetSubtargetInfo.h"
30 #include <cassert>
31 
32 using namespace llvm;
33 
34 #define GET_INSTRINFO_CTOR_DTOR
35 #include "MipsGenInstrInfo.inc"
36 
37 // Pin the vtable to this file.
38 void MipsInstrInfo::anchor() {}
39 
40 MipsInstrInfo::MipsInstrInfo(const MipsSubtarget &STI, unsigned UncondBr)
41     : MipsGenInstrInfo(Mips::ADJCALLSTACKDOWN, Mips::ADJCALLSTACKUP),
42       Subtarget(STI), UncondBrOpc(UncondBr) {}
43 
44 const MipsInstrInfo *MipsInstrInfo::create(MipsSubtarget &STI) {
45   if (STI.inMips16Mode())
46     return createMips16InstrInfo(STI);
47 
48   return createMipsSEInstrInfo(STI);
49 }
50 
51 bool MipsInstrInfo::isZeroImm(const MachineOperand &op) const {
52   return op.isImm() && op.getImm() == 0;
53 }
54 
55 /// insertNoop - If data hazard condition is found insert the target nop
56 /// instruction.
57 // FIXME: This appears to be dead code.
58 void MipsInstrInfo::
59 insertNoop(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI) const
60 {
61   DebugLoc DL;
62   BuildMI(MBB, MI, DL, get(Mips::NOP));
63 }
64 
65 MachineMemOperand *
66 MipsInstrInfo::GetMemOperand(MachineBasicBlock &MBB, int FI,
67                              MachineMemOperand::Flags Flags) const {
68   MachineFunction &MF = *MBB.getParent();
69   MachineFrameInfo &MFI = MF.getFrameInfo();
70   unsigned Align = MFI.getObjectAlignment(FI);
71 
72   return MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(MF, FI),
73                                  Flags, MFI.getObjectSize(FI), Align);
74 }
75 
76 //===----------------------------------------------------------------------===//
77 // Branch Analysis
78 //===----------------------------------------------------------------------===//
79 
80 void MipsInstrInfo::AnalyzeCondBr(const MachineInstr *Inst, unsigned Opc,
81                                   MachineBasicBlock *&BB,
82                                   SmallVectorImpl<MachineOperand> &Cond) const {
83   assert(getAnalyzableBrOpc(Opc) && "Not an analyzable branch");
84   int NumOp = Inst->getNumExplicitOperands();
85 
86   // for both int and fp branches, the last explicit operand is the
87   // MBB.
88   BB = Inst->getOperand(NumOp-1).getMBB();
89   Cond.push_back(MachineOperand::CreateImm(Opc));
90 
91   for (int i = 0; i < NumOp-1; i++)
92     Cond.push_back(Inst->getOperand(i));
93 }
94 
95 bool MipsInstrInfo::analyzeBranch(MachineBasicBlock &MBB,
96                                   MachineBasicBlock *&TBB,
97                                   MachineBasicBlock *&FBB,
98                                   SmallVectorImpl<MachineOperand> &Cond,
99                                   bool AllowModify) const {
100   SmallVector<MachineInstr*, 2> BranchInstrs;
101   BranchType BT = analyzeBranch(MBB, TBB, FBB, Cond, AllowModify, BranchInstrs);
102 
103   return (BT == BT_None) || (BT == BT_Indirect);
104 }
105 
106 void MipsInstrInfo::BuildCondBr(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
107                                 const DebugLoc &DL,
108                                 ArrayRef<MachineOperand> Cond) const {
109   unsigned Opc = Cond[0].getImm();
110   const MCInstrDesc &MCID = get(Opc);
111   MachineInstrBuilder MIB = BuildMI(&MBB, DL, MCID);
112 
113   for (unsigned i = 1; i < Cond.size(); ++i) {
114     assert((Cond[i].isImm() || Cond[i].isReg()) &&
115            "Cannot copy operand for conditional branch!");
116     MIB.add(Cond[i]);
117   }
118   MIB.addMBB(TBB);
119 }
120 
121 unsigned MipsInstrInfo::insertBranch(MachineBasicBlock &MBB,
122                                      MachineBasicBlock *TBB,
123                                      MachineBasicBlock *FBB,
124                                      ArrayRef<MachineOperand> Cond,
125                                      const DebugLoc &DL,
126                                      int *BytesAdded) const {
127   // Shouldn't be a fall through.
128   assert(TBB && "insertBranch must not be told to insert a fallthrough");
129   assert(!BytesAdded && "code size not handled");
130 
131   // # of condition operands:
132   //  Unconditional branches: 0
133   //  Floating point branches: 1 (opc)
134   //  Int BranchZero: 2 (opc, reg)
135   //  Int Branch: 3 (opc, reg0, reg1)
136   assert((Cond.size() <= 3) &&
137          "# of Mips branch conditions must be <= 3!");
138 
139   // Two-way Conditional branch.
140   if (FBB) {
141     BuildCondBr(MBB, TBB, DL, Cond);
142     BuildMI(&MBB, DL, get(UncondBrOpc)).addMBB(FBB);
143     return 2;
144   }
145 
146   // One way branch.
147   // Unconditional branch.
148   if (Cond.empty())
149     BuildMI(&MBB, DL, get(UncondBrOpc)).addMBB(TBB);
150   else // Conditional branch.
151     BuildCondBr(MBB, TBB, DL, Cond);
152   return 1;
153 }
154 
155 unsigned MipsInstrInfo::removeBranch(MachineBasicBlock &MBB,
156                                      int *BytesRemoved) const {
157   assert(!BytesRemoved && "code size not handled");
158 
159   MachineBasicBlock::reverse_iterator I = MBB.rbegin(), REnd = MBB.rend();
160   unsigned removed;
161 
162   // Skip all the debug instructions.
163   while (I != REnd && I->isDebugValue())
164     ++I;
165 
166   if (I == REnd)
167     return 0;
168 
169   MachineBasicBlock::iterator FirstBr = ++I.getReverse();
170 
171   // Up to 2 branches are removed.
172   // Note that indirect branches are not removed.
173   for (removed = 0; I != REnd && removed < 2; ++I, ++removed)
174     if (!getAnalyzableBrOpc(I->getOpcode()))
175       break;
176 
177   MBB.erase((--I).getReverse(), FirstBr);
178 
179   return removed;
180 }
181 
182 /// reverseBranchCondition - Return the inverse opcode of the
183 /// specified Branch instruction.
184 bool MipsInstrInfo::reverseBranchCondition(
185     SmallVectorImpl<MachineOperand> &Cond) const {
186   assert( (Cond.size() && Cond.size() <= 3) &&
187           "Invalid Mips branch condition!");
188   Cond[0].setImm(getOppositeBranchOpc(Cond[0].getImm()));
189   return false;
190 }
191 
192 MipsInstrInfo::BranchType MipsInstrInfo::analyzeBranch(
193     MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB,
194     SmallVectorImpl<MachineOperand> &Cond, bool AllowModify,
195     SmallVectorImpl<MachineInstr *> &BranchInstrs) const {
196   MachineBasicBlock::reverse_iterator I = MBB.rbegin(), REnd = MBB.rend();
197 
198   // Skip all the debug instructions.
199   while (I != REnd && I->isDebugValue())
200     ++I;
201 
202   if (I == REnd || !isUnpredicatedTerminator(*I)) {
203     // This block ends with no branches (it just falls through to its succ).
204     // Leave TBB/FBB null.
205     TBB = FBB = nullptr;
206     return BT_NoBranch;
207   }
208 
209   MachineInstr *LastInst = &*I;
210   unsigned LastOpc = LastInst->getOpcode();
211   BranchInstrs.push_back(LastInst);
212 
213   // Not an analyzable branch (e.g., indirect jump).
214   if (!getAnalyzableBrOpc(LastOpc))
215     return LastInst->isIndirectBranch() ? BT_Indirect : BT_None;
216 
217   // Get the second to last instruction in the block.
218   unsigned SecondLastOpc = 0;
219   MachineInstr *SecondLastInst = nullptr;
220 
221   // Skip past any debug instruction to see if the second last actual
222   // is a branch.
223   ++I;
224   while (I != REnd && I->isDebugValue())
225     ++I;
226 
227   if (I != REnd) {
228     SecondLastInst = &*I;
229     SecondLastOpc = getAnalyzableBrOpc(SecondLastInst->getOpcode());
230 
231     // Not an analyzable branch (must be an indirect jump).
232     if (isUnpredicatedTerminator(*SecondLastInst) && !SecondLastOpc)
233       return BT_None;
234   }
235 
236   // If there is only one terminator instruction, process it.
237   if (!SecondLastOpc) {
238     // Unconditional branch.
239     if (LastInst->isUnconditionalBranch()) {
240       TBB = LastInst->getOperand(0).getMBB();
241       return BT_Uncond;
242     }
243 
244     // Conditional branch
245     AnalyzeCondBr(LastInst, LastOpc, TBB, Cond);
246     return BT_Cond;
247   }
248 
249   // If we reached here, there are two branches.
250   // If there are three terminators, we don't know what sort of block this is.
251   if (++I != REnd && isUnpredicatedTerminator(*I))
252     return BT_None;
253 
254   BranchInstrs.insert(BranchInstrs.begin(), SecondLastInst);
255 
256   // If second to last instruction is an unconditional branch,
257   // analyze it and remove the last instruction.
258   if (SecondLastInst->isUnconditionalBranch()) {
259     // Return if the last instruction cannot be removed.
260     if (!AllowModify)
261       return BT_None;
262 
263     TBB = SecondLastInst->getOperand(0).getMBB();
264     LastInst->eraseFromParent();
265     BranchInstrs.pop_back();
266     return BT_Uncond;
267   }
268 
269   // Conditional branch followed by an unconditional branch.
270   // The last one must be unconditional.
271   if (!LastInst->isUnconditionalBranch())
272     return BT_None;
273 
274   AnalyzeCondBr(SecondLastInst, SecondLastOpc, TBB, Cond);
275   FBB = LastInst->getOperand(0).getMBB();
276 
277   return BT_CondUncond;
278 }
279 
280 /// Return the corresponding compact (no delay slot) form of a branch.
281 unsigned MipsInstrInfo::getEquivalentCompactForm(
282     const MachineBasicBlock::iterator I) const {
283   unsigned Opcode = I->getOpcode();
284   bool canUseShortMicroMipsCTI = false;
285 
286   if (Subtarget.inMicroMipsMode()) {
287     switch (Opcode) {
288     case Mips::BNE:
289     case Mips::BNE_MM:
290     case Mips::BEQ:
291     case Mips::BEQ_MM:
292     // microMIPS has NE,EQ branches that do not have delay slots provided one
293     // of the operands is zero.
294       if (I->getOperand(1).getReg() == Subtarget.getABI().GetZeroReg())
295         canUseShortMicroMipsCTI = true;
296       break;
297     // For microMIPS the PseudoReturn and PseudoIndirectBranch are always
298     // expanded to JR_MM, so they can be replaced with JRC16_MM.
299     case Mips::JR:
300     case Mips::PseudoReturn:
301     case Mips::PseudoIndirectBranch:
302     case Mips::TAILCALLREG:
303       canUseShortMicroMipsCTI = true;
304       break;
305     }
306   }
307 
308   // MIPSR6 forbids both operands being the zero register.
309   if (Subtarget.hasMips32r6() && (I->getNumOperands() > 1) &&
310       (I->getOperand(0).isReg() &&
311        (I->getOperand(0).getReg() == Mips::ZERO ||
312         I->getOperand(0).getReg() == Mips::ZERO_64)) &&
313       (I->getOperand(1).isReg() &&
314        (I->getOperand(1).getReg() == Mips::ZERO ||
315         I->getOperand(1).getReg() == Mips::ZERO_64)))
316     return 0;
317 
318   if (Subtarget.hasMips32r6() || canUseShortMicroMipsCTI) {
319     switch (Opcode) {
320     case Mips::B:
321       return Mips::BC;
322     case Mips::BAL:
323       return Mips::BALC;
324     case Mips::BEQ:
325     case Mips::BEQ_MM:
326       if (canUseShortMicroMipsCTI)
327         return Mips::BEQZC_MM;
328       else if (I->getOperand(0).getReg() == I->getOperand(1).getReg())
329         return 0;
330       return Mips::BEQC;
331     case Mips::BNE:
332     case Mips::BNE_MM:
333       if (canUseShortMicroMipsCTI)
334         return Mips::BNEZC_MM;
335       else if (I->getOperand(0).getReg() == I->getOperand(1).getReg())
336         return 0;
337       return Mips::BNEC;
338     case Mips::BGE:
339       if (I->getOperand(0).getReg() == I->getOperand(1).getReg())
340         return 0;
341       return Mips::BGEC;
342     case Mips::BGEU:
343       if (I->getOperand(0).getReg() == I->getOperand(1).getReg())
344         return 0;
345       return Mips::BGEUC;
346     case Mips::BGEZ:
347       return Mips::BGEZC;
348     case Mips::BGTZ:
349       return Mips::BGTZC;
350     case Mips::BLEZ:
351       return Mips::BLEZC;
352     case Mips::BLT:
353       if (I->getOperand(0).getReg() == I->getOperand(1).getReg())
354         return 0;
355       return Mips::BLTC;
356     case Mips::BLTU:
357       if (I->getOperand(0).getReg() == I->getOperand(1).getReg())
358         return 0;
359       return Mips::BLTUC;
360     case Mips::BLTZ:
361       return Mips::BLTZC;
362     case Mips::BEQ64:
363       if (I->getOperand(0).getReg() == I->getOperand(1).getReg())
364         return 0;
365       return Mips::BEQC64;
366     case Mips::BNE64:
367       if (I->getOperand(0).getReg() == I->getOperand(1).getReg())
368         return 0;
369       return Mips::BNEC64;
370     case Mips::BGTZ64:
371       return Mips::BGTZC64;
372     case Mips::BGEZ64:
373       return Mips::BGEZC64;
374     case Mips::BLTZ64:
375       return Mips::BLTZC64;
376     case Mips::BLEZ64:
377       return Mips::BLEZC64;
378     // For MIPSR6, the instruction 'jic' can be used for these cases. Some
379     // tools will accept 'jrc reg' as an alias for 'jic 0, $reg'.
380     case Mips::JR:
381     case Mips::PseudoReturn:
382     case Mips::PseudoIndirectBranch:
383     case Mips::TAILCALLREG:
384       if (canUseShortMicroMipsCTI)
385         return Mips::JRC16_MM;
386       return Mips::JIC;
387     case Mips::JALRPseudo:
388       return Mips::JIALC;
389     case Mips::JR64:
390     case Mips::PseudoReturn64:
391     case Mips::PseudoIndirectBranch64:
392     case Mips::TAILCALLREG64:
393       return Mips::JIC64;
394     case Mips::JALR64Pseudo:
395       return Mips::JIALC64;
396     default:
397       return 0;
398     }
399   }
400 
401   return 0;
402 }
403 
404 /// Predicate for distingushing between control transfer instructions and all
405 /// other instructions for handling forbidden slots. Consider inline assembly
406 /// as unsafe as well.
407 bool MipsInstrInfo::SafeInForbiddenSlot(const MachineInstr &MI) const {
408   if (MI.isInlineAsm())
409     return false;
410 
411   return (MI.getDesc().TSFlags & MipsII::IsCTI) == 0;
412 }
413 
414 /// Predicate for distingushing instructions that have forbidden slots.
415 bool MipsInstrInfo::HasForbiddenSlot(const MachineInstr &MI) const {
416   return (MI.getDesc().TSFlags & MipsII::HasForbiddenSlot) != 0;
417 }
418 
419 /// Return the number of bytes of code the specified instruction may be.
420 unsigned MipsInstrInfo::getInstSizeInBytes(const MachineInstr &MI) const {
421   switch (MI.getOpcode()) {
422   default:
423     return MI.getDesc().getSize();
424   case  TargetOpcode::INLINEASM: {       // Inline Asm: Variable size.
425     const MachineFunction *MF = MI.getParent()->getParent();
426     const char *AsmStr = MI.getOperand(0).getSymbolName();
427     return getInlineAsmLength(AsmStr, *MF->getTarget().getMCAsmInfo());
428   }
429   case Mips::CONSTPOOL_ENTRY:
430     // If this machine instr is a constant pool entry, its size is recorded as
431     // operand #2.
432     return MI.getOperand(2).getImm();
433   }
434 }
435 
436 MachineInstrBuilder
437 MipsInstrInfo::genInstrWithNewOpc(unsigned NewOpc,
438                                   MachineBasicBlock::iterator I) const {
439   MachineInstrBuilder MIB;
440 
441   // Certain branches have two forms: e.g beq $1, $zero, dest vs beqz $1, dest
442   // Pick the zero form of the branch for readable assembly and for greater
443   // branch distance in non-microMIPS mode.
444   // Additional MIPSR6 does not permit the use of register $zero for compact
445   // branches.
446   // FIXME: Certain atomic sequences on mips64 generate 32bit references to
447   // Mips::ZERO, which is incorrect. This test should be updated to use
448   // Subtarget.getABI().GetZeroReg() when those atomic sequences and others
449   // are fixed.
450   int ZeroOperandPosition = -1;
451   bool BranchWithZeroOperand = false;
452   if (I->isBranch() && !I->isPseudo()) {
453     auto TRI = I->getParent()->getParent()->getSubtarget().getRegisterInfo();
454     ZeroOperandPosition = I->findRegisterUseOperandIdx(Mips::ZERO, false, TRI);
455     BranchWithZeroOperand = ZeroOperandPosition != -1;
456   }
457 
458   if (BranchWithZeroOperand) {
459     switch (NewOpc) {
460     case Mips::BEQC:
461       NewOpc = Mips::BEQZC;
462       break;
463     case Mips::BNEC:
464       NewOpc = Mips::BNEZC;
465       break;
466     case Mips::BGEC:
467       NewOpc = Mips::BGEZC;
468       break;
469     case Mips::BLTC:
470       NewOpc = Mips::BLTZC;
471       break;
472     case Mips::BEQC64:
473       NewOpc = Mips::BEQZC64;
474       break;
475     case Mips::BNEC64:
476       NewOpc = Mips::BNEZC64;
477       break;
478     }
479   }
480 
481   MIB = BuildMI(*I->getParent(), I, I->getDebugLoc(), get(NewOpc));
482 
483   // For MIPSR6 JI*C requires an immediate 0 as an operand, JIALC(64) an
484   // immediate 0 as an operand and requires the removal of it's %RA<imp-def>
485   // implicit operand as copying the implicit operations of the instructio we're
486   // looking at will give us the correct flags.
487   if (NewOpc == Mips::JIC || NewOpc == Mips::JIALC || NewOpc == Mips::JIC64 ||
488       NewOpc == Mips::JIALC64) {
489 
490     if (NewOpc == Mips::JIALC || NewOpc == Mips::JIALC64)
491       MIB->RemoveOperand(0);
492 
493     for (unsigned J = 0, E = I->getDesc().getNumOperands(); J < E; ++J) {
494       MIB.add(I->getOperand(J));
495     }
496 
497     MIB.addImm(0);
498 
499   } else {
500     for (unsigned J = 0, E = I->getDesc().getNumOperands(); J < E; ++J) {
501       if (BranchWithZeroOperand && (unsigned)ZeroOperandPosition == J)
502         continue;
503 
504       MIB.add(I->getOperand(J));
505     }
506   }
507 
508   MIB.copyImplicitOps(*I);
509 
510   MIB.setMemRefs(I->memoperands_begin(), I->memoperands_end());
511   return MIB;
512 }
513 
514 bool MipsInstrInfo::findCommutedOpIndices(MachineInstr &MI, unsigned &SrcOpIdx1,
515                                           unsigned &SrcOpIdx2) const {
516   assert(!MI.isBundle() &&
517          "TargetInstrInfo::findCommutedOpIndices() can't handle bundles");
518 
519   const MCInstrDesc &MCID = MI.getDesc();
520   if (!MCID.isCommutable())
521     return false;
522 
523   switch (MI.getOpcode()) {
524   case Mips::DPADD_U_H:
525   case Mips::DPADD_U_W:
526   case Mips::DPADD_U_D:
527   case Mips::DPADD_S_H:
528   case Mips::DPADD_S_W:
529   case Mips::DPADD_S_D:
530     // The first operand is both input and output, so it should not commute
531     if (!fixCommutedOpIndices(SrcOpIdx1, SrcOpIdx2, 2, 3))
532       return false;
533 
534     if (!MI.getOperand(SrcOpIdx1).isReg() || !MI.getOperand(SrcOpIdx2).isReg())
535       return false;
536     return true;
537   }
538   return TargetInstrInfo::findCommutedOpIndices(MI, SrcOpIdx1, SrcOpIdx2);
539 }
540 
541 // ins, ext, dext*, dins have the following constraints:
542 // 0 <= pos      <  X
543 // 0 <  size     <= X
544 // 0 <  pos+size <= x
545 //
546 // dinsm and dinsm have the following contraints:
547 // 0 <= pos      <  X
548 // 0 <= size     <= X
549 // 0 <  pos+size <= x
550 
551 static bool verifyInsExtInstruction(const MachineInstr &MI, StringRef &ErrInfo,
552                                     const int64_t PosLow, const int64_t PosHigh,
553                                     const int64_t SizeLow,
554                                     const int64_t SizeHigh,
555                                     const int64_t BothLow,
556                                     const int64_t BothHigh) {
557   MachineOperand MOPos = MI.getOperand(2);
558   if (!MOPos.isImm()) {
559     ErrInfo = "Position is not an immediate!";
560     return false;
561   }
562   int64_t Pos = MOPos.getImm();
563   if (!((PosLow <= Pos) && (Pos < PosHigh))) {
564     ErrInfo = "Position operand is out of range!";
565     return false;
566   }
567 
568   MachineOperand MOSize = MI.getOperand(3);
569   if (!MOSize.isImm()) {
570     ErrInfo = "Size operand is not an immediate!";
571     return false;
572   }
573   int64_t Size = MOSize.getImm();
574   if (!((SizeLow < Size) && (Size <= SizeHigh))) {
575     ErrInfo = "Size operand is out of range!";
576     return false;
577   }
578 
579   if (!((BothLow < (Pos + Size)) && ((Pos + Size) <= BothHigh))) {
580     ErrInfo = "Position + Size is out of range!";
581     return false;
582   }
583 
584   return true;
585 }
586 
587 //  Perform target specific instruction verification.
588 bool MipsInstrInfo::verifyInstruction(const MachineInstr &MI,
589                                       StringRef &ErrInfo) const {
590   // Verify that ins and ext instructions are well formed.
591   switch (MI.getOpcode()) {
592     case Mips::EXT:
593     case Mips::EXT_MM:
594     case Mips::INS:
595     case Mips::INS_MM:
596     case Mips::DINS:
597     case Mips::DINS_MM64R6:
598       return verifyInsExtInstruction(MI, ErrInfo, 0, 32, 0, 32, 0, 32);
599     case Mips::DINSM:
600     case Mips::DINSM_MM64R6:
601       // The ISA spec has a subtle difference here in that it says:
602       //  2 <= size <= 64 for 'dinsm', so we change the bounds so that it
603       // is in line with the rest of instructions.
604       return verifyInsExtInstruction(MI, ErrInfo, 0, 32, 1, 64, 32, 64);
605     case Mips::DINSU:
606     case Mips::DINSU_MM64R6:
607       // The ISA spec has a subtle difference here in that it says:
608       //  2 <= size <= 64 for 'dinsm', so we change the bounds so that it
609       // is in line with the rest of instructions.
610       return verifyInsExtInstruction(MI, ErrInfo, 32, 64, 1, 32, 32, 64);
611     case Mips::DEXT:
612     case Mips::DEXT_MM64R6:
613       return verifyInsExtInstruction(MI, ErrInfo, 0, 32, 0, 32, 0, 63);
614     case Mips::DEXTM:
615     case Mips::DEXTM_MM64R6:
616       return verifyInsExtInstruction(MI, ErrInfo, 0, 32, 32, 64, 32, 64);
617     case Mips::DEXTU:
618     case Mips::DEXTU_MM64R6:
619       return verifyInsExtInstruction(MI, ErrInfo, 32, 64, 0, 32, 32, 64);
620     default:
621       return true;
622   }
623 
624   return true;
625 }
626 
627 std::pair<unsigned, unsigned>
628 MipsInstrInfo::decomposeMachineOperandsTargetFlags(unsigned TF) const {
629   return std::make_pair(TF, 0u);
630 }
631 
632 ArrayRef<std::pair<unsigned, const char*>>
633 MipsInstrInfo::getSerializableDirectMachineOperandTargetFlags() const {
634  using namespace MipsII;
635 
636  static const std::pair<unsigned, const char*> Flags[] = {
637     {MO_GOT,          "mips-got"},
638     {MO_GOT_CALL,     "mips-got-call"},
639     {MO_GPREL,        "mips-gprel"},
640     {MO_ABS_HI,       "mips-abs-hi"},
641     {MO_ABS_LO,       "mips-abs-lo"},
642     {MO_TLSGD,        "mips-tlsgd"},
643     {MO_TLSLDM,       "mips-tlsldm"},
644     {MO_DTPREL_HI,    "mips-dtprel-hi"},
645     {MO_DTPREL_LO,    "mips-dtprel-lo"},
646     {MO_GOTTPREL,     "mips-gottprel"},
647     {MO_TPREL_HI,     "mips-tprel-hi"},
648     {MO_TPREL_LO,     "mips-tprel-lo"},
649     {MO_GPOFF_HI,     "mips-gpoff-hi"},
650     {MO_GPOFF_LO,     "mips-gpoff-lo"},
651     {MO_GOT_DISP,     "mips-got-disp"},
652     {MO_GOT_PAGE,     "mips-got-page"},
653     {MO_GOT_OFST,     "mips-got-ofst"},
654     {MO_HIGHER,       "mips-higher"},
655     {MO_HIGHEST,      "mips-highest"},
656     {MO_GOT_HI16,     "mips-got-hi16"},
657     {MO_GOT_LO16,     "mips-got-lo16"},
658     {MO_CALL_HI16,    "mips-call-hi16"},
659     {MO_CALL_LO16,    "mips-call-lo16"}
660   };
661   return makeArrayRef(Flags);
662 }
663