1 //===- MipsInstrInfo.cpp - Mips Instruction Information -------------------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file contains the Mips implementation of the TargetInstrInfo class.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #include "MipsInstrInfo.h"
15 #include "MCTargetDesc/MipsBaseInfo.h"
16 #include "MCTargetDesc/MipsMCTargetDesc.h"
17 #include "MipsSubtarget.h"
18 #include "llvm/ADT/SmallVector.h"
19 #include "llvm/CodeGen/MachineBasicBlock.h"
20 #include "llvm/CodeGen/MachineFrameInfo.h"
21 #include "llvm/CodeGen/MachineFunction.h"
22 #include "llvm/CodeGen/MachineInstr.h"
23 #include "llvm/CodeGen/MachineInstrBuilder.h"
24 #include "llvm/CodeGen/MachineOperand.h"
25 #include "llvm/CodeGen/TargetOpcodes.h"
26 #include "llvm/CodeGen/TargetSubtargetInfo.h"
27 #include "llvm/IR/DebugLoc.h"
28 #include "llvm/MC/MCInstrDesc.h"
29 #include "llvm/Target/TargetMachine.h"
30 #include <cassert>
31 
32 using namespace llvm;
33 
34 #define GET_INSTRINFO_CTOR_DTOR
35 #include "MipsGenInstrInfo.inc"
36 
37 // Pin the vtable to this file.
38 void MipsInstrInfo::anchor() {}
39 
40 MipsInstrInfo::MipsInstrInfo(const MipsSubtarget &STI, unsigned UncondBr)
41     : MipsGenInstrInfo(Mips::ADJCALLSTACKDOWN, Mips::ADJCALLSTACKUP),
42       Subtarget(STI), UncondBrOpc(UncondBr) {}
43 
44 const MipsInstrInfo *MipsInstrInfo::create(MipsSubtarget &STI) {
45   if (STI.inMips16Mode())
46     return createMips16InstrInfo(STI);
47 
48   return createMipsSEInstrInfo(STI);
49 }
50 
51 bool MipsInstrInfo::isZeroImm(const MachineOperand &op) const {
52   return op.isImm() && op.getImm() == 0;
53 }
54 
55 /// insertNoop - If data hazard condition is found insert the target nop
56 /// instruction.
57 // FIXME: This appears to be dead code.
58 void MipsInstrInfo::
59 insertNoop(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI) const
60 {
61   DebugLoc DL;
62   BuildMI(MBB, MI, DL, get(Mips::NOP));
63 }
64 
65 MachineMemOperand *
66 MipsInstrInfo::GetMemOperand(MachineBasicBlock &MBB, int FI,
67                              MachineMemOperand::Flags Flags) const {
68   MachineFunction &MF = *MBB.getParent();
69   MachineFrameInfo &MFI = MF.getFrameInfo();
70   unsigned Align = MFI.getObjectAlignment(FI);
71 
72   return MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(MF, FI),
73                                  Flags, MFI.getObjectSize(FI), Align);
74 }
75 
76 //===----------------------------------------------------------------------===//
77 // Branch Analysis
78 //===----------------------------------------------------------------------===//
79 
80 void MipsInstrInfo::AnalyzeCondBr(const MachineInstr *Inst, unsigned Opc,
81                                   MachineBasicBlock *&BB,
82                                   SmallVectorImpl<MachineOperand> &Cond) const {
83   assert(getAnalyzableBrOpc(Opc) && "Not an analyzable branch");
84   int NumOp = Inst->getNumExplicitOperands();
85 
86   // for both int and fp branches, the last explicit operand is the
87   // MBB.
88   BB = Inst->getOperand(NumOp-1).getMBB();
89   Cond.push_back(MachineOperand::CreateImm(Opc));
90 
91   for (int i = 0; i < NumOp-1; i++)
92     Cond.push_back(Inst->getOperand(i));
93 }
94 
95 bool MipsInstrInfo::analyzeBranch(MachineBasicBlock &MBB,
96                                   MachineBasicBlock *&TBB,
97                                   MachineBasicBlock *&FBB,
98                                   SmallVectorImpl<MachineOperand> &Cond,
99                                   bool AllowModify) const {
100   SmallVector<MachineInstr*, 2> BranchInstrs;
101   BranchType BT = analyzeBranch(MBB, TBB, FBB, Cond, AllowModify, BranchInstrs);
102 
103   return (BT == BT_None) || (BT == BT_Indirect);
104 }
105 
106 void MipsInstrInfo::BuildCondBr(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
107                                 const DebugLoc &DL,
108                                 ArrayRef<MachineOperand> Cond) const {
109   unsigned Opc = Cond[0].getImm();
110   const MCInstrDesc &MCID = get(Opc);
111   MachineInstrBuilder MIB = BuildMI(&MBB, DL, MCID);
112 
113   for (unsigned i = 1; i < Cond.size(); ++i) {
114     assert((Cond[i].isImm() || Cond[i].isReg()) &&
115            "Cannot copy operand for conditional branch!");
116     MIB.add(Cond[i]);
117   }
118   MIB.addMBB(TBB);
119 }
120 
121 unsigned MipsInstrInfo::insertBranch(MachineBasicBlock &MBB,
122                                      MachineBasicBlock *TBB,
123                                      MachineBasicBlock *FBB,
124                                      ArrayRef<MachineOperand> Cond,
125                                      const DebugLoc &DL,
126                                      int *BytesAdded) const {
127   // Shouldn't be a fall through.
128   assert(TBB && "insertBranch must not be told to insert a fallthrough");
129   assert(!BytesAdded && "code size not handled");
130 
131   // # of condition operands:
132   //  Unconditional branches: 0
133   //  Floating point branches: 1 (opc)
134   //  Int BranchZero: 2 (opc, reg)
135   //  Int Branch: 3 (opc, reg0, reg1)
136   assert((Cond.size() <= 3) &&
137          "# of Mips branch conditions must be <= 3!");
138 
139   // Two-way Conditional branch.
140   if (FBB) {
141     BuildCondBr(MBB, TBB, DL, Cond);
142     BuildMI(&MBB, DL, get(UncondBrOpc)).addMBB(FBB);
143     return 2;
144   }
145 
146   // One way branch.
147   // Unconditional branch.
148   if (Cond.empty())
149     BuildMI(&MBB, DL, get(UncondBrOpc)).addMBB(TBB);
150   else // Conditional branch.
151     BuildCondBr(MBB, TBB, DL, Cond);
152   return 1;
153 }
154 
155 unsigned MipsInstrInfo::removeBranch(MachineBasicBlock &MBB,
156                                      int *BytesRemoved) const {
157   assert(!BytesRemoved && "code size not handled");
158 
159   MachineBasicBlock::reverse_iterator I = MBB.rbegin(), REnd = MBB.rend();
160   unsigned removed = 0;
161 
162   // Up to 2 branches are removed.
163   // Note that indirect branches are not removed.
164   while (I != REnd && removed < 2) {
165     // Skip past debug instructions.
166     if (I->isDebugInstr()) {
167       ++I;
168       continue;
169     }
170     if (!getAnalyzableBrOpc(I->getOpcode()))
171       break;
172     // Remove the branch.
173     I->eraseFromParent();
174     I = MBB.rbegin();
175     ++removed;
176   }
177 
178   return removed;
179 }
180 
181 /// reverseBranchCondition - Return the inverse opcode of the
182 /// specified Branch instruction.
183 bool MipsInstrInfo::reverseBranchCondition(
184     SmallVectorImpl<MachineOperand> &Cond) const {
185   assert( (Cond.size() && Cond.size() <= 3) &&
186           "Invalid Mips branch condition!");
187   Cond[0].setImm(getOppositeBranchOpc(Cond[0].getImm()));
188   return false;
189 }
190 
191 MipsInstrInfo::BranchType MipsInstrInfo::analyzeBranch(
192     MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB,
193     SmallVectorImpl<MachineOperand> &Cond, bool AllowModify,
194     SmallVectorImpl<MachineInstr *> &BranchInstrs) const {
195   MachineBasicBlock::reverse_iterator I = MBB.rbegin(), REnd = MBB.rend();
196 
197   // Skip all the debug instructions.
198   while (I != REnd && I->isDebugInstr())
199     ++I;
200 
201   if (I == REnd || !isUnpredicatedTerminator(*I)) {
202     // This block ends with no branches (it just falls through to its succ).
203     // Leave TBB/FBB null.
204     TBB = FBB = nullptr;
205     return BT_NoBranch;
206   }
207 
208   MachineInstr *LastInst = &*I;
209   unsigned LastOpc = LastInst->getOpcode();
210   BranchInstrs.push_back(LastInst);
211 
212   // Not an analyzable branch (e.g., indirect jump).
213   if (!getAnalyzableBrOpc(LastOpc))
214     return LastInst->isIndirectBranch() ? BT_Indirect : BT_None;
215 
216   // Get the second to last instruction in the block.
217   unsigned SecondLastOpc = 0;
218   MachineInstr *SecondLastInst = nullptr;
219 
220   // Skip past any debug instruction to see if the second last actual
221   // is a branch.
222   ++I;
223   while (I != REnd && I->isDebugInstr())
224     ++I;
225 
226   if (I != REnd) {
227     SecondLastInst = &*I;
228     SecondLastOpc = getAnalyzableBrOpc(SecondLastInst->getOpcode());
229 
230     // Not an analyzable branch (must be an indirect jump).
231     if (isUnpredicatedTerminator(*SecondLastInst) && !SecondLastOpc)
232       return BT_None;
233   }
234 
235   // If there is only one terminator instruction, process it.
236   if (!SecondLastOpc) {
237     // Unconditional branch.
238     if (LastInst->isUnconditionalBranch()) {
239       TBB = LastInst->getOperand(0).getMBB();
240       return BT_Uncond;
241     }
242 
243     // Conditional branch
244     AnalyzeCondBr(LastInst, LastOpc, TBB, Cond);
245     return BT_Cond;
246   }
247 
248   // If we reached here, there are two branches.
249   // If there are three terminators, we don't know what sort of block this is.
250   if (++I != REnd && isUnpredicatedTerminator(*I))
251     return BT_None;
252 
253   BranchInstrs.insert(BranchInstrs.begin(), SecondLastInst);
254 
255   // If second to last instruction is an unconditional branch,
256   // analyze it and remove the last instruction.
257   if (SecondLastInst->isUnconditionalBranch()) {
258     // Return if the last instruction cannot be removed.
259     if (!AllowModify)
260       return BT_None;
261 
262     TBB = SecondLastInst->getOperand(0).getMBB();
263     LastInst->eraseFromParent();
264     BranchInstrs.pop_back();
265     return BT_Uncond;
266   }
267 
268   // Conditional branch followed by an unconditional branch.
269   // The last one must be unconditional.
270   if (!LastInst->isUnconditionalBranch())
271     return BT_None;
272 
273   AnalyzeCondBr(SecondLastInst, SecondLastOpc, TBB, Cond);
274   FBB = LastInst->getOperand(0).getMBB();
275 
276   return BT_CondUncond;
277 }
278 
279 bool MipsInstrInfo::isBranchOffsetInRange(unsigned BranchOpc, int64_t BrOffset) const {
280   switch (BranchOpc) {
281   case Mips::B:
282   case Mips::BAL:
283   case Mips::BAL_BR:
284   case Mips::BAL_BR_MM:
285   case Mips::BC1F:
286   case Mips::BC1FL:
287   case Mips::BC1T:
288   case Mips::BC1TL:
289   case Mips::BEQ:     case Mips::BEQ64:
290   case Mips::BEQL:
291   case Mips::BGEZ:    case Mips::BGEZ64:
292   case Mips::BGEZL:
293   case Mips::BGEZAL:
294   case Mips::BGEZALL:
295   case Mips::BGTZ:    case Mips::BGTZ64:
296   case Mips::BGTZL:
297   case Mips::BLEZ:    case Mips::BLEZ64:
298   case Mips::BLEZL:
299   case Mips::BLTZ:    case Mips::BLTZ64:
300   case Mips::BLTZL:
301   case Mips::BLTZAL:
302   case Mips::BLTZALL:
303   case Mips::BNE:     case Mips::BNE64:
304   case Mips::BNEL:
305     return isInt<18>(BrOffset);
306 
307   // microMIPSr3 branches
308   case Mips::B_MM:
309   case Mips::BC1F_MM:
310   case Mips::BC1T_MM:
311   case Mips::BEQ_MM:
312   case Mips::BGEZ_MM:
313   case Mips::BGEZAL_MM:
314   case Mips::BGTZ_MM:
315   case Mips::BLEZ_MM:
316   case Mips::BLTZ_MM:
317   case Mips::BLTZAL_MM:
318   case Mips::BNE_MM:
319   case Mips::BEQZC_MM:
320   case Mips::BNEZC_MM:
321     return isInt<17>(BrOffset);
322 
323   // microMIPSR3 short branches.
324   case Mips::B16_MM:
325     return isInt<11>(BrOffset);
326 
327   case Mips::BEQZ16_MM:
328   case Mips::BNEZ16_MM:
329     return isInt<8>(BrOffset);
330 
331   // MIPSR6 branches.
332   case Mips::BALC:
333   case Mips::BC:
334     return isInt<28>(BrOffset);
335 
336   case Mips::BC1EQZ:
337   case Mips::BC1NEZ:
338   case Mips::BC2EQZ:
339   case Mips::BC2NEZ:
340   case Mips::BEQC:   case Mips::BEQC64:
341   case Mips::BNEC:   case Mips::BNEC64:
342   case Mips::BGEC:   case Mips::BGEC64:
343   case Mips::BGEUC:  case Mips::BGEUC64:
344   case Mips::BGEZC:  case Mips::BGEZC64:
345   case Mips::BGTZC:  case Mips::BGTZC64:
346   case Mips::BLEZC:  case Mips::BLEZC64:
347   case Mips::BLTC:   case Mips::BLTC64:
348   case Mips::BLTUC:  case Mips::BLTUC64:
349   case Mips::BLTZC:  case Mips::BLTZC64:
350   case Mips::BNVC:
351   case Mips::BOVC:
352   case Mips::BGEZALC:
353   case Mips::BEQZALC:
354   case Mips::BGTZALC:
355   case Mips::BLEZALC:
356   case Mips::BLTZALC:
357   case Mips::BNEZALC:
358     return isInt<18>(BrOffset);
359 
360   case Mips::BEQZC:  case Mips::BEQZC64:
361   case Mips::BNEZC:  case Mips::BNEZC64:
362     return isInt<23>(BrOffset);
363 
364   // microMIPSR6 branches
365   case Mips::BC16_MMR6:
366     return isInt<11>(BrOffset);
367 
368   case Mips::BEQZC16_MMR6:
369   case Mips::BNEZC16_MMR6:
370     return isInt<8>(BrOffset);
371 
372   case Mips::BALC_MMR6:
373   case Mips::BC_MMR6:
374     return isInt<27>(BrOffset);
375 
376   case Mips::BC1EQZC_MMR6:
377   case Mips::BC1NEZC_MMR6:
378   case Mips::BC2EQZC_MMR6:
379   case Mips::BC2NEZC_MMR6:
380   case Mips::BGEZALC_MMR6:
381   case Mips::BEQZALC_MMR6:
382   case Mips::BGTZALC_MMR6:
383   case Mips::BLEZALC_MMR6:
384   case Mips::BLTZALC_MMR6:
385   case Mips::BNEZALC_MMR6:
386   case Mips::BNVC_MMR6:
387   case Mips::BOVC_MMR6:
388     return isInt<17>(BrOffset);
389 
390   case Mips::BEQC_MMR6:
391   case Mips::BNEC_MMR6:
392   case Mips::BGEC_MMR6:
393   case Mips::BGEUC_MMR6:
394   case Mips::BGEZC_MMR6:
395   case Mips::BGTZC_MMR6:
396   case Mips::BLEZC_MMR6:
397   case Mips::BLTC_MMR6:
398   case Mips::BLTUC_MMR6:
399   case Mips::BLTZC_MMR6:
400     return isInt<18>(BrOffset);
401 
402   case Mips::BEQZC_MMR6:
403   case Mips::BNEZC_MMR6:
404     return isInt<23>(BrOffset);
405 
406   // DSP branches.
407   case Mips::BPOSGE32:
408     return isInt<18>(BrOffset);
409   case Mips::BPOSGE32_MM:
410   case Mips::BPOSGE32C_MMR3:
411     return isInt<17>(BrOffset);
412 
413   // cnMIPS branches.
414   case Mips::BBIT0:
415   case Mips::BBIT032:
416   case Mips::BBIT1:
417   case Mips::BBIT132:
418     return isInt<18>(BrOffset);
419 
420   // MSA branches.
421   case Mips::BZ_B:
422   case Mips::BZ_H:
423   case Mips::BZ_W:
424   case Mips::BZ_D:
425   case Mips::BZ_V:
426   case Mips::BNZ_B:
427   case Mips::BNZ_H:
428   case Mips::BNZ_W:
429   case Mips::BNZ_D:
430   case Mips::BNZ_V:
431     return isInt<18>(BrOffset);
432   }
433 
434   llvm_unreachable("Unknown branch instruction!");
435 }
436 
437 
438 /// Return the corresponding compact (no delay slot) form of a branch.
439 unsigned MipsInstrInfo::getEquivalentCompactForm(
440     const MachineBasicBlock::iterator I) const {
441   unsigned Opcode = I->getOpcode();
442   bool canUseShortMicroMipsCTI = false;
443 
444   if (Subtarget.inMicroMipsMode()) {
445     switch (Opcode) {
446     case Mips::BNE:
447     case Mips::BNE_MM:
448     case Mips::BEQ:
449     case Mips::BEQ_MM:
450     // microMIPS has NE,EQ branches that do not have delay slots provided one
451     // of the operands is zero.
452       if (I->getOperand(1).getReg() == Subtarget.getABI().GetZeroReg())
453         canUseShortMicroMipsCTI = true;
454       break;
455     // For microMIPS the PseudoReturn and PseudoIndirectBranch are always
456     // expanded to JR_MM, so they can be replaced with JRC16_MM.
457     case Mips::JR:
458     case Mips::PseudoReturn:
459     case Mips::PseudoIndirectBranch:
460       canUseShortMicroMipsCTI = true;
461       break;
462     }
463   }
464 
465   // MIPSR6 forbids both operands being the zero register.
466   if (Subtarget.hasMips32r6() && (I->getNumOperands() > 1) &&
467       (I->getOperand(0).isReg() &&
468        (I->getOperand(0).getReg() == Mips::ZERO ||
469         I->getOperand(0).getReg() == Mips::ZERO_64)) &&
470       (I->getOperand(1).isReg() &&
471        (I->getOperand(1).getReg() == Mips::ZERO ||
472         I->getOperand(1).getReg() == Mips::ZERO_64)))
473     return 0;
474 
475   if (Subtarget.hasMips32r6() || canUseShortMicroMipsCTI) {
476     switch (Opcode) {
477     case Mips::B:
478       return Mips::BC;
479     case Mips::BAL:
480       return Mips::BALC;
481     case Mips::BEQ:
482     case Mips::BEQ_MM:
483       if (canUseShortMicroMipsCTI)
484         return Mips::BEQZC_MM;
485       else if (I->getOperand(0).getReg() == I->getOperand(1).getReg())
486         return 0;
487       return Mips::BEQC;
488     case Mips::BNE:
489     case Mips::BNE_MM:
490       if (canUseShortMicroMipsCTI)
491         return Mips::BNEZC_MM;
492       else if (I->getOperand(0).getReg() == I->getOperand(1).getReg())
493         return 0;
494       return Mips::BNEC;
495     case Mips::BGE:
496       if (I->getOperand(0).getReg() == I->getOperand(1).getReg())
497         return 0;
498       return Mips::BGEC;
499     case Mips::BGEU:
500       if (I->getOperand(0).getReg() == I->getOperand(1).getReg())
501         return 0;
502       return Mips::BGEUC;
503     case Mips::BGEZ:
504       return Mips::BGEZC;
505     case Mips::BGTZ:
506       return Mips::BGTZC;
507     case Mips::BLEZ:
508       return Mips::BLEZC;
509     case Mips::BLT:
510       if (I->getOperand(0).getReg() == I->getOperand(1).getReg())
511         return 0;
512       return Mips::BLTC;
513     case Mips::BLTU:
514       if (I->getOperand(0).getReg() == I->getOperand(1).getReg())
515         return 0;
516       return Mips::BLTUC;
517     case Mips::BLTZ:
518       return Mips::BLTZC;
519     case Mips::BEQ64:
520       if (I->getOperand(0).getReg() == I->getOperand(1).getReg())
521         return 0;
522       return Mips::BEQC64;
523     case Mips::BNE64:
524       if (I->getOperand(0).getReg() == I->getOperand(1).getReg())
525         return 0;
526       return Mips::BNEC64;
527     case Mips::BGTZ64:
528       return Mips::BGTZC64;
529     case Mips::BGEZ64:
530       return Mips::BGEZC64;
531     case Mips::BLTZ64:
532       return Mips::BLTZC64;
533     case Mips::BLEZ64:
534       return Mips::BLEZC64;
535     // For MIPSR6, the instruction 'jic' can be used for these cases. Some
536     // tools will accept 'jrc reg' as an alias for 'jic 0, $reg'.
537     case Mips::JR:
538     case Mips::PseudoIndirectBranchR6:
539     case Mips::PseudoReturn:
540     case Mips::TAILCALLR6REG:
541       if (canUseShortMicroMipsCTI)
542         return Mips::JRC16_MM;
543       return Mips::JIC;
544     case Mips::JALRPseudo:
545       return Mips::JIALC;
546     case Mips::JR64:
547     case Mips::PseudoIndirectBranch64R6:
548     case Mips::PseudoReturn64:
549     case Mips::TAILCALL64R6REG:
550       return Mips::JIC64;
551     case Mips::JALR64Pseudo:
552       return Mips::JIALC64;
553     default:
554       return 0;
555     }
556   }
557 
558   return 0;
559 }
560 
561 /// Predicate for distingushing between control transfer instructions and all
562 /// other instructions for handling forbidden slots. Consider inline assembly
563 /// as unsafe as well.
564 bool MipsInstrInfo::SafeInForbiddenSlot(const MachineInstr &MI) const {
565   if (MI.isInlineAsm())
566     return false;
567 
568   return (MI.getDesc().TSFlags & MipsII::IsCTI) == 0;
569 }
570 
571 /// Predicate for distingushing instructions that have forbidden slots.
572 bool MipsInstrInfo::HasForbiddenSlot(const MachineInstr &MI) const {
573   return (MI.getDesc().TSFlags & MipsII::HasForbiddenSlot) != 0;
574 }
575 
576 /// Return the number of bytes of code the specified instruction may be.
577 unsigned MipsInstrInfo::getInstSizeInBytes(const MachineInstr &MI) const {
578   switch (MI.getOpcode()) {
579   default:
580     return MI.getDesc().getSize();
581   case  TargetOpcode::INLINEASM: {       // Inline Asm: Variable size.
582     const MachineFunction *MF = MI.getParent()->getParent();
583     const char *AsmStr = MI.getOperand(0).getSymbolName();
584     return getInlineAsmLength(AsmStr, *MF->getTarget().getMCAsmInfo());
585   }
586   case Mips::CONSTPOOL_ENTRY:
587     // If this machine instr is a constant pool entry, its size is recorded as
588     // operand #2.
589     return MI.getOperand(2).getImm();
590   }
591 }
592 
593 MachineInstrBuilder
594 MipsInstrInfo::genInstrWithNewOpc(unsigned NewOpc,
595                                   MachineBasicBlock::iterator I) const {
596   MachineInstrBuilder MIB;
597 
598   // Certain branches have two forms: e.g beq $1, $zero, dest vs beqz $1, dest
599   // Pick the zero form of the branch for readable assembly and for greater
600   // branch distance in non-microMIPS mode.
601   // Additional MIPSR6 does not permit the use of register $zero for compact
602   // branches.
603   // FIXME: Certain atomic sequences on mips64 generate 32bit references to
604   // Mips::ZERO, which is incorrect. This test should be updated to use
605   // Subtarget.getABI().GetZeroReg() when those atomic sequences and others
606   // are fixed.
607   int ZeroOperandPosition = -1;
608   bool BranchWithZeroOperand = false;
609   if (I->isBranch() && !I->isPseudo()) {
610     auto TRI = I->getParent()->getParent()->getSubtarget().getRegisterInfo();
611     ZeroOperandPosition = I->findRegisterUseOperandIdx(Mips::ZERO, false, TRI);
612     BranchWithZeroOperand = ZeroOperandPosition != -1;
613   }
614 
615   if (BranchWithZeroOperand) {
616     switch (NewOpc) {
617     case Mips::BEQC:
618       NewOpc = Mips::BEQZC;
619       break;
620     case Mips::BNEC:
621       NewOpc = Mips::BNEZC;
622       break;
623     case Mips::BGEC:
624       NewOpc = Mips::BGEZC;
625       break;
626     case Mips::BLTC:
627       NewOpc = Mips::BLTZC;
628       break;
629     case Mips::BEQC64:
630       NewOpc = Mips::BEQZC64;
631       break;
632     case Mips::BNEC64:
633       NewOpc = Mips::BNEZC64;
634       break;
635     }
636   }
637 
638   MIB = BuildMI(*I->getParent(), I, I->getDebugLoc(), get(NewOpc));
639 
640   // For MIPSR6 JI*C requires an immediate 0 as an operand, JIALC(64) an
641   // immediate 0 as an operand and requires the removal of it's implicit-def %ra
642   // implicit operand as copying the implicit operations of the instructio we're
643   // looking at will give us the correct flags.
644   if (NewOpc == Mips::JIC || NewOpc == Mips::JIALC || NewOpc == Mips::JIC64 ||
645       NewOpc == Mips::JIALC64) {
646 
647     if (NewOpc == Mips::JIALC || NewOpc == Mips::JIALC64)
648       MIB->RemoveOperand(0);
649 
650     for (unsigned J = 0, E = I->getDesc().getNumOperands(); J < E; ++J) {
651       MIB.add(I->getOperand(J));
652     }
653 
654     MIB.addImm(0);
655 
656   } else {
657     for (unsigned J = 0, E = I->getDesc().getNumOperands(); J < E; ++J) {
658       if (BranchWithZeroOperand && (unsigned)ZeroOperandPosition == J)
659         continue;
660 
661       MIB.add(I->getOperand(J));
662     }
663   }
664 
665   MIB.copyImplicitOps(*I);
666   MIB.cloneMemRefs(*I);
667   return MIB;
668 }
669 
670 bool MipsInstrInfo::findCommutedOpIndices(MachineInstr &MI, unsigned &SrcOpIdx1,
671                                           unsigned &SrcOpIdx2) const {
672   assert(!MI.isBundle() &&
673          "TargetInstrInfo::findCommutedOpIndices() can't handle bundles");
674 
675   const MCInstrDesc &MCID = MI.getDesc();
676   if (!MCID.isCommutable())
677     return false;
678 
679   switch (MI.getOpcode()) {
680   case Mips::DPADD_U_H:
681   case Mips::DPADD_U_W:
682   case Mips::DPADD_U_D:
683   case Mips::DPADD_S_H:
684   case Mips::DPADD_S_W:
685   case Mips::DPADD_S_D:
686     // The first operand is both input and output, so it should not commute
687     if (!fixCommutedOpIndices(SrcOpIdx1, SrcOpIdx2, 2, 3))
688       return false;
689 
690     if (!MI.getOperand(SrcOpIdx1).isReg() || !MI.getOperand(SrcOpIdx2).isReg())
691       return false;
692     return true;
693   }
694   return TargetInstrInfo::findCommutedOpIndices(MI, SrcOpIdx1, SrcOpIdx2);
695 }
696 
697 // ins, ext, dext*, dins have the following constraints:
698 // X <= pos      <  Y
699 // X <  size     <= Y
700 // X <  pos+size <= Y
701 //
702 // dinsm and dinsu have the following constraints:
703 // X <= pos      <  Y
704 // X <= size     <= Y
705 // X <  pos+size <= Y
706 //
707 // The callee of verifyInsExtInstruction however gives the bounds of
708 // dins[um] like the other (d)ins (d)ext(um) instructions, so that this
709 // function doesn't have to vary it's behaviour based on the instruction
710 // being checked.
711 static bool verifyInsExtInstruction(const MachineInstr &MI, StringRef &ErrInfo,
712                                     const int64_t PosLow, const int64_t PosHigh,
713                                     const int64_t SizeLow,
714                                     const int64_t SizeHigh,
715                                     const int64_t BothLow,
716                                     const int64_t BothHigh) {
717   MachineOperand MOPos = MI.getOperand(2);
718   if (!MOPos.isImm()) {
719     ErrInfo = "Position is not an immediate!";
720     return false;
721   }
722   int64_t Pos = MOPos.getImm();
723   if (!((PosLow <= Pos) && (Pos < PosHigh))) {
724     ErrInfo = "Position operand is out of range!";
725     return false;
726   }
727 
728   MachineOperand MOSize = MI.getOperand(3);
729   if (!MOSize.isImm()) {
730     ErrInfo = "Size operand is not an immediate!";
731     return false;
732   }
733   int64_t Size = MOSize.getImm();
734   if (!((SizeLow < Size) && (Size <= SizeHigh))) {
735     ErrInfo = "Size operand is out of range!";
736     return false;
737   }
738 
739   if (!((BothLow < (Pos + Size)) && ((Pos + Size) <= BothHigh))) {
740     ErrInfo = "Position + Size is out of range!";
741     return false;
742   }
743 
744   return true;
745 }
746 
747 //  Perform target specific instruction verification.
748 bool MipsInstrInfo::verifyInstruction(const MachineInstr &MI,
749                                       StringRef &ErrInfo) const {
750   // Verify that ins and ext instructions are well formed.
751   switch (MI.getOpcode()) {
752     case Mips::EXT:
753     case Mips::EXT_MM:
754     case Mips::INS:
755     case Mips::INS_MM:
756     case Mips::DINS:
757       return verifyInsExtInstruction(MI, ErrInfo, 0, 32, 0, 32, 0, 32);
758     case Mips::DINSM:
759       // The ISA spec has a subtle difference between dinsm and dextm
760       // in that it says:
761       // 2 <= size <= 64 for 'dinsm' but 'dextm' has 32 < size <= 64.
762       // To make the bounds checks similar, the range 1 < size <= 64 is checked
763       // for 'dinsm'.
764       return verifyInsExtInstruction(MI, ErrInfo, 0, 32, 1, 64, 32, 64);
765     case Mips::DINSU:
766       // The ISA spec has a subtle difference between dinsu and dextu in that
767       // the size range of dinsu is specified as 1 <= size <= 32 whereas size
768       // for dextu is 0 < size <= 32. The range checked for dinsu here is
769       // 0 < size <= 32, which is equivalent and similar to dextu.
770       return verifyInsExtInstruction(MI, ErrInfo, 32, 64, 0, 32, 32, 64);
771     case Mips::DEXT:
772       return verifyInsExtInstruction(MI, ErrInfo, 0, 32, 0, 32, 0, 63);
773     case Mips::DEXTM:
774       return verifyInsExtInstruction(MI, ErrInfo, 0, 32, 32, 64, 32, 64);
775     case Mips::DEXTU:
776       return verifyInsExtInstruction(MI, ErrInfo, 32, 64, 0, 32, 32, 64);
777     case Mips::TAILCALLREG:
778     case Mips::PseudoIndirectBranch:
779     case Mips::JR:
780     case Mips::JR64:
781     case Mips::JALR:
782     case Mips::JALR64:
783     case Mips::JALRPseudo:
784       if (!Subtarget.useIndirectJumpsHazard())
785         return true;
786 
787       ErrInfo = "invalid instruction when using jump guards!";
788       return false;
789     default:
790       return true;
791   }
792 
793   return true;
794 }
795 
796 std::pair<unsigned, unsigned>
797 MipsInstrInfo::decomposeMachineOperandsTargetFlags(unsigned TF) const {
798   return std::make_pair(TF, 0u);
799 }
800 
801 ArrayRef<std::pair<unsigned, const char*>>
802 MipsInstrInfo::getSerializableDirectMachineOperandTargetFlags() const {
803  using namespace MipsII;
804 
805  static const std::pair<unsigned, const char*> Flags[] = {
806     {MO_GOT,          "mips-got"},
807     {MO_GOT_CALL,     "mips-got-call"},
808     {MO_GPREL,        "mips-gprel"},
809     {MO_ABS_HI,       "mips-abs-hi"},
810     {MO_ABS_LO,       "mips-abs-lo"},
811     {MO_TLSGD,        "mips-tlsgd"},
812     {MO_TLSLDM,       "mips-tlsldm"},
813     {MO_DTPREL_HI,    "mips-dtprel-hi"},
814     {MO_DTPREL_LO,    "mips-dtprel-lo"},
815     {MO_GOTTPREL,     "mips-gottprel"},
816     {MO_TPREL_HI,     "mips-tprel-hi"},
817     {MO_TPREL_LO,     "mips-tprel-lo"},
818     {MO_GPOFF_HI,     "mips-gpoff-hi"},
819     {MO_GPOFF_LO,     "mips-gpoff-lo"},
820     {MO_GOT_DISP,     "mips-got-disp"},
821     {MO_GOT_PAGE,     "mips-got-page"},
822     {MO_GOT_OFST,     "mips-got-ofst"},
823     {MO_HIGHER,       "mips-higher"},
824     {MO_HIGHEST,      "mips-highest"},
825     {MO_GOT_HI16,     "mips-got-hi16"},
826     {MO_GOT_LO16,     "mips-got-lo16"},
827     {MO_CALL_HI16,    "mips-call-hi16"},
828     {MO_CALL_LO16,    "mips-call-lo16"}
829   };
830   return makeArrayRef(Flags);
831 }
832