1 //===- MipsInstrInfo.cpp - Mips Instruction Information ---------*- C++ -*-===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file contains the Mips implementation of the TargetInstrInfo class.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #include "MipsInstrInfo.h"
15 #include "MipsTargetMachine.h"
16 #include "MipsMachineFunction.h"
17 #include "llvm/ADT/STLExtras.h"
18 #include "llvm/CodeGen/MachineInstrBuilder.h"
19 #include "llvm/CodeGen/MachineRegisterInfo.h"
20 #include "llvm/Support/ErrorHandling.h"
21 #include "MipsGenInstrInfo.inc"
22 
23 using namespace llvm;
24 
25 MipsInstrInfo::MipsInstrInfo(MipsTargetMachine &tm)
26   : TargetInstrInfoImpl(MipsInsts, array_lengthof(MipsInsts)),
27     TM(tm), RI(*TM.getSubtargetImpl(), *this) {}
28 
29 static bool isZeroImm(const MachineOperand &op) {
30   return op.isImm() && op.getImm() == 0;
31 }
32 
33 /// Return true if the instruction is a register to register move and
34 /// leave the source and dest operands in the passed parameters.
35 bool MipsInstrInfo::
36 isMoveInstr(const MachineInstr &MI, unsigned &SrcReg, unsigned &DstReg,
37             unsigned &SrcSubIdx, unsigned &DstSubIdx) const
38 {
39   SrcSubIdx = DstSubIdx = 0; // No sub-registers.
40 
41   // addu $dst, $src, $zero || addu $dst, $zero, $src
42   // or   $dst, $src, $zero || or   $dst, $zero, $src
43   if ((MI.getOpcode() == Mips::ADDu) || (MI.getOpcode() == Mips::OR)) {
44     if (MI.getOperand(1).getReg() == Mips::ZERO) {
45       DstReg = MI.getOperand(0).getReg();
46       SrcReg = MI.getOperand(2).getReg();
47       return true;
48     } else if (MI.getOperand(2).getReg() == Mips::ZERO) {
49       DstReg = MI.getOperand(0).getReg();
50       SrcReg = MI.getOperand(1).getReg();
51       return true;
52     }
53   }
54 
55   // mov $fpDst, $fpSrc
56   // mfc $gpDst, $fpSrc
57   // mtc $fpDst, $gpSrc
58   if (MI.getOpcode() == Mips::FMOV_S32 ||
59       MI.getOpcode() == Mips::FMOV_D32 ||
60       MI.getOpcode() == Mips::MFC1 ||
61       MI.getOpcode() == Mips::MTC1 ||
62       MI.getOpcode() == Mips::MOVCCRToCCR) {
63     DstReg = MI.getOperand(0).getReg();
64     SrcReg = MI.getOperand(1).getReg();
65     return true;
66   }
67 
68   // addiu $dst, $src, 0
69   if (MI.getOpcode() == Mips::ADDiu) {
70     if ((MI.getOperand(1).isReg()) && (isZeroImm(MI.getOperand(2)))) {
71       DstReg = MI.getOperand(0).getReg();
72       SrcReg = MI.getOperand(1).getReg();
73       return true;
74     }
75   }
76 
77   return false;
78 }
79 
80 /// isLoadFromStackSlot - If the specified machine instruction is a direct
81 /// load from a stack slot, return the virtual or physical register number of
82 /// the destination along with the FrameIndex of the loaded stack slot.  If
83 /// not, return 0.  This predicate must return 0 if the instruction has
84 /// any side effects other than loading from the stack slot.
85 unsigned MipsInstrInfo::
86 isLoadFromStackSlot(const MachineInstr *MI, int &FrameIndex) const
87 {
88   if ((MI->getOpcode() == Mips::LW) || (MI->getOpcode() == Mips::LWC1) ||
89       (MI->getOpcode() == Mips::LDC1)) {
90     if ((MI->getOperand(2).isFI()) && // is a stack slot
91         (MI->getOperand(1).isImm()) &&  // the imm is zero
92         (isZeroImm(MI->getOperand(1)))) {
93       FrameIndex = MI->getOperand(2).getIndex();
94       return MI->getOperand(0).getReg();
95     }
96   }
97 
98   return 0;
99 }
100 
101 /// isStoreToStackSlot - If the specified machine instruction is a direct
102 /// store to a stack slot, return the virtual or physical register number of
103 /// the source reg along with the FrameIndex of the loaded stack slot.  If
104 /// not, return 0.  This predicate must return 0 if the instruction has
105 /// any side effects other than storing to the stack slot.
106 unsigned MipsInstrInfo::
107 isStoreToStackSlot(const MachineInstr *MI, int &FrameIndex) const
108 {
109   if ((MI->getOpcode() == Mips::SW) || (MI->getOpcode() == Mips::SWC1) ||
110       (MI->getOpcode() == Mips::SDC1)) {
111     if ((MI->getOperand(2).isFI()) && // is a stack slot
112         (MI->getOperand(1).isImm()) &&  // the imm is zero
113         (isZeroImm(MI->getOperand(1)))) {
114       FrameIndex = MI->getOperand(2).getIndex();
115       return MI->getOperand(0).getReg();
116     }
117   }
118   return 0;
119 }
120 
121 /// insertNoop - If data hazard condition is found insert the target nop
122 /// instruction.
123 void MipsInstrInfo::
124 insertNoop(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI) const
125 {
126   DebugLoc DL;
127   BuildMI(MBB, MI, DL, get(Mips::NOP));
128 }
129 
130 bool MipsInstrInfo::
131 copyRegToReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
132              unsigned DestReg, unsigned SrcReg,
133              const TargetRegisterClass *DestRC,
134              const TargetRegisterClass *SrcRC,
135              DebugLoc DL) const {
136 
137   if (DestRC != SrcRC) {
138 
139     // Copy to/from FCR31 condition register
140     if ((DestRC == Mips::CPURegsRegisterClass) &&
141         (SrcRC == Mips::CCRRegisterClass))
142       BuildMI(MBB, I, DL, get(Mips::CFC1), DestReg).addReg(SrcReg);
143     else if ((DestRC == Mips::CCRRegisterClass) &&
144         (SrcRC == Mips::CPURegsRegisterClass))
145       BuildMI(MBB, I, DL, get(Mips::CTC1), DestReg).addReg(SrcReg);
146 
147     // Moves between coprocessors and cpu
148     else if ((DestRC == Mips::CPURegsRegisterClass) &&
149         (SrcRC == Mips::FGR32RegisterClass))
150       BuildMI(MBB, I, DL, get(Mips::MFC1), DestReg).addReg(SrcReg);
151     else if ((DestRC == Mips::FGR32RegisterClass) &&
152              (SrcRC == Mips::CPURegsRegisterClass))
153       BuildMI(MBB, I, DL, get(Mips::MTC1), DestReg).addReg(SrcReg);
154 
155     // Move from/to Hi/Lo registers
156     else if ((DestRC == Mips::HILORegisterClass) &&
157              (SrcRC == Mips::CPURegsRegisterClass)) {
158       unsigned Opc = (DestReg == Mips::HI) ? Mips::MTHI : Mips::MTLO;
159       BuildMI(MBB, I, DL, get(Opc), DestReg);
160     } else if ((SrcRC == Mips::HILORegisterClass) &&
161                (DestRC == Mips::CPURegsRegisterClass)) {
162       unsigned Opc = (SrcReg == Mips::HI) ? Mips::MFHI : Mips::MFLO;
163       BuildMI(MBB, I, DL, get(Opc), DestReg);
164     } else
165       // Can't copy this register
166       return false;
167 
168     return true;
169   }
170 
171   if (DestRC == Mips::CPURegsRegisterClass)
172     BuildMI(MBB, I, DL, get(Mips::ADDu), DestReg).addReg(Mips::ZERO)
173       .addReg(SrcReg);
174   else if (DestRC == Mips::FGR32RegisterClass)
175     BuildMI(MBB, I, DL, get(Mips::FMOV_S32), DestReg).addReg(SrcReg);
176   else if (DestRC == Mips::AFGR64RegisterClass)
177     BuildMI(MBB, I, DL, get(Mips::FMOV_D32), DestReg).addReg(SrcReg);
178   else if (DestRC == Mips::CCRRegisterClass)
179     BuildMI(MBB, I, DL, get(Mips::MOVCCRToCCR), DestReg).addReg(SrcReg);
180   else
181     // Can't copy this register
182     return false;
183 
184   return true;
185 }
186 
187 void MipsInstrInfo::
188 storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
189                     unsigned SrcReg, bool isKill, int FI,
190                     const TargetRegisterClass *RC,
191                     const TargetRegisterInfo *TRI) const {
192   DebugLoc DL;
193   if (I != MBB.end()) DL = I->getDebugLoc();
194 
195   if (RC == Mips::CPURegsRegisterClass)
196     BuildMI(MBB, I, DL, get(Mips::SW)).addReg(SrcReg, getKillRegState(isKill))
197           .addImm(0).addFrameIndex(FI);
198   else if (RC == Mips::FGR32RegisterClass)
199     BuildMI(MBB, I, DL, get(Mips::SWC1)).addReg(SrcReg, getKillRegState(isKill))
200           .addImm(0).addFrameIndex(FI);
201   else if (RC == Mips::AFGR64RegisterClass) {
202     if (!TM.getSubtarget<MipsSubtarget>().isMips1()) {
203       BuildMI(MBB, I, DL, get(Mips::SDC1))
204         .addReg(SrcReg, getKillRegState(isKill))
205         .addImm(0).addFrameIndex(FI);
206     } else {
207       const TargetRegisterInfo *TRI =
208         MBB.getParent()->getTarget().getRegisterInfo();
209       const unsigned *SubSet = TRI->getSubRegisters(SrcReg);
210       BuildMI(MBB, I, DL, get(Mips::SWC1))
211         .addReg(SubSet[0], getKillRegState(isKill))
212         .addImm(0).addFrameIndex(FI);
213       BuildMI(MBB, I, DL, get(Mips::SWC1))
214         .addReg(SubSet[1], getKillRegState(isKill))
215         .addImm(4).addFrameIndex(FI);
216     }
217   } else
218     llvm_unreachable("Register class not handled!");
219 }
220 
221 void MipsInstrInfo::
222 loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
223                      unsigned DestReg, int FI,
224                      const TargetRegisterClass *RC,
225                      const TargetRegisterInfo *TRI) const
226 {
227   DebugLoc DL;
228   if (I != MBB.end()) DL = I->getDebugLoc();
229 
230   if (RC == Mips::CPURegsRegisterClass)
231     BuildMI(MBB, I, DL, get(Mips::LW), DestReg).addImm(0).addFrameIndex(FI);
232   else if (RC == Mips::FGR32RegisterClass)
233     BuildMI(MBB, I, DL, get(Mips::LWC1), DestReg).addImm(0).addFrameIndex(FI);
234   else if (RC == Mips::AFGR64RegisterClass) {
235     if (!TM.getSubtarget<MipsSubtarget>().isMips1()) {
236       BuildMI(MBB, I, DL, get(Mips::LDC1), DestReg).addImm(0).addFrameIndex(FI);
237     } else {
238       const TargetRegisterInfo *TRI =
239         MBB.getParent()->getTarget().getRegisterInfo();
240       const unsigned *SubSet = TRI->getSubRegisters(DestReg);
241       BuildMI(MBB, I, DL, get(Mips::LWC1), SubSet[0])
242         .addImm(0).addFrameIndex(FI);
243       BuildMI(MBB, I, DL, get(Mips::LWC1), SubSet[1])
244         .addImm(4).addFrameIndex(FI);
245     }
246   } else
247     llvm_unreachable("Register class not handled!");
248 }
249 
250 MachineInstr *MipsInstrInfo::
251 foldMemoryOperandImpl(MachineFunction &MF,
252                       MachineInstr* MI,
253                       const SmallVectorImpl<unsigned> &Ops, int FI) const
254 {
255   if (Ops.size() != 1) return NULL;
256 
257   MachineInstr *NewMI = NULL;
258 
259   switch (MI->getOpcode()) {
260   case Mips::ADDu:
261     if ((MI->getOperand(0).isReg()) &&
262         (MI->getOperand(1).isReg()) &&
263         (MI->getOperand(1).getReg() == Mips::ZERO) &&
264         (MI->getOperand(2).isReg())) {
265       if (Ops[0] == 0) {    // COPY -> STORE
266         unsigned SrcReg = MI->getOperand(2).getReg();
267         bool isKill = MI->getOperand(2).isKill();
268         bool isUndef = MI->getOperand(2).isUndef();
269         NewMI = BuildMI(MF, MI->getDebugLoc(), get(Mips::SW))
270           .addReg(SrcReg, getKillRegState(isKill) | getUndefRegState(isUndef))
271           .addImm(0).addFrameIndex(FI);
272       } else {              // COPY -> LOAD
273         unsigned DstReg = MI->getOperand(0).getReg();
274         bool isDead = MI->getOperand(0).isDead();
275         bool isUndef = MI->getOperand(0).isUndef();
276         NewMI = BuildMI(MF, MI->getDebugLoc(), get(Mips::LW))
277           .addReg(DstReg, RegState::Define | getDeadRegState(isDead) |
278                   getUndefRegState(isUndef))
279           .addImm(0).addFrameIndex(FI);
280       }
281     }
282     break;
283   case Mips::FMOV_S32:
284   case Mips::FMOV_D32:
285     if ((MI->getOperand(0).isReg()) &&
286         (MI->getOperand(1).isReg())) {
287       const TargetRegisterClass
288         *RC = RI.getRegClass(MI->getOperand(0).getReg());
289       unsigned StoreOpc, LoadOpc;
290       bool IsMips1 = TM.getSubtarget<MipsSubtarget>().isMips1();
291 
292       if (RC == Mips::FGR32RegisterClass) {
293         LoadOpc = Mips::LWC1; StoreOpc = Mips::SWC1;
294       } else {
295         assert(RC == Mips::AFGR64RegisterClass);
296         // Mips1 doesn't have ldc/sdc instructions.
297         if (IsMips1) break;
298         LoadOpc = Mips::LDC1; StoreOpc = Mips::SDC1;
299       }
300 
301       if (Ops[0] == 0) {    // COPY -> STORE
302         unsigned SrcReg = MI->getOperand(1).getReg();
303         bool isKill = MI->getOperand(1).isKill();
304         bool isUndef = MI->getOperand(2).isUndef();
305         NewMI = BuildMI(MF, MI->getDebugLoc(), get(StoreOpc))
306           .addReg(SrcReg, getKillRegState(isKill) | getUndefRegState(isUndef))
307           .addImm(0).addFrameIndex(FI) ;
308       } else {              // COPY -> LOAD
309         unsigned DstReg = MI->getOperand(0).getReg();
310         bool isDead = MI->getOperand(0).isDead();
311         bool isUndef = MI->getOperand(0).isUndef();
312         NewMI = BuildMI(MF, MI->getDebugLoc(), get(LoadOpc))
313           .addReg(DstReg, RegState::Define | getDeadRegState(isDead) |
314                   getUndefRegState(isUndef))
315           .addImm(0).addFrameIndex(FI);
316       }
317     }
318     break;
319   }
320 
321   return NewMI;
322 }
323 
324 //===----------------------------------------------------------------------===//
325 // Branch Analysis
326 //===----------------------------------------------------------------------===//
327 
328 /// GetCondFromBranchOpc - Return the Mips CC that matches
329 /// the correspondent Branch instruction opcode.
330 static Mips::CondCode GetCondFromBranchOpc(unsigned BrOpc)
331 {
332   switch (BrOpc) {
333   default: return Mips::COND_INVALID;
334   case Mips::BEQ  : return Mips::COND_E;
335   case Mips::BNE  : return Mips::COND_NE;
336   case Mips::BGTZ : return Mips::COND_GZ;
337   case Mips::BGEZ : return Mips::COND_GEZ;
338   case Mips::BLTZ : return Mips::COND_LZ;
339   case Mips::BLEZ : return Mips::COND_LEZ;
340 
341   // We dont do fp branch analysis yet!
342   case Mips::BC1T :
343   case Mips::BC1F : return Mips::COND_INVALID;
344   }
345 }
346 
347 /// GetCondBranchFromCond - Return the Branch instruction
348 /// opcode that matches the cc.
349 unsigned Mips::GetCondBranchFromCond(Mips::CondCode CC)
350 {
351   switch (CC) {
352   default: llvm_unreachable("Illegal condition code!");
353   case Mips::COND_E   : return Mips::BEQ;
354   case Mips::COND_NE  : return Mips::BNE;
355   case Mips::COND_GZ  : return Mips::BGTZ;
356   case Mips::COND_GEZ : return Mips::BGEZ;
357   case Mips::COND_LZ  : return Mips::BLTZ;
358   case Mips::COND_LEZ : return Mips::BLEZ;
359 
360   case Mips::FCOND_F:
361   case Mips::FCOND_UN:
362   case Mips::FCOND_EQ:
363   case Mips::FCOND_UEQ:
364   case Mips::FCOND_OLT:
365   case Mips::FCOND_ULT:
366   case Mips::FCOND_OLE:
367   case Mips::FCOND_ULE:
368   case Mips::FCOND_SF:
369   case Mips::FCOND_NGLE:
370   case Mips::FCOND_SEQ:
371   case Mips::FCOND_NGL:
372   case Mips::FCOND_LT:
373   case Mips::FCOND_NGE:
374   case Mips::FCOND_LE:
375   case Mips::FCOND_NGT: return Mips::BC1T;
376 
377   case Mips::FCOND_T:
378   case Mips::FCOND_OR:
379   case Mips::FCOND_NEQ:
380   case Mips::FCOND_OGL:
381   case Mips::FCOND_UGE:
382   case Mips::FCOND_OGE:
383   case Mips::FCOND_UGT:
384   case Mips::FCOND_OGT:
385   case Mips::FCOND_ST:
386   case Mips::FCOND_GLE:
387   case Mips::FCOND_SNE:
388   case Mips::FCOND_GL:
389   case Mips::FCOND_NLT:
390   case Mips::FCOND_GE:
391   case Mips::FCOND_NLE:
392   case Mips::FCOND_GT: return Mips::BC1F;
393   }
394 }
395 
396 /// GetOppositeBranchCondition - Return the inverse of the specified
397 /// condition, e.g. turning COND_E to COND_NE.
398 Mips::CondCode Mips::GetOppositeBranchCondition(Mips::CondCode CC)
399 {
400   switch (CC) {
401   default: llvm_unreachable("Illegal condition code!");
402   case Mips::COND_E   : return Mips::COND_NE;
403   case Mips::COND_NE  : return Mips::COND_E;
404   case Mips::COND_GZ  : return Mips::COND_LEZ;
405   case Mips::COND_GEZ : return Mips::COND_LZ;
406   case Mips::COND_LZ  : return Mips::COND_GEZ;
407   case Mips::COND_LEZ : return Mips::COND_GZ;
408   case Mips::FCOND_F  : return Mips::FCOND_T;
409   case Mips::FCOND_UN : return Mips::FCOND_OR;
410   case Mips::FCOND_EQ : return Mips::FCOND_NEQ;
411   case Mips::FCOND_UEQ: return Mips::FCOND_OGL;
412   case Mips::FCOND_OLT: return Mips::FCOND_UGE;
413   case Mips::FCOND_ULT: return Mips::FCOND_OGE;
414   case Mips::FCOND_OLE: return Mips::FCOND_UGT;
415   case Mips::FCOND_ULE: return Mips::FCOND_OGT;
416   case Mips::FCOND_SF:  return Mips::FCOND_ST;
417   case Mips::FCOND_NGLE:return Mips::FCOND_GLE;
418   case Mips::FCOND_SEQ: return Mips::FCOND_SNE;
419   case Mips::FCOND_NGL: return Mips::FCOND_GL;
420   case Mips::FCOND_LT:  return Mips::FCOND_NLT;
421   case Mips::FCOND_NGE: return Mips::FCOND_GE;
422   case Mips::FCOND_LE:  return Mips::FCOND_NLE;
423   case Mips::FCOND_NGT: return Mips::FCOND_GT;
424   }
425 }
426 
427 bool MipsInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,
428                                   MachineBasicBlock *&TBB,
429                                   MachineBasicBlock *&FBB,
430                                   SmallVectorImpl<MachineOperand> &Cond,
431                                   bool AllowModify) const
432 {
433   // If the block has no terminators, it just falls into the block after it.
434   MachineBasicBlock::iterator I = MBB.end();
435   if (I == MBB.begin())
436     return false;
437   --I;
438   while (I->isDebugValue()) {
439     if (I == MBB.begin())
440       return false;
441     --I;
442   }
443   if (!isUnpredicatedTerminator(I))
444     return false;
445 
446   // Get the last instruction in the block.
447   MachineInstr *LastInst = I;
448 
449   // If there is only one terminator instruction, process it.
450   unsigned LastOpc = LastInst->getOpcode();
451   if (I == MBB.begin() || !isUnpredicatedTerminator(--I)) {
452     if (!LastInst->getDesc().isBranch())
453       return true;
454 
455     // Unconditional branch
456     if (LastOpc == Mips::J) {
457       TBB = LastInst->getOperand(0).getMBB();
458       return false;
459     }
460 
461     Mips::CondCode BranchCode = GetCondFromBranchOpc(LastInst->getOpcode());
462     if (BranchCode == Mips::COND_INVALID)
463       return true;  // Can't handle indirect branch.
464 
465     // Conditional branch
466     // Block ends with fall-through condbranch.
467     if (LastOpc != Mips::COND_INVALID) {
468       int LastNumOp = LastInst->getNumOperands();
469 
470       TBB = LastInst->getOperand(LastNumOp-1).getMBB();
471       Cond.push_back(MachineOperand::CreateImm(BranchCode));
472 
473       for (int i=0; i<LastNumOp-1; i++) {
474         Cond.push_back(LastInst->getOperand(i));
475       }
476 
477       return false;
478     }
479   }
480 
481   // Get the instruction before it if it is a terminator.
482   MachineInstr *SecondLastInst = I;
483 
484   // If there are three terminators, we don't know what sort of block this is.
485   if (SecondLastInst && I != MBB.begin() && isUnpredicatedTerminator(--I))
486     return true;
487 
488   // If the block ends with Mips::J and a Mips::BNE/Mips::BEQ, handle it.
489   unsigned SecondLastOpc    = SecondLastInst->getOpcode();
490   Mips::CondCode BranchCode = GetCondFromBranchOpc(SecondLastOpc);
491 
492   if (BranchCode != Mips::COND_INVALID && LastOpc == Mips::J) {
493     int SecondNumOp = SecondLastInst->getNumOperands();
494 
495     TBB = SecondLastInst->getOperand(SecondNumOp-1).getMBB();
496     Cond.push_back(MachineOperand::CreateImm(BranchCode));
497 
498     for (int i=0; i<SecondNumOp-1; i++) {
499       Cond.push_back(SecondLastInst->getOperand(i));
500     }
501 
502     FBB = LastInst->getOperand(0).getMBB();
503     return false;
504   }
505 
506   // If the block ends with two unconditional branches, handle it. The last
507   // one is not executed, so remove it.
508   if ((SecondLastOpc == Mips::J) && (LastOpc == Mips::J)) {
509     TBB = SecondLastInst->getOperand(0).getMBB();
510     I = LastInst;
511     if (AllowModify)
512       I->eraseFromParent();
513     return false;
514   }
515 
516   // Otherwise, can't handle this.
517   return true;
518 }
519 
520 unsigned MipsInstrInfo::
521 InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
522              MachineBasicBlock *FBB,
523              const SmallVectorImpl<MachineOperand> &Cond) const {
524   // FIXME this should probably have a DebugLoc argument
525   DebugLoc dl;
526   // Shouldn't be a fall through.
527   assert(TBB && "InsertBranch must not be told to insert a fallthrough");
528   assert((Cond.size() == 3 || Cond.size() == 2 || Cond.size() == 0) &&
529          "Mips branch conditions can have two|three components!");
530 
531   if (FBB == 0) { // One way branch.
532     if (Cond.empty()) {
533       // Unconditional branch?
534       BuildMI(&MBB, dl, get(Mips::J)).addMBB(TBB);
535     } else {
536       // Conditional branch.
537       unsigned Opc = GetCondBranchFromCond((Mips::CondCode)Cond[0].getImm());
538       const TargetInstrDesc &TID = get(Opc);
539 
540       if (TID.getNumOperands() == 3)
541         BuildMI(&MBB, dl, TID).addReg(Cond[1].getReg())
542                           .addReg(Cond[2].getReg())
543                           .addMBB(TBB);
544       else
545         BuildMI(&MBB, dl, TID).addReg(Cond[1].getReg())
546                           .addMBB(TBB);
547 
548     }
549     return 1;
550   }
551 
552   // Two-way Conditional branch.
553   unsigned Opc = GetCondBranchFromCond((Mips::CondCode)Cond[0].getImm());
554   const TargetInstrDesc &TID = get(Opc);
555 
556   if (TID.getNumOperands() == 3)
557     BuildMI(&MBB, dl, TID).addReg(Cond[1].getReg()).addReg(Cond[2].getReg())
558                       .addMBB(TBB);
559   else
560     BuildMI(&MBB, dl, TID).addReg(Cond[1].getReg()).addMBB(TBB);
561 
562   BuildMI(&MBB, dl, get(Mips::J)).addMBB(FBB);
563   return 2;
564 }
565 
566 unsigned MipsInstrInfo::
567 RemoveBranch(MachineBasicBlock &MBB) const
568 {
569   MachineBasicBlock::iterator I = MBB.end();
570   if (I == MBB.begin()) return 0;
571   --I;
572   while (I->isDebugValue()) {
573     if (I == MBB.begin())
574       return 0;
575     --I;
576   }
577   if (I->getOpcode() != Mips::J &&
578       GetCondFromBranchOpc(I->getOpcode()) == Mips::COND_INVALID)
579     return 0;
580 
581   // Remove the branch.
582   I->eraseFromParent();
583 
584   I = MBB.end();
585 
586   if (I == MBB.begin()) return 1;
587   --I;
588   if (GetCondFromBranchOpc(I->getOpcode()) == Mips::COND_INVALID)
589     return 1;
590 
591   // Remove the branch.
592   I->eraseFromParent();
593   return 2;
594 }
595 
596 /// ReverseBranchCondition - Return the inverse opcode of the
597 /// specified Branch instruction.
598 bool MipsInstrInfo::
599 ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const
600 {
601   assert( (Cond.size() == 3 || Cond.size() == 2) &&
602           "Invalid Mips branch condition!");
603   Cond[0].setImm(GetOppositeBranchCondition((Mips::CondCode)Cond[0].getImm()));
604   return false;
605 }
606 
607 /// getGlobalBaseReg - Return a virtual register initialized with the
608 /// the global base register value. Output instructions required to
609 /// initialize the register in the function entry block, if necessary.
610 ///
611 unsigned MipsInstrInfo::getGlobalBaseReg(MachineFunction *MF) const {
612   MipsFunctionInfo *MipsFI = MF->getInfo<MipsFunctionInfo>();
613   unsigned GlobalBaseReg = MipsFI->getGlobalBaseReg();
614   if (GlobalBaseReg != 0)
615     return GlobalBaseReg;
616 
617   // Insert the set of GlobalBaseReg into the first MBB of the function
618   MachineBasicBlock &FirstMBB = MF->front();
619   MachineBasicBlock::iterator MBBI = FirstMBB.begin();
620   MachineRegisterInfo &RegInfo = MF->getRegInfo();
621   const TargetInstrInfo *TII = MF->getTarget().getInstrInfo();
622 
623   GlobalBaseReg = RegInfo.createVirtualRegister(Mips::CPURegsRegisterClass);
624   bool Ok = TII->copyRegToReg(FirstMBB, MBBI, GlobalBaseReg, Mips::GP,
625                               Mips::CPURegsRegisterClass,
626                               Mips::CPURegsRegisterClass,
627                               DebugLoc());
628   assert(Ok && "Couldn't assign to global base register!");
629   Ok = Ok; // Silence warning when assertions are turned off.
630   RegInfo.addLiveIn(Mips::GP);
631 
632   MipsFI->setGlobalBaseReg(GlobalBaseReg);
633   return GlobalBaseReg;
634 }
635