1//===- MipsRegisterInfo.td - Mips Register defs -----------------*- C++ -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9
10//===----------------------------------------------------------------------===//
11//  Describe MIPS instructions format
12//
13//  CPU INSTRUCTION FORMATS
14//
15//  opcode  - operation code.
16//  rs      - src reg.
17//  rt      - dst reg (on a 2 regs instr) or src reg (on a 3 reg instr).
18//  rd      - dst reg, only used on 3 regs instr.
19//  shamt   - only used on shift instructions, contains the shift amount.
20//  funct   - combined with opcode field give us an operation code.
21//
22//===----------------------------------------------------------------------===//
23
24// Generic Mips Format
25class MipsInst<dag outs, dag ins, string asmstr, list<dag> pattern,
26               InstrItinClass itin>: Instruction
27{
28  field bits<32> Inst;
29
30  let Namespace = "Mips";
31
32  bits<6> opcode;
33
34  // Top 5 bits are the 'opcode' field
35  let Inst{31-26} = opcode;
36
37  dag OutOperandList = outs;
38  dag InOperandList  = ins;
39
40  let AsmString   = asmstr;
41  let Pattern     = pattern;
42  let Itinerary   = itin;
43}
44
45// Mips Pseudo Instructions Format
46class MipsPseudo<dag outs, dag ins, string asmstr, list<dag> pattern>:
47      MipsInst<outs, ins, asmstr, pattern, IIPseudo>;
48
49//===----------------------------------------------------------------------===//
50// Format R instruction class in Mips : <|opcode|rs|rt|rd|shamt|funct|>
51//===----------------------------------------------------------------------===//
52
53class FR<bits<6> op, bits<6> _funct, dag outs, dag ins, string asmstr,
54         list<dag> pattern, InstrItinClass itin>:
55      MipsInst<outs, ins, asmstr, pattern, itin>
56{
57  bits<5>  rd;
58  bits<5>  rs;
59  bits<5>  rt;
60  bits<5>  shamt;
61  bits<6>  funct;
62
63  let opcode = op;
64  let funct  = _funct;
65
66  let Inst{25-21} = rs;
67  let Inst{20-16} = rt;
68  let Inst{15-11} = rd;
69  let Inst{10-6}  = shamt;
70  let Inst{5-0}   = funct;
71}
72
73//===----------------------------------------------------------------------===//
74// Format I instruction class in Mips : <|opcode|rs|rt|immediate|>
75//===----------------------------------------------------------------------===//
76
77class FI<bits<6> op, dag outs, dag ins, string asmstr, list<dag> pattern,
78         InstrItinClass itin>: MipsInst<outs, ins, asmstr, pattern, itin>
79{
80  bits<5>  rt;
81  bits<5>  rs;
82  bits<16> imm16;
83
84  let opcode = op;
85
86  let Inst{25-21} = rs;
87  let Inst{20-16} = rt;
88  let Inst{15-0}  = imm16;
89}
90
91//===----------------------------------------------------------------------===//
92// Format J instruction class in Mips : <|opcode|address|>
93//===----------------------------------------------------------------------===//
94
95class FJ<bits<6> op, dag outs, dag ins, string asmstr, list<dag> pattern,
96         InstrItinClass itin>: MipsInst<outs, ins, asmstr, pattern, itin>
97{
98  bits<26> addr;
99
100  let opcode = op;
101
102  let Inst{25-0} = addr;
103}
104
105//===----------------------------------------------------------------------===//
106//
107//  FLOATING POINT INSTRUCTION FORMATS
108//
109//  opcode  - operation code.
110//  fs      - src reg.
111//  ft      - dst reg (on a 2 regs instr) or src reg (on a 3 reg instr).
112//  fd      - dst reg, only used on 3 regs instr.
113//  fmt     - double or single precision.
114//  funct   - combined with opcode field give us an operation code.
115//
116//===----------------------------------------------------------------------===//
117
118//===----------------------------------------------------------------------===//
119// Format FR instruction class in Mips : <|opcode|fmt|ft|fs|fd|funct|>
120//===----------------------------------------------------------------------===//
121
122class FFR<bits<6> op, bits<6> _funct, bits<5> _fmt, dag outs, dag ins,
123          string asmstr, list<dag> pattern> :
124          MipsInst<outs, ins, asmstr, pattern, NoItinerary>
125{
126  bits<5>  fd;
127  bits<5>  fs;
128  bits<5>  ft;
129  bits<5>  fmt;
130  bits<6>  funct;
131
132  let opcode = op;
133  let funct  = _funct;
134  let fmt    = _fmt;
135
136  let Inst{25-21} = fmt;
137  let Inst{20-16} = ft;
138  let Inst{15-11} = fs;
139  let Inst{10-6}  = fd;
140  let Inst{5-0}   = funct;
141}
142
143//===----------------------------------------------------------------------===//
144// Format FI instruction class in Mips : <|opcode|base|ft|immediate|>
145//===----------------------------------------------------------------------===//
146
147class FFI<bits<6> op, dag outs, dag ins, string asmstr, list<dag> pattern>:
148          MipsInst<outs, ins, asmstr, pattern, NoItinerary>
149{
150  bits<5>  ft;
151  bits<5>  base;
152  bits<16> imm16;
153
154  let opcode = op;
155
156  let Inst{25-21} = base;
157  let Inst{20-16} = ft;
158  let Inst{15-0}  = imm16;
159}
160
161//===----------------------------------------------------------------------===//
162// Compare instruction class in Mips : <|010001|fmt|ft|fs|0000011|condcode|>
163//===----------------------------------------------------------------------===//
164
165class FCC<bits<5> _fmt, dag outs, dag ins, string asmstr, list<dag> pattern> :
166          MipsInst<outs, ins, asmstr, pattern, NoItinerary>
167{
168  bits<5>  fs;
169  bits<5>  ft;
170  bits<4>  cc;
171  bits<5>  fmt;
172
173  let opcode = 0x11;
174  let fmt    = _fmt;
175
176  let Inst{25-21} = fmt;
177  let Inst{20-16} = ft;
178  let Inst{15-11} = fs;
179  let Inst{10-6}  = 0;
180  let Inst{5-4}   = 0b11;
181  let Inst{3-0}   = cc;
182}
183