1//===-- MipsInstrFormats.td - Mips Instruction Formats -----*- tablegen -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9
10//===----------------------------------------------------------------------===//
11//  Describe MIPS instructions format
12//
13//  CPU INSTRUCTION FORMATS
14//
15//  opcode  - operation code.
16//  rs      - src reg.
17//  rt      - dst reg (on a 2 regs instr) or src reg (on a 3 reg instr).
18//  rd      - dst reg, only used on 3 regs instr.
19//  shamt   - only used on shift instructions, contains the shift amount.
20//  funct   - combined with opcode field give us an operation code.
21//
22//===----------------------------------------------------------------------===//
23
24// Format specifies the encoding used by the instruction.  This is part of the
25// ad-hoc solution used to emit machine instruction encodings by our machine
26// code emitter.
27class Format<bits<4> val> {
28  bits<4> Value = val;
29}
30
31def Pseudo    : Format<0>;
32def FrmR      : Format<1>;
33def FrmI      : Format<2>;
34def FrmJ      : Format<3>;
35def FrmFR     : Format<4>;
36def FrmFI     : Format<5>;
37def FrmOther  : Format<6>; // Instruction w/ a custom format
38
39class MMRel;
40
41def Std2MicroMips : InstrMapping {
42  let FilterClass = "MMRel";
43  // Instructions with the same BaseOpcode and isNVStore values form a row.
44  let RowFields = ["BaseOpcode"];
45  // Instructions with the same predicate sense form a column.
46  let ColFields = ["Arch"];
47  // The key column is the unpredicated instructions.
48  let KeyCol = ["se"];
49  // Value columns are PredSense=true and PredSense=false
50  let ValueCols = [["se"], ["micromips"]];
51}
52
53class StdMMR6Rel;
54
55def Std2MicroMipsR6 : InstrMapping {
56  let FilterClass = "StdMMR6Rel";
57  // Instructions with the same BaseOpcode and isNVStore values form a row.
58  let RowFields = ["BaseOpcode"];
59  // Instructions with the same predicate sense form a column.
60  let ColFields = ["Arch"];
61  // The key column is the unpredicated instructions.
62  let KeyCol = ["se"];
63  // Value columns are PredSense=true and PredSense=false
64  let ValueCols = [["se"], ["micromipsr6"]];
65}
66
67class StdArch {
68  string Arch = "se";
69}
70
71// Generic Mips Format
72class MipsInst<dag outs, dag ins, string asmstr, list<dag> pattern,
73               InstrItinClass itin, Format f>: Instruction
74{
75  field bits<32> Inst;
76  Format Form = f;
77
78  let Namespace = "Mips";
79
80  let Size = 4;
81
82  bits<6> Opcode = 0;
83
84  // Top 6 bits are the 'opcode' field
85  let Inst{31-26} = Opcode;
86
87  let OutOperandList = outs;
88  let InOperandList  = ins;
89
90  let AsmString   = asmstr;
91  let Pattern     = pattern;
92  let Itinerary   = itin;
93
94  //
95  // Attributes specific to Mips instructions...
96  //
97  bits<4> FormBits     = Form.Value;
98  bit isCTI            = 0; // Any form of Control Transfer Instruction.
99                            // Required for MIPSR6
100  bit hasForbiddenSlot = 0; // Instruction has a forbidden slot.
101  bit IsPCRelativeLoad = 0; // Load instruction with implicit source register
102                            // ($pc) and with explicit offset and destination
103                            // register
104
105  // TSFlags layout should be kept in sync with MipsInstrInfo.h.
106  let TSFlags{3-0}   = FormBits;
107  let TSFlags{4}     = isCTI;
108  let TSFlags{5}     = hasForbiddenSlot;
109  let TSFlags{6}     = IsPCRelativeLoad;
110
111  let DecoderNamespace = "Mips";
112
113  field bits<32> SoftFail = 0;
114}
115
116// Mips32/64 Instruction Format
117class InstSE<dag outs, dag ins, string asmstr, list<dag> pattern,
118             InstrItinClass itin, Format f, string opstr = ""> :
119  MipsInst<outs, ins, asmstr, pattern, itin, f>, PredicateControl {
120  let EncodingPredicates = [HasStdEnc];
121  string BaseOpcode = opstr;
122  string Arch;
123}
124
125// Mips Pseudo Instructions Format
126class MipsPseudo<dag outs, dag ins, list<dag> pattern,
127                 InstrItinClass itin = IIPseudo> :
128  MipsInst<outs, ins, "", pattern, itin, Pseudo> {
129  let isCodeGenOnly = 1;
130  let isPseudo = 1;
131}
132
133// Mips32/64 Pseudo Instruction Format
134class PseudoSE<dag outs, dag ins, list<dag> pattern,
135               InstrItinClass itin = IIPseudo> :
136  MipsPseudo<outs, ins, pattern, itin>, PredicateControl {
137  let EncodingPredicates = [HasStdEnc];
138}
139
140// Pseudo-instructions for alternate assembly syntax (never used by codegen).
141// These are aliases that require C++ handling to convert to the target
142// instruction, while InstAliases can be handled directly by tblgen.
143class MipsAsmPseudoInst<dag outs, dag ins, string asmstr>:
144  MipsInst<outs, ins, asmstr, [], IIPseudo, Pseudo>, PredicateControl {
145  let isPseudo = 1;
146  let Pattern = [];
147}
148//===----------------------------------------------------------------------===//
149// Format R instruction class in Mips : <|opcode|rs|rt|rd|shamt|funct|>
150//===----------------------------------------------------------------------===//
151
152class FR<bits<6> op, bits<6> _funct, dag outs, dag ins, string asmstr,
153         list<dag> pattern, InstrItinClass itin>:
154  InstSE<outs, ins, asmstr, pattern, itin, FrmR>
155{
156  bits<5>  rd;
157  bits<5>  rs;
158  bits<5>  rt;
159  bits<5>  shamt;
160  bits<6>  funct;
161
162  let Opcode = op;
163  let funct  = _funct;
164
165  let Inst{25-21} = rs;
166  let Inst{20-16} = rt;
167  let Inst{15-11} = rd;
168  let Inst{10-6}  = shamt;
169  let Inst{5-0}   = funct;
170}
171
172//===----------------------------------------------------------------------===//
173// Format I instruction class in Mips : <|opcode|rs|rt|immediate|>
174//===----------------------------------------------------------------------===//
175
176class FI<bits<6> op, dag outs, dag ins, string asmstr, list<dag> pattern,
177         InstrItinClass itin>: InstSE<outs, ins, asmstr, pattern, itin, FrmI>
178{
179  bits<5>  rt;
180  bits<5>  rs;
181  bits<16> imm16;
182
183  let Opcode = op;
184
185  let Inst{25-21} = rs;
186  let Inst{20-16} = rt;
187  let Inst{15-0}  = imm16;
188}
189
190class BranchBase<bits<6> op, dag outs, dag ins, string asmstr,
191                  list<dag> pattern, InstrItinClass itin>:
192  InstSE<outs, ins, asmstr, pattern, itin, FrmI>
193{
194  bits<5>  rs;
195  bits<5>  rt;
196  bits<16> imm16;
197
198  let Opcode = op;
199
200  let Inst{25-21} = rs;
201  let Inst{20-16} = rt;
202  let Inst{15-0}  = imm16;
203}
204
205//===----------------------------------------------------------------------===//
206// Format J instruction class in Mips : <|opcode|address|>
207//===----------------------------------------------------------------------===//
208
209class FJ<bits<6> op> : StdArch
210{
211  bits<26> target;
212
213  bits<32> Inst;
214
215  let Inst{31-26} = op;
216  let Inst{25-0}  = target;
217}
218
219//===----------------------------------------------------------------------===//
220// MFC instruction class in Mips : <|op|mf|rt|rd|0000000|sel|>
221//===----------------------------------------------------------------------===//
222class MFC3OP_FM<bits<6> op, bits<5> mfmt>
223{
224  bits<5> rt;
225  bits<5> rd;
226  bits<3> sel;
227
228  bits<32> Inst;
229
230  let Inst{31-26} = op;
231  let Inst{25-21} = mfmt;
232  let Inst{20-16} = rt;
233  let Inst{15-11} = rd;
234  let Inst{10-3}  = 0;
235  let Inst{2-0}   = sel;
236}
237
238class MFC2OP_FM<bits<6> op, bits<5> mfmt> : StdArch {
239  bits<5>  rt;
240  bits<16> imm16;
241
242  bits<32> Inst;
243
244  let Inst{31-26} = op;
245  let Inst{25-21} = mfmt;
246  let Inst{20-16} = rt;
247  let Inst{15-0}  = imm16;
248}
249
250class ADD_FM<bits<6> op, bits<6> funct> : StdArch {
251  bits<5> rd;
252  bits<5> rs;
253  bits<5> rt;
254
255  bits<32> Inst;
256
257  let Inst{31-26} = op;
258  let Inst{25-21} = rs;
259  let Inst{20-16} = rt;
260  let Inst{15-11} = rd;
261  let Inst{10-6}  = 0;
262  let Inst{5-0}   = funct;
263}
264
265class ADDI_FM<bits<6> op> : StdArch {
266  bits<5>  rs;
267  bits<5>  rt;
268  bits<16> imm16;
269
270  bits<32> Inst;
271
272  let Inst{31-26} = op;
273  let Inst{25-21} = rs;
274  let Inst{20-16} = rt;
275  let Inst{15-0}  = imm16;
276}
277
278class SRA_FM<bits<6> funct, bit rotate> : StdArch {
279  bits<5> rd;
280  bits<5> rt;
281  bits<5> shamt;
282
283  bits<32> Inst;
284
285  let Inst{31-26} = 0;
286  let Inst{25-22} = 0;
287  let Inst{21}    = rotate;
288  let Inst{20-16} = rt;
289  let Inst{15-11} = rd;
290  let Inst{10-6}  = shamt;
291  let Inst{5-0}   = funct;
292}
293
294class SRLV_FM<bits<6> funct, bit rotate> : StdArch {
295  bits<5> rd;
296  bits<5> rt;
297  bits<5> rs;
298
299  bits<32> Inst;
300
301  let Inst{31-26} = 0;
302  let Inst{25-21} = rs;
303  let Inst{20-16} = rt;
304  let Inst{15-11} = rd;
305  let Inst{10-7}  = 0;
306  let Inst{6}     = rotate;
307  let Inst{5-0}   = funct;
308}
309
310class BEQ_FM<bits<6> op> : StdArch {
311  bits<5>  rs;
312  bits<5>  rt;
313  bits<16> offset;
314
315  bits<32> Inst;
316
317  let Inst{31-26} = op;
318  let Inst{25-21} = rs;
319  let Inst{20-16} = rt;
320  let Inst{15-0}  = offset;
321}
322
323class BGEZ_FM<bits<6> op, bits<5> funct> : StdArch {
324  bits<5>  rs;
325  bits<16> offset;
326
327  bits<32> Inst;
328
329  let Inst{31-26} = op;
330  let Inst{25-21} = rs;
331  let Inst{20-16} = funct;
332  let Inst{15-0}  = offset;
333}
334
335class BBIT_FM<bits<6> op> : StdArch {
336  bits<5>  rs;
337  bits<5>  p;
338  bits<16> offset;
339
340  bits<32> Inst;
341
342  let Inst{31-26} = op;
343  let Inst{25-21} = rs;
344  let Inst{20-16} = p;
345  let Inst{15-0}  = offset;
346}
347
348class SLTI_FM<bits<6> op> : StdArch {
349  bits<5> rt;
350  bits<5> rs;
351  bits<16> imm16;
352
353  bits<32> Inst;
354
355  let Inst{31-26} = op;
356  let Inst{25-21} = rs;
357  let Inst{20-16} = rt;
358  let Inst{15-0}  = imm16;
359}
360
361class MFLO_FM<bits<6> funct> : StdArch {
362  bits<5> rd;
363
364  bits<32> Inst;
365
366  let Inst{31-26} = 0;
367  let Inst{25-16} = 0;
368  let Inst{15-11} = rd;
369  let Inst{10-6}  = 0;
370  let Inst{5-0}   = funct;
371}
372
373class MTLO_FM<bits<6> funct> : StdArch {
374  bits<5> rs;
375
376  bits<32> Inst;
377
378  let Inst{31-26} = 0;
379  let Inst{25-21} = rs;
380  let Inst{20-6}  = 0;
381  let Inst{5-0}   = funct;
382}
383
384class SEB_FM<bits<5> funct, bits<6> funct2> : StdArch {
385  bits<5> rd;
386  bits<5> rt;
387
388  bits<32> Inst;
389
390  let Inst{31-26} = 0x1f;
391  let Inst{25-21} = 0;
392  let Inst{20-16} = rt;
393  let Inst{15-11} = rd;
394  let Inst{10-6}  = funct;
395  let Inst{5-0}   = funct2;
396}
397
398class CLO_FM<bits<6> funct> : StdArch {
399  bits<5> rd;
400  bits<5> rs;
401  bits<5> rt;
402
403  bits<32> Inst;
404
405  let Inst{31-26} = 0x1c;
406  let Inst{25-21} = rs;
407  let Inst{20-16} = rt;
408  let Inst{15-11} = rd;
409  let Inst{10-6}  = 0;
410  let Inst{5-0}   = funct;
411  let rt = rd;
412}
413
414class LUI_FM : StdArch {
415  bits<5> rt;
416  bits<16> imm16;
417
418  bits<32> Inst;
419
420  let Inst{31-26} = 0xf;
421  let Inst{25-21} = 0;
422  let Inst{20-16} = rt;
423  let Inst{15-0}  = imm16;
424}
425
426class JALR_FM {
427  bits<5> rd;
428  bits<5> rs;
429
430  bits<32> Inst;
431
432  let Inst{31-26} = 0;
433  let Inst{25-21} = rs;
434  let Inst{20-16} = 0;
435  let Inst{15-11} = rd;
436  let Inst{10-6}  = 0;
437  let Inst{5-0}   = 9;
438}
439
440class BGEZAL_FM<bits<5> funct> : StdArch {
441  bits<5>  rs;
442  bits<16> offset;
443
444  bits<32> Inst;
445
446  let Inst{31-26} = 1;
447  let Inst{25-21} = rs;
448  let Inst{20-16} = funct;
449  let Inst{15-0}  = offset;
450}
451
452class SYNC_FM : StdArch {
453  bits<5> stype;
454
455  bits<32> Inst;
456
457  let Inst{31-26} = 0;
458  let Inst{10-6}  = stype;
459  let Inst{5-0}   = 0xf;
460}
461
462class SYNCI_FM : StdArch {
463  // Produced by the mem_simm16 address as reg << 16 | imm (see getMemEncoding).
464  bits<21> addr;
465  bits<5> rs = addr{20-16};
466  bits<16> offset = addr{15-0};
467
468  bits<32> Inst;
469
470  let Inst{31-26} = 0b000001;
471  let Inst{25-21} = rs;
472  let Inst{20-16} = 0b11111;
473  let Inst{15-0}  = offset;
474}
475
476class MULT_FM<bits<6> op, bits<6> funct> : StdArch {
477  bits<5>  rs;
478  bits<5>  rt;
479
480  bits<32> Inst;
481
482  let Inst{31-26} = op;
483  let Inst{25-21} = rs;
484  let Inst{20-16} = rt;
485  let Inst{15-6}  = 0;
486  let Inst{5-0}   = funct;
487}
488
489class EXT_FM<bits<6> funct> : StdArch {
490  bits<5> rt;
491  bits<5> rs;
492  bits<5> pos;
493  bits<5> size;
494
495  bits<32> Inst;
496
497  let Inst{31-26} = 0x1f;
498  let Inst{25-21} = rs;
499  let Inst{20-16} = rt;
500  let Inst{15-11} = size;
501  let Inst{10-6}  = pos;
502  let Inst{5-0}   = funct;
503}
504
505class RDHWR_FM : StdArch {
506  bits<5> rt;
507  bits<5> rd;
508
509  bits<32> Inst;
510
511  let Inst{31-26} = 0x1f;
512  let Inst{25-21} = 0;
513  let Inst{20-16} = rt;
514  let Inst{15-11} = rd;
515  let Inst{10-6}  = 0;
516  let Inst{5-0}   = 0x3b;
517}
518
519class TEQ_FM<bits<6> funct> : StdArch {
520  bits<5> rs;
521  bits<5> rt;
522  bits<10> code_;
523
524  bits<32> Inst;
525
526  let Inst{31-26} = 0;
527  let Inst{25-21} = rs;
528  let Inst{20-16} = rt;
529  let Inst{15-6}  = code_;
530  let Inst{5-0}   = funct;
531}
532
533class TEQI_FM<bits<5> funct> : StdArch {
534  bits<5> rs;
535  bits<16> imm16;
536
537  bits<32> Inst;
538
539  let Inst{31-26} = 1;
540  let Inst{25-21} = rs;
541  let Inst{20-16}   = funct;
542  let Inst{15-0}  = imm16;
543}
544
545class WAIT_FM : StdArch {
546  bits<32> Inst;
547
548  let Inst{31-26} = 0x10;
549  let Inst{25}    = 1;
550  let Inst{24-6}  = 0;
551  let Inst{5-0}   = 0x20;
552}
553
554class EXTS_FM<bits<6> funct> : StdArch {
555  bits<5> rt;
556  bits<5> rs;
557  bits<5> pos;
558  bits<5> lenm1;
559
560  bits<32> Inst;
561
562  let Inst{31-26} = 0x1c;
563  let Inst{25-21} = rs;
564  let Inst{20-16} = rt;
565  let Inst{15-11} = lenm1;
566  let Inst{10-6}  = pos;
567  let Inst{5-0}   = funct;
568}
569
570class MTMR_FM<bits<6> funct> : StdArch {
571  bits<5> rs;
572
573  bits<32> Inst;
574
575  let Inst{31-26} = 0x1c;
576  let Inst{25-21} = rs;
577  let Inst{20-6}  = 0;
578  let Inst{5-0}   = funct;
579}
580
581class POP_FM<bits<6> funct> : StdArch {
582  bits<5> rd;
583  bits<5> rs;
584
585  bits<32> Inst;
586
587  let Inst{31-26} = 0x1c;
588  let Inst{25-21} = rs;
589  let Inst{20-16} = 0;
590  let Inst{15-11} = rd;
591  let Inst{10-6}  = 0;
592  let Inst{5-0}   = funct;
593}
594
595class SEQ_FM<bits<6> funct> : StdArch {
596  bits<5> rd;
597  bits<5> rs;
598  bits<5> rt;
599
600  bits<32> Inst;
601
602  let Inst{31-26} = 0x1c;
603  let Inst{25-21} = rs;
604  let Inst{20-16} = rt;
605  let Inst{15-11} = rd;
606  let Inst{10-6}  = 0;
607  let Inst{5-0}   = funct;
608}
609
610class SEQI_FM<bits<6> funct> : StdArch {
611  bits<5> rs;
612  bits<5> rt;
613  bits<10> imm10;
614
615  bits<32> Inst;
616
617  let Inst{31-26} = 0x1c;
618  let Inst{25-21} = rs;
619  let Inst{20-16} = rt;
620  let Inst{15-6}  = imm10;
621  let Inst{5-0}   = funct;
622}
623
624//===----------------------------------------------------------------------===//
625//  System calls format <op|code_|funct>
626//===----------------------------------------------------------------------===//
627
628class SYS_FM<bits<6> funct> : StdArch
629{
630  bits<20> code_;
631  bits<32> Inst;
632  let Inst{31-26} = 0x0;
633  let Inst{25-6} = code_;
634  let Inst{5-0}  = funct;
635}
636
637//===----------------------------------------------------------------------===//
638//  Break instruction format <op|code_1|funct>
639//===----------------------------------------------------------------------===//
640
641class BRK_FM<bits<6> funct> : StdArch
642{
643  bits<10> code_1;
644  bits<10> code_2;
645  bits<32> Inst;
646  let Inst{31-26} = 0x0;
647  let Inst{25-16} = code_1;
648  let Inst{15-6}  = code_2;
649  let Inst{5-0}   = funct;
650}
651
652//===----------------------------------------------------------------------===//
653//  Exception return format <Cop0|1|0|funct>
654//===----------------------------------------------------------------------===//
655
656class ER_FM<bits<6> funct, bit LLBit> : StdArch
657{
658  bits<32> Inst;
659  let Inst{31-26} = 0x10;
660  let Inst{25}    = 1;
661  let Inst{24-7}  = 0;
662  let Inst{6} = LLBit;
663  let Inst{5-0}   = funct;
664}
665
666//===----------------------------------------------------------------------===//
667//  Enable/disable interrupt instruction format <Cop0|MFMC0|rt|12|0|sc|0|0>
668//===----------------------------------------------------------------------===//
669
670class EI_FM<bits<1> sc> : StdArch
671{
672  bits<32> Inst;
673  bits<5> rt;
674  let Inst{31-26} = 0x10;
675  let Inst{25-21} = 0xb;
676  let Inst{20-16} = rt;
677  let Inst{15-11} = 0xc;
678  let Inst{10-6}  = 0;
679  let Inst{5}     = sc;
680  let Inst{4-0}   = 0;
681}
682
683//===----------------------------------------------------------------------===//
684//
685//  FLOATING POINT INSTRUCTION FORMATS
686//
687//  opcode  - operation code.
688//  fs      - src reg.
689//  ft      - dst reg (on a 2 regs instr) or src reg (on a 3 reg instr).
690//  fd      - dst reg, only used on 3 regs instr.
691//  fmt     - double or single precision.
692//  funct   - combined with opcode field give us an operation code.
693//
694//===----------------------------------------------------------------------===//
695
696//===----------------------------------------------------------------------===//
697// Format FI instruction class in Mips : <|opcode|base|ft|immediate|>
698//===----------------------------------------------------------------------===//
699
700class FFI<bits<6> op, dag outs, dag ins, string asmstr, list<dag> pattern>:
701  InstSE<outs, ins, asmstr, pattern, NoItinerary, FrmFI>
702{
703  bits<5>  ft;
704  bits<5>  base;
705  bits<16> imm16;
706
707  let Opcode = op;
708
709  let Inst{25-21} = base;
710  let Inst{20-16} = ft;
711  let Inst{15-0}  = imm16;
712}
713
714class ADDS_FM<bits<6> funct, bits<5> fmt> : StdArch {
715  bits<5> fd;
716  bits<5> fs;
717  bits<5> ft;
718
719  bits<32> Inst;
720
721  let Inst{31-26} = 0x11;
722  let Inst{25-21} = fmt;
723  let Inst{20-16} = ft;
724  let Inst{15-11} = fs;
725  let Inst{10-6}  = fd;
726  let Inst{5-0}   = funct;
727}
728
729class ABSS_FM<bits<6> funct, bits<5> fmt> : StdArch {
730  bits<5> fd;
731  bits<5> fs;
732
733  bits<32> Inst;
734
735  let Inst{31-26} = 0x11;
736  let Inst{25-21} = fmt;
737  let Inst{20-16} = 0;
738  let Inst{15-11} = fs;
739  let Inst{10-6}  = fd;
740  let Inst{5-0}   = funct;
741}
742
743class MFC1_FM<bits<5> funct> : StdArch {
744  bits<5> rt;
745  bits<5> fs;
746
747  bits<32> Inst;
748
749  let Inst{31-26} = 0x11;
750  let Inst{25-21} = funct;
751  let Inst{20-16} = rt;
752  let Inst{15-11} = fs;
753  let Inst{10-0}  = 0;
754}
755
756class LW_FM<bits<6> op> : StdArch {
757  bits<5> rt;
758  bits<21> addr;
759
760  bits<32> Inst;
761
762  let Inst{31-26} = op;
763  let Inst{25-21} = addr{20-16};
764  let Inst{20-16} = rt;
765  let Inst{15-0}  = addr{15-0};
766}
767
768class MADDS_FM<bits<3> funct, bits<3> fmt> : StdArch {
769  bits<5> fd;
770  bits<5> fr;
771  bits<5> fs;
772  bits<5> ft;
773
774  bits<32> Inst;
775
776  let Inst{31-26} = 0x13;
777  let Inst{25-21} = fr;
778  let Inst{20-16} = ft;
779  let Inst{15-11} = fs;
780  let Inst{10-6}  = fd;
781  let Inst{5-3}   = funct;
782  let Inst{2-0}   = fmt;
783}
784
785class LWXC1_FM<bits<6> funct> : StdArch {
786  bits<5> fd;
787  bits<5> base;
788  bits<5> index;
789
790  bits<32> Inst;
791
792  let Inst{31-26} = 0x13;
793  let Inst{25-21} = base;
794  let Inst{20-16} = index;
795  let Inst{15-11} = 0;
796  let Inst{10-6}  = fd;
797  let Inst{5-0}   = funct;
798}
799
800class SWXC1_FM<bits<6> funct> : StdArch {
801  bits<5> fs;
802  bits<5> base;
803  bits<5> index;
804
805  bits<32> Inst;
806
807  let Inst{31-26} = 0x13;
808  let Inst{25-21} = base;
809  let Inst{20-16} = index;
810  let Inst{15-11} = fs;
811  let Inst{10-6}  = 0;
812  let Inst{5-0}   = funct;
813}
814
815class BC1F_FM<bit nd, bit tf> : StdArch {
816  bits<3>  fcc;
817  bits<16> offset;
818
819  bits<32> Inst;
820
821  let Inst{31-26} = 0x11;
822  let Inst{25-21} = 0x8;
823  let Inst{20-18} = fcc;
824  let Inst{17} = nd;
825  let Inst{16} = tf;
826  let Inst{15-0} = offset;
827}
828
829class CEQS_FM<bits<5> fmt> : StdArch {
830  bits<5> fs;
831  bits<5> ft;
832  bits<4> cond;
833
834  bits<32> Inst;
835
836  let Inst{31-26} = 0x11;
837  let Inst{25-21} = fmt;
838  let Inst{20-16} = ft;
839  let Inst{15-11} = fs;
840  let Inst{10-8} = 0; // cc
841  let Inst{7-4} = 0x3;
842  let Inst{3-0} = cond;
843}
844
845class C_COND_FM<bits<5> fmt, bits<4> c> : CEQS_FM<fmt> {
846  let cond = c;
847}
848
849class CMov_I_F_FM<bits<6> funct, bits<5> fmt> : StdArch {
850  bits<5> fd;
851  bits<5> fs;
852  bits<5> rt;
853
854  bits<32> Inst;
855
856  let Inst{31-26} = 0x11;
857  let Inst{25-21} = fmt;
858  let Inst{20-16} = rt;
859  let Inst{15-11} = fs;
860  let Inst{10-6} = fd;
861  let Inst{5-0} = funct;
862}
863
864class CMov_F_I_FM<bit tf> : StdArch {
865  bits<5> rd;
866  bits<5> rs;
867  bits<3> fcc;
868
869  bits<32> Inst;
870
871  let Inst{31-26} = 0;
872  let Inst{25-21} = rs;
873  let Inst{20-18} = fcc;
874  let Inst{17} = 0;
875  let Inst{16} = tf;
876  let Inst{15-11} = rd;
877  let Inst{10-6} = 0;
878  let Inst{5-0} = 1;
879}
880
881class CMov_F_F_FM<bits<5> fmt, bit tf> : StdArch {
882  bits<5> fd;
883  bits<5> fs;
884  bits<3> fcc;
885
886  bits<32> Inst;
887
888  let Inst{31-26} = 0x11;
889  let Inst{25-21} = fmt;
890  let Inst{20-18} = fcc;
891  let Inst{17} = 0;
892  let Inst{16} = tf;
893  let Inst{15-11} = fs;
894  let Inst{10-6} = fd;
895  let Inst{5-0} = 0x11;
896}
897
898class BARRIER_FM<bits<5> op> : StdArch {
899  bits<32> Inst;
900
901  let Inst{31-26} = 0; // SPECIAL
902  let Inst{25-21} = 0;
903  let Inst{20-16} = 0; // rt = 0
904  let Inst{15-11} = 0; // rd = 0
905  let Inst{10-6} = op; // Operation
906  let Inst{5-0} = 0;   // SLL
907}
908
909class SDBBP_FM : StdArch {
910  bits<20> code_;
911
912  bits<32> Inst;
913
914  let Inst{31-26} = 0b011100; // SPECIAL2
915  let Inst{25-6} = code_;
916  let Inst{5-0} = 0b111111;   // SDBBP
917}
918
919class JR_HB_FM<bits<6> op> : StdArch{
920  bits<5> rs;
921
922  bits<32> Inst;
923
924  let Inst{31-26} = 0; // SPECIAL
925  let Inst{25-21} = rs;
926  let Inst{20-11} = 0;
927  let Inst{10} = 1;
928  let Inst{9-6} = 0;
929  let Inst{5-0} = op;
930}
931
932class JALR_HB_FM<bits<6> op> : StdArch {
933  bits<5> rd;
934  bits<5> rs;
935
936  bits<32> Inst;
937
938  let Inst{31-26} = 0; // SPECIAL
939  let Inst{25-21} = rs;
940  let Inst{20-16} = 0;
941  let Inst{15-11} = rd;
942  let Inst{10} = 1;
943  let Inst{9-6} = 0;
944  let Inst{5-0} = op;
945}
946
947class COP0_TLB_FM<bits<6> op> : StdArch {
948  bits<32> Inst;
949
950  let Inst{31-26} = 0x10; // COP0
951  let Inst{25} = 1;       // CO
952  let Inst{24-6} = 0;
953  let Inst{5-0} = op;     // Operation
954}
955
956class CACHEOP_FM<bits<6> op> : StdArch {
957  bits<21> addr;
958  bits<5> hint;
959  bits<5> base = addr{20-16};
960  bits<16> offset = addr{15-0};
961
962  bits<32> Inst;
963
964  let Inst{31-26} = op;
965  let Inst{25-21} = base;
966  let Inst{20-16} = hint;
967  let Inst{15-0}  = offset;
968}
969