1//===-- MipsInstrFPU.td - Mips FPU Instruction Information -*- tablegen -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file describes the Mips FPU instruction set. 11// 12//===----------------------------------------------------------------------===// 13 14//===----------------------------------------------------------------------===// 15// Floating Point Instructions 16// ------------------------ 17// * 64bit fp: 18// - 32 64-bit registers (default mode) 19// - 16 even 32-bit registers (32-bit compatible mode) for 20// single and double access. 21// * 32bit fp: 22// - 16 even 32-bit registers - single and double (aliased) 23// - 32 32-bit registers (within single-only mode) 24//===----------------------------------------------------------------------===// 25 26// Floating Point Compare and Branch 27def SDT_MipsFPBrcond : SDTypeProfile<0, 3, [SDTCisInt<0>, 28 SDTCisVT<1, i32>, 29 SDTCisVT<2, OtherVT>]>; 30def SDT_MipsFPCmp : SDTypeProfile<0, 3, [SDTCisSameAs<0, 1>, SDTCisFP<1>, 31 SDTCisVT<2, i32>]>; 32def SDT_MipsCMovFP : SDTypeProfile<1, 3, [SDTCisSameAs<0, 1>, SDTCisVT<2, i32>, 33 SDTCisSameAs<1, 3>]>; 34def SDT_MipsTruncIntFP : SDTypeProfile<1, 1, [SDTCisFP<0>, SDTCisFP<1>]>; 35def SDT_MipsBuildPairF64 : SDTypeProfile<1, 2, [SDTCisVT<0, f64>, 36 SDTCisVT<1, i32>, 37 SDTCisSameAs<1, 2>]>; 38def SDT_MipsExtractElementF64 : SDTypeProfile<1, 2, [SDTCisVT<0, i32>, 39 SDTCisVT<1, f64>, 40 SDTCisVT<2, i32>]>; 41 42def MipsFPCmp : SDNode<"MipsISD::FPCmp", SDT_MipsFPCmp, [SDNPOutGlue]>; 43def MipsCMovFP_T : SDNode<"MipsISD::CMovFP_T", SDT_MipsCMovFP, [SDNPInGlue]>; 44def MipsCMovFP_F : SDNode<"MipsISD::CMovFP_F", SDT_MipsCMovFP, [SDNPInGlue]>; 45def MipsFPBrcond : SDNode<"MipsISD::FPBrcond", SDT_MipsFPBrcond, 46 [SDNPHasChain, SDNPOptInGlue]>; 47def MipsTruncIntFP : SDNode<"MipsISD::TruncIntFP", SDT_MipsTruncIntFP>; 48def MipsBuildPairF64 : SDNode<"MipsISD::BuildPairF64", SDT_MipsBuildPairF64>; 49def MipsExtractElementF64 : SDNode<"MipsISD::ExtractElementF64", 50 SDT_MipsExtractElementF64>; 51 52// Operand for printing out a condition code. 53let PrintMethod = "printFCCOperand", DecoderMethod = "DecodeCondCode" in 54 def condcode : Operand<i32>; 55 56//===----------------------------------------------------------------------===// 57// Feature predicates. 58//===----------------------------------------------------------------------===// 59 60def IsFP64bit : Predicate<"Subtarget->isFP64bit()">, 61 AssemblerPredicate<"FeatureFP64Bit">; 62def NotFP64bit : Predicate<"!Subtarget->isFP64bit()">, 63 AssemblerPredicate<"!FeatureFP64Bit">; 64def IsSingleFloat : Predicate<"Subtarget->isSingleFloat()">, 65 AssemblerPredicate<"FeatureSingleFloat">; 66def IsNotSingleFloat : Predicate<"!Subtarget->isSingleFloat()">, 67 AssemblerPredicate<"!FeatureSingleFloat">; 68 69//===----------------------------------------------------------------------===// 70// Mips FGR size adjectives. 71// They are mutually exclusive. 72//===----------------------------------------------------------------------===// 73 74class FGR_32 { list<Predicate> FGRPredicates = [NotFP64bit]; } 75class FGR_64 { list<Predicate> FGRPredicates = [IsFP64bit]; } 76 77//===----------------------------------------------------------------------===// 78 79// FP immediate patterns. 80def fpimm0 : PatLeaf<(fpimm), [{ 81 return N->isExactlyValue(+0.0); 82}]>; 83 84def fpimm0neg : PatLeaf<(fpimm), [{ 85 return N->isExactlyValue(-0.0); 86}]>; 87 88//===----------------------------------------------------------------------===// 89// Instruction Class Templates 90// 91// A set of multiclasses is used to address the register usage. 92// 93// S32 - single precision in 16 32bit even fp registers 94// single precision in 32 32bit fp registers in SingleOnly mode 95// S64 - single precision in 32 64bit fp registers (In64BitMode) 96// D32 - double precision in 16 32bit even fp registers 97// D64 - double precision in 32 64bit fp registers (In64BitMode) 98// 99// Only S32 and D32 are supported right now. 100//===----------------------------------------------------------------------===// 101 102class ADDS_FT<string opstr, RegisterOperand RC, InstrItinClass Itin, bit IsComm, 103 SDPatternOperator OpNode= null_frag> : 104 InstSE<(outs RC:$fd), (ins RC:$fs, RC:$ft), 105 !strconcat(opstr, "\t$fd, $fs, $ft"), 106 [(set RC:$fd, (OpNode RC:$fs, RC:$ft))], Itin, FrmFR, opstr> { 107 let isCommutable = IsComm; 108} 109 110multiclass ADDS_M<string opstr, InstrItinClass Itin, bit IsComm, 111 SDPatternOperator OpNode = null_frag> { 112 def _D32 : MMRel, ADDS_FT<opstr, AFGR64Opnd, Itin, IsComm, OpNode>, 113 AdditionalRequires<[NotFP64bit]>; 114 def _D64 : ADDS_FT<opstr, FGR64Opnd, Itin, 115 IsComm, OpNode>, 116 AdditionalRequires<[IsFP64bit]> { 117 string DecoderNamespace = "Mips64"; 118 } 119} 120 121class ABSS_FT<string opstr, RegisterOperand DstRC, RegisterOperand SrcRC, 122 InstrItinClass Itin, SDPatternOperator OpNode= null_frag> : 123 InstSE<(outs DstRC:$fd), (ins SrcRC:$fs), !strconcat(opstr, "\t$fd, $fs"), 124 [(set DstRC:$fd, (OpNode SrcRC:$fs))], Itin, FrmFR, opstr>, 125 NeverHasSideEffects; 126 127multiclass ABSS_M<string opstr, InstrItinClass Itin, 128 SDPatternOperator OpNode= null_frag> { 129 def _D32 : MMRel, ABSS_FT<opstr, AFGR64Opnd, AFGR64Opnd, Itin, OpNode>, 130 AdditionalRequires<[NotFP64bit]>; 131 def _D64 : ABSS_FT<opstr, FGR64Opnd, FGR64Opnd, Itin, OpNode>, 132 AdditionalRequires<[IsFP64bit]> { 133 string DecoderNamespace = "Mips64"; 134 } 135} 136 137multiclass ROUND_M<string opstr, InstrItinClass Itin> { 138 def _D32 : MMRel, ABSS_FT<opstr, FGR32Opnd, AFGR64Opnd, Itin>, 139 AdditionalRequires<[NotFP64bit]>; 140 def _D64 : ABSS_FT<opstr, FGR32Opnd, FGR64Opnd, Itin>, 141 AdditionalRequires<[IsFP64bit]> { 142 let DecoderNamespace = "Mips64"; 143 } 144} 145 146class MFC1_FT<string opstr, RegisterOperand DstRC, RegisterOperand SrcRC, 147 InstrItinClass Itin, SDPatternOperator OpNode= null_frag> : 148 InstSE<(outs DstRC:$rt), (ins SrcRC:$fs), !strconcat(opstr, "\t$rt, $fs"), 149 [(set DstRC:$rt, (OpNode SrcRC:$fs))], Itin, FrmFR, opstr>; 150 151class MTC1_FT<string opstr, RegisterOperand DstRC, RegisterOperand SrcRC, 152 InstrItinClass Itin, SDPatternOperator OpNode= null_frag> : 153 InstSE<(outs DstRC:$fs), (ins SrcRC:$rt), !strconcat(opstr, "\t$rt, $fs"), 154 [(set DstRC:$fs, (OpNode SrcRC:$rt))], Itin, FrmFR, opstr>; 155 156class MTC1_64_FT<string opstr, RegisterOperand DstRC, RegisterOperand SrcRC, 157 InstrItinClass Itin> : 158 InstSE<(outs DstRC:$fs), (ins DstRC:$fs_in, SrcRC:$rt), 159 !strconcat(opstr, "\t$rt, $fs"), [], Itin, FrmFR, opstr> { 160 // $fs_in is part of a white lie to work around a widespread bug in the FPU 161 // implementation. See expandBuildPairF64 for details. 162 let Constraints = "$fs = $fs_in"; 163} 164 165class LW_FT<string opstr, RegisterOperand RC, InstrItinClass Itin, 166 SDPatternOperator OpNode= null_frag> : 167 InstSE<(outs RC:$rt), (ins mem:$addr), !strconcat(opstr, "\t$rt, $addr"), 168 [(set RC:$rt, (OpNode addrDefault:$addr))], Itin, FrmFI, opstr> { 169 let DecoderMethod = "DecodeFMem"; 170 let mayLoad = 1; 171} 172 173class SW_FT<string opstr, RegisterOperand RC, InstrItinClass Itin, 174 SDPatternOperator OpNode= null_frag> : 175 InstSE<(outs), (ins RC:$rt, mem:$addr), !strconcat(opstr, "\t$rt, $addr"), 176 [(OpNode RC:$rt, addrDefault:$addr)], Itin, FrmFI, opstr> { 177 let DecoderMethod = "DecodeFMem"; 178 let mayStore = 1; 179} 180 181class SW_FT2<string opstr, RegisterOperand RC, InstrItinClass Itin, 182 SDPatternOperator OpNode= null_frag> : 183 InstSE<(outs), (ins RC:$rt, mem:$addr), !strconcat(opstr, "\t$rt, $addr"), 184 [(OpNode RC:$rt, addrDefault:$addr)], Itin, FrmFI, opstr> { 185 let DecoderMethod = "DecodeFMem2"; 186 let mayStore = 1; 187} 188 189class LW_FT2<string opstr, RegisterOperand RC, InstrItinClass Itin, 190 SDPatternOperator OpNode= null_frag> : 191 InstSE<(outs RC:$rt), (ins mem:$addr), !strconcat(opstr, "\t$rt, $addr"), 192 [(set RC:$rt, (OpNode addrDefault:$addr))], Itin, FrmFI, opstr> { 193 let DecoderMethod = "DecodeFMem2"; 194 let mayLoad = 1; 195} 196 197class SW_FT3<string opstr, RegisterOperand RC, InstrItinClass Itin, 198 SDPatternOperator OpNode= null_frag> : 199 InstSE<(outs), (ins RC:$rt, mem:$addr), !strconcat(opstr, "\t$rt, $addr"), 200 [(OpNode RC:$rt, addrDefault:$addr)], Itin, FrmFI, opstr> { 201 let DecoderMethod = "DecodeFMem3"; 202 let mayStore = 1; 203} 204 205class LW_FT3<string opstr, RegisterOperand RC, InstrItinClass Itin, 206 SDPatternOperator OpNode= null_frag> : 207 InstSE<(outs RC:$rt), (ins mem:$addr), !strconcat(opstr, "\t$rt, $addr"), 208 [(set RC:$rt, (OpNode addrDefault:$addr))], Itin, FrmFI, opstr> { 209 let DecoderMethod = "DecodeFMem3"; 210 let mayLoad = 1; 211} 212 213class MADDS_FT<string opstr, RegisterOperand RC, InstrItinClass Itin, 214 SDPatternOperator OpNode = null_frag> : 215 InstSE<(outs RC:$fd), (ins RC:$fr, RC:$fs, RC:$ft), 216 !strconcat(opstr, "\t$fd, $fr, $fs, $ft"), 217 [(set RC:$fd, (OpNode (fmul RC:$fs, RC:$ft), RC:$fr))], Itin, 218 FrmFR, opstr>; 219 220class NMADDS_FT<string opstr, RegisterOperand RC, InstrItinClass Itin, 221 SDPatternOperator OpNode = null_frag> : 222 InstSE<(outs RC:$fd), (ins RC:$fr, RC:$fs, RC:$ft), 223 !strconcat(opstr, "\t$fd, $fr, $fs, $ft"), 224 [(set RC:$fd, (fsub fpimm0, (OpNode (fmul RC:$fs, RC:$ft), RC:$fr)))], 225 Itin, FrmFR, opstr>; 226 227class LWXC1_FT<string opstr, RegisterOperand DRC, 228 InstrItinClass Itin, SDPatternOperator OpNode = null_frag> : 229 InstSE<(outs DRC:$fd), (ins PtrRC:$base, PtrRC:$index), 230 !strconcat(opstr, "\t$fd, ${index}(${base})"), 231 [(set DRC:$fd, (OpNode (add iPTR:$base, iPTR:$index)))], Itin, 232 FrmFI, opstr> { 233 let AddedComplexity = 20; 234} 235 236class SWXC1_FT<string opstr, RegisterOperand DRC, 237 InstrItinClass Itin, SDPatternOperator OpNode = null_frag> : 238 InstSE<(outs), (ins DRC:$fs, PtrRC:$base, PtrRC:$index), 239 !strconcat(opstr, "\t$fs, ${index}(${base})"), 240 [(OpNode DRC:$fs, (add iPTR:$base, iPTR:$index))], Itin, 241 FrmFI, opstr> { 242 let AddedComplexity = 20; 243} 244 245class BC1F_FT<string opstr, DAGOperand opnd, InstrItinClass Itin, 246 SDPatternOperator Op = null_frag> : 247 InstSE<(outs), (ins FCCRegsOpnd:$fcc, opnd:$offset), 248 !strconcat(opstr, "\t$fcc, $offset"), 249 [(MipsFPBrcond Op, FCCRegsOpnd:$fcc, bb:$offset)], Itin, 250 FrmFI, opstr> { 251 let isBranch = 1; 252 let isTerminator = 1; 253 let hasDelaySlot = 1; 254 let Defs = [AT]; 255} 256 257class CEQS_FT<string typestr, RegisterClass RC, InstrItinClass Itin, 258 SDPatternOperator OpNode = null_frag> : 259 InstSE<(outs), (ins RC:$fs, RC:$ft, condcode:$cond), 260 !strconcat("c.$cond.", typestr, "\t$fs, $ft"), 261 [(OpNode RC:$fs, RC:$ft, imm:$cond)], Itin, FrmFR, 262 !strconcat("c.$cond.", typestr)> { 263 let Defs = [FCC0]; 264 let isCodeGenOnly = 1; 265} 266 267class C_COND_FT<string CondStr, string Typestr, RegisterOperand RC, 268 InstrItinClass itin> : 269 InstSE<(outs), (ins RC:$fs, RC:$ft), 270 !strconcat("c.", CondStr, ".", Typestr, "\t$fs, $ft"), [], itin, 271 FrmFR>; 272 273multiclass C_COND_M<string TypeStr, RegisterOperand RC, bits<5> fmt, 274 InstrItinClass itin> { 275 def C_F_#NAME : C_COND_FT<"f", TypeStr, RC, itin>, C_COND_FM<fmt, 0>; 276 def C_UN_#NAME : C_COND_FT<"un", TypeStr, RC, itin>, C_COND_FM<fmt, 1>; 277 def C_EQ_#NAME : C_COND_FT<"eq", TypeStr, RC, itin>, C_COND_FM<fmt, 2>; 278 def C_UEQ_#NAME : C_COND_FT<"ueq", TypeStr, RC, itin>, C_COND_FM<fmt, 3>; 279 def C_OLT_#NAME : C_COND_FT<"olt", TypeStr, RC, itin>, C_COND_FM<fmt, 4>; 280 def C_ULT_#NAME : C_COND_FT<"ult", TypeStr, RC, itin>, C_COND_FM<fmt, 5>; 281 def C_OLE_#NAME : C_COND_FT<"ole", TypeStr, RC, itin>, C_COND_FM<fmt, 6>; 282 def C_ULE_#NAME : C_COND_FT<"ule", TypeStr, RC, itin>, C_COND_FM<fmt, 7>; 283 def C_SF_#NAME : C_COND_FT<"sf", TypeStr, RC, itin>, C_COND_FM<fmt, 8>; 284 def C_NGLE_#NAME : C_COND_FT<"ngle", TypeStr, RC, itin>, C_COND_FM<fmt, 9>; 285 def C_SEQ_#NAME : C_COND_FT<"seq", TypeStr, RC, itin>, C_COND_FM<fmt, 10>; 286 def C_NGL_#NAME : C_COND_FT<"ngl", TypeStr, RC, itin>, C_COND_FM<fmt, 11>; 287 def C_LT_#NAME : C_COND_FT<"lt", TypeStr, RC, itin>, C_COND_FM<fmt, 12>; 288 def C_NGE_#NAME : C_COND_FT<"nge", TypeStr, RC, itin>, C_COND_FM<fmt, 13>; 289 def C_LE_#NAME : C_COND_FT<"le", TypeStr, RC, itin>, C_COND_FM<fmt, 14>; 290 def C_NGT_#NAME : C_COND_FT<"ngt", TypeStr, RC, itin>, C_COND_FM<fmt, 15>; 291} 292 293defm S : C_COND_M<"s", FGR32Opnd, 16, II_C_CC_S>, ISA_MIPS1_NOT_32R6_64R6; 294defm D32 : C_COND_M<"d", AFGR64Opnd, 17, II_C_CC_D>, ISA_MIPS1_NOT_32R6_64R6, 295 AdditionalRequires<[NotFP64bit]>; 296let DecoderNamespace = "Mips64" in 297defm D64 : C_COND_M<"d", FGR64Opnd, 17, II_C_CC_D>, ISA_MIPS1_NOT_32R6_64R6, 298 AdditionalRequires<[IsFP64bit]>; 299 300//===----------------------------------------------------------------------===// 301// Floating Point Instructions 302//===----------------------------------------------------------------------===// 303def ROUND_W_S : MMRel, ABSS_FT<"round.w.s", FGR32Opnd, FGR32Opnd, II_ROUND>, 304 ABSS_FM<0xc, 16>, ISA_MIPS2; 305def TRUNC_W_S : MMRel, ABSS_FT<"trunc.w.s", FGR32Opnd, FGR32Opnd, II_TRUNC>, 306 ABSS_FM<0xd, 16>, ISA_MIPS2; 307def CEIL_W_S : MMRel, ABSS_FT<"ceil.w.s", FGR32Opnd, FGR32Opnd, II_CEIL>, 308 ABSS_FM<0xe, 16>, ISA_MIPS2; 309def FLOOR_W_S : MMRel, ABSS_FT<"floor.w.s", FGR32Opnd, FGR32Opnd, II_FLOOR>, 310 ABSS_FM<0xf, 16>, ISA_MIPS2; 311def CVT_W_S : MMRel, ABSS_FT<"cvt.w.s", FGR32Opnd, FGR32Opnd, II_CVT>, 312 ABSS_FM<0x24, 16>; 313 314defm ROUND_W : ROUND_M<"round.w.d", II_ROUND>, ABSS_FM<0xc, 17>, ISA_MIPS2; 315defm TRUNC_W : ROUND_M<"trunc.w.d", II_TRUNC>, ABSS_FM<0xd, 17>, ISA_MIPS2; 316defm CEIL_W : ROUND_M<"ceil.w.d", II_CEIL>, ABSS_FM<0xe, 17>, ISA_MIPS2; 317defm FLOOR_W : ROUND_M<"floor.w.d", II_FLOOR>, ABSS_FM<0xf, 17>, ISA_MIPS2; 318defm CVT_W : ROUND_M<"cvt.w.d", II_CVT>, ABSS_FM<0x24, 17>; 319 320let DecoderNamespace = "Mips64" in { 321 def ROUND_L_S : ABSS_FT<"round.l.s", FGR64Opnd, FGR32Opnd, II_ROUND>, 322 ABSS_FM<0x8, 16>, FGR_64; 323 def ROUND_L_D64 : ABSS_FT<"round.l.d", FGR64Opnd, FGR64Opnd, II_ROUND>, 324 ABSS_FM<0x8, 17>, FGR_64; 325 def TRUNC_L_S : ABSS_FT<"trunc.l.s", FGR64Opnd, FGR32Opnd, II_TRUNC>, 326 ABSS_FM<0x9, 16>, FGR_64; 327 def TRUNC_L_D64 : ABSS_FT<"trunc.l.d", FGR64Opnd, FGR64Opnd, II_TRUNC>, 328 ABSS_FM<0x9, 17>, FGR_64; 329 def CEIL_L_S : ABSS_FT<"ceil.l.s", FGR64Opnd, FGR32Opnd, II_CEIL>, 330 ABSS_FM<0xa, 16>, FGR_64; 331 def CEIL_L_D64 : ABSS_FT<"ceil.l.d", FGR64Opnd, FGR64Opnd, II_CEIL>, 332 ABSS_FM<0xa, 17>, FGR_64; 333 def FLOOR_L_S : ABSS_FT<"floor.l.s", FGR64Opnd, FGR32Opnd, II_FLOOR>, 334 ABSS_FM<0xb, 16>, FGR_64; 335 def FLOOR_L_D64 : ABSS_FT<"floor.l.d", FGR64Opnd, FGR64Opnd, II_FLOOR>, 336 ABSS_FM<0xb, 17>, FGR_64; 337} 338 339def CVT_S_W : MMRel, ABSS_FT<"cvt.s.w", FGR32Opnd, FGR32Opnd, II_CVT>, 340 ABSS_FM<0x20, 20>; 341def CVT_L_S : MMRel, ABSS_FT<"cvt.l.s", FGR64Opnd, FGR32Opnd, II_CVT>, 342 ABSS_FM<0x25, 16>, INSN_MIPS3_32R2; 343def CVT_L_D64: MMRel, ABSS_FT<"cvt.l.d", FGR64Opnd, FGR64Opnd, II_CVT>, 344 ABSS_FM<0x25, 17>, INSN_MIPS3_32R2; 345 346def CVT_S_D32 : MMRel, ABSS_FT<"cvt.s.d", FGR32Opnd, AFGR64Opnd, II_CVT>, 347 ABSS_FM<0x20, 17>, FGR_32; 348def CVT_D32_W : MMRel, ABSS_FT<"cvt.d.w", AFGR64Opnd, FGR32Opnd, II_CVT>, 349 ABSS_FM<0x21, 20>, FGR_32; 350def CVT_D32_S : MMRel, ABSS_FT<"cvt.d.s", AFGR64Opnd, FGR32Opnd, II_CVT>, 351 ABSS_FM<0x21, 16>, FGR_32; 352 353let DecoderNamespace = "Mips64" in { 354 def CVT_S_D64 : ABSS_FT<"cvt.s.d", FGR32Opnd, FGR64Opnd, II_CVT>, 355 ABSS_FM<0x20, 17>, FGR_64; 356 def CVT_S_L : ABSS_FT<"cvt.s.l", FGR32Opnd, FGR64Opnd, II_CVT>, 357 ABSS_FM<0x20, 21>, FGR_64; 358 def CVT_D64_W : ABSS_FT<"cvt.d.w", FGR64Opnd, FGR32Opnd, II_CVT>, 359 ABSS_FM<0x21, 20>, FGR_64; 360 def CVT_D64_S : ABSS_FT<"cvt.d.s", FGR64Opnd, FGR32Opnd, II_CVT>, 361 ABSS_FM<0x21, 16>, FGR_64; 362 def CVT_D64_L : ABSS_FT<"cvt.d.l", FGR64Opnd, FGR64Opnd, II_CVT>, 363 ABSS_FM<0x21, 21>, FGR_64; 364} 365 366let isPseudo = 1, isCodeGenOnly = 1 in { 367 def PseudoCVT_S_W : ABSS_FT<"", FGR32Opnd, GPR32Opnd, II_CVT>; 368 def PseudoCVT_D32_W : ABSS_FT<"", AFGR64Opnd, GPR32Opnd, II_CVT>; 369 def PseudoCVT_S_L : ABSS_FT<"", FGR64Opnd, GPR64Opnd, II_CVT>; 370 def PseudoCVT_D64_W : ABSS_FT<"", FGR64Opnd, GPR32Opnd, II_CVT>; 371 def PseudoCVT_D64_L : ABSS_FT<"", FGR64Opnd, GPR64Opnd, II_CVT>; 372} 373 374def FABS_S : MMRel, ABSS_FT<"abs.s", FGR32Opnd, FGR32Opnd, II_ABS, fabs>, 375 ABSS_FM<0x5, 16>; 376def FNEG_S : MMRel, ABSS_FT<"neg.s", FGR32Opnd, FGR32Opnd, II_NEG, fneg>, 377 ABSS_FM<0x7, 16>; 378defm FABS : ABSS_M<"abs.d", II_ABS, fabs>, ABSS_FM<0x5, 17>; 379defm FNEG : ABSS_M<"neg.d", II_NEG, fneg>, ABSS_FM<0x7, 17>; 380 381def FSQRT_S : MMRel, ABSS_FT<"sqrt.s", FGR32Opnd, FGR32Opnd, II_SQRT_S, fsqrt>, 382 ABSS_FM<0x4, 16>, ISA_MIPS2; 383defm FSQRT : ABSS_M<"sqrt.d", II_SQRT_D, fsqrt>, ABSS_FM<0x4, 17>, ISA_MIPS2; 384 385// The odd-numbered registers are only referenced when doing loads, 386// stores, and moves between floating-point and integer registers. 387// When defining instructions, we reference all 32-bit registers, 388// regardless of register aliasing. 389 390/// Move Control Registers From/To CPU Registers 391def CFC1 : MMRel, MFC1_FT<"cfc1", GPR32Opnd, CCROpnd, II_CFC1>, MFC1_FM<2>; 392def CTC1 : MMRel, MTC1_FT<"ctc1", CCROpnd, GPR32Opnd, II_CTC1>, MFC1_FM<6>; 393def MFC1 : MMRel, MFC1_FT<"mfc1", GPR32Opnd, FGR32Opnd, II_MFC1, 394 bitconvert>, MFC1_FM<0>; 395def MTC1 : MMRel, MTC1_FT<"mtc1", FGR32Opnd, GPR32Opnd, II_MTC1, 396 bitconvert>, MFC1_FM<4>; 397def MFHC1_D32 : MMRel, MFC1_FT<"mfhc1", GPR32Opnd, AFGR64Opnd, II_MFHC1>, 398 MFC1_FM<3>, ISA_MIPS32R2, AdditionalRequires<[NotFP64bit]>; 399def MFHC1_D64 : MFC1_FT<"mfhc1", GPR32Opnd, FGR64Opnd, II_MFHC1>, 400 MFC1_FM<3>, ISA_MIPS32R2, AdditionalRequires<[IsFP64bit]> { 401 let DecoderNamespace = "Mips64"; 402} 403def MTHC1_D32 : MMRel, MTC1_64_FT<"mthc1", AFGR64Opnd, GPR32Opnd, II_MTHC1>, 404 MFC1_FM<7>, ISA_MIPS32R2, AdditionalRequires<[NotFP64bit]>; 405def MTHC1_D64 : MTC1_64_FT<"mthc1", FGR64Opnd, GPR32Opnd, II_MTHC1>, 406 MFC1_FM<7>, ISA_MIPS32R2, AdditionalRequires<[IsFP64bit]> { 407 let DecoderNamespace = "Mips64"; 408} 409def DMFC1 : MFC1_FT<"dmfc1", GPR64Opnd, FGR64Opnd, II_DMFC1, 410 bitconvert>, MFC1_FM<1>, ISA_MIPS3; 411def DMTC1 : MTC1_FT<"dmtc1", FGR64Opnd, GPR64Opnd, II_DMTC1, 412 bitconvert>, MFC1_FM<5>, ISA_MIPS3; 413 414def FMOV_S : MMRel, ABSS_FT<"mov.s", FGR32Opnd, FGR32Opnd, II_MOV_S>, 415 ABSS_FM<0x6, 16>; 416def FMOV_D32 : MMRel, ABSS_FT<"mov.d", AFGR64Opnd, AFGR64Opnd, II_MOV_D>, 417 ABSS_FM<0x6, 17>, AdditionalRequires<[NotFP64bit]>; 418def FMOV_D64 : ABSS_FT<"mov.d", FGR64Opnd, FGR64Opnd, II_MOV_D>, 419 ABSS_FM<0x6, 17>, AdditionalRequires<[IsFP64bit]> { 420 let DecoderNamespace = "Mips64"; 421} 422 423/// Floating Point Memory Instructions 424def LWC1 : MMRel, LW_FT<"lwc1", FGR32Opnd, II_LWC1, load>, LW_FM<0x31>; 425def SWC1 : MMRel, SW_FT<"swc1", FGR32Opnd, II_SWC1, store>, LW_FM<0x39>; 426 427let DecoderNamespace = "Mips64" in { 428 def LDC164 : LW_FT<"ldc1", FGR64Opnd, II_LDC1, load>, LW_FM<0x35>, ISA_MIPS2, 429 FGR_64; 430 def SDC164 : SW_FT<"sdc1", FGR64Opnd, II_SDC1, store>, LW_FM<0x3d>, ISA_MIPS2, 431 FGR_64; 432} 433 434def LDC1 : MMRel, LW_FT<"ldc1", AFGR64Opnd, II_LDC1, load>, LW_FM<0x35>, 435 ISA_MIPS2, FGR_32; 436def SDC1 : MMRel, SW_FT<"sdc1", AFGR64Opnd, II_SDC1, store>, LW_FM<0x3d>, 437 ISA_MIPS2, FGR_32; 438 439// Cop2 Memory Instructions 440// FIXME: These aren't really FPU instructions and as such don't belong in this 441// file 442def LWC2 : LW_FT2<"lwc2", COP2Opnd, NoItinerary, load>, LW_FM<0x32>, 443 ISA_MIPS1_NOT_32R6_64R6; 444def SWC2 : SW_FT2<"swc2", COP2Opnd, NoItinerary, store>, LW_FM<0x3a>, 445 ISA_MIPS1_NOT_32R6_64R6; 446def LDC2 : LW_FT2<"ldc2", COP2Opnd, NoItinerary, load>, LW_FM<0x36>, 447 ISA_MIPS2_NOT_32R6_64R6; 448def SDC2 : SW_FT2<"sdc2", COP2Opnd, NoItinerary, store>, LW_FM<0x3e>, 449 ISA_MIPS2_NOT_32R6_64R6; 450 451// Cop3 Memory Instructions 452// FIXME: These aren't really FPU instructions and as such don't belong in this 453// file 454let DecoderNamespace = "COP3_" in { 455 def LWC3 : LW_FT3<"lwc3", COP3Opnd, NoItinerary, load>, LW_FM<0x33>; 456 def SWC3 : SW_FT3<"swc3", COP3Opnd, NoItinerary, store>, LW_FM<0x3b>; 457 def LDC3 : LW_FT3<"ldc3", COP3Opnd, NoItinerary, load>, LW_FM<0x37>, 458 ISA_MIPS2; 459 def SDC3 : SW_FT3<"sdc3", COP3Opnd, NoItinerary, store>, LW_FM<0x3f>, 460 ISA_MIPS2; 461} 462 463// Indexed loads and stores. 464// Base register + offset register addressing mode (indicated by "x" in the 465// instruction mnemonic) is disallowed under NaCl. 466let AdditionalPredicates = [IsNotNaCl] in { 467 def LWXC1 : MMRel, LWXC1_FT<"lwxc1", FGR32Opnd, II_LWXC1, load>, LWXC1_FM<0>, 468 INSN_MIPS4_32R2_NOT_32R6_64R6; 469 def SWXC1 : MMRel, SWXC1_FT<"swxc1", FGR32Opnd, II_SWXC1, store>, SWXC1_FM<8>, 470 INSN_MIPS4_32R2_NOT_32R6_64R6; 471} 472 473let AdditionalPredicates = [NotInMicroMips, IsNotNaCl] in { 474 def LDXC1 : LWXC1_FT<"ldxc1", AFGR64Opnd, II_LDXC1, load>, LWXC1_FM<1>, 475 INSN_MIPS4_32R2_NOT_32R6_64R6, FGR_32; 476 def SDXC1 : SWXC1_FT<"sdxc1", AFGR64Opnd, II_SDXC1, store>, SWXC1_FM<9>, 477 INSN_MIPS4_32R2_NOT_32R6_64R6, FGR_32; 478} 479 480let DecoderNamespace="Mips64" in { 481 def LDXC164 : LWXC1_FT<"ldxc1", FGR64Opnd, II_LDXC1, load>, LWXC1_FM<1>, 482 INSN_MIPS4_32R2_NOT_32R6_64R6, FGR_64; 483 def SDXC164 : SWXC1_FT<"sdxc1", FGR64Opnd, II_SDXC1, store>, SWXC1_FM<9>, 484 INSN_MIPS4_32R2_NOT_32R6_64R6, FGR_64; 485} 486 487// Load/store doubleword indexed unaligned. 488let AdditionalPredicates = [IsNotNaCl] in { 489 def LUXC1 : MMRel, LWXC1_FT<"luxc1", AFGR64Opnd, II_LUXC1>, LWXC1_FM<0x5>, 490 INSN_MIPS5_32R2_NOT_32R6_64R6, FGR_32; 491 def SUXC1 : MMRel, SWXC1_FT<"suxc1", AFGR64Opnd, II_SUXC1>, SWXC1_FM<0xd>, 492 INSN_MIPS5_32R2_NOT_32R6_64R6, FGR_32; 493} 494 495let DecoderNamespace="Mips64" in { 496 def LUXC164 : LWXC1_FT<"luxc1", FGR64Opnd, II_LUXC1>, LWXC1_FM<0x5>, 497 INSN_MIPS5_32R2_NOT_32R6_64R6, FGR_64; 498 def SUXC164 : SWXC1_FT<"suxc1", FGR64Opnd, II_SUXC1>, SWXC1_FM<0xd>, 499 INSN_MIPS5_32R2_NOT_32R6_64R6, FGR_64; 500} 501 502/// Floating-point Aritmetic 503def FADD_S : MMRel, ADDS_FT<"add.s", FGR32Opnd, II_ADD_S, 1, fadd>, 504 ADDS_FM<0x00, 16>; 505defm FADD : ADDS_M<"add.d", II_ADD_D, 1, fadd>, ADDS_FM<0x00, 17>; 506def FDIV_S : MMRel, ADDS_FT<"div.s", FGR32Opnd, II_DIV_S, 0, fdiv>, 507 ADDS_FM<0x03, 16>; 508defm FDIV : ADDS_M<"div.d", II_DIV_D, 0, fdiv>, ADDS_FM<0x03, 17>; 509def FMUL_S : MMRel, ADDS_FT<"mul.s", FGR32Opnd, II_MUL_S, 1, fmul>, 510 ADDS_FM<0x02, 16>; 511defm FMUL : ADDS_M<"mul.d", II_MUL_D, 1, fmul>, ADDS_FM<0x02, 17>; 512def FSUB_S : MMRel, ADDS_FT<"sub.s", FGR32Opnd, II_SUB_S, 0, fsub>, 513 ADDS_FM<0x01, 16>; 514defm FSUB : ADDS_M<"sub.d", II_SUB_D, 0, fsub>, ADDS_FM<0x01, 17>; 515 516def MADD_S : MMRel, MADDS_FT<"madd.s", FGR32Opnd, II_MADD_S, fadd>, 517 MADDS_FM<4, 0>, ISA_MIPS32R2_NOT_32R6_64R6; 518def MSUB_S : MMRel, MADDS_FT<"msub.s", FGR32Opnd, II_MSUB_S, fsub>, 519 MADDS_FM<5, 0>, ISA_MIPS32R2_NOT_32R6_64R6; 520 521let AdditionalPredicates = [NoNaNsFPMath] in { 522 def NMADD_S : MMRel, NMADDS_FT<"nmadd.s", FGR32Opnd, II_NMADD_S, fadd>, 523 MADDS_FM<6, 0>, ISA_MIPS32R2_NOT_32R6_64R6; 524 def NMSUB_S : MMRel, NMADDS_FT<"nmsub.s", FGR32Opnd, II_NMSUB_S, fsub>, 525 MADDS_FM<7, 0>, ISA_MIPS32R2_NOT_32R6_64R6; 526} 527 528def MADD_D32 : MMRel, MADDS_FT<"madd.d", AFGR64Opnd, II_MADD_D, fadd>, 529 MADDS_FM<4, 1>, ISA_MIPS32R2_NOT_32R6_64R6, FGR_32; 530def MSUB_D32 : MMRel, MADDS_FT<"msub.d", AFGR64Opnd, II_MSUB_D, fsub>, 531 MADDS_FM<5, 1>, ISA_MIPS32R2_NOT_32R6_64R6, FGR_32; 532 533let AdditionalPredicates = [NoNaNsFPMath] in { 534 def NMADD_D32 : MMRel, NMADDS_FT<"nmadd.d", AFGR64Opnd, II_NMADD_D, fadd>, 535 MADDS_FM<6, 1>, ISA_MIPS32R2_NOT_32R6_64R6, FGR_32; 536 def NMSUB_D32 : MMRel, NMADDS_FT<"nmsub.d", AFGR64Opnd, II_NMSUB_D, fsub>, 537 MADDS_FM<7, 1>, ISA_MIPS32R2_NOT_32R6_64R6, FGR_32; 538} 539 540let isCodeGenOnly=1 in { 541 def MADD_D64 : MADDS_FT<"madd.d", FGR64Opnd, II_MADD_D, fadd>, 542 MADDS_FM<4, 1>, ISA_MIPS32R2_NOT_32R6_64R6, FGR_64; 543 def MSUB_D64 : MADDS_FT<"msub.d", FGR64Opnd, II_MSUB_D, fsub>, 544 MADDS_FM<5, 1>, ISA_MIPS32R2_NOT_32R6_64R6, FGR_64; 545} 546 547let AdditionalPredicates = [NoNaNsFPMath], 548 isCodeGenOnly=1 in { 549 def NMADD_D64 : NMADDS_FT<"nmadd.d", FGR64Opnd, II_NMADD_D, fadd>, 550 MADDS_FM<6, 1>, ISA_MIPS32R2_NOT_32R6_64R6, FGR_64; 551 def NMSUB_D64 : NMADDS_FT<"nmsub.d", FGR64Opnd, II_NMSUB_D, fsub>, 552 MADDS_FM<7, 1>, ISA_MIPS32R2_NOT_32R6_64R6, FGR_64; 553} 554 555//===----------------------------------------------------------------------===// 556// Floating Point Branch Codes 557//===----------------------------------------------------------------------===// 558// Mips branch codes. These correspond to condcode in MipsInstrInfo.h. 559// They must be kept in synch. 560def MIPS_BRANCH_F : PatLeaf<(i32 0)>; 561def MIPS_BRANCH_T : PatLeaf<(i32 1)>; 562 563def BC1F : MMRel, BC1F_FT<"bc1f", brtarget, IIBranch, MIPS_BRANCH_F>, 564 BC1F_FM<0, 0>, ISA_MIPS1_NOT_32R6_64R6; 565def BC1T : MMRel, BC1F_FT<"bc1t", brtarget, IIBranch, MIPS_BRANCH_T>, 566 BC1F_FM<0, 1>, ISA_MIPS1_NOT_32R6_64R6; 567 568//===----------------------------------------------------------------------===// 569// Floating Point Flag Conditions 570//===----------------------------------------------------------------------===// 571// Mips condition codes. They must correspond to condcode in MipsInstrInfo.h. 572// They must be kept in synch. 573def MIPS_FCOND_F : PatLeaf<(i32 0)>; 574def MIPS_FCOND_UN : PatLeaf<(i32 1)>; 575def MIPS_FCOND_OEQ : PatLeaf<(i32 2)>; 576def MIPS_FCOND_UEQ : PatLeaf<(i32 3)>; 577def MIPS_FCOND_OLT : PatLeaf<(i32 4)>; 578def MIPS_FCOND_ULT : PatLeaf<(i32 5)>; 579def MIPS_FCOND_OLE : PatLeaf<(i32 6)>; 580def MIPS_FCOND_ULE : PatLeaf<(i32 7)>; 581def MIPS_FCOND_SF : PatLeaf<(i32 8)>; 582def MIPS_FCOND_NGLE : PatLeaf<(i32 9)>; 583def MIPS_FCOND_SEQ : PatLeaf<(i32 10)>; 584def MIPS_FCOND_NGL : PatLeaf<(i32 11)>; 585def MIPS_FCOND_LT : PatLeaf<(i32 12)>; 586def MIPS_FCOND_NGE : PatLeaf<(i32 13)>; 587def MIPS_FCOND_LE : PatLeaf<(i32 14)>; 588def MIPS_FCOND_NGT : PatLeaf<(i32 15)>; 589 590/// Floating Point Compare 591def FCMP_S32 : MMRel, CEQS_FT<"s", FGR32, II_C_CC_S, MipsFPCmp>, CEQS_FM<16>, 592 ISA_MIPS1_NOT_32R6_64R6; 593def FCMP_D32 : MMRel, CEQS_FT<"d", AFGR64, II_C_CC_D, MipsFPCmp>, CEQS_FM<17>, 594 ISA_MIPS1_NOT_32R6_64R6, AdditionalRequires<[NotFP64bit]>; 595let DecoderNamespace = "Mips64" in 596def FCMP_D64 : CEQS_FT<"d", FGR64, II_C_CC_D, MipsFPCmp>, CEQS_FM<17>, 597 ISA_MIPS1_NOT_32R6_64R6, AdditionalRequires<[IsFP64bit]>; 598 599//===----------------------------------------------------------------------===// 600// Floating Point Pseudo-Instructions 601//===----------------------------------------------------------------------===// 602 603// This pseudo instr gets expanded into 2 mtc1 instrs after register 604// allocation. 605class BuildPairF64Base<RegisterOperand RO> : 606 PseudoSE<(outs RO:$dst), (ins GPR32Opnd:$lo, GPR32Opnd:$hi), 607 [(set RO:$dst, (MipsBuildPairF64 GPR32Opnd:$lo, GPR32Opnd:$hi))]>; 608 609def BuildPairF64 : BuildPairF64Base<AFGR64Opnd>, 610 AdditionalRequires<[NotFP64bit]>; 611def BuildPairF64_64 : BuildPairF64Base<FGR64Opnd>, 612 AdditionalRequires<[IsFP64bit]>; 613 614// This pseudo instr gets expanded into 2 mfc1 instrs after register 615// allocation. 616// if n is 0, lower part of src is extracted. 617// if n is 1, higher part of src is extracted. 618class ExtractElementF64Base<RegisterOperand RO> : 619 PseudoSE<(outs GPR32Opnd:$dst), (ins RO:$src, i32imm:$n), 620 [(set GPR32Opnd:$dst, (MipsExtractElementF64 RO:$src, imm:$n))]>; 621 622def ExtractElementF64 : ExtractElementF64Base<AFGR64Opnd>, 623 AdditionalRequires<[NotFP64bit]>; 624def ExtractElementF64_64 : ExtractElementF64Base<FGR64Opnd>, 625 AdditionalRequires<[IsFP64bit]>; 626 627//===----------------------------------------------------------------------===// 628// InstAliases. 629//===----------------------------------------------------------------------===// 630def : MipsInstAlias<"bc1t $offset", (BC1T FCC0, brtarget:$offset)>, 631 ISA_MIPS1_NOT_32R6_64R6; 632def : MipsInstAlias<"bc1f $offset", (BC1F FCC0, brtarget:$offset)>, 633 ISA_MIPS1_NOT_32R6_64R6; 634 635//===----------------------------------------------------------------------===// 636// Floating Point Patterns 637//===----------------------------------------------------------------------===// 638def : MipsPat<(f32 fpimm0), (MTC1 ZERO)>; 639def : MipsPat<(f32 fpimm0neg), (FNEG_S (MTC1 ZERO))>; 640 641def : MipsPat<(f32 (sint_to_fp GPR32Opnd:$src)), 642 (PseudoCVT_S_W GPR32Opnd:$src)>; 643def : MipsPat<(MipsTruncIntFP FGR32Opnd:$src), 644 (TRUNC_W_S FGR32Opnd:$src)>; 645 646def : MipsPat<(f64 (sint_to_fp GPR32Opnd:$src)), 647 (PseudoCVT_D32_W GPR32Opnd:$src)>, FGR_32; 648def : MipsPat<(MipsTruncIntFP AFGR64Opnd:$src), 649 (TRUNC_W_D32 AFGR64Opnd:$src)>, FGR_32; 650def : MipsPat<(f32 (fround AFGR64Opnd:$src)), 651 (CVT_S_D32 AFGR64Opnd:$src)>, FGR_32; 652def : MipsPat<(f64 (fextend FGR32Opnd:$src)), 653 (CVT_D32_S FGR32Opnd:$src)>, FGR_32; 654 655def : MipsPat<(f64 fpimm0), (DMTC1 ZERO_64)>, FGR_64; 656def : MipsPat<(f64 fpimm0neg), (FNEG_D64 (DMTC1 ZERO_64))>, FGR_64; 657 658def : MipsPat<(f64 (sint_to_fp GPR32Opnd:$src)), 659 (PseudoCVT_D64_W GPR32Opnd:$src)>, FGR_64; 660def : MipsPat<(f32 (sint_to_fp GPR64Opnd:$src)), 661 (EXTRACT_SUBREG (PseudoCVT_S_L GPR64Opnd:$src), sub_lo)>, FGR_64; 662def : MipsPat<(f64 (sint_to_fp GPR64Opnd:$src)), 663 (PseudoCVT_D64_L GPR64Opnd:$src)>, FGR_64; 664 665def : MipsPat<(MipsTruncIntFP FGR64Opnd:$src), 666 (TRUNC_W_D64 FGR64Opnd:$src)>, FGR_64; 667def : MipsPat<(MipsTruncIntFP FGR32Opnd:$src), 668 (TRUNC_L_S FGR32Opnd:$src)>, FGR_64; 669def : MipsPat<(MipsTruncIntFP FGR64Opnd:$src), 670 (TRUNC_L_D64 FGR64Opnd:$src)>, FGR_64; 671 672def : MipsPat<(f32 (fround FGR64Opnd:$src)), 673 (CVT_S_D64 FGR64Opnd:$src)>, FGR_64; 674def : MipsPat<(f64 (fextend FGR32Opnd:$src)), 675 (CVT_D64_S FGR32Opnd:$src)>, FGR_64; 676 677// Patterns for loads/stores with a reg+imm operand. 678let AddedComplexity = 40 in { 679 def : LoadRegImmPat<LWC1, f32, load>; 680 def : StoreRegImmPat<SWC1, f32>; 681 682 def : LoadRegImmPat<LDC164, f64, load>, FGR_64; 683 def : StoreRegImmPat<SDC164, f64>, FGR_64; 684 685 def : LoadRegImmPat<LDC1, f64, load>, FGR_32; 686 def : StoreRegImmPat<SDC1, f64>, FGR_32; 687} 688