1//===-- MipsInstrFPU.td - Mips FPU Instruction Information -*- tablegen -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file describes the Mips FPU instruction set. 11// 12//===----------------------------------------------------------------------===// 13 14//===----------------------------------------------------------------------===// 15// Floating Point Instructions 16// ------------------------ 17// * 64bit fp: 18// - 32 64-bit registers (default mode) 19// - 16 even 32-bit registers (32-bit compatible mode) for 20// single and double access. 21// * 32bit fp: 22// - 16 even 32-bit registers - single and double (aliased) 23// - 32 32-bit registers (within single-only mode) 24//===----------------------------------------------------------------------===// 25 26// Floating Point Compare and Branch 27def SDT_MipsFPBrcond : SDTypeProfile<0, 3, [SDTCisInt<0>, 28 SDTCisVT<1, i32>, 29 SDTCisVT<2, OtherVT>]>; 30def SDT_MipsFPCmp : SDTypeProfile<0, 3, [SDTCisSameAs<0, 1>, SDTCisFP<1>, 31 SDTCisVT<2, i32>]>; 32def SDT_MipsCMovFP : SDTypeProfile<1, 3, [SDTCisSameAs<0, 1>, SDTCisVT<2, i32>, 33 SDTCisSameAs<1, 3>]>; 34def SDT_MipsTruncIntFP : SDTypeProfile<1, 1, [SDTCisFP<0>, SDTCisFP<1>]>; 35def SDT_MipsBuildPairF64 : SDTypeProfile<1, 2, [SDTCisVT<0, f64>, 36 SDTCisVT<1, i32>, 37 SDTCisSameAs<1, 2>]>; 38def SDT_MipsExtractElementF64 : SDTypeProfile<1, 2, [SDTCisVT<0, i32>, 39 SDTCisVT<1, f64>, 40 SDTCisVT<2, i32>]>; 41 42def SDT_MipsMTC1_D64 : SDTypeProfile<1, 1, [SDTCisVT<0, f64>, 43 SDTCisVT<1, i32>]>; 44 45def MipsFPCmp : SDNode<"MipsISD::FPCmp", SDT_MipsFPCmp, [SDNPOutGlue]>; 46def MipsCMovFP_T : SDNode<"MipsISD::CMovFP_T", SDT_MipsCMovFP, [SDNPInGlue]>; 47def MipsCMovFP_F : SDNode<"MipsISD::CMovFP_F", SDT_MipsCMovFP, [SDNPInGlue]>; 48def MipsFPBrcond : SDNode<"MipsISD::FPBrcond", SDT_MipsFPBrcond, 49 [SDNPHasChain, SDNPOptInGlue]>; 50def MipsTruncIntFP : SDNode<"MipsISD::TruncIntFP", SDT_MipsTruncIntFP>; 51def MipsBuildPairF64 : SDNode<"MipsISD::BuildPairF64", SDT_MipsBuildPairF64>; 52def MipsExtractElementF64 : SDNode<"MipsISD::ExtractElementF64", 53 SDT_MipsExtractElementF64>; 54 55def MipsMTC1_D64 : SDNode<"MipsISD::MTC1_D64", SDT_MipsMTC1_D64>; 56 57// Operand for printing out a condition code. 58let PrintMethod = "printFCCOperand", DecoderMethod = "DecodeCondCode" in 59 def condcode : Operand<i32>; 60 61//===----------------------------------------------------------------------===// 62// Feature predicates. 63//===----------------------------------------------------------------------===// 64 65def IsFP64bit : Predicate<"Subtarget->isFP64bit()">, 66 AssemblerPredicate<"FeatureFP64Bit">; 67def NotFP64bit : Predicate<"!Subtarget->isFP64bit()">, 68 AssemblerPredicate<"!FeatureFP64Bit">; 69def IsSingleFloat : Predicate<"Subtarget->isSingleFloat()">, 70 AssemblerPredicate<"FeatureSingleFloat">; 71def IsNotSingleFloat : Predicate<"!Subtarget->isSingleFloat()">, 72 AssemblerPredicate<"!FeatureSingleFloat">; 73def IsNotSoftFloat : Predicate<"!Subtarget->useSoftFloat()">, 74 AssemblerPredicate<"!FeatureSoftFloat">; 75 76//===----------------------------------------------------------------------===// 77// Mips FGR size adjectives. 78// They are mutually exclusive. 79//===----------------------------------------------------------------------===// 80 81class FGR_32 { list<Predicate> FGRPredicates = [NotFP64bit]; } 82class FGR_64 { list<Predicate> FGRPredicates = [IsFP64bit]; } 83class HARDFLOAT { list<Predicate> HardFloatPredicate = [IsNotSoftFloat]; } 84 85//===----------------------------------------------------------------------===// 86 87// FP immediate patterns. 88def fpimm0 : PatLeaf<(fpimm), [{ 89 return N->isExactlyValue(+0.0); 90}]>; 91 92def fpimm0neg : PatLeaf<(fpimm), [{ 93 return N->isExactlyValue(-0.0); 94}]>; 95 96//===----------------------------------------------------------------------===// 97// Instruction Class Templates 98// 99// A set of multiclasses is used to address the register usage. 100// 101// S32 - single precision in 16 32bit even fp registers 102// single precision in 32 32bit fp registers in SingleOnly mode 103// S64 - single precision in 32 64bit fp registers (In64BitMode) 104// D32 - double precision in 16 32bit even fp registers 105// D64 - double precision in 32 64bit fp registers (In64BitMode) 106// 107// Only S32 and D32 are supported right now. 108//===----------------------------------------------------------------------===// 109class ADDS_FT<string opstr, RegisterOperand RC, InstrItinClass Itin, bit IsComm, 110 SDPatternOperator OpNode= null_frag> : 111 InstSE<(outs RC:$fd), (ins RC:$fs, RC:$ft), 112 !strconcat(opstr, "\t$fd, $fs, $ft"), 113 [(set RC:$fd, (OpNode RC:$fs, RC:$ft))], Itin, FrmFR, opstr>, 114 HARDFLOAT { 115 let isCommutable = IsComm; 116} 117 118multiclass ADDS_M<string opstr, InstrItinClass Itin, bit IsComm, 119 SDPatternOperator OpNode = null_frag> { 120 def _D32 : MMRel, ADDS_FT<opstr, AFGR64Opnd, Itin, IsComm, OpNode>, FGR_32; 121 def _D64 : ADDS_FT<opstr, FGR64Opnd, Itin, IsComm, OpNode>, FGR_64 { 122 string DecoderNamespace = "MipsFP64"; 123 } 124} 125 126class ABSS_FT<string opstr, RegisterOperand DstRC, RegisterOperand SrcRC, 127 InstrItinClass Itin, SDPatternOperator OpNode= null_frag> : 128 InstSE<(outs DstRC:$fd), (ins SrcRC:$fs), !strconcat(opstr, "\t$fd, $fs"), 129 [(set DstRC:$fd, (OpNode SrcRC:$fs))], Itin, FrmFR, opstr>, 130 HARDFLOAT, 131 NeverHasSideEffects; 132 133multiclass ABSS_M<string opstr, InstrItinClass Itin, 134 SDPatternOperator OpNode= null_frag> { 135 def _D32 : MMRel, ABSS_FT<opstr, AFGR64Opnd, AFGR64Opnd, Itin, OpNode>, 136 FGR_32; 137 def _D64 : ABSS_FT<opstr, FGR64Opnd, FGR64Opnd, Itin, OpNode>, FGR_64 { 138 string DecoderNamespace = "MipsFP64"; 139 } 140} 141 142multiclass ROUND_M<string opstr, InstrItinClass Itin> { 143 def _D32 : MMRel, ABSS_FT<opstr, FGR32Opnd, AFGR64Opnd, Itin>, FGR_32; 144 def _D64 : StdMMR6Rel, ABSS_FT<opstr, FGR32Opnd, FGR64Opnd, Itin>, FGR_64 { 145 let DecoderNamespace = "MipsFP64"; 146 } 147} 148 149class MFC1_FT<string opstr, RegisterOperand DstRC, RegisterOperand SrcRC, 150 InstrItinClass Itin, SDPatternOperator OpNode= null_frag> : 151 InstSE<(outs DstRC:$rt), (ins SrcRC:$fs), !strconcat(opstr, "\t$rt, $fs"), 152 [(set DstRC:$rt, (OpNode SrcRC:$fs))], Itin, FrmFR, opstr>, HARDFLOAT; 153 154class MTC1_FT<string opstr, RegisterOperand DstRC, RegisterOperand SrcRC, 155 InstrItinClass Itin, SDPatternOperator OpNode= null_frag> : 156 InstSE<(outs DstRC:$fs), (ins SrcRC:$rt), !strconcat(opstr, "\t$rt, $fs"), 157 [(set DstRC:$fs, (OpNode SrcRC:$rt))], Itin, FrmFR, opstr>, HARDFLOAT; 158 159class MTC1_64_FT<string opstr, RegisterOperand DstRC, RegisterOperand SrcRC, 160 InstrItinClass Itin> : 161 InstSE<(outs DstRC:$fs), (ins DstRC:$fs_in, SrcRC:$rt), 162 !strconcat(opstr, "\t$rt, $fs"), [], Itin, FrmFR, opstr>, HARDFLOAT { 163 // $fs_in is part of a white lie to work around a widespread bug in the FPU 164 // implementation. See expandBuildPairF64 for details. 165 let Constraints = "$fs = $fs_in"; 166} 167 168class LW_FT<string opstr, RegisterOperand RC, DAGOperand MO, 169 InstrItinClass Itin, SDPatternOperator OpNode = null_frag> : 170 InstSE<(outs RC:$rt), (ins MO:$addr), !strconcat(opstr, "\t$rt, $addr"), 171 [(set RC:$rt, (OpNode addrDefault:$addr))], Itin, FrmFI, opstr>, 172 HARDFLOAT { 173 let DecoderMethod = "DecodeFMem"; 174 let mayLoad = 1; 175} 176 177class SW_FT<string opstr, RegisterOperand RC, DAGOperand MO, 178 InstrItinClass Itin, SDPatternOperator OpNode = null_frag> : 179 InstSE<(outs), (ins RC:$rt, MO:$addr), !strconcat(opstr, "\t$rt, $addr"), 180 [(OpNode RC:$rt, addrDefault:$addr)], Itin, FrmFI, opstr>, HARDFLOAT { 181 let DecoderMethod = "DecodeFMem"; 182 let mayStore = 1; 183} 184 185class MADDS_FT<string opstr, RegisterOperand RC, InstrItinClass Itin, 186 SDPatternOperator OpNode = null_frag> : 187 InstSE<(outs RC:$fd), (ins RC:$fr, RC:$fs, RC:$ft), 188 !strconcat(opstr, "\t$fd, $fr, $fs, $ft"), 189 [(set RC:$fd, (OpNode (fmul RC:$fs, RC:$ft), RC:$fr))], Itin, 190 FrmFR, opstr>, HARDFLOAT; 191 192class NMADDS_FT<string opstr, RegisterOperand RC, InstrItinClass Itin, 193 SDPatternOperator OpNode = null_frag> : 194 InstSE<(outs RC:$fd), (ins RC:$fr, RC:$fs, RC:$ft), 195 !strconcat(opstr, "\t$fd, $fr, $fs, $ft"), 196 [(set RC:$fd, (fsub fpimm0, (OpNode (fmul RC:$fs, RC:$ft), RC:$fr)))], 197 Itin, FrmFR, opstr>, HARDFLOAT; 198 199class LWXC1_FT<string opstr, RegisterOperand DRC, 200 InstrItinClass Itin, SDPatternOperator OpNode = null_frag> : 201 InstSE<(outs DRC:$fd), (ins PtrRC:$base, PtrRC:$index), 202 !strconcat(opstr, "\t$fd, ${index}(${base})"), 203 [(set DRC:$fd, (OpNode (add iPTR:$base, iPTR:$index)))], Itin, 204 FrmFI, opstr>, HARDFLOAT { 205 let AddedComplexity = 20; 206} 207 208class SWXC1_FT<string opstr, RegisterOperand DRC, 209 InstrItinClass Itin, SDPatternOperator OpNode = null_frag> : 210 InstSE<(outs), (ins DRC:$fs, PtrRC:$base, PtrRC:$index), 211 !strconcat(opstr, "\t$fs, ${index}(${base})"), 212 [(OpNode DRC:$fs, (add iPTR:$base, iPTR:$index))], Itin, 213 FrmFI, opstr>, HARDFLOAT { 214 let AddedComplexity = 20; 215} 216 217class BC1F_FT<string opstr, DAGOperand opnd, InstrItinClass Itin, 218 SDPatternOperator Op = null_frag> : 219 InstSE<(outs), (ins FCCRegsOpnd:$fcc, opnd:$offset), 220 !strconcat(opstr, "\t$fcc, $offset"), 221 [(MipsFPBrcond Op, FCCRegsOpnd:$fcc, bb:$offset)], Itin, 222 FrmFI, opstr>, HARDFLOAT { 223 let isBranch = 1; 224 let isTerminator = 1; 225 let hasDelaySlot = 1; 226 let Defs = [AT]; 227 let hasFCCRegOperand = 1; 228} 229 230class BC1XL_FT<string opstr, DAGOperand opnd, InstrItinClass Itin> : 231 InstSE<(outs), (ins FCCRegsOpnd:$fcc, opnd:$offset), 232 !strconcat(opstr, "\t$fcc, $offset"), [], Itin, 233 FrmFI, opstr>, HARDFLOAT { 234 let isBranch = 1; 235 let isTerminator = 1; 236 let hasDelaySlot = 1; 237 let Defs = [AT]; 238 let hasFCCRegOperand = 1; 239} 240 241class CEQS_FT<string typestr, RegisterClass RC, InstrItinClass Itin, 242 SDPatternOperator OpNode = null_frag> : 243 InstSE<(outs), (ins RC:$fs, RC:$ft, condcode:$cond), 244 !strconcat("c.$cond.", typestr, "\t$fs, $ft"), 245 [(OpNode RC:$fs, RC:$ft, imm:$cond)], Itin, FrmFR, 246 !strconcat("c.$cond.", typestr)>, HARDFLOAT { 247 let Defs = [FCC0]; 248 let isCodeGenOnly = 1; 249 let hasFCCRegOperand = 1; 250} 251 252 253// Note: MIPS-IV introduced $fcc1-$fcc7 and renamed FCSR31[23] $fcc0. Rather 254// duplicating the instruction definition for MIPS1 - MIPS3, we expand 255// c.cond.ft if necessary, and reject it after constructing the 256// instruction if the ISA doesn't support it. 257class C_COND_FT<string CondStr, string Typestr, RegisterOperand RC, 258 InstrItinClass itin> : 259 InstSE<(outs FCCRegsOpnd:$fcc), (ins RC:$fs, RC:$ft), 260 !strconcat("c.", CondStr, ".", Typestr, "\t$fcc, $fs, $ft"), [], itin, 261 FrmFR>, HARDFLOAT { 262 let isCompare = 1; 263 let hasFCCRegOperand = 1; 264} 265 266 267multiclass C_COND_M<string TypeStr, RegisterOperand RC, bits<5> fmt, 268 InstrItinClass itin> { 269 def C_F_#NAME : MMRel, C_COND_FT<"f", TypeStr, RC, itin>, 270 C_COND_FM<fmt, 0> { 271 let BaseOpcode = "c.f."#NAME; 272 let isCommutable = 1; 273 } 274 def C_UN_#NAME : MMRel, C_COND_FT<"un", TypeStr, RC, itin>, 275 C_COND_FM<fmt, 1> { 276 let BaseOpcode = "c.un."#NAME; 277 let isCommutable = 1; 278 } 279 def C_EQ_#NAME : MMRel, C_COND_FT<"eq", TypeStr, RC, itin>, 280 C_COND_FM<fmt, 2> { 281 let BaseOpcode = "c.eq."#NAME; 282 let isCommutable = 1; 283 } 284 def C_UEQ_#NAME : MMRel, C_COND_FT<"ueq", TypeStr, RC, itin>, 285 C_COND_FM<fmt, 3> { 286 let BaseOpcode = "c.ueq."#NAME; 287 let isCommutable = 1; 288 } 289 def C_OLT_#NAME : MMRel, C_COND_FT<"olt", TypeStr, RC, itin>, 290 C_COND_FM<fmt, 4> { 291 let BaseOpcode = "c.olt."#NAME; 292 } 293 def C_ULT_#NAME : MMRel, C_COND_FT<"ult", TypeStr, RC, itin>, 294 C_COND_FM<fmt, 5> { 295 let BaseOpcode = "c.ult."#NAME; 296 } 297 def C_OLE_#NAME : MMRel, C_COND_FT<"ole", TypeStr, RC, itin>, 298 C_COND_FM<fmt, 6> { 299 let BaseOpcode = "c.ole."#NAME; 300 } 301 def C_ULE_#NAME : MMRel, C_COND_FT<"ule", TypeStr, RC, itin>, 302 C_COND_FM<fmt, 7> { 303 let BaseOpcode = "c.ule."#NAME; 304 } 305 def C_SF_#NAME : MMRel, C_COND_FT<"sf", TypeStr, RC, itin>, 306 C_COND_FM<fmt, 8> { 307 let BaseOpcode = "c.sf."#NAME; 308 let isCommutable = 1; 309 } 310 def C_NGLE_#NAME : MMRel, C_COND_FT<"ngle", TypeStr, RC, itin>, 311 C_COND_FM<fmt, 9> { 312 let BaseOpcode = "c.ngle."#NAME; 313 } 314 def C_SEQ_#NAME : MMRel, C_COND_FT<"seq", TypeStr, RC, itin>, 315 C_COND_FM<fmt, 10> { 316 let BaseOpcode = "c.seq."#NAME; 317 let isCommutable = 1; 318 } 319 def C_NGL_#NAME : MMRel, C_COND_FT<"ngl", TypeStr, RC, itin>, 320 C_COND_FM<fmt, 11> { 321 let BaseOpcode = "c.ngl."#NAME; 322 } 323 def C_LT_#NAME : MMRel, C_COND_FT<"lt", TypeStr, RC, itin>, 324 C_COND_FM<fmt, 12> { 325 let BaseOpcode = "c.lt."#NAME; 326 } 327 def C_NGE_#NAME : MMRel, C_COND_FT<"nge", TypeStr, RC, itin>, 328 C_COND_FM<fmt, 13> { 329 let BaseOpcode = "c.nge."#NAME; 330 } 331 def C_LE_#NAME : MMRel, C_COND_FT<"le", TypeStr, RC, itin>, 332 C_COND_FM<fmt, 14> { 333 let BaseOpcode = "c.le."#NAME; 334 } 335 def C_NGT_#NAME : MMRel, C_COND_FT<"ngt", TypeStr, RC, itin>, 336 C_COND_FM<fmt, 15> { 337 let BaseOpcode = "c.ngt."#NAME; 338 } 339} 340 341let AdditionalPredicates = [NotInMicroMips] in { 342defm S : C_COND_M<"s", FGR32Opnd, 16, II_C_CC_S>, ISA_MIPS1_NOT_32R6_64R6; 343defm D32 : C_COND_M<"d", AFGR64Opnd, 17, II_C_CC_D>, ISA_MIPS1_NOT_32R6_64R6, 344 FGR_32; 345let DecoderNamespace = "MipsFP64" in 346defm D64 : C_COND_M<"d", FGR64Opnd, 17, II_C_CC_D>, ISA_MIPS1_NOT_32R6_64R6, 347 FGR_64; 348} 349//===----------------------------------------------------------------------===// 350// Floating Point Instructions 351//===----------------------------------------------------------------------===// 352def ROUND_W_S : MMRel, StdMMR6Rel, ABSS_FT<"round.w.s", FGR32Opnd, FGR32Opnd, II_ROUND>, 353 ABSS_FM<0xc, 16>, ISA_MIPS2; 354defm ROUND_W : ROUND_M<"round.w.d", II_ROUND>, ABSS_FM<0xc, 17>, ISA_MIPS2; 355def TRUNC_W_S : MMRel, StdMMR6Rel, ABSS_FT<"trunc.w.s", FGR32Opnd, FGR32Opnd, II_TRUNC>, 356 ABSS_FM<0xd, 16>, ISA_MIPS2; 357def CEIL_W_S : MMRel, StdMMR6Rel, ABSS_FT<"ceil.w.s", FGR32Opnd, FGR32Opnd, II_CEIL>, 358 ABSS_FM<0xe, 16>, ISA_MIPS2; 359def FLOOR_W_S : MMRel, StdMMR6Rel, ABSS_FT<"floor.w.s", FGR32Opnd, FGR32Opnd, II_FLOOR>, 360 ABSS_FM<0xf, 16>, ISA_MIPS2; 361def CVT_W_S : MMRel, ABSS_FT<"cvt.w.s", FGR32Opnd, FGR32Opnd, II_CVT>, 362 ABSS_FM<0x24, 16>; 363 364defm TRUNC_W : ROUND_M<"trunc.w.d", II_TRUNC>, ABSS_FM<0xd, 17>, ISA_MIPS2; 365defm CEIL_W : ROUND_M<"ceil.w.d", II_CEIL>, ABSS_FM<0xe, 17>, ISA_MIPS2; 366defm FLOOR_W : ROUND_M<"floor.w.d", II_FLOOR>, ABSS_FM<0xf, 17>, ISA_MIPS2; 367defm CVT_W : ROUND_M<"cvt.w.d", II_CVT>, ABSS_FM<0x24, 17>; 368 369let AdditionalPredicates = [NotInMicroMips] in { 370 def RECIP_S : MMRel, ABSS_FT<"recip.s", FGR32Opnd, FGR32Opnd, II_RECIP_S>, 371 ABSS_FM<0b010101, 0x10>, INSN_MIPS4_32R2; 372 def RECIP_D32 : MMRel, ABSS_FT<"recip.d", AFGR64Opnd, AFGR64Opnd, II_RECIP_D>, 373 ABSS_FM<0b010101, 0x11>, INSN_MIPS4_32R2, FGR_32 { 374 let BaseOpcode = "RECIP_D32"; 375 } 376 let DecoderNamespace = "MipsFP64" in 377 def RECIP_D64 : MMRel, ABSS_FT<"recip.d", FGR64Opnd, FGR64Opnd, 378 II_RECIP_D>, ABSS_FM<0b010101, 0x11>, 379 INSN_MIPS4_32R2, FGR_64; 380 def RSQRT_S : MMRel, ABSS_FT<"rsqrt.s", FGR32Opnd, FGR32Opnd, II_RSQRT_S>, 381 ABSS_FM<0b010110, 0x10>, INSN_MIPS4_32R2; 382 def RSQRT_D32 : MMRel, ABSS_FT<"rsqrt.d", AFGR64Opnd, AFGR64Opnd, II_RSQRT_D>, 383 ABSS_FM<0b010110, 0x11>, INSN_MIPS4_32R2, FGR_32 { 384 let BaseOpcode = "RSQRT_D32"; 385 } 386 let DecoderNamespace = "MipsFP64" in 387 def RSQRT_D64 : MMRel, ABSS_FT<"rsqrt.d", FGR64Opnd, FGR64Opnd, 388 II_RSQRT_D>, ABSS_FM<0b010110, 0x11>, 389 INSN_MIPS4_32R2, FGR_64; 390} 391let DecoderNamespace = "MipsFP64" in { 392 let AdditionalPredicates = [NotInMicroMips] in { 393 def ROUND_L_S : ABSS_FT<"round.l.s", FGR64Opnd, FGR32Opnd, II_ROUND>, 394 ABSS_FM<0x8, 16>, FGR_64; 395 def ROUND_L_D64 : ABSS_FT<"round.l.d", FGR64Opnd, FGR64Opnd, II_ROUND>, 396 ABSS_FM<0x8, 17>, FGR_64; 397 def TRUNC_L_S : ABSS_FT<"trunc.l.s", FGR64Opnd, FGR32Opnd, II_TRUNC>, 398 ABSS_FM<0x9, 16>, FGR_64; 399 def TRUNC_L_D64 : ABSS_FT<"trunc.l.d", FGR64Opnd, FGR64Opnd, II_TRUNC>, 400 ABSS_FM<0x9, 17>, FGR_64; 401 def CEIL_L_S : ABSS_FT<"ceil.l.s", FGR64Opnd, FGR32Opnd, II_CEIL>, 402 ABSS_FM<0xa, 16>, FGR_64; 403 def CEIL_L_D64 : ABSS_FT<"ceil.l.d", FGR64Opnd, FGR64Opnd, II_CEIL>, 404 ABSS_FM<0xa, 17>, FGR_64; 405 def FLOOR_L_S : ABSS_FT<"floor.l.s", FGR64Opnd, FGR32Opnd, II_FLOOR>, 406 ABSS_FM<0xb, 16>, FGR_64; 407 def FLOOR_L_D64 : ABSS_FT<"floor.l.d", FGR64Opnd, FGR64Opnd, II_FLOOR>, 408 ABSS_FM<0xb, 17>, FGR_64; 409 } 410} 411 412def CVT_S_W : MMRel, ABSS_FT<"cvt.s.w", FGR32Opnd, FGR32Opnd, II_CVT>, 413 ABSS_FM<0x20, 20>; 414let AdditionalPredicates = [NotInMicroMips] in{ 415 def CVT_L_S : MMRel, ABSS_FT<"cvt.l.s", FGR64Opnd, FGR32Opnd, II_CVT>, 416 ABSS_FM<0x25, 16>, INSN_MIPS3_32R2; 417 def CVT_L_D64: MMRel, ABSS_FT<"cvt.l.d", FGR64Opnd, FGR64Opnd, II_CVT>, 418 ABSS_FM<0x25, 17>, INSN_MIPS3_32R2; 419} 420 421def CVT_S_D32 : MMRel, ABSS_FT<"cvt.s.d", FGR32Opnd, AFGR64Opnd, II_CVT>, 422 ABSS_FM<0x20, 17>, FGR_32; 423def CVT_D32_W : MMRel, ABSS_FT<"cvt.d.w", AFGR64Opnd, FGR32Opnd, II_CVT>, 424 ABSS_FM<0x21, 20>, FGR_32; 425def CVT_D32_S : MMRel, ABSS_FT<"cvt.d.s", AFGR64Opnd, FGR32Opnd, II_CVT>, 426 ABSS_FM<0x21, 16>, FGR_32; 427 428let DecoderNamespace = "MipsFP64" in { 429 def CVT_S_D64 : ABSS_FT<"cvt.s.d", FGR32Opnd, FGR64Opnd, II_CVT>, 430 ABSS_FM<0x20, 17>, FGR_64; 431 let AdditionalPredicates = [NotInMicroMips] in{ 432 def CVT_S_L : ABSS_FT<"cvt.s.l", FGR32Opnd, FGR64Opnd, II_CVT>, 433 ABSS_FM<0x20, 21>, FGR_64; 434 } 435 def CVT_D64_W : ABSS_FT<"cvt.d.w", FGR64Opnd, FGR32Opnd, II_CVT>, 436 ABSS_FM<0x21, 20>, FGR_64; 437 def CVT_D64_S : ABSS_FT<"cvt.d.s", FGR64Opnd, FGR32Opnd, II_CVT>, 438 ABSS_FM<0x21, 16>, FGR_64; 439 def CVT_D64_L : ABSS_FT<"cvt.d.l", FGR64Opnd, FGR64Opnd, II_CVT>, 440 ABSS_FM<0x21, 21>, FGR_64; 441} 442 443let isPseudo = 1, isCodeGenOnly = 1 in { 444 def PseudoCVT_S_W : ABSS_FT<"", FGR32Opnd, GPR32Opnd, II_CVT>; 445 def PseudoCVT_D32_W : ABSS_FT<"", AFGR64Opnd, GPR32Opnd, II_CVT>; 446 def PseudoCVT_S_L : ABSS_FT<"", FGR64Opnd, GPR64Opnd, II_CVT>; 447 def PseudoCVT_D64_W : ABSS_FT<"", FGR64Opnd, GPR32Opnd, II_CVT>; 448 def PseudoCVT_D64_L : ABSS_FT<"", FGR64Opnd, GPR64Opnd, II_CVT>; 449} 450 451def FABS_S : MMRel, ABSS_FT<"abs.s", FGR32Opnd, FGR32Opnd, II_ABS, fabs>, 452 ABSS_FM<0x5, 16>; 453def FNEG_S : MMRel, ABSS_FT<"neg.s", FGR32Opnd, FGR32Opnd, II_NEG, fneg>, 454 ABSS_FM<0x7, 16>; 455defm FABS : ABSS_M<"abs.d", II_ABS, fabs>, ABSS_FM<0x5, 17>; 456defm FNEG : ABSS_M<"neg.d", II_NEG, fneg>, ABSS_FM<0x7, 17>; 457 458def FSQRT_S : MMRel, StdMMR6Rel, ABSS_FT<"sqrt.s", FGR32Opnd, FGR32Opnd, 459 II_SQRT_S, fsqrt>, ABSS_FM<0x4, 16>, ISA_MIPS2; 460defm FSQRT : ABSS_M<"sqrt.d", II_SQRT_D, fsqrt>, ABSS_FM<0x4, 17>, ISA_MIPS2; 461 462// The odd-numbered registers are only referenced when doing loads, 463// stores, and moves between floating-point and integer registers. 464// When defining instructions, we reference all 32-bit registers, 465// regardless of register aliasing. 466 467/// Move Control Registers From/To CPU Registers 468let AdditionalPredicates = [NotInMicroMips] in { 469 def CFC1 : MMRel, MFC1_FT<"cfc1", GPR32Opnd, CCROpnd, II_CFC1>, MFC1_FM<2>; 470 def CTC1 : MMRel, MTC1_FT<"ctc1", CCROpnd, GPR32Opnd, II_CTC1>, MFC1_FM<6>; 471} 472def MFC1 : MMRel, MFC1_FT<"mfc1", GPR32Opnd, FGR32Opnd, II_MFC1, 473 bitconvert>, MFC1_FM<0>; 474def MFC1_D64 : MFC1_FT<"mfc1", GPR32Opnd, FGR64Opnd, II_MFC1>, MFC1_FM<0>, 475 FGR_64 { 476 let DecoderNamespace = "MipsFP64"; 477} 478def MTC1 : MMRel, MTC1_FT<"mtc1", FGR32Opnd, GPR32Opnd, II_MTC1, 479 bitconvert>, MFC1_FM<4>; 480def MTC1_D64 : MTC1_FT<"mtc1", FGR64Opnd, GPR32Opnd, II_MTC1>, MFC1_FM<4>, 481 FGR_64 { 482 let DecoderNamespace = "MipsFP64"; 483} 484 485let AdditionalPredicates = [NotInMicroMips] in { 486 def MFHC1_D32 : MMRel, MFC1_FT<"mfhc1", GPR32Opnd, AFGR64Opnd, II_MFHC1>, 487 MFC1_FM<3>, ISA_MIPS32R2, FGR_32; 488 def MFHC1_D64 : MFC1_FT<"mfhc1", GPR32Opnd, FGR64Opnd, II_MFHC1>, 489 MFC1_FM<3>, ISA_MIPS32R2, FGR_64 { 490 let DecoderNamespace = "MipsFP64"; 491 } 492} 493let AdditionalPredicates = [NotInMicroMips] in { 494 def MTHC1_D32 : MMRel, StdMMR6Rel, MTC1_64_FT<"mthc1", AFGR64Opnd, GPR32Opnd, II_MTHC1>, 495 MFC1_FM<7>, ISA_MIPS32R2, FGR_32; 496 def MTHC1_D64 : MTC1_64_FT<"mthc1", FGR64Opnd, GPR32Opnd, II_MTHC1>, 497 MFC1_FM<7>, ISA_MIPS32R2, FGR_64 { 498 let DecoderNamespace = "MipsFP64"; 499 } 500} 501let AdditionalPredicates = [NotInMicroMips] in { 502 def DMTC1 : MTC1_FT<"dmtc1", FGR64Opnd, GPR64Opnd, II_DMTC1, 503 bitconvert>, MFC1_FM<5>, ISA_MIPS3; 504 def DMFC1 : MFC1_FT<"dmfc1", GPR64Opnd, FGR64Opnd, II_DMFC1, 505 bitconvert>, MFC1_FM<1>, ISA_MIPS3; 506} 507 508def FMOV_S : MMRel, ABSS_FT<"mov.s", FGR32Opnd, FGR32Opnd, II_MOV_S>, 509 ABSS_FM<0x6, 16>; 510def FMOV_D32 : MMRel, ABSS_FT<"mov.d", AFGR64Opnd, AFGR64Opnd, II_MOV_D>, 511 ABSS_FM<0x6, 17>, FGR_32; 512def FMOV_D64 : ABSS_FT<"mov.d", FGR64Opnd, FGR64Opnd, II_MOV_D>, 513 ABSS_FM<0x6, 17>, FGR_64 { 514 let DecoderNamespace = "MipsFP64"; 515} 516 517/// Floating Point Memory Instructions 518let AdditionalPredicates = [NotInMicroMips] in { 519 def LWC1 : MMRel, LW_FT<"lwc1", FGR32Opnd, mem_simm16, II_LWC1, load>, 520 LW_FM<0x31>; 521 def SWC1 : MMRel, SW_FT<"swc1", FGR32Opnd, mem_simm16, II_SWC1, store>, 522 LW_FM<0x39>; 523} 524 525let DecoderNamespace = "MipsFP64", AdditionalPredicates = [NotInMicroMips] in { 526 def LDC164 : StdMMR6Rel, LW_FT<"ldc1", FGR64Opnd, mem_simm16, II_LDC1, load>, 527 LW_FM<0x35>, ISA_MIPS2, FGR_64 { 528 let BaseOpcode = "LDC164"; 529 } 530 def SDC164 : StdMMR6Rel, SW_FT<"sdc1", FGR64Opnd, mem_simm16, II_SDC1, store>, 531 LW_FM<0x3d>, ISA_MIPS2, FGR_64; 532} 533 534let AdditionalPredicates = [NotInMicroMips] in { 535 def LDC1 : MMRel, StdMMR6Rel, LW_FT<"ldc1", AFGR64Opnd, mem_simm16, II_LDC1, 536 load>, LW_FM<0x35>, ISA_MIPS2, FGR_32 { 537 let BaseOpcode = "LDC132"; 538 } 539 def SDC1 : MMRel, SW_FT<"sdc1", AFGR64Opnd, mem_simm16, II_SDC1, store>, 540 LW_FM<0x3d>, ISA_MIPS2, FGR_32; 541} 542 543// Indexed loads and stores. 544// Base register + offset register addressing mode (indicated by "x" in the 545// instruction mnemonic) is disallowed under NaCl. 546let AdditionalPredicates = [IsNotNaCl] in { 547 def LWXC1 : MMRel, LWXC1_FT<"lwxc1", FGR32Opnd, II_LWXC1, load>, LWXC1_FM<0>, 548 INSN_MIPS4_32R2_NOT_32R6_64R6; 549 def SWXC1 : MMRel, SWXC1_FT<"swxc1", FGR32Opnd, II_SWXC1, store>, SWXC1_FM<8>, 550 INSN_MIPS4_32R2_NOT_32R6_64R6; 551} 552 553let AdditionalPredicates = [NotInMicroMips, IsNotNaCl] in { 554 def LDXC1 : LWXC1_FT<"ldxc1", AFGR64Opnd, II_LDXC1, load>, LWXC1_FM<1>, 555 INSN_MIPS4_32R2_NOT_32R6_64R6, FGR_32; 556 def SDXC1 : SWXC1_FT<"sdxc1", AFGR64Opnd, II_SDXC1, store>, SWXC1_FM<9>, 557 INSN_MIPS4_32R2_NOT_32R6_64R6, FGR_32; 558} 559 560let DecoderNamespace="MipsFP64" in { 561 def LDXC164 : LWXC1_FT<"ldxc1", FGR64Opnd, II_LDXC1, load>, LWXC1_FM<1>, 562 INSN_MIPS4_32R2_NOT_32R6_64R6, FGR_64; 563 def SDXC164 : SWXC1_FT<"sdxc1", FGR64Opnd, II_SDXC1, store>, SWXC1_FM<9>, 564 INSN_MIPS4_32R2_NOT_32R6_64R6, FGR_64; 565} 566 567// Load/store doubleword indexed unaligned. 568// FIXME: This instruction should not be defined for FGR_32. 569let AdditionalPredicates = [IsNotNaCl] in { 570 def LUXC1 : MMRel, LWXC1_FT<"luxc1", AFGR64Opnd, II_LUXC1>, LWXC1_FM<0x5>, 571 INSN_MIPS5_32R2_NOT_32R6_64R6, FGR_32; 572 def SUXC1 : MMRel, SWXC1_FT<"suxc1", AFGR64Opnd, II_SUXC1>, SWXC1_FM<0xd>, 573 INSN_MIPS5_32R2_NOT_32R6_64R6, FGR_32; 574} 575 576let DecoderNamespace="MipsFP64" in { 577 def LUXC164 : LWXC1_FT<"luxc1", FGR64Opnd, II_LUXC1>, LWXC1_FM<0x5>, 578 INSN_MIPS5_32R2_NOT_32R6_64R6, FGR_64; 579 def SUXC164 : SWXC1_FT<"suxc1", FGR64Opnd, II_SUXC1>, SWXC1_FM<0xd>, 580 INSN_MIPS5_32R2_NOT_32R6_64R6, FGR_64; 581} 582 583/// Floating-point Aritmetic 584def FADD_S : MMRel, ADDS_FT<"add.s", FGR32Opnd, II_ADD_S, 1, fadd>, 585 ADDS_FM<0x00, 16>; 586defm FADD : ADDS_M<"add.d", II_ADD_D, 1, fadd>, ADDS_FM<0x00, 17>; 587def FDIV_S : MMRel, ADDS_FT<"div.s", FGR32Opnd, II_DIV_S, 0, fdiv>, 588 ADDS_FM<0x03, 16>; 589defm FDIV : ADDS_M<"div.d", II_DIV_D, 0, fdiv>, ADDS_FM<0x03, 17>; 590def FMUL_S : MMRel, ADDS_FT<"mul.s", FGR32Opnd, II_MUL_S, 1, fmul>, 591 ADDS_FM<0x02, 16>; 592defm FMUL : ADDS_M<"mul.d", II_MUL_D, 1, fmul>, ADDS_FM<0x02, 17>; 593def FSUB_S : MMRel, ADDS_FT<"sub.s", FGR32Opnd, II_SUB_S, 0, fsub>, 594 ADDS_FM<0x01, 16>; 595defm FSUB : ADDS_M<"sub.d", II_SUB_D, 0, fsub>, ADDS_FM<0x01, 17>; 596 597def MADD_S : MMRel, MADDS_FT<"madd.s", FGR32Opnd, II_MADD_S, fadd>, 598 MADDS_FM<4, 0>, INSN_MIPS4_32R2_NOT_32R6_64R6, MADD4; 599def MSUB_S : MMRel, MADDS_FT<"msub.s", FGR32Opnd, II_MSUB_S, fsub>, 600 MADDS_FM<5, 0>, INSN_MIPS4_32R2_NOT_32R6_64R6, MADD4; 601 602let AdditionalPredicates = [NoNaNsFPMath, HasMadd4] in { 603 def NMADD_S : MMRel, NMADDS_FT<"nmadd.s", FGR32Opnd, II_NMADD_S, fadd>, 604 MADDS_FM<6, 0>, INSN_MIPS4_32R2_NOT_32R6_64R6; 605 def NMSUB_S : MMRel, NMADDS_FT<"nmsub.s", FGR32Opnd, II_NMSUB_S, fsub>, 606 MADDS_FM<7, 0>, INSN_MIPS4_32R2_NOT_32R6_64R6; 607} 608 609def MADD_D32 : MMRel, MADDS_FT<"madd.d", AFGR64Opnd, II_MADD_D, fadd>, 610 MADDS_FM<4, 1>, INSN_MIPS4_32R2_NOT_32R6_64R6, FGR_32, MADD4; 611def MSUB_D32 : MMRel, MADDS_FT<"msub.d", AFGR64Opnd, II_MSUB_D, fsub>, 612 MADDS_FM<5, 1>, INSN_MIPS4_32R2_NOT_32R6_64R6, FGR_32, MADD4; 613 614let AdditionalPredicates = [NoNaNsFPMath, HasMadd4] in { 615 def NMADD_D32 : MMRel, NMADDS_FT<"nmadd.d", AFGR64Opnd, II_NMADD_D, fadd>, 616 MADDS_FM<6, 1>, INSN_MIPS4_32R2_NOT_32R6_64R6, FGR_32; 617 def NMSUB_D32 : MMRel, NMADDS_FT<"nmsub.d", AFGR64Opnd, II_NMSUB_D, fsub>, 618 MADDS_FM<7, 1>, INSN_MIPS4_32R2_NOT_32R6_64R6, FGR_32; 619} 620 621let DecoderNamespace = "MipsFP64" in { 622 def MADD_D64 : MADDS_FT<"madd.d", FGR64Opnd, II_MADD_D, fadd>, 623 MADDS_FM<4, 1>, INSN_MIPS4_32R2_NOT_32R6_64R6, FGR_64, MADD4; 624 def MSUB_D64 : MADDS_FT<"msub.d", FGR64Opnd, II_MSUB_D, fsub>, 625 MADDS_FM<5, 1>, INSN_MIPS4_32R2_NOT_32R6_64R6, FGR_64, MADD4; 626} 627 628let AdditionalPredicates = [NoNaNsFPMath, HasMadd4], 629 DecoderNamespace = "MipsFP64" in { 630 def NMADD_D64 : NMADDS_FT<"nmadd.d", FGR64Opnd, II_NMADD_D, fadd>, 631 MADDS_FM<6, 1>, INSN_MIPS4_32R2_NOT_32R6_64R6, FGR_64; 632 def NMSUB_D64 : NMADDS_FT<"nmsub.d", FGR64Opnd, II_NMSUB_D, fsub>, 633 MADDS_FM<7, 1>, INSN_MIPS4_32R2_NOT_32R6_64R6, FGR_64; 634} 635 636//===----------------------------------------------------------------------===// 637// Floating Point Branch Codes 638//===----------------------------------------------------------------------===// 639// Mips branch codes. These correspond to condcode in MipsInstrInfo.h. 640// They must be kept in synch. 641def MIPS_BRANCH_F : PatLeaf<(i32 0)>; 642def MIPS_BRANCH_T : PatLeaf<(i32 1)>; 643 644def BC1F : MMRel, BC1F_FT<"bc1f", brtarget, II_BC1F, MIPS_BRANCH_F>, 645 BC1F_FM<0, 0>, ISA_MIPS1_NOT_32R6_64R6; 646def BC1FL : MMRel, BC1XL_FT<"bc1fl", brtarget, II_BC1FL>, 647 BC1F_FM<1, 0>, ISA_MIPS2_NOT_32R6_64R6; 648def BC1T : MMRel, BC1F_FT<"bc1t", brtarget, II_BC1T, MIPS_BRANCH_T>, 649 BC1F_FM<0, 1>, ISA_MIPS1_NOT_32R6_64R6; 650def BC1TL : MMRel, BC1XL_FT<"bc1tl", brtarget, II_BC1TL>, 651 BC1F_FM<1, 1>, ISA_MIPS2_NOT_32R6_64R6; 652 653/// Floating Point Compare 654let AdditionalPredicates = [NotInMicroMips] in { 655 def FCMP_S32 : MMRel, CEQS_FT<"s", FGR32, II_C_CC_S, MipsFPCmp>, CEQS_FM<16>, 656 ISA_MIPS1_NOT_32R6_64R6 { 657 658 // FIXME: This is a required to work around the fact that these instructions 659 // only use $fcc0. Ideally, MipsFPCmp nodes could be removed and the 660 // fcc register set is used directly. 661 bits<3> fcc = 0; 662 } 663 def FCMP_D32 : MMRel, CEQS_FT<"d", AFGR64, II_C_CC_D, MipsFPCmp>, CEQS_FM<17>, 664 ISA_MIPS1_NOT_32R6_64R6, FGR_32 { 665 // FIXME: This is a required to work around the fact that these instructions 666 // only use $fcc0. Ideally, MipsFPCmp nodes could be removed and the 667 // fcc register set is used directly. 668 bits<3> fcc = 0; 669 } 670} 671let DecoderNamespace = "MipsFP64" in 672def FCMP_D64 : CEQS_FT<"d", FGR64, II_C_CC_D, MipsFPCmp>, CEQS_FM<17>, 673 ISA_MIPS1_NOT_32R6_64R6, FGR_64 { 674 // FIXME: This is a required to work around the fact that thiese instructions 675 // only use $fcc0. Ideally, MipsFPCmp nodes could be removed and the 676 // fcc register set is used directly. 677 bits<3> fcc = 0; 678} 679 680//===----------------------------------------------------------------------===// 681// Floating Point Pseudo-Instructions 682//===----------------------------------------------------------------------===// 683 684// This pseudo instr gets expanded into 2 mtc1 instrs after register 685// allocation. 686class BuildPairF64Base<RegisterOperand RO> : 687 PseudoSE<(outs RO:$dst), (ins GPR32Opnd:$lo, GPR32Opnd:$hi), 688 [(set RO:$dst, (MipsBuildPairF64 GPR32Opnd:$lo, GPR32Opnd:$hi))], 689 II_MTC1>; 690 691def BuildPairF64 : BuildPairF64Base<AFGR64Opnd>, FGR_32, HARDFLOAT; 692def BuildPairF64_64 : BuildPairF64Base<FGR64Opnd>, FGR_64, HARDFLOAT; 693 694// This pseudo instr gets expanded into 2 mfc1 instrs after register 695// allocation. 696// if n is 0, lower part of src is extracted. 697// if n is 1, higher part of src is extracted. 698// This node has associated scheduling information as the pre RA scheduler 699// asserts otherwise. 700class ExtractElementF64Base<RegisterOperand RO> : 701 PseudoSE<(outs GPR32Opnd:$dst), (ins RO:$src, i32imm:$n), 702 [(set GPR32Opnd:$dst, (MipsExtractElementF64 RO:$src, imm:$n))], 703 II_MFC1>; 704 705def ExtractElementF64 : ExtractElementF64Base<AFGR64Opnd>, FGR_32, HARDFLOAT; 706def ExtractElementF64_64 : ExtractElementF64Base<FGR64Opnd>, FGR_64, HARDFLOAT; 707 708def PseudoTRUNC_W_S : MipsAsmPseudoInst<(outs FGR32Opnd:$fd), 709 (ins FGR32Opnd:$fs, GPR32Opnd:$rs), 710 "trunc.w.s\t$fd, $fs, $rs">; 711 712def PseudoTRUNC_W_D32 : MipsAsmPseudoInst<(outs FGR32Opnd:$fd), 713 (ins AFGR64Opnd:$fs, GPR32Opnd:$rs), 714 "trunc.w.d\t$fd, $fs, $rs">, 715 FGR_32, HARDFLOAT; 716 717def PseudoTRUNC_W_D : MipsAsmPseudoInst<(outs FGR32Opnd:$fd), 718 (ins FGR64Opnd:$fs, GPR32Opnd:$rs), 719 "trunc.w.d\t$fd, $fs, $rs">, 720 FGR_64, HARDFLOAT; 721 722def LoadImmSingleGPR : MipsAsmPseudoInst<(outs GPR32Opnd:$rd), 723 (ins imm64:$fpimm), 724 "li.s\t$rd, $fpimm">; 725 726def LoadImmSingleFGR : MipsAsmPseudoInst<(outs StrictlyFGR32Opnd:$rd), 727 (ins imm64:$fpimm), 728 "li.s\t$rd, $fpimm">, 729 HARDFLOAT; 730 731def LoadImmDoubleGPR : MipsAsmPseudoInst<(outs GPR32Opnd:$rd), 732 (ins imm64:$fpimm), 733 "li.d\t$rd, $fpimm">; 734 735def LoadImmDoubleFGR_32 : MipsAsmPseudoInst<(outs StrictlyAFGR64Opnd:$rd), 736 (ins imm64:$fpimm), 737 "li.d\t$rd, $fpimm">, 738 FGR_32, HARDFLOAT; 739 740def LoadImmDoubleFGR : MipsAsmPseudoInst<(outs StrictlyFGR64Opnd:$rd), 741 (ins imm64:$fpimm), 742 "li.d\t$rd, $fpimm">, 743 FGR_64, HARDFLOAT; 744 745//===----------------------------------------------------------------------===// 746// InstAliases. 747//===----------------------------------------------------------------------===// 748def : MipsInstAlias 749 <"s.s $fd, $addr", (SWC1 FGR32Opnd:$fd, mem_simm16:$addr), 0>, 750 ISA_MIPS2, HARDFLOAT; 751def : MipsInstAlias 752 <"s.d $fd, $addr", (SDC1 AFGR64Opnd:$fd, mem_simm16:$addr), 0>, 753 FGR_32, ISA_MIPS2, HARDFLOAT; 754def : MipsInstAlias 755 <"s.d $fd, $addr", (SDC164 FGR64Opnd:$fd, mem_simm16:$addr), 0>, 756 FGR_64, ISA_MIPS2, HARDFLOAT; 757 758def : MipsInstAlias 759 <"l.s $fd, $addr", (LWC1 FGR32Opnd:$fd, mem_simm16:$addr), 0>, 760 ISA_MIPS2, HARDFLOAT; 761def : MipsInstAlias 762 <"l.d $fd, $addr", (LDC1 AFGR64Opnd:$fd, mem_simm16:$addr), 0>, 763 FGR_32, ISA_MIPS2, HARDFLOAT; 764def : MipsInstAlias 765 <"l.d $fd, $addr", (LDC164 FGR64Opnd:$fd, mem_simm16:$addr), 0>, 766 FGR_64, ISA_MIPS2, HARDFLOAT; 767 768multiclass C_COND_ALIASES<string TypeStr, RegisterOperand RC> { 769 def : MipsInstAlias<!strconcat("c.f.", TypeStr, " $fs, $ft"), 770 (!cast<Instruction>("C_F_"#NAME) FCC0, 771 RC:$fs, RC:$ft), 1>; 772 def : MipsInstAlias<!strconcat("c.un.", TypeStr, " $fs, $ft"), 773 (!cast<Instruction>("C_UN_"#NAME) FCC0, 774 RC:$fs, RC:$ft), 1>; 775 def : MipsInstAlias<!strconcat("c.eq.", TypeStr, " $fs, $ft"), 776 (!cast<Instruction>("C_EQ_"#NAME) FCC0, 777 RC:$fs, RC:$ft), 1>; 778 def : MipsInstAlias<!strconcat("c.ueq.", TypeStr, " $fs, $ft"), 779 (!cast<Instruction>("C_UEQ_"#NAME) FCC0, 780 RC:$fs, RC:$ft), 1>; 781 def : MipsInstAlias<!strconcat("c.olt.", TypeStr, " $fs, $ft"), 782 (!cast<Instruction>("C_OLT_"#NAME) FCC0, 783 RC:$fs, RC:$ft), 1>; 784 def : MipsInstAlias<!strconcat("c.ult.", TypeStr, " $fs, $ft"), 785 (!cast<Instruction>("C_ULT_"#NAME) FCC0, 786 RC:$fs, RC:$ft), 1>; 787 def : MipsInstAlias<!strconcat("c.ole.", TypeStr, " $fs, $ft"), 788 (!cast<Instruction>("C_OLE_"#NAME) FCC0, 789 RC:$fs, RC:$ft), 1>; 790 def : MipsInstAlias<!strconcat("c.ule.", TypeStr, " $fs, $ft"), 791 (!cast<Instruction>("C_ULE_"#NAME) FCC0, 792 RC:$fs, RC:$ft), 1>; 793 def : MipsInstAlias<!strconcat("c.sf.", TypeStr, " $fs, $ft"), 794 (!cast<Instruction>("C_SF_"#NAME) FCC0, 795 RC:$fs, RC:$ft), 1>; 796 def : MipsInstAlias<!strconcat("c.ngle.", TypeStr, " $fs, $ft"), 797 (!cast<Instruction>("C_NGLE_"#NAME) FCC0, 798 RC:$fs, RC:$ft), 1>; 799 def : MipsInstAlias<!strconcat("c.seq.", TypeStr, " $fs, $ft"), 800 (!cast<Instruction>("C_SEQ_"#NAME) FCC0, 801 RC:$fs, RC:$ft), 1>; 802 def : MipsInstAlias<!strconcat("c.ngl.", TypeStr, " $fs, $ft"), 803 (!cast<Instruction>("C_NGL_"#NAME) FCC0, 804 RC:$fs, RC:$ft), 1>; 805 def : MipsInstAlias<!strconcat("c.lt.", TypeStr, " $fs, $ft"), 806 (!cast<Instruction>("C_LT_"#NAME) FCC0, 807 RC:$fs, RC:$ft), 1>; 808 def : MipsInstAlias<!strconcat("c.nge.", TypeStr, " $fs, $ft"), 809 (!cast<Instruction>("C_NGE_"#NAME) FCC0, 810 RC:$fs, RC:$ft), 1>; 811 def : MipsInstAlias<!strconcat("c.le.", TypeStr, " $fs, $ft"), 812 (!cast<Instruction>("C_LE_"#NAME) FCC0, 813 RC:$fs, RC:$ft), 1>; 814 def : MipsInstAlias<!strconcat("c.ngt.", TypeStr, " $fs, $ft"), 815 (!cast<Instruction>("C_NGT_"#NAME) FCC0, 816 RC:$fs, RC:$ft), 1>; 817} 818 819multiclass BC1_ALIASES<Instruction BCTrue, string BCTrueString, 820 Instruction BCFalse, string BCFalseString> { 821 def : MipsInstAlias<!strconcat(BCTrueString, " $offset"), 822 (BCTrue FCC0, brtarget:$offset), 1>; 823 824 def : MipsInstAlias<!strconcat(BCFalseString, " $offset"), 825 (BCFalse FCC0, brtarget:$offset), 1>; 826} 827 828let AdditionalPredicates = [NotInMicroMips] in { 829 defm S : C_COND_ALIASES<"s", FGR32Opnd>, HARDFLOAT, 830 ISA_MIPS1_NOT_32R6_64R6; 831 defm D32 : C_COND_ALIASES<"d", AFGR64Opnd>, HARDFLOAT, 832 ISA_MIPS1_NOT_32R6_64R6, FGR_32; 833 defm D64 : C_COND_ALIASES<"d", FGR64Opnd>, HARDFLOAT, 834 ISA_MIPS1_NOT_32R6_64R6, FGR_64; 835 836 defm : BC1_ALIASES<BC1T, "bc1t", BC1F, "bc1f">, ISA_MIPS1_NOT_32R6_64R6, 837 HARDFLOAT; 838 defm : BC1_ALIASES<BC1TL, "bc1tl", BC1FL, "bc1fl">, ISA_MIPS2_NOT_32R6_64R6, 839 HARDFLOAT; 840} 841//===----------------------------------------------------------------------===// 842// Floating Point Patterns 843//===----------------------------------------------------------------------===// 844def : MipsPat<(f32 fpimm0), (MTC1 ZERO)>; 845def : MipsPat<(f32 fpimm0neg), (FNEG_S (MTC1 ZERO))>; 846 847def : MipsPat<(f32 (sint_to_fp GPR32Opnd:$src)), 848 (PseudoCVT_S_W GPR32Opnd:$src)>; 849def : MipsPat<(MipsTruncIntFP FGR32Opnd:$src), 850 (TRUNC_W_S FGR32Opnd:$src)>; 851 852def : MipsPat<(MipsMTC1_D64 GPR32Opnd:$src), 853 (MTC1_D64 GPR32Opnd:$src)>, FGR_64; 854 855def : MipsPat<(f64 (sint_to_fp GPR32Opnd:$src)), 856 (PseudoCVT_D32_W GPR32Opnd:$src)>, FGR_32; 857def : MipsPat<(MipsTruncIntFP AFGR64Opnd:$src), 858 (TRUNC_W_D32 AFGR64Opnd:$src)>, FGR_32; 859def : MipsPat<(f32 (fpround AFGR64Opnd:$src)), 860 (CVT_S_D32 AFGR64Opnd:$src)>, FGR_32; 861def : MipsPat<(f64 (fpextend FGR32Opnd:$src)), 862 (CVT_D32_S FGR32Opnd:$src)>, FGR_32; 863 864def : MipsPat<(f64 fpimm0), (DMTC1 ZERO_64)>, FGR_64; 865def : MipsPat<(f64 fpimm0neg), (FNEG_D64 (DMTC1 ZERO_64))>, FGR_64; 866 867def : MipsPat<(f64 (sint_to_fp GPR32Opnd:$src)), 868 (PseudoCVT_D64_W GPR32Opnd:$src)>, FGR_64; 869def : MipsPat<(f32 (sint_to_fp GPR64Opnd:$src)), 870 (EXTRACT_SUBREG (PseudoCVT_S_L GPR64Opnd:$src), sub_lo)>, FGR_64; 871def : MipsPat<(f64 (sint_to_fp GPR64Opnd:$src)), 872 (PseudoCVT_D64_L GPR64Opnd:$src)>, FGR_64; 873 874def : MipsPat<(MipsTruncIntFP FGR64Opnd:$src), 875 (TRUNC_W_D64 FGR64Opnd:$src)>, FGR_64; 876def : MipsPat<(MipsTruncIntFP FGR32Opnd:$src), 877 (TRUNC_L_S FGR32Opnd:$src)>, FGR_64; 878def : MipsPat<(MipsTruncIntFP FGR64Opnd:$src), 879 (TRUNC_L_D64 FGR64Opnd:$src)>, FGR_64; 880 881def : MipsPat<(f32 (fpround FGR64Opnd:$src)), 882 (CVT_S_D64 FGR64Opnd:$src)>, FGR_64; 883def : MipsPat<(f64 (fpextend FGR32Opnd:$src)), 884 (CVT_D64_S FGR32Opnd:$src)>, FGR_64; 885 886// To generate NMADD and NMSUB instructions when fneg node is present 887multiclass NMADD_NMSUB<Instruction Nmadd, Instruction Nmsub, RegisterOperand RC> { 888 def : MipsPat<(fneg (fadd (fmul RC:$fs, RC:$ft), RC:$fr)), 889 (Nmadd RC:$fr, RC:$fs, RC:$ft)>; 890 def : MipsPat<(fneg (fsub (fmul RC:$fs, RC:$ft), RC:$fr)), 891 (Nmsub RC:$fr, RC:$fs, RC:$ft)>; 892} 893 894let AdditionalPredicates = [NoNaNsFPMath, HasMadd4, NotInMicroMips] in { 895 defm : NMADD_NMSUB<NMADD_S, NMSUB_S, FGR32Opnd>, INSN_MIPS4_32R2_NOT_32R6_64R6; 896 defm : NMADD_NMSUB<NMADD_D32, NMSUB_D32, AFGR64Opnd>, FGR_32, INSN_MIPS4_32R2_NOT_32R6_64R6; 897 defm : NMADD_NMSUB<NMADD_D64, NMSUB_D64, FGR64Opnd>, FGR_64, INSN_MIPS4_32R2_NOT_32R6_64R6; 898} 899 900// Patterns for loads/stores with a reg+imm operand. 901let AdditionalPredicates = [NotInMicroMips] in { 902 let AddedComplexity = 40 in { 903 def : LoadRegImmPat<LWC1, f32, load>; 904 def : StoreRegImmPat<SWC1, f32>; 905 906 def : LoadRegImmPat<LDC164, f64, load>, FGR_64; 907 def : StoreRegImmPat<SDC164, f64>, FGR_64; 908 909 def : LoadRegImmPat<LDC1, f64, load>, FGR_32; 910 def : StoreRegImmPat<SDC1, f64>, FGR_32; 911 } 912} 913