1 //===-- MipsISelLowering.h - Mips DAG Lowering Interface --------*- C++ -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file defines the interfaces that Mips uses to lower LLVM code into a 11 // selection DAG. 12 // 13 //===----------------------------------------------------------------------===// 14 15 #ifndef LLVM_LIB_TARGET_MIPS_MIPSISELLOWERING_H 16 #define LLVM_LIB_TARGET_MIPS_MIPSISELLOWERING_H 17 18 #include "MCTargetDesc/MipsBaseInfo.h" 19 #include "Mips.h" 20 #include "llvm/CodeGen/CallingConvLower.h" 21 #include "llvm/CodeGen/SelectionDAG.h" 22 #include "llvm/IR/Function.h" 23 #include "llvm/Target/TargetLowering.h" 24 #include <deque> 25 #include <string> 26 27 namespace llvm { 28 namespace MipsISD { 29 enum NodeType { 30 // Start the numbering from where ISD NodeType finishes. 31 FIRST_NUMBER = ISD::BUILTIN_OP_END, 32 33 // Jump and link (call) 34 JmpLink, 35 36 // Tail call 37 TailCall, 38 39 // Get the Higher 16 bits from a 32-bit immediate 40 // No relation with Mips Hi register 41 Hi, 42 43 // Get the Lower 16 bits from a 32-bit immediate 44 // No relation with Mips Lo register 45 Lo, 46 47 // Handle gp_rel (small data/bss sections) relocation. 48 GPRel, 49 50 // Thread Pointer 51 ThreadPointer, 52 53 // Floating Point Branch Conditional 54 FPBrcond, 55 56 // Floating Point Compare 57 FPCmp, 58 59 // Floating Point Conditional Moves 60 CMovFP_T, 61 CMovFP_F, 62 63 // FP-to-int truncation node. 64 TruncIntFP, 65 66 // Return 67 Ret, 68 69 EH_RETURN, 70 71 // Node used to extract integer from accumulator. 72 MFHI, 73 MFLO, 74 75 // Node used to insert integers to accumulator. 76 MTLOHI, 77 78 // Mult nodes. 79 Mult, 80 Multu, 81 82 // MAdd/Sub nodes 83 MAdd, 84 MAddu, 85 MSub, 86 MSubu, 87 88 // DivRem(u) 89 DivRem, 90 DivRemU, 91 DivRem16, 92 DivRemU16, 93 94 BuildPairF64, 95 ExtractElementF64, 96 97 Wrapper, 98 99 DynAlloc, 100 101 Sync, 102 103 Ext, 104 Ins, 105 106 // EXTR.W instrinsic nodes. 107 EXTP, 108 EXTPDP, 109 EXTR_S_H, 110 EXTR_W, 111 EXTR_R_W, 112 EXTR_RS_W, 113 SHILO, 114 MTHLIP, 115 116 // DPA.W intrinsic nodes. 117 MULSAQ_S_W_PH, 118 MAQ_S_W_PHL, 119 MAQ_S_W_PHR, 120 MAQ_SA_W_PHL, 121 MAQ_SA_W_PHR, 122 DPAU_H_QBL, 123 DPAU_H_QBR, 124 DPSU_H_QBL, 125 DPSU_H_QBR, 126 DPAQ_S_W_PH, 127 DPSQ_S_W_PH, 128 DPAQ_SA_L_W, 129 DPSQ_SA_L_W, 130 DPA_W_PH, 131 DPS_W_PH, 132 DPAQX_S_W_PH, 133 DPAQX_SA_W_PH, 134 DPAX_W_PH, 135 DPSX_W_PH, 136 DPSQX_S_W_PH, 137 DPSQX_SA_W_PH, 138 MULSA_W_PH, 139 140 MULT, 141 MULTU, 142 MADD_DSP, 143 MADDU_DSP, 144 MSUB_DSP, 145 MSUBU_DSP, 146 147 // DSP shift nodes. 148 SHLL_DSP, 149 SHRA_DSP, 150 SHRL_DSP, 151 152 // DSP setcc and select_cc nodes. 153 SETCC_DSP, 154 SELECT_CC_DSP, 155 156 // Vector comparisons. 157 // These take a vector and return a boolean. 158 VALL_ZERO, 159 VANY_ZERO, 160 VALL_NONZERO, 161 VANY_NONZERO, 162 163 // These take a vector and return a vector bitmask. 164 VCEQ, 165 VCLE_S, 166 VCLE_U, 167 VCLT_S, 168 VCLT_U, 169 170 // Element-wise vector max/min. 171 VSMAX, 172 VSMIN, 173 VUMAX, 174 VUMIN, 175 176 // Vector Shuffle with mask as an operand 177 VSHF, // Generic shuffle 178 SHF, // 4-element set shuffle. 179 ILVEV, // Interleave even elements 180 ILVOD, // Interleave odd elements 181 ILVL, // Interleave left elements 182 ILVR, // Interleave right elements 183 PCKEV, // Pack even elements 184 PCKOD, // Pack odd elements 185 186 // Vector Lane Copy 187 INSVE, // Copy element from one vector to another 188 189 // Combined (XOR (OR $a, $b), -1) 190 VNOR, 191 192 // Extended vector element extraction 193 VEXTRACT_SEXT_ELT, 194 VEXTRACT_ZEXT_ELT, 195 196 // Load/Store Left/Right nodes. 197 LWL = ISD::FIRST_TARGET_MEMORY_OPCODE, 198 LWR, 199 SWL, 200 SWR, 201 LDL, 202 LDR, 203 SDL, 204 SDR 205 }; 206 } 207 208 //===--------------------------------------------------------------------===// 209 // TargetLowering Implementation 210 //===--------------------------------------------------------------------===// 211 class MipsFunctionInfo; 212 class MipsSubtarget; 213 214 class MipsTargetLowering : public TargetLowering { 215 bool isMicroMips; 216 public: 217 explicit MipsTargetLowering(const MipsTargetMachine &TM, 218 const MipsSubtarget &STI); 219 220 static const MipsTargetLowering *create(const MipsTargetMachine &TM, 221 const MipsSubtarget &STI); 222 223 /// createFastISel - This method returns a target specific FastISel object, 224 /// or null if the target does not support "fast" ISel. 225 FastISel *createFastISel(FunctionLoweringInfo &funcInfo, 226 const TargetLibraryInfo *libInfo) const override; 227 228 MVT getScalarShiftAmountTy(EVT LHSTy) const override { return MVT::i32; } 229 230 void LowerOperationWrapper(SDNode *N, 231 SmallVectorImpl<SDValue> &Results, 232 SelectionDAG &DAG) const override; 233 234 /// LowerOperation - Provide custom lowering hooks for some operations. 235 SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override; 236 237 /// ReplaceNodeResults - Replace the results of node with an illegal result 238 /// type with new values built out of custom code. 239 /// 240 void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue>&Results, 241 SelectionDAG &DAG) const override; 242 243 /// getTargetNodeName - This method returns the name of a target specific 244 // DAG node. 245 const char *getTargetNodeName(unsigned Opcode) const override; 246 247 /// getSetCCResultType - get the ISD::SETCC result ValueType 248 EVT getSetCCResultType(LLVMContext &Context, EVT VT) const override; 249 250 SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override; 251 252 MachineBasicBlock * 253 EmitInstrWithCustomInserter(MachineInstr *MI, 254 MachineBasicBlock *MBB) const override; 255 256 struct LTStr { 257 bool operator()(const char *S1, const char *S2) const { 258 return strcmp(S1, S2) < 0; 259 } 260 }; 261 262 protected: 263 SDValue getGlobalReg(SelectionDAG &DAG, EVT Ty) const; 264 265 // This method creates the following nodes, which are necessary for 266 // computing a local symbol's address: 267 // 268 // (add (load (wrapper $gp, %got(sym)), %lo(sym)) 269 template <class NodeTy> 270 SDValue getAddrLocal(NodeTy *N, EVT Ty, SelectionDAG &DAG, 271 bool IsN32OrN64) const { 272 SDLoc DL(N); 273 unsigned GOTFlag = IsN32OrN64 ? MipsII::MO_GOT_PAGE : MipsII::MO_GOT; 274 SDValue GOT = DAG.getNode(MipsISD::Wrapper, DL, Ty, getGlobalReg(DAG, Ty), 275 getTargetNode(N, Ty, DAG, GOTFlag)); 276 SDValue Load = DAG.getLoad(Ty, DL, DAG.getEntryNode(), GOT, 277 MachinePointerInfo::getGOT(), false, false, 278 false, 0); 279 unsigned LoFlag = IsN32OrN64 ? MipsII::MO_GOT_OFST : MipsII::MO_ABS_LO; 280 SDValue Lo = DAG.getNode(MipsISD::Lo, DL, Ty, 281 getTargetNode(N, Ty, DAG, LoFlag)); 282 return DAG.getNode(ISD::ADD, DL, Ty, Load, Lo); 283 } 284 285 // This method creates the following nodes, which are necessary for 286 // computing a global symbol's address: 287 // 288 // (load (wrapper $gp, %got(sym))) 289 template<class NodeTy> 290 SDValue getAddrGlobal(NodeTy *N, EVT Ty, SelectionDAG &DAG, 291 unsigned Flag, SDValue Chain, 292 const MachinePointerInfo &PtrInfo) const { 293 SDLoc DL(N); 294 SDValue Tgt = DAG.getNode(MipsISD::Wrapper, DL, Ty, getGlobalReg(DAG, Ty), 295 getTargetNode(N, Ty, DAG, Flag)); 296 return DAG.getLoad(Ty, DL, Chain, Tgt, PtrInfo, false, false, false, 0); 297 } 298 299 // This method creates the following nodes, which are necessary for 300 // computing a global symbol's address in large-GOT mode: 301 // 302 // (load (wrapper (add %hi(sym), $gp), %lo(sym))) 303 template<class NodeTy> 304 SDValue getAddrGlobalLargeGOT(NodeTy *N, EVT Ty, SelectionDAG &DAG, 305 unsigned HiFlag, unsigned LoFlag, 306 SDValue Chain, 307 const MachinePointerInfo &PtrInfo) const { 308 SDLoc DL(N); 309 SDValue Hi = DAG.getNode(MipsISD::Hi, DL, Ty, 310 getTargetNode(N, Ty, DAG, HiFlag)); 311 Hi = DAG.getNode(ISD::ADD, DL, Ty, Hi, getGlobalReg(DAG, Ty)); 312 SDValue Wrapper = DAG.getNode(MipsISD::Wrapper, DL, Ty, Hi, 313 getTargetNode(N, Ty, DAG, LoFlag)); 314 return DAG.getLoad(Ty, DL, Chain, Wrapper, PtrInfo, false, false, false, 315 0); 316 } 317 318 // This method creates the following nodes, which are necessary for 319 // computing a symbol's address in non-PIC mode: 320 // 321 // (add %hi(sym), %lo(sym)) 322 template<class NodeTy> 323 SDValue getAddrNonPIC(NodeTy *N, EVT Ty, SelectionDAG &DAG) const { 324 SDLoc DL(N); 325 SDValue Hi = getTargetNode(N, Ty, DAG, MipsII::MO_ABS_HI); 326 SDValue Lo = getTargetNode(N, Ty, DAG, MipsII::MO_ABS_LO); 327 return DAG.getNode(ISD::ADD, DL, Ty, 328 DAG.getNode(MipsISD::Hi, DL, Ty, Hi), 329 DAG.getNode(MipsISD::Lo, DL, Ty, Lo)); 330 } 331 332 /// This function fills Ops, which is the list of operands that will later 333 /// be used when a function call node is created. It also generates 334 /// copyToReg nodes to set up argument registers. 335 virtual void 336 getOpndList(SmallVectorImpl<SDValue> &Ops, 337 std::deque< std::pair<unsigned, SDValue> > &RegsToPass, 338 bool IsPICCall, bool GlobalOrExternal, bool InternalLinkage, 339 bool IsCallReloc, CallLoweringInfo &CLI, SDValue Callee, 340 SDValue Chain) const; 341 342 /// ByValArgInfo - Byval argument information. 343 struct ByValArgInfo { 344 unsigned FirstIdx; // Index of the first register used. 345 unsigned NumRegs; // Number of registers used for this argument. 346 unsigned Address; // Offset of the stack area used to pass this argument. 347 348 ByValArgInfo() : FirstIdx(0), NumRegs(0), Address(0) {} 349 }; 350 351 /// MipsCC - This class provides methods used to analyze formal and call 352 /// arguments and inquire about calling convention information. 353 class MipsCC { 354 public: 355 enum SpecialCallingConvType { 356 Mips16RetHelperConv, NoSpecialCallingConv 357 }; 358 359 MipsCC(CallingConv::ID CallConv, const MipsSubtarget &Subtarget, 360 CCState &Info, 361 SpecialCallingConvType SpecialCallingConv = NoSpecialCallingConv); 362 363 void analyzeCallOperands(const SmallVectorImpl<ISD::OutputArg> &Outs, 364 bool IsVarArg, bool IsSoftFloat, 365 const SDNode *CallNode, 366 std::vector<ArgListEntry> &FuncArgs); 367 void analyzeFormalArguments(const SmallVectorImpl<ISD::InputArg> &Ins, 368 bool IsSoftFloat, 369 Function::const_arg_iterator FuncArg); 370 371 const CCState &getCCInfo() const { return CCInfo; } 372 373 /// hasByValArg - Returns true if function has byval arguments. 374 bool hasByValArg() const { return !ByValArgs.empty(); } 375 376 /// reservedArgArea - The size of the area the caller reserves for 377 /// register arguments. This is 16-byte if ABI is O32. 378 unsigned reservedArgArea() const; 379 380 /// Return pointer to array of integer argument registers. 381 const ArrayRef<MCPhysReg> intArgRegs() const; 382 383 typedef SmallVectorImpl<ByValArgInfo>::const_iterator byval_iterator; 384 byval_iterator byval_begin() const { return ByValArgs.begin(); } 385 byval_iterator byval_end() const { return ByValArgs.end(); } 386 387 private: 388 void handleByValArg(unsigned ValNo, MVT ValVT, MVT LocVT, 389 CCValAssign::LocInfo LocInfo, 390 ISD::ArgFlagsTy ArgFlags); 391 392 /// useRegsForByval - Returns true if the calling convention allows the 393 /// use of registers to pass byval arguments. 394 bool useRegsForByval() const { return CallConv != CallingConv::Fast; } 395 396 /// Return the function that analyzes fixed argument list functions. 397 llvm::CCAssignFn *fixedArgFn() const; 398 399 /// Return the function that analyzes variable argument list functions. 400 llvm::CCAssignFn *varArgFn() const; 401 402 const MCPhysReg *shadowRegs() const; 403 404 void allocateRegs(ByValArgInfo &ByVal, unsigned ByValSize, 405 unsigned Align); 406 407 /// Return the type of the register which is used to pass an argument or 408 /// return a value. This function returns f64 if the argument is an i64 409 /// value which has been generated as a result of softening an f128 value. 410 /// Otherwise, it just returns VT. 411 MVT getRegVT(MVT VT, const Type *OrigTy, const SDNode *CallNode, 412 bool IsSoftFloat) const; 413 414 template<typename Ty> 415 void analyzeReturn(const SmallVectorImpl<Ty> &RetVals, bool IsSoftFloat, 416 const SDNode *CallNode, const Type *RetTy) const; 417 418 CCState &CCInfo; 419 CallingConv::ID CallConv; 420 const MipsSubtarget &Subtarget; 421 SpecialCallingConvType SpecialCallingConv; 422 SmallVector<ByValArgInfo, 2> ByValArgs; 423 }; 424 protected: 425 SDValue lowerLOAD(SDValue Op, SelectionDAG &DAG) const; 426 SDValue lowerSTORE(SDValue Op, SelectionDAG &DAG) const; 427 428 // Subtarget Info 429 const MipsSubtarget &Subtarget; 430 431 private: 432 // Create a TargetGlobalAddress node. 433 SDValue getTargetNode(GlobalAddressSDNode *N, EVT Ty, SelectionDAG &DAG, 434 unsigned Flag) const; 435 436 // Create a TargetExternalSymbol node. 437 SDValue getTargetNode(ExternalSymbolSDNode *N, EVT Ty, SelectionDAG &DAG, 438 unsigned Flag) const; 439 440 // Create a TargetBlockAddress node. 441 SDValue getTargetNode(BlockAddressSDNode *N, EVT Ty, SelectionDAG &DAG, 442 unsigned Flag) const; 443 444 // Create a TargetJumpTable node. 445 SDValue getTargetNode(JumpTableSDNode *N, EVT Ty, SelectionDAG &DAG, 446 unsigned Flag) const; 447 448 // Create a TargetConstantPool node. 449 SDValue getTargetNode(ConstantPoolSDNode *N, EVT Ty, SelectionDAG &DAG, 450 unsigned Flag) const; 451 452 MipsCC::SpecialCallingConvType getSpecialCallingConv(SDValue Callee) const; 453 454 // Lower Operand helpers 455 SDValue LowerCallResult(SDValue Chain, SDValue InFlag, 456 CallingConv::ID CallConv, bool isVarArg, 457 const SmallVectorImpl<ISD::InputArg> &Ins, SDLoc dl, 458 SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals, 459 TargetLowering::CallLoweringInfo &CLI) const; 460 461 // Lower Operand specifics 462 SDValue lowerBR_JT(SDValue Op, SelectionDAG &DAG) const; 463 SDValue lowerBRCOND(SDValue Op, SelectionDAG &DAG) const; 464 SDValue lowerConstantPool(SDValue Op, SelectionDAG &DAG) const; 465 SDValue lowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const; 466 SDValue lowerBlockAddress(SDValue Op, SelectionDAG &DAG) const; 467 SDValue lowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const; 468 SDValue lowerJumpTable(SDValue Op, SelectionDAG &DAG) const; 469 SDValue lowerSELECT(SDValue Op, SelectionDAG &DAG) const; 470 SDValue lowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const; 471 SDValue lowerSETCC(SDValue Op, SelectionDAG &DAG) const; 472 SDValue lowerVASTART(SDValue Op, SelectionDAG &DAG) const; 473 SDValue lowerVAARG(SDValue Op, SelectionDAG &DAG) const; 474 SDValue lowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const; 475 SDValue lowerFABS(SDValue Op, SelectionDAG &DAG) const; 476 SDValue lowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const; 477 SDValue lowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const; 478 SDValue lowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const; 479 SDValue lowerATOMIC_FENCE(SDValue Op, SelectionDAG& DAG) const; 480 SDValue lowerShiftLeftParts(SDValue Op, SelectionDAG& DAG) const; 481 SDValue lowerShiftRightParts(SDValue Op, SelectionDAG& DAG, 482 bool IsSRA) const; 483 SDValue lowerADD(SDValue Op, SelectionDAG &DAG) const; 484 SDValue lowerFP_TO_SINT(SDValue Op, SelectionDAG &DAG) const; 485 486 /// isEligibleForTailCallOptimization - Check whether the call is eligible 487 /// for tail call optimization. 488 virtual bool 489 isEligibleForTailCallOptimization(const MipsCC &MipsCCInfo, 490 unsigned NextStackOffset, 491 const MipsFunctionInfo& FI) const = 0; 492 493 /// copyByValArg - Copy argument registers which were used to pass a byval 494 /// argument to the stack. Create a stack frame object for the byval 495 /// argument. 496 void copyByValRegs(SDValue Chain, SDLoc DL, 497 std::vector<SDValue> &OutChains, SelectionDAG &DAG, 498 const ISD::ArgFlagsTy &Flags, 499 SmallVectorImpl<SDValue> &InVals, 500 const Argument *FuncArg, 501 const MipsCC &CC, const ByValArgInfo &ByVal) const; 502 503 /// passByValArg - Pass a byval argument in registers or on stack. 504 void passByValArg(SDValue Chain, SDLoc DL, 505 std::deque< std::pair<unsigned, SDValue> > &RegsToPass, 506 SmallVectorImpl<SDValue> &MemOpChains, SDValue StackPtr, 507 MachineFrameInfo *MFI, SelectionDAG &DAG, SDValue Arg, 508 const MipsCC &CC, const ByValArgInfo &ByVal, 509 const ISD::ArgFlagsTy &Flags, bool isLittle) const; 510 511 /// writeVarArgRegs - Write variable function arguments passed in registers 512 /// to the stack. Also create a stack frame object for the first variable 513 /// argument. 514 void writeVarArgRegs(std::vector<SDValue> &OutChains, const MipsCC &CC, 515 SDValue Chain, SDLoc DL, SelectionDAG &DAG) const; 516 517 SDValue 518 LowerFormalArguments(SDValue Chain, 519 CallingConv::ID CallConv, bool isVarArg, 520 const SmallVectorImpl<ISD::InputArg> &Ins, 521 SDLoc dl, SelectionDAG &DAG, 522 SmallVectorImpl<SDValue> &InVals) const override; 523 524 SDValue passArgOnStack(SDValue StackPtr, unsigned Offset, SDValue Chain, 525 SDValue Arg, SDLoc DL, bool IsTailCall, 526 SelectionDAG &DAG) const; 527 528 SDValue LowerCall(TargetLowering::CallLoweringInfo &CLI, 529 SmallVectorImpl<SDValue> &InVals) const override; 530 531 bool CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF, 532 bool isVarArg, 533 const SmallVectorImpl<ISD::OutputArg> &Outs, 534 LLVMContext &Context) const override; 535 536 SDValue LowerReturn(SDValue Chain, 537 CallingConv::ID CallConv, bool isVarArg, 538 const SmallVectorImpl<ISD::OutputArg> &Outs, 539 const SmallVectorImpl<SDValue> &OutVals, 540 SDLoc dl, SelectionDAG &DAG) const override; 541 542 // Inline asm support 543 ConstraintType 544 getConstraintType(const std::string &Constraint) const override; 545 546 /// Examine constraint string and operand type and determine a weight value. 547 /// The operand object must already have been set up with the operand type. 548 ConstraintWeight getSingleConstraintMatchWeight( 549 AsmOperandInfo &info, const char *constraint) const override; 550 551 /// This function parses registers that appear in inline-asm constraints. 552 /// It returns pair (0, 0) on failure. 553 std::pair<unsigned, const TargetRegisterClass *> 554 parseRegForInlineAsmConstraint(StringRef C, MVT VT) const; 555 556 std::pair<unsigned, const TargetRegisterClass*> 557 getRegForInlineAsmConstraint(const std::string &Constraint, 558 MVT VT) const override; 559 560 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops 561 /// vector. If it is invalid, don't add anything to Ops. If hasMemory is 562 /// true it means one of the asm constraint of the inline asm instruction 563 /// being processed is 'm'. 564 void LowerAsmOperandForConstraint(SDValue Op, 565 std::string &Constraint, 566 std::vector<SDValue> &Ops, 567 SelectionDAG &DAG) const override; 568 569 bool isLegalAddressingMode(const AddrMode &AM, Type *Ty) const override; 570 571 bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const override; 572 573 EVT getOptimalMemOpType(uint64_t Size, unsigned DstAlign, 574 unsigned SrcAlign, 575 bool IsMemset, bool ZeroMemset, 576 bool MemcpyStrSrc, 577 MachineFunction &MF) const override; 578 579 /// isFPImmLegal - Returns true if the target can instruction select the 580 /// specified FP immediate natively. If false, the legalizer will 581 /// materialize the FP immediate as a load from a constant pool. 582 bool isFPImmLegal(const APFloat &Imm, EVT VT) const override; 583 584 unsigned getJumpTableEncoding() const override; 585 586 /// Emit a sign-extension using sll/sra, seb, or seh appropriately. 587 MachineBasicBlock *emitSignExtendToI32InReg(MachineInstr *MI, 588 MachineBasicBlock *BB, 589 unsigned Size, unsigned DstReg, 590 unsigned SrcRec) const; 591 592 MachineBasicBlock *emitAtomicBinary(MachineInstr *MI, MachineBasicBlock *BB, 593 unsigned Size, unsigned BinOpcode, bool Nand = false) const; 594 MachineBasicBlock *emitAtomicBinaryPartword(MachineInstr *MI, 595 MachineBasicBlock *BB, unsigned Size, unsigned BinOpcode, 596 bool Nand = false) const; 597 MachineBasicBlock *emitAtomicCmpSwap(MachineInstr *MI, 598 MachineBasicBlock *BB, unsigned Size) const; 599 MachineBasicBlock *emitAtomicCmpSwapPartword(MachineInstr *MI, 600 MachineBasicBlock *BB, unsigned Size) const; 601 MachineBasicBlock *emitSEL_D(MachineInstr *MI, MachineBasicBlock *BB) const; 602 }; 603 604 /// Create MipsTargetLowering objects. 605 const MipsTargetLowering * 606 createMips16TargetLowering(const MipsTargetMachine &TM, 607 const MipsSubtarget &STI); 608 const MipsTargetLowering * 609 createMipsSETargetLowering(const MipsTargetMachine &TM, 610 const MipsSubtarget &STI); 611 612 namespace Mips { 613 FastISel *createFastISel(FunctionLoweringInfo &funcInfo, 614 const TargetLibraryInfo *libInfo); 615 } 616 } 617 618 #endif 619