1 //===- MipsISelLowering.cpp - Mips DAG Lowering Implementation ------------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file defines the interfaces that Mips uses to lower LLVM code into a 11 // selection DAG. 12 // 13 //===----------------------------------------------------------------------===// 14 15 #include "MipsISelLowering.h" 16 #include "InstPrinter/MipsInstPrinter.h" 17 #include "MCTargetDesc/MipsBaseInfo.h" 18 #include "MCTargetDesc/MipsMCTargetDesc.h" 19 #include "MipsCCState.h" 20 #include "MipsInstrInfo.h" 21 #include "MipsMachineFunction.h" 22 #include "MipsRegisterInfo.h" 23 #include "MipsSubtarget.h" 24 #include "MipsTargetMachine.h" 25 #include "MipsTargetObjectFile.h" 26 #include "llvm/ADT/APFloat.h" 27 #include "llvm/ADT/ArrayRef.h" 28 #include "llvm/ADT/SmallVector.h" 29 #include "llvm/ADT/Statistic.h" 30 #include "llvm/ADT/StringRef.h" 31 #include "llvm/ADT/StringSwitch.h" 32 #include "llvm/CodeGen/CallingConvLower.h" 33 #include "llvm/CodeGen/FunctionLoweringInfo.h" 34 #include "llvm/CodeGen/ISDOpcodes.h" 35 #include "llvm/CodeGen/MachineBasicBlock.h" 36 #include "llvm/CodeGen/MachineFrameInfo.h" 37 #include "llvm/CodeGen/MachineFunction.h" 38 #include "llvm/CodeGen/MachineInstr.h" 39 #include "llvm/CodeGen/MachineInstrBuilder.h" 40 #include "llvm/CodeGen/MachineJumpTableInfo.h" 41 #include "llvm/CodeGen/MachineMemOperand.h" 42 #include "llvm/CodeGen/MachineOperand.h" 43 #include "llvm/CodeGen/MachineRegisterInfo.h" 44 #include "llvm/CodeGen/RuntimeLibcalls.h" 45 #include "llvm/CodeGen/SelectionDAG.h" 46 #include "llvm/CodeGen/SelectionDAGNodes.h" 47 #include "llvm/CodeGen/TargetFrameLowering.h" 48 #include "llvm/CodeGen/TargetInstrInfo.h" 49 #include "llvm/CodeGen/TargetRegisterInfo.h" 50 #include "llvm/CodeGen/ValueTypes.h" 51 #include "llvm/IR/CallingConv.h" 52 #include "llvm/IR/Constants.h" 53 #include "llvm/IR/DataLayout.h" 54 #include "llvm/IR/DebugLoc.h" 55 #include "llvm/IR/DerivedTypes.h" 56 #include "llvm/IR/Function.h" 57 #include "llvm/IR/GlobalValue.h" 58 #include "llvm/IR/Type.h" 59 #include "llvm/IR/Value.h" 60 #include "llvm/MC/MCRegisterInfo.h" 61 #include "llvm/Support/Casting.h" 62 #include "llvm/Support/CodeGen.h" 63 #include "llvm/Support/CommandLine.h" 64 #include "llvm/Support/Compiler.h" 65 #include "llvm/Support/ErrorHandling.h" 66 #include "llvm/Support/MachineValueType.h" 67 #include "llvm/Support/MathExtras.h" 68 #include "llvm/Target/TargetMachine.h" 69 #include "llvm/Target/TargetOptions.h" 70 #include <algorithm> 71 #include <cassert> 72 #include <cctype> 73 #include <cstdint> 74 #include <deque> 75 #include <iterator> 76 #include <utility> 77 #include <vector> 78 79 using namespace llvm; 80 81 #define DEBUG_TYPE "mips-lower" 82 83 STATISTIC(NumTailCalls, "Number of tail calls"); 84 85 static cl::opt<bool> 86 LargeGOT("mxgot", cl::Hidden, 87 cl::desc("MIPS: Enable GOT larger than 64k."), cl::init(false)); 88 89 static cl::opt<bool> 90 NoZeroDivCheck("mno-check-zero-division", cl::Hidden, 91 cl::desc("MIPS: Don't trap on integer division by zero."), 92 cl::init(false)); 93 94 static const MCPhysReg Mips64DPRegs[8] = { 95 Mips::D12_64, Mips::D13_64, Mips::D14_64, Mips::D15_64, 96 Mips::D16_64, Mips::D17_64, Mips::D18_64, Mips::D19_64 97 }; 98 99 // If I is a shifted mask, set the size (Size) and the first bit of the 100 // mask (Pos), and return true. 101 // For example, if I is 0x003ff800, (Pos, Size) = (11, 11). 102 static bool isShiftedMask(uint64_t I, uint64_t &Pos, uint64_t &Size) { 103 if (!isShiftedMask_64(I)) 104 return false; 105 106 Size = countPopulation(I); 107 Pos = countTrailingZeros(I); 108 return true; 109 } 110 111 // The MIPS MSA ABI passes vector arguments in the integer register set. 112 // The number of integer registers used is dependant on the ABI used. 113 MVT MipsTargetLowering::getRegisterTypeForCallingConv(MVT VT) const { 114 if (VT.isVector() && Subtarget.hasMSA()) 115 return Subtarget.isABI_O32() ? MVT::i32 : MVT::i64; 116 return MipsTargetLowering::getRegisterType(VT); 117 } 118 119 MVT MipsTargetLowering::getRegisterTypeForCallingConv(LLVMContext &Context, 120 EVT VT) const { 121 if (VT.isVector()) { 122 if (Subtarget.isABI_O32()) { 123 return MVT::i32; 124 } else { 125 return (VT.getSizeInBits() == 32) ? MVT::i32 : MVT::i64; 126 } 127 } 128 return MipsTargetLowering::getRegisterType(Context, VT); 129 } 130 131 unsigned MipsTargetLowering::getNumRegistersForCallingConv(LLVMContext &Context, 132 EVT VT) const { 133 if (VT.isVector()) 134 return std::max((VT.getSizeInBits() / (Subtarget.isABI_O32() ? 32 : 64)), 135 1U); 136 return MipsTargetLowering::getNumRegisters(Context, VT); 137 } 138 139 unsigned MipsTargetLowering::getVectorTypeBreakdownForCallingConv( 140 LLVMContext &Context, EVT VT, EVT &IntermediateVT, 141 unsigned &NumIntermediates, MVT &RegisterVT) const { 142 // Break down vector types to either 2 i64s or 4 i32s. 143 RegisterVT = getRegisterTypeForCallingConv(Context, VT) ; 144 IntermediateVT = RegisterVT; 145 NumIntermediates = VT.getSizeInBits() < RegisterVT.getSizeInBits() 146 ? VT.getVectorNumElements() 147 : VT.getSizeInBits() / RegisterVT.getSizeInBits(); 148 149 return NumIntermediates; 150 } 151 152 SDValue MipsTargetLowering::getGlobalReg(SelectionDAG &DAG, EVT Ty) const { 153 MipsFunctionInfo *FI = DAG.getMachineFunction().getInfo<MipsFunctionInfo>(); 154 return DAG.getRegister(FI->getGlobalBaseReg(), Ty); 155 } 156 157 SDValue MipsTargetLowering::getTargetNode(GlobalAddressSDNode *N, EVT Ty, 158 SelectionDAG &DAG, 159 unsigned Flag) const { 160 return DAG.getTargetGlobalAddress(N->getGlobal(), SDLoc(N), Ty, 0, Flag); 161 } 162 163 SDValue MipsTargetLowering::getTargetNode(ExternalSymbolSDNode *N, EVT Ty, 164 SelectionDAG &DAG, 165 unsigned Flag) const { 166 return DAG.getTargetExternalSymbol(N->getSymbol(), Ty, Flag); 167 } 168 169 SDValue MipsTargetLowering::getTargetNode(BlockAddressSDNode *N, EVT Ty, 170 SelectionDAG &DAG, 171 unsigned Flag) const { 172 return DAG.getTargetBlockAddress(N->getBlockAddress(), Ty, 0, Flag); 173 } 174 175 SDValue MipsTargetLowering::getTargetNode(JumpTableSDNode *N, EVT Ty, 176 SelectionDAG &DAG, 177 unsigned Flag) const { 178 return DAG.getTargetJumpTable(N->getIndex(), Ty, Flag); 179 } 180 181 SDValue MipsTargetLowering::getTargetNode(ConstantPoolSDNode *N, EVT Ty, 182 SelectionDAG &DAG, 183 unsigned Flag) const { 184 return DAG.getTargetConstantPool(N->getConstVal(), Ty, N->getAlignment(), 185 N->getOffset(), Flag); 186 } 187 188 const char *MipsTargetLowering::getTargetNodeName(unsigned Opcode) const { 189 switch ((MipsISD::NodeType)Opcode) { 190 case MipsISD::FIRST_NUMBER: break; 191 case MipsISD::JmpLink: return "MipsISD::JmpLink"; 192 case MipsISD::TailCall: return "MipsISD::TailCall"; 193 case MipsISD::Highest: return "MipsISD::Highest"; 194 case MipsISD::Higher: return "MipsISD::Higher"; 195 case MipsISD::Hi: return "MipsISD::Hi"; 196 case MipsISD::Lo: return "MipsISD::Lo"; 197 case MipsISD::GotHi: return "MipsISD::GotHi"; 198 case MipsISD::GPRel: return "MipsISD::GPRel"; 199 case MipsISD::ThreadPointer: return "MipsISD::ThreadPointer"; 200 case MipsISD::Ret: return "MipsISD::Ret"; 201 case MipsISD::ERet: return "MipsISD::ERet"; 202 case MipsISD::EH_RETURN: return "MipsISD::EH_RETURN"; 203 case MipsISD::FMS: return "MipsISD::FMS"; 204 case MipsISD::FPBrcond: return "MipsISD::FPBrcond"; 205 case MipsISD::FPCmp: return "MipsISD::FPCmp"; 206 case MipsISD::FSELECT: return "MipsISD::FSELECT"; 207 case MipsISD::MTC1_D64: return "MipsISD::MTC1_D64"; 208 case MipsISD::CMovFP_T: return "MipsISD::CMovFP_T"; 209 case MipsISD::CMovFP_F: return "MipsISD::CMovFP_F"; 210 case MipsISD::TruncIntFP: return "MipsISD::TruncIntFP"; 211 case MipsISD::MFHI: return "MipsISD::MFHI"; 212 case MipsISD::MFLO: return "MipsISD::MFLO"; 213 case MipsISD::MTLOHI: return "MipsISD::MTLOHI"; 214 case MipsISD::Mult: return "MipsISD::Mult"; 215 case MipsISD::Multu: return "MipsISD::Multu"; 216 case MipsISD::MAdd: return "MipsISD::MAdd"; 217 case MipsISD::MAddu: return "MipsISD::MAddu"; 218 case MipsISD::MSub: return "MipsISD::MSub"; 219 case MipsISD::MSubu: return "MipsISD::MSubu"; 220 case MipsISD::DivRem: return "MipsISD::DivRem"; 221 case MipsISD::DivRemU: return "MipsISD::DivRemU"; 222 case MipsISD::DivRem16: return "MipsISD::DivRem16"; 223 case MipsISD::DivRemU16: return "MipsISD::DivRemU16"; 224 case MipsISD::BuildPairF64: return "MipsISD::BuildPairF64"; 225 case MipsISD::ExtractElementF64: return "MipsISD::ExtractElementF64"; 226 case MipsISD::Wrapper: return "MipsISD::Wrapper"; 227 case MipsISD::DynAlloc: return "MipsISD::DynAlloc"; 228 case MipsISD::Sync: return "MipsISD::Sync"; 229 case MipsISD::Ext: return "MipsISD::Ext"; 230 case MipsISD::Ins: return "MipsISD::Ins"; 231 case MipsISD::CIns: return "MipsISD::CIns"; 232 case MipsISD::LWL: return "MipsISD::LWL"; 233 case MipsISD::LWR: return "MipsISD::LWR"; 234 case MipsISD::SWL: return "MipsISD::SWL"; 235 case MipsISD::SWR: return "MipsISD::SWR"; 236 case MipsISD::LDL: return "MipsISD::LDL"; 237 case MipsISD::LDR: return "MipsISD::LDR"; 238 case MipsISD::SDL: return "MipsISD::SDL"; 239 case MipsISD::SDR: return "MipsISD::SDR"; 240 case MipsISD::EXTP: return "MipsISD::EXTP"; 241 case MipsISD::EXTPDP: return "MipsISD::EXTPDP"; 242 case MipsISD::EXTR_S_H: return "MipsISD::EXTR_S_H"; 243 case MipsISD::EXTR_W: return "MipsISD::EXTR_W"; 244 case MipsISD::EXTR_R_W: return "MipsISD::EXTR_R_W"; 245 case MipsISD::EXTR_RS_W: return "MipsISD::EXTR_RS_W"; 246 case MipsISD::SHILO: return "MipsISD::SHILO"; 247 case MipsISD::MTHLIP: return "MipsISD::MTHLIP"; 248 case MipsISD::MULSAQ_S_W_PH: return "MipsISD::MULSAQ_S_W_PH"; 249 case MipsISD::MAQ_S_W_PHL: return "MipsISD::MAQ_S_W_PHL"; 250 case MipsISD::MAQ_S_W_PHR: return "MipsISD::MAQ_S_W_PHR"; 251 case MipsISD::MAQ_SA_W_PHL: return "MipsISD::MAQ_SA_W_PHL"; 252 case MipsISD::MAQ_SA_W_PHR: return "MipsISD::MAQ_SA_W_PHR"; 253 case MipsISD::DPAU_H_QBL: return "MipsISD::DPAU_H_QBL"; 254 case MipsISD::DPAU_H_QBR: return "MipsISD::DPAU_H_QBR"; 255 case MipsISD::DPSU_H_QBL: return "MipsISD::DPSU_H_QBL"; 256 case MipsISD::DPSU_H_QBR: return "MipsISD::DPSU_H_QBR"; 257 case MipsISD::DPAQ_S_W_PH: return "MipsISD::DPAQ_S_W_PH"; 258 case MipsISD::DPSQ_S_W_PH: return "MipsISD::DPSQ_S_W_PH"; 259 case MipsISD::DPAQ_SA_L_W: return "MipsISD::DPAQ_SA_L_W"; 260 case MipsISD::DPSQ_SA_L_W: return "MipsISD::DPSQ_SA_L_W"; 261 case MipsISD::DPA_W_PH: return "MipsISD::DPA_W_PH"; 262 case MipsISD::DPS_W_PH: return "MipsISD::DPS_W_PH"; 263 case MipsISD::DPAQX_S_W_PH: return "MipsISD::DPAQX_S_W_PH"; 264 case MipsISD::DPAQX_SA_W_PH: return "MipsISD::DPAQX_SA_W_PH"; 265 case MipsISD::DPAX_W_PH: return "MipsISD::DPAX_W_PH"; 266 case MipsISD::DPSX_W_PH: return "MipsISD::DPSX_W_PH"; 267 case MipsISD::DPSQX_S_W_PH: return "MipsISD::DPSQX_S_W_PH"; 268 case MipsISD::DPSQX_SA_W_PH: return "MipsISD::DPSQX_SA_W_PH"; 269 case MipsISD::MULSA_W_PH: return "MipsISD::MULSA_W_PH"; 270 case MipsISD::MULT: return "MipsISD::MULT"; 271 case MipsISD::MULTU: return "MipsISD::MULTU"; 272 case MipsISD::MADD_DSP: return "MipsISD::MADD_DSP"; 273 case MipsISD::MADDU_DSP: return "MipsISD::MADDU_DSP"; 274 case MipsISD::MSUB_DSP: return "MipsISD::MSUB_DSP"; 275 case MipsISD::MSUBU_DSP: return "MipsISD::MSUBU_DSP"; 276 case MipsISD::SHLL_DSP: return "MipsISD::SHLL_DSP"; 277 case MipsISD::SHRA_DSP: return "MipsISD::SHRA_DSP"; 278 case MipsISD::SHRL_DSP: return "MipsISD::SHRL_DSP"; 279 case MipsISD::SETCC_DSP: return "MipsISD::SETCC_DSP"; 280 case MipsISD::SELECT_CC_DSP: return "MipsISD::SELECT_CC_DSP"; 281 case MipsISD::VALL_ZERO: return "MipsISD::VALL_ZERO"; 282 case MipsISD::VANY_ZERO: return "MipsISD::VANY_ZERO"; 283 case MipsISD::VALL_NONZERO: return "MipsISD::VALL_NONZERO"; 284 case MipsISD::VANY_NONZERO: return "MipsISD::VANY_NONZERO"; 285 case MipsISD::VCEQ: return "MipsISD::VCEQ"; 286 case MipsISD::VCLE_S: return "MipsISD::VCLE_S"; 287 case MipsISD::VCLE_U: return "MipsISD::VCLE_U"; 288 case MipsISD::VCLT_S: return "MipsISD::VCLT_S"; 289 case MipsISD::VCLT_U: return "MipsISD::VCLT_U"; 290 case MipsISD::VEXTRACT_SEXT_ELT: return "MipsISD::VEXTRACT_SEXT_ELT"; 291 case MipsISD::VEXTRACT_ZEXT_ELT: return "MipsISD::VEXTRACT_ZEXT_ELT"; 292 case MipsISD::VNOR: return "MipsISD::VNOR"; 293 case MipsISD::VSHF: return "MipsISD::VSHF"; 294 case MipsISD::SHF: return "MipsISD::SHF"; 295 case MipsISD::ILVEV: return "MipsISD::ILVEV"; 296 case MipsISD::ILVOD: return "MipsISD::ILVOD"; 297 case MipsISD::ILVL: return "MipsISD::ILVL"; 298 case MipsISD::ILVR: return "MipsISD::ILVR"; 299 case MipsISD::PCKEV: return "MipsISD::PCKEV"; 300 case MipsISD::PCKOD: return "MipsISD::PCKOD"; 301 case MipsISD::INSVE: return "MipsISD::INSVE"; 302 } 303 return nullptr; 304 } 305 306 MipsTargetLowering::MipsTargetLowering(const MipsTargetMachine &TM, 307 const MipsSubtarget &STI) 308 : TargetLowering(TM), Subtarget(STI), ABI(TM.getABI()) { 309 // Mips does not have i1 type, so use i32 for 310 // setcc operations results (slt, sgt, ...). 311 setBooleanContents(ZeroOrOneBooleanContent); 312 setBooleanVectorContents(ZeroOrNegativeOneBooleanContent); 313 // The cmp.cond.fmt instruction in MIPS32r6/MIPS64r6 uses 0 and -1 like MSA 314 // does. Integer booleans still use 0 and 1. 315 if (Subtarget.hasMips32r6()) 316 setBooleanContents(ZeroOrOneBooleanContent, 317 ZeroOrNegativeOneBooleanContent); 318 319 // Load extented operations for i1 types must be promoted 320 for (MVT VT : MVT::integer_valuetypes()) { 321 setLoadExtAction(ISD::EXTLOAD, VT, MVT::i1, Promote); 322 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i1, Promote); 323 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i1, Promote); 324 } 325 326 // MIPS doesn't have extending float->double load/store. Set LoadExtAction 327 // for f32, f16 328 for (MVT VT : MVT::fp_valuetypes()) { 329 setLoadExtAction(ISD::EXTLOAD, VT, MVT::f32, Expand); 330 setLoadExtAction(ISD::EXTLOAD, VT, MVT::f16, Expand); 331 } 332 333 // Set LoadExtAction for f16 vectors to Expand 334 for (MVT VT : MVT::fp_vector_valuetypes()) { 335 MVT F16VT = MVT::getVectorVT(MVT::f16, VT.getVectorNumElements()); 336 if (F16VT.isValid()) 337 setLoadExtAction(ISD::EXTLOAD, VT, F16VT, Expand); 338 } 339 340 setTruncStoreAction(MVT::f32, MVT::f16, Expand); 341 setTruncStoreAction(MVT::f64, MVT::f16, Expand); 342 343 setTruncStoreAction(MVT::f64, MVT::f32, Expand); 344 345 // Used by legalize types to correctly generate the setcc result. 346 // Without this, every float setcc comes with a AND/OR with the result, 347 // we don't want this, since the fpcmp result goes to a flag register, 348 // which is used implicitly by brcond and select operations. 349 AddPromotedToType(ISD::SETCC, MVT::i1, MVT::i32); 350 351 // Mips Custom Operations 352 setOperationAction(ISD::BR_JT, MVT::Other, Expand); 353 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom); 354 setOperationAction(ISD::BlockAddress, MVT::i32, Custom); 355 setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom); 356 setOperationAction(ISD::JumpTable, MVT::i32, Custom); 357 setOperationAction(ISD::ConstantPool, MVT::i32, Custom); 358 setOperationAction(ISD::SELECT, MVT::f32, Custom); 359 setOperationAction(ISD::SELECT, MVT::f64, Custom); 360 setOperationAction(ISD::SELECT, MVT::i32, Custom); 361 setOperationAction(ISD::SETCC, MVT::f32, Custom); 362 setOperationAction(ISD::SETCC, MVT::f64, Custom); 363 setOperationAction(ISD::BRCOND, MVT::Other, Custom); 364 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom); 365 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom); 366 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom); 367 368 if (Subtarget.isGP64bit()) { 369 setOperationAction(ISD::GlobalAddress, MVT::i64, Custom); 370 setOperationAction(ISD::BlockAddress, MVT::i64, Custom); 371 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom); 372 setOperationAction(ISD::JumpTable, MVT::i64, Custom); 373 setOperationAction(ISD::ConstantPool, MVT::i64, Custom); 374 setOperationAction(ISD::SELECT, MVT::i64, Custom); 375 setOperationAction(ISD::LOAD, MVT::i64, Custom); 376 setOperationAction(ISD::STORE, MVT::i64, Custom); 377 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom); 378 setOperationAction(ISD::SHL_PARTS, MVT::i64, Custom); 379 setOperationAction(ISD::SRA_PARTS, MVT::i64, Custom); 380 setOperationAction(ISD::SRL_PARTS, MVT::i64, Custom); 381 } 382 383 if (!Subtarget.isGP64bit()) { 384 setOperationAction(ISD::SHL_PARTS, MVT::i32, Custom); 385 setOperationAction(ISD::SRA_PARTS, MVT::i32, Custom); 386 setOperationAction(ISD::SRL_PARTS, MVT::i32, Custom); 387 } 388 389 setOperationAction(ISD::EH_DWARF_CFA, MVT::i32, Custom); 390 if (Subtarget.isGP64bit()) 391 setOperationAction(ISD::EH_DWARF_CFA, MVT::i64, Custom); 392 393 setOperationAction(ISD::SDIV, MVT::i32, Expand); 394 setOperationAction(ISD::SREM, MVT::i32, Expand); 395 setOperationAction(ISD::UDIV, MVT::i32, Expand); 396 setOperationAction(ISD::UREM, MVT::i32, Expand); 397 setOperationAction(ISD::SDIV, MVT::i64, Expand); 398 setOperationAction(ISD::SREM, MVT::i64, Expand); 399 setOperationAction(ISD::UDIV, MVT::i64, Expand); 400 setOperationAction(ISD::UREM, MVT::i64, Expand); 401 402 if (!(Subtarget.hasDSP() && Subtarget.hasMips32r2())) { 403 setOperationAction(ISD::ADDC, MVT::i32, Expand); 404 setOperationAction(ISD::ADDE, MVT::i32, Expand); 405 } 406 407 setOperationAction(ISD::ADDC, MVT::i64, Expand); 408 setOperationAction(ISD::ADDE, MVT::i64, Expand); 409 setOperationAction(ISD::SUBC, MVT::i32, Expand); 410 setOperationAction(ISD::SUBE, MVT::i32, Expand); 411 setOperationAction(ISD::SUBC, MVT::i64, Expand); 412 setOperationAction(ISD::SUBE, MVT::i64, Expand); 413 414 // Operations not directly supported by Mips. 415 setOperationAction(ISD::BR_CC, MVT::f32, Expand); 416 setOperationAction(ISD::BR_CC, MVT::f64, Expand); 417 setOperationAction(ISD::BR_CC, MVT::i32, Expand); 418 setOperationAction(ISD::BR_CC, MVT::i64, Expand); 419 setOperationAction(ISD::SELECT_CC, MVT::i32, Expand); 420 setOperationAction(ISD::SELECT_CC, MVT::i64, Expand); 421 setOperationAction(ISD::SELECT_CC, MVT::f32, Expand); 422 setOperationAction(ISD::SELECT_CC, MVT::f64, Expand); 423 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand); 424 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Expand); 425 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand); 426 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Expand); 427 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand); 428 if (Subtarget.hasCnMips()) { 429 setOperationAction(ISD::CTPOP, MVT::i32, Legal); 430 setOperationAction(ISD::CTPOP, MVT::i64, Legal); 431 } else { 432 setOperationAction(ISD::CTPOP, MVT::i32, Expand); 433 setOperationAction(ISD::CTPOP, MVT::i64, Expand); 434 } 435 setOperationAction(ISD::CTTZ, MVT::i32, Expand); 436 setOperationAction(ISD::CTTZ, MVT::i64, Expand); 437 setOperationAction(ISD::ROTL, MVT::i32, Expand); 438 setOperationAction(ISD::ROTL, MVT::i64, Expand); 439 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Expand); 440 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64, Expand); 441 442 if (!Subtarget.hasMips32r2()) 443 setOperationAction(ISD::ROTR, MVT::i32, Expand); 444 445 if (!Subtarget.hasMips64r2()) 446 setOperationAction(ISD::ROTR, MVT::i64, Expand); 447 448 setOperationAction(ISD::FSIN, MVT::f32, Expand); 449 setOperationAction(ISD::FSIN, MVT::f64, Expand); 450 setOperationAction(ISD::FCOS, MVT::f32, Expand); 451 setOperationAction(ISD::FCOS, MVT::f64, Expand); 452 setOperationAction(ISD::FSINCOS, MVT::f32, Expand); 453 setOperationAction(ISD::FSINCOS, MVT::f64, Expand); 454 setOperationAction(ISD::FPOW, MVT::f32, Expand); 455 setOperationAction(ISD::FPOW, MVT::f64, Expand); 456 setOperationAction(ISD::FLOG, MVT::f32, Expand); 457 setOperationAction(ISD::FLOG2, MVT::f32, Expand); 458 setOperationAction(ISD::FLOG10, MVT::f32, Expand); 459 setOperationAction(ISD::FEXP, MVT::f32, Expand); 460 setOperationAction(ISD::FMA, MVT::f32, Expand); 461 setOperationAction(ISD::FMA, MVT::f64, Expand); 462 setOperationAction(ISD::FREM, MVT::f32, Expand); 463 setOperationAction(ISD::FREM, MVT::f64, Expand); 464 465 // Lower f16 conversion operations into library calls 466 setOperationAction(ISD::FP16_TO_FP, MVT::f32, Expand); 467 setOperationAction(ISD::FP_TO_FP16, MVT::f32, Expand); 468 setOperationAction(ISD::FP16_TO_FP, MVT::f64, Expand); 469 setOperationAction(ISD::FP_TO_FP16, MVT::f64, Expand); 470 471 setOperationAction(ISD::EH_RETURN, MVT::Other, Custom); 472 473 setOperationAction(ISD::VASTART, MVT::Other, Custom); 474 setOperationAction(ISD::VAARG, MVT::Other, Custom); 475 setOperationAction(ISD::VACOPY, MVT::Other, Expand); 476 setOperationAction(ISD::VAEND, MVT::Other, Expand); 477 478 // Use the default for now 479 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand); 480 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand); 481 482 if (!Subtarget.isGP64bit()) { 483 setOperationAction(ISD::ATOMIC_LOAD, MVT::i64, Expand); 484 setOperationAction(ISD::ATOMIC_STORE, MVT::i64, Expand); 485 } 486 487 if (!Subtarget.hasMips32r2()) { 488 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8, Expand); 489 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand); 490 } 491 492 // MIPS16 lacks MIPS32's clz and clo instructions. 493 if (!Subtarget.hasMips32() || Subtarget.inMips16Mode()) 494 setOperationAction(ISD::CTLZ, MVT::i32, Expand); 495 if (!Subtarget.hasMips64()) 496 setOperationAction(ISD::CTLZ, MVT::i64, Expand); 497 498 if (!Subtarget.hasMips32r2()) 499 setOperationAction(ISD::BSWAP, MVT::i32, Expand); 500 if (!Subtarget.hasMips64r2()) 501 setOperationAction(ISD::BSWAP, MVT::i64, Expand); 502 503 if (Subtarget.isGP64bit()) { 504 setLoadExtAction(ISD::SEXTLOAD, MVT::i64, MVT::i32, Custom); 505 setLoadExtAction(ISD::ZEXTLOAD, MVT::i64, MVT::i32, Custom); 506 setLoadExtAction(ISD::EXTLOAD, MVT::i64, MVT::i32, Custom); 507 setTruncStoreAction(MVT::i64, MVT::i32, Custom); 508 } 509 510 setOperationAction(ISD::TRAP, MVT::Other, Legal); 511 512 setTargetDAGCombine(ISD::SDIVREM); 513 setTargetDAGCombine(ISD::UDIVREM); 514 setTargetDAGCombine(ISD::SELECT); 515 setTargetDAGCombine(ISD::AND); 516 setTargetDAGCombine(ISD::OR); 517 setTargetDAGCombine(ISD::ADD); 518 setTargetDAGCombine(ISD::SUB); 519 setTargetDAGCombine(ISD::AssertZext); 520 setTargetDAGCombine(ISD::SHL); 521 522 if (ABI.IsO32()) { 523 // These libcalls are not available in 32-bit. 524 setLibcallName(RTLIB::SHL_I128, nullptr); 525 setLibcallName(RTLIB::SRL_I128, nullptr); 526 setLibcallName(RTLIB::SRA_I128, nullptr); 527 } 528 529 setMinFunctionAlignment(Subtarget.isGP64bit() ? 3 : 2); 530 531 // The arguments on the stack are defined in terms of 4-byte slots on O32 532 // and 8-byte slots on N32/N64. 533 setMinStackArgumentAlignment((ABI.IsN32() || ABI.IsN64()) ? 8 : 4); 534 535 setStackPointerRegisterToSaveRestore(ABI.IsN64() ? Mips::SP_64 : Mips::SP); 536 537 MaxStoresPerMemcpy = 16; 538 539 isMicroMips = Subtarget.inMicroMipsMode(); 540 } 541 542 const MipsTargetLowering *MipsTargetLowering::create(const MipsTargetMachine &TM, 543 const MipsSubtarget &STI) { 544 if (STI.inMips16Mode()) 545 return createMips16TargetLowering(TM, STI); 546 547 return createMipsSETargetLowering(TM, STI); 548 } 549 550 // Create a fast isel object. 551 FastISel * 552 MipsTargetLowering::createFastISel(FunctionLoweringInfo &funcInfo, 553 const TargetLibraryInfo *libInfo) const { 554 const MipsTargetMachine &TM = 555 static_cast<const MipsTargetMachine &>(funcInfo.MF->getTarget()); 556 557 // We support only the standard encoding [MIPS32,MIPS32R5] ISAs. 558 bool UseFastISel = TM.Options.EnableFastISel && Subtarget.hasMips32() && 559 !Subtarget.hasMips32r6() && !Subtarget.inMips16Mode() && 560 !Subtarget.inMicroMipsMode(); 561 562 // Disable if either of the following is true: 563 // We do not generate PIC, the ABI is not O32, LargeGOT is being used. 564 if (!TM.isPositionIndependent() || !TM.getABI().IsO32() || LargeGOT) 565 UseFastISel = false; 566 567 return UseFastISel ? Mips::createFastISel(funcInfo, libInfo) : nullptr; 568 } 569 570 EVT MipsTargetLowering::getSetCCResultType(const DataLayout &, LLVMContext &, 571 EVT VT) const { 572 if (!VT.isVector()) 573 return MVT::i32; 574 return VT.changeVectorElementTypeToInteger(); 575 } 576 577 static SDValue performDivRemCombine(SDNode *N, SelectionDAG &DAG, 578 TargetLowering::DAGCombinerInfo &DCI, 579 const MipsSubtarget &Subtarget) { 580 if (DCI.isBeforeLegalizeOps()) 581 return SDValue(); 582 583 EVT Ty = N->getValueType(0); 584 unsigned LO = (Ty == MVT::i32) ? Mips::LO0 : Mips::LO0_64; 585 unsigned HI = (Ty == MVT::i32) ? Mips::HI0 : Mips::HI0_64; 586 unsigned Opc = N->getOpcode() == ISD::SDIVREM ? MipsISD::DivRem16 : 587 MipsISD::DivRemU16; 588 SDLoc DL(N); 589 590 SDValue DivRem = DAG.getNode(Opc, DL, MVT::Glue, 591 N->getOperand(0), N->getOperand(1)); 592 SDValue InChain = DAG.getEntryNode(); 593 SDValue InGlue = DivRem; 594 595 // insert MFLO 596 if (N->hasAnyUseOfValue(0)) { 597 SDValue CopyFromLo = DAG.getCopyFromReg(InChain, DL, LO, Ty, 598 InGlue); 599 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), CopyFromLo); 600 InChain = CopyFromLo.getValue(1); 601 InGlue = CopyFromLo.getValue(2); 602 } 603 604 // insert MFHI 605 if (N->hasAnyUseOfValue(1)) { 606 SDValue CopyFromHi = DAG.getCopyFromReg(InChain, DL, 607 HI, Ty, InGlue); 608 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), CopyFromHi); 609 } 610 611 return SDValue(); 612 } 613 614 static Mips::CondCode condCodeToFCC(ISD::CondCode CC) { 615 switch (CC) { 616 default: llvm_unreachable("Unknown fp condition code!"); 617 case ISD::SETEQ: 618 case ISD::SETOEQ: return Mips::FCOND_OEQ; 619 case ISD::SETUNE: return Mips::FCOND_UNE; 620 case ISD::SETLT: 621 case ISD::SETOLT: return Mips::FCOND_OLT; 622 case ISD::SETGT: 623 case ISD::SETOGT: return Mips::FCOND_OGT; 624 case ISD::SETLE: 625 case ISD::SETOLE: return Mips::FCOND_OLE; 626 case ISD::SETGE: 627 case ISD::SETOGE: return Mips::FCOND_OGE; 628 case ISD::SETULT: return Mips::FCOND_ULT; 629 case ISD::SETULE: return Mips::FCOND_ULE; 630 case ISD::SETUGT: return Mips::FCOND_UGT; 631 case ISD::SETUGE: return Mips::FCOND_UGE; 632 case ISD::SETUO: return Mips::FCOND_UN; 633 case ISD::SETO: return Mips::FCOND_OR; 634 case ISD::SETNE: 635 case ISD::SETONE: return Mips::FCOND_ONE; 636 case ISD::SETUEQ: return Mips::FCOND_UEQ; 637 } 638 } 639 640 /// This function returns true if the floating point conditional branches and 641 /// conditional moves which use condition code CC should be inverted. 642 static bool invertFPCondCodeUser(Mips::CondCode CC) { 643 if (CC >= Mips::FCOND_F && CC <= Mips::FCOND_NGT) 644 return false; 645 646 assert((CC >= Mips::FCOND_T && CC <= Mips::FCOND_GT) && 647 "Illegal Condition Code"); 648 649 return true; 650 } 651 652 // Creates and returns an FPCmp node from a setcc node. 653 // Returns Op if setcc is not a floating point comparison. 654 static SDValue createFPCmp(SelectionDAG &DAG, const SDValue &Op) { 655 // must be a SETCC node 656 if (Op.getOpcode() != ISD::SETCC) 657 return Op; 658 659 SDValue LHS = Op.getOperand(0); 660 661 if (!LHS.getValueType().isFloatingPoint()) 662 return Op; 663 664 SDValue RHS = Op.getOperand(1); 665 SDLoc DL(Op); 666 667 // Assume the 3rd operand is a CondCodeSDNode. Add code to check the type of 668 // node if necessary. 669 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get(); 670 671 return DAG.getNode(MipsISD::FPCmp, DL, MVT::Glue, LHS, RHS, 672 DAG.getConstant(condCodeToFCC(CC), DL, MVT::i32)); 673 } 674 675 // Creates and returns a CMovFPT/F node. 676 static SDValue createCMovFP(SelectionDAG &DAG, SDValue Cond, SDValue True, 677 SDValue False, const SDLoc &DL) { 678 ConstantSDNode *CC = cast<ConstantSDNode>(Cond.getOperand(2)); 679 bool invert = invertFPCondCodeUser((Mips::CondCode)CC->getSExtValue()); 680 SDValue FCC0 = DAG.getRegister(Mips::FCC0, MVT::i32); 681 682 return DAG.getNode((invert ? MipsISD::CMovFP_F : MipsISD::CMovFP_T), DL, 683 True.getValueType(), True, FCC0, False, Cond); 684 } 685 686 static SDValue performSELECTCombine(SDNode *N, SelectionDAG &DAG, 687 TargetLowering::DAGCombinerInfo &DCI, 688 const MipsSubtarget &Subtarget) { 689 if (DCI.isBeforeLegalizeOps()) 690 return SDValue(); 691 692 SDValue SetCC = N->getOperand(0); 693 694 if ((SetCC.getOpcode() != ISD::SETCC) || 695 !SetCC.getOperand(0).getValueType().isInteger()) 696 return SDValue(); 697 698 SDValue False = N->getOperand(2); 699 EVT FalseTy = False.getValueType(); 700 701 if (!FalseTy.isInteger()) 702 return SDValue(); 703 704 ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(False); 705 706 // If the RHS (False) is 0, we swap the order of the operands 707 // of ISD::SELECT (obviously also inverting the condition) so that we can 708 // take advantage of conditional moves using the $0 register. 709 // Example: 710 // return (a != 0) ? x : 0; 711 // load $reg, x 712 // movz $reg, $0, a 713 if (!FalseC) 714 return SDValue(); 715 716 const SDLoc DL(N); 717 718 if (!FalseC->getZExtValue()) { 719 ISD::CondCode CC = cast<CondCodeSDNode>(SetCC.getOperand(2))->get(); 720 SDValue True = N->getOperand(1); 721 722 SetCC = DAG.getSetCC(DL, SetCC.getValueType(), SetCC.getOperand(0), 723 SetCC.getOperand(1), ISD::getSetCCInverse(CC, true)); 724 725 return DAG.getNode(ISD::SELECT, DL, FalseTy, SetCC, False, True); 726 } 727 728 // If both operands are integer constants there's a possibility that we 729 // can do some interesting optimizations. 730 SDValue True = N->getOperand(1); 731 ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(True); 732 733 if (!TrueC || !True.getValueType().isInteger()) 734 return SDValue(); 735 736 // We'll also ignore MVT::i64 operands as this optimizations proves 737 // to be ineffective because of the required sign extensions as the result 738 // of a SETCC operator is always MVT::i32 for non-vector types. 739 if (True.getValueType() == MVT::i64) 740 return SDValue(); 741 742 int64_t Diff = TrueC->getSExtValue() - FalseC->getSExtValue(); 743 744 // 1) (a < x) ? y : y-1 745 // slti $reg1, a, x 746 // addiu $reg2, $reg1, y-1 747 if (Diff == 1) 748 return DAG.getNode(ISD::ADD, DL, SetCC.getValueType(), SetCC, False); 749 750 // 2) (a < x) ? y-1 : y 751 // slti $reg1, a, x 752 // xor $reg1, $reg1, 1 753 // addiu $reg2, $reg1, y-1 754 if (Diff == -1) { 755 ISD::CondCode CC = cast<CondCodeSDNode>(SetCC.getOperand(2))->get(); 756 SetCC = DAG.getSetCC(DL, SetCC.getValueType(), SetCC.getOperand(0), 757 SetCC.getOperand(1), ISD::getSetCCInverse(CC, true)); 758 return DAG.getNode(ISD::ADD, DL, SetCC.getValueType(), SetCC, True); 759 } 760 761 // Couldn't optimize. 762 return SDValue(); 763 } 764 765 static SDValue performCMovFPCombine(SDNode *N, SelectionDAG &DAG, 766 TargetLowering::DAGCombinerInfo &DCI, 767 const MipsSubtarget &Subtarget) { 768 if (DCI.isBeforeLegalizeOps()) 769 return SDValue(); 770 771 SDValue ValueIfTrue = N->getOperand(0), ValueIfFalse = N->getOperand(2); 772 773 ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(ValueIfFalse); 774 if (!FalseC || FalseC->getZExtValue()) 775 return SDValue(); 776 777 // Since RHS (False) is 0, we swap the order of the True/False operands 778 // (obviously also inverting the condition) so that we can 779 // take advantage of conditional moves using the $0 register. 780 // Example: 781 // return (a != 0) ? x : 0; 782 // load $reg, x 783 // movz $reg, $0, a 784 unsigned Opc = (N->getOpcode() == MipsISD::CMovFP_T) ? MipsISD::CMovFP_F : 785 MipsISD::CMovFP_T; 786 787 SDValue FCC = N->getOperand(1), Glue = N->getOperand(3); 788 return DAG.getNode(Opc, SDLoc(N), ValueIfFalse.getValueType(), 789 ValueIfFalse, FCC, ValueIfTrue, Glue); 790 } 791 792 static SDValue performANDCombine(SDNode *N, SelectionDAG &DAG, 793 TargetLowering::DAGCombinerInfo &DCI, 794 const MipsSubtarget &Subtarget) { 795 if (DCI.isBeforeLegalizeOps() || !Subtarget.hasExtractInsert()) 796 return SDValue(); 797 798 SDValue FirstOperand = N->getOperand(0); 799 unsigned FirstOperandOpc = FirstOperand.getOpcode(); 800 SDValue Mask = N->getOperand(1); 801 EVT ValTy = N->getValueType(0); 802 SDLoc DL(N); 803 804 uint64_t Pos = 0, SMPos, SMSize; 805 ConstantSDNode *CN; 806 SDValue NewOperand; 807 unsigned Opc; 808 809 // Op's second operand must be a shifted mask. 810 if (!(CN = dyn_cast<ConstantSDNode>(Mask)) || 811 !isShiftedMask(CN->getZExtValue(), SMPos, SMSize)) 812 return SDValue(); 813 814 if (FirstOperandOpc == ISD::SRA || FirstOperandOpc == ISD::SRL) { 815 // Pattern match EXT. 816 // $dst = and ((sra or srl) $src , pos), (2**size - 1) 817 // => ext $dst, $src, pos, size 818 819 // The second operand of the shift must be an immediate. 820 if (!(CN = dyn_cast<ConstantSDNode>(FirstOperand.getOperand(1)))) 821 return SDValue(); 822 823 Pos = CN->getZExtValue(); 824 825 // Return if the shifted mask does not start at bit 0 or the sum of its size 826 // and Pos exceeds the word's size. 827 if (SMPos != 0 || Pos + SMSize > ValTy.getSizeInBits()) 828 return SDValue(); 829 830 Opc = MipsISD::Ext; 831 NewOperand = FirstOperand.getOperand(0); 832 } else if (FirstOperandOpc == ISD::SHL && Subtarget.hasCnMips()) { 833 // Pattern match CINS. 834 // $dst = and (shl $src , pos), mask 835 // => cins $dst, $src, pos, size 836 // mask is a shifted mask with consecutive 1's, pos = shift amount, 837 // size = population count. 838 839 // The second operand of the shift must be an immediate. 840 if (!(CN = dyn_cast<ConstantSDNode>(FirstOperand.getOperand(1)))) 841 return SDValue(); 842 843 Pos = CN->getZExtValue(); 844 845 if (SMPos != Pos || Pos >= ValTy.getSizeInBits() || SMSize >= 32 || 846 Pos + SMSize > ValTy.getSizeInBits()) 847 return SDValue(); 848 849 NewOperand = FirstOperand.getOperand(0); 850 // SMSize is 'location' (position) in this case, not size. 851 SMSize--; 852 Opc = MipsISD::CIns; 853 } else { 854 // Pattern match EXT. 855 // $dst = and $src, (2**size - 1) , if size > 16 856 // => ext $dst, $src, pos, size , pos = 0 857 858 // If the mask is <= 0xffff, andi can be used instead. 859 if (CN->getZExtValue() <= 0xffff) 860 return SDValue(); 861 862 // Return if the mask doesn't start at position 0. 863 if (SMPos) 864 return SDValue(); 865 866 Opc = MipsISD::Ext; 867 NewOperand = FirstOperand; 868 } 869 return DAG.getNode(Opc, DL, ValTy, NewOperand, 870 DAG.getConstant(Pos, DL, MVT::i32), 871 DAG.getConstant(SMSize, DL, MVT::i32)); 872 } 873 874 static SDValue performORCombine(SDNode *N, SelectionDAG &DAG, 875 TargetLowering::DAGCombinerInfo &DCI, 876 const MipsSubtarget &Subtarget) { 877 // Pattern match INS. 878 // $dst = or (and $src1 , mask0), (and (shl $src, pos), mask1), 879 // where mask1 = (2**size - 1) << pos, mask0 = ~mask1 880 // => ins $dst, $src, size, pos, $src1 881 if (DCI.isBeforeLegalizeOps() || !Subtarget.hasExtractInsert()) 882 return SDValue(); 883 884 SDValue And0 = N->getOperand(0), And1 = N->getOperand(1); 885 uint64_t SMPos0, SMSize0, SMPos1, SMSize1; 886 ConstantSDNode *CN, *CN1; 887 888 // See if Op's first operand matches (and $src1 , mask0). 889 if (And0.getOpcode() != ISD::AND) 890 return SDValue(); 891 892 if (!(CN = dyn_cast<ConstantSDNode>(And0.getOperand(1))) || 893 !isShiftedMask(~CN->getSExtValue(), SMPos0, SMSize0)) 894 return SDValue(); 895 896 // See if Op's second operand matches (and (shl $src, pos), mask1). 897 if (And1.getOpcode() == ISD::AND && 898 And1.getOperand(0).getOpcode() == ISD::SHL) { 899 900 if (!(CN = dyn_cast<ConstantSDNode>(And1.getOperand(1))) || 901 !isShiftedMask(CN->getZExtValue(), SMPos1, SMSize1)) 902 return SDValue(); 903 904 // The shift masks must have the same position and size. 905 if (SMPos0 != SMPos1 || SMSize0 != SMSize1) 906 return SDValue(); 907 908 SDValue Shl = And1.getOperand(0); 909 910 if (!(CN = dyn_cast<ConstantSDNode>(Shl.getOperand(1)))) 911 return SDValue(); 912 913 unsigned Shamt = CN->getZExtValue(); 914 915 // Return if the shift amount and the first bit position of mask are not the 916 // same. 917 EVT ValTy = N->getValueType(0); 918 if ((Shamt != SMPos0) || (SMPos0 + SMSize0 > ValTy.getSizeInBits())) 919 return SDValue(); 920 921 SDLoc DL(N); 922 return DAG.getNode(MipsISD::Ins, DL, ValTy, Shl.getOperand(0), 923 DAG.getConstant(SMPos0, DL, MVT::i32), 924 DAG.getConstant(SMSize0, DL, MVT::i32), 925 And0.getOperand(0)); 926 } else { 927 // Pattern match DINS. 928 // $dst = or (and $src, mask0), mask1 929 // where mask0 = ((1 << SMSize0) -1) << SMPos0 930 // => dins $dst, $src, pos, size 931 if (~CN->getSExtValue() == ((((int64_t)1 << SMSize0) - 1) << SMPos0) && 932 ((SMSize0 + SMPos0 <= 64 && Subtarget.hasMips64r2()) || 933 (SMSize0 + SMPos0 <= 32))) { 934 // Check if AND instruction has constant as argument 935 bool isConstCase = And1.getOpcode() != ISD::AND; 936 if (And1.getOpcode() == ISD::AND) { 937 if (!(CN1 = dyn_cast<ConstantSDNode>(And1->getOperand(1)))) 938 return SDValue(); 939 } else { 940 if (!(CN1 = dyn_cast<ConstantSDNode>(N->getOperand(1)))) 941 return SDValue(); 942 } 943 // Don't generate INS if constant OR operand doesn't fit into bits 944 // cleared by constant AND operand. 945 if (CN->getSExtValue() & CN1->getSExtValue()) 946 return SDValue(); 947 948 SDLoc DL(N); 949 EVT ValTy = N->getOperand(0)->getValueType(0); 950 SDValue Const1; 951 SDValue SrlX; 952 if (!isConstCase) { 953 Const1 = DAG.getConstant(SMPos0, DL, MVT::i32); 954 SrlX = DAG.getNode(ISD::SRL, DL, And1->getValueType(0), And1, Const1); 955 } 956 return DAG.getNode( 957 MipsISD::Ins, DL, N->getValueType(0), 958 isConstCase 959 ? DAG.getConstant(CN1->getSExtValue() >> SMPos0, DL, ValTy) 960 : SrlX, 961 DAG.getConstant(SMPos0, DL, MVT::i32), 962 DAG.getConstant(ValTy.getSizeInBits() / 8 < 8 ? SMSize0 & 31 963 : SMSize0, 964 DL, MVT::i32), 965 And0->getOperand(0)); 966 967 } 968 return SDValue(); 969 } 970 } 971 972 static SDValue performMADD_MSUBCombine(SDNode *ROOTNode, SelectionDAG &CurDAG, 973 const MipsSubtarget &Subtarget) { 974 // ROOTNode must have a multiplication as an operand for the match to be 975 // successful. 976 if (ROOTNode->getOperand(0).getOpcode() != ISD::MUL && 977 ROOTNode->getOperand(1).getOpcode() != ISD::MUL) 978 return SDValue(); 979 980 // We don't handle vector types here. 981 if (ROOTNode->getValueType(0).isVector()) 982 return SDValue(); 983 984 // For MIPS64, madd / msub instructions are inefficent to use with 64 bit 985 // arithmetic. E.g. 986 // (add (mul a b) c) => 987 // let res = (madd (mthi (drotr c 32))x(mtlo c) a b) in 988 // MIPS64: (or (dsll (mfhi res) 32) (dsrl (dsll (mflo res) 32) 32) 989 // or 990 // MIPS64R2: (dins (mflo res) (mfhi res) 32 32) 991 // 992 // The overhead of setting up the Hi/Lo registers and reassembling the 993 // result makes this a dubious optimzation for MIPS64. The core of the 994 // problem is that Hi/Lo contain the upper and lower 32 bits of the 995 // operand and result. 996 // 997 // It requires a chain of 4 add/mul for MIPS64R2 to get better code 998 // density than doing it naively, 5 for MIPS64. Additionally, using 999 // madd/msub on MIPS64 requires the operands actually be 32 bit sign 1000 // extended operands, not true 64 bit values. 1001 // 1002 // FIXME: For the moment, disable this completely for MIPS64. 1003 if (Subtarget.hasMips64()) 1004 return SDValue(); 1005 1006 SDValue Mult = ROOTNode->getOperand(0).getOpcode() == ISD::MUL 1007 ? ROOTNode->getOperand(0) 1008 : ROOTNode->getOperand(1); 1009 1010 SDValue AddOperand = ROOTNode->getOperand(0).getOpcode() == ISD::MUL 1011 ? ROOTNode->getOperand(1) 1012 : ROOTNode->getOperand(0); 1013 1014 // Transform this to a MADD only if the user of this node is the add. 1015 // If there are other users of the mul, this function returns here. 1016 if (!Mult.hasOneUse()) 1017 return SDValue(); 1018 1019 // maddu and madd are unusual instructions in that on MIPS64 bits 63..31 1020 // must be in canonical form, i.e. sign extended. For MIPS32, the operands 1021 // of the multiply must have 32 or more sign bits, otherwise we cannot 1022 // perform this optimization. We have to check this here as we're performing 1023 // this optimization pre-legalization. 1024 SDValue MultLHS = Mult->getOperand(0); 1025 SDValue MultRHS = Mult->getOperand(1); 1026 1027 bool IsSigned = MultLHS->getOpcode() == ISD::SIGN_EXTEND && 1028 MultRHS->getOpcode() == ISD::SIGN_EXTEND; 1029 bool IsUnsigned = MultLHS->getOpcode() == ISD::ZERO_EXTEND && 1030 MultRHS->getOpcode() == ISD::ZERO_EXTEND; 1031 1032 if (!IsSigned && !IsUnsigned) 1033 return SDValue(); 1034 1035 // Initialize accumulator. 1036 SDLoc DL(ROOTNode); 1037 SDValue TopHalf; 1038 SDValue BottomHalf; 1039 BottomHalf = CurDAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32, AddOperand, 1040 CurDAG.getIntPtrConstant(0, DL)); 1041 1042 TopHalf = CurDAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32, AddOperand, 1043 CurDAG.getIntPtrConstant(1, DL)); 1044 SDValue ACCIn = CurDAG.getNode(MipsISD::MTLOHI, DL, MVT::Untyped, 1045 BottomHalf, 1046 TopHalf); 1047 1048 // Create MipsMAdd(u) / MipsMSub(u) node. 1049 bool IsAdd = ROOTNode->getOpcode() == ISD::ADD; 1050 unsigned Opcode = IsAdd ? (IsUnsigned ? MipsISD::MAddu : MipsISD::MAdd) 1051 : (IsUnsigned ? MipsISD::MSubu : MipsISD::MSub); 1052 SDValue MAddOps[3] = { 1053 CurDAG.getNode(ISD::TRUNCATE, DL, MVT::i32, Mult->getOperand(0)), 1054 CurDAG.getNode(ISD::TRUNCATE, DL, MVT::i32, Mult->getOperand(1)), ACCIn}; 1055 EVT VTs[2] = {MVT::i32, MVT::i32}; 1056 SDValue MAdd = CurDAG.getNode(Opcode, DL, VTs, MAddOps); 1057 1058 SDValue ResLo = CurDAG.getNode(MipsISD::MFLO, DL, MVT::i32, MAdd); 1059 SDValue ResHi = CurDAG.getNode(MipsISD::MFHI, DL, MVT::i32, MAdd); 1060 SDValue Combined = 1061 CurDAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, ResLo, ResHi); 1062 return Combined; 1063 } 1064 1065 static SDValue performSUBCombine(SDNode *N, SelectionDAG &DAG, 1066 TargetLowering::DAGCombinerInfo &DCI, 1067 const MipsSubtarget &Subtarget) { 1068 // (sub v0 (mul v1, v2)) => (msub v1, v2, v0) 1069 if (DCI.isBeforeLegalizeOps()) { 1070 if (Subtarget.hasMips32() && !Subtarget.hasMips32r6() && 1071 !Subtarget.inMips16Mode() && N->getValueType(0) == MVT::i64) 1072 return performMADD_MSUBCombine(N, DAG, Subtarget); 1073 1074 return SDValue(); 1075 } 1076 1077 return SDValue(); 1078 } 1079 1080 static SDValue performADDCombine(SDNode *N, SelectionDAG &DAG, 1081 TargetLowering::DAGCombinerInfo &DCI, 1082 const MipsSubtarget &Subtarget) { 1083 // (add v0 (mul v1, v2)) => (madd v1, v2, v0) 1084 if (DCI.isBeforeLegalizeOps()) { 1085 if (Subtarget.hasMips32() && !Subtarget.hasMips32r6() && 1086 !Subtarget.inMips16Mode() && N->getValueType(0) == MVT::i64) 1087 return performMADD_MSUBCombine(N, DAG, Subtarget); 1088 1089 return SDValue(); 1090 } 1091 1092 // (add v0, (add v1, abs_lo(tjt))) => (add (add v0, v1), abs_lo(tjt)) 1093 SDValue Add = N->getOperand(1); 1094 1095 if (Add.getOpcode() != ISD::ADD) 1096 return SDValue(); 1097 1098 SDValue Lo = Add.getOperand(1); 1099 1100 if ((Lo.getOpcode() != MipsISD::Lo) || 1101 (Lo.getOperand(0).getOpcode() != ISD::TargetJumpTable)) 1102 return SDValue(); 1103 1104 EVT ValTy = N->getValueType(0); 1105 SDLoc DL(N); 1106 1107 SDValue Add1 = DAG.getNode(ISD::ADD, DL, ValTy, N->getOperand(0), 1108 Add.getOperand(0)); 1109 return DAG.getNode(ISD::ADD, DL, ValTy, Add1, Lo); 1110 } 1111 1112 static SDValue performSHLCombine(SDNode *N, SelectionDAG &DAG, 1113 TargetLowering::DAGCombinerInfo &DCI, 1114 const MipsSubtarget &Subtarget) { 1115 // Pattern match CINS. 1116 // $dst = shl (and $src , imm), pos 1117 // => cins $dst, $src, pos, size 1118 1119 if (DCI.isBeforeLegalizeOps() || !Subtarget.hasCnMips()) 1120 return SDValue(); 1121 1122 SDValue FirstOperand = N->getOperand(0); 1123 unsigned FirstOperandOpc = FirstOperand.getOpcode(); 1124 SDValue SecondOperand = N->getOperand(1); 1125 EVT ValTy = N->getValueType(0); 1126 SDLoc DL(N); 1127 1128 uint64_t Pos = 0, SMPos, SMSize; 1129 ConstantSDNode *CN; 1130 SDValue NewOperand; 1131 1132 // The second operand of the shift must be an immediate. 1133 if (!(CN = dyn_cast<ConstantSDNode>(SecondOperand))) 1134 return SDValue(); 1135 1136 Pos = CN->getZExtValue(); 1137 1138 if (Pos >= ValTy.getSizeInBits()) 1139 return SDValue(); 1140 1141 if (FirstOperandOpc != ISD::AND) 1142 return SDValue(); 1143 1144 // AND's second operand must be a shifted mask. 1145 if (!(CN = dyn_cast<ConstantSDNode>(FirstOperand.getOperand(1))) || 1146 !isShiftedMask(CN->getZExtValue(), SMPos, SMSize)) 1147 return SDValue(); 1148 1149 // Return if the shifted mask does not start at bit 0 or the sum of its size 1150 // and Pos exceeds the word's size. 1151 if (SMPos != 0 || SMSize > 32 || Pos + SMSize > ValTy.getSizeInBits()) 1152 return SDValue(); 1153 1154 NewOperand = FirstOperand.getOperand(0); 1155 // SMSize is 'location' (position) in this case, not size. 1156 SMSize--; 1157 1158 return DAG.getNode(MipsISD::CIns, DL, ValTy, NewOperand, 1159 DAG.getConstant(Pos, DL, MVT::i32), 1160 DAG.getConstant(SMSize, DL, MVT::i32)); 1161 } 1162 1163 SDValue MipsTargetLowering::PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) 1164 const { 1165 SelectionDAG &DAG = DCI.DAG; 1166 unsigned Opc = N->getOpcode(); 1167 1168 switch (Opc) { 1169 default: break; 1170 case ISD::SDIVREM: 1171 case ISD::UDIVREM: 1172 return performDivRemCombine(N, DAG, DCI, Subtarget); 1173 case ISD::SELECT: 1174 return performSELECTCombine(N, DAG, DCI, Subtarget); 1175 case MipsISD::CMovFP_F: 1176 case MipsISD::CMovFP_T: 1177 return performCMovFPCombine(N, DAG, DCI, Subtarget); 1178 case ISD::AND: 1179 return performANDCombine(N, DAG, DCI, Subtarget); 1180 case ISD::OR: 1181 return performORCombine(N, DAG, DCI, Subtarget); 1182 case ISD::ADD: 1183 return performADDCombine(N, DAG, DCI, Subtarget); 1184 case ISD::SHL: 1185 return performSHLCombine(N, DAG, DCI, Subtarget); 1186 case ISD::SUB: 1187 return performSUBCombine(N, DAG, DCI, Subtarget); 1188 } 1189 1190 return SDValue(); 1191 } 1192 1193 bool MipsTargetLowering::isCheapToSpeculateCttz() const { 1194 return Subtarget.hasMips32(); 1195 } 1196 1197 bool MipsTargetLowering::isCheapToSpeculateCtlz() const { 1198 return Subtarget.hasMips32(); 1199 } 1200 1201 void 1202 MipsTargetLowering::LowerOperationWrapper(SDNode *N, 1203 SmallVectorImpl<SDValue> &Results, 1204 SelectionDAG &DAG) const { 1205 SDValue Res = LowerOperation(SDValue(N, 0), DAG); 1206 1207 for (unsigned I = 0, E = Res->getNumValues(); I != E; ++I) 1208 Results.push_back(Res.getValue(I)); 1209 } 1210 1211 void 1212 MipsTargetLowering::ReplaceNodeResults(SDNode *N, 1213 SmallVectorImpl<SDValue> &Results, 1214 SelectionDAG &DAG) const { 1215 return LowerOperationWrapper(N, Results, DAG); 1216 } 1217 1218 SDValue MipsTargetLowering:: 1219 LowerOperation(SDValue Op, SelectionDAG &DAG) const 1220 { 1221 switch (Op.getOpcode()) 1222 { 1223 case ISD::BRCOND: return lowerBRCOND(Op, DAG); 1224 case ISD::ConstantPool: return lowerConstantPool(Op, DAG); 1225 case ISD::GlobalAddress: return lowerGlobalAddress(Op, DAG); 1226 case ISD::BlockAddress: return lowerBlockAddress(Op, DAG); 1227 case ISD::GlobalTLSAddress: return lowerGlobalTLSAddress(Op, DAG); 1228 case ISD::JumpTable: return lowerJumpTable(Op, DAG); 1229 case ISD::SELECT: return lowerSELECT(Op, DAG); 1230 case ISD::SETCC: return lowerSETCC(Op, DAG); 1231 case ISD::VASTART: return lowerVASTART(Op, DAG); 1232 case ISD::VAARG: return lowerVAARG(Op, DAG); 1233 case ISD::FCOPYSIGN: return lowerFCOPYSIGN(Op, DAG); 1234 case ISD::FRAMEADDR: return lowerFRAMEADDR(Op, DAG); 1235 case ISD::RETURNADDR: return lowerRETURNADDR(Op, DAG); 1236 case ISD::EH_RETURN: return lowerEH_RETURN(Op, DAG); 1237 case ISD::ATOMIC_FENCE: return lowerATOMIC_FENCE(Op, DAG); 1238 case ISD::SHL_PARTS: return lowerShiftLeftParts(Op, DAG); 1239 case ISD::SRA_PARTS: return lowerShiftRightParts(Op, DAG, true); 1240 case ISD::SRL_PARTS: return lowerShiftRightParts(Op, DAG, false); 1241 case ISD::LOAD: return lowerLOAD(Op, DAG); 1242 case ISD::STORE: return lowerSTORE(Op, DAG); 1243 case ISD::EH_DWARF_CFA: return lowerEH_DWARF_CFA(Op, DAG); 1244 case ISD::FP_TO_SINT: return lowerFP_TO_SINT(Op, DAG); 1245 } 1246 return SDValue(); 1247 } 1248 1249 //===----------------------------------------------------------------------===// 1250 // Lower helper functions 1251 //===----------------------------------------------------------------------===// 1252 1253 // addLiveIn - This helper function adds the specified physical register to the 1254 // MachineFunction as a live in value. It also creates a corresponding 1255 // virtual register for it. 1256 static unsigned 1257 addLiveIn(MachineFunction &MF, unsigned PReg, const TargetRegisterClass *RC) 1258 { 1259 unsigned VReg = MF.getRegInfo().createVirtualRegister(RC); 1260 MF.getRegInfo().addLiveIn(PReg, VReg); 1261 return VReg; 1262 } 1263 1264 static MachineBasicBlock *insertDivByZeroTrap(MachineInstr &MI, 1265 MachineBasicBlock &MBB, 1266 const TargetInstrInfo &TII, 1267 bool Is64Bit, bool IsMicroMips) { 1268 if (NoZeroDivCheck) 1269 return &MBB; 1270 1271 // Insert instruction "teq $divisor_reg, $zero, 7". 1272 MachineBasicBlock::iterator I(MI); 1273 MachineInstrBuilder MIB; 1274 MachineOperand &Divisor = MI.getOperand(2); 1275 MIB = BuildMI(MBB, std::next(I), MI.getDebugLoc(), 1276 TII.get(IsMicroMips ? Mips::TEQ_MM : Mips::TEQ)) 1277 .addReg(Divisor.getReg(), getKillRegState(Divisor.isKill())) 1278 .addReg(Mips::ZERO) 1279 .addImm(7); 1280 1281 // Use the 32-bit sub-register if this is a 64-bit division. 1282 if (Is64Bit) 1283 MIB->getOperand(0).setSubReg(Mips::sub_32); 1284 1285 // Clear Divisor's kill flag. 1286 Divisor.setIsKill(false); 1287 1288 // We would normally delete the original instruction here but in this case 1289 // we only needed to inject an additional instruction rather than replace it. 1290 1291 return &MBB; 1292 } 1293 1294 MachineBasicBlock * 1295 MipsTargetLowering::EmitInstrWithCustomInserter(MachineInstr &MI, 1296 MachineBasicBlock *BB) const { 1297 switch (MI.getOpcode()) { 1298 default: 1299 llvm_unreachable("Unexpected instr type to insert"); 1300 case Mips::ATOMIC_LOAD_ADD_I8: 1301 return emitAtomicBinaryPartword(MI, BB, 1, Mips::ADDu); 1302 case Mips::ATOMIC_LOAD_ADD_I16: 1303 return emitAtomicBinaryPartword(MI, BB, 2, Mips::ADDu); 1304 case Mips::ATOMIC_LOAD_ADD_I32: 1305 return emitAtomicBinary(MI, BB, 4, Mips::ADDu); 1306 case Mips::ATOMIC_LOAD_ADD_I64: 1307 return emitAtomicBinary(MI, BB, 8, Mips::DADDu); 1308 1309 case Mips::ATOMIC_LOAD_AND_I8: 1310 return emitAtomicBinaryPartword(MI, BB, 1, Mips::AND); 1311 case Mips::ATOMIC_LOAD_AND_I16: 1312 return emitAtomicBinaryPartword(MI, BB, 2, Mips::AND); 1313 case Mips::ATOMIC_LOAD_AND_I32: 1314 return emitAtomicBinary(MI, BB, 4, Mips::AND); 1315 case Mips::ATOMIC_LOAD_AND_I64: 1316 return emitAtomicBinary(MI, BB, 8, Mips::AND64); 1317 1318 case Mips::ATOMIC_LOAD_OR_I8: 1319 return emitAtomicBinaryPartword(MI, BB, 1, Mips::OR); 1320 case Mips::ATOMIC_LOAD_OR_I16: 1321 return emitAtomicBinaryPartword(MI, BB, 2, Mips::OR); 1322 case Mips::ATOMIC_LOAD_OR_I32: 1323 return emitAtomicBinary(MI, BB, 4, Mips::OR); 1324 case Mips::ATOMIC_LOAD_OR_I64: 1325 return emitAtomicBinary(MI, BB, 8, Mips::OR64); 1326 1327 case Mips::ATOMIC_LOAD_XOR_I8: 1328 return emitAtomicBinaryPartword(MI, BB, 1, Mips::XOR); 1329 case Mips::ATOMIC_LOAD_XOR_I16: 1330 return emitAtomicBinaryPartword(MI, BB, 2, Mips::XOR); 1331 case Mips::ATOMIC_LOAD_XOR_I32: 1332 return emitAtomicBinary(MI, BB, 4, Mips::XOR); 1333 case Mips::ATOMIC_LOAD_XOR_I64: 1334 return emitAtomicBinary(MI, BB, 8, Mips::XOR64); 1335 1336 case Mips::ATOMIC_LOAD_NAND_I8: 1337 return emitAtomicBinaryPartword(MI, BB, 1, 0, true); 1338 case Mips::ATOMIC_LOAD_NAND_I16: 1339 return emitAtomicBinaryPartword(MI, BB, 2, 0, true); 1340 case Mips::ATOMIC_LOAD_NAND_I32: 1341 return emitAtomicBinary(MI, BB, 4, 0, true); 1342 case Mips::ATOMIC_LOAD_NAND_I64: 1343 return emitAtomicBinary(MI, BB, 8, 0, true); 1344 1345 case Mips::ATOMIC_LOAD_SUB_I8: 1346 return emitAtomicBinaryPartword(MI, BB, 1, Mips::SUBu); 1347 case Mips::ATOMIC_LOAD_SUB_I16: 1348 return emitAtomicBinaryPartword(MI, BB, 2, Mips::SUBu); 1349 case Mips::ATOMIC_LOAD_SUB_I32: 1350 return emitAtomicBinary(MI, BB, 4, Mips::SUBu); 1351 case Mips::ATOMIC_LOAD_SUB_I64: 1352 return emitAtomicBinary(MI, BB, 8, Mips::DSUBu); 1353 1354 case Mips::ATOMIC_SWAP_I8: 1355 return emitAtomicBinaryPartword(MI, BB, 1, 0); 1356 case Mips::ATOMIC_SWAP_I16: 1357 return emitAtomicBinaryPartword(MI, BB, 2, 0); 1358 case Mips::ATOMIC_SWAP_I32: 1359 return emitAtomicBinary(MI, BB, 4, 0); 1360 case Mips::ATOMIC_SWAP_I64: 1361 return emitAtomicBinary(MI, BB, 8, 0); 1362 1363 case Mips::ATOMIC_CMP_SWAP_I8: 1364 return emitAtomicCmpSwapPartword(MI, BB, 1); 1365 case Mips::ATOMIC_CMP_SWAP_I16: 1366 return emitAtomicCmpSwapPartword(MI, BB, 2); 1367 case Mips::ATOMIC_CMP_SWAP_I32: 1368 return emitAtomicCmpSwap(MI, BB, 4); 1369 case Mips::ATOMIC_CMP_SWAP_I64: 1370 return emitAtomicCmpSwap(MI, BB, 8); 1371 case Mips::PseudoSDIV: 1372 case Mips::PseudoUDIV: 1373 case Mips::DIV: 1374 case Mips::DIVU: 1375 case Mips::MOD: 1376 case Mips::MODU: 1377 return insertDivByZeroTrap(MI, *BB, *Subtarget.getInstrInfo(), false, 1378 false); 1379 case Mips::SDIV_MM_Pseudo: 1380 case Mips::UDIV_MM_Pseudo: 1381 case Mips::SDIV_MM: 1382 case Mips::UDIV_MM: 1383 case Mips::DIV_MMR6: 1384 case Mips::DIVU_MMR6: 1385 case Mips::MOD_MMR6: 1386 case Mips::MODU_MMR6: 1387 return insertDivByZeroTrap(MI, *BB, *Subtarget.getInstrInfo(), false, true); 1388 case Mips::PseudoDSDIV: 1389 case Mips::PseudoDUDIV: 1390 case Mips::DDIV: 1391 case Mips::DDIVU: 1392 case Mips::DMOD: 1393 case Mips::DMODU: 1394 return insertDivByZeroTrap(MI, *BB, *Subtarget.getInstrInfo(), true, false); 1395 1396 case Mips::PseudoSELECT_I: 1397 case Mips::PseudoSELECT_I64: 1398 case Mips::PseudoSELECT_S: 1399 case Mips::PseudoSELECT_D32: 1400 case Mips::PseudoSELECT_D64: 1401 return emitPseudoSELECT(MI, BB, false, Mips::BNE); 1402 case Mips::PseudoSELECTFP_F_I: 1403 case Mips::PseudoSELECTFP_F_I64: 1404 case Mips::PseudoSELECTFP_F_S: 1405 case Mips::PseudoSELECTFP_F_D32: 1406 case Mips::PseudoSELECTFP_F_D64: 1407 return emitPseudoSELECT(MI, BB, true, Mips::BC1F); 1408 case Mips::PseudoSELECTFP_T_I: 1409 case Mips::PseudoSELECTFP_T_I64: 1410 case Mips::PseudoSELECTFP_T_S: 1411 case Mips::PseudoSELECTFP_T_D32: 1412 case Mips::PseudoSELECTFP_T_D64: 1413 return emitPseudoSELECT(MI, BB, true, Mips::BC1T); 1414 } 1415 } 1416 1417 // This function also handles Mips::ATOMIC_SWAP_I32 (when BinOpcode == 0), and 1418 // Mips::ATOMIC_LOAD_NAND_I32 (when Nand == true) 1419 MachineBasicBlock *MipsTargetLowering::emitAtomicBinary(MachineInstr &MI, 1420 MachineBasicBlock *BB, 1421 unsigned Size, 1422 unsigned BinOpcode, 1423 bool Nand) const { 1424 assert((Size == 4 || Size == 8) && "Unsupported size for EmitAtomicBinary."); 1425 1426 MachineFunction *MF = BB->getParent(); 1427 MachineRegisterInfo &RegInfo = MF->getRegInfo(); 1428 const TargetRegisterClass *RC = getRegClassFor(MVT::getIntegerVT(Size * 8)); 1429 const TargetInstrInfo *TII = Subtarget.getInstrInfo(); 1430 const bool ArePtrs64bit = ABI.ArePtrs64bit(); 1431 DebugLoc DL = MI.getDebugLoc(); 1432 unsigned LL, SC, AND, NOR, ZERO, BEQ; 1433 1434 if (Size == 4) { 1435 if (isMicroMips) { 1436 LL = Mips::LL_MM; 1437 SC = Mips::SC_MM; 1438 } else { 1439 LL = Subtarget.hasMips32r6() 1440 ? (ArePtrs64bit ? Mips::LL64_R6 : Mips::LL_R6) 1441 : (ArePtrs64bit ? Mips::LL64 : Mips::LL); 1442 SC = Subtarget.hasMips32r6() 1443 ? (ArePtrs64bit ? Mips::SC64_R6 : Mips::SC_R6) 1444 : (ArePtrs64bit ? Mips::SC64 : Mips::SC); 1445 } 1446 1447 AND = Mips::AND; 1448 NOR = Mips::NOR; 1449 ZERO = Mips::ZERO; 1450 BEQ = Mips::BEQ; 1451 } else { 1452 LL = Subtarget.hasMips64r6() ? Mips::LLD_R6 : Mips::LLD; 1453 SC = Subtarget.hasMips64r6() ? Mips::SCD_R6 : Mips::SCD; 1454 AND = Mips::AND64; 1455 NOR = Mips::NOR64; 1456 ZERO = Mips::ZERO_64; 1457 BEQ = Mips::BEQ64; 1458 } 1459 1460 unsigned OldVal = MI.getOperand(0).getReg(); 1461 unsigned Ptr = MI.getOperand(1).getReg(); 1462 unsigned Incr = MI.getOperand(2).getReg(); 1463 1464 unsigned StoreVal = RegInfo.createVirtualRegister(RC); 1465 unsigned AndRes = RegInfo.createVirtualRegister(RC); 1466 unsigned Success = RegInfo.createVirtualRegister(RC); 1467 1468 // insert new blocks after the current block 1469 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 1470 MachineBasicBlock *loopMBB = MF->CreateMachineBasicBlock(LLVM_BB); 1471 MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB); 1472 MachineFunction::iterator It = ++BB->getIterator(); 1473 MF->insert(It, loopMBB); 1474 MF->insert(It, exitMBB); 1475 1476 // Transfer the remainder of BB and its successor edges to exitMBB. 1477 exitMBB->splice(exitMBB->begin(), BB, 1478 std::next(MachineBasicBlock::iterator(MI)), BB->end()); 1479 exitMBB->transferSuccessorsAndUpdatePHIs(BB); 1480 1481 // thisMBB: 1482 // ... 1483 // fallthrough --> loopMBB 1484 BB->addSuccessor(loopMBB); 1485 loopMBB->addSuccessor(loopMBB); 1486 loopMBB->addSuccessor(exitMBB); 1487 1488 // loopMBB: 1489 // ll oldval, 0(ptr) 1490 // <binop> storeval, oldval, incr 1491 // sc success, storeval, 0(ptr) 1492 // beq success, $0, loopMBB 1493 BB = loopMBB; 1494 BuildMI(BB, DL, TII->get(LL), OldVal).addReg(Ptr).addImm(0); 1495 if (Nand) { 1496 // and andres, oldval, incr 1497 // nor storeval, $0, andres 1498 BuildMI(BB, DL, TII->get(AND), AndRes).addReg(OldVal).addReg(Incr); 1499 BuildMI(BB, DL, TII->get(NOR), StoreVal).addReg(ZERO).addReg(AndRes); 1500 } else if (BinOpcode) { 1501 // <binop> storeval, oldval, incr 1502 BuildMI(BB, DL, TII->get(BinOpcode), StoreVal).addReg(OldVal).addReg(Incr); 1503 } else { 1504 StoreVal = Incr; 1505 } 1506 BuildMI(BB, DL, TII->get(SC), Success).addReg(StoreVal).addReg(Ptr).addImm(0); 1507 BuildMI(BB, DL, TII->get(BEQ)).addReg(Success).addReg(ZERO).addMBB(loopMBB); 1508 1509 MI.eraseFromParent(); // The instruction is gone now. 1510 1511 return exitMBB; 1512 } 1513 1514 MachineBasicBlock *MipsTargetLowering::emitSignExtendToI32InReg( 1515 MachineInstr &MI, MachineBasicBlock *BB, unsigned Size, unsigned DstReg, 1516 unsigned SrcReg) const { 1517 const TargetInstrInfo *TII = Subtarget.getInstrInfo(); 1518 const DebugLoc &DL = MI.getDebugLoc(); 1519 1520 if (Subtarget.hasMips32r2() && Size == 1) { 1521 BuildMI(BB, DL, TII->get(Mips::SEB), DstReg).addReg(SrcReg); 1522 return BB; 1523 } 1524 1525 if (Subtarget.hasMips32r2() && Size == 2) { 1526 BuildMI(BB, DL, TII->get(Mips::SEH), DstReg).addReg(SrcReg); 1527 return BB; 1528 } 1529 1530 MachineFunction *MF = BB->getParent(); 1531 MachineRegisterInfo &RegInfo = MF->getRegInfo(); 1532 const TargetRegisterClass *RC = getRegClassFor(MVT::i32); 1533 unsigned ScrReg = RegInfo.createVirtualRegister(RC); 1534 1535 assert(Size < 32); 1536 int64_t ShiftImm = 32 - (Size * 8); 1537 1538 BuildMI(BB, DL, TII->get(Mips::SLL), ScrReg).addReg(SrcReg).addImm(ShiftImm); 1539 BuildMI(BB, DL, TII->get(Mips::SRA), DstReg).addReg(ScrReg).addImm(ShiftImm); 1540 1541 return BB; 1542 } 1543 1544 MachineBasicBlock *MipsTargetLowering::emitAtomicBinaryPartword( 1545 MachineInstr &MI, MachineBasicBlock *BB, unsigned Size, unsigned BinOpcode, 1546 bool Nand) const { 1547 assert((Size == 1 || Size == 2) && 1548 "Unsupported size for EmitAtomicBinaryPartial."); 1549 1550 MachineFunction *MF = BB->getParent(); 1551 MachineRegisterInfo &RegInfo = MF->getRegInfo(); 1552 const TargetRegisterClass *RC = getRegClassFor(MVT::i32); 1553 const bool ArePtrs64bit = ABI.ArePtrs64bit(); 1554 const TargetRegisterClass *RCp = 1555 getRegClassFor(ArePtrs64bit ? MVT::i64 : MVT::i32); 1556 const TargetInstrInfo *TII = Subtarget.getInstrInfo(); 1557 DebugLoc DL = MI.getDebugLoc(); 1558 1559 unsigned Dest = MI.getOperand(0).getReg(); 1560 unsigned Ptr = MI.getOperand(1).getReg(); 1561 unsigned Incr = MI.getOperand(2).getReg(); 1562 1563 unsigned AlignedAddr = RegInfo.createVirtualRegister(RCp); 1564 unsigned ShiftAmt = RegInfo.createVirtualRegister(RC); 1565 unsigned Mask = RegInfo.createVirtualRegister(RC); 1566 unsigned Mask2 = RegInfo.createVirtualRegister(RC); 1567 unsigned NewVal = RegInfo.createVirtualRegister(RC); 1568 unsigned OldVal = RegInfo.createVirtualRegister(RC); 1569 unsigned Incr2 = RegInfo.createVirtualRegister(RC); 1570 unsigned MaskLSB2 = RegInfo.createVirtualRegister(RCp); 1571 unsigned PtrLSB2 = RegInfo.createVirtualRegister(RC); 1572 unsigned MaskUpper = RegInfo.createVirtualRegister(RC); 1573 unsigned AndRes = RegInfo.createVirtualRegister(RC); 1574 unsigned BinOpRes = RegInfo.createVirtualRegister(RC); 1575 unsigned MaskedOldVal0 = RegInfo.createVirtualRegister(RC); 1576 unsigned StoreVal = RegInfo.createVirtualRegister(RC); 1577 unsigned MaskedOldVal1 = RegInfo.createVirtualRegister(RC); 1578 unsigned SrlRes = RegInfo.createVirtualRegister(RC); 1579 unsigned Success = RegInfo.createVirtualRegister(RC); 1580 1581 unsigned LL, SC; 1582 if (isMicroMips) { 1583 LL = Mips::LL_MM; 1584 SC = Mips::SC_MM; 1585 } else { 1586 LL = Subtarget.hasMips32r6() ? (ArePtrs64bit ? Mips::LL64_R6 : Mips::LL_R6) 1587 : (ArePtrs64bit ? Mips::LL64 : Mips::LL); 1588 SC = Subtarget.hasMips32r6() ? (ArePtrs64bit ? Mips::SC64_R6 : Mips::SC_R6) 1589 : (ArePtrs64bit ? Mips::SC64 : Mips::SC); 1590 } 1591 1592 // insert new blocks after the current block 1593 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 1594 MachineBasicBlock *loopMBB = MF->CreateMachineBasicBlock(LLVM_BB); 1595 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(LLVM_BB); 1596 MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB); 1597 MachineFunction::iterator It = ++BB->getIterator(); 1598 MF->insert(It, loopMBB); 1599 MF->insert(It, sinkMBB); 1600 MF->insert(It, exitMBB); 1601 1602 // Transfer the remainder of BB and its successor edges to exitMBB. 1603 exitMBB->splice(exitMBB->begin(), BB, 1604 std::next(MachineBasicBlock::iterator(MI)), BB->end()); 1605 exitMBB->transferSuccessorsAndUpdatePHIs(BB); 1606 1607 BB->addSuccessor(loopMBB); 1608 loopMBB->addSuccessor(loopMBB); 1609 loopMBB->addSuccessor(sinkMBB); 1610 sinkMBB->addSuccessor(exitMBB); 1611 1612 // thisMBB: 1613 // addiu masklsb2,$0,-4 # 0xfffffffc 1614 // and alignedaddr,ptr,masklsb2 1615 // andi ptrlsb2,ptr,3 1616 // sll shiftamt,ptrlsb2,3 1617 // ori maskupper,$0,255 # 0xff 1618 // sll mask,maskupper,shiftamt 1619 // nor mask2,$0,mask 1620 // sll incr2,incr,shiftamt 1621 1622 int64_t MaskImm = (Size == 1) ? 255 : 65535; 1623 BuildMI(BB, DL, TII->get(ABI.GetPtrAddiuOp()), MaskLSB2) 1624 .addReg(ABI.GetNullPtr()).addImm(-4); 1625 BuildMI(BB, DL, TII->get(ABI.GetPtrAndOp()), AlignedAddr) 1626 .addReg(Ptr).addReg(MaskLSB2); 1627 BuildMI(BB, DL, TII->get(Mips::ANDi), PtrLSB2) 1628 .addReg(Ptr, 0, ArePtrs64bit ? Mips::sub_32 : 0).addImm(3); 1629 if (Subtarget.isLittle()) { 1630 BuildMI(BB, DL, TII->get(Mips::SLL), ShiftAmt).addReg(PtrLSB2).addImm(3); 1631 } else { 1632 unsigned Off = RegInfo.createVirtualRegister(RC); 1633 BuildMI(BB, DL, TII->get(Mips::XORi), Off) 1634 .addReg(PtrLSB2).addImm((Size == 1) ? 3 : 2); 1635 BuildMI(BB, DL, TII->get(Mips::SLL), ShiftAmt).addReg(Off).addImm(3); 1636 } 1637 BuildMI(BB, DL, TII->get(Mips::ORi), MaskUpper) 1638 .addReg(Mips::ZERO).addImm(MaskImm); 1639 BuildMI(BB, DL, TII->get(Mips::SLLV), Mask) 1640 .addReg(MaskUpper).addReg(ShiftAmt); 1641 BuildMI(BB, DL, TII->get(Mips::NOR), Mask2).addReg(Mips::ZERO).addReg(Mask); 1642 BuildMI(BB, DL, TII->get(Mips::SLLV), Incr2).addReg(Incr).addReg(ShiftAmt); 1643 1644 // atomic.load.binop 1645 // loopMBB: 1646 // ll oldval,0(alignedaddr) 1647 // binop binopres,oldval,incr2 1648 // and newval,binopres,mask 1649 // and maskedoldval0,oldval,mask2 1650 // or storeval,maskedoldval0,newval 1651 // sc success,storeval,0(alignedaddr) 1652 // beq success,$0,loopMBB 1653 1654 // atomic.swap 1655 // loopMBB: 1656 // ll oldval,0(alignedaddr) 1657 // and newval,incr2,mask 1658 // and maskedoldval0,oldval,mask2 1659 // or storeval,maskedoldval0,newval 1660 // sc success,storeval,0(alignedaddr) 1661 // beq success,$0,loopMBB 1662 1663 BB = loopMBB; 1664 BuildMI(BB, DL, TII->get(LL), OldVal).addReg(AlignedAddr).addImm(0); 1665 if (Nand) { 1666 // and andres, oldval, incr2 1667 // nor binopres, $0, andres 1668 // and newval, binopres, mask 1669 BuildMI(BB, DL, TII->get(Mips::AND), AndRes).addReg(OldVal).addReg(Incr2); 1670 BuildMI(BB, DL, TII->get(Mips::NOR), BinOpRes) 1671 .addReg(Mips::ZERO).addReg(AndRes); 1672 BuildMI(BB, DL, TII->get(Mips::AND), NewVal).addReg(BinOpRes).addReg(Mask); 1673 } else if (BinOpcode) { 1674 // <binop> binopres, oldval, incr2 1675 // and newval, binopres, mask 1676 BuildMI(BB, DL, TII->get(BinOpcode), BinOpRes).addReg(OldVal).addReg(Incr2); 1677 BuildMI(BB, DL, TII->get(Mips::AND), NewVal).addReg(BinOpRes).addReg(Mask); 1678 } else { // atomic.swap 1679 // and newval, incr2, mask 1680 BuildMI(BB, DL, TII->get(Mips::AND), NewVal).addReg(Incr2).addReg(Mask); 1681 } 1682 1683 BuildMI(BB, DL, TII->get(Mips::AND), MaskedOldVal0) 1684 .addReg(OldVal).addReg(Mask2); 1685 BuildMI(BB, DL, TII->get(Mips::OR), StoreVal) 1686 .addReg(MaskedOldVal0).addReg(NewVal); 1687 BuildMI(BB, DL, TII->get(SC), Success) 1688 .addReg(StoreVal).addReg(AlignedAddr).addImm(0); 1689 BuildMI(BB, DL, TII->get(Mips::BEQ)) 1690 .addReg(Success).addReg(Mips::ZERO).addMBB(loopMBB); 1691 1692 // sinkMBB: 1693 // and maskedoldval1,oldval,mask 1694 // srl srlres,maskedoldval1,shiftamt 1695 // sign_extend dest,srlres 1696 BB = sinkMBB; 1697 1698 BuildMI(BB, DL, TII->get(Mips::AND), MaskedOldVal1) 1699 .addReg(OldVal).addReg(Mask); 1700 BuildMI(BB, DL, TII->get(Mips::SRLV), SrlRes) 1701 .addReg(MaskedOldVal1).addReg(ShiftAmt); 1702 BB = emitSignExtendToI32InReg(MI, BB, Size, Dest, SrlRes); 1703 1704 MI.eraseFromParent(); // The instruction is gone now. 1705 1706 return exitMBB; 1707 } 1708 1709 MachineBasicBlock *MipsTargetLowering::emitAtomicCmpSwap(MachineInstr &MI, 1710 MachineBasicBlock *BB, 1711 unsigned Size) const { 1712 assert((Size == 4 || Size == 8) && "Unsupported size for EmitAtomicCmpSwap."); 1713 1714 MachineFunction *MF = BB->getParent(); 1715 MachineRegisterInfo &RegInfo = MF->getRegInfo(); 1716 const TargetRegisterClass *RC = getRegClassFor(MVT::getIntegerVT(Size * 8)); 1717 const TargetInstrInfo *TII = Subtarget.getInstrInfo(); 1718 const bool ArePtrs64bit = ABI.ArePtrs64bit(); 1719 DebugLoc DL = MI.getDebugLoc(); 1720 unsigned LL, SC, ZERO, BNE, BEQ; 1721 1722 if (Size == 4) { 1723 if (isMicroMips) { 1724 LL = Mips::LL_MM; 1725 SC = Mips::SC_MM; 1726 } else { 1727 LL = Subtarget.hasMips32r6() 1728 ? (ArePtrs64bit ? Mips::LL64_R6 : Mips::LL_R6) 1729 : (ArePtrs64bit ? Mips::LL64 : Mips::LL); 1730 SC = Subtarget.hasMips32r6() 1731 ? (ArePtrs64bit ? Mips::SC64_R6 : Mips::SC_R6) 1732 : (ArePtrs64bit ? Mips::SC64 : Mips::SC); 1733 } 1734 1735 ZERO = Mips::ZERO; 1736 BNE = Mips::BNE; 1737 BEQ = Mips::BEQ; 1738 } else { 1739 LL = Subtarget.hasMips64r6() ? Mips::LLD_R6 : Mips::LLD; 1740 SC = Subtarget.hasMips64r6() ? Mips::SCD_R6 : Mips::SCD; 1741 ZERO = Mips::ZERO_64; 1742 BNE = Mips::BNE64; 1743 BEQ = Mips::BEQ64; 1744 } 1745 1746 unsigned Dest = MI.getOperand(0).getReg(); 1747 unsigned Ptr = MI.getOperand(1).getReg(); 1748 unsigned OldVal = MI.getOperand(2).getReg(); 1749 unsigned NewVal = MI.getOperand(3).getReg(); 1750 1751 unsigned Success = RegInfo.createVirtualRegister(RC); 1752 1753 // insert new blocks after the current block 1754 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 1755 MachineBasicBlock *loop1MBB = MF->CreateMachineBasicBlock(LLVM_BB); 1756 MachineBasicBlock *loop2MBB = MF->CreateMachineBasicBlock(LLVM_BB); 1757 MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB); 1758 MachineFunction::iterator It = ++BB->getIterator(); 1759 MF->insert(It, loop1MBB); 1760 MF->insert(It, loop2MBB); 1761 MF->insert(It, exitMBB); 1762 1763 // Transfer the remainder of BB and its successor edges to exitMBB. 1764 exitMBB->splice(exitMBB->begin(), BB, 1765 std::next(MachineBasicBlock::iterator(MI)), BB->end()); 1766 exitMBB->transferSuccessorsAndUpdatePHIs(BB); 1767 1768 // thisMBB: 1769 // ... 1770 // fallthrough --> loop1MBB 1771 BB->addSuccessor(loop1MBB); 1772 loop1MBB->addSuccessor(exitMBB); 1773 loop1MBB->addSuccessor(loop2MBB); 1774 loop2MBB->addSuccessor(loop1MBB); 1775 loop2MBB->addSuccessor(exitMBB); 1776 1777 // loop1MBB: 1778 // ll dest, 0(ptr) 1779 // bne dest, oldval, exitMBB 1780 BB = loop1MBB; 1781 BuildMI(BB, DL, TII->get(LL), Dest).addReg(Ptr).addImm(0); 1782 BuildMI(BB, DL, TII->get(BNE)) 1783 .addReg(Dest).addReg(OldVal).addMBB(exitMBB); 1784 1785 // loop2MBB: 1786 // sc success, newval, 0(ptr) 1787 // beq success, $0, loop1MBB 1788 BB = loop2MBB; 1789 BuildMI(BB, DL, TII->get(SC), Success) 1790 .addReg(NewVal).addReg(Ptr).addImm(0); 1791 BuildMI(BB, DL, TII->get(BEQ)) 1792 .addReg(Success).addReg(ZERO).addMBB(loop1MBB); 1793 1794 MI.eraseFromParent(); // The instruction is gone now. 1795 1796 return exitMBB; 1797 } 1798 1799 MachineBasicBlock *MipsTargetLowering::emitAtomicCmpSwapPartword( 1800 MachineInstr &MI, MachineBasicBlock *BB, unsigned Size) const { 1801 assert((Size == 1 || Size == 2) && 1802 "Unsupported size for EmitAtomicCmpSwapPartial."); 1803 1804 MachineFunction *MF = BB->getParent(); 1805 MachineRegisterInfo &RegInfo = MF->getRegInfo(); 1806 const TargetRegisterClass *RC = getRegClassFor(MVT::i32); 1807 const bool ArePtrs64bit = ABI.ArePtrs64bit(); 1808 const TargetRegisterClass *RCp = 1809 getRegClassFor(ArePtrs64bit ? MVT::i64 : MVT::i32); 1810 const TargetInstrInfo *TII = Subtarget.getInstrInfo(); 1811 DebugLoc DL = MI.getDebugLoc(); 1812 1813 unsigned Dest = MI.getOperand(0).getReg(); 1814 unsigned Ptr = MI.getOperand(1).getReg(); 1815 unsigned CmpVal = MI.getOperand(2).getReg(); 1816 unsigned NewVal = MI.getOperand(3).getReg(); 1817 1818 unsigned AlignedAddr = RegInfo.createVirtualRegister(RCp); 1819 unsigned ShiftAmt = RegInfo.createVirtualRegister(RC); 1820 unsigned Mask = RegInfo.createVirtualRegister(RC); 1821 unsigned Mask2 = RegInfo.createVirtualRegister(RC); 1822 unsigned ShiftedCmpVal = RegInfo.createVirtualRegister(RC); 1823 unsigned OldVal = RegInfo.createVirtualRegister(RC); 1824 unsigned MaskedOldVal0 = RegInfo.createVirtualRegister(RC); 1825 unsigned ShiftedNewVal = RegInfo.createVirtualRegister(RC); 1826 unsigned MaskLSB2 = RegInfo.createVirtualRegister(RCp); 1827 unsigned PtrLSB2 = RegInfo.createVirtualRegister(RC); 1828 unsigned MaskUpper = RegInfo.createVirtualRegister(RC); 1829 unsigned MaskedCmpVal = RegInfo.createVirtualRegister(RC); 1830 unsigned MaskedNewVal = RegInfo.createVirtualRegister(RC); 1831 unsigned MaskedOldVal1 = RegInfo.createVirtualRegister(RC); 1832 unsigned StoreVal = RegInfo.createVirtualRegister(RC); 1833 unsigned SrlRes = RegInfo.createVirtualRegister(RC); 1834 unsigned Success = RegInfo.createVirtualRegister(RC); 1835 unsigned LL, SC; 1836 1837 if (isMicroMips) { 1838 LL = Mips::LL_MM; 1839 SC = Mips::SC_MM; 1840 } else { 1841 LL = Subtarget.hasMips32r6() ? (ArePtrs64bit ? Mips::LL64_R6 : Mips::LL_R6) 1842 : (ArePtrs64bit ? Mips::LL64 : Mips::LL); 1843 SC = Subtarget.hasMips32r6() ? (ArePtrs64bit ? Mips::SC64_R6 : Mips::SC_R6) 1844 : (ArePtrs64bit ? Mips::SC64 : Mips::SC); 1845 } 1846 1847 // insert new blocks after the current block 1848 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 1849 MachineBasicBlock *loop1MBB = MF->CreateMachineBasicBlock(LLVM_BB); 1850 MachineBasicBlock *loop2MBB = MF->CreateMachineBasicBlock(LLVM_BB); 1851 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(LLVM_BB); 1852 MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB); 1853 MachineFunction::iterator It = ++BB->getIterator(); 1854 MF->insert(It, loop1MBB); 1855 MF->insert(It, loop2MBB); 1856 MF->insert(It, sinkMBB); 1857 MF->insert(It, exitMBB); 1858 1859 // Transfer the remainder of BB and its successor edges to exitMBB. 1860 exitMBB->splice(exitMBB->begin(), BB, 1861 std::next(MachineBasicBlock::iterator(MI)), BB->end()); 1862 exitMBB->transferSuccessorsAndUpdatePHIs(BB); 1863 1864 BB->addSuccessor(loop1MBB); 1865 loop1MBB->addSuccessor(sinkMBB); 1866 loop1MBB->addSuccessor(loop2MBB); 1867 loop2MBB->addSuccessor(loop1MBB); 1868 loop2MBB->addSuccessor(sinkMBB); 1869 sinkMBB->addSuccessor(exitMBB); 1870 1871 // FIXME: computation of newval2 can be moved to loop2MBB. 1872 // thisMBB: 1873 // addiu masklsb2,$0,-4 # 0xfffffffc 1874 // and alignedaddr,ptr,masklsb2 1875 // andi ptrlsb2,ptr,3 1876 // xori ptrlsb2,ptrlsb2,3 # Only for BE 1877 // sll shiftamt,ptrlsb2,3 1878 // ori maskupper,$0,255 # 0xff 1879 // sll mask,maskupper,shiftamt 1880 // nor mask2,$0,mask 1881 // andi maskedcmpval,cmpval,255 1882 // sll shiftedcmpval,maskedcmpval,shiftamt 1883 // andi maskednewval,newval,255 1884 // sll shiftednewval,maskednewval,shiftamt 1885 int64_t MaskImm = (Size == 1) ? 255 : 65535; 1886 BuildMI(BB, DL, TII->get(ArePtrs64bit ? Mips::DADDiu : Mips::ADDiu), MaskLSB2) 1887 .addReg(ABI.GetNullPtr()).addImm(-4); 1888 BuildMI(BB, DL, TII->get(ArePtrs64bit ? Mips::AND64 : Mips::AND), AlignedAddr) 1889 .addReg(Ptr).addReg(MaskLSB2); 1890 BuildMI(BB, DL, TII->get(Mips::ANDi), PtrLSB2) 1891 .addReg(Ptr, 0, ArePtrs64bit ? Mips::sub_32 : 0).addImm(3); 1892 if (Subtarget.isLittle()) { 1893 BuildMI(BB, DL, TII->get(Mips::SLL), ShiftAmt).addReg(PtrLSB2).addImm(3); 1894 } else { 1895 unsigned Off = RegInfo.createVirtualRegister(RC); 1896 BuildMI(BB, DL, TII->get(Mips::XORi), Off) 1897 .addReg(PtrLSB2).addImm((Size == 1) ? 3 : 2); 1898 BuildMI(BB, DL, TII->get(Mips::SLL), ShiftAmt).addReg(Off).addImm(3); 1899 } 1900 BuildMI(BB, DL, TII->get(Mips::ORi), MaskUpper) 1901 .addReg(Mips::ZERO).addImm(MaskImm); 1902 BuildMI(BB, DL, TII->get(Mips::SLLV), Mask) 1903 .addReg(MaskUpper).addReg(ShiftAmt); 1904 BuildMI(BB, DL, TII->get(Mips::NOR), Mask2).addReg(Mips::ZERO).addReg(Mask); 1905 BuildMI(BB, DL, TII->get(Mips::ANDi), MaskedCmpVal) 1906 .addReg(CmpVal).addImm(MaskImm); 1907 BuildMI(BB, DL, TII->get(Mips::SLLV), ShiftedCmpVal) 1908 .addReg(MaskedCmpVal).addReg(ShiftAmt); 1909 BuildMI(BB, DL, TII->get(Mips::ANDi), MaskedNewVal) 1910 .addReg(NewVal).addImm(MaskImm); 1911 BuildMI(BB, DL, TII->get(Mips::SLLV), ShiftedNewVal) 1912 .addReg(MaskedNewVal).addReg(ShiftAmt); 1913 1914 // loop1MBB: 1915 // ll oldval,0(alginedaddr) 1916 // and maskedoldval0,oldval,mask 1917 // bne maskedoldval0,shiftedcmpval,sinkMBB 1918 BB = loop1MBB; 1919 BuildMI(BB, DL, TII->get(LL), OldVal).addReg(AlignedAddr).addImm(0); 1920 BuildMI(BB, DL, TII->get(Mips::AND), MaskedOldVal0) 1921 .addReg(OldVal).addReg(Mask); 1922 BuildMI(BB, DL, TII->get(Mips::BNE)) 1923 .addReg(MaskedOldVal0).addReg(ShiftedCmpVal).addMBB(sinkMBB); 1924 1925 // loop2MBB: 1926 // and maskedoldval1,oldval,mask2 1927 // or storeval,maskedoldval1,shiftednewval 1928 // sc success,storeval,0(alignedaddr) 1929 // beq success,$0,loop1MBB 1930 BB = loop2MBB; 1931 BuildMI(BB, DL, TII->get(Mips::AND), MaskedOldVal1) 1932 .addReg(OldVal).addReg(Mask2); 1933 BuildMI(BB, DL, TII->get(Mips::OR), StoreVal) 1934 .addReg(MaskedOldVal1).addReg(ShiftedNewVal); 1935 BuildMI(BB, DL, TII->get(SC), Success) 1936 .addReg(StoreVal).addReg(AlignedAddr).addImm(0); 1937 BuildMI(BB, DL, TII->get(Mips::BEQ)) 1938 .addReg(Success).addReg(Mips::ZERO).addMBB(loop1MBB); 1939 1940 // sinkMBB: 1941 // srl srlres,maskedoldval0,shiftamt 1942 // sign_extend dest,srlres 1943 BB = sinkMBB; 1944 1945 BuildMI(BB, DL, TII->get(Mips::SRLV), SrlRes) 1946 .addReg(MaskedOldVal0).addReg(ShiftAmt); 1947 BB = emitSignExtendToI32InReg(MI, BB, Size, Dest, SrlRes); 1948 1949 MI.eraseFromParent(); // The instruction is gone now. 1950 1951 return exitMBB; 1952 } 1953 1954 SDValue MipsTargetLowering::lowerBRCOND(SDValue Op, SelectionDAG &DAG) const { 1955 // The first operand is the chain, the second is the condition, the third is 1956 // the block to branch to if the condition is true. 1957 SDValue Chain = Op.getOperand(0); 1958 SDValue Dest = Op.getOperand(2); 1959 SDLoc DL(Op); 1960 1961 assert(!Subtarget.hasMips32r6() && !Subtarget.hasMips64r6()); 1962 SDValue CondRes = createFPCmp(DAG, Op.getOperand(1)); 1963 1964 // Return if flag is not set by a floating point comparison. 1965 if (CondRes.getOpcode() != MipsISD::FPCmp) 1966 return Op; 1967 1968 SDValue CCNode = CondRes.getOperand(2); 1969 Mips::CondCode CC = 1970 (Mips::CondCode)cast<ConstantSDNode>(CCNode)->getZExtValue(); 1971 unsigned Opc = invertFPCondCodeUser(CC) ? Mips::BRANCH_F : Mips::BRANCH_T; 1972 SDValue BrCode = DAG.getConstant(Opc, DL, MVT::i32); 1973 SDValue FCC0 = DAG.getRegister(Mips::FCC0, MVT::i32); 1974 return DAG.getNode(MipsISD::FPBrcond, DL, Op.getValueType(), Chain, BrCode, 1975 FCC0, Dest, CondRes); 1976 } 1977 1978 SDValue MipsTargetLowering:: 1979 lowerSELECT(SDValue Op, SelectionDAG &DAG) const 1980 { 1981 assert(!Subtarget.hasMips32r6() && !Subtarget.hasMips64r6()); 1982 SDValue Cond = createFPCmp(DAG, Op.getOperand(0)); 1983 1984 // Return if flag is not set by a floating point comparison. 1985 if (Cond.getOpcode() != MipsISD::FPCmp) 1986 return Op; 1987 1988 return createCMovFP(DAG, Cond, Op.getOperand(1), Op.getOperand(2), 1989 SDLoc(Op)); 1990 } 1991 1992 SDValue MipsTargetLowering::lowerSETCC(SDValue Op, SelectionDAG &DAG) const { 1993 assert(!Subtarget.hasMips32r6() && !Subtarget.hasMips64r6()); 1994 SDValue Cond = createFPCmp(DAG, Op); 1995 1996 assert(Cond.getOpcode() == MipsISD::FPCmp && 1997 "Floating point operand expected."); 1998 1999 SDLoc DL(Op); 2000 SDValue True = DAG.getConstant(1, DL, MVT::i32); 2001 SDValue False = DAG.getConstant(0, DL, MVT::i32); 2002 2003 return createCMovFP(DAG, Cond, True, False, DL); 2004 } 2005 2006 SDValue MipsTargetLowering::lowerGlobalAddress(SDValue Op, 2007 SelectionDAG &DAG) const { 2008 EVT Ty = Op.getValueType(); 2009 GlobalAddressSDNode *N = cast<GlobalAddressSDNode>(Op); 2010 const GlobalValue *GV = N->getGlobal(); 2011 2012 if (!isPositionIndependent()) { 2013 const MipsTargetObjectFile *TLOF = 2014 static_cast<const MipsTargetObjectFile *>( 2015 getTargetMachine().getObjFileLowering()); 2016 const GlobalObject *GO = GV->getBaseObject(); 2017 if (GO && TLOF->IsGlobalInSmallSection(GO, getTargetMachine())) 2018 // %gp_rel relocation 2019 return getAddrGPRel(N, SDLoc(N), Ty, DAG, ABI.IsN64()); 2020 2021 // %hi/%lo relocation 2022 return Subtarget.hasSym32() ? getAddrNonPIC(N, SDLoc(N), Ty, DAG) 2023 // %highest/%higher/%hi/%lo relocation 2024 : getAddrNonPICSym64(N, SDLoc(N), Ty, DAG); 2025 } 2026 2027 // Every other architecture would use shouldAssumeDSOLocal in here, but 2028 // mips is special. 2029 // * In PIC code mips requires got loads even for local statics! 2030 // * To save on got entries, for local statics the got entry contains the 2031 // page and an additional add instruction takes care of the low bits. 2032 // * It is legal to access a hidden symbol with a non hidden undefined, 2033 // so one cannot guarantee that all access to a hidden symbol will know 2034 // it is hidden. 2035 // * Mips linkers don't support creating a page and a full got entry for 2036 // the same symbol. 2037 // * Given all that, we have to use a full got entry for hidden symbols :-( 2038 if (GV->hasLocalLinkage()) 2039 return getAddrLocal(N, SDLoc(N), Ty, DAG, ABI.IsN32() || ABI.IsN64()); 2040 2041 if (LargeGOT) 2042 return getAddrGlobalLargeGOT( 2043 N, SDLoc(N), Ty, DAG, MipsII::MO_GOT_HI16, MipsII::MO_GOT_LO16, 2044 DAG.getEntryNode(), 2045 MachinePointerInfo::getGOT(DAG.getMachineFunction())); 2046 2047 return getAddrGlobal( 2048 N, SDLoc(N), Ty, DAG, 2049 (ABI.IsN32() || ABI.IsN64()) ? MipsII::MO_GOT_DISP : MipsII::MO_GOT, 2050 DAG.getEntryNode(), MachinePointerInfo::getGOT(DAG.getMachineFunction())); 2051 } 2052 2053 SDValue MipsTargetLowering::lowerBlockAddress(SDValue Op, 2054 SelectionDAG &DAG) const { 2055 BlockAddressSDNode *N = cast<BlockAddressSDNode>(Op); 2056 EVT Ty = Op.getValueType(); 2057 2058 if (!isPositionIndependent()) 2059 return Subtarget.hasSym32() ? getAddrNonPIC(N, SDLoc(N), Ty, DAG) 2060 : getAddrNonPICSym64(N, SDLoc(N), Ty, DAG); 2061 2062 return getAddrLocal(N, SDLoc(N), Ty, DAG, ABI.IsN32() || ABI.IsN64()); 2063 } 2064 2065 SDValue MipsTargetLowering:: 2066 lowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const 2067 { 2068 // If the relocation model is PIC, use the General Dynamic TLS Model or 2069 // Local Dynamic TLS model, otherwise use the Initial Exec or 2070 // Local Exec TLS Model. 2071 2072 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op); 2073 if (DAG.getTarget().useEmulatedTLS()) 2074 return LowerToTLSEmulatedModel(GA, DAG); 2075 2076 SDLoc DL(GA); 2077 const GlobalValue *GV = GA->getGlobal(); 2078 EVT PtrVT = getPointerTy(DAG.getDataLayout()); 2079 2080 TLSModel::Model model = getTargetMachine().getTLSModel(GV); 2081 2082 if (model == TLSModel::GeneralDynamic || model == TLSModel::LocalDynamic) { 2083 // General Dynamic and Local Dynamic TLS Model. 2084 unsigned Flag = (model == TLSModel::LocalDynamic) ? MipsII::MO_TLSLDM 2085 : MipsII::MO_TLSGD; 2086 2087 SDValue TGA = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, Flag); 2088 SDValue Argument = DAG.getNode(MipsISD::Wrapper, DL, PtrVT, 2089 getGlobalReg(DAG, PtrVT), TGA); 2090 unsigned PtrSize = PtrVT.getSizeInBits(); 2091 IntegerType *PtrTy = Type::getIntNTy(*DAG.getContext(), PtrSize); 2092 2093 SDValue TlsGetAddr = DAG.getExternalSymbol("__tls_get_addr", PtrVT); 2094 2095 ArgListTy Args; 2096 ArgListEntry Entry; 2097 Entry.Node = Argument; 2098 Entry.Ty = PtrTy; 2099 Args.push_back(Entry); 2100 2101 TargetLowering::CallLoweringInfo CLI(DAG); 2102 CLI.setDebugLoc(DL) 2103 .setChain(DAG.getEntryNode()) 2104 .setLibCallee(CallingConv::C, PtrTy, TlsGetAddr, std::move(Args)); 2105 std::pair<SDValue, SDValue> CallResult = LowerCallTo(CLI); 2106 2107 SDValue Ret = CallResult.first; 2108 2109 if (model != TLSModel::LocalDynamic) 2110 return Ret; 2111 2112 SDValue TGAHi = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, 2113 MipsII::MO_DTPREL_HI); 2114 SDValue Hi = DAG.getNode(MipsISD::Hi, DL, PtrVT, TGAHi); 2115 SDValue TGALo = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, 2116 MipsII::MO_DTPREL_LO); 2117 SDValue Lo = DAG.getNode(MipsISD::Lo, DL, PtrVT, TGALo); 2118 SDValue Add = DAG.getNode(ISD::ADD, DL, PtrVT, Hi, Ret); 2119 return DAG.getNode(ISD::ADD, DL, PtrVT, Add, Lo); 2120 } 2121 2122 SDValue Offset; 2123 if (model == TLSModel::InitialExec) { 2124 // Initial Exec TLS Model 2125 SDValue TGA = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, 2126 MipsII::MO_GOTTPREL); 2127 TGA = DAG.getNode(MipsISD::Wrapper, DL, PtrVT, getGlobalReg(DAG, PtrVT), 2128 TGA); 2129 Offset = 2130 DAG.getLoad(PtrVT, DL, DAG.getEntryNode(), TGA, MachinePointerInfo()); 2131 } else { 2132 // Local Exec TLS Model 2133 assert(model == TLSModel::LocalExec); 2134 SDValue TGAHi = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, 2135 MipsII::MO_TPREL_HI); 2136 SDValue TGALo = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, 2137 MipsII::MO_TPREL_LO); 2138 SDValue Hi = DAG.getNode(MipsISD::Hi, DL, PtrVT, TGAHi); 2139 SDValue Lo = DAG.getNode(MipsISD::Lo, DL, PtrVT, TGALo); 2140 Offset = DAG.getNode(ISD::ADD, DL, PtrVT, Hi, Lo); 2141 } 2142 2143 SDValue ThreadPointer = DAG.getNode(MipsISD::ThreadPointer, DL, PtrVT); 2144 return DAG.getNode(ISD::ADD, DL, PtrVT, ThreadPointer, Offset); 2145 } 2146 2147 SDValue MipsTargetLowering:: 2148 lowerJumpTable(SDValue Op, SelectionDAG &DAG) const 2149 { 2150 JumpTableSDNode *N = cast<JumpTableSDNode>(Op); 2151 EVT Ty = Op.getValueType(); 2152 2153 if (!isPositionIndependent()) 2154 return Subtarget.hasSym32() ? getAddrNonPIC(N, SDLoc(N), Ty, DAG) 2155 : getAddrNonPICSym64(N, SDLoc(N), Ty, DAG); 2156 2157 return getAddrLocal(N, SDLoc(N), Ty, DAG, ABI.IsN32() || ABI.IsN64()); 2158 } 2159 2160 SDValue MipsTargetLowering:: 2161 lowerConstantPool(SDValue Op, SelectionDAG &DAG) const 2162 { 2163 ConstantPoolSDNode *N = cast<ConstantPoolSDNode>(Op); 2164 EVT Ty = Op.getValueType(); 2165 2166 if (!isPositionIndependent()) { 2167 const MipsTargetObjectFile *TLOF = 2168 static_cast<const MipsTargetObjectFile *>( 2169 getTargetMachine().getObjFileLowering()); 2170 2171 if (TLOF->IsConstantInSmallSection(DAG.getDataLayout(), N->getConstVal(), 2172 getTargetMachine())) 2173 // %gp_rel relocation 2174 return getAddrGPRel(N, SDLoc(N), Ty, DAG, ABI.IsN64()); 2175 2176 return Subtarget.hasSym32() ? getAddrNonPIC(N, SDLoc(N), Ty, DAG) 2177 : getAddrNonPICSym64(N, SDLoc(N), Ty, DAG); 2178 } 2179 2180 return getAddrLocal(N, SDLoc(N), Ty, DAG, ABI.IsN32() || ABI.IsN64()); 2181 } 2182 2183 SDValue MipsTargetLowering::lowerVASTART(SDValue Op, SelectionDAG &DAG) const { 2184 MachineFunction &MF = DAG.getMachineFunction(); 2185 MipsFunctionInfo *FuncInfo = MF.getInfo<MipsFunctionInfo>(); 2186 2187 SDLoc DL(Op); 2188 SDValue FI = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), 2189 getPointerTy(MF.getDataLayout())); 2190 2191 // vastart just stores the address of the VarArgsFrameIndex slot into the 2192 // memory location argument. 2193 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue(); 2194 return DAG.getStore(Op.getOperand(0), DL, FI, Op.getOperand(1), 2195 MachinePointerInfo(SV)); 2196 } 2197 2198 SDValue MipsTargetLowering::lowerVAARG(SDValue Op, SelectionDAG &DAG) const { 2199 SDNode *Node = Op.getNode(); 2200 EVT VT = Node->getValueType(0); 2201 SDValue Chain = Node->getOperand(0); 2202 SDValue VAListPtr = Node->getOperand(1); 2203 unsigned Align = Node->getConstantOperandVal(3); 2204 const Value *SV = cast<SrcValueSDNode>(Node->getOperand(2))->getValue(); 2205 SDLoc DL(Node); 2206 unsigned ArgSlotSizeInBytes = (ABI.IsN32() || ABI.IsN64()) ? 8 : 4; 2207 2208 SDValue VAListLoad = DAG.getLoad(getPointerTy(DAG.getDataLayout()), DL, Chain, 2209 VAListPtr, MachinePointerInfo(SV)); 2210 SDValue VAList = VAListLoad; 2211 2212 // Re-align the pointer if necessary. 2213 // It should only ever be necessary for 64-bit types on O32 since the minimum 2214 // argument alignment is the same as the maximum type alignment for N32/N64. 2215 // 2216 // FIXME: We currently align too often. The code generator doesn't notice 2217 // when the pointer is still aligned from the last va_arg (or pair of 2218 // va_args for the i64 on O32 case). 2219 if (Align > getMinStackArgumentAlignment()) { 2220 assert(((Align & (Align-1)) == 0) && "Expected Align to be a power of 2"); 2221 2222 VAList = DAG.getNode(ISD::ADD, DL, VAList.getValueType(), VAList, 2223 DAG.getConstant(Align - 1, DL, VAList.getValueType())); 2224 2225 VAList = DAG.getNode(ISD::AND, DL, VAList.getValueType(), VAList, 2226 DAG.getConstant(-(int64_t)Align, DL, 2227 VAList.getValueType())); 2228 } 2229 2230 // Increment the pointer, VAList, to the next vaarg. 2231 auto &TD = DAG.getDataLayout(); 2232 unsigned ArgSizeInBytes = 2233 TD.getTypeAllocSize(VT.getTypeForEVT(*DAG.getContext())); 2234 SDValue Tmp3 = 2235 DAG.getNode(ISD::ADD, DL, VAList.getValueType(), VAList, 2236 DAG.getConstant(alignTo(ArgSizeInBytes, ArgSlotSizeInBytes), 2237 DL, VAList.getValueType())); 2238 // Store the incremented VAList to the legalized pointer 2239 Chain = DAG.getStore(VAListLoad.getValue(1), DL, Tmp3, VAListPtr, 2240 MachinePointerInfo(SV)); 2241 2242 // In big-endian mode we must adjust the pointer when the load size is smaller 2243 // than the argument slot size. We must also reduce the known alignment to 2244 // match. For example in the N64 ABI, we must add 4 bytes to the offset to get 2245 // the correct half of the slot, and reduce the alignment from 8 (slot 2246 // alignment) down to 4 (type alignment). 2247 if (!Subtarget.isLittle() && ArgSizeInBytes < ArgSlotSizeInBytes) { 2248 unsigned Adjustment = ArgSlotSizeInBytes - ArgSizeInBytes; 2249 VAList = DAG.getNode(ISD::ADD, DL, VAListPtr.getValueType(), VAList, 2250 DAG.getIntPtrConstant(Adjustment, DL)); 2251 } 2252 // Load the actual argument out of the pointer VAList 2253 return DAG.getLoad(VT, DL, Chain, VAList, MachinePointerInfo()); 2254 } 2255 2256 static SDValue lowerFCOPYSIGN32(SDValue Op, SelectionDAG &DAG, 2257 bool HasExtractInsert) { 2258 EVT TyX = Op.getOperand(0).getValueType(); 2259 EVT TyY = Op.getOperand(1).getValueType(); 2260 SDLoc DL(Op); 2261 SDValue Const1 = DAG.getConstant(1, DL, MVT::i32); 2262 SDValue Const31 = DAG.getConstant(31, DL, MVT::i32); 2263 SDValue Res; 2264 2265 // If operand is of type f64, extract the upper 32-bit. Otherwise, bitcast it 2266 // to i32. 2267 SDValue X = (TyX == MVT::f32) ? 2268 DAG.getNode(ISD::BITCAST, DL, MVT::i32, Op.getOperand(0)) : 2269 DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32, Op.getOperand(0), 2270 Const1); 2271 SDValue Y = (TyY == MVT::f32) ? 2272 DAG.getNode(ISD::BITCAST, DL, MVT::i32, Op.getOperand(1)) : 2273 DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32, Op.getOperand(1), 2274 Const1); 2275 2276 if (HasExtractInsert) { 2277 // ext E, Y, 31, 1 ; extract bit31 of Y 2278 // ins X, E, 31, 1 ; insert extracted bit at bit31 of X 2279 SDValue E = DAG.getNode(MipsISD::Ext, DL, MVT::i32, Y, Const31, Const1); 2280 Res = DAG.getNode(MipsISD::Ins, DL, MVT::i32, E, Const31, Const1, X); 2281 } else { 2282 // sll SllX, X, 1 2283 // srl SrlX, SllX, 1 2284 // srl SrlY, Y, 31 2285 // sll SllY, SrlX, 31 2286 // or Or, SrlX, SllY 2287 SDValue SllX = DAG.getNode(ISD::SHL, DL, MVT::i32, X, Const1); 2288 SDValue SrlX = DAG.getNode(ISD::SRL, DL, MVT::i32, SllX, Const1); 2289 SDValue SrlY = DAG.getNode(ISD::SRL, DL, MVT::i32, Y, Const31); 2290 SDValue SllY = DAG.getNode(ISD::SHL, DL, MVT::i32, SrlY, Const31); 2291 Res = DAG.getNode(ISD::OR, DL, MVT::i32, SrlX, SllY); 2292 } 2293 2294 if (TyX == MVT::f32) 2295 return DAG.getNode(ISD::BITCAST, DL, Op.getOperand(0).getValueType(), Res); 2296 2297 SDValue LowX = DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32, 2298 Op.getOperand(0), 2299 DAG.getConstant(0, DL, MVT::i32)); 2300 return DAG.getNode(MipsISD::BuildPairF64, DL, MVT::f64, LowX, Res); 2301 } 2302 2303 static SDValue lowerFCOPYSIGN64(SDValue Op, SelectionDAG &DAG, 2304 bool HasExtractInsert) { 2305 unsigned WidthX = Op.getOperand(0).getValueSizeInBits(); 2306 unsigned WidthY = Op.getOperand(1).getValueSizeInBits(); 2307 EVT TyX = MVT::getIntegerVT(WidthX), TyY = MVT::getIntegerVT(WidthY); 2308 SDLoc DL(Op); 2309 SDValue Const1 = DAG.getConstant(1, DL, MVT::i32); 2310 2311 // Bitcast to integer nodes. 2312 SDValue X = DAG.getNode(ISD::BITCAST, DL, TyX, Op.getOperand(0)); 2313 SDValue Y = DAG.getNode(ISD::BITCAST, DL, TyY, Op.getOperand(1)); 2314 2315 if (HasExtractInsert) { 2316 // ext E, Y, width(Y) - 1, 1 ; extract bit width(Y)-1 of Y 2317 // ins X, E, width(X) - 1, 1 ; insert extracted bit at bit width(X)-1 of X 2318 SDValue E = DAG.getNode(MipsISD::Ext, DL, TyY, Y, 2319 DAG.getConstant(WidthY - 1, DL, MVT::i32), Const1); 2320 2321 if (WidthX > WidthY) 2322 E = DAG.getNode(ISD::ZERO_EXTEND, DL, TyX, E); 2323 else if (WidthY > WidthX) 2324 E = DAG.getNode(ISD::TRUNCATE, DL, TyX, E); 2325 2326 SDValue I = DAG.getNode(MipsISD::Ins, DL, TyX, E, 2327 DAG.getConstant(WidthX - 1, DL, MVT::i32), Const1, 2328 X); 2329 return DAG.getNode(ISD::BITCAST, DL, Op.getOperand(0).getValueType(), I); 2330 } 2331 2332 // (d)sll SllX, X, 1 2333 // (d)srl SrlX, SllX, 1 2334 // (d)srl SrlY, Y, width(Y)-1 2335 // (d)sll SllY, SrlX, width(Y)-1 2336 // or Or, SrlX, SllY 2337 SDValue SllX = DAG.getNode(ISD::SHL, DL, TyX, X, Const1); 2338 SDValue SrlX = DAG.getNode(ISD::SRL, DL, TyX, SllX, Const1); 2339 SDValue SrlY = DAG.getNode(ISD::SRL, DL, TyY, Y, 2340 DAG.getConstant(WidthY - 1, DL, MVT::i32)); 2341 2342 if (WidthX > WidthY) 2343 SrlY = DAG.getNode(ISD::ZERO_EXTEND, DL, TyX, SrlY); 2344 else if (WidthY > WidthX) 2345 SrlY = DAG.getNode(ISD::TRUNCATE, DL, TyX, SrlY); 2346 2347 SDValue SllY = DAG.getNode(ISD::SHL, DL, TyX, SrlY, 2348 DAG.getConstant(WidthX - 1, DL, MVT::i32)); 2349 SDValue Or = DAG.getNode(ISD::OR, DL, TyX, SrlX, SllY); 2350 return DAG.getNode(ISD::BITCAST, DL, Op.getOperand(0).getValueType(), Or); 2351 } 2352 2353 SDValue 2354 MipsTargetLowering::lowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const { 2355 if (Subtarget.isGP64bit()) 2356 return lowerFCOPYSIGN64(Op, DAG, Subtarget.hasExtractInsert()); 2357 2358 return lowerFCOPYSIGN32(Op, DAG, Subtarget.hasExtractInsert()); 2359 } 2360 2361 SDValue MipsTargetLowering:: 2362 lowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const { 2363 // check the depth 2364 assert((cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue() == 0) && 2365 "Frame address can only be determined for current frame."); 2366 2367 MachineFrameInfo &MFI = DAG.getMachineFunction().getFrameInfo(); 2368 MFI.setFrameAddressIsTaken(true); 2369 EVT VT = Op.getValueType(); 2370 SDLoc DL(Op); 2371 SDValue FrameAddr = DAG.getCopyFromReg( 2372 DAG.getEntryNode(), DL, ABI.IsN64() ? Mips::FP_64 : Mips::FP, VT); 2373 return FrameAddr; 2374 } 2375 2376 SDValue MipsTargetLowering::lowerRETURNADDR(SDValue Op, 2377 SelectionDAG &DAG) const { 2378 if (verifyReturnAddressArgumentIsConstant(Op, DAG)) 2379 return SDValue(); 2380 2381 // check the depth 2382 assert((cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue() == 0) && 2383 "Return address can be determined only for current frame."); 2384 2385 MachineFunction &MF = DAG.getMachineFunction(); 2386 MachineFrameInfo &MFI = MF.getFrameInfo(); 2387 MVT VT = Op.getSimpleValueType(); 2388 unsigned RA = ABI.IsN64() ? Mips::RA_64 : Mips::RA; 2389 MFI.setReturnAddressIsTaken(true); 2390 2391 // Return RA, which contains the return address. Mark it an implicit live-in. 2392 unsigned Reg = MF.addLiveIn(RA, getRegClassFor(VT)); 2393 return DAG.getCopyFromReg(DAG.getEntryNode(), SDLoc(Op), Reg, VT); 2394 } 2395 2396 // An EH_RETURN is the result of lowering llvm.eh.return which in turn is 2397 // generated from __builtin_eh_return (offset, handler) 2398 // The effect of this is to adjust the stack pointer by "offset" 2399 // and then branch to "handler". 2400 SDValue MipsTargetLowering::lowerEH_RETURN(SDValue Op, SelectionDAG &DAG) 2401 const { 2402 MachineFunction &MF = DAG.getMachineFunction(); 2403 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>(); 2404 2405 MipsFI->setCallsEhReturn(); 2406 SDValue Chain = Op.getOperand(0); 2407 SDValue Offset = Op.getOperand(1); 2408 SDValue Handler = Op.getOperand(2); 2409 SDLoc DL(Op); 2410 EVT Ty = ABI.IsN64() ? MVT::i64 : MVT::i32; 2411 2412 // Store stack offset in V1, store jump target in V0. Glue CopyToReg and 2413 // EH_RETURN nodes, so that instructions are emitted back-to-back. 2414 unsigned OffsetReg = ABI.IsN64() ? Mips::V1_64 : Mips::V1; 2415 unsigned AddrReg = ABI.IsN64() ? Mips::V0_64 : Mips::V0; 2416 Chain = DAG.getCopyToReg(Chain, DL, OffsetReg, Offset, SDValue()); 2417 Chain = DAG.getCopyToReg(Chain, DL, AddrReg, Handler, Chain.getValue(1)); 2418 return DAG.getNode(MipsISD::EH_RETURN, DL, MVT::Other, Chain, 2419 DAG.getRegister(OffsetReg, Ty), 2420 DAG.getRegister(AddrReg, getPointerTy(MF.getDataLayout())), 2421 Chain.getValue(1)); 2422 } 2423 2424 SDValue MipsTargetLowering::lowerATOMIC_FENCE(SDValue Op, 2425 SelectionDAG &DAG) const { 2426 // FIXME: Need pseudo-fence for 'singlethread' fences 2427 // FIXME: Set SType for weaker fences where supported/appropriate. 2428 unsigned SType = 0; 2429 SDLoc DL(Op); 2430 return DAG.getNode(MipsISD::Sync, DL, MVT::Other, Op.getOperand(0), 2431 DAG.getConstant(SType, DL, MVT::i32)); 2432 } 2433 2434 SDValue MipsTargetLowering::lowerShiftLeftParts(SDValue Op, 2435 SelectionDAG &DAG) const { 2436 SDLoc DL(Op); 2437 MVT VT = Subtarget.isGP64bit() ? MVT::i64 : MVT::i32; 2438 2439 SDValue Lo = Op.getOperand(0), Hi = Op.getOperand(1); 2440 SDValue Shamt = Op.getOperand(2); 2441 // if shamt < (VT.bits): 2442 // lo = (shl lo, shamt) 2443 // hi = (or (shl hi, shamt) (srl (srl lo, 1), ~shamt)) 2444 // else: 2445 // lo = 0 2446 // hi = (shl lo, shamt[4:0]) 2447 SDValue Not = DAG.getNode(ISD::XOR, DL, MVT::i32, Shamt, 2448 DAG.getConstant(-1, DL, MVT::i32)); 2449 SDValue ShiftRight1Lo = DAG.getNode(ISD::SRL, DL, VT, Lo, 2450 DAG.getConstant(1, DL, VT)); 2451 SDValue ShiftRightLo = DAG.getNode(ISD::SRL, DL, VT, ShiftRight1Lo, Not); 2452 SDValue ShiftLeftHi = DAG.getNode(ISD::SHL, DL, VT, Hi, Shamt); 2453 SDValue Or = DAG.getNode(ISD::OR, DL, VT, ShiftLeftHi, ShiftRightLo); 2454 SDValue ShiftLeftLo = DAG.getNode(ISD::SHL, DL, VT, Lo, Shamt); 2455 SDValue Cond = DAG.getNode(ISD::AND, DL, MVT::i32, Shamt, 2456 DAG.getConstant(VT.getSizeInBits(), DL, MVT::i32)); 2457 Lo = DAG.getNode(ISD::SELECT, DL, VT, Cond, 2458 DAG.getConstant(0, DL, VT), ShiftLeftLo); 2459 Hi = DAG.getNode(ISD::SELECT, DL, VT, Cond, ShiftLeftLo, Or); 2460 2461 SDValue Ops[2] = {Lo, Hi}; 2462 return DAG.getMergeValues(Ops, DL); 2463 } 2464 2465 SDValue MipsTargetLowering::lowerShiftRightParts(SDValue Op, SelectionDAG &DAG, 2466 bool IsSRA) const { 2467 SDLoc DL(Op); 2468 SDValue Lo = Op.getOperand(0), Hi = Op.getOperand(1); 2469 SDValue Shamt = Op.getOperand(2); 2470 MVT VT = Subtarget.isGP64bit() ? MVT::i64 : MVT::i32; 2471 2472 // if shamt < (VT.bits): 2473 // lo = (or (shl (shl hi, 1), ~shamt) (srl lo, shamt)) 2474 // if isSRA: 2475 // hi = (sra hi, shamt) 2476 // else: 2477 // hi = (srl hi, shamt) 2478 // else: 2479 // if isSRA: 2480 // lo = (sra hi, shamt[4:0]) 2481 // hi = (sra hi, 31) 2482 // else: 2483 // lo = (srl hi, shamt[4:0]) 2484 // hi = 0 2485 SDValue Not = DAG.getNode(ISD::XOR, DL, MVT::i32, Shamt, 2486 DAG.getConstant(-1, DL, MVT::i32)); 2487 SDValue ShiftLeft1Hi = DAG.getNode(ISD::SHL, DL, VT, Hi, 2488 DAG.getConstant(1, DL, VT)); 2489 SDValue ShiftLeftHi = DAG.getNode(ISD::SHL, DL, VT, ShiftLeft1Hi, Not); 2490 SDValue ShiftRightLo = DAG.getNode(ISD::SRL, DL, VT, Lo, Shamt); 2491 SDValue Or = DAG.getNode(ISD::OR, DL, VT, ShiftLeftHi, ShiftRightLo); 2492 SDValue ShiftRightHi = DAG.getNode(IsSRA ? ISD::SRA : ISD::SRL, 2493 DL, VT, Hi, Shamt); 2494 SDValue Cond = DAG.getNode(ISD::AND, DL, MVT::i32, Shamt, 2495 DAG.getConstant(VT.getSizeInBits(), DL, MVT::i32)); 2496 SDValue Ext = DAG.getNode(ISD::SRA, DL, VT, Hi, 2497 DAG.getConstant(VT.getSizeInBits() - 1, DL, VT)); 2498 Lo = DAG.getNode(ISD::SELECT, DL, VT, Cond, ShiftRightHi, Or); 2499 Hi = DAG.getNode(ISD::SELECT, DL, VT, Cond, 2500 IsSRA ? Ext : DAG.getConstant(0, DL, VT), ShiftRightHi); 2501 2502 SDValue Ops[2] = {Lo, Hi}; 2503 return DAG.getMergeValues(Ops, DL); 2504 } 2505 2506 static SDValue createLoadLR(unsigned Opc, SelectionDAG &DAG, LoadSDNode *LD, 2507 SDValue Chain, SDValue Src, unsigned Offset) { 2508 SDValue Ptr = LD->getBasePtr(); 2509 EVT VT = LD->getValueType(0), MemVT = LD->getMemoryVT(); 2510 EVT BasePtrVT = Ptr.getValueType(); 2511 SDLoc DL(LD); 2512 SDVTList VTList = DAG.getVTList(VT, MVT::Other); 2513 2514 if (Offset) 2515 Ptr = DAG.getNode(ISD::ADD, DL, BasePtrVT, Ptr, 2516 DAG.getConstant(Offset, DL, BasePtrVT)); 2517 2518 SDValue Ops[] = { Chain, Ptr, Src }; 2519 return DAG.getMemIntrinsicNode(Opc, DL, VTList, Ops, MemVT, 2520 LD->getMemOperand()); 2521 } 2522 2523 // Expand an unaligned 32 or 64-bit integer load node. 2524 SDValue MipsTargetLowering::lowerLOAD(SDValue Op, SelectionDAG &DAG) const { 2525 LoadSDNode *LD = cast<LoadSDNode>(Op); 2526 EVT MemVT = LD->getMemoryVT(); 2527 2528 if (Subtarget.systemSupportsUnalignedAccess()) 2529 return Op; 2530 2531 // Return if load is aligned or if MemVT is neither i32 nor i64. 2532 if ((LD->getAlignment() >= MemVT.getSizeInBits() / 8) || 2533 ((MemVT != MVT::i32) && (MemVT != MVT::i64))) 2534 return SDValue(); 2535 2536 bool IsLittle = Subtarget.isLittle(); 2537 EVT VT = Op.getValueType(); 2538 ISD::LoadExtType ExtType = LD->getExtensionType(); 2539 SDValue Chain = LD->getChain(), Undef = DAG.getUNDEF(VT); 2540 2541 assert((VT == MVT::i32) || (VT == MVT::i64)); 2542 2543 // Expand 2544 // (set dst, (i64 (load baseptr))) 2545 // to 2546 // (set tmp, (ldl (add baseptr, 7), undef)) 2547 // (set dst, (ldr baseptr, tmp)) 2548 if ((VT == MVT::i64) && (ExtType == ISD::NON_EXTLOAD)) { 2549 SDValue LDL = createLoadLR(MipsISD::LDL, DAG, LD, Chain, Undef, 2550 IsLittle ? 7 : 0); 2551 return createLoadLR(MipsISD::LDR, DAG, LD, LDL.getValue(1), LDL, 2552 IsLittle ? 0 : 7); 2553 } 2554 2555 SDValue LWL = createLoadLR(MipsISD::LWL, DAG, LD, Chain, Undef, 2556 IsLittle ? 3 : 0); 2557 SDValue LWR = createLoadLR(MipsISD::LWR, DAG, LD, LWL.getValue(1), LWL, 2558 IsLittle ? 0 : 3); 2559 2560 // Expand 2561 // (set dst, (i32 (load baseptr))) or 2562 // (set dst, (i64 (sextload baseptr))) or 2563 // (set dst, (i64 (extload baseptr))) 2564 // to 2565 // (set tmp, (lwl (add baseptr, 3), undef)) 2566 // (set dst, (lwr baseptr, tmp)) 2567 if ((VT == MVT::i32) || (ExtType == ISD::SEXTLOAD) || 2568 (ExtType == ISD::EXTLOAD)) 2569 return LWR; 2570 2571 assert((VT == MVT::i64) && (ExtType == ISD::ZEXTLOAD)); 2572 2573 // Expand 2574 // (set dst, (i64 (zextload baseptr))) 2575 // to 2576 // (set tmp0, (lwl (add baseptr, 3), undef)) 2577 // (set tmp1, (lwr baseptr, tmp0)) 2578 // (set tmp2, (shl tmp1, 32)) 2579 // (set dst, (srl tmp2, 32)) 2580 SDLoc DL(LD); 2581 SDValue Const32 = DAG.getConstant(32, DL, MVT::i32); 2582 SDValue SLL = DAG.getNode(ISD::SHL, DL, MVT::i64, LWR, Const32); 2583 SDValue SRL = DAG.getNode(ISD::SRL, DL, MVT::i64, SLL, Const32); 2584 SDValue Ops[] = { SRL, LWR.getValue(1) }; 2585 return DAG.getMergeValues(Ops, DL); 2586 } 2587 2588 static SDValue createStoreLR(unsigned Opc, SelectionDAG &DAG, StoreSDNode *SD, 2589 SDValue Chain, unsigned Offset) { 2590 SDValue Ptr = SD->getBasePtr(), Value = SD->getValue(); 2591 EVT MemVT = SD->getMemoryVT(), BasePtrVT = Ptr.getValueType(); 2592 SDLoc DL(SD); 2593 SDVTList VTList = DAG.getVTList(MVT::Other); 2594 2595 if (Offset) 2596 Ptr = DAG.getNode(ISD::ADD, DL, BasePtrVT, Ptr, 2597 DAG.getConstant(Offset, DL, BasePtrVT)); 2598 2599 SDValue Ops[] = { Chain, Value, Ptr }; 2600 return DAG.getMemIntrinsicNode(Opc, DL, VTList, Ops, MemVT, 2601 SD->getMemOperand()); 2602 } 2603 2604 // Expand an unaligned 32 or 64-bit integer store node. 2605 static SDValue lowerUnalignedIntStore(StoreSDNode *SD, SelectionDAG &DAG, 2606 bool IsLittle) { 2607 SDValue Value = SD->getValue(), Chain = SD->getChain(); 2608 EVT VT = Value.getValueType(); 2609 2610 // Expand 2611 // (store val, baseptr) or 2612 // (truncstore val, baseptr) 2613 // to 2614 // (swl val, (add baseptr, 3)) 2615 // (swr val, baseptr) 2616 if ((VT == MVT::i32) || SD->isTruncatingStore()) { 2617 SDValue SWL = createStoreLR(MipsISD::SWL, DAG, SD, Chain, 2618 IsLittle ? 3 : 0); 2619 return createStoreLR(MipsISD::SWR, DAG, SD, SWL, IsLittle ? 0 : 3); 2620 } 2621 2622 assert(VT == MVT::i64); 2623 2624 // Expand 2625 // (store val, baseptr) 2626 // to 2627 // (sdl val, (add baseptr, 7)) 2628 // (sdr val, baseptr) 2629 SDValue SDL = createStoreLR(MipsISD::SDL, DAG, SD, Chain, IsLittle ? 7 : 0); 2630 return createStoreLR(MipsISD::SDR, DAG, SD, SDL, IsLittle ? 0 : 7); 2631 } 2632 2633 // Lower (store (fp_to_sint $fp) $ptr) to (store (TruncIntFP $fp), $ptr). 2634 static SDValue lowerFP_TO_SINT_STORE(StoreSDNode *SD, SelectionDAG &DAG) { 2635 SDValue Val = SD->getValue(); 2636 2637 if (Val.getOpcode() != ISD::FP_TO_SINT) 2638 return SDValue(); 2639 2640 EVT FPTy = EVT::getFloatingPointVT(Val.getValueSizeInBits()); 2641 SDValue Tr = DAG.getNode(MipsISD::TruncIntFP, SDLoc(Val), FPTy, 2642 Val.getOperand(0)); 2643 return DAG.getStore(SD->getChain(), SDLoc(SD), Tr, SD->getBasePtr(), 2644 SD->getPointerInfo(), SD->getAlignment(), 2645 SD->getMemOperand()->getFlags()); 2646 } 2647 2648 SDValue MipsTargetLowering::lowerSTORE(SDValue Op, SelectionDAG &DAG) const { 2649 StoreSDNode *SD = cast<StoreSDNode>(Op); 2650 EVT MemVT = SD->getMemoryVT(); 2651 2652 // Lower unaligned integer stores. 2653 if (!Subtarget.systemSupportsUnalignedAccess() && 2654 (SD->getAlignment() < MemVT.getSizeInBits() / 8) && 2655 ((MemVT == MVT::i32) || (MemVT == MVT::i64))) 2656 return lowerUnalignedIntStore(SD, DAG, Subtarget.isLittle()); 2657 2658 return lowerFP_TO_SINT_STORE(SD, DAG); 2659 } 2660 2661 SDValue MipsTargetLowering::lowerEH_DWARF_CFA(SDValue Op, 2662 SelectionDAG &DAG) const { 2663 2664 // Return a fixed StackObject with offset 0 which points to the old stack 2665 // pointer. 2666 MachineFrameInfo &MFI = DAG.getMachineFunction().getFrameInfo(); 2667 EVT ValTy = Op->getValueType(0); 2668 int FI = MFI.CreateFixedObject(Op.getValueSizeInBits() / 8, 0, false); 2669 return DAG.getFrameIndex(FI, ValTy); 2670 } 2671 2672 SDValue MipsTargetLowering::lowerFP_TO_SINT(SDValue Op, 2673 SelectionDAG &DAG) const { 2674 EVT FPTy = EVT::getFloatingPointVT(Op.getValueSizeInBits()); 2675 SDValue Trunc = DAG.getNode(MipsISD::TruncIntFP, SDLoc(Op), FPTy, 2676 Op.getOperand(0)); 2677 return DAG.getNode(ISD::BITCAST, SDLoc(Op), Op.getValueType(), Trunc); 2678 } 2679 2680 //===----------------------------------------------------------------------===// 2681 // Calling Convention Implementation 2682 //===----------------------------------------------------------------------===// 2683 2684 //===----------------------------------------------------------------------===// 2685 // TODO: Implement a generic logic using tblgen that can support this. 2686 // Mips O32 ABI rules: 2687 // --- 2688 // i32 - Passed in A0, A1, A2, A3 and stack 2689 // f32 - Only passed in f32 registers if no int reg has been used yet to hold 2690 // an argument. Otherwise, passed in A1, A2, A3 and stack. 2691 // f64 - Only passed in two aliased f32 registers if no int reg has been used 2692 // yet to hold an argument. Otherwise, use A2, A3 and stack. If A1 is 2693 // not used, it must be shadowed. If only A3 is available, shadow it and 2694 // go to stack. 2695 // vXiX - Received as scalarized i32s, passed in A0 - A3 and the stack. 2696 // vXf32 - Passed in either a pair of registers {A0, A1}, {A2, A3} or {A0 - A3} 2697 // with the remainder spilled to the stack. 2698 // vXf64 - Passed in either {A0, A1, A2, A3} or {A2, A3} and in both cases 2699 // spilling the remainder to the stack. 2700 // 2701 // For vararg functions, all arguments are passed in A0, A1, A2, A3 and stack. 2702 //===----------------------------------------------------------------------===// 2703 2704 static bool CC_MipsO32(unsigned ValNo, MVT ValVT, MVT LocVT, 2705 CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, 2706 CCState &State, ArrayRef<MCPhysReg> F64Regs) { 2707 const MipsSubtarget &Subtarget = static_cast<const MipsSubtarget &>( 2708 State.getMachineFunction().getSubtarget()); 2709 2710 static const MCPhysReg IntRegs[] = { Mips::A0, Mips::A1, Mips::A2, Mips::A3 }; 2711 2712 const MipsCCState * MipsState = static_cast<MipsCCState *>(&State); 2713 2714 static const MCPhysReg F32Regs[] = { Mips::F12, Mips::F14 }; 2715 2716 static const MCPhysReg FloatVectorIntRegs[] = { Mips::A0, Mips::A2 }; 2717 2718 // Do not process byval args here. 2719 if (ArgFlags.isByVal()) 2720 return true; 2721 2722 // Promote i8 and i16 2723 if (ArgFlags.isInReg() && !Subtarget.isLittle()) { 2724 if (LocVT == MVT::i8 || LocVT == MVT::i16 || LocVT == MVT::i32) { 2725 LocVT = MVT::i32; 2726 if (ArgFlags.isSExt()) 2727 LocInfo = CCValAssign::SExtUpper; 2728 else if (ArgFlags.isZExt()) 2729 LocInfo = CCValAssign::ZExtUpper; 2730 else 2731 LocInfo = CCValAssign::AExtUpper; 2732 } 2733 } 2734 2735 // Promote i8 and i16 2736 if (LocVT == MVT::i8 || LocVT == MVT::i16) { 2737 LocVT = MVT::i32; 2738 if (ArgFlags.isSExt()) 2739 LocInfo = CCValAssign::SExt; 2740 else if (ArgFlags.isZExt()) 2741 LocInfo = CCValAssign::ZExt; 2742 else 2743 LocInfo = CCValAssign::AExt; 2744 } 2745 2746 unsigned Reg; 2747 2748 // f32 and f64 are allocated in A0, A1, A2, A3 when either of the following 2749 // is true: function is vararg, argument is 3rd or higher, there is previous 2750 // argument which is not f32 or f64. 2751 bool AllocateFloatsInIntReg = State.isVarArg() || ValNo > 1 || 2752 State.getFirstUnallocated(F32Regs) != ValNo; 2753 unsigned OrigAlign = ArgFlags.getOrigAlign(); 2754 bool isI64 = (ValVT == MVT::i32 && OrigAlign == 8); 2755 bool isVectorFloat = MipsState->WasOriginalArgVectorFloat(ValNo); 2756 2757 // The MIPS vector ABI for floats passes them in a pair of registers 2758 if (ValVT == MVT::i32 && isVectorFloat) { 2759 // This is the start of an vector that was scalarized into an unknown number 2760 // of components. It doesn't matter how many there are. Allocate one of the 2761 // notional 8 byte aligned registers which map onto the argument stack, and 2762 // shadow the register lost to alignment requirements. 2763 if (ArgFlags.isSplit()) { 2764 Reg = State.AllocateReg(FloatVectorIntRegs); 2765 if (Reg == Mips::A2) 2766 State.AllocateReg(Mips::A1); 2767 else if (Reg == 0) 2768 State.AllocateReg(Mips::A3); 2769 } else { 2770 // If we're an intermediate component of the split, we can just attempt to 2771 // allocate a register directly. 2772 Reg = State.AllocateReg(IntRegs); 2773 } 2774 } else if (ValVT == MVT::i32 || (ValVT == MVT::f32 && AllocateFloatsInIntReg)) { 2775 Reg = State.AllocateReg(IntRegs); 2776 // If this is the first part of an i64 arg, 2777 // the allocated register must be either A0 or A2. 2778 if (isI64 && (Reg == Mips::A1 || Reg == Mips::A3)) 2779 Reg = State.AllocateReg(IntRegs); 2780 LocVT = MVT::i32; 2781 } else if (ValVT == MVT::f64 && AllocateFloatsInIntReg) { 2782 // Allocate int register and shadow next int register. If first 2783 // available register is Mips::A1 or Mips::A3, shadow it too. 2784 Reg = State.AllocateReg(IntRegs); 2785 if (Reg == Mips::A1 || Reg == Mips::A3) 2786 Reg = State.AllocateReg(IntRegs); 2787 State.AllocateReg(IntRegs); 2788 LocVT = MVT::i32; 2789 } else if (ValVT.isFloatingPoint() && !AllocateFloatsInIntReg) { 2790 // we are guaranteed to find an available float register 2791 if (ValVT == MVT::f32) { 2792 Reg = State.AllocateReg(F32Regs); 2793 // Shadow int register 2794 State.AllocateReg(IntRegs); 2795 } else { 2796 Reg = State.AllocateReg(F64Regs); 2797 // Shadow int registers 2798 unsigned Reg2 = State.AllocateReg(IntRegs); 2799 if (Reg2 == Mips::A1 || Reg2 == Mips::A3) 2800 State.AllocateReg(IntRegs); 2801 State.AllocateReg(IntRegs); 2802 } 2803 } else 2804 llvm_unreachable("Cannot handle this ValVT."); 2805 2806 if (!Reg) { 2807 unsigned Offset = State.AllocateStack(ValVT.getStoreSize(), OrigAlign); 2808 State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo)); 2809 } else 2810 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); 2811 2812 return false; 2813 } 2814 2815 static bool CC_MipsO32_FP32(unsigned ValNo, MVT ValVT, 2816 MVT LocVT, CCValAssign::LocInfo LocInfo, 2817 ISD::ArgFlagsTy ArgFlags, CCState &State) { 2818 static const MCPhysReg F64Regs[] = { Mips::D6, Mips::D7 }; 2819 2820 return CC_MipsO32(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State, F64Regs); 2821 } 2822 2823 static bool CC_MipsO32_FP64(unsigned ValNo, MVT ValVT, 2824 MVT LocVT, CCValAssign::LocInfo LocInfo, 2825 ISD::ArgFlagsTy ArgFlags, CCState &State) { 2826 static const MCPhysReg F64Regs[] = { Mips::D12_64, Mips::D14_64 }; 2827 2828 return CC_MipsO32(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State, F64Regs); 2829 } 2830 2831 static bool CC_MipsO32(unsigned ValNo, MVT ValVT, MVT LocVT, 2832 CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, 2833 CCState &State) LLVM_ATTRIBUTE_UNUSED; 2834 2835 #include "MipsGenCallingConv.inc" 2836 2837 CCAssignFn *MipsTargetLowering::CCAssignFnForCall() const{ 2838 return CC_Mips; 2839 } 2840 2841 CCAssignFn *MipsTargetLowering::CCAssignFnForReturn() const{ 2842 return RetCC_Mips; 2843 } 2844 //===----------------------------------------------------------------------===// 2845 // Call Calling Convention Implementation 2846 //===----------------------------------------------------------------------===// 2847 2848 // Return next O32 integer argument register. 2849 static unsigned getNextIntArgReg(unsigned Reg) { 2850 assert((Reg == Mips::A0) || (Reg == Mips::A2)); 2851 return (Reg == Mips::A0) ? Mips::A1 : Mips::A3; 2852 } 2853 2854 SDValue MipsTargetLowering::passArgOnStack(SDValue StackPtr, unsigned Offset, 2855 SDValue Chain, SDValue Arg, 2856 const SDLoc &DL, bool IsTailCall, 2857 SelectionDAG &DAG) const { 2858 if (!IsTailCall) { 2859 SDValue PtrOff = 2860 DAG.getNode(ISD::ADD, DL, getPointerTy(DAG.getDataLayout()), StackPtr, 2861 DAG.getIntPtrConstant(Offset, DL)); 2862 return DAG.getStore(Chain, DL, Arg, PtrOff, MachinePointerInfo()); 2863 } 2864 2865 MachineFrameInfo &MFI = DAG.getMachineFunction().getFrameInfo(); 2866 int FI = MFI.CreateFixedObject(Arg.getValueSizeInBits() / 8, Offset, false); 2867 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy(DAG.getDataLayout())); 2868 return DAG.getStore(Chain, DL, Arg, FIN, MachinePointerInfo(), 2869 /* Alignment = */ 0, MachineMemOperand::MOVolatile); 2870 } 2871 2872 void MipsTargetLowering:: 2873 getOpndList(SmallVectorImpl<SDValue> &Ops, 2874 std::deque<std::pair<unsigned, SDValue>> &RegsToPass, 2875 bool IsPICCall, bool GlobalOrExternal, bool InternalLinkage, 2876 bool IsCallReloc, CallLoweringInfo &CLI, SDValue Callee, 2877 SDValue Chain) const { 2878 // Insert node "GP copy globalreg" before call to function. 2879 // 2880 // R_MIPS_CALL* operators (emitted when non-internal functions are called 2881 // in PIC mode) allow symbols to be resolved via lazy binding. 2882 // The lazy binding stub requires GP to point to the GOT. 2883 // Note that we don't need GP to point to the GOT for indirect calls 2884 // (when R_MIPS_CALL* is not used for the call) because Mips linker generates 2885 // lazy binding stub for a function only when R_MIPS_CALL* are the only relocs 2886 // used for the function (that is, Mips linker doesn't generate lazy binding 2887 // stub for a function whose address is taken in the program). 2888 if (IsPICCall && !InternalLinkage && IsCallReloc) { 2889 unsigned GPReg = ABI.IsN64() ? Mips::GP_64 : Mips::GP; 2890 EVT Ty = ABI.IsN64() ? MVT::i64 : MVT::i32; 2891 RegsToPass.push_back(std::make_pair(GPReg, getGlobalReg(CLI.DAG, Ty))); 2892 } 2893 2894 // Build a sequence of copy-to-reg nodes chained together with token 2895 // chain and flag operands which copy the outgoing args into registers. 2896 // The InFlag in necessary since all emitted instructions must be 2897 // stuck together. 2898 SDValue InFlag; 2899 2900 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) { 2901 Chain = CLI.DAG.getCopyToReg(Chain, CLI.DL, RegsToPass[i].first, 2902 RegsToPass[i].second, InFlag); 2903 InFlag = Chain.getValue(1); 2904 } 2905 2906 // Add argument registers to the end of the list so that they are 2907 // known live into the call. 2908 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) 2909 Ops.push_back(CLI.DAG.getRegister(RegsToPass[i].first, 2910 RegsToPass[i].second.getValueType())); 2911 2912 // Add a register mask operand representing the call-preserved registers. 2913 const TargetRegisterInfo *TRI = Subtarget.getRegisterInfo(); 2914 const uint32_t *Mask = 2915 TRI->getCallPreservedMask(CLI.DAG.getMachineFunction(), CLI.CallConv); 2916 assert(Mask && "Missing call preserved mask for calling convention"); 2917 if (Subtarget.inMips16HardFloat()) { 2918 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(CLI.Callee)) { 2919 StringRef Sym = G->getGlobal()->getName(); 2920 Function *F = G->getGlobal()->getParent()->getFunction(Sym); 2921 if (F && F->hasFnAttribute("__Mips16RetHelper")) { 2922 Mask = MipsRegisterInfo::getMips16RetHelperMask(); 2923 } 2924 } 2925 } 2926 Ops.push_back(CLI.DAG.getRegisterMask(Mask)); 2927 2928 if (InFlag.getNode()) 2929 Ops.push_back(InFlag); 2930 } 2931 2932 /// LowerCall - functions arguments are copied from virtual regs to 2933 /// (physical regs)/(stack frame), CALLSEQ_START and CALLSEQ_END are emitted. 2934 SDValue 2935 MipsTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI, 2936 SmallVectorImpl<SDValue> &InVals) const { 2937 SelectionDAG &DAG = CLI.DAG; 2938 SDLoc DL = CLI.DL; 2939 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs; 2940 SmallVectorImpl<SDValue> &OutVals = CLI.OutVals; 2941 SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins; 2942 SDValue Chain = CLI.Chain; 2943 SDValue Callee = CLI.Callee; 2944 bool &IsTailCall = CLI.IsTailCall; 2945 CallingConv::ID CallConv = CLI.CallConv; 2946 bool IsVarArg = CLI.IsVarArg; 2947 2948 MachineFunction &MF = DAG.getMachineFunction(); 2949 MachineFrameInfo &MFI = MF.getFrameInfo(); 2950 const TargetFrameLowering *TFL = Subtarget.getFrameLowering(); 2951 MipsFunctionInfo *FuncInfo = MF.getInfo<MipsFunctionInfo>(); 2952 bool IsPIC = isPositionIndependent(); 2953 2954 // Analyze operands of the call, assigning locations to each operand. 2955 SmallVector<CCValAssign, 16> ArgLocs; 2956 MipsCCState CCInfo( 2957 CallConv, IsVarArg, DAG.getMachineFunction(), ArgLocs, *DAG.getContext(), 2958 MipsCCState::getSpecialCallingConvForCallee(Callee.getNode(), Subtarget)); 2959 2960 const ExternalSymbolSDNode *ES = 2961 dyn_cast_or_null<const ExternalSymbolSDNode>(Callee.getNode()); 2962 2963 // There is one case where CALLSEQ_START..CALLSEQ_END can be nested, which 2964 // is during the lowering of a call with a byval argument which produces 2965 // a call to memcpy. For the O32 case, this causes the caller to allocate 2966 // stack space for the reserved argument area for the callee, then recursively 2967 // again for the memcpy call. In the NEWABI case, this doesn't occur as those 2968 // ABIs mandate that the callee allocates the reserved argument area. We do 2969 // still produce nested CALLSEQ_START..CALLSEQ_END with zero space though. 2970 // 2971 // If the callee has a byval argument and memcpy is used, we are mandated 2972 // to already have produced a reserved argument area for the callee for O32. 2973 // Therefore, the reserved argument area can be reused for both calls. 2974 // 2975 // Other cases of calling memcpy cannot have a chain with a CALLSEQ_START 2976 // present, as we have yet to hook that node onto the chain. 2977 // 2978 // Hence, the CALLSEQ_START and CALLSEQ_END nodes can be eliminated in this 2979 // case. GCC does a similar trick, in that wherever possible, it calculates 2980 // the maximum out going argument area (including the reserved area), and 2981 // preallocates the stack space on entrance to the caller. 2982 // 2983 // FIXME: We should do the same for efficency and space. 2984 2985 // Note: The check on the calling convention below must match 2986 // MipsABIInfo::GetCalleeAllocdArgSizeInBytes(). 2987 bool MemcpyInByVal = ES && 2988 StringRef(ES->getSymbol()) == StringRef("memcpy") && 2989 CallConv != CallingConv::Fast && 2990 Chain.getOpcode() == ISD::CALLSEQ_START; 2991 2992 // Allocate the reserved argument area. It seems strange to do this from the 2993 // caller side but removing it breaks the frame size calculation. 2994 unsigned ReservedArgArea = 2995 MemcpyInByVal ? 0 : ABI.GetCalleeAllocdArgSizeInBytes(CallConv); 2996 CCInfo.AllocateStack(ReservedArgArea, 1); 2997 2998 CCInfo.AnalyzeCallOperands(Outs, CC_Mips, CLI.getArgs(), 2999 ES ? ES->getSymbol() : nullptr); 3000 3001 // Get a count of how many bytes are to be pushed on the stack. 3002 unsigned NextStackOffset = CCInfo.getNextStackOffset(); 3003 3004 // Check if it's really possible to do a tail call. Restrict it to functions 3005 // that are part of this compilation unit. 3006 bool InternalLinkage = false; 3007 if (IsTailCall) { 3008 IsTailCall = isEligibleForTailCallOptimization( 3009 CCInfo, NextStackOffset, *MF.getInfo<MipsFunctionInfo>()); 3010 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) { 3011 InternalLinkage = G->getGlobal()->hasInternalLinkage(); 3012 IsTailCall &= (InternalLinkage || G->getGlobal()->hasLocalLinkage() || 3013 G->getGlobal()->hasPrivateLinkage() || 3014 G->getGlobal()->hasHiddenVisibility() || 3015 G->getGlobal()->hasProtectedVisibility()); 3016 } 3017 } 3018 if (!IsTailCall && CLI.CS && CLI.CS.isMustTailCall()) 3019 report_fatal_error("failed to perform tail call elimination on a call " 3020 "site marked musttail"); 3021 3022 if (IsTailCall) 3023 ++NumTailCalls; 3024 3025 // Chain is the output chain of the last Load/Store or CopyToReg node. 3026 // ByValChain is the output chain of the last Memcpy node created for copying 3027 // byval arguments to the stack. 3028 unsigned StackAlignment = TFL->getStackAlignment(); 3029 NextStackOffset = alignTo(NextStackOffset, StackAlignment); 3030 SDValue NextStackOffsetVal = DAG.getIntPtrConstant(NextStackOffset, DL, true); 3031 3032 if (!(IsTailCall || MemcpyInByVal)) 3033 Chain = DAG.getCALLSEQ_START(Chain, NextStackOffset, 0, DL); 3034 3035 SDValue StackPtr = 3036 DAG.getCopyFromReg(Chain, DL, ABI.IsN64() ? Mips::SP_64 : Mips::SP, 3037 getPointerTy(DAG.getDataLayout())); 3038 3039 std::deque<std::pair<unsigned, SDValue>> RegsToPass; 3040 SmallVector<SDValue, 8> MemOpChains; 3041 3042 CCInfo.rewindByValRegsInfo(); 3043 3044 // Walk the register/memloc assignments, inserting copies/loads. 3045 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { 3046 SDValue Arg = OutVals[i]; 3047 CCValAssign &VA = ArgLocs[i]; 3048 MVT ValVT = VA.getValVT(), LocVT = VA.getLocVT(); 3049 ISD::ArgFlagsTy Flags = Outs[i].Flags; 3050 bool UseUpperBits = false; 3051 3052 // ByVal Arg. 3053 if (Flags.isByVal()) { 3054 unsigned FirstByValReg, LastByValReg; 3055 unsigned ByValIdx = CCInfo.getInRegsParamsProcessed(); 3056 CCInfo.getInRegsParamInfo(ByValIdx, FirstByValReg, LastByValReg); 3057 3058 assert(Flags.getByValSize() && 3059 "ByVal args of size 0 should have been ignored by front-end."); 3060 assert(ByValIdx < CCInfo.getInRegsParamsCount()); 3061 assert(!IsTailCall && 3062 "Do not tail-call optimize if there is a byval argument."); 3063 passByValArg(Chain, DL, RegsToPass, MemOpChains, StackPtr, MFI, DAG, Arg, 3064 FirstByValReg, LastByValReg, Flags, Subtarget.isLittle(), 3065 VA); 3066 CCInfo.nextInRegsParam(); 3067 continue; 3068 } 3069 3070 // Promote the value if needed. 3071 switch (VA.getLocInfo()) { 3072 default: 3073 llvm_unreachable("Unknown loc info!"); 3074 case CCValAssign::Full: 3075 if (VA.isRegLoc()) { 3076 if ((ValVT == MVT::f32 && LocVT == MVT::i32) || 3077 (ValVT == MVT::f64 && LocVT == MVT::i64) || 3078 (ValVT == MVT::i64 && LocVT == MVT::f64)) 3079 Arg = DAG.getNode(ISD::BITCAST, DL, LocVT, Arg); 3080 else if (ValVT == MVT::f64 && LocVT == MVT::i32) { 3081 SDValue Lo = DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32, 3082 Arg, DAG.getConstant(0, DL, MVT::i32)); 3083 SDValue Hi = DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32, 3084 Arg, DAG.getConstant(1, DL, MVT::i32)); 3085 if (!Subtarget.isLittle()) 3086 std::swap(Lo, Hi); 3087 unsigned LocRegLo = VA.getLocReg(); 3088 unsigned LocRegHigh = getNextIntArgReg(LocRegLo); 3089 RegsToPass.push_back(std::make_pair(LocRegLo, Lo)); 3090 RegsToPass.push_back(std::make_pair(LocRegHigh, Hi)); 3091 continue; 3092 } 3093 } 3094 break; 3095 case CCValAssign::BCvt: 3096 Arg = DAG.getNode(ISD::BITCAST, DL, LocVT, Arg); 3097 break; 3098 case CCValAssign::SExtUpper: 3099 UseUpperBits = true; 3100 LLVM_FALLTHROUGH; 3101 case CCValAssign::SExt: 3102 Arg = DAG.getNode(ISD::SIGN_EXTEND, DL, LocVT, Arg); 3103 break; 3104 case CCValAssign::ZExtUpper: 3105 UseUpperBits = true; 3106 LLVM_FALLTHROUGH; 3107 case CCValAssign::ZExt: 3108 Arg = DAG.getNode(ISD::ZERO_EXTEND, DL, LocVT, Arg); 3109 break; 3110 case CCValAssign::AExtUpper: 3111 UseUpperBits = true; 3112 LLVM_FALLTHROUGH; 3113 case CCValAssign::AExt: 3114 Arg = DAG.getNode(ISD::ANY_EXTEND, DL, LocVT, Arg); 3115 break; 3116 } 3117 3118 if (UseUpperBits) { 3119 unsigned ValSizeInBits = Outs[i].ArgVT.getSizeInBits(); 3120 unsigned LocSizeInBits = VA.getLocVT().getSizeInBits(); 3121 Arg = DAG.getNode( 3122 ISD::SHL, DL, VA.getLocVT(), Arg, 3123 DAG.getConstant(LocSizeInBits - ValSizeInBits, DL, VA.getLocVT())); 3124 } 3125 3126 // Arguments that can be passed on register must be kept at 3127 // RegsToPass vector 3128 if (VA.isRegLoc()) { 3129 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg)); 3130 continue; 3131 } 3132 3133 // Register can't get to this point... 3134 assert(VA.isMemLoc()); 3135 3136 // emit ISD::STORE whichs stores the 3137 // parameter value to a stack Location 3138 MemOpChains.push_back(passArgOnStack(StackPtr, VA.getLocMemOffset(), 3139 Chain, Arg, DL, IsTailCall, DAG)); 3140 } 3141 3142 // Transform all store nodes into one single node because all store 3143 // nodes are independent of each other. 3144 if (!MemOpChains.empty()) 3145 Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, MemOpChains); 3146 3147 // If the callee is a GlobalAddress/ExternalSymbol node (quite common, every 3148 // direct call is) turn it into a TargetGlobalAddress/TargetExternalSymbol 3149 // node so that legalize doesn't hack it. 3150 3151 EVT Ty = Callee.getValueType(); 3152 bool GlobalOrExternal = false, IsCallReloc = false; 3153 3154 // The long-calls feature is ignored in case of PIC. 3155 // While we do not support -mshared / -mno-shared properly, 3156 // ignore long-calls in case of -mabicalls too. 3157 if (!Subtarget.isABICalls() && !IsPIC) { 3158 // If the function should be called using "long call", 3159 // get its address into a register to prevent using 3160 // of the `jal` instruction for the direct call. 3161 if (auto *N = dyn_cast<ExternalSymbolSDNode>(Callee)) { 3162 if (Subtarget.useLongCalls()) 3163 Callee = Subtarget.hasSym32() 3164 ? getAddrNonPIC(N, SDLoc(N), Ty, DAG) 3165 : getAddrNonPICSym64(N, SDLoc(N), Ty, DAG); 3166 } else if (auto *N = dyn_cast<GlobalAddressSDNode>(Callee)) { 3167 bool UseLongCalls = Subtarget.useLongCalls(); 3168 // If the function has long-call/far/near attribute 3169 // it overrides command line switch pased to the backend. 3170 if (auto *F = dyn_cast<Function>(N->getGlobal())) { 3171 if (F->hasFnAttribute("long-call")) 3172 UseLongCalls = true; 3173 else if (F->hasFnAttribute("short-call")) 3174 UseLongCalls = false; 3175 } 3176 if (UseLongCalls) 3177 Callee = Subtarget.hasSym32() 3178 ? getAddrNonPIC(N, SDLoc(N), Ty, DAG) 3179 : getAddrNonPICSym64(N, SDLoc(N), Ty, DAG); 3180 } 3181 } 3182 3183 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) { 3184 if (IsPIC) { 3185 const GlobalValue *Val = G->getGlobal(); 3186 InternalLinkage = Val->hasInternalLinkage(); 3187 3188 if (InternalLinkage) 3189 Callee = getAddrLocal(G, DL, Ty, DAG, ABI.IsN32() || ABI.IsN64()); 3190 else if (LargeGOT) { 3191 Callee = getAddrGlobalLargeGOT(G, DL, Ty, DAG, MipsII::MO_CALL_HI16, 3192 MipsII::MO_CALL_LO16, Chain, 3193 FuncInfo->callPtrInfo(Val)); 3194 IsCallReloc = true; 3195 } else { 3196 Callee = getAddrGlobal(G, DL, Ty, DAG, MipsII::MO_GOT_CALL, Chain, 3197 FuncInfo->callPtrInfo(Val)); 3198 IsCallReloc = true; 3199 } 3200 } else 3201 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), DL, 3202 getPointerTy(DAG.getDataLayout()), 0, 3203 MipsII::MO_NO_FLAG); 3204 GlobalOrExternal = true; 3205 } 3206 else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) { 3207 const char *Sym = S->getSymbol(); 3208 3209 if (!IsPIC) // static 3210 Callee = DAG.getTargetExternalSymbol( 3211 Sym, getPointerTy(DAG.getDataLayout()), MipsII::MO_NO_FLAG); 3212 else if (LargeGOT) { 3213 Callee = getAddrGlobalLargeGOT(S, DL, Ty, DAG, MipsII::MO_CALL_HI16, 3214 MipsII::MO_CALL_LO16, Chain, 3215 FuncInfo->callPtrInfo(Sym)); 3216 IsCallReloc = true; 3217 } else { // PIC 3218 Callee = getAddrGlobal(S, DL, Ty, DAG, MipsII::MO_GOT_CALL, Chain, 3219 FuncInfo->callPtrInfo(Sym)); 3220 IsCallReloc = true; 3221 } 3222 3223 GlobalOrExternal = true; 3224 } 3225 3226 SmallVector<SDValue, 8> Ops(1, Chain); 3227 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue); 3228 3229 getOpndList(Ops, RegsToPass, IsPIC, GlobalOrExternal, InternalLinkage, 3230 IsCallReloc, CLI, Callee, Chain); 3231 3232 if (IsTailCall) { 3233 MF.getFrameInfo().setHasTailCall(); 3234 return DAG.getNode(MipsISD::TailCall, DL, MVT::Other, Ops); 3235 } 3236 3237 Chain = DAG.getNode(MipsISD::JmpLink, DL, NodeTys, Ops); 3238 SDValue InFlag = Chain.getValue(1); 3239 3240 // Create the CALLSEQ_END node in the case of where it is not a call to 3241 // memcpy. 3242 if (!(MemcpyInByVal)) { 3243 Chain = DAG.getCALLSEQ_END(Chain, NextStackOffsetVal, 3244 DAG.getIntPtrConstant(0, DL, true), InFlag, DL); 3245 InFlag = Chain.getValue(1); 3246 } 3247 3248 // Handle result values, copying them out of physregs into vregs that we 3249 // return. 3250 return LowerCallResult(Chain, InFlag, CallConv, IsVarArg, Ins, DL, DAG, 3251 InVals, CLI); 3252 } 3253 3254 /// LowerCallResult - Lower the result values of a call into the 3255 /// appropriate copies out of appropriate physical registers. 3256 SDValue MipsTargetLowering::LowerCallResult( 3257 SDValue Chain, SDValue InFlag, CallingConv::ID CallConv, bool IsVarArg, 3258 const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &DL, 3259 SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals, 3260 TargetLowering::CallLoweringInfo &CLI) const { 3261 // Assign locations to each value returned by this call. 3262 SmallVector<CCValAssign, 16> RVLocs; 3263 MipsCCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), RVLocs, 3264 *DAG.getContext()); 3265 3266 const ExternalSymbolSDNode *ES = 3267 dyn_cast_or_null<const ExternalSymbolSDNode>(CLI.Callee.getNode()); 3268 CCInfo.AnalyzeCallResult(Ins, RetCC_Mips, CLI.RetTy, 3269 ES ? ES->getSymbol() : nullptr); 3270 3271 // Copy all of the result registers out of their specified physreg. 3272 for (unsigned i = 0; i != RVLocs.size(); ++i) { 3273 CCValAssign &VA = RVLocs[i]; 3274 assert(VA.isRegLoc() && "Can only return in registers!"); 3275 3276 SDValue Val = DAG.getCopyFromReg(Chain, DL, RVLocs[i].getLocReg(), 3277 RVLocs[i].getLocVT(), InFlag); 3278 Chain = Val.getValue(1); 3279 InFlag = Val.getValue(2); 3280 3281 if (VA.isUpperBitsInLoc()) { 3282 unsigned ValSizeInBits = Ins[i].ArgVT.getSizeInBits(); 3283 unsigned LocSizeInBits = VA.getLocVT().getSizeInBits(); 3284 unsigned Shift = 3285 VA.getLocInfo() == CCValAssign::ZExtUpper ? ISD::SRL : ISD::SRA; 3286 Val = DAG.getNode( 3287 Shift, DL, VA.getLocVT(), Val, 3288 DAG.getConstant(LocSizeInBits - ValSizeInBits, DL, VA.getLocVT())); 3289 } 3290 3291 switch (VA.getLocInfo()) { 3292 default: 3293 llvm_unreachable("Unknown loc info!"); 3294 case CCValAssign::Full: 3295 break; 3296 case CCValAssign::BCvt: 3297 Val = DAG.getNode(ISD::BITCAST, DL, VA.getValVT(), Val); 3298 break; 3299 case CCValAssign::AExt: 3300 case CCValAssign::AExtUpper: 3301 Val = DAG.getNode(ISD::TRUNCATE, DL, VA.getValVT(), Val); 3302 break; 3303 case CCValAssign::ZExt: 3304 case CCValAssign::ZExtUpper: 3305 Val = DAG.getNode(ISD::AssertZext, DL, VA.getLocVT(), Val, 3306 DAG.getValueType(VA.getValVT())); 3307 Val = DAG.getNode(ISD::TRUNCATE, DL, VA.getValVT(), Val); 3308 break; 3309 case CCValAssign::SExt: 3310 case CCValAssign::SExtUpper: 3311 Val = DAG.getNode(ISD::AssertSext, DL, VA.getLocVT(), Val, 3312 DAG.getValueType(VA.getValVT())); 3313 Val = DAG.getNode(ISD::TRUNCATE, DL, VA.getValVT(), Val); 3314 break; 3315 } 3316 3317 InVals.push_back(Val); 3318 } 3319 3320 return Chain; 3321 } 3322 3323 static SDValue UnpackFromArgumentSlot(SDValue Val, const CCValAssign &VA, 3324 EVT ArgVT, const SDLoc &DL, 3325 SelectionDAG &DAG) { 3326 MVT LocVT = VA.getLocVT(); 3327 EVT ValVT = VA.getValVT(); 3328 3329 // Shift into the upper bits if necessary. 3330 switch (VA.getLocInfo()) { 3331 default: 3332 break; 3333 case CCValAssign::AExtUpper: 3334 case CCValAssign::SExtUpper: 3335 case CCValAssign::ZExtUpper: { 3336 unsigned ValSizeInBits = ArgVT.getSizeInBits(); 3337 unsigned LocSizeInBits = VA.getLocVT().getSizeInBits(); 3338 unsigned Opcode = 3339 VA.getLocInfo() == CCValAssign::ZExtUpper ? ISD::SRL : ISD::SRA; 3340 Val = DAG.getNode( 3341 Opcode, DL, VA.getLocVT(), Val, 3342 DAG.getConstant(LocSizeInBits - ValSizeInBits, DL, VA.getLocVT())); 3343 break; 3344 } 3345 } 3346 3347 // If this is an value smaller than the argument slot size (32-bit for O32, 3348 // 64-bit for N32/N64), it has been promoted in some way to the argument slot 3349 // size. Extract the value and insert any appropriate assertions regarding 3350 // sign/zero extension. 3351 switch (VA.getLocInfo()) { 3352 default: 3353 llvm_unreachable("Unknown loc info!"); 3354 case CCValAssign::Full: 3355 break; 3356 case CCValAssign::AExtUpper: 3357 case CCValAssign::AExt: 3358 Val = DAG.getNode(ISD::TRUNCATE, DL, ValVT, Val); 3359 break; 3360 case CCValAssign::SExtUpper: 3361 case CCValAssign::SExt: 3362 Val = DAG.getNode(ISD::AssertSext, DL, LocVT, Val, DAG.getValueType(ValVT)); 3363 Val = DAG.getNode(ISD::TRUNCATE, DL, ValVT, Val); 3364 break; 3365 case CCValAssign::ZExtUpper: 3366 case CCValAssign::ZExt: 3367 Val = DAG.getNode(ISD::AssertZext, DL, LocVT, Val, DAG.getValueType(ValVT)); 3368 Val = DAG.getNode(ISD::TRUNCATE, DL, ValVT, Val); 3369 break; 3370 case CCValAssign::BCvt: 3371 Val = DAG.getNode(ISD::BITCAST, DL, ValVT, Val); 3372 break; 3373 } 3374 3375 return Val; 3376 } 3377 3378 //===----------------------------------------------------------------------===// 3379 // Formal Arguments Calling Convention Implementation 3380 //===----------------------------------------------------------------------===// 3381 /// LowerFormalArguments - transform physical registers into virtual registers 3382 /// and generate load operations for arguments places on the stack. 3383 SDValue MipsTargetLowering::LowerFormalArguments( 3384 SDValue Chain, CallingConv::ID CallConv, bool IsVarArg, 3385 const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &DL, 3386 SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const { 3387 MachineFunction &MF = DAG.getMachineFunction(); 3388 MachineFrameInfo &MFI = MF.getFrameInfo(); 3389 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>(); 3390 3391 MipsFI->setVarArgsFrameIndex(0); 3392 3393 // Used with vargs to acumulate store chains. 3394 std::vector<SDValue> OutChains; 3395 3396 // Assign locations to all of the incoming arguments. 3397 SmallVector<CCValAssign, 16> ArgLocs; 3398 MipsCCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), ArgLocs, 3399 *DAG.getContext()); 3400 CCInfo.AllocateStack(ABI.GetCalleeAllocdArgSizeInBytes(CallConv), 1); 3401 const Function &Func = DAG.getMachineFunction().getFunction(); 3402 Function::const_arg_iterator FuncArg = Func.arg_begin(); 3403 3404 if (Func.hasFnAttribute("interrupt") && !Func.arg_empty()) 3405 report_fatal_error( 3406 "Functions with the interrupt attribute cannot have arguments!"); 3407 3408 CCInfo.AnalyzeFormalArguments(Ins, CC_Mips_FixedArg); 3409 MipsFI->setFormalArgInfo(CCInfo.getNextStackOffset(), 3410 CCInfo.getInRegsParamsCount() > 0); 3411 3412 unsigned CurArgIdx = 0; 3413 CCInfo.rewindByValRegsInfo(); 3414 3415 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { 3416 CCValAssign &VA = ArgLocs[i]; 3417 if (Ins[i].isOrigArg()) { 3418 std::advance(FuncArg, Ins[i].getOrigArgIndex() - CurArgIdx); 3419 CurArgIdx = Ins[i].getOrigArgIndex(); 3420 } 3421 EVT ValVT = VA.getValVT(); 3422 ISD::ArgFlagsTy Flags = Ins[i].Flags; 3423 bool IsRegLoc = VA.isRegLoc(); 3424 3425 if (Flags.isByVal()) { 3426 assert(Ins[i].isOrigArg() && "Byval arguments cannot be implicit"); 3427 unsigned FirstByValReg, LastByValReg; 3428 unsigned ByValIdx = CCInfo.getInRegsParamsProcessed(); 3429 CCInfo.getInRegsParamInfo(ByValIdx, FirstByValReg, LastByValReg); 3430 3431 assert(Flags.getByValSize() && 3432 "ByVal args of size 0 should have been ignored by front-end."); 3433 assert(ByValIdx < CCInfo.getInRegsParamsCount()); 3434 copyByValRegs(Chain, DL, OutChains, DAG, Flags, InVals, &*FuncArg, 3435 FirstByValReg, LastByValReg, VA, CCInfo); 3436 CCInfo.nextInRegsParam(); 3437 continue; 3438 } 3439 3440 // Arguments stored on registers 3441 if (IsRegLoc) { 3442 MVT RegVT = VA.getLocVT(); 3443 unsigned ArgReg = VA.getLocReg(); 3444 const TargetRegisterClass *RC = getRegClassFor(RegVT); 3445 3446 // Transform the arguments stored on 3447 // physical registers into virtual ones 3448 unsigned Reg = addLiveIn(DAG.getMachineFunction(), ArgReg, RC); 3449 SDValue ArgValue = DAG.getCopyFromReg(Chain, DL, Reg, RegVT); 3450 3451 ArgValue = UnpackFromArgumentSlot(ArgValue, VA, Ins[i].ArgVT, DL, DAG); 3452 3453 // Handle floating point arguments passed in integer registers and 3454 // long double arguments passed in floating point registers. 3455 if ((RegVT == MVT::i32 && ValVT == MVT::f32) || 3456 (RegVT == MVT::i64 && ValVT == MVT::f64) || 3457 (RegVT == MVT::f64 && ValVT == MVT::i64)) 3458 ArgValue = DAG.getNode(ISD::BITCAST, DL, ValVT, ArgValue); 3459 else if (ABI.IsO32() && RegVT == MVT::i32 && 3460 ValVT == MVT::f64) { 3461 unsigned Reg2 = addLiveIn(DAG.getMachineFunction(), 3462 getNextIntArgReg(ArgReg), RC); 3463 SDValue ArgValue2 = DAG.getCopyFromReg(Chain, DL, Reg2, RegVT); 3464 if (!Subtarget.isLittle()) 3465 std::swap(ArgValue, ArgValue2); 3466 ArgValue = DAG.getNode(MipsISD::BuildPairF64, DL, MVT::f64, 3467 ArgValue, ArgValue2); 3468 } 3469 3470 InVals.push_back(ArgValue); 3471 } else { // VA.isRegLoc() 3472 MVT LocVT = VA.getLocVT(); 3473 3474 if (ABI.IsO32()) { 3475 // We ought to be able to use LocVT directly but O32 sets it to i32 3476 // when allocating floating point values to integer registers. 3477 // This shouldn't influence how we load the value into registers unless 3478 // we are targeting softfloat. 3479 if (VA.getValVT().isFloatingPoint() && !Subtarget.useSoftFloat()) 3480 LocVT = VA.getValVT(); 3481 } 3482 3483 // sanity check 3484 assert(VA.isMemLoc()); 3485 3486 // The stack pointer offset is relative to the caller stack frame. 3487 int FI = MFI.CreateFixedObject(LocVT.getSizeInBits() / 8, 3488 VA.getLocMemOffset(), true); 3489 3490 // Create load nodes to retrieve arguments from the stack 3491 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy(DAG.getDataLayout())); 3492 SDValue ArgValue = DAG.getLoad( 3493 LocVT, DL, Chain, FIN, 3494 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), FI)); 3495 OutChains.push_back(ArgValue.getValue(1)); 3496 3497 ArgValue = UnpackFromArgumentSlot(ArgValue, VA, Ins[i].ArgVT, DL, DAG); 3498 3499 InVals.push_back(ArgValue); 3500 } 3501 } 3502 3503 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { 3504 // The mips ABIs for returning structs by value requires that we copy 3505 // the sret argument into $v0 for the return. Save the argument into 3506 // a virtual register so that we can access it from the return points. 3507 if (Ins[i].Flags.isSRet()) { 3508 unsigned Reg = MipsFI->getSRetReturnReg(); 3509 if (!Reg) { 3510 Reg = MF.getRegInfo().createVirtualRegister( 3511 getRegClassFor(ABI.IsN64() ? MVT::i64 : MVT::i32)); 3512 MipsFI->setSRetReturnReg(Reg); 3513 } 3514 SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), DL, Reg, InVals[i]); 3515 Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, Copy, Chain); 3516 break; 3517 } 3518 } 3519 3520 if (IsVarArg) 3521 writeVarArgRegs(OutChains, Chain, DL, DAG, CCInfo); 3522 3523 // All stores are grouped in one node to allow the matching between 3524 // the size of Ins and InVals. This only happens when on varg functions 3525 if (!OutChains.empty()) { 3526 OutChains.push_back(Chain); 3527 Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, OutChains); 3528 } 3529 3530 return Chain; 3531 } 3532 3533 //===----------------------------------------------------------------------===// 3534 // Return Value Calling Convention Implementation 3535 //===----------------------------------------------------------------------===// 3536 3537 bool 3538 MipsTargetLowering::CanLowerReturn(CallingConv::ID CallConv, 3539 MachineFunction &MF, bool IsVarArg, 3540 const SmallVectorImpl<ISD::OutputArg> &Outs, 3541 LLVMContext &Context) const { 3542 SmallVector<CCValAssign, 16> RVLocs; 3543 MipsCCState CCInfo(CallConv, IsVarArg, MF, RVLocs, Context); 3544 return CCInfo.CheckReturn(Outs, RetCC_Mips); 3545 } 3546 3547 bool 3548 MipsTargetLowering::shouldSignExtendTypeInLibCall(EVT Type, bool IsSigned) const { 3549 if ((ABI.IsN32() || ABI.IsN64()) && Type == MVT::i32) 3550 return true; 3551 3552 return IsSigned; 3553 } 3554 3555 SDValue 3556 MipsTargetLowering::LowerInterruptReturn(SmallVectorImpl<SDValue> &RetOps, 3557 const SDLoc &DL, 3558 SelectionDAG &DAG) const { 3559 MachineFunction &MF = DAG.getMachineFunction(); 3560 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>(); 3561 3562 MipsFI->setISR(); 3563 3564 return DAG.getNode(MipsISD::ERet, DL, MVT::Other, RetOps); 3565 } 3566 3567 SDValue 3568 MipsTargetLowering::LowerReturn(SDValue Chain, CallingConv::ID CallConv, 3569 bool IsVarArg, 3570 const SmallVectorImpl<ISD::OutputArg> &Outs, 3571 const SmallVectorImpl<SDValue> &OutVals, 3572 const SDLoc &DL, SelectionDAG &DAG) const { 3573 // CCValAssign - represent the assignment of 3574 // the return value to a location 3575 SmallVector<CCValAssign, 16> RVLocs; 3576 MachineFunction &MF = DAG.getMachineFunction(); 3577 3578 // CCState - Info about the registers and stack slot. 3579 MipsCCState CCInfo(CallConv, IsVarArg, MF, RVLocs, *DAG.getContext()); 3580 3581 // Analyze return values. 3582 CCInfo.AnalyzeReturn(Outs, RetCC_Mips); 3583 3584 SDValue Flag; 3585 SmallVector<SDValue, 4> RetOps(1, Chain); 3586 3587 // Copy the result values into the output registers. 3588 for (unsigned i = 0; i != RVLocs.size(); ++i) { 3589 SDValue Val = OutVals[i]; 3590 CCValAssign &VA = RVLocs[i]; 3591 assert(VA.isRegLoc() && "Can only return in registers!"); 3592 bool UseUpperBits = false; 3593 3594 switch (VA.getLocInfo()) { 3595 default: 3596 llvm_unreachable("Unknown loc info!"); 3597 case CCValAssign::Full: 3598 break; 3599 case CCValAssign::BCvt: 3600 Val = DAG.getNode(ISD::BITCAST, DL, VA.getLocVT(), Val); 3601 break; 3602 case CCValAssign::AExtUpper: 3603 UseUpperBits = true; 3604 LLVM_FALLTHROUGH; 3605 case CCValAssign::AExt: 3606 Val = DAG.getNode(ISD::ANY_EXTEND, DL, VA.getLocVT(), Val); 3607 break; 3608 case CCValAssign::ZExtUpper: 3609 UseUpperBits = true; 3610 LLVM_FALLTHROUGH; 3611 case CCValAssign::ZExt: 3612 Val = DAG.getNode(ISD::ZERO_EXTEND, DL, VA.getLocVT(), Val); 3613 break; 3614 case CCValAssign::SExtUpper: 3615 UseUpperBits = true; 3616 LLVM_FALLTHROUGH; 3617 case CCValAssign::SExt: 3618 Val = DAG.getNode(ISD::SIGN_EXTEND, DL, VA.getLocVT(), Val); 3619 break; 3620 } 3621 3622 if (UseUpperBits) { 3623 unsigned ValSizeInBits = Outs[i].ArgVT.getSizeInBits(); 3624 unsigned LocSizeInBits = VA.getLocVT().getSizeInBits(); 3625 Val = DAG.getNode( 3626 ISD::SHL, DL, VA.getLocVT(), Val, 3627 DAG.getConstant(LocSizeInBits - ValSizeInBits, DL, VA.getLocVT())); 3628 } 3629 3630 Chain = DAG.getCopyToReg(Chain, DL, VA.getLocReg(), Val, Flag); 3631 3632 // Guarantee that all emitted copies are stuck together with flags. 3633 Flag = Chain.getValue(1); 3634 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT())); 3635 } 3636 3637 // The mips ABIs for returning structs by value requires that we copy 3638 // the sret argument into $v0 for the return. We saved the argument into 3639 // a virtual register in the entry block, so now we copy the value out 3640 // and into $v0. 3641 if (MF.getFunction().hasStructRetAttr()) { 3642 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>(); 3643 unsigned Reg = MipsFI->getSRetReturnReg(); 3644 3645 if (!Reg) 3646 llvm_unreachable("sret virtual register not created in the entry block"); 3647 SDValue Val = 3648 DAG.getCopyFromReg(Chain, DL, Reg, getPointerTy(DAG.getDataLayout())); 3649 unsigned V0 = ABI.IsN64() ? Mips::V0_64 : Mips::V0; 3650 3651 Chain = DAG.getCopyToReg(Chain, DL, V0, Val, Flag); 3652 Flag = Chain.getValue(1); 3653 RetOps.push_back(DAG.getRegister(V0, getPointerTy(DAG.getDataLayout()))); 3654 } 3655 3656 RetOps[0] = Chain; // Update chain. 3657 3658 // Add the flag if we have it. 3659 if (Flag.getNode()) 3660 RetOps.push_back(Flag); 3661 3662 // ISRs must use "eret". 3663 if (DAG.getMachineFunction().getFunction().hasFnAttribute("interrupt")) 3664 return LowerInterruptReturn(RetOps, DL, DAG); 3665 3666 // Standard return on Mips is a "jr $ra" 3667 return DAG.getNode(MipsISD::Ret, DL, MVT::Other, RetOps); 3668 } 3669 3670 //===----------------------------------------------------------------------===// 3671 // Mips Inline Assembly Support 3672 //===----------------------------------------------------------------------===// 3673 3674 /// getConstraintType - Given a constraint letter, return the type of 3675 /// constraint it is for this target. 3676 MipsTargetLowering::ConstraintType 3677 MipsTargetLowering::getConstraintType(StringRef Constraint) const { 3678 // Mips specific constraints 3679 // GCC config/mips/constraints.md 3680 // 3681 // 'd' : An address register. Equivalent to r 3682 // unless generating MIPS16 code. 3683 // 'y' : Equivalent to r; retained for 3684 // backwards compatibility. 3685 // 'c' : A register suitable for use in an indirect 3686 // jump. This will always be $25 for -mabicalls. 3687 // 'l' : The lo register. 1 word storage. 3688 // 'x' : The hilo register pair. Double word storage. 3689 if (Constraint.size() == 1) { 3690 switch (Constraint[0]) { 3691 default : break; 3692 case 'd': 3693 case 'y': 3694 case 'f': 3695 case 'c': 3696 case 'l': 3697 case 'x': 3698 return C_RegisterClass; 3699 case 'R': 3700 return C_Memory; 3701 } 3702 } 3703 3704 if (Constraint == "ZC") 3705 return C_Memory; 3706 3707 return TargetLowering::getConstraintType(Constraint); 3708 } 3709 3710 /// Examine constraint type and operand type and determine a weight value. 3711 /// This object must already have been set up with the operand type 3712 /// and the current alternative constraint selected. 3713 TargetLowering::ConstraintWeight 3714 MipsTargetLowering::getSingleConstraintMatchWeight( 3715 AsmOperandInfo &info, const char *constraint) const { 3716 ConstraintWeight weight = CW_Invalid; 3717 Value *CallOperandVal = info.CallOperandVal; 3718 // If we don't have a value, we can't do a match, 3719 // but allow it at the lowest weight. 3720 if (!CallOperandVal) 3721 return CW_Default; 3722 Type *type = CallOperandVal->getType(); 3723 // Look at the constraint type. 3724 switch (*constraint) { 3725 default: 3726 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint); 3727 break; 3728 case 'd': 3729 case 'y': 3730 if (type->isIntegerTy()) 3731 weight = CW_Register; 3732 break; 3733 case 'f': // FPU or MSA register 3734 if (Subtarget.hasMSA() && type->isVectorTy() && 3735 cast<VectorType>(type)->getBitWidth() == 128) 3736 weight = CW_Register; 3737 else if (type->isFloatTy()) 3738 weight = CW_Register; 3739 break; 3740 case 'c': // $25 for indirect jumps 3741 case 'l': // lo register 3742 case 'x': // hilo register pair 3743 if (type->isIntegerTy()) 3744 weight = CW_SpecificReg; 3745 break; 3746 case 'I': // signed 16 bit immediate 3747 case 'J': // integer zero 3748 case 'K': // unsigned 16 bit immediate 3749 case 'L': // signed 32 bit immediate where lower 16 bits are 0 3750 case 'N': // immediate in the range of -65535 to -1 (inclusive) 3751 case 'O': // signed 15 bit immediate (+- 16383) 3752 case 'P': // immediate in the range of 65535 to 1 (inclusive) 3753 if (isa<ConstantInt>(CallOperandVal)) 3754 weight = CW_Constant; 3755 break; 3756 case 'R': 3757 weight = CW_Memory; 3758 break; 3759 } 3760 return weight; 3761 } 3762 3763 /// This is a helper function to parse a physical register string and split it 3764 /// into non-numeric and numeric parts (Prefix and Reg). The first boolean flag 3765 /// that is returned indicates whether parsing was successful. The second flag 3766 /// is true if the numeric part exists. 3767 static std::pair<bool, bool> parsePhysicalReg(StringRef C, StringRef &Prefix, 3768 unsigned long long &Reg) { 3769 if (C.front() != '{' || C.back() != '}') 3770 return std::make_pair(false, false); 3771 3772 // Search for the first numeric character. 3773 StringRef::const_iterator I, B = C.begin() + 1, E = C.end() - 1; 3774 I = std::find_if(B, E, isdigit); 3775 3776 Prefix = StringRef(B, I - B); 3777 3778 // The second flag is set to false if no numeric characters were found. 3779 if (I == E) 3780 return std::make_pair(true, false); 3781 3782 // Parse the numeric characters. 3783 return std::make_pair(!getAsUnsignedInteger(StringRef(I, E - I), 10, Reg), 3784 true); 3785 } 3786 3787 std::pair<unsigned, const TargetRegisterClass *> MipsTargetLowering:: 3788 parseRegForInlineAsmConstraint(StringRef C, MVT VT) const { 3789 const TargetRegisterInfo *TRI = 3790 Subtarget.getRegisterInfo(); 3791 const TargetRegisterClass *RC; 3792 StringRef Prefix; 3793 unsigned long long Reg; 3794 3795 std::pair<bool, bool> R = parsePhysicalReg(C, Prefix, Reg); 3796 3797 if (!R.first) 3798 return std::make_pair(0U, nullptr); 3799 3800 if ((Prefix == "hi" || Prefix == "lo")) { // Parse hi/lo. 3801 // No numeric characters follow "hi" or "lo". 3802 if (R.second) 3803 return std::make_pair(0U, nullptr); 3804 3805 RC = TRI->getRegClass(Prefix == "hi" ? 3806 Mips::HI32RegClassID : Mips::LO32RegClassID); 3807 return std::make_pair(*(RC->begin()), RC); 3808 } else if (Prefix.startswith("$msa")) { 3809 // Parse $msa(ir|csr|access|save|modify|request|map|unmap) 3810 3811 // No numeric characters follow the name. 3812 if (R.second) 3813 return std::make_pair(0U, nullptr); 3814 3815 Reg = StringSwitch<unsigned long long>(Prefix) 3816 .Case("$msair", Mips::MSAIR) 3817 .Case("$msacsr", Mips::MSACSR) 3818 .Case("$msaaccess", Mips::MSAAccess) 3819 .Case("$msasave", Mips::MSASave) 3820 .Case("$msamodify", Mips::MSAModify) 3821 .Case("$msarequest", Mips::MSARequest) 3822 .Case("$msamap", Mips::MSAMap) 3823 .Case("$msaunmap", Mips::MSAUnmap) 3824 .Default(0); 3825 3826 if (!Reg) 3827 return std::make_pair(0U, nullptr); 3828 3829 RC = TRI->getRegClass(Mips::MSACtrlRegClassID); 3830 return std::make_pair(Reg, RC); 3831 } 3832 3833 if (!R.second) 3834 return std::make_pair(0U, nullptr); 3835 3836 if (Prefix == "$f") { // Parse $f0-$f31. 3837 // If the size of FP registers is 64-bit or Reg is an even number, select 3838 // the 64-bit register class. Otherwise, select the 32-bit register class. 3839 if (VT == MVT::Other) 3840 VT = (Subtarget.isFP64bit() || !(Reg % 2)) ? MVT::f64 : MVT::f32; 3841 3842 RC = getRegClassFor(VT); 3843 3844 if (RC == &Mips::AFGR64RegClass) { 3845 assert(Reg % 2 == 0); 3846 Reg >>= 1; 3847 } 3848 } else if (Prefix == "$fcc") // Parse $fcc0-$fcc7. 3849 RC = TRI->getRegClass(Mips::FCCRegClassID); 3850 else if (Prefix == "$w") { // Parse $w0-$w31. 3851 RC = getRegClassFor((VT == MVT::Other) ? MVT::v16i8 : VT); 3852 } else { // Parse $0-$31. 3853 assert(Prefix == "$"); 3854 RC = getRegClassFor((VT == MVT::Other) ? MVT::i32 : VT); 3855 } 3856 3857 assert(Reg < RC->getNumRegs()); 3858 return std::make_pair(*(RC->begin() + Reg), RC); 3859 } 3860 3861 /// Given a register class constraint, like 'r', if this corresponds directly 3862 /// to an LLVM register class, return a register of 0 and the register class 3863 /// pointer. 3864 std::pair<unsigned, const TargetRegisterClass *> 3865 MipsTargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, 3866 StringRef Constraint, 3867 MVT VT) const { 3868 if (Constraint.size() == 1) { 3869 switch (Constraint[0]) { 3870 case 'd': // Address register. Same as 'r' unless generating MIPS16 code. 3871 case 'y': // Same as 'r'. Exists for compatibility. 3872 case 'r': 3873 if (VT == MVT::i32 || VT == MVT::i16 || VT == MVT::i8) { 3874 if (Subtarget.inMips16Mode()) 3875 return std::make_pair(0U, &Mips::CPU16RegsRegClass); 3876 return std::make_pair(0U, &Mips::GPR32RegClass); 3877 } 3878 if (VT == MVT::i64 && !Subtarget.isGP64bit()) 3879 return std::make_pair(0U, &Mips::GPR32RegClass); 3880 if (VT == MVT::i64 && Subtarget.isGP64bit()) 3881 return std::make_pair(0U, &Mips::GPR64RegClass); 3882 // This will generate an error message 3883 return std::make_pair(0U, nullptr); 3884 case 'f': // FPU or MSA register 3885 if (VT == MVT::v16i8) 3886 return std::make_pair(0U, &Mips::MSA128BRegClass); 3887 else if (VT == MVT::v8i16 || VT == MVT::v8f16) 3888 return std::make_pair(0U, &Mips::MSA128HRegClass); 3889 else if (VT == MVT::v4i32 || VT == MVT::v4f32) 3890 return std::make_pair(0U, &Mips::MSA128WRegClass); 3891 else if (VT == MVT::v2i64 || VT == MVT::v2f64) 3892 return std::make_pair(0U, &Mips::MSA128DRegClass); 3893 else if (VT == MVT::f32) 3894 return std::make_pair(0U, &Mips::FGR32RegClass); 3895 else if ((VT == MVT::f64) && (!Subtarget.isSingleFloat())) { 3896 if (Subtarget.isFP64bit()) 3897 return std::make_pair(0U, &Mips::FGR64RegClass); 3898 return std::make_pair(0U, &Mips::AFGR64RegClass); 3899 } 3900 break; 3901 case 'c': // register suitable for indirect jump 3902 if (VT == MVT::i32) 3903 return std::make_pair((unsigned)Mips::T9, &Mips::GPR32RegClass); 3904 if (VT == MVT::i64) 3905 return std::make_pair((unsigned)Mips::T9_64, &Mips::GPR64RegClass); 3906 // This will generate an error message 3907 return std::make_pair(0U, nullptr); 3908 case 'l': // use the `lo` register to store values 3909 // that are no bigger than a word 3910 if (VT == MVT::i32 || VT == MVT::i16 || VT == MVT::i8) 3911 return std::make_pair((unsigned)Mips::LO0, &Mips::LO32RegClass); 3912 return std::make_pair((unsigned)Mips::LO0_64, &Mips::LO64RegClass); 3913 case 'x': // use the concatenated `hi` and `lo` registers 3914 // to store doubleword values 3915 // Fixme: Not triggering the use of both hi and low 3916 // This will generate an error message 3917 return std::make_pair(0U, nullptr); 3918 } 3919 } 3920 3921 std::pair<unsigned, const TargetRegisterClass *> R; 3922 R = parseRegForInlineAsmConstraint(Constraint, VT); 3923 3924 if (R.second) 3925 return R; 3926 3927 return TargetLowering::getRegForInlineAsmConstraint(TRI, Constraint, VT); 3928 } 3929 3930 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops 3931 /// vector. If it is invalid, don't add anything to Ops. 3932 void MipsTargetLowering::LowerAsmOperandForConstraint(SDValue Op, 3933 std::string &Constraint, 3934 std::vector<SDValue>&Ops, 3935 SelectionDAG &DAG) const { 3936 SDLoc DL(Op); 3937 SDValue Result; 3938 3939 // Only support length 1 constraints for now. 3940 if (Constraint.length() > 1) return; 3941 3942 char ConstraintLetter = Constraint[0]; 3943 switch (ConstraintLetter) { 3944 default: break; // This will fall through to the generic implementation 3945 case 'I': // Signed 16 bit constant 3946 // If this fails, the parent routine will give an error 3947 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 3948 EVT Type = Op.getValueType(); 3949 int64_t Val = C->getSExtValue(); 3950 if (isInt<16>(Val)) { 3951 Result = DAG.getTargetConstant(Val, DL, Type); 3952 break; 3953 } 3954 } 3955 return; 3956 case 'J': // integer zero 3957 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 3958 EVT Type = Op.getValueType(); 3959 int64_t Val = C->getZExtValue(); 3960 if (Val == 0) { 3961 Result = DAG.getTargetConstant(0, DL, Type); 3962 break; 3963 } 3964 } 3965 return; 3966 case 'K': // unsigned 16 bit immediate 3967 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 3968 EVT Type = Op.getValueType(); 3969 uint64_t Val = (uint64_t)C->getZExtValue(); 3970 if (isUInt<16>(Val)) { 3971 Result = DAG.getTargetConstant(Val, DL, Type); 3972 break; 3973 } 3974 } 3975 return; 3976 case 'L': // signed 32 bit immediate where lower 16 bits are 0 3977 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 3978 EVT Type = Op.getValueType(); 3979 int64_t Val = C->getSExtValue(); 3980 if ((isInt<32>(Val)) && ((Val & 0xffff) == 0)){ 3981 Result = DAG.getTargetConstant(Val, DL, Type); 3982 break; 3983 } 3984 } 3985 return; 3986 case 'N': // immediate in the range of -65535 to -1 (inclusive) 3987 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 3988 EVT Type = Op.getValueType(); 3989 int64_t Val = C->getSExtValue(); 3990 if ((Val >= -65535) && (Val <= -1)) { 3991 Result = DAG.getTargetConstant(Val, DL, Type); 3992 break; 3993 } 3994 } 3995 return; 3996 case 'O': // signed 15 bit immediate 3997 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 3998 EVT Type = Op.getValueType(); 3999 int64_t Val = C->getSExtValue(); 4000 if ((isInt<15>(Val))) { 4001 Result = DAG.getTargetConstant(Val, DL, Type); 4002 break; 4003 } 4004 } 4005 return; 4006 case 'P': // immediate in the range of 1 to 65535 (inclusive) 4007 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 4008 EVT Type = Op.getValueType(); 4009 int64_t Val = C->getSExtValue(); 4010 if ((Val <= 65535) && (Val >= 1)) { 4011 Result = DAG.getTargetConstant(Val, DL, Type); 4012 break; 4013 } 4014 } 4015 return; 4016 } 4017 4018 if (Result.getNode()) { 4019 Ops.push_back(Result); 4020 return; 4021 } 4022 4023 TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG); 4024 } 4025 4026 bool MipsTargetLowering::isLegalAddressingMode(const DataLayout &DL, 4027 const AddrMode &AM, Type *Ty, 4028 unsigned AS, Instruction *I) const { 4029 // No global is ever allowed as a base. 4030 if (AM.BaseGV) 4031 return false; 4032 4033 switch (AM.Scale) { 4034 case 0: // "r+i" or just "i", depending on HasBaseReg. 4035 break; 4036 case 1: 4037 if (!AM.HasBaseReg) // allow "r+i". 4038 break; 4039 return false; // disallow "r+r" or "r+r+i". 4040 default: 4041 return false; 4042 } 4043 4044 return true; 4045 } 4046 4047 bool 4048 MipsTargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const { 4049 // The Mips target isn't yet aware of offsets. 4050 return false; 4051 } 4052 4053 EVT MipsTargetLowering::getOptimalMemOpType(uint64_t Size, unsigned DstAlign, 4054 unsigned SrcAlign, 4055 bool IsMemset, bool ZeroMemset, 4056 bool MemcpyStrSrc, 4057 MachineFunction &MF) const { 4058 if (Subtarget.hasMips64()) 4059 return MVT::i64; 4060 4061 return MVT::i32; 4062 } 4063 4064 bool MipsTargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const { 4065 if (VT != MVT::f32 && VT != MVT::f64) 4066 return false; 4067 if (Imm.isNegZero()) 4068 return false; 4069 return Imm.isZero(); 4070 } 4071 4072 unsigned MipsTargetLowering::getJumpTableEncoding() const { 4073 4074 // FIXME: For space reasons this should be: EK_GPRel32BlockAddress. 4075 if (ABI.IsN64() && isPositionIndependent()) 4076 return MachineJumpTableInfo::EK_GPRel64BlockAddress; 4077 4078 return TargetLowering::getJumpTableEncoding(); 4079 } 4080 4081 bool MipsTargetLowering::useSoftFloat() const { 4082 return Subtarget.useSoftFloat(); 4083 } 4084 4085 void MipsTargetLowering::copyByValRegs( 4086 SDValue Chain, const SDLoc &DL, std::vector<SDValue> &OutChains, 4087 SelectionDAG &DAG, const ISD::ArgFlagsTy &Flags, 4088 SmallVectorImpl<SDValue> &InVals, const Argument *FuncArg, 4089 unsigned FirstReg, unsigned LastReg, const CCValAssign &VA, 4090 MipsCCState &State) const { 4091 MachineFunction &MF = DAG.getMachineFunction(); 4092 MachineFrameInfo &MFI = MF.getFrameInfo(); 4093 unsigned GPRSizeInBytes = Subtarget.getGPRSizeInBytes(); 4094 unsigned NumRegs = LastReg - FirstReg; 4095 unsigned RegAreaSize = NumRegs * GPRSizeInBytes; 4096 unsigned FrameObjSize = std::max(Flags.getByValSize(), RegAreaSize); 4097 int FrameObjOffset; 4098 ArrayRef<MCPhysReg> ByValArgRegs = ABI.GetByValArgRegs(); 4099 4100 if (RegAreaSize) 4101 FrameObjOffset = 4102 (int)ABI.GetCalleeAllocdArgSizeInBytes(State.getCallingConv()) - 4103 (int)((ByValArgRegs.size() - FirstReg) * GPRSizeInBytes); 4104 else 4105 FrameObjOffset = VA.getLocMemOffset(); 4106 4107 // Create frame object. 4108 EVT PtrTy = getPointerTy(DAG.getDataLayout()); 4109 // Make the fixed object stored to mutable so that the load instructions 4110 // referencing it have their memory dependencies added. 4111 // Set the frame object as isAliased which clears the underlying objects 4112 // vector in ScheduleDAGInstrs::buildSchedGraph() resulting in addition of all 4113 // stores as dependencies for loads referencing this fixed object. 4114 int FI = MFI.CreateFixedObject(FrameObjSize, FrameObjOffset, false, true); 4115 SDValue FIN = DAG.getFrameIndex(FI, PtrTy); 4116 InVals.push_back(FIN); 4117 4118 if (!NumRegs) 4119 return; 4120 4121 // Copy arg registers. 4122 MVT RegTy = MVT::getIntegerVT(GPRSizeInBytes * 8); 4123 const TargetRegisterClass *RC = getRegClassFor(RegTy); 4124 4125 for (unsigned I = 0; I < NumRegs; ++I) { 4126 unsigned ArgReg = ByValArgRegs[FirstReg + I]; 4127 unsigned VReg = addLiveIn(MF, ArgReg, RC); 4128 unsigned Offset = I * GPRSizeInBytes; 4129 SDValue StorePtr = DAG.getNode(ISD::ADD, DL, PtrTy, FIN, 4130 DAG.getConstant(Offset, DL, PtrTy)); 4131 SDValue Store = DAG.getStore(Chain, DL, DAG.getRegister(VReg, RegTy), 4132 StorePtr, MachinePointerInfo(FuncArg, Offset)); 4133 OutChains.push_back(Store); 4134 } 4135 } 4136 4137 // Copy byVal arg to registers and stack. 4138 void MipsTargetLowering::passByValArg( 4139 SDValue Chain, const SDLoc &DL, 4140 std::deque<std::pair<unsigned, SDValue>> &RegsToPass, 4141 SmallVectorImpl<SDValue> &MemOpChains, SDValue StackPtr, 4142 MachineFrameInfo &MFI, SelectionDAG &DAG, SDValue Arg, unsigned FirstReg, 4143 unsigned LastReg, const ISD::ArgFlagsTy &Flags, bool isLittle, 4144 const CCValAssign &VA) const { 4145 unsigned ByValSizeInBytes = Flags.getByValSize(); 4146 unsigned OffsetInBytes = 0; // From beginning of struct 4147 unsigned RegSizeInBytes = Subtarget.getGPRSizeInBytes(); 4148 unsigned Alignment = std::min(Flags.getByValAlign(), RegSizeInBytes); 4149 EVT PtrTy = getPointerTy(DAG.getDataLayout()), 4150 RegTy = MVT::getIntegerVT(RegSizeInBytes * 8); 4151 unsigned NumRegs = LastReg - FirstReg; 4152 4153 if (NumRegs) { 4154 ArrayRef<MCPhysReg> ArgRegs = ABI.GetByValArgRegs(); 4155 bool LeftoverBytes = (NumRegs * RegSizeInBytes > ByValSizeInBytes); 4156 unsigned I = 0; 4157 4158 // Copy words to registers. 4159 for (; I < NumRegs - LeftoverBytes; ++I, OffsetInBytes += RegSizeInBytes) { 4160 SDValue LoadPtr = DAG.getNode(ISD::ADD, DL, PtrTy, Arg, 4161 DAG.getConstant(OffsetInBytes, DL, PtrTy)); 4162 SDValue LoadVal = DAG.getLoad(RegTy, DL, Chain, LoadPtr, 4163 MachinePointerInfo(), Alignment); 4164 MemOpChains.push_back(LoadVal.getValue(1)); 4165 unsigned ArgReg = ArgRegs[FirstReg + I]; 4166 RegsToPass.push_back(std::make_pair(ArgReg, LoadVal)); 4167 } 4168 4169 // Return if the struct has been fully copied. 4170 if (ByValSizeInBytes == OffsetInBytes) 4171 return; 4172 4173 // Copy the remainder of the byval argument with sub-word loads and shifts. 4174 if (LeftoverBytes) { 4175 SDValue Val; 4176 4177 for (unsigned LoadSizeInBytes = RegSizeInBytes / 2, TotalBytesLoaded = 0; 4178 OffsetInBytes < ByValSizeInBytes; LoadSizeInBytes /= 2) { 4179 unsigned RemainingSizeInBytes = ByValSizeInBytes - OffsetInBytes; 4180 4181 if (RemainingSizeInBytes < LoadSizeInBytes) 4182 continue; 4183 4184 // Load subword. 4185 SDValue LoadPtr = DAG.getNode(ISD::ADD, DL, PtrTy, Arg, 4186 DAG.getConstant(OffsetInBytes, DL, 4187 PtrTy)); 4188 SDValue LoadVal = DAG.getExtLoad( 4189 ISD::ZEXTLOAD, DL, RegTy, Chain, LoadPtr, MachinePointerInfo(), 4190 MVT::getIntegerVT(LoadSizeInBytes * 8), Alignment); 4191 MemOpChains.push_back(LoadVal.getValue(1)); 4192 4193 // Shift the loaded value. 4194 unsigned Shamt; 4195 4196 if (isLittle) 4197 Shamt = TotalBytesLoaded * 8; 4198 else 4199 Shamt = (RegSizeInBytes - (TotalBytesLoaded + LoadSizeInBytes)) * 8; 4200 4201 SDValue Shift = DAG.getNode(ISD::SHL, DL, RegTy, LoadVal, 4202 DAG.getConstant(Shamt, DL, MVT::i32)); 4203 4204 if (Val.getNode()) 4205 Val = DAG.getNode(ISD::OR, DL, RegTy, Val, Shift); 4206 else 4207 Val = Shift; 4208 4209 OffsetInBytes += LoadSizeInBytes; 4210 TotalBytesLoaded += LoadSizeInBytes; 4211 Alignment = std::min(Alignment, LoadSizeInBytes); 4212 } 4213 4214 unsigned ArgReg = ArgRegs[FirstReg + I]; 4215 RegsToPass.push_back(std::make_pair(ArgReg, Val)); 4216 return; 4217 } 4218 } 4219 4220 // Copy remainder of byval arg to it with memcpy. 4221 unsigned MemCpySize = ByValSizeInBytes - OffsetInBytes; 4222 SDValue Src = DAG.getNode(ISD::ADD, DL, PtrTy, Arg, 4223 DAG.getConstant(OffsetInBytes, DL, PtrTy)); 4224 SDValue Dst = DAG.getNode(ISD::ADD, DL, PtrTy, StackPtr, 4225 DAG.getIntPtrConstant(VA.getLocMemOffset(), DL)); 4226 Chain = DAG.getMemcpy(Chain, DL, Dst, Src, 4227 DAG.getConstant(MemCpySize, DL, PtrTy), 4228 Alignment, /*isVolatile=*/false, /*AlwaysInline=*/false, 4229 /*isTailCall=*/false, 4230 MachinePointerInfo(), MachinePointerInfo()); 4231 MemOpChains.push_back(Chain); 4232 } 4233 4234 void MipsTargetLowering::writeVarArgRegs(std::vector<SDValue> &OutChains, 4235 SDValue Chain, const SDLoc &DL, 4236 SelectionDAG &DAG, 4237 CCState &State) const { 4238 ArrayRef<MCPhysReg> ArgRegs = ABI.GetVarArgRegs(); 4239 unsigned Idx = State.getFirstUnallocated(ArgRegs); 4240 unsigned RegSizeInBytes = Subtarget.getGPRSizeInBytes(); 4241 MVT RegTy = MVT::getIntegerVT(RegSizeInBytes * 8); 4242 const TargetRegisterClass *RC = getRegClassFor(RegTy); 4243 MachineFunction &MF = DAG.getMachineFunction(); 4244 MachineFrameInfo &MFI = MF.getFrameInfo(); 4245 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>(); 4246 4247 // Offset of the first variable argument from stack pointer. 4248 int VaArgOffset; 4249 4250 if (ArgRegs.size() == Idx) 4251 VaArgOffset = alignTo(State.getNextStackOffset(), RegSizeInBytes); 4252 else { 4253 VaArgOffset = 4254 (int)ABI.GetCalleeAllocdArgSizeInBytes(State.getCallingConv()) - 4255 (int)(RegSizeInBytes * (ArgRegs.size() - Idx)); 4256 } 4257 4258 // Record the frame index of the first variable argument 4259 // which is a value necessary to VASTART. 4260 int FI = MFI.CreateFixedObject(RegSizeInBytes, VaArgOffset, true); 4261 MipsFI->setVarArgsFrameIndex(FI); 4262 4263 // Copy the integer registers that have not been used for argument passing 4264 // to the argument register save area. For O32, the save area is allocated 4265 // in the caller's stack frame, while for N32/64, it is allocated in the 4266 // callee's stack frame. 4267 for (unsigned I = Idx; I < ArgRegs.size(); 4268 ++I, VaArgOffset += RegSizeInBytes) { 4269 unsigned Reg = addLiveIn(MF, ArgRegs[I], RC); 4270 SDValue ArgValue = DAG.getCopyFromReg(Chain, DL, Reg, RegTy); 4271 FI = MFI.CreateFixedObject(RegSizeInBytes, VaArgOffset, true); 4272 SDValue PtrOff = DAG.getFrameIndex(FI, getPointerTy(DAG.getDataLayout())); 4273 SDValue Store = 4274 DAG.getStore(Chain, DL, ArgValue, PtrOff, MachinePointerInfo()); 4275 cast<StoreSDNode>(Store.getNode())->getMemOperand()->setValue( 4276 (Value *)nullptr); 4277 OutChains.push_back(Store); 4278 } 4279 } 4280 4281 void MipsTargetLowering::HandleByVal(CCState *State, unsigned &Size, 4282 unsigned Align) const { 4283 const TargetFrameLowering *TFL = Subtarget.getFrameLowering(); 4284 4285 assert(Size && "Byval argument's size shouldn't be 0."); 4286 4287 Align = std::min(Align, TFL->getStackAlignment()); 4288 4289 unsigned FirstReg = 0; 4290 unsigned NumRegs = 0; 4291 4292 if (State->getCallingConv() != CallingConv::Fast) { 4293 unsigned RegSizeInBytes = Subtarget.getGPRSizeInBytes(); 4294 ArrayRef<MCPhysReg> IntArgRegs = ABI.GetByValArgRegs(); 4295 // FIXME: The O32 case actually describes no shadow registers. 4296 const MCPhysReg *ShadowRegs = 4297 ABI.IsO32() ? IntArgRegs.data() : Mips64DPRegs; 4298 4299 // We used to check the size as well but we can't do that anymore since 4300 // CCState::HandleByVal() rounds up the size after calling this function. 4301 assert(!(Align % RegSizeInBytes) && 4302 "Byval argument's alignment should be a multiple of" 4303 "RegSizeInBytes."); 4304 4305 FirstReg = State->getFirstUnallocated(IntArgRegs); 4306 4307 // If Align > RegSizeInBytes, the first arg register must be even. 4308 // FIXME: This condition happens to do the right thing but it's not the 4309 // right way to test it. We want to check that the stack frame offset 4310 // of the register is aligned. 4311 if ((Align > RegSizeInBytes) && (FirstReg % 2)) { 4312 State->AllocateReg(IntArgRegs[FirstReg], ShadowRegs[FirstReg]); 4313 ++FirstReg; 4314 } 4315 4316 // Mark the registers allocated. 4317 Size = alignTo(Size, RegSizeInBytes); 4318 for (unsigned I = FirstReg; Size > 0 && (I < IntArgRegs.size()); 4319 Size -= RegSizeInBytes, ++I, ++NumRegs) 4320 State->AllocateReg(IntArgRegs[I], ShadowRegs[I]); 4321 } 4322 4323 State->addInRegsParamInfo(FirstReg, FirstReg + NumRegs); 4324 } 4325 4326 MachineBasicBlock *MipsTargetLowering::emitPseudoSELECT(MachineInstr &MI, 4327 MachineBasicBlock *BB, 4328 bool isFPCmp, 4329 unsigned Opc) const { 4330 assert(!(Subtarget.hasMips4() || Subtarget.hasMips32()) && 4331 "Subtarget already supports SELECT nodes with the use of" 4332 "conditional-move instructions."); 4333 4334 const TargetInstrInfo *TII = 4335 Subtarget.getInstrInfo(); 4336 DebugLoc DL = MI.getDebugLoc(); 4337 4338 // To "insert" a SELECT instruction, we actually have to insert the 4339 // diamond control-flow pattern. The incoming instruction knows the 4340 // destination vreg to set, the condition code register to branch on, the 4341 // true/false values to select between, and a branch opcode to use. 4342 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 4343 MachineFunction::iterator It = ++BB->getIterator(); 4344 4345 // thisMBB: 4346 // ... 4347 // TrueVal = ... 4348 // setcc r1, r2, r3 4349 // bNE r1, r0, copy1MBB 4350 // fallthrough --> copy0MBB 4351 MachineBasicBlock *thisMBB = BB; 4352 MachineFunction *F = BB->getParent(); 4353 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB); 4354 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB); 4355 F->insert(It, copy0MBB); 4356 F->insert(It, sinkMBB); 4357 4358 // Transfer the remainder of BB and its successor edges to sinkMBB. 4359 sinkMBB->splice(sinkMBB->begin(), BB, 4360 std::next(MachineBasicBlock::iterator(MI)), BB->end()); 4361 sinkMBB->transferSuccessorsAndUpdatePHIs(BB); 4362 4363 // Next, add the true and fallthrough blocks as its successors. 4364 BB->addSuccessor(copy0MBB); 4365 BB->addSuccessor(sinkMBB); 4366 4367 if (isFPCmp) { 4368 // bc1[tf] cc, sinkMBB 4369 BuildMI(BB, DL, TII->get(Opc)) 4370 .addReg(MI.getOperand(1).getReg()) 4371 .addMBB(sinkMBB); 4372 } else { 4373 // bne rs, $0, sinkMBB 4374 BuildMI(BB, DL, TII->get(Opc)) 4375 .addReg(MI.getOperand(1).getReg()) 4376 .addReg(Mips::ZERO) 4377 .addMBB(sinkMBB); 4378 } 4379 4380 // copy0MBB: 4381 // %FalseValue = ... 4382 // # fallthrough to sinkMBB 4383 BB = copy0MBB; 4384 4385 // Update machine-CFG edges 4386 BB->addSuccessor(sinkMBB); 4387 4388 // sinkMBB: 4389 // %Result = phi [ %TrueValue, thisMBB ], [ %FalseValue, copy0MBB ] 4390 // ... 4391 BB = sinkMBB; 4392 4393 BuildMI(*BB, BB->begin(), DL, TII->get(Mips::PHI), MI.getOperand(0).getReg()) 4394 .addReg(MI.getOperand(2).getReg()) 4395 .addMBB(thisMBB) 4396 .addReg(MI.getOperand(3).getReg()) 4397 .addMBB(copy0MBB); 4398 4399 MI.eraseFromParent(); // The pseudo instruction is gone now. 4400 4401 return BB; 4402 } 4403 4404 // FIXME? Maybe this could be a TableGen attribute on some registers and 4405 // this table could be generated automatically from RegInfo. 4406 unsigned MipsTargetLowering::getRegisterByName(const char* RegName, EVT VT, 4407 SelectionDAG &DAG) const { 4408 // Named registers is expected to be fairly rare. For now, just support $28 4409 // since the linux kernel uses it. 4410 if (Subtarget.isGP64bit()) { 4411 unsigned Reg = StringSwitch<unsigned>(RegName) 4412 .Case("$28", Mips::GP_64) 4413 .Default(0); 4414 if (Reg) 4415 return Reg; 4416 } else { 4417 unsigned Reg = StringSwitch<unsigned>(RegName) 4418 .Case("$28", Mips::GP) 4419 .Default(0); 4420 if (Reg) 4421 return Reg; 4422 } 4423 report_fatal_error("Invalid register name global variable"); 4424 } 4425