1 //===-- MipsISelLowering.cpp - Mips DAG Lowering Implementation -----------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file defines the interfaces that Mips uses to lower LLVM code into a 11 // selection DAG. 12 // 13 //===----------------------------------------------------------------------===// 14 #include "MipsISelLowering.h" 15 #include "InstPrinter/MipsInstPrinter.h" 16 #include "MCTargetDesc/MipsBaseInfo.h" 17 #include "MipsCCState.h" 18 #include "MipsMachineFunction.h" 19 #include "MipsSubtarget.h" 20 #include "MipsTargetMachine.h" 21 #include "MipsTargetObjectFile.h" 22 #include "llvm/ADT/Statistic.h" 23 #include "llvm/ADT/StringSwitch.h" 24 #include "llvm/CodeGen/CallingConvLower.h" 25 #include "llvm/CodeGen/MachineFrameInfo.h" 26 #include "llvm/CodeGen/MachineFunction.h" 27 #include "llvm/CodeGen/MachineInstrBuilder.h" 28 #include "llvm/CodeGen/MachineJumpTableInfo.h" 29 #include "llvm/CodeGen/MachineRegisterInfo.h" 30 #include "llvm/CodeGen/FunctionLoweringInfo.h" 31 #include "llvm/CodeGen/SelectionDAGISel.h" 32 #include "llvm/CodeGen/ValueTypes.h" 33 #include "llvm/IR/CallingConv.h" 34 #include "llvm/IR/DerivedTypes.h" 35 #include "llvm/IR/GlobalVariable.h" 36 #include "llvm/Support/CommandLine.h" 37 #include "llvm/Support/Debug.h" 38 #include "llvm/Support/ErrorHandling.h" 39 #include "llvm/Support/raw_ostream.h" 40 #include <cctype> 41 42 using namespace llvm; 43 44 #define DEBUG_TYPE "mips-lower" 45 46 STATISTIC(NumTailCalls, "Number of tail calls"); 47 48 static cl::opt<bool> 49 LargeGOT("mxgot", cl::Hidden, 50 cl::desc("MIPS: Enable GOT larger than 64k."), cl::init(false)); 51 52 static cl::opt<bool> 53 NoZeroDivCheck("mno-check-zero-division", cl::Hidden, 54 cl::desc("MIPS: Don't trap on integer division by zero."), 55 cl::init(false)); 56 57 static const MCPhysReg Mips64DPRegs[8] = { 58 Mips::D12_64, Mips::D13_64, Mips::D14_64, Mips::D15_64, 59 Mips::D16_64, Mips::D17_64, Mips::D18_64, Mips::D19_64 60 }; 61 62 // If I is a shifted mask, set the size (Size) and the first bit of the 63 // mask (Pos), and return true. 64 // For example, if I is 0x003ff800, (Pos, Size) = (11, 11). 65 static bool isShiftedMask(uint64_t I, uint64_t &Pos, uint64_t &Size) { 66 if (!isShiftedMask_64(I)) 67 return false; 68 69 Size = countPopulation(I); 70 Pos = countTrailingZeros(I); 71 return true; 72 } 73 74 SDValue MipsTargetLowering::getGlobalReg(SelectionDAG &DAG, EVT Ty) const { 75 MipsFunctionInfo *FI = DAG.getMachineFunction().getInfo<MipsFunctionInfo>(); 76 return DAG.getRegister(FI->getGlobalBaseReg(), Ty); 77 } 78 79 SDValue MipsTargetLowering::getTargetNode(GlobalAddressSDNode *N, EVT Ty, 80 SelectionDAG &DAG, 81 unsigned Flag) const { 82 return DAG.getTargetGlobalAddress(N->getGlobal(), SDLoc(N), Ty, 0, Flag); 83 } 84 85 SDValue MipsTargetLowering::getTargetNode(ExternalSymbolSDNode *N, EVT Ty, 86 SelectionDAG &DAG, 87 unsigned Flag) const { 88 return DAG.getTargetExternalSymbol(N->getSymbol(), Ty, Flag); 89 } 90 91 SDValue MipsTargetLowering::getTargetNode(BlockAddressSDNode *N, EVT Ty, 92 SelectionDAG &DAG, 93 unsigned Flag) const { 94 return DAG.getTargetBlockAddress(N->getBlockAddress(), Ty, 0, Flag); 95 } 96 97 SDValue MipsTargetLowering::getTargetNode(JumpTableSDNode *N, EVT Ty, 98 SelectionDAG &DAG, 99 unsigned Flag) const { 100 return DAG.getTargetJumpTable(N->getIndex(), Ty, Flag); 101 } 102 103 SDValue MipsTargetLowering::getTargetNode(ConstantPoolSDNode *N, EVT Ty, 104 SelectionDAG &DAG, 105 unsigned Flag) const { 106 return DAG.getTargetConstantPool(N->getConstVal(), Ty, N->getAlignment(), 107 N->getOffset(), Flag); 108 } 109 110 const char *MipsTargetLowering::getTargetNodeName(unsigned Opcode) const { 111 switch ((MipsISD::NodeType)Opcode) { 112 case MipsISD::FIRST_NUMBER: break; 113 case MipsISD::JmpLink: return "MipsISD::JmpLink"; 114 case MipsISD::TailCall: return "MipsISD::TailCall"; 115 case MipsISD::Hi: return "MipsISD::Hi"; 116 case MipsISD::Lo: return "MipsISD::Lo"; 117 case MipsISD::GPRel: return "MipsISD::GPRel"; 118 case MipsISD::ThreadPointer: return "MipsISD::ThreadPointer"; 119 case MipsISD::Ret: return "MipsISD::Ret"; 120 case MipsISD::ERet: return "MipsISD::ERet"; 121 case MipsISD::EH_RETURN: return "MipsISD::EH_RETURN"; 122 case MipsISD::FPBrcond: return "MipsISD::FPBrcond"; 123 case MipsISD::FPCmp: return "MipsISD::FPCmp"; 124 case MipsISD::CMovFP_T: return "MipsISD::CMovFP_T"; 125 case MipsISD::CMovFP_F: return "MipsISD::CMovFP_F"; 126 case MipsISD::TruncIntFP: return "MipsISD::TruncIntFP"; 127 case MipsISD::MFHI: return "MipsISD::MFHI"; 128 case MipsISD::MFLO: return "MipsISD::MFLO"; 129 case MipsISD::MTLOHI: return "MipsISD::MTLOHI"; 130 case MipsISD::Mult: return "MipsISD::Mult"; 131 case MipsISD::Multu: return "MipsISD::Multu"; 132 case MipsISD::MAdd: return "MipsISD::MAdd"; 133 case MipsISD::MAddu: return "MipsISD::MAddu"; 134 case MipsISD::MSub: return "MipsISD::MSub"; 135 case MipsISD::MSubu: return "MipsISD::MSubu"; 136 case MipsISD::DivRem: return "MipsISD::DivRem"; 137 case MipsISD::DivRemU: return "MipsISD::DivRemU"; 138 case MipsISD::DivRem16: return "MipsISD::DivRem16"; 139 case MipsISD::DivRemU16: return "MipsISD::DivRemU16"; 140 case MipsISD::BuildPairF64: return "MipsISD::BuildPairF64"; 141 case MipsISD::ExtractElementF64: return "MipsISD::ExtractElementF64"; 142 case MipsISD::Wrapper: return "MipsISD::Wrapper"; 143 case MipsISD::DynAlloc: return "MipsISD::DynAlloc"; 144 case MipsISD::Sync: return "MipsISD::Sync"; 145 case MipsISD::Ext: return "MipsISD::Ext"; 146 case MipsISD::Ins: return "MipsISD::Ins"; 147 case MipsISD::LWL: return "MipsISD::LWL"; 148 case MipsISD::LWR: return "MipsISD::LWR"; 149 case MipsISD::SWL: return "MipsISD::SWL"; 150 case MipsISD::SWR: return "MipsISD::SWR"; 151 case MipsISD::LDL: return "MipsISD::LDL"; 152 case MipsISD::LDR: return "MipsISD::LDR"; 153 case MipsISD::SDL: return "MipsISD::SDL"; 154 case MipsISD::SDR: return "MipsISD::SDR"; 155 case MipsISD::EXTP: return "MipsISD::EXTP"; 156 case MipsISD::EXTPDP: return "MipsISD::EXTPDP"; 157 case MipsISD::EXTR_S_H: return "MipsISD::EXTR_S_H"; 158 case MipsISD::EXTR_W: return "MipsISD::EXTR_W"; 159 case MipsISD::EXTR_R_W: return "MipsISD::EXTR_R_W"; 160 case MipsISD::EXTR_RS_W: return "MipsISD::EXTR_RS_W"; 161 case MipsISD::SHILO: return "MipsISD::SHILO"; 162 case MipsISD::MTHLIP: return "MipsISD::MTHLIP"; 163 case MipsISD::MULSAQ_S_W_PH: return "MipsISD::MULSAQ_S_W_PH"; 164 case MipsISD::MAQ_S_W_PHL: return "MipsISD::MAQ_S_W_PHL"; 165 case MipsISD::MAQ_S_W_PHR: return "MipsISD::MAQ_S_W_PHR"; 166 case MipsISD::MAQ_SA_W_PHL: return "MipsISD::MAQ_SA_W_PHL"; 167 case MipsISD::MAQ_SA_W_PHR: return "MipsISD::MAQ_SA_W_PHR"; 168 case MipsISD::DPAU_H_QBL: return "MipsISD::DPAU_H_QBL"; 169 case MipsISD::DPAU_H_QBR: return "MipsISD::DPAU_H_QBR"; 170 case MipsISD::DPSU_H_QBL: return "MipsISD::DPSU_H_QBL"; 171 case MipsISD::DPSU_H_QBR: return "MipsISD::DPSU_H_QBR"; 172 case MipsISD::DPAQ_S_W_PH: return "MipsISD::DPAQ_S_W_PH"; 173 case MipsISD::DPSQ_S_W_PH: return "MipsISD::DPSQ_S_W_PH"; 174 case MipsISD::DPAQ_SA_L_W: return "MipsISD::DPAQ_SA_L_W"; 175 case MipsISD::DPSQ_SA_L_W: return "MipsISD::DPSQ_SA_L_W"; 176 case MipsISD::DPA_W_PH: return "MipsISD::DPA_W_PH"; 177 case MipsISD::DPS_W_PH: return "MipsISD::DPS_W_PH"; 178 case MipsISD::DPAQX_S_W_PH: return "MipsISD::DPAQX_S_W_PH"; 179 case MipsISD::DPAQX_SA_W_PH: return "MipsISD::DPAQX_SA_W_PH"; 180 case MipsISD::DPAX_W_PH: return "MipsISD::DPAX_W_PH"; 181 case MipsISD::DPSX_W_PH: return "MipsISD::DPSX_W_PH"; 182 case MipsISD::DPSQX_S_W_PH: return "MipsISD::DPSQX_S_W_PH"; 183 case MipsISD::DPSQX_SA_W_PH: return "MipsISD::DPSQX_SA_W_PH"; 184 case MipsISD::MULSA_W_PH: return "MipsISD::MULSA_W_PH"; 185 case MipsISD::MULT: return "MipsISD::MULT"; 186 case MipsISD::MULTU: return "MipsISD::MULTU"; 187 case MipsISD::MADD_DSP: return "MipsISD::MADD_DSP"; 188 case MipsISD::MADDU_DSP: return "MipsISD::MADDU_DSP"; 189 case MipsISD::MSUB_DSP: return "MipsISD::MSUB_DSP"; 190 case MipsISD::MSUBU_DSP: return "MipsISD::MSUBU_DSP"; 191 case MipsISD::SHLL_DSP: return "MipsISD::SHLL_DSP"; 192 case MipsISD::SHRA_DSP: return "MipsISD::SHRA_DSP"; 193 case MipsISD::SHRL_DSP: return "MipsISD::SHRL_DSP"; 194 case MipsISD::SETCC_DSP: return "MipsISD::SETCC_DSP"; 195 case MipsISD::SELECT_CC_DSP: return "MipsISD::SELECT_CC_DSP"; 196 case MipsISD::VALL_ZERO: return "MipsISD::VALL_ZERO"; 197 case MipsISD::VANY_ZERO: return "MipsISD::VANY_ZERO"; 198 case MipsISD::VALL_NONZERO: return "MipsISD::VALL_NONZERO"; 199 case MipsISD::VANY_NONZERO: return "MipsISD::VANY_NONZERO"; 200 case MipsISD::VCEQ: return "MipsISD::VCEQ"; 201 case MipsISD::VCLE_S: return "MipsISD::VCLE_S"; 202 case MipsISD::VCLE_U: return "MipsISD::VCLE_U"; 203 case MipsISD::VCLT_S: return "MipsISD::VCLT_S"; 204 case MipsISD::VCLT_U: return "MipsISD::VCLT_U"; 205 case MipsISD::VSMAX: return "MipsISD::VSMAX"; 206 case MipsISD::VSMIN: return "MipsISD::VSMIN"; 207 case MipsISD::VUMAX: return "MipsISD::VUMAX"; 208 case MipsISD::VUMIN: return "MipsISD::VUMIN"; 209 case MipsISD::VEXTRACT_SEXT_ELT: return "MipsISD::VEXTRACT_SEXT_ELT"; 210 case MipsISD::VEXTRACT_ZEXT_ELT: return "MipsISD::VEXTRACT_ZEXT_ELT"; 211 case MipsISD::VNOR: return "MipsISD::VNOR"; 212 case MipsISD::VSHF: return "MipsISD::VSHF"; 213 case MipsISD::SHF: return "MipsISD::SHF"; 214 case MipsISD::ILVEV: return "MipsISD::ILVEV"; 215 case MipsISD::ILVOD: return "MipsISD::ILVOD"; 216 case MipsISD::ILVL: return "MipsISD::ILVL"; 217 case MipsISD::ILVR: return "MipsISD::ILVR"; 218 case MipsISD::PCKEV: return "MipsISD::PCKEV"; 219 case MipsISD::PCKOD: return "MipsISD::PCKOD"; 220 case MipsISD::INSVE: return "MipsISD::INSVE"; 221 } 222 return nullptr; 223 } 224 225 MipsTargetLowering::MipsTargetLowering(const MipsTargetMachine &TM, 226 const MipsSubtarget &STI) 227 : TargetLowering(TM), Subtarget(STI), ABI(TM.getABI()) { 228 // Mips does not have i1 type, so use i32 for 229 // setcc operations results (slt, sgt, ...). 230 setBooleanContents(ZeroOrOneBooleanContent); 231 setBooleanVectorContents(ZeroOrNegativeOneBooleanContent); 232 // The cmp.cond.fmt instruction in MIPS32r6/MIPS64r6 uses 0 and -1 like MSA 233 // does. Integer booleans still use 0 and 1. 234 if (Subtarget.hasMips32r6()) 235 setBooleanContents(ZeroOrOneBooleanContent, 236 ZeroOrNegativeOneBooleanContent); 237 238 // Load extented operations for i1 types must be promoted 239 for (MVT VT : MVT::integer_valuetypes()) { 240 setLoadExtAction(ISD::EXTLOAD, VT, MVT::i1, Promote); 241 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i1, Promote); 242 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i1, Promote); 243 } 244 245 // MIPS doesn't have extending float->double load/store. Set LoadExtAction 246 // for f32, f16 247 for (MVT VT : MVT::fp_valuetypes()) { 248 setLoadExtAction(ISD::EXTLOAD, VT, MVT::f32, Expand); 249 setLoadExtAction(ISD::EXTLOAD, VT, MVT::f16, Expand); 250 } 251 252 // Set LoadExtAction for f16 vectors to Expand 253 for (MVT VT : MVT::fp_vector_valuetypes()) { 254 MVT F16VT = MVT::getVectorVT(MVT::f16, VT.getVectorNumElements()); 255 if (F16VT.isValid()) 256 setLoadExtAction(ISD::EXTLOAD, VT, F16VT, Expand); 257 } 258 259 setTruncStoreAction(MVT::f32, MVT::f16, Expand); 260 setTruncStoreAction(MVT::f64, MVT::f16, Expand); 261 262 setTruncStoreAction(MVT::f64, MVT::f32, Expand); 263 264 // Used by legalize types to correctly generate the setcc result. 265 // Without this, every float setcc comes with a AND/OR with the result, 266 // we don't want this, since the fpcmp result goes to a flag register, 267 // which is used implicitly by brcond and select operations. 268 AddPromotedToType(ISD::SETCC, MVT::i1, MVT::i32); 269 270 // Mips Custom Operations 271 setOperationAction(ISD::BR_JT, MVT::Other, Custom); 272 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom); 273 setOperationAction(ISD::BlockAddress, MVT::i32, Custom); 274 setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom); 275 setOperationAction(ISD::JumpTable, MVT::i32, Custom); 276 setOperationAction(ISD::ConstantPool, MVT::i32, Custom); 277 setOperationAction(ISD::SELECT, MVT::f32, Custom); 278 setOperationAction(ISD::SELECT, MVT::f64, Custom); 279 setOperationAction(ISD::SELECT, MVT::i32, Custom); 280 setOperationAction(ISD::SETCC, MVT::f32, Custom); 281 setOperationAction(ISD::SETCC, MVT::f64, Custom); 282 setOperationAction(ISD::BRCOND, MVT::Other, Custom); 283 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom); 284 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom); 285 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom); 286 287 if (Subtarget.isGP64bit()) { 288 setOperationAction(ISD::GlobalAddress, MVT::i64, Custom); 289 setOperationAction(ISD::BlockAddress, MVT::i64, Custom); 290 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom); 291 setOperationAction(ISD::JumpTable, MVT::i64, Custom); 292 setOperationAction(ISD::ConstantPool, MVT::i64, Custom); 293 setOperationAction(ISD::SELECT, MVT::i64, Custom); 294 setOperationAction(ISD::LOAD, MVT::i64, Custom); 295 setOperationAction(ISD::STORE, MVT::i64, Custom); 296 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom); 297 setOperationAction(ISD::SHL_PARTS, MVT::i64, Custom); 298 setOperationAction(ISD::SRA_PARTS, MVT::i64, Custom); 299 setOperationAction(ISD::SRL_PARTS, MVT::i64, Custom); 300 } 301 302 if (!Subtarget.isGP64bit()) { 303 setOperationAction(ISD::SHL_PARTS, MVT::i32, Custom); 304 setOperationAction(ISD::SRA_PARTS, MVT::i32, Custom); 305 setOperationAction(ISD::SRL_PARTS, MVT::i32, Custom); 306 } 307 308 setOperationAction(ISD::EH_DWARF_CFA, MVT::i32, Custom); 309 if (Subtarget.isGP64bit()) 310 setOperationAction(ISD::EH_DWARF_CFA, MVT::i64, Custom); 311 312 setOperationAction(ISD::SDIV, MVT::i32, Expand); 313 setOperationAction(ISD::SREM, MVT::i32, Expand); 314 setOperationAction(ISD::UDIV, MVT::i32, Expand); 315 setOperationAction(ISD::UREM, MVT::i32, Expand); 316 setOperationAction(ISD::SDIV, MVT::i64, Expand); 317 setOperationAction(ISD::SREM, MVT::i64, Expand); 318 setOperationAction(ISD::UDIV, MVT::i64, Expand); 319 setOperationAction(ISD::UREM, MVT::i64, Expand); 320 321 // Operations not directly supported by Mips. 322 setOperationAction(ISD::BR_CC, MVT::f32, Expand); 323 setOperationAction(ISD::BR_CC, MVT::f64, Expand); 324 setOperationAction(ISD::BR_CC, MVT::i32, Expand); 325 setOperationAction(ISD::BR_CC, MVT::i64, Expand); 326 setOperationAction(ISD::SELECT_CC, MVT::i32, Expand); 327 setOperationAction(ISD::SELECT_CC, MVT::i64, Expand); 328 setOperationAction(ISD::SELECT_CC, MVT::f32, Expand); 329 setOperationAction(ISD::SELECT_CC, MVT::f64, Expand); 330 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand); 331 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Expand); 332 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand); 333 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Expand); 334 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand); 335 if (Subtarget.hasCnMips()) { 336 setOperationAction(ISD::CTPOP, MVT::i32, Legal); 337 setOperationAction(ISD::CTPOP, MVT::i64, Legal); 338 } else { 339 setOperationAction(ISD::CTPOP, MVT::i32, Expand); 340 setOperationAction(ISD::CTPOP, MVT::i64, Expand); 341 } 342 setOperationAction(ISD::CTTZ, MVT::i32, Expand); 343 setOperationAction(ISD::CTTZ, MVT::i64, Expand); 344 setOperationAction(ISD::ROTL, MVT::i32, Expand); 345 setOperationAction(ISD::ROTL, MVT::i64, Expand); 346 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Expand); 347 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64, Expand); 348 349 if (!Subtarget.hasMips32r2()) 350 setOperationAction(ISD::ROTR, MVT::i32, Expand); 351 352 if (!Subtarget.hasMips64r2()) 353 setOperationAction(ISD::ROTR, MVT::i64, Expand); 354 355 setOperationAction(ISD::FSIN, MVT::f32, Expand); 356 setOperationAction(ISD::FSIN, MVT::f64, Expand); 357 setOperationAction(ISD::FCOS, MVT::f32, Expand); 358 setOperationAction(ISD::FCOS, MVT::f64, Expand); 359 setOperationAction(ISD::FSINCOS, MVT::f32, Expand); 360 setOperationAction(ISD::FSINCOS, MVT::f64, Expand); 361 setOperationAction(ISD::FPOWI, MVT::f32, Expand); 362 setOperationAction(ISD::FPOW, MVT::f32, Expand); 363 setOperationAction(ISD::FPOW, MVT::f64, Expand); 364 setOperationAction(ISD::FLOG, MVT::f32, Expand); 365 setOperationAction(ISD::FLOG2, MVT::f32, Expand); 366 setOperationAction(ISD::FLOG10, MVT::f32, Expand); 367 setOperationAction(ISD::FEXP, MVT::f32, Expand); 368 setOperationAction(ISD::FMA, MVT::f32, Expand); 369 setOperationAction(ISD::FMA, MVT::f64, Expand); 370 setOperationAction(ISD::FREM, MVT::f32, Expand); 371 setOperationAction(ISD::FREM, MVT::f64, Expand); 372 373 // Lower f16 conversion operations into library calls 374 setOperationAction(ISD::FP16_TO_FP, MVT::f32, Expand); 375 setOperationAction(ISD::FP_TO_FP16, MVT::f32, Expand); 376 setOperationAction(ISD::FP16_TO_FP, MVT::f64, Expand); 377 setOperationAction(ISD::FP_TO_FP16, MVT::f64, Expand); 378 379 setOperationAction(ISD::EH_RETURN, MVT::Other, Custom); 380 381 setOperationAction(ISD::VASTART, MVT::Other, Custom); 382 setOperationAction(ISD::VAARG, MVT::Other, Custom); 383 setOperationAction(ISD::VACOPY, MVT::Other, Expand); 384 setOperationAction(ISD::VAEND, MVT::Other, Expand); 385 386 // Use the default for now 387 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand); 388 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand); 389 390 if (!Subtarget.isGP64bit()) { 391 setOperationAction(ISD::ATOMIC_LOAD, MVT::i64, Expand); 392 setOperationAction(ISD::ATOMIC_STORE, MVT::i64, Expand); 393 } 394 395 396 if (!Subtarget.hasMips32r2()) { 397 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8, Expand); 398 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand); 399 } 400 401 // MIPS16 lacks MIPS32's clz and clo instructions. 402 if (!Subtarget.hasMips32() || Subtarget.inMips16Mode()) 403 setOperationAction(ISD::CTLZ, MVT::i32, Expand); 404 if (!Subtarget.hasMips64()) 405 setOperationAction(ISD::CTLZ, MVT::i64, Expand); 406 407 if (!Subtarget.hasMips32r2()) 408 setOperationAction(ISD::BSWAP, MVT::i32, Expand); 409 if (!Subtarget.hasMips64r2()) 410 setOperationAction(ISD::BSWAP, MVT::i64, Expand); 411 412 if (Subtarget.isGP64bit()) { 413 setLoadExtAction(ISD::SEXTLOAD, MVT::i64, MVT::i32, Custom); 414 setLoadExtAction(ISD::ZEXTLOAD, MVT::i64, MVT::i32, Custom); 415 setLoadExtAction(ISD::EXTLOAD, MVT::i64, MVT::i32, Custom); 416 setTruncStoreAction(MVT::i64, MVT::i32, Custom); 417 } 418 419 setOperationAction(ISD::TRAP, MVT::Other, Legal); 420 421 setTargetDAGCombine(ISD::SDIVREM); 422 setTargetDAGCombine(ISD::UDIVREM); 423 setTargetDAGCombine(ISD::SELECT); 424 setTargetDAGCombine(ISD::AND); 425 setTargetDAGCombine(ISD::OR); 426 setTargetDAGCombine(ISD::ADD); 427 setTargetDAGCombine(ISD::AssertZext); 428 429 if (ABI.IsO32()) { 430 // These libcalls are not available in 32-bit. 431 setLibcallName(RTLIB::SHL_I128, nullptr); 432 setLibcallName(RTLIB::SRL_I128, nullptr); 433 setLibcallName(RTLIB::SRA_I128, nullptr); 434 } 435 436 setMinFunctionAlignment(Subtarget.isGP64bit() ? 3 : 2); 437 438 // The arguments on the stack are defined in terms of 4-byte slots on O32 439 // and 8-byte slots on N32/N64. 440 setMinStackArgumentAlignment((ABI.IsN32() || ABI.IsN64()) ? 8 : 4); 441 442 setStackPointerRegisterToSaveRestore(ABI.IsN64() ? Mips::SP_64 : Mips::SP); 443 444 MaxStoresPerMemcpy = 16; 445 446 isMicroMips = Subtarget.inMicroMipsMode(); 447 } 448 449 const MipsTargetLowering *MipsTargetLowering::create(const MipsTargetMachine &TM, 450 const MipsSubtarget &STI) { 451 if (STI.inMips16Mode()) 452 return llvm::createMips16TargetLowering(TM, STI); 453 454 return llvm::createMipsSETargetLowering(TM, STI); 455 } 456 457 // Create a fast isel object. 458 FastISel * 459 MipsTargetLowering::createFastISel(FunctionLoweringInfo &funcInfo, 460 const TargetLibraryInfo *libInfo) const { 461 const MipsTargetMachine &TM = 462 static_cast<const MipsTargetMachine &>(funcInfo.MF->getTarget()); 463 464 // We support only the standard encoding [MIPS32,MIPS32R5] ISAs. 465 bool UseFastISel = TM.Options.EnableFastISel && Subtarget.hasMips32() && 466 !Subtarget.hasMips32r6() && !Subtarget.inMips16Mode() && 467 !Subtarget.inMicroMipsMode(); 468 469 // Disable if we don't generate PIC or the ABI isn't O32. 470 if (!TM.isPositionIndependent() || !TM.getABI().IsO32()) 471 UseFastISel = false; 472 473 return UseFastISel ? Mips::createFastISel(funcInfo, libInfo) : nullptr; 474 } 475 476 EVT MipsTargetLowering::getSetCCResultType(const DataLayout &, LLVMContext &, 477 EVT VT) const { 478 if (!VT.isVector()) 479 return MVT::i32; 480 return VT.changeVectorElementTypeToInteger(); 481 } 482 483 static SDValue performDivRemCombine(SDNode *N, SelectionDAG &DAG, 484 TargetLowering::DAGCombinerInfo &DCI, 485 const MipsSubtarget &Subtarget) { 486 if (DCI.isBeforeLegalizeOps()) 487 return SDValue(); 488 489 EVT Ty = N->getValueType(0); 490 unsigned LO = (Ty == MVT::i32) ? Mips::LO0 : Mips::LO0_64; 491 unsigned HI = (Ty == MVT::i32) ? Mips::HI0 : Mips::HI0_64; 492 unsigned Opc = N->getOpcode() == ISD::SDIVREM ? MipsISD::DivRem16 : 493 MipsISD::DivRemU16; 494 SDLoc DL(N); 495 496 SDValue DivRem = DAG.getNode(Opc, DL, MVT::Glue, 497 N->getOperand(0), N->getOperand(1)); 498 SDValue InChain = DAG.getEntryNode(); 499 SDValue InGlue = DivRem; 500 501 // insert MFLO 502 if (N->hasAnyUseOfValue(0)) { 503 SDValue CopyFromLo = DAG.getCopyFromReg(InChain, DL, LO, Ty, 504 InGlue); 505 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), CopyFromLo); 506 InChain = CopyFromLo.getValue(1); 507 InGlue = CopyFromLo.getValue(2); 508 } 509 510 // insert MFHI 511 if (N->hasAnyUseOfValue(1)) { 512 SDValue CopyFromHi = DAG.getCopyFromReg(InChain, DL, 513 HI, Ty, InGlue); 514 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), CopyFromHi); 515 } 516 517 return SDValue(); 518 } 519 520 static Mips::CondCode condCodeToFCC(ISD::CondCode CC) { 521 switch (CC) { 522 default: llvm_unreachable("Unknown fp condition code!"); 523 case ISD::SETEQ: 524 case ISD::SETOEQ: return Mips::FCOND_OEQ; 525 case ISD::SETUNE: return Mips::FCOND_UNE; 526 case ISD::SETLT: 527 case ISD::SETOLT: return Mips::FCOND_OLT; 528 case ISD::SETGT: 529 case ISD::SETOGT: return Mips::FCOND_OGT; 530 case ISD::SETLE: 531 case ISD::SETOLE: return Mips::FCOND_OLE; 532 case ISD::SETGE: 533 case ISD::SETOGE: return Mips::FCOND_OGE; 534 case ISD::SETULT: return Mips::FCOND_ULT; 535 case ISD::SETULE: return Mips::FCOND_ULE; 536 case ISD::SETUGT: return Mips::FCOND_UGT; 537 case ISD::SETUGE: return Mips::FCOND_UGE; 538 case ISD::SETUO: return Mips::FCOND_UN; 539 case ISD::SETO: return Mips::FCOND_OR; 540 case ISD::SETNE: 541 case ISD::SETONE: return Mips::FCOND_ONE; 542 case ISD::SETUEQ: return Mips::FCOND_UEQ; 543 } 544 } 545 546 547 /// This function returns true if the floating point conditional branches and 548 /// conditional moves which use condition code CC should be inverted. 549 static bool invertFPCondCodeUser(Mips::CondCode CC) { 550 if (CC >= Mips::FCOND_F && CC <= Mips::FCOND_NGT) 551 return false; 552 553 assert((CC >= Mips::FCOND_T && CC <= Mips::FCOND_GT) && 554 "Illegal Condition Code"); 555 556 return true; 557 } 558 559 // Creates and returns an FPCmp node from a setcc node. 560 // Returns Op if setcc is not a floating point comparison. 561 static SDValue createFPCmp(SelectionDAG &DAG, const SDValue &Op) { 562 // must be a SETCC node 563 if (Op.getOpcode() != ISD::SETCC) 564 return Op; 565 566 SDValue LHS = Op.getOperand(0); 567 568 if (!LHS.getValueType().isFloatingPoint()) 569 return Op; 570 571 SDValue RHS = Op.getOperand(1); 572 SDLoc DL(Op); 573 574 // Assume the 3rd operand is a CondCodeSDNode. Add code to check the type of 575 // node if necessary. 576 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get(); 577 578 return DAG.getNode(MipsISD::FPCmp, DL, MVT::Glue, LHS, RHS, 579 DAG.getConstant(condCodeToFCC(CC), DL, MVT::i32)); 580 } 581 582 // Creates and returns a CMovFPT/F node. 583 static SDValue createCMovFP(SelectionDAG &DAG, SDValue Cond, SDValue True, 584 SDValue False, const SDLoc &DL) { 585 ConstantSDNode *CC = cast<ConstantSDNode>(Cond.getOperand(2)); 586 bool invert = invertFPCondCodeUser((Mips::CondCode)CC->getSExtValue()); 587 SDValue FCC0 = DAG.getRegister(Mips::FCC0, MVT::i32); 588 589 return DAG.getNode((invert ? MipsISD::CMovFP_F : MipsISD::CMovFP_T), DL, 590 True.getValueType(), True, FCC0, False, Cond); 591 } 592 593 static SDValue performSELECTCombine(SDNode *N, SelectionDAG &DAG, 594 TargetLowering::DAGCombinerInfo &DCI, 595 const MipsSubtarget &Subtarget) { 596 if (DCI.isBeforeLegalizeOps()) 597 return SDValue(); 598 599 SDValue SetCC = N->getOperand(0); 600 601 if ((SetCC.getOpcode() != ISD::SETCC) || 602 !SetCC.getOperand(0).getValueType().isInteger()) 603 return SDValue(); 604 605 SDValue False = N->getOperand(2); 606 EVT FalseTy = False.getValueType(); 607 608 if (!FalseTy.isInteger()) 609 return SDValue(); 610 611 ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(False); 612 613 // If the RHS (False) is 0, we swap the order of the operands 614 // of ISD::SELECT (obviously also inverting the condition) so that we can 615 // take advantage of conditional moves using the $0 register. 616 // Example: 617 // return (a != 0) ? x : 0; 618 // load $reg, x 619 // movz $reg, $0, a 620 if (!FalseC) 621 return SDValue(); 622 623 const SDLoc DL(N); 624 625 if (!FalseC->getZExtValue()) { 626 ISD::CondCode CC = cast<CondCodeSDNode>(SetCC.getOperand(2))->get(); 627 SDValue True = N->getOperand(1); 628 629 SetCC = DAG.getSetCC(DL, SetCC.getValueType(), SetCC.getOperand(0), 630 SetCC.getOperand(1), ISD::getSetCCInverse(CC, true)); 631 632 return DAG.getNode(ISD::SELECT, DL, FalseTy, SetCC, False, True); 633 } 634 635 // If both operands are integer constants there's a possibility that we 636 // can do some interesting optimizations. 637 SDValue True = N->getOperand(1); 638 ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(True); 639 640 if (!TrueC || !True.getValueType().isInteger()) 641 return SDValue(); 642 643 // We'll also ignore MVT::i64 operands as this optimizations proves 644 // to be ineffective because of the required sign extensions as the result 645 // of a SETCC operator is always MVT::i32 for non-vector types. 646 if (True.getValueType() == MVT::i64) 647 return SDValue(); 648 649 int64_t Diff = TrueC->getSExtValue() - FalseC->getSExtValue(); 650 651 // 1) (a < x) ? y : y-1 652 // slti $reg1, a, x 653 // addiu $reg2, $reg1, y-1 654 if (Diff == 1) 655 return DAG.getNode(ISD::ADD, DL, SetCC.getValueType(), SetCC, False); 656 657 // 2) (a < x) ? y-1 : y 658 // slti $reg1, a, x 659 // xor $reg1, $reg1, 1 660 // addiu $reg2, $reg1, y-1 661 if (Diff == -1) { 662 ISD::CondCode CC = cast<CondCodeSDNode>(SetCC.getOperand(2))->get(); 663 SetCC = DAG.getSetCC(DL, SetCC.getValueType(), SetCC.getOperand(0), 664 SetCC.getOperand(1), ISD::getSetCCInverse(CC, true)); 665 return DAG.getNode(ISD::ADD, DL, SetCC.getValueType(), SetCC, True); 666 } 667 668 // Couldn't optimize. 669 return SDValue(); 670 } 671 672 static SDValue performCMovFPCombine(SDNode *N, SelectionDAG &DAG, 673 TargetLowering::DAGCombinerInfo &DCI, 674 const MipsSubtarget &Subtarget) { 675 if (DCI.isBeforeLegalizeOps()) 676 return SDValue(); 677 678 SDValue ValueIfTrue = N->getOperand(0), ValueIfFalse = N->getOperand(2); 679 680 ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(ValueIfFalse); 681 if (!FalseC || FalseC->getZExtValue()) 682 return SDValue(); 683 684 // Since RHS (False) is 0, we swap the order of the True/False operands 685 // (obviously also inverting the condition) so that we can 686 // take advantage of conditional moves using the $0 register. 687 // Example: 688 // return (a != 0) ? x : 0; 689 // load $reg, x 690 // movz $reg, $0, a 691 unsigned Opc = (N->getOpcode() == MipsISD::CMovFP_T) ? MipsISD::CMovFP_F : 692 MipsISD::CMovFP_T; 693 694 SDValue FCC = N->getOperand(1), Glue = N->getOperand(3); 695 return DAG.getNode(Opc, SDLoc(N), ValueIfFalse.getValueType(), 696 ValueIfFalse, FCC, ValueIfTrue, Glue); 697 } 698 699 static SDValue performANDCombine(SDNode *N, SelectionDAG &DAG, 700 TargetLowering::DAGCombinerInfo &DCI, 701 const MipsSubtarget &Subtarget) { 702 // Pattern match EXT. 703 // $dst = and ((sra or srl) $src , pos), (2**size - 1) 704 // => ext $dst, $src, size, pos 705 if (DCI.isBeforeLegalizeOps() || !Subtarget.hasExtractInsert()) 706 return SDValue(); 707 708 SDValue ShiftRight = N->getOperand(0), Mask = N->getOperand(1); 709 unsigned ShiftRightOpc = ShiftRight.getOpcode(); 710 711 // Op's first operand must be a shift right. 712 if (ShiftRightOpc != ISD::SRA && ShiftRightOpc != ISD::SRL) 713 return SDValue(); 714 715 // The second operand of the shift must be an immediate. 716 ConstantSDNode *CN; 717 if (!(CN = dyn_cast<ConstantSDNode>(ShiftRight.getOperand(1)))) 718 return SDValue(); 719 720 uint64_t Pos = CN->getZExtValue(); 721 uint64_t SMPos, SMSize; 722 723 // Op's second operand must be a shifted mask. 724 if (!(CN = dyn_cast<ConstantSDNode>(Mask)) || 725 !isShiftedMask(CN->getZExtValue(), SMPos, SMSize)) 726 return SDValue(); 727 728 // Return if the shifted mask does not start at bit 0 or the sum of its size 729 // and Pos exceeds the word's size. 730 EVT ValTy = N->getValueType(0); 731 if (SMPos != 0 || Pos + SMSize > ValTy.getSizeInBits()) 732 return SDValue(); 733 734 SDLoc DL(N); 735 return DAG.getNode(MipsISD::Ext, DL, ValTy, 736 ShiftRight.getOperand(0), 737 DAG.getConstant(Pos, DL, MVT::i32), 738 DAG.getConstant(SMSize, DL, MVT::i32)); 739 } 740 741 static SDValue performORCombine(SDNode *N, SelectionDAG &DAG, 742 TargetLowering::DAGCombinerInfo &DCI, 743 const MipsSubtarget &Subtarget) { 744 // Pattern match INS. 745 // $dst = or (and $src1 , mask0), (and (shl $src, pos), mask1), 746 // where mask1 = (2**size - 1) << pos, mask0 = ~mask1 747 // => ins $dst, $src, size, pos, $src1 748 if (DCI.isBeforeLegalizeOps() || !Subtarget.hasExtractInsert()) 749 return SDValue(); 750 751 SDValue And0 = N->getOperand(0), And1 = N->getOperand(1); 752 uint64_t SMPos0, SMSize0, SMPos1, SMSize1; 753 ConstantSDNode *CN; 754 755 // See if Op's first operand matches (and $src1 , mask0). 756 if (And0.getOpcode() != ISD::AND) 757 return SDValue(); 758 759 if (!(CN = dyn_cast<ConstantSDNode>(And0.getOperand(1))) || 760 !isShiftedMask(~CN->getSExtValue(), SMPos0, SMSize0)) 761 return SDValue(); 762 763 // See if Op's second operand matches (and (shl $src, pos), mask1). 764 if (And1.getOpcode() != ISD::AND) 765 return SDValue(); 766 767 if (!(CN = dyn_cast<ConstantSDNode>(And1.getOperand(1))) || 768 !isShiftedMask(CN->getZExtValue(), SMPos1, SMSize1)) 769 return SDValue(); 770 771 // The shift masks must have the same position and size. 772 if (SMPos0 != SMPos1 || SMSize0 != SMSize1) 773 return SDValue(); 774 775 SDValue Shl = And1.getOperand(0); 776 if (Shl.getOpcode() != ISD::SHL) 777 return SDValue(); 778 779 if (!(CN = dyn_cast<ConstantSDNode>(Shl.getOperand(1)))) 780 return SDValue(); 781 782 unsigned Shamt = CN->getZExtValue(); 783 784 // Return if the shift amount and the first bit position of mask are not the 785 // same. 786 EVT ValTy = N->getValueType(0); 787 if ((Shamt != SMPos0) || (SMPos0 + SMSize0 > ValTy.getSizeInBits())) 788 return SDValue(); 789 790 SDLoc DL(N); 791 return DAG.getNode(MipsISD::Ins, DL, ValTy, Shl.getOperand(0), 792 DAG.getConstant(SMPos0, DL, MVT::i32), 793 DAG.getConstant(SMSize0, DL, MVT::i32), 794 And0.getOperand(0)); 795 } 796 797 static SDValue performADDCombine(SDNode *N, SelectionDAG &DAG, 798 TargetLowering::DAGCombinerInfo &DCI, 799 const MipsSubtarget &Subtarget) { 800 // (add v0, (add v1, abs_lo(tjt))) => (add (add v0, v1), abs_lo(tjt)) 801 802 if (DCI.isBeforeLegalizeOps()) 803 return SDValue(); 804 805 SDValue Add = N->getOperand(1); 806 807 if (Add.getOpcode() != ISD::ADD) 808 return SDValue(); 809 810 SDValue Lo = Add.getOperand(1); 811 812 if ((Lo.getOpcode() != MipsISD::Lo) || 813 (Lo.getOperand(0).getOpcode() != ISD::TargetJumpTable)) 814 return SDValue(); 815 816 EVT ValTy = N->getValueType(0); 817 SDLoc DL(N); 818 819 SDValue Add1 = DAG.getNode(ISD::ADD, DL, ValTy, N->getOperand(0), 820 Add.getOperand(0)); 821 return DAG.getNode(ISD::ADD, DL, ValTy, Add1, Lo); 822 } 823 824 static SDValue performAssertZextCombine(SDNode *N, SelectionDAG &DAG, 825 TargetLowering::DAGCombinerInfo &DCI, 826 const MipsSubtarget &Subtarget) { 827 SDValue N0 = N->getOperand(0); 828 EVT NarrowerVT = cast<VTSDNode>(N->getOperand(1))->getVT(); 829 830 if (N0.getOpcode() != ISD::TRUNCATE) 831 return SDValue(); 832 833 if (N0.getOperand(0).getOpcode() != ISD::AssertZext) 834 return SDValue(); 835 836 // fold (AssertZext (trunc (AssertZext x))) -> (trunc (AssertZext x)) 837 // if the type of the extension of the innermost AssertZext node is 838 // smaller from that of the outermost node, eg: 839 // (AssertZext:i32 (trunc:i32 (AssertZext:i64 X, i32)), i8) 840 // -> (trunc:i32 (AssertZext X, i8)) 841 SDValue WiderAssertZext = N0.getOperand(0); 842 EVT WiderVT = cast<VTSDNode>(WiderAssertZext->getOperand(1))->getVT(); 843 844 if (NarrowerVT.bitsLT(WiderVT)) { 845 SDValue NewAssertZext = DAG.getNode( 846 ISD::AssertZext, SDLoc(N), WiderAssertZext.getValueType(), 847 WiderAssertZext.getOperand(0), DAG.getValueType(NarrowerVT)); 848 return DAG.getNode(ISD::TRUNCATE, SDLoc(N), N->getValueType(0), 849 NewAssertZext); 850 } 851 852 return SDValue(); 853 } 854 855 SDValue MipsTargetLowering::PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) 856 const { 857 SelectionDAG &DAG = DCI.DAG; 858 unsigned Opc = N->getOpcode(); 859 860 switch (Opc) { 861 default: break; 862 case ISD::SDIVREM: 863 case ISD::UDIVREM: 864 return performDivRemCombine(N, DAG, DCI, Subtarget); 865 case ISD::SELECT: 866 return performSELECTCombine(N, DAG, DCI, Subtarget); 867 case MipsISD::CMovFP_F: 868 case MipsISD::CMovFP_T: 869 return performCMovFPCombine(N, DAG, DCI, Subtarget); 870 case ISD::AND: 871 return performANDCombine(N, DAG, DCI, Subtarget); 872 case ISD::OR: 873 return performORCombine(N, DAG, DCI, Subtarget); 874 case ISD::ADD: 875 return performADDCombine(N, DAG, DCI, Subtarget); 876 case ISD::AssertZext: 877 return performAssertZextCombine(N, DAG, DCI, Subtarget); 878 } 879 880 return SDValue(); 881 } 882 883 bool MipsTargetLowering::isCheapToSpeculateCttz() const { 884 return Subtarget.hasMips32(); 885 } 886 887 bool MipsTargetLowering::isCheapToSpeculateCtlz() const { 888 return Subtarget.hasMips32(); 889 } 890 891 void 892 MipsTargetLowering::LowerOperationWrapper(SDNode *N, 893 SmallVectorImpl<SDValue> &Results, 894 SelectionDAG &DAG) const { 895 SDValue Res = LowerOperation(SDValue(N, 0), DAG); 896 897 for (unsigned I = 0, E = Res->getNumValues(); I != E; ++I) 898 Results.push_back(Res.getValue(I)); 899 } 900 901 void 902 MipsTargetLowering::ReplaceNodeResults(SDNode *N, 903 SmallVectorImpl<SDValue> &Results, 904 SelectionDAG &DAG) const { 905 return LowerOperationWrapper(N, Results, DAG); 906 } 907 908 SDValue MipsTargetLowering:: 909 LowerOperation(SDValue Op, SelectionDAG &DAG) const 910 { 911 switch (Op.getOpcode()) 912 { 913 case ISD::BR_JT: return lowerBR_JT(Op, DAG); 914 case ISD::BRCOND: return lowerBRCOND(Op, DAG); 915 case ISD::ConstantPool: return lowerConstantPool(Op, DAG); 916 case ISD::GlobalAddress: return lowerGlobalAddress(Op, DAG); 917 case ISD::BlockAddress: return lowerBlockAddress(Op, DAG); 918 case ISD::GlobalTLSAddress: return lowerGlobalTLSAddress(Op, DAG); 919 case ISD::JumpTable: return lowerJumpTable(Op, DAG); 920 case ISD::SELECT: return lowerSELECT(Op, DAG); 921 case ISD::SETCC: return lowerSETCC(Op, DAG); 922 case ISD::VASTART: return lowerVASTART(Op, DAG); 923 case ISD::VAARG: return lowerVAARG(Op, DAG); 924 case ISD::FCOPYSIGN: return lowerFCOPYSIGN(Op, DAG); 925 case ISD::FRAMEADDR: return lowerFRAMEADDR(Op, DAG); 926 case ISD::RETURNADDR: return lowerRETURNADDR(Op, DAG); 927 case ISD::EH_RETURN: return lowerEH_RETURN(Op, DAG); 928 case ISD::ATOMIC_FENCE: return lowerATOMIC_FENCE(Op, DAG); 929 case ISD::SHL_PARTS: return lowerShiftLeftParts(Op, DAG); 930 case ISD::SRA_PARTS: return lowerShiftRightParts(Op, DAG, true); 931 case ISD::SRL_PARTS: return lowerShiftRightParts(Op, DAG, false); 932 case ISD::LOAD: return lowerLOAD(Op, DAG); 933 case ISD::STORE: return lowerSTORE(Op, DAG); 934 case ISD::EH_DWARF_CFA: return lowerEH_DWARF_CFA(Op, DAG); 935 case ISD::FP_TO_SINT: return lowerFP_TO_SINT(Op, DAG); 936 } 937 return SDValue(); 938 } 939 940 //===----------------------------------------------------------------------===// 941 // Lower helper functions 942 //===----------------------------------------------------------------------===// 943 944 // addLiveIn - This helper function adds the specified physical register to the 945 // MachineFunction as a live in value. It also creates a corresponding 946 // virtual register for it. 947 static unsigned 948 addLiveIn(MachineFunction &MF, unsigned PReg, const TargetRegisterClass *RC) 949 { 950 unsigned VReg = MF.getRegInfo().createVirtualRegister(RC); 951 MF.getRegInfo().addLiveIn(PReg, VReg); 952 return VReg; 953 } 954 955 static MachineBasicBlock *insertDivByZeroTrap(MachineInstr &MI, 956 MachineBasicBlock &MBB, 957 const TargetInstrInfo &TII, 958 bool Is64Bit, bool IsMicroMips) { 959 if (NoZeroDivCheck) 960 return &MBB; 961 962 // Insert instruction "teq $divisor_reg, $zero, 7". 963 MachineBasicBlock::iterator I(MI); 964 MachineInstrBuilder MIB; 965 MachineOperand &Divisor = MI.getOperand(2); 966 MIB = BuildMI(MBB, std::next(I), MI.getDebugLoc(), 967 TII.get(IsMicroMips ? Mips::TEQ_MM : Mips::TEQ)) 968 .addReg(Divisor.getReg(), getKillRegState(Divisor.isKill())) 969 .addReg(Mips::ZERO) 970 .addImm(7); 971 972 // Use the 32-bit sub-register if this is a 64-bit division. 973 if (Is64Bit) 974 MIB->getOperand(0).setSubReg(Mips::sub_32); 975 976 // Clear Divisor's kill flag. 977 Divisor.setIsKill(false); 978 979 // We would normally delete the original instruction here but in this case 980 // we only needed to inject an additional instruction rather than replace it. 981 982 return &MBB; 983 } 984 985 MachineBasicBlock * 986 MipsTargetLowering::EmitInstrWithCustomInserter(MachineInstr &MI, 987 MachineBasicBlock *BB) const { 988 switch (MI.getOpcode()) { 989 default: 990 llvm_unreachable("Unexpected instr type to insert"); 991 case Mips::ATOMIC_LOAD_ADD_I8: 992 return emitAtomicBinaryPartword(MI, BB, 1, Mips::ADDu); 993 case Mips::ATOMIC_LOAD_ADD_I16: 994 return emitAtomicBinaryPartword(MI, BB, 2, Mips::ADDu); 995 case Mips::ATOMIC_LOAD_ADD_I32: 996 return emitAtomicBinary(MI, BB, 4, Mips::ADDu); 997 case Mips::ATOMIC_LOAD_ADD_I64: 998 return emitAtomicBinary(MI, BB, 8, Mips::DADDu); 999 1000 case Mips::ATOMIC_LOAD_AND_I8: 1001 return emitAtomicBinaryPartword(MI, BB, 1, Mips::AND); 1002 case Mips::ATOMIC_LOAD_AND_I16: 1003 return emitAtomicBinaryPartword(MI, BB, 2, Mips::AND); 1004 case Mips::ATOMIC_LOAD_AND_I32: 1005 return emitAtomicBinary(MI, BB, 4, Mips::AND); 1006 case Mips::ATOMIC_LOAD_AND_I64: 1007 return emitAtomicBinary(MI, BB, 8, Mips::AND64); 1008 1009 case Mips::ATOMIC_LOAD_OR_I8: 1010 return emitAtomicBinaryPartword(MI, BB, 1, Mips::OR); 1011 case Mips::ATOMIC_LOAD_OR_I16: 1012 return emitAtomicBinaryPartword(MI, BB, 2, Mips::OR); 1013 case Mips::ATOMIC_LOAD_OR_I32: 1014 return emitAtomicBinary(MI, BB, 4, Mips::OR); 1015 case Mips::ATOMIC_LOAD_OR_I64: 1016 return emitAtomicBinary(MI, BB, 8, Mips::OR64); 1017 1018 case Mips::ATOMIC_LOAD_XOR_I8: 1019 return emitAtomicBinaryPartword(MI, BB, 1, Mips::XOR); 1020 case Mips::ATOMIC_LOAD_XOR_I16: 1021 return emitAtomicBinaryPartword(MI, BB, 2, Mips::XOR); 1022 case Mips::ATOMIC_LOAD_XOR_I32: 1023 return emitAtomicBinary(MI, BB, 4, Mips::XOR); 1024 case Mips::ATOMIC_LOAD_XOR_I64: 1025 return emitAtomicBinary(MI, BB, 8, Mips::XOR64); 1026 1027 case Mips::ATOMIC_LOAD_NAND_I8: 1028 return emitAtomicBinaryPartword(MI, BB, 1, 0, true); 1029 case Mips::ATOMIC_LOAD_NAND_I16: 1030 return emitAtomicBinaryPartword(MI, BB, 2, 0, true); 1031 case Mips::ATOMIC_LOAD_NAND_I32: 1032 return emitAtomicBinary(MI, BB, 4, 0, true); 1033 case Mips::ATOMIC_LOAD_NAND_I64: 1034 return emitAtomicBinary(MI, BB, 8, 0, true); 1035 1036 case Mips::ATOMIC_LOAD_SUB_I8: 1037 return emitAtomicBinaryPartword(MI, BB, 1, Mips::SUBu); 1038 case Mips::ATOMIC_LOAD_SUB_I16: 1039 return emitAtomicBinaryPartword(MI, BB, 2, Mips::SUBu); 1040 case Mips::ATOMIC_LOAD_SUB_I32: 1041 return emitAtomicBinary(MI, BB, 4, Mips::SUBu); 1042 case Mips::ATOMIC_LOAD_SUB_I64: 1043 return emitAtomicBinary(MI, BB, 8, Mips::DSUBu); 1044 1045 case Mips::ATOMIC_SWAP_I8: 1046 return emitAtomicBinaryPartword(MI, BB, 1, 0); 1047 case Mips::ATOMIC_SWAP_I16: 1048 return emitAtomicBinaryPartword(MI, BB, 2, 0); 1049 case Mips::ATOMIC_SWAP_I32: 1050 return emitAtomicBinary(MI, BB, 4, 0); 1051 case Mips::ATOMIC_SWAP_I64: 1052 return emitAtomicBinary(MI, BB, 8, 0); 1053 1054 case Mips::ATOMIC_CMP_SWAP_I8: 1055 return emitAtomicCmpSwapPartword(MI, BB, 1); 1056 case Mips::ATOMIC_CMP_SWAP_I16: 1057 return emitAtomicCmpSwapPartword(MI, BB, 2); 1058 case Mips::ATOMIC_CMP_SWAP_I32: 1059 return emitAtomicCmpSwap(MI, BB, 4); 1060 case Mips::ATOMIC_CMP_SWAP_I64: 1061 return emitAtomicCmpSwap(MI, BB, 8); 1062 case Mips::PseudoSDIV: 1063 case Mips::PseudoUDIV: 1064 case Mips::DIV: 1065 case Mips::DIVU: 1066 case Mips::MOD: 1067 case Mips::MODU: 1068 return insertDivByZeroTrap(MI, *BB, *Subtarget.getInstrInfo(), false, 1069 false); 1070 case Mips::SDIV_MM_Pseudo: 1071 case Mips::UDIV_MM_Pseudo: 1072 case Mips::SDIV_MM: 1073 case Mips::UDIV_MM: 1074 case Mips::DIV_MMR6: 1075 case Mips::DIVU_MMR6: 1076 case Mips::MOD_MMR6: 1077 case Mips::MODU_MMR6: 1078 return insertDivByZeroTrap(MI, *BB, *Subtarget.getInstrInfo(), false, true); 1079 case Mips::PseudoDSDIV: 1080 case Mips::PseudoDUDIV: 1081 case Mips::DDIV: 1082 case Mips::DDIVU: 1083 case Mips::DMOD: 1084 case Mips::DMODU: 1085 return insertDivByZeroTrap(MI, *BB, *Subtarget.getInstrInfo(), true, false); 1086 case Mips::DDIV_MM64R6: 1087 case Mips::DDIVU_MM64R6: 1088 case Mips::DMOD_MM64R6: 1089 case Mips::DMODU_MM64R6: 1090 return insertDivByZeroTrap(MI, *BB, *Subtarget.getInstrInfo(), true, true); 1091 case Mips::SEL_D: 1092 case Mips::SEL_D_MMR6: 1093 return emitSEL_D(MI, BB); 1094 1095 case Mips::PseudoSELECT_I: 1096 case Mips::PseudoSELECT_I64: 1097 case Mips::PseudoSELECT_S: 1098 case Mips::PseudoSELECT_D32: 1099 case Mips::PseudoSELECT_D64: 1100 return emitPseudoSELECT(MI, BB, false, Mips::BNE); 1101 case Mips::PseudoSELECTFP_F_I: 1102 case Mips::PseudoSELECTFP_F_I64: 1103 case Mips::PseudoSELECTFP_F_S: 1104 case Mips::PseudoSELECTFP_F_D32: 1105 case Mips::PseudoSELECTFP_F_D64: 1106 return emitPseudoSELECT(MI, BB, true, Mips::BC1F); 1107 case Mips::PseudoSELECTFP_T_I: 1108 case Mips::PseudoSELECTFP_T_I64: 1109 case Mips::PseudoSELECTFP_T_S: 1110 case Mips::PseudoSELECTFP_T_D32: 1111 case Mips::PseudoSELECTFP_T_D64: 1112 return emitPseudoSELECT(MI, BB, true, Mips::BC1T); 1113 } 1114 } 1115 1116 // This function also handles Mips::ATOMIC_SWAP_I32 (when BinOpcode == 0), and 1117 // Mips::ATOMIC_LOAD_NAND_I32 (when Nand == true) 1118 MachineBasicBlock *MipsTargetLowering::emitAtomicBinary(MachineInstr &MI, 1119 MachineBasicBlock *BB, 1120 unsigned Size, 1121 unsigned BinOpcode, 1122 bool Nand) const { 1123 assert((Size == 4 || Size == 8) && "Unsupported size for EmitAtomicBinary."); 1124 1125 MachineFunction *MF = BB->getParent(); 1126 MachineRegisterInfo &RegInfo = MF->getRegInfo(); 1127 const TargetRegisterClass *RC = getRegClassFor(MVT::getIntegerVT(Size * 8)); 1128 const TargetInstrInfo *TII = Subtarget.getInstrInfo(); 1129 const bool ArePtrs64bit = ABI.ArePtrs64bit(); 1130 DebugLoc DL = MI.getDebugLoc(); 1131 unsigned LL, SC, AND, NOR, ZERO, BEQ; 1132 1133 if (Size == 4) { 1134 if (isMicroMips) { 1135 LL = Mips::LL_MM; 1136 SC = Mips::SC_MM; 1137 } else { 1138 LL = Subtarget.hasMips32r6() 1139 ? (ArePtrs64bit ? Mips::LL64_R6 : Mips::LL_R6) 1140 : (ArePtrs64bit ? Mips::LL64 : Mips::LL); 1141 SC = Subtarget.hasMips32r6() 1142 ? (ArePtrs64bit ? Mips::SC64_R6 : Mips::SC_R6) 1143 : (ArePtrs64bit ? Mips::SC64 : Mips::SC); 1144 } 1145 1146 AND = Mips::AND; 1147 NOR = Mips::NOR; 1148 ZERO = Mips::ZERO; 1149 BEQ = Mips::BEQ; 1150 } else { 1151 LL = Subtarget.hasMips64r6() ? Mips::LLD_R6 : Mips::LLD; 1152 SC = Subtarget.hasMips64r6() ? Mips::SCD_R6 : Mips::SCD; 1153 AND = Mips::AND64; 1154 NOR = Mips::NOR64; 1155 ZERO = Mips::ZERO_64; 1156 BEQ = Mips::BEQ64; 1157 } 1158 1159 unsigned OldVal = MI.getOperand(0).getReg(); 1160 unsigned Ptr = MI.getOperand(1).getReg(); 1161 unsigned Incr = MI.getOperand(2).getReg(); 1162 1163 unsigned StoreVal = RegInfo.createVirtualRegister(RC); 1164 unsigned AndRes = RegInfo.createVirtualRegister(RC); 1165 unsigned Success = RegInfo.createVirtualRegister(RC); 1166 1167 // insert new blocks after the current block 1168 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 1169 MachineBasicBlock *loopMBB = MF->CreateMachineBasicBlock(LLVM_BB); 1170 MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB); 1171 MachineFunction::iterator It = ++BB->getIterator(); 1172 MF->insert(It, loopMBB); 1173 MF->insert(It, exitMBB); 1174 1175 // Transfer the remainder of BB and its successor edges to exitMBB. 1176 exitMBB->splice(exitMBB->begin(), BB, 1177 std::next(MachineBasicBlock::iterator(MI)), BB->end()); 1178 exitMBB->transferSuccessorsAndUpdatePHIs(BB); 1179 1180 // thisMBB: 1181 // ... 1182 // fallthrough --> loopMBB 1183 BB->addSuccessor(loopMBB); 1184 loopMBB->addSuccessor(loopMBB); 1185 loopMBB->addSuccessor(exitMBB); 1186 1187 // loopMBB: 1188 // ll oldval, 0(ptr) 1189 // <binop> storeval, oldval, incr 1190 // sc success, storeval, 0(ptr) 1191 // beq success, $0, loopMBB 1192 BB = loopMBB; 1193 BuildMI(BB, DL, TII->get(LL), OldVal).addReg(Ptr).addImm(0); 1194 if (Nand) { 1195 // and andres, oldval, incr 1196 // nor storeval, $0, andres 1197 BuildMI(BB, DL, TII->get(AND), AndRes).addReg(OldVal).addReg(Incr); 1198 BuildMI(BB, DL, TII->get(NOR), StoreVal).addReg(ZERO).addReg(AndRes); 1199 } else if (BinOpcode) { 1200 // <binop> storeval, oldval, incr 1201 BuildMI(BB, DL, TII->get(BinOpcode), StoreVal).addReg(OldVal).addReg(Incr); 1202 } else { 1203 StoreVal = Incr; 1204 } 1205 BuildMI(BB, DL, TII->get(SC), Success).addReg(StoreVal).addReg(Ptr).addImm(0); 1206 BuildMI(BB, DL, TII->get(BEQ)).addReg(Success).addReg(ZERO).addMBB(loopMBB); 1207 1208 MI.eraseFromParent(); // The instruction is gone now. 1209 1210 return exitMBB; 1211 } 1212 1213 MachineBasicBlock *MipsTargetLowering::emitSignExtendToI32InReg( 1214 MachineInstr &MI, MachineBasicBlock *BB, unsigned Size, unsigned DstReg, 1215 unsigned SrcReg) const { 1216 const TargetInstrInfo *TII = Subtarget.getInstrInfo(); 1217 const DebugLoc &DL = MI.getDebugLoc(); 1218 1219 if (Subtarget.hasMips32r2() && Size == 1) { 1220 BuildMI(BB, DL, TII->get(Mips::SEB), DstReg).addReg(SrcReg); 1221 return BB; 1222 } 1223 1224 if (Subtarget.hasMips32r2() && Size == 2) { 1225 BuildMI(BB, DL, TII->get(Mips::SEH), DstReg).addReg(SrcReg); 1226 return BB; 1227 } 1228 1229 MachineFunction *MF = BB->getParent(); 1230 MachineRegisterInfo &RegInfo = MF->getRegInfo(); 1231 const TargetRegisterClass *RC = getRegClassFor(MVT::i32); 1232 unsigned ScrReg = RegInfo.createVirtualRegister(RC); 1233 1234 assert(Size < 32); 1235 int64_t ShiftImm = 32 - (Size * 8); 1236 1237 BuildMI(BB, DL, TII->get(Mips::SLL), ScrReg).addReg(SrcReg).addImm(ShiftImm); 1238 BuildMI(BB, DL, TII->get(Mips::SRA), DstReg).addReg(ScrReg).addImm(ShiftImm); 1239 1240 return BB; 1241 } 1242 1243 MachineBasicBlock *MipsTargetLowering::emitAtomicBinaryPartword( 1244 MachineInstr &MI, MachineBasicBlock *BB, unsigned Size, unsigned BinOpcode, 1245 bool Nand) const { 1246 assert((Size == 1 || Size == 2) && 1247 "Unsupported size for EmitAtomicBinaryPartial."); 1248 1249 MachineFunction *MF = BB->getParent(); 1250 MachineRegisterInfo &RegInfo = MF->getRegInfo(); 1251 const TargetRegisterClass *RC = getRegClassFor(MVT::i32); 1252 const bool ArePtrs64bit = ABI.ArePtrs64bit(); 1253 const TargetRegisterClass *RCp = 1254 getRegClassFor(ArePtrs64bit ? MVT::i64 : MVT::i32); 1255 const TargetInstrInfo *TII = Subtarget.getInstrInfo(); 1256 DebugLoc DL = MI.getDebugLoc(); 1257 1258 unsigned Dest = MI.getOperand(0).getReg(); 1259 unsigned Ptr = MI.getOperand(1).getReg(); 1260 unsigned Incr = MI.getOperand(2).getReg(); 1261 1262 unsigned AlignedAddr = RegInfo.createVirtualRegister(RCp); 1263 unsigned ShiftAmt = RegInfo.createVirtualRegister(RC); 1264 unsigned Mask = RegInfo.createVirtualRegister(RC); 1265 unsigned Mask2 = RegInfo.createVirtualRegister(RC); 1266 unsigned NewVal = RegInfo.createVirtualRegister(RC); 1267 unsigned OldVal = RegInfo.createVirtualRegister(RC); 1268 unsigned Incr2 = RegInfo.createVirtualRegister(RC); 1269 unsigned MaskLSB2 = RegInfo.createVirtualRegister(RCp); 1270 unsigned PtrLSB2 = RegInfo.createVirtualRegister(RC); 1271 unsigned MaskUpper = RegInfo.createVirtualRegister(RC); 1272 unsigned AndRes = RegInfo.createVirtualRegister(RC); 1273 unsigned BinOpRes = RegInfo.createVirtualRegister(RC); 1274 unsigned MaskedOldVal0 = RegInfo.createVirtualRegister(RC); 1275 unsigned StoreVal = RegInfo.createVirtualRegister(RC); 1276 unsigned MaskedOldVal1 = RegInfo.createVirtualRegister(RC); 1277 unsigned SrlRes = RegInfo.createVirtualRegister(RC); 1278 unsigned Success = RegInfo.createVirtualRegister(RC); 1279 1280 unsigned LL, SC; 1281 if (isMicroMips) { 1282 LL = Mips::LL_MM; 1283 SC = Mips::SC_MM; 1284 } else { 1285 LL = Subtarget.hasMips32r6() ? (ArePtrs64bit ? Mips::LL64_R6 : Mips::LL_R6) 1286 : (ArePtrs64bit ? Mips::LL64 : Mips::LL); 1287 SC = Subtarget.hasMips32r6() ? (ArePtrs64bit ? Mips::SC64_R6 : Mips::SC_R6) 1288 : (ArePtrs64bit ? Mips::SC64 : Mips::SC); 1289 } 1290 1291 // insert new blocks after the current block 1292 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 1293 MachineBasicBlock *loopMBB = MF->CreateMachineBasicBlock(LLVM_BB); 1294 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(LLVM_BB); 1295 MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB); 1296 MachineFunction::iterator It = ++BB->getIterator(); 1297 MF->insert(It, loopMBB); 1298 MF->insert(It, sinkMBB); 1299 MF->insert(It, exitMBB); 1300 1301 // Transfer the remainder of BB and its successor edges to exitMBB. 1302 exitMBB->splice(exitMBB->begin(), BB, 1303 std::next(MachineBasicBlock::iterator(MI)), BB->end()); 1304 exitMBB->transferSuccessorsAndUpdatePHIs(BB); 1305 1306 BB->addSuccessor(loopMBB); 1307 loopMBB->addSuccessor(loopMBB); 1308 loopMBB->addSuccessor(sinkMBB); 1309 sinkMBB->addSuccessor(exitMBB); 1310 1311 // thisMBB: 1312 // addiu masklsb2,$0,-4 # 0xfffffffc 1313 // and alignedaddr,ptr,masklsb2 1314 // andi ptrlsb2,ptr,3 1315 // sll shiftamt,ptrlsb2,3 1316 // ori maskupper,$0,255 # 0xff 1317 // sll mask,maskupper,shiftamt 1318 // nor mask2,$0,mask 1319 // sll incr2,incr,shiftamt 1320 1321 int64_t MaskImm = (Size == 1) ? 255 : 65535; 1322 BuildMI(BB, DL, TII->get(ABI.GetPtrAddiuOp()), MaskLSB2) 1323 .addReg(ABI.GetNullPtr()).addImm(-4); 1324 BuildMI(BB, DL, TII->get(ABI.GetPtrAndOp()), AlignedAddr) 1325 .addReg(Ptr).addReg(MaskLSB2); 1326 BuildMI(BB, DL, TII->get(Mips::ANDi), PtrLSB2) 1327 .addReg(Ptr, 0, ArePtrs64bit ? Mips::sub_32 : 0).addImm(3); 1328 if (Subtarget.isLittle()) { 1329 BuildMI(BB, DL, TII->get(Mips::SLL), ShiftAmt).addReg(PtrLSB2).addImm(3); 1330 } else { 1331 unsigned Off = RegInfo.createVirtualRegister(RC); 1332 BuildMI(BB, DL, TII->get(Mips::XORi), Off) 1333 .addReg(PtrLSB2).addImm((Size == 1) ? 3 : 2); 1334 BuildMI(BB, DL, TII->get(Mips::SLL), ShiftAmt).addReg(Off).addImm(3); 1335 } 1336 BuildMI(BB, DL, TII->get(Mips::ORi), MaskUpper) 1337 .addReg(Mips::ZERO).addImm(MaskImm); 1338 BuildMI(BB, DL, TII->get(Mips::SLLV), Mask) 1339 .addReg(MaskUpper).addReg(ShiftAmt); 1340 BuildMI(BB, DL, TII->get(Mips::NOR), Mask2).addReg(Mips::ZERO).addReg(Mask); 1341 BuildMI(BB, DL, TII->get(Mips::SLLV), Incr2).addReg(Incr).addReg(ShiftAmt); 1342 1343 // atomic.load.binop 1344 // loopMBB: 1345 // ll oldval,0(alignedaddr) 1346 // binop binopres,oldval,incr2 1347 // and newval,binopres,mask 1348 // and maskedoldval0,oldval,mask2 1349 // or storeval,maskedoldval0,newval 1350 // sc success,storeval,0(alignedaddr) 1351 // beq success,$0,loopMBB 1352 1353 // atomic.swap 1354 // loopMBB: 1355 // ll oldval,0(alignedaddr) 1356 // and newval,incr2,mask 1357 // and maskedoldval0,oldval,mask2 1358 // or storeval,maskedoldval0,newval 1359 // sc success,storeval,0(alignedaddr) 1360 // beq success,$0,loopMBB 1361 1362 BB = loopMBB; 1363 BuildMI(BB, DL, TII->get(LL), OldVal).addReg(AlignedAddr).addImm(0); 1364 if (Nand) { 1365 // and andres, oldval, incr2 1366 // nor binopres, $0, andres 1367 // and newval, binopres, mask 1368 BuildMI(BB, DL, TII->get(Mips::AND), AndRes).addReg(OldVal).addReg(Incr2); 1369 BuildMI(BB, DL, TII->get(Mips::NOR), BinOpRes) 1370 .addReg(Mips::ZERO).addReg(AndRes); 1371 BuildMI(BB, DL, TII->get(Mips::AND), NewVal).addReg(BinOpRes).addReg(Mask); 1372 } else if (BinOpcode) { 1373 // <binop> binopres, oldval, incr2 1374 // and newval, binopres, mask 1375 BuildMI(BB, DL, TII->get(BinOpcode), BinOpRes).addReg(OldVal).addReg(Incr2); 1376 BuildMI(BB, DL, TII->get(Mips::AND), NewVal).addReg(BinOpRes).addReg(Mask); 1377 } else { // atomic.swap 1378 // and newval, incr2, mask 1379 BuildMI(BB, DL, TII->get(Mips::AND), NewVal).addReg(Incr2).addReg(Mask); 1380 } 1381 1382 BuildMI(BB, DL, TII->get(Mips::AND), MaskedOldVal0) 1383 .addReg(OldVal).addReg(Mask2); 1384 BuildMI(BB, DL, TII->get(Mips::OR), StoreVal) 1385 .addReg(MaskedOldVal0).addReg(NewVal); 1386 BuildMI(BB, DL, TII->get(SC), Success) 1387 .addReg(StoreVal).addReg(AlignedAddr).addImm(0); 1388 BuildMI(BB, DL, TII->get(Mips::BEQ)) 1389 .addReg(Success).addReg(Mips::ZERO).addMBB(loopMBB); 1390 1391 // sinkMBB: 1392 // and maskedoldval1,oldval,mask 1393 // srl srlres,maskedoldval1,shiftamt 1394 // sign_extend dest,srlres 1395 BB = sinkMBB; 1396 1397 BuildMI(BB, DL, TII->get(Mips::AND), MaskedOldVal1) 1398 .addReg(OldVal).addReg(Mask); 1399 BuildMI(BB, DL, TII->get(Mips::SRLV), SrlRes) 1400 .addReg(MaskedOldVal1).addReg(ShiftAmt); 1401 BB = emitSignExtendToI32InReg(MI, BB, Size, Dest, SrlRes); 1402 1403 MI.eraseFromParent(); // The instruction is gone now. 1404 1405 return exitMBB; 1406 } 1407 1408 MachineBasicBlock *MipsTargetLowering::emitAtomicCmpSwap(MachineInstr &MI, 1409 MachineBasicBlock *BB, 1410 unsigned Size) const { 1411 assert((Size == 4 || Size == 8) && "Unsupported size for EmitAtomicCmpSwap."); 1412 1413 MachineFunction *MF = BB->getParent(); 1414 MachineRegisterInfo &RegInfo = MF->getRegInfo(); 1415 const TargetRegisterClass *RC = getRegClassFor(MVT::getIntegerVT(Size * 8)); 1416 const TargetInstrInfo *TII = Subtarget.getInstrInfo(); 1417 const bool ArePtrs64bit = ABI.ArePtrs64bit(); 1418 DebugLoc DL = MI.getDebugLoc(); 1419 unsigned LL, SC, ZERO, BNE, BEQ; 1420 1421 if (Size == 4) { 1422 if (isMicroMips) { 1423 LL = Mips::LL_MM; 1424 SC = Mips::SC_MM; 1425 } else { 1426 LL = Subtarget.hasMips32r6() 1427 ? (ArePtrs64bit ? Mips::LL64_R6 : Mips::LL_R6) 1428 : (ArePtrs64bit ? Mips::LL64 : Mips::LL); 1429 SC = Subtarget.hasMips32r6() 1430 ? (ArePtrs64bit ? Mips::SC64_R6 : Mips::SC_R6) 1431 : (ArePtrs64bit ? Mips::SC64 : Mips::SC); 1432 } 1433 1434 ZERO = Mips::ZERO; 1435 BNE = Mips::BNE; 1436 BEQ = Mips::BEQ; 1437 } else { 1438 LL = Subtarget.hasMips64r6() ? Mips::LLD_R6 : Mips::LLD; 1439 SC = Subtarget.hasMips64r6() ? Mips::SCD_R6 : Mips::SCD; 1440 ZERO = Mips::ZERO_64; 1441 BNE = Mips::BNE64; 1442 BEQ = Mips::BEQ64; 1443 } 1444 1445 unsigned Dest = MI.getOperand(0).getReg(); 1446 unsigned Ptr = MI.getOperand(1).getReg(); 1447 unsigned OldVal = MI.getOperand(2).getReg(); 1448 unsigned NewVal = MI.getOperand(3).getReg(); 1449 1450 unsigned Success = RegInfo.createVirtualRegister(RC); 1451 1452 // insert new blocks after the current block 1453 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 1454 MachineBasicBlock *loop1MBB = MF->CreateMachineBasicBlock(LLVM_BB); 1455 MachineBasicBlock *loop2MBB = MF->CreateMachineBasicBlock(LLVM_BB); 1456 MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB); 1457 MachineFunction::iterator It = ++BB->getIterator(); 1458 MF->insert(It, loop1MBB); 1459 MF->insert(It, loop2MBB); 1460 MF->insert(It, exitMBB); 1461 1462 // Transfer the remainder of BB and its successor edges to exitMBB. 1463 exitMBB->splice(exitMBB->begin(), BB, 1464 std::next(MachineBasicBlock::iterator(MI)), BB->end()); 1465 exitMBB->transferSuccessorsAndUpdatePHIs(BB); 1466 1467 // thisMBB: 1468 // ... 1469 // fallthrough --> loop1MBB 1470 BB->addSuccessor(loop1MBB); 1471 loop1MBB->addSuccessor(exitMBB); 1472 loop1MBB->addSuccessor(loop2MBB); 1473 loop2MBB->addSuccessor(loop1MBB); 1474 loop2MBB->addSuccessor(exitMBB); 1475 1476 // loop1MBB: 1477 // ll dest, 0(ptr) 1478 // bne dest, oldval, exitMBB 1479 BB = loop1MBB; 1480 BuildMI(BB, DL, TII->get(LL), Dest).addReg(Ptr).addImm(0); 1481 BuildMI(BB, DL, TII->get(BNE)) 1482 .addReg(Dest).addReg(OldVal).addMBB(exitMBB); 1483 1484 // loop2MBB: 1485 // sc success, newval, 0(ptr) 1486 // beq success, $0, loop1MBB 1487 BB = loop2MBB; 1488 BuildMI(BB, DL, TII->get(SC), Success) 1489 .addReg(NewVal).addReg(Ptr).addImm(0); 1490 BuildMI(BB, DL, TII->get(BEQ)) 1491 .addReg(Success).addReg(ZERO).addMBB(loop1MBB); 1492 1493 MI.eraseFromParent(); // The instruction is gone now. 1494 1495 return exitMBB; 1496 } 1497 1498 MachineBasicBlock *MipsTargetLowering::emitAtomicCmpSwapPartword( 1499 MachineInstr &MI, MachineBasicBlock *BB, unsigned Size) const { 1500 assert((Size == 1 || Size == 2) && 1501 "Unsupported size for EmitAtomicCmpSwapPartial."); 1502 1503 MachineFunction *MF = BB->getParent(); 1504 MachineRegisterInfo &RegInfo = MF->getRegInfo(); 1505 const TargetRegisterClass *RC = getRegClassFor(MVT::i32); 1506 const bool ArePtrs64bit = ABI.ArePtrs64bit(); 1507 const TargetRegisterClass *RCp = 1508 getRegClassFor(ArePtrs64bit ? MVT::i64 : MVT::i32); 1509 const TargetInstrInfo *TII = Subtarget.getInstrInfo(); 1510 DebugLoc DL = MI.getDebugLoc(); 1511 1512 unsigned Dest = MI.getOperand(0).getReg(); 1513 unsigned Ptr = MI.getOperand(1).getReg(); 1514 unsigned CmpVal = MI.getOperand(2).getReg(); 1515 unsigned NewVal = MI.getOperand(3).getReg(); 1516 1517 unsigned AlignedAddr = RegInfo.createVirtualRegister(RCp); 1518 unsigned ShiftAmt = RegInfo.createVirtualRegister(RC); 1519 unsigned Mask = RegInfo.createVirtualRegister(RC); 1520 unsigned Mask2 = RegInfo.createVirtualRegister(RC); 1521 unsigned ShiftedCmpVal = RegInfo.createVirtualRegister(RC); 1522 unsigned OldVal = RegInfo.createVirtualRegister(RC); 1523 unsigned MaskedOldVal0 = RegInfo.createVirtualRegister(RC); 1524 unsigned ShiftedNewVal = RegInfo.createVirtualRegister(RC); 1525 unsigned MaskLSB2 = RegInfo.createVirtualRegister(RCp); 1526 unsigned PtrLSB2 = RegInfo.createVirtualRegister(RC); 1527 unsigned MaskUpper = RegInfo.createVirtualRegister(RC); 1528 unsigned MaskedCmpVal = RegInfo.createVirtualRegister(RC); 1529 unsigned MaskedNewVal = RegInfo.createVirtualRegister(RC); 1530 unsigned MaskedOldVal1 = RegInfo.createVirtualRegister(RC); 1531 unsigned StoreVal = RegInfo.createVirtualRegister(RC); 1532 unsigned SrlRes = RegInfo.createVirtualRegister(RC); 1533 unsigned Success = RegInfo.createVirtualRegister(RC); 1534 unsigned LL, SC; 1535 1536 if (isMicroMips) { 1537 LL = Mips::LL_MM; 1538 SC = Mips::SC_MM; 1539 } else { 1540 LL = Subtarget.hasMips32r6() ? (ArePtrs64bit ? Mips::LL64_R6 : Mips::LL_R6) 1541 : (ArePtrs64bit ? Mips::LL64 : Mips::LL); 1542 SC = Subtarget.hasMips32r6() ? (ArePtrs64bit ? Mips::SC64_R6 : Mips::SC_R6) 1543 : (ArePtrs64bit ? Mips::SC64 : Mips::SC); 1544 } 1545 1546 // insert new blocks after the current block 1547 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 1548 MachineBasicBlock *loop1MBB = MF->CreateMachineBasicBlock(LLVM_BB); 1549 MachineBasicBlock *loop2MBB = MF->CreateMachineBasicBlock(LLVM_BB); 1550 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(LLVM_BB); 1551 MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB); 1552 MachineFunction::iterator It = ++BB->getIterator(); 1553 MF->insert(It, loop1MBB); 1554 MF->insert(It, loop2MBB); 1555 MF->insert(It, sinkMBB); 1556 MF->insert(It, exitMBB); 1557 1558 // Transfer the remainder of BB and its successor edges to exitMBB. 1559 exitMBB->splice(exitMBB->begin(), BB, 1560 std::next(MachineBasicBlock::iterator(MI)), BB->end()); 1561 exitMBB->transferSuccessorsAndUpdatePHIs(BB); 1562 1563 BB->addSuccessor(loop1MBB); 1564 loop1MBB->addSuccessor(sinkMBB); 1565 loop1MBB->addSuccessor(loop2MBB); 1566 loop2MBB->addSuccessor(loop1MBB); 1567 loop2MBB->addSuccessor(sinkMBB); 1568 sinkMBB->addSuccessor(exitMBB); 1569 1570 // FIXME: computation of newval2 can be moved to loop2MBB. 1571 // thisMBB: 1572 // addiu masklsb2,$0,-4 # 0xfffffffc 1573 // and alignedaddr,ptr,masklsb2 1574 // andi ptrlsb2,ptr,3 1575 // xori ptrlsb2,ptrlsb2,3 # Only for BE 1576 // sll shiftamt,ptrlsb2,3 1577 // ori maskupper,$0,255 # 0xff 1578 // sll mask,maskupper,shiftamt 1579 // nor mask2,$0,mask 1580 // andi maskedcmpval,cmpval,255 1581 // sll shiftedcmpval,maskedcmpval,shiftamt 1582 // andi maskednewval,newval,255 1583 // sll shiftednewval,maskednewval,shiftamt 1584 int64_t MaskImm = (Size == 1) ? 255 : 65535; 1585 BuildMI(BB, DL, TII->get(ArePtrs64bit ? Mips::DADDiu : Mips::ADDiu), MaskLSB2) 1586 .addReg(ABI.GetNullPtr()).addImm(-4); 1587 BuildMI(BB, DL, TII->get(ArePtrs64bit ? Mips::AND64 : Mips::AND), AlignedAddr) 1588 .addReg(Ptr).addReg(MaskLSB2); 1589 BuildMI(BB, DL, TII->get(Mips::ANDi), PtrLSB2) 1590 .addReg(Ptr, 0, ArePtrs64bit ? Mips::sub_32 : 0).addImm(3); 1591 if (Subtarget.isLittle()) { 1592 BuildMI(BB, DL, TII->get(Mips::SLL), ShiftAmt).addReg(PtrLSB2).addImm(3); 1593 } else { 1594 unsigned Off = RegInfo.createVirtualRegister(RC); 1595 BuildMI(BB, DL, TII->get(Mips::XORi), Off) 1596 .addReg(PtrLSB2).addImm((Size == 1) ? 3 : 2); 1597 BuildMI(BB, DL, TII->get(Mips::SLL), ShiftAmt).addReg(Off).addImm(3); 1598 } 1599 BuildMI(BB, DL, TII->get(Mips::ORi), MaskUpper) 1600 .addReg(Mips::ZERO).addImm(MaskImm); 1601 BuildMI(BB, DL, TII->get(Mips::SLLV), Mask) 1602 .addReg(MaskUpper).addReg(ShiftAmt); 1603 BuildMI(BB, DL, TII->get(Mips::NOR), Mask2).addReg(Mips::ZERO).addReg(Mask); 1604 BuildMI(BB, DL, TII->get(Mips::ANDi), MaskedCmpVal) 1605 .addReg(CmpVal).addImm(MaskImm); 1606 BuildMI(BB, DL, TII->get(Mips::SLLV), ShiftedCmpVal) 1607 .addReg(MaskedCmpVal).addReg(ShiftAmt); 1608 BuildMI(BB, DL, TII->get(Mips::ANDi), MaskedNewVal) 1609 .addReg(NewVal).addImm(MaskImm); 1610 BuildMI(BB, DL, TII->get(Mips::SLLV), ShiftedNewVal) 1611 .addReg(MaskedNewVal).addReg(ShiftAmt); 1612 1613 // loop1MBB: 1614 // ll oldval,0(alginedaddr) 1615 // and maskedoldval0,oldval,mask 1616 // bne maskedoldval0,shiftedcmpval,sinkMBB 1617 BB = loop1MBB; 1618 BuildMI(BB, DL, TII->get(LL), OldVal).addReg(AlignedAddr).addImm(0); 1619 BuildMI(BB, DL, TII->get(Mips::AND), MaskedOldVal0) 1620 .addReg(OldVal).addReg(Mask); 1621 BuildMI(BB, DL, TII->get(Mips::BNE)) 1622 .addReg(MaskedOldVal0).addReg(ShiftedCmpVal).addMBB(sinkMBB); 1623 1624 // loop2MBB: 1625 // and maskedoldval1,oldval,mask2 1626 // or storeval,maskedoldval1,shiftednewval 1627 // sc success,storeval,0(alignedaddr) 1628 // beq success,$0,loop1MBB 1629 BB = loop2MBB; 1630 BuildMI(BB, DL, TII->get(Mips::AND), MaskedOldVal1) 1631 .addReg(OldVal).addReg(Mask2); 1632 BuildMI(BB, DL, TII->get(Mips::OR), StoreVal) 1633 .addReg(MaskedOldVal1).addReg(ShiftedNewVal); 1634 BuildMI(BB, DL, TII->get(SC), Success) 1635 .addReg(StoreVal).addReg(AlignedAddr).addImm(0); 1636 BuildMI(BB, DL, TII->get(Mips::BEQ)) 1637 .addReg(Success).addReg(Mips::ZERO).addMBB(loop1MBB); 1638 1639 // sinkMBB: 1640 // srl srlres,maskedoldval0,shiftamt 1641 // sign_extend dest,srlres 1642 BB = sinkMBB; 1643 1644 BuildMI(BB, DL, TII->get(Mips::SRLV), SrlRes) 1645 .addReg(MaskedOldVal0).addReg(ShiftAmt); 1646 BB = emitSignExtendToI32InReg(MI, BB, Size, Dest, SrlRes); 1647 1648 MI.eraseFromParent(); // The instruction is gone now. 1649 1650 return exitMBB; 1651 } 1652 1653 MachineBasicBlock *MipsTargetLowering::emitSEL_D(MachineInstr &MI, 1654 MachineBasicBlock *BB) const { 1655 MachineFunction *MF = BB->getParent(); 1656 const TargetRegisterInfo *TRI = Subtarget.getRegisterInfo(); 1657 const TargetInstrInfo *TII = Subtarget.getInstrInfo(); 1658 MachineRegisterInfo &RegInfo = MF->getRegInfo(); 1659 DebugLoc DL = MI.getDebugLoc(); 1660 MachineBasicBlock::iterator II(MI); 1661 1662 unsigned Fc = MI.getOperand(1).getReg(); 1663 const auto &FGR64RegClass = TRI->getRegClass(Mips::FGR64RegClassID); 1664 1665 unsigned Fc2 = RegInfo.createVirtualRegister(FGR64RegClass); 1666 1667 BuildMI(*BB, II, DL, TII->get(Mips::SUBREG_TO_REG), Fc2) 1668 .addImm(0) 1669 .addReg(Fc) 1670 .addImm(Mips::sub_lo); 1671 1672 // We don't erase the original instruction, we just replace the condition 1673 // register with the 64-bit super-register. 1674 MI.getOperand(1).setReg(Fc2); 1675 1676 return BB; 1677 } 1678 1679 //===----------------------------------------------------------------------===// 1680 // Misc Lower Operation implementation 1681 //===----------------------------------------------------------------------===// 1682 SDValue MipsTargetLowering::lowerBR_JT(SDValue Op, SelectionDAG &DAG) const { 1683 SDValue Chain = Op.getOperand(0); 1684 SDValue Table = Op.getOperand(1); 1685 SDValue Index = Op.getOperand(2); 1686 SDLoc DL(Op); 1687 auto &TD = DAG.getDataLayout(); 1688 EVT PTy = getPointerTy(TD); 1689 unsigned EntrySize = 1690 DAG.getMachineFunction().getJumpTableInfo()->getEntrySize(TD); 1691 1692 Index = DAG.getNode(ISD::MUL, DL, PTy, Index, 1693 DAG.getConstant(EntrySize, DL, PTy)); 1694 SDValue Addr = DAG.getNode(ISD::ADD, DL, PTy, Index, Table); 1695 1696 EVT MemVT = EVT::getIntegerVT(*DAG.getContext(), EntrySize * 8); 1697 Addr = DAG.getExtLoad( 1698 ISD::SEXTLOAD, DL, PTy, Chain, Addr, 1699 MachinePointerInfo::getJumpTable(DAG.getMachineFunction()), MemVT); 1700 Chain = Addr.getValue(1); 1701 1702 if (isPositionIndependent() || ABI.IsN64()) { 1703 // For PIC, the sequence is: 1704 // BRIND(load(Jumptable + index) + RelocBase) 1705 // RelocBase can be JumpTable, GOT or some sort of global base. 1706 Addr = DAG.getNode(ISD::ADD, DL, PTy, Addr, 1707 getPICJumpTableRelocBase(Table, DAG)); 1708 } 1709 1710 return DAG.getNode(ISD::BRIND, DL, MVT::Other, Chain, Addr); 1711 } 1712 1713 SDValue MipsTargetLowering::lowerBRCOND(SDValue Op, SelectionDAG &DAG) const { 1714 // The first operand is the chain, the second is the condition, the third is 1715 // the block to branch to if the condition is true. 1716 SDValue Chain = Op.getOperand(0); 1717 SDValue Dest = Op.getOperand(2); 1718 SDLoc DL(Op); 1719 1720 assert(!Subtarget.hasMips32r6() && !Subtarget.hasMips64r6()); 1721 SDValue CondRes = createFPCmp(DAG, Op.getOperand(1)); 1722 1723 // Return if flag is not set by a floating point comparison. 1724 if (CondRes.getOpcode() != MipsISD::FPCmp) 1725 return Op; 1726 1727 SDValue CCNode = CondRes.getOperand(2); 1728 Mips::CondCode CC = 1729 (Mips::CondCode)cast<ConstantSDNode>(CCNode)->getZExtValue(); 1730 unsigned Opc = invertFPCondCodeUser(CC) ? Mips::BRANCH_F : Mips::BRANCH_T; 1731 SDValue BrCode = DAG.getConstant(Opc, DL, MVT::i32); 1732 SDValue FCC0 = DAG.getRegister(Mips::FCC0, MVT::i32); 1733 return DAG.getNode(MipsISD::FPBrcond, DL, Op.getValueType(), Chain, BrCode, 1734 FCC0, Dest, CondRes); 1735 } 1736 1737 SDValue MipsTargetLowering:: 1738 lowerSELECT(SDValue Op, SelectionDAG &DAG) const 1739 { 1740 assert(!Subtarget.hasMips32r6() && !Subtarget.hasMips64r6()); 1741 SDValue Cond = createFPCmp(DAG, Op.getOperand(0)); 1742 1743 // Return if flag is not set by a floating point comparison. 1744 if (Cond.getOpcode() != MipsISD::FPCmp) 1745 return Op; 1746 1747 return createCMovFP(DAG, Cond, Op.getOperand(1), Op.getOperand(2), 1748 SDLoc(Op)); 1749 } 1750 1751 SDValue MipsTargetLowering::lowerSETCC(SDValue Op, SelectionDAG &DAG) const { 1752 assert(!Subtarget.hasMips32r6() && !Subtarget.hasMips64r6()); 1753 SDValue Cond = createFPCmp(DAG, Op); 1754 1755 assert(Cond.getOpcode() == MipsISD::FPCmp && 1756 "Floating point operand expected."); 1757 1758 SDLoc DL(Op); 1759 SDValue True = DAG.getConstant(1, DL, MVT::i32); 1760 SDValue False = DAG.getConstant(0, DL, MVT::i32); 1761 1762 return createCMovFP(DAG, Cond, True, False, DL); 1763 } 1764 1765 SDValue MipsTargetLowering::lowerGlobalAddress(SDValue Op, 1766 SelectionDAG &DAG) const { 1767 EVT Ty = Op.getValueType(); 1768 GlobalAddressSDNode *N = cast<GlobalAddressSDNode>(Op); 1769 const GlobalValue *GV = N->getGlobal(); 1770 1771 if (!isPositionIndependent() && !ABI.IsN64()) { 1772 const MipsTargetObjectFile *TLOF = 1773 static_cast<const MipsTargetObjectFile *>( 1774 getTargetMachine().getObjFileLowering()); 1775 if (TLOF->IsGlobalInSmallSection(GV, getTargetMachine())) 1776 // %gp_rel relocation 1777 return getAddrGPRel(N, SDLoc(N), Ty, DAG); 1778 1779 // %hi/%lo relocation 1780 return getAddrNonPIC(N, SDLoc(N), Ty, DAG); 1781 } 1782 1783 // Every other architecture would use shouldAssumeDSOLocal in here, but 1784 // mips is special. 1785 // * In PIC code mips requires got loads even for local statics! 1786 // * To save on got entries, for local statics the got entry contains the 1787 // page and an additional add instruction takes care of the low bits. 1788 // * It is legal to access a hidden symbol with a non hidden undefined, 1789 // so one cannot guarantee that all access to a hidden symbol will know 1790 // it is hidden. 1791 // * Mips linkers don't support creating a page and a full got entry for 1792 // the same symbol. 1793 // * Given all that, we have to use a full got entry for hidden symbols :-( 1794 if (GV->hasLocalLinkage()) 1795 return getAddrLocal(N, SDLoc(N), Ty, DAG, ABI.IsN32() || ABI.IsN64()); 1796 1797 if (LargeGOT) 1798 return getAddrGlobalLargeGOT( 1799 N, SDLoc(N), Ty, DAG, MipsII::MO_GOT_HI16, MipsII::MO_GOT_LO16, 1800 DAG.getEntryNode(), 1801 MachinePointerInfo::getGOT(DAG.getMachineFunction())); 1802 1803 return getAddrGlobal( 1804 N, SDLoc(N), Ty, DAG, 1805 (ABI.IsN32() || ABI.IsN64()) ? MipsII::MO_GOT_DISP : MipsII::MO_GOT, 1806 DAG.getEntryNode(), MachinePointerInfo::getGOT(DAG.getMachineFunction())); 1807 } 1808 1809 SDValue MipsTargetLowering::lowerBlockAddress(SDValue Op, 1810 SelectionDAG &DAG) const { 1811 BlockAddressSDNode *N = cast<BlockAddressSDNode>(Op); 1812 EVT Ty = Op.getValueType(); 1813 1814 if (!isPositionIndependent() && !ABI.IsN64()) 1815 return getAddrNonPIC(N, SDLoc(N), Ty, DAG); 1816 1817 return getAddrLocal(N, SDLoc(N), Ty, DAG, ABI.IsN32() || ABI.IsN64()); 1818 } 1819 1820 SDValue MipsTargetLowering:: 1821 lowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const 1822 { 1823 // If the relocation model is PIC, use the General Dynamic TLS Model or 1824 // Local Dynamic TLS model, otherwise use the Initial Exec or 1825 // Local Exec TLS Model. 1826 1827 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op); 1828 if (DAG.getTarget().Options.EmulatedTLS) 1829 return LowerToTLSEmulatedModel(GA, DAG); 1830 1831 SDLoc DL(GA); 1832 const GlobalValue *GV = GA->getGlobal(); 1833 EVT PtrVT = getPointerTy(DAG.getDataLayout()); 1834 1835 TLSModel::Model model = getTargetMachine().getTLSModel(GV); 1836 1837 if (model == TLSModel::GeneralDynamic || model == TLSModel::LocalDynamic) { 1838 // General Dynamic and Local Dynamic TLS Model. 1839 unsigned Flag = (model == TLSModel::LocalDynamic) ? MipsII::MO_TLSLDM 1840 : MipsII::MO_TLSGD; 1841 1842 SDValue TGA = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, Flag); 1843 SDValue Argument = DAG.getNode(MipsISD::Wrapper, DL, PtrVT, 1844 getGlobalReg(DAG, PtrVT), TGA); 1845 unsigned PtrSize = PtrVT.getSizeInBits(); 1846 IntegerType *PtrTy = Type::getIntNTy(*DAG.getContext(), PtrSize); 1847 1848 SDValue TlsGetAddr = DAG.getExternalSymbol("__tls_get_addr", PtrVT); 1849 1850 ArgListTy Args; 1851 ArgListEntry Entry; 1852 Entry.Node = Argument; 1853 Entry.Ty = PtrTy; 1854 Args.push_back(Entry); 1855 1856 TargetLowering::CallLoweringInfo CLI(DAG); 1857 CLI.setDebugLoc(DL).setChain(DAG.getEntryNode()) 1858 .setCallee(CallingConv::C, PtrTy, TlsGetAddr, std::move(Args)); 1859 std::pair<SDValue, SDValue> CallResult = LowerCallTo(CLI); 1860 1861 SDValue Ret = CallResult.first; 1862 1863 if (model != TLSModel::LocalDynamic) 1864 return Ret; 1865 1866 SDValue TGAHi = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, 1867 MipsII::MO_DTPREL_HI); 1868 SDValue Hi = DAG.getNode(MipsISD::Hi, DL, PtrVT, TGAHi); 1869 SDValue TGALo = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, 1870 MipsII::MO_DTPREL_LO); 1871 SDValue Lo = DAG.getNode(MipsISD::Lo, DL, PtrVT, TGALo); 1872 SDValue Add = DAG.getNode(ISD::ADD, DL, PtrVT, Hi, Ret); 1873 return DAG.getNode(ISD::ADD, DL, PtrVT, Add, Lo); 1874 } 1875 1876 SDValue Offset; 1877 if (model == TLSModel::InitialExec) { 1878 // Initial Exec TLS Model 1879 SDValue TGA = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, 1880 MipsII::MO_GOTTPREL); 1881 TGA = DAG.getNode(MipsISD::Wrapper, DL, PtrVT, getGlobalReg(DAG, PtrVT), 1882 TGA); 1883 Offset = 1884 DAG.getLoad(PtrVT, DL, DAG.getEntryNode(), TGA, MachinePointerInfo()); 1885 } else { 1886 // Local Exec TLS Model 1887 assert(model == TLSModel::LocalExec); 1888 SDValue TGAHi = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, 1889 MipsII::MO_TPREL_HI); 1890 SDValue TGALo = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, 1891 MipsII::MO_TPREL_LO); 1892 SDValue Hi = DAG.getNode(MipsISD::Hi, DL, PtrVT, TGAHi); 1893 SDValue Lo = DAG.getNode(MipsISD::Lo, DL, PtrVT, TGALo); 1894 Offset = DAG.getNode(ISD::ADD, DL, PtrVT, Hi, Lo); 1895 } 1896 1897 SDValue ThreadPointer = DAG.getNode(MipsISD::ThreadPointer, DL, PtrVT); 1898 return DAG.getNode(ISD::ADD, DL, PtrVT, ThreadPointer, Offset); 1899 } 1900 1901 SDValue MipsTargetLowering:: 1902 lowerJumpTable(SDValue Op, SelectionDAG &DAG) const 1903 { 1904 JumpTableSDNode *N = cast<JumpTableSDNode>(Op); 1905 EVT Ty = Op.getValueType(); 1906 1907 if (!isPositionIndependent() && !ABI.IsN64()) 1908 return getAddrNonPIC(N, SDLoc(N), Ty, DAG); 1909 1910 return getAddrLocal(N, SDLoc(N), Ty, DAG, ABI.IsN32() || ABI.IsN64()); 1911 } 1912 1913 SDValue MipsTargetLowering:: 1914 lowerConstantPool(SDValue Op, SelectionDAG &DAG) const 1915 { 1916 ConstantPoolSDNode *N = cast<ConstantPoolSDNode>(Op); 1917 EVT Ty = Op.getValueType(); 1918 1919 if (!isPositionIndependent() && !ABI.IsN64()) { 1920 const MipsTargetObjectFile *TLOF = 1921 static_cast<const MipsTargetObjectFile *>( 1922 getTargetMachine().getObjFileLowering()); 1923 1924 if (TLOF->IsConstantInSmallSection(DAG.getDataLayout(), N->getConstVal(), 1925 getTargetMachine())) 1926 // %gp_rel relocation 1927 return getAddrGPRel(N, SDLoc(N), Ty, DAG); 1928 1929 return getAddrNonPIC(N, SDLoc(N), Ty, DAG); 1930 } 1931 1932 return getAddrLocal(N, SDLoc(N), Ty, DAG, ABI.IsN32() || ABI.IsN64()); 1933 } 1934 1935 SDValue MipsTargetLowering::lowerVASTART(SDValue Op, SelectionDAG &DAG) const { 1936 MachineFunction &MF = DAG.getMachineFunction(); 1937 MipsFunctionInfo *FuncInfo = MF.getInfo<MipsFunctionInfo>(); 1938 1939 SDLoc DL(Op); 1940 SDValue FI = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), 1941 getPointerTy(MF.getDataLayout())); 1942 1943 // vastart just stores the address of the VarArgsFrameIndex slot into the 1944 // memory location argument. 1945 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue(); 1946 return DAG.getStore(Op.getOperand(0), DL, FI, Op.getOperand(1), 1947 MachinePointerInfo(SV)); 1948 } 1949 1950 SDValue MipsTargetLowering::lowerVAARG(SDValue Op, SelectionDAG &DAG) const { 1951 SDNode *Node = Op.getNode(); 1952 EVT VT = Node->getValueType(0); 1953 SDValue Chain = Node->getOperand(0); 1954 SDValue VAListPtr = Node->getOperand(1); 1955 unsigned Align = Node->getConstantOperandVal(3); 1956 const Value *SV = cast<SrcValueSDNode>(Node->getOperand(2))->getValue(); 1957 SDLoc DL(Node); 1958 unsigned ArgSlotSizeInBytes = (ABI.IsN32() || ABI.IsN64()) ? 8 : 4; 1959 1960 SDValue VAListLoad = DAG.getLoad(getPointerTy(DAG.getDataLayout()), DL, Chain, 1961 VAListPtr, MachinePointerInfo(SV)); 1962 SDValue VAList = VAListLoad; 1963 1964 // Re-align the pointer if necessary. 1965 // It should only ever be necessary for 64-bit types on O32 since the minimum 1966 // argument alignment is the same as the maximum type alignment for N32/N64. 1967 // 1968 // FIXME: We currently align too often. The code generator doesn't notice 1969 // when the pointer is still aligned from the last va_arg (or pair of 1970 // va_args for the i64 on O32 case). 1971 if (Align > getMinStackArgumentAlignment()) { 1972 assert(((Align & (Align-1)) == 0) && "Expected Align to be a power of 2"); 1973 1974 VAList = DAG.getNode(ISD::ADD, DL, VAList.getValueType(), VAList, 1975 DAG.getConstant(Align - 1, DL, VAList.getValueType())); 1976 1977 VAList = DAG.getNode(ISD::AND, DL, VAList.getValueType(), VAList, 1978 DAG.getConstant(-(int64_t)Align, DL, 1979 VAList.getValueType())); 1980 } 1981 1982 // Increment the pointer, VAList, to the next vaarg. 1983 auto &TD = DAG.getDataLayout(); 1984 unsigned ArgSizeInBytes = 1985 TD.getTypeAllocSize(VT.getTypeForEVT(*DAG.getContext())); 1986 SDValue Tmp3 = 1987 DAG.getNode(ISD::ADD, DL, VAList.getValueType(), VAList, 1988 DAG.getConstant(alignTo(ArgSizeInBytes, ArgSlotSizeInBytes), 1989 DL, VAList.getValueType())); 1990 // Store the incremented VAList to the legalized pointer 1991 Chain = DAG.getStore(VAListLoad.getValue(1), DL, Tmp3, VAListPtr, 1992 MachinePointerInfo(SV)); 1993 1994 // In big-endian mode we must adjust the pointer when the load size is smaller 1995 // than the argument slot size. We must also reduce the known alignment to 1996 // match. For example in the N64 ABI, we must add 4 bytes to the offset to get 1997 // the correct half of the slot, and reduce the alignment from 8 (slot 1998 // alignment) down to 4 (type alignment). 1999 if (!Subtarget.isLittle() && ArgSizeInBytes < ArgSlotSizeInBytes) { 2000 unsigned Adjustment = ArgSlotSizeInBytes - ArgSizeInBytes; 2001 VAList = DAG.getNode(ISD::ADD, DL, VAListPtr.getValueType(), VAList, 2002 DAG.getIntPtrConstant(Adjustment, DL)); 2003 } 2004 // Load the actual argument out of the pointer VAList 2005 return DAG.getLoad(VT, DL, Chain, VAList, MachinePointerInfo()); 2006 } 2007 2008 static SDValue lowerFCOPYSIGN32(SDValue Op, SelectionDAG &DAG, 2009 bool HasExtractInsert) { 2010 EVT TyX = Op.getOperand(0).getValueType(); 2011 EVT TyY = Op.getOperand(1).getValueType(); 2012 SDLoc DL(Op); 2013 SDValue Const1 = DAG.getConstant(1, DL, MVT::i32); 2014 SDValue Const31 = DAG.getConstant(31, DL, MVT::i32); 2015 SDValue Res; 2016 2017 // If operand is of type f64, extract the upper 32-bit. Otherwise, bitcast it 2018 // to i32. 2019 SDValue X = (TyX == MVT::f32) ? 2020 DAG.getNode(ISD::BITCAST, DL, MVT::i32, Op.getOperand(0)) : 2021 DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32, Op.getOperand(0), 2022 Const1); 2023 SDValue Y = (TyY == MVT::f32) ? 2024 DAG.getNode(ISD::BITCAST, DL, MVT::i32, Op.getOperand(1)) : 2025 DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32, Op.getOperand(1), 2026 Const1); 2027 2028 if (HasExtractInsert) { 2029 // ext E, Y, 31, 1 ; extract bit31 of Y 2030 // ins X, E, 31, 1 ; insert extracted bit at bit31 of X 2031 SDValue E = DAG.getNode(MipsISD::Ext, DL, MVT::i32, Y, Const31, Const1); 2032 Res = DAG.getNode(MipsISD::Ins, DL, MVT::i32, E, Const31, Const1, X); 2033 } else { 2034 // sll SllX, X, 1 2035 // srl SrlX, SllX, 1 2036 // srl SrlY, Y, 31 2037 // sll SllY, SrlX, 31 2038 // or Or, SrlX, SllY 2039 SDValue SllX = DAG.getNode(ISD::SHL, DL, MVT::i32, X, Const1); 2040 SDValue SrlX = DAG.getNode(ISD::SRL, DL, MVT::i32, SllX, Const1); 2041 SDValue SrlY = DAG.getNode(ISD::SRL, DL, MVT::i32, Y, Const31); 2042 SDValue SllY = DAG.getNode(ISD::SHL, DL, MVT::i32, SrlY, Const31); 2043 Res = DAG.getNode(ISD::OR, DL, MVT::i32, SrlX, SllY); 2044 } 2045 2046 if (TyX == MVT::f32) 2047 return DAG.getNode(ISD::BITCAST, DL, Op.getOperand(0).getValueType(), Res); 2048 2049 SDValue LowX = DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32, 2050 Op.getOperand(0), 2051 DAG.getConstant(0, DL, MVT::i32)); 2052 return DAG.getNode(MipsISD::BuildPairF64, DL, MVT::f64, LowX, Res); 2053 } 2054 2055 static SDValue lowerFCOPYSIGN64(SDValue Op, SelectionDAG &DAG, 2056 bool HasExtractInsert) { 2057 unsigned WidthX = Op.getOperand(0).getValueSizeInBits(); 2058 unsigned WidthY = Op.getOperand(1).getValueSizeInBits(); 2059 EVT TyX = MVT::getIntegerVT(WidthX), TyY = MVT::getIntegerVT(WidthY); 2060 SDLoc DL(Op); 2061 SDValue Const1 = DAG.getConstant(1, DL, MVT::i32); 2062 2063 // Bitcast to integer nodes. 2064 SDValue X = DAG.getNode(ISD::BITCAST, DL, TyX, Op.getOperand(0)); 2065 SDValue Y = DAG.getNode(ISD::BITCAST, DL, TyY, Op.getOperand(1)); 2066 2067 if (HasExtractInsert) { 2068 // ext E, Y, width(Y) - 1, 1 ; extract bit width(Y)-1 of Y 2069 // ins X, E, width(X) - 1, 1 ; insert extracted bit at bit width(X)-1 of X 2070 SDValue E = DAG.getNode(MipsISD::Ext, DL, TyY, Y, 2071 DAG.getConstant(WidthY - 1, DL, MVT::i32), Const1); 2072 2073 if (WidthX > WidthY) 2074 E = DAG.getNode(ISD::ZERO_EXTEND, DL, TyX, E); 2075 else if (WidthY > WidthX) 2076 E = DAG.getNode(ISD::TRUNCATE, DL, TyX, E); 2077 2078 SDValue I = DAG.getNode(MipsISD::Ins, DL, TyX, E, 2079 DAG.getConstant(WidthX - 1, DL, MVT::i32), Const1, 2080 X); 2081 return DAG.getNode(ISD::BITCAST, DL, Op.getOperand(0).getValueType(), I); 2082 } 2083 2084 // (d)sll SllX, X, 1 2085 // (d)srl SrlX, SllX, 1 2086 // (d)srl SrlY, Y, width(Y)-1 2087 // (d)sll SllY, SrlX, width(Y)-1 2088 // or Or, SrlX, SllY 2089 SDValue SllX = DAG.getNode(ISD::SHL, DL, TyX, X, Const1); 2090 SDValue SrlX = DAG.getNode(ISD::SRL, DL, TyX, SllX, Const1); 2091 SDValue SrlY = DAG.getNode(ISD::SRL, DL, TyY, Y, 2092 DAG.getConstant(WidthY - 1, DL, MVT::i32)); 2093 2094 if (WidthX > WidthY) 2095 SrlY = DAG.getNode(ISD::ZERO_EXTEND, DL, TyX, SrlY); 2096 else if (WidthY > WidthX) 2097 SrlY = DAG.getNode(ISD::TRUNCATE, DL, TyX, SrlY); 2098 2099 SDValue SllY = DAG.getNode(ISD::SHL, DL, TyX, SrlY, 2100 DAG.getConstant(WidthX - 1, DL, MVT::i32)); 2101 SDValue Or = DAG.getNode(ISD::OR, DL, TyX, SrlX, SllY); 2102 return DAG.getNode(ISD::BITCAST, DL, Op.getOperand(0).getValueType(), Or); 2103 } 2104 2105 SDValue 2106 MipsTargetLowering::lowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const { 2107 if (Subtarget.isGP64bit()) 2108 return lowerFCOPYSIGN64(Op, DAG, Subtarget.hasExtractInsert()); 2109 2110 return lowerFCOPYSIGN32(Op, DAG, Subtarget.hasExtractInsert()); 2111 } 2112 2113 SDValue MipsTargetLowering:: 2114 lowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const { 2115 // check the depth 2116 assert((cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue() == 0) && 2117 "Frame address can only be determined for current frame."); 2118 2119 MachineFrameInfo &MFI = DAG.getMachineFunction().getFrameInfo(); 2120 MFI.setFrameAddressIsTaken(true); 2121 EVT VT = Op.getValueType(); 2122 SDLoc DL(Op); 2123 SDValue FrameAddr = DAG.getCopyFromReg( 2124 DAG.getEntryNode(), DL, ABI.IsN64() ? Mips::FP_64 : Mips::FP, VT); 2125 return FrameAddr; 2126 } 2127 2128 SDValue MipsTargetLowering::lowerRETURNADDR(SDValue Op, 2129 SelectionDAG &DAG) const { 2130 if (verifyReturnAddressArgumentIsConstant(Op, DAG)) 2131 return SDValue(); 2132 2133 // check the depth 2134 assert((cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue() == 0) && 2135 "Return address can be determined only for current frame."); 2136 2137 MachineFunction &MF = DAG.getMachineFunction(); 2138 MachineFrameInfo &MFI = MF.getFrameInfo(); 2139 MVT VT = Op.getSimpleValueType(); 2140 unsigned RA = ABI.IsN64() ? Mips::RA_64 : Mips::RA; 2141 MFI.setReturnAddressIsTaken(true); 2142 2143 // Return RA, which contains the return address. Mark it an implicit live-in. 2144 unsigned Reg = MF.addLiveIn(RA, getRegClassFor(VT)); 2145 return DAG.getCopyFromReg(DAG.getEntryNode(), SDLoc(Op), Reg, VT); 2146 } 2147 2148 // An EH_RETURN is the result of lowering llvm.eh.return which in turn is 2149 // generated from __builtin_eh_return (offset, handler) 2150 // The effect of this is to adjust the stack pointer by "offset" 2151 // and then branch to "handler". 2152 SDValue MipsTargetLowering::lowerEH_RETURN(SDValue Op, SelectionDAG &DAG) 2153 const { 2154 MachineFunction &MF = DAG.getMachineFunction(); 2155 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>(); 2156 2157 MipsFI->setCallsEhReturn(); 2158 SDValue Chain = Op.getOperand(0); 2159 SDValue Offset = Op.getOperand(1); 2160 SDValue Handler = Op.getOperand(2); 2161 SDLoc DL(Op); 2162 EVT Ty = ABI.IsN64() ? MVT::i64 : MVT::i32; 2163 2164 // Store stack offset in V1, store jump target in V0. Glue CopyToReg and 2165 // EH_RETURN nodes, so that instructions are emitted back-to-back. 2166 unsigned OffsetReg = ABI.IsN64() ? Mips::V1_64 : Mips::V1; 2167 unsigned AddrReg = ABI.IsN64() ? Mips::V0_64 : Mips::V0; 2168 Chain = DAG.getCopyToReg(Chain, DL, OffsetReg, Offset, SDValue()); 2169 Chain = DAG.getCopyToReg(Chain, DL, AddrReg, Handler, Chain.getValue(1)); 2170 return DAG.getNode(MipsISD::EH_RETURN, DL, MVT::Other, Chain, 2171 DAG.getRegister(OffsetReg, Ty), 2172 DAG.getRegister(AddrReg, getPointerTy(MF.getDataLayout())), 2173 Chain.getValue(1)); 2174 } 2175 2176 SDValue MipsTargetLowering::lowerATOMIC_FENCE(SDValue Op, 2177 SelectionDAG &DAG) const { 2178 // FIXME: Need pseudo-fence for 'singlethread' fences 2179 // FIXME: Set SType for weaker fences where supported/appropriate. 2180 unsigned SType = 0; 2181 SDLoc DL(Op); 2182 return DAG.getNode(MipsISD::Sync, DL, MVT::Other, Op.getOperand(0), 2183 DAG.getConstant(SType, DL, MVT::i32)); 2184 } 2185 2186 SDValue MipsTargetLowering::lowerShiftLeftParts(SDValue Op, 2187 SelectionDAG &DAG) const { 2188 SDLoc DL(Op); 2189 MVT VT = Subtarget.isGP64bit() ? MVT::i64 : MVT::i32; 2190 2191 SDValue Lo = Op.getOperand(0), Hi = Op.getOperand(1); 2192 SDValue Shamt = Op.getOperand(2); 2193 // if shamt < (VT.bits): 2194 // lo = (shl lo, shamt) 2195 // hi = (or (shl hi, shamt) (srl (srl lo, 1), ~shamt)) 2196 // else: 2197 // lo = 0 2198 // hi = (shl lo, shamt[4:0]) 2199 SDValue Not = DAG.getNode(ISD::XOR, DL, MVT::i32, Shamt, 2200 DAG.getConstant(-1, DL, MVT::i32)); 2201 SDValue ShiftRight1Lo = DAG.getNode(ISD::SRL, DL, VT, Lo, 2202 DAG.getConstant(1, DL, VT)); 2203 SDValue ShiftRightLo = DAG.getNode(ISD::SRL, DL, VT, ShiftRight1Lo, Not); 2204 SDValue ShiftLeftHi = DAG.getNode(ISD::SHL, DL, VT, Hi, Shamt); 2205 SDValue Or = DAG.getNode(ISD::OR, DL, VT, ShiftLeftHi, ShiftRightLo); 2206 SDValue ShiftLeftLo = DAG.getNode(ISD::SHL, DL, VT, Lo, Shamt); 2207 SDValue Cond = DAG.getNode(ISD::AND, DL, MVT::i32, Shamt, 2208 DAG.getConstant(VT.getSizeInBits(), DL, MVT::i32)); 2209 Lo = DAG.getNode(ISD::SELECT, DL, VT, Cond, 2210 DAG.getConstant(0, DL, VT), ShiftLeftLo); 2211 Hi = DAG.getNode(ISD::SELECT, DL, VT, Cond, ShiftLeftLo, Or); 2212 2213 SDValue Ops[2] = {Lo, Hi}; 2214 return DAG.getMergeValues(Ops, DL); 2215 } 2216 2217 SDValue MipsTargetLowering::lowerShiftRightParts(SDValue Op, SelectionDAG &DAG, 2218 bool IsSRA) const { 2219 SDLoc DL(Op); 2220 SDValue Lo = Op.getOperand(0), Hi = Op.getOperand(1); 2221 SDValue Shamt = Op.getOperand(2); 2222 MVT VT = Subtarget.isGP64bit() ? MVT::i64 : MVT::i32; 2223 2224 // if shamt < (VT.bits): 2225 // lo = (or (shl (shl hi, 1), ~shamt) (srl lo, shamt)) 2226 // if isSRA: 2227 // hi = (sra hi, shamt) 2228 // else: 2229 // hi = (srl hi, shamt) 2230 // else: 2231 // if isSRA: 2232 // lo = (sra hi, shamt[4:0]) 2233 // hi = (sra hi, 31) 2234 // else: 2235 // lo = (srl hi, shamt[4:0]) 2236 // hi = 0 2237 SDValue Not = DAG.getNode(ISD::XOR, DL, MVT::i32, Shamt, 2238 DAG.getConstant(-1, DL, MVT::i32)); 2239 SDValue ShiftLeft1Hi = DAG.getNode(ISD::SHL, DL, VT, Hi, 2240 DAG.getConstant(1, DL, VT)); 2241 SDValue ShiftLeftHi = DAG.getNode(ISD::SHL, DL, VT, ShiftLeft1Hi, Not); 2242 SDValue ShiftRightLo = DAG.getNode(ISD::SRL, DL, VT, Lo, Shamt); 2243 SDValue Or = DAG.getNode(ISD::OR, DL, VT, ShiftLeftHi, ShiftRightLo); 2244 SDValue ShiftRightHi = DAG.getNode(IsSRA ? ISD::SRA : ISD::SRL, 2245 DL, VT, Hi, Shamt); 2246 SDValue Cond = DAG.getNode(ISD::AND, DL, MVT::i32, Shamt, 2247 DAG.getConstant(VT.getSizeInBits(), DL, MVT::i32)); 2248 SDValue Ext = DAG.getNode(ISD::SRA, DL, VT, Hi, 2249 DAG.getConstant(VT.getSizeInBits() - 1, DL, VT)); 2250 Lo = DAG.getNode(ISD::SELECT, DL, VT, Cond, ShiftRightHi, Or); 2251 Hi = DAG.getNode(ISD::SELECT, DL, VT, Cond, 2252 IsSRA ? Ext : DAG.getConstant(0, DL, VT), ShiftRightHi); 2253 2254 SDValue Ops[2] = {Lo, Hi}; 2255 return DAG.getMergeValues(Ops, DL); 2256 } 2257 2258 static SDValue createLoadLR(unsigned Opc, SelectionDAG &DAG, LoadSDNode *LD, 2259 SDValue Chain, SDValue Src, unsigned Offset) { 2260 SDValue Ptr = LD->getBasePtr(); 2261 EVT VT = LD->getValueType(0), MemVT = LD->getMemoryVT(); 2262 EVT BasePtrVT = Ptr.getValueType(); 2263 SDLoc DL(LD); 2264 SDVTList VTList = DAG.getVTList(VT, MVT::Other); 2265 2266 if (Offset) 2267 Ptr = DAG.getNode(ISD::ADD, DL, BasePtrVT, Ptr, 2268 DAG.getConstant(Offset, DL, BasePtrVT)); 2269 2270 SDValue Ops[] = { Chain, Ptr, Src }; 2271 return DAG.getMemIntrinsicNode(Opc, DL, VTList, Ops, MemVT, 2272 LD->getMemOperand()); 2273 } 2274 2275 // Expand an unaligned 32 or 64-bit integer load node. 2276 SDValue MipsTargetLowering::lowerLOAD(SDValue Op, SelectionDAG &DAG) const { 2277 LoadSDNode *LD = cast<LoadSDNode>(Op); 2278 EVT MemVT = LD->getMemoryVT(); 2279 2280 if (Subtarget.systemSupportsUnalignedAccess()) 2281 return Op; 2282 2283 // Return if load is aligned or if MemVT is neither i32 nor i64. 2284 if ((LD->getAlignment() >= MemVT.getSizeInBits() / 8) || 2285 ((MemVT != MVT::i32) && (MemVT != MVT::i64))) 2286 return SDValue(); 2287 2288 bool IsLittle = Subtarget.isLittle(); 2289 EVT VT = Op.getValueType(); 2290 ISD::LoadExtType ExtType = LD->getExtensionType(); 2291 SDValue Chain = LD->getChain(), Undef = DAG.getUNDEF(VT); 2292 2293 assert((VT == MVT::i32) || (VT == MVT::i64)); 2294 2295 // Expand 2296 // (set dst, (i64 (load baseptr))) 2297 // to 2298 // (set tmp, (ldl (add baseptr, 7), undef)) 2299 // (set dst, (ldr baseptr, tmp)) 2300 if ((VT == MVT::i64) && (ExtType == ISD::NON_EXTLOAD)) { 2301 SDValue LDL = createLoadLR(MipsISD::LDL, DAG, LD, Chain, Undef, 2302 IsLittle ? 7 : 0); 2303 return createLoadLR(MipsISD::LDR, DAG, LD, LDL.getValue(1), LDL, 2304 IsLittle ? 0 : 7); 2305 } 2306 2307 SDValue LWL = createLoadLR(MipsISD::LWL, DAG, LD, Chain, Undef, 2308 IsLittle ? 3 : 0); 2309 SDValue LWR = createLoadLR(MipsISD::LWR, DAG, LD, LWL.getValue(1), LWL, 2310 IsLittle ? 0 : 3); 2311 2312 // Expand 2313 // (set dst, (i32 (load baseptr))) or 2314 // (set dst, (i64 (sextload baseptr))) or 2315 // (set dst, (i64 (extload baseptr))) 2316 // to 2317 // (set tmp, (lwl (add baseptr, 3), undef)) 2318 // (set dst, (lwr baseptr, tmp)) 2319 if ((VT == MVT::i32) || (ExtType == ISD::SEXTLOAD) || 2320 (ExtType == ISD::EXTLOAD)) 2321 return LWR; 2322 2323 assert((VT == MVT::i64) && (ExtType == ISD::ZEXTLOAD)); 2324 2325 // Expand 2326 // (set dst, (i64 (zextload baseptr))) 2327 // to 2328 // (set tmp0, (lwl (add baseptr, 3), undef)) 2329 // (set tmp1, (lwr baseptr, tmp0)) 2330 // (set tmp2, (shl tmp1, 32)) 2331 // (set dst, (srl tmp2, 32)) 2332 SDLoc DL(LD); 2333 SDValue Const32 = DAG.getConstant(32, DL, MVT::i32); 2334 SDValue SLL = DAG.getNode(ISD::SHL, DL, MVT::i64, LWR, Const32); 2335 SDValue SRL = DAG.getNode(ISD::SRL, DL, MVT::i64, SLL, Const32); 2336 SDValue Ops[] = { SRL, LWR.getValue(1) }; 2337 return DAG.getMergeValues(Ops, DL); 2338 } 2339 2340 static SDValue createStoreLR(unsigned Opc, SelectionDAG &DAG, StoreSDNode *SD, 2341 SDValue Chain, unsigned Offset) { 2342 SDValue Ptr = SD->getBasePtr(), Value = SD->getValue(); 2343 EVT MemVT = SD->getMemoryVT(), BasePtrVT = Ptr.getValueType(); 2344 SDLoc DL(SD); 2345 SDVTList VTList = DAG.getVTList(MVT::Other); 2346 2347 if (Offset) 2348 Ptr = DAG.getNode(ISD::ADD, DL, BasePtrVT, Ptr, 2349 DAG.getConstant(Offset, DL, BasePtrVT)); 2350 2351 SDValue Ops[] = { Chain, Value, Ptr }; 2352 return DAG.getMemIntrinsicNode(Opc, DL, VTList, Ops, MemVT, 2353 SD->getMemOperand()); 2354 } 2355 2356 // Expand an unaligned 32 or 64-bit integer store node. 2357 static SDValue lowerUnalignedIntStore(StoreSDNode *SD, SelectionDAG &DAG, 2358 bool IsLittle) { 2359 SDValue Value = SD->getValue(), Chain = SD->getChain(); 2360 EVT VT = Value.getValueType(); 2361 2362 // Expand 2363 // (store val, baseptr) or 2364 // (truncstore val, baseptr) 2365 // to 2366 // (swl val, (add baseptr, 3)) 2367 // (swr val, baseptr) 2368 if ((VT == MVT::i32) || SD->isTruncatingStore()) { 2369 SDValue SWL = createStoreLR(MipsISD::SWL, DAG, SD, Chain, 2370 IsLittle ? 3 : 0); 2371 return createStoreLR(MipsISD::SWR, DAG, SD, SWL, IsLittle ? 0 : 3); 2372 } 2373 2374 assert(VT == MVT::i64); 2375 2376 // Expand 2377 // (store val, baseptr) 2378 // to 2379 // (sdl val, (add baseptr, 7)) 2380 // (sdr val, baseptr) 2381 SDValue SDL = createStoreLR(MipsISD::SDL, DAG, SD, Chain, IsLittle ? 7 : 0); 2382 return createStoreLR(MipsISD::SDR, DAG, SD, SDL, IsLittle ? 0 : 7); 2383 } 2384 2385 // Lower (store (fp_to_sint $fp) $ptr) to (store (TruncIntFP $fp), $ptr). 2386 static SDValue lowerFP_TO_SINT_STORE(StoreSDNode *SD, SelectionDAG &DAG) { 2387 SDValue Val = SD->getValue(); 2388 2389 if (Val.getOpcode() != ISD::FP_TO_SINT) 2390 return SDValue(); 2391 2392 EVT FPTy = EVT::getFloatingPointVT(Val.getValueSizeInBits()); 2393 SDValue Tr = DAG.getNode(MipsISD::TruncIntFP, SDLoc(Val), FPTy, 2394 Val.getOperand(0)); 2395 return DAG.getStore(SD->getChain(), SDLoc(SD), Tr, SD->getBasePtr(), 2396 SD->getPointerInfo(), SD->getAlignment(), 2397 SD->getMemOperand()->getFlags()); 2398 } 2399 2400 SDValue MipsTargetLowering::lowerSTORE(SDValue Op, SelectionDAG &DAG) const { 2401 StoreSDNode *SD = cast<StoreSDNode>(Op); 2402 EVT MemVT = SD->getMemoryVT(); 2403 2404 // Lower unaligned integer stores. 2405 if (!Subtarget.systemSupportsUnalignedAccess() && 2406 (SD->getAlignment() < MemVT.getSizeInBits() / 8) && 2407 ((MemVT == MVT::i32) || (MemVT == MVT::i64))) 2408 return lowerUnalignedIntStore(SD, DAG, Subtarget.isLittle()); 2409 2410 return lowerFP_TO_SINT_STORE(SD, DAG); 2411 } 2412 2413 SDValue MipsTargetLowering::lowerEH_DWARF_CFA(SDValue Op, 2414 SelectionDAG &DAG) const { 2415 2416 // Return a fixed StackObject with offset 0 which points to the old stack 2417 // pointer. 2418 MachineFrameInfo &MFI = DAG.getMachineFunction().getFrameInfo(); 2419 EVT ValTy = Op->getValueType(0); 2420 int FI = MFI.CreateFixedObject(Op.getValueSizeInBits() / 8, 0, false); 2421 return DAG.getFrameIndex(FI, ValTy); 2422 } 2423 2424 SDValue MipsTargetLowering::lowerFP_TO_SINT(SDValue Op, 2425 SelectionDAG &DAG) const { 2426 EVT FPTy = EVT::getFloatingPointVT(Op.getValueSizeInBits()); 2427 SDValue Trunc = DAG.getNode(MipsISD::TruncIntFP, SDLoc(Op), FPTy, 2428 Op.getOperand(0)); 2429 return DAG.getNode(ISD::BITCAST, SDLoc(Op), Op.getValueType(), Trunc); 2430 } 2431 2432 //===----------------------------------------------------------------------===// 2433 // Calling Convention Implementation 2434 //===----------------------------------------------------------------------===// 2435 2436 //===----------------------------------------------------------------------===// 2437 // TODO: Implement a generic logic using tblgen that can support this. 2438 // Mips O32 ABI rules: 2439 // --- 2440 // i32 - Passed in A0, A1, A2, A3 and stack 2441 // f32 - Only passed in f32 registers if no int reg has been used yet to hold 2442 // an argument. Otherwise, passed in A1, A2, A3 and stack. 2443 // f64 - Only passed in two aliased f32 registers if no int reg has been used 2444 // yet to hold an argument. Otherwise, use A2, A3 and stack. If A1 is 2445 // not used, it must be shadowed. If only A3 is available, shadow it and 2446 // go to stack. 2447 // 2448 // For vararg functions, all arguments are passed in A0, A1, A2, A3 and stack. 2449 //===----------------------------------------------------------------------===// 2450 2451 static bool CC_MipsO32(unsigned ValNo, MVT ValVT, MVT LocVT, 2452 CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, 2453 CCState &State, ArrayRef<MCPhysReg> F64Regs) { 2454 const MipsSubtarget &Subtarget = static_cast<const MipsSubtarget &>( 2455 State.getMachineFunction().getSubtarget()); 2456 2457 static const MCPhysReg IntRegs[] = { Mips::A0, Mips::A1, Mips::A2, Mips::A3 }; 2458 static const MCPhysReg F32Regs[] = { Mips::F12, Mips::F14 }; 2459 2460 // Do not process byval args here. 2461 if (ArgFlags.isByVal()) 2462 return true; 2463 2464 // Promote i8 and i16 2465 if (ArgFlags.isInReg() && !Subtarget.isLittle()) { 2466 if (LocVT == MVT::i8 || LocVT == MVT::i16 || LocVT == MVT::i32) { 2467 LocVT = MVT::i32; 2468 if (ArgFlags.isSExt()) 2469 LocInfo = CCValAssign::SExtUpper; 2470 else if (ArgFlags.isZExt()) 2471 LocInfo = CCValAssign::ZExtUpper; 2472 else 2473 LocInfo = CCValAssign::AExtUpper; 2474 } 2475 } 2476 2477 // Promote i8 and i16 2478 if (LocVT == MVT::i8 || LocVT == MVT::i16) { 2479 LocVT = MVT::i32; 2480 if (ArgFlags.isSExt()) 2481 LocInfo = CCValAssign::SExt; 2482 else if (ArgFlags.isZExt()) 2483 LocInfo = CCValAssign::ZExt; 2484 else 2485 LocInfo = CCValAssign::AExt; 2486 } 2487 2488 unsigned Reg; 2489 2490 // f32 and f64 are allocated in A0, A1, A2, A3 when either of the following 2491 // is true: function is vararg, argument is 3rd or higher, there is previous 2492 // argument which is not f32 or f64. 2493 bool AllocateFloatsInIntReg = State.isVarArg() || ValNo > 1 || 2494 State.getFirstUnallocated(F32Regs) != ValNo; 2495 unsigned OrigAlign = ArgFlags.getOrigAlign(); 2496 bool isI64 = (ValVT == MVT::i32 && OrigAlign == 8); 2497 2498 if (ValVT == MVT::i32 || (ValVT == MVT::f32 && AllocateFloatsInIntReg)) { 2499 Reg = State.AllocateReg(IntRegs); 2500 // If this is the first part of an i64 arg, 2501 // the allocated register must be either A0 or A2. 2502 if (isI64 && (Reg == Mips::A1 || Reg == Mips::A3)) 2503 Reg = State.AllocateReg(IntRegs); 2504 LocVT = MVT::i32; 2505 } else if (ValVT == MVT::f64 && AllocateFloatsInIntReg) { 2506 // Allocate int register and shadow next int register. If first 2507 // available register is Mips::A1 or Mips::A3, shadow it too. 2508 Reg = State.AllocateReg(IntRegs); 2509 if (Reg == Mips::A1 || Reg == Mips::A3) 2510 Reg = State.AllocateReg(IntRegs); 2511 State.AllocateReg(IntRegs); 2512 LocVT = MVT::i32; 2513 } else if (ValVT.isFloatingPoint() && !AllocateFloatsInIntReg) { 2514 // we are guaranteed to find an available float register 2515 if (ValVT == MVT::f32) { 2516 Reg = State.AllocateReg(F32Regs); 2517 // Shadow int register 2518 State.AllocateReg(IntRegs); 2519 } else { 2520 Reg = State.AllocateReg(F64Regs); 2521 // Shadow int registers 2522 unsigned Reg2 = State.AllocateReg(IntRegs); 2523 if (Reg2 == Mips::A1 || Reg2 == Mips::A3) 2524 State.AllocateReg(IntRegs); 2525 State.AllocateReg(IntRegs); 2526 } 2527 } else 2528 llvm_unreachable("Cannot handle this ValVT."); 2529 2530 if (!Reg) { 2531 unsigned Offset = State.AllocateStack(ValVT.getSizeInBits() >> 3, 2532 OrigAlign); 2533 State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo)); 2534 } else 2535 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); 2536 2537 return false; 2538 } 2539 2540 static bool CC_MipsO32_FP32(unsigned ValNo, MVT ValVT, 2541 MVT LocVT, CCValAssign::LocInfo LocInfo, 2542 ISD::ArgFlagsTy ArgFlags, CCState &State) { 2543 static const MCPhysReg F64Regs[] = { Mips::D6, Mips::D7 }; 2544 2545 return CC_MipsO32(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State, F64Regs); 2546 } 2547 2548 static bool CC_MipsO32_FP64(unsigned ValNo, MVT ValVT, 2549 MVT LocVT, CCValAssign::LocInfo LocInfo, 2550 ISD::ArgFlagsTy ArgFlags, CCState &State) { 2551 static const MCPhysReg F64Regs[] = { Mips::D12_64, Mips::D14_64 }; 2552 2553 return CC_MipsO32(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State, F64Regs); 2554 } 2555 2556 static bool CC_MipsO32(unsigned ValNo, MVT ValVT, MVT LocVT, 2557 CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, 2558 CCState &State) LLVM_ATTRIBUTE_UNUSED; 2559 2560 #include "MipsGenCallingConv.inc" 2561 2562 //===----------------------------------------------------------------------===// 2563 // Call Calling Convention Implementation 2564 //===----------------------------------------------------------------------===// 2565 2566 // Return next O32 integer argument register. 2567 static unsigned getNextIntArgReg(unsigned Reg) { 2568 assert((Reg == Mips::A0) || (Reg == Mips::A2)); 2569 return (Reg == Mips::A0) ? Mips::A1 : Mips::A3; 2570 } 2571 2572 SDValue MipsTargetLowering::passArgOnStack(SDValue StackPtr, unsigned Offset, 2573 SDValue Chain, SDValue Arg, 2574 const SDLoc &DL, bool IsTailCall, 2575 SelectionDAG &DAG) const { 2576 if (!IsTailCall) { 2577 SDValue PtrOff = 2578 DAG.getNode(ISD::ADD, DL, getPointerTy(DAG.getDataLayout()), StackPtr, 2579 DAG.getIntPtrConstant(Offset, DL)); 2580 return DAG.getStore(Chain, DL, Arg, PtrOff, MachinePointerInfo()); 2581 } 2582 2583 MachineFrameInfo &MFI = DAG.getMachineFunction().getFrameInfo(); 2584 int FI = MFI.CreateFixedObject(Arg.getValueSizeInBits() / 8, Offset, false); 2585 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy(DAG.getDataLayout())); 2586 return DAG.getStore(Chain, DL, Arg, FIN, MachinePointerInfo(), 2587 /* Alignment = */ 0, MachineMemOperand::MOVolatile); 2588 } 2589 2590 void MipsTargetLowering:: 2591 getOpndList(SmallVectorImpl<SDValue> &Ops, 2592 std::deque< std::pair<unsigned, SDValue> > &RegsToPass, 2593 bool IsPICCall, bool GlobalOrExternal, bool InternalLinkage, 2594 bool IsCallReloc, CallLoweringInfo &CLI, SDValue Callee, 2595 SDValue Chain) const { 2596 // Insert node "GP copy globalreg" before call to function. 2597 // 2598 // R_MIPS_CALL* operators (emitted when non-internal functions are called 2599 // in PIC mode) allow symbols to be resolved via lazy binding. 2600 // The lazy binding stub requires GP to point to the GOT. 2601 // Note that we don't need GP to point to the GOT for indirect calls 2602 // (when R_MIPS_CALL* is not used for the call) because Mips linker generates 2603 // lazy binding stub for a function only when R_MIPS_CALL* are the only relocs 2604 // used for the function (that is, Mips linker doesn't generate lazy binding 2605 // stub for a function whose address is taken in the program). 2606 if (IsPICCall && !InternalLinkage && IsCallReloc) { 2607 unsigned GPReg = ABI.IsN64() ? Mips::GP_64 : Mips::GP; 2608 EVT Ty = ABI.IsN64() ? MVT::i64 : MVT::i32; 2609 RegsToPass.push_back(std::make_pair(GPReg, getGlobalReg(CLI.DAG, Ty))); 2610 } 2611 2612 // Build a sequence of copy-to-reg nodes chained together with token 2613 // chain and flag operands which copy the outgoing args into registers. 2614 // The InFlag in necessary since all emitted instructions must be 2615 // stuck together. 2616 SDValue InFlag; 2617 2618 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) { 2619 Chain = CLI.DAG.getCopyToReg(Chain, CLI.DL, RegsToPass[i].first, 2620 RegsToPass[i].second, InFlag); 2621 InFlag = Chain.getValue(1); 2622 } 2623 2624 // Add argument registers to the end of the list so that they are 2625 // known live into the call. 2626 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) 2627 Ops.push_back(CLI.DAG.getRegister(RegsToPass[i].first, 2628 RegsToPass[i].second.getValueType())); 2629 2630 // Add a register mask operand representing the call-preserved registers. 2631 const TargetRegisterInfo *TRI = Subtarget.getRegisterInfo(); 2632 const uint32_t *Mask = 2633 TRI->getCallPreservedMask(CLI.DAG.getMachineFunction(), CLI.CallConv); 2634 assert(Mask && "Missing call preserved mask for calling convention"); 2635 if (Subtarget.inMips16HardFloat()) { 2636 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(CLI.Callee)) { 2637 llvm::StringRef Sym = G->getGlobal()->getName(); 2638 Function *F = G->getGlobal()->getParent()->getFunction(Sym); 2639 if (F && F->hasFnAttribute("__Mips16RetHelper")) { 2640 Mask = MipsRegisterInfo::getMips16RetHelperMask(); 2641 } 2642 } 2643 } 2644 Ops.push_back(CLI.DAG.getRegisterMask(Mask)); 2645 2646 if (InFlag.getNode()) 2647 Ops.push_back(InFlag); 2648 } 2649 2650 /// LowerCall - functions arguments are copied from virtual regs to 2651 /// (physical regs)/(stack frame), CALLSEQ_START and CALLSEQ_END are emitted. 2652 SDValue 2653 MipsTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI, 2654 SmallVectorImpl<SDValue> &InVals) const { 2655 SelectionDAG &DAG = CLI.DAG; 2656 SDLoc DL = CLI.DL; 2657 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs; 2658 SmallVectorImpl<SDValue> &OutVals = CLI.OutVals; 2659 SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins; 2660 SDValue Chain = CLI.Chain; 2661 SDValue Callee = CLI.Callee; 2662 bool &IsTailCall = CLI.IsTailCall; 2663 CallingConv::ID CallConv = CLI.CallConv; 2664 bool IsVarArg = CLI.IsVarArg; 2665 2666 MachineFunction &MF = DAG.getMachineFunction(); 2667 MachineFrameInfo &MFI = MF.getFrameInfo(); 2668 const TargetFrameLowering *TFL = Subtarget.getFrameLowering(); 2669 MipsFunctionInfo *FuncInfo = MF.getInfo<MipsFunctionInfo>(); 2670 bool IsPIC = isPositionIndependent(); 2671 2672 // Analyze operands of the call, assigning locations to each operand. 2673 SmallVector<CCValAssign, 16> ArgLocs; 2674 MipsCCState CCInfo( 2675 CallConv, IsVarArg, DAG.getMachineFunction(), ArgLocs, *DAG.getContext(), 2676 MipsCCState::getSpecialCallingConvForCallee(Callee.getNode(), Subtarget)); 2677 2678 // Allocate the reserved argument area. It seems strange to do this from the 2679 // caller side but removing it breaks the frame size calculation. 2680 CCInfo.AllocateStack(ABI.GetCalleeAllocdArgSizeInBytes(CallConv), 1); 2681 2682 CCInfo.AnalyzeCallOperands(Outs, CC_Mips, CLI.getArgs(), Callee.getNode()); 2683 2684 // Get a count of how many bytes are to be pushed on the stack. 2685 unsigned NextStackOffset = CCInfo.getNextStackOffset(); 2686 2687 // Check if it's really possible to do a tail call. 2688 if (IsTailCall) 2689 IsTailCall = isEligibleForTailCallOptimization( 2690 CCInfo, NextStackOffset, *MF.getInfo<MipsFunctionInfo>()); 2691 2692 if (!IsTailCall && CLI.CS && CLI.CS->isMustTailCall()) 2693 report_fatal_error("failed to perform tail call elimination on a call " 2694 "site marked musttail"); 2695 2696 if (IsTailCall) 2697 ++NumTailCalls; 2698 2699 // Chain is the output chain of the last Load/Store or CopyToReg node. 2700 // ByValChain is the output chain of the last Memcpy node created for copying 2701 // byval arguments to the stack. 2702 unsigned StackAlignment = TFL->getStackAlignment(); 2703 NextStackOffset = alignTo(NextStackOffset, StackAlignment); 2704 SDValue NextStackOffsetVal = DAG.getIntPtrConstant(NextStackOffset, DL, true); 2705 2706 if (!IsTailCall) 2707 Chain = DAG.getCALLSEQ_START(Chain, NextStackOffsetVal, DL); 2708 2709 SDValue StackPtr = 2710 DAG.getCopyFromReg(Chain, DL, ABI.IsN64() ? Mips::SP_64 : Mips::SP, 2711 getPointerTy(DAG.getDataLayout())); 2712 2713 std::deque< std::pair<unsigned, SDValue> > RegsToPass; 2714 SmallVector<SDValue, 8> MemOpChains; 2715 2716 CCInfo.rewindByValRegsInfo(); 2717 2718 // Walk the register/memloc assignments, inserting copies/loads. 2719 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { 2720 SDValue Arg = OutVals[i]; 2721 CCValAssign &VA = ArgLocs[i]; 2722 MVT ValVT = VA.getValVT(), LocVT = VA.getLocVT(); 2723 ISD::ArgFlagsTy Flags = Outs[i].Flags; 2724 bool UseUpperBits = false; 2725 2726 // ByVal Arg. 2727 if (Flags.isByVal()) { 2728 unsigned FirstByValReg, LastByValReg; 2729 unsigned ByValIdx = CCInfo.getInRegsParamsProcessed(); 2730 CCInfo.getInRegsParamInfo(ByValIdx, FirstByValReg, LastByValReg); 2731 2732 assert(Flags.getByValSize() && 2733 "ByVal args of size 0 should have been ignored by front-end."); 2734 assert(ByValIdx < CCInfo.getInRegsParamsCount()); 2735 assert(!IsTailCall && 2736 "Do not tail-call optimize if there is a byval argument."); 2737 passByValArg(Chain, DL, RegsToPass, MemOpChains, StackPtr, MFI, DAG, Arg, 2738 FirstByValReg, LastByValReg, Flags, Subtarget.isLittle(), 2739 VA); 2740 CCInfo.nextInRegsParam(); 2741 continue; 2742 } 2743 2744 // Promote the value if needed. 2745 switch (VA.getLocInfo()) { 2746 default: 2747 llvm_unreachable("Unknown loc info!"); 2748 case CCValAssign::Full: 2749 if (VA.isRegLoc()) { 2750 if ((ValVT == MVT::f32 && LocVT == MVT::i32) || 2751 (ValVT == MVT::f64 && LocVT == MVT::i64) || 2752 (ValVT == MVT::i64 && LocVT == MVT::f64)) 2753 Arg = DAG.getNode(ISD::BITCAST, DL, LocVT, Arg); 2754 else if (ValVT == MVT::f64 && LocVT == MVT::i32) { 2755 SDValue Lo = DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32, 2756 Arg, DAG.getConstant(0, DL, MVT::i32)); 2757 SDValue Hi = DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32, 2758 Arg, DAG.getConstant(1, DL, MVT::i32)); 2759 if (!Subtarget.isLittle()) 2760 std::swap(Lo, Hi); 2761 unsigned LocRegLo = VA.getLocReg(); 2762 unsigned LocRegHigh = getNextIntArgReg(LocRegLo); 2763 RegsToPass.push_back(std::make_pair(LocRegLo, Lo)); 2764 RegsToPass.push_back(std::make_pair(LocRegHigh, Hi)); 2765 continue; 2766 } 2767 } 2768 break; 2769 case CCValAssign::BCvt: 2770 Arg = DAG.getNode(ISD::BITCAST, DL, LocVT, Arg); 2771 break; 2772 case CCValAssign::SExtUpper: 2773 UseUpperBits = true; 2774 LLVM_FALLTHROUGH; 2775 case CCValAssign::SExt: 2776 Arg = DAG.getNode(ISD::SIGN_EXTEND, DL, LocVT, Arg); 2777 break; 2778 case CCValAssign::ZExtUpper: 2779 UseUpperBits = true; 2780 LLVM_FALLTHROUGH; 2781 case CCValAssign::ZExt: 2782 Arg = DAG.getNode(ISD::ZERO_EXTEND, DL, LocVT, Arg); 2783 break; 2784 case CCValAssign::AExtUpper: 2785 UseUpperBits = true; 2786 LLVM_FALLTHROUGH; 2787 case CCValAssign::AExt: 2788 Arg = DAG.getNode(ISD::ANY_EXTEND, DL, LocVT, Arg); 2789 break; 2790 } 2791 2792 if (UseUpperBits) { 2793 unsigned ValSizeInBits = Outs[i].ArgVT.getSizeInBits(); 2794 unsigned LocSizeInBits = VA.getLocVT().getSizeInBits(); 2795 Arg = DAG.getNode( 2796 ISD::SHL, DL, VA.getLocVT(), Arg, 2797 DAG.getConstant(LocSizeInBits - ValSizeInBits, DL, VA.getLocVT())); 2798 } 2799 2800 // Arguments that can be passed on register must be kept at 2801 // RegsToPass vector 2802 if (VA.isRegLoc()) { 2803 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg)); 2804 continue; 2805 } 2806 2807 // Register can't get to this point... 2808 assert(VA.isMemLoc()); 2809 2810 // emit ISD::STORE whichs stores the 2811 // parameter value to a stack Location 2812 MemOpChains.push_back(passArgOnStack(StackPtr, VA.getLocMemOffset(), 2813 Chain, Arg, DL, IsTailCall, DAG)); 2814 } 2815 2816 // Transform all store nodes into one single node because all store 2817 // nodes are independent of each other. 2818 if (!MemOpChains.empty()) 2819 Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, MemOpChains); 2820 2821 // If the callee is a GlobalAddress/ExternalSymbol node (quite common, every 2822 // direct call is) turn it into a TargetGlobalAddress/TargetExternalSymbol 2823 // node so that legalize doesn't hack it. 2824 bool IsPICCall = (ABI.IsN64() || IsPIC); // true if calls are translated to 2825 // jalr $25 2826 bool GlobalOrExternal = false, InternalLinkage = false, IsCallReloc = false; 2827 SDValue CalleeLo; 2828 EVT Ty = Callee.getValueType(); 2829 2830 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) { 2831 if (IsPICCall) { 2832 const GlobalValue *Val = G->getGlobal(); 2833 InternalLinkage = Val->hasInternalLinkage(); 2834 2835 if (InternalLinkage) 2836 Callee = getAddrLocal(G, DL, Ty, DAG, ABI.IsN32() || ABI.IsN64()); 2837 else if (LargeGOT) { 2838 Callee = getAddrGlobalLargeGOT(G, DL, Ty, DAG, MipsII::MO_CALL_HI16, 2839 MipsII::MO_CALL_LO16, Chain, 2840 FuncInfo->callPtrInfo(Val)); 2841 IsCallReloc = true; 2842 } else { 2843 Callee = getAddrGlobal(G, DL, Ty, DAG, MipsII::MO_GOT_CALL, Chain, 2844 FuncInfo->callPtrInfo(Val)); 2845 IsCallReloc = true; 2846 } 2847 } else 2848 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), DL, 2849 getPointerTy(DAG.getDataLayout()), 0, 2850 MipsII::MO_NO_FLAG); 2851 GlobalOrExternal = true; 2852 } 2853 else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) { 2854 const char *Sym = S->getSymbol(); 2855 2856 if (!ABI.IsN64() && !IsPIC) // !N64 && static 2857 Callee = DAG.getTargetExternalSymbol( 2858 Sym, getPointerTy(DAG.getDataLayout()), MipsII::MO_NO_FLAG); 2859 else if (LargeGOT) { 2860 Callee = getAddrGlobalLargeGOT(S, DL, Ty, DAG, MipsII::MO_CALL_HI16, 2861 MipsII::MO_CALL_LO16, Chain, 2862 FuncInfo->callPtrInfo(Sym)); 2863 IsCallReloc = true; 2864 } else { // N64 || PIC 2865 Callee = getAddrGlobal(S, DL, Ty, DAG, MipsII::MO_GOT_CALL, Chain, 2866 FuncInfo->callPtrInfo(Sym)); 2867 IsCallReloc = true; 2868 } 2869 2870 GlobalOrExternal = true; 2871 } 2872 2873 SmallVector<SDValue, 8> Ops(1, Chain); 2874 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue); 2875 2876 getOpndList(Ops, RegsToPass, IsPICCall, GlobalOrExternal, InternalLinkage, 2877 IsCallReloc, CLI, Callee, Chain); 2878 2879 if (IsTailCall) { 2880 MF.getFrameInfo().setHasTailCall(); 2881 return DAG.getNode(MipsISD::TailCall, DL, MVT::Other, Ops); 2882 } 2883 2884 Chain = DAG.getNode(MipsISD::JmpLink, DL, NodeTys, Ops); 2885 SDValue InFlag = Chain.getValue(1); 2886 2887 // Create the CALLSEQ_END node. 2888 Chain = DAG.getCALLSEQ_END(Chain, NextStackOffsetVal, 2889 DAG.getIntPtrConstant(0, DL, true), InFlag, DL); 2890 InFlag = Chain.getValue(1); 2891 2892 // Handle result values, copying them out of physregs into vregs that we 2893 // return. 2894 return LowerCallResult(Chain, InFlag, CallConv, IsVarArg, Ins, DL, DAG, 2895 InVals, CLI); 2896 } 2897 2898 /// LowerCallResult - Lower the result values of a call into the 2899 /// appropriate copies out of appropriate physical registers. 2900 SDValue MipsTargetLowering::LowerCallResult( 2901 SDValue Chain, SDValue InFlag, CallingConv::ID CallConv, bool IsVarArg, 2902 const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &DL, 2903 SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals, 2904 TargetLowering::CallLoweringInfo &CLI) const { 2905 // Assign locations to each value returned by this call. 2906 SmallVector<CCValAssign, 16> RVLocs; 2907 MipsCCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), RVLocs, 2908 *DAG.getContext()); 2909 CCInfo.AnalyzeCallResult(Ins, RetCC_Mips, CLI); 2910 2911 // Copy all of the result registers out of their specified physreg. 2912 for (unsigned i = 0; i != RVLocs.size(); ++i) { 2913 CCValAssign &VA = RVLocs[i]; 2914 assert(VA.isRegLoc() && "Can only return in registers!"); 2915 2916 SDValue Val = DAG.getCopyFromReg(Chain, DL, RVLocs[i].getLocReg(), 2917 RVLocs[i].getLocVT(), InFlag); 2918 Chain = Val.getValue(1); 2919 InFlag = Val.getValue(2); 2920 2921 if (VA.isUpperBitsInLoc()) { 2922 unsigned ValSizeInBits = Ins[i].ArgVT.getSizeInBits(); 2923 unsigned LocSizeInBits = VA.getLocVT().getSizeInBits(); 2924 unsigned Shift = 2925 VA.getLocInfo() == CCValAssign::ZExtUpper ? ISD::SRL : ISD::SRA; 2926 Val = DAG.getNode( 2927 Shift, DL, VA.getLocVT(), Val, 2928 DAG.getConstant(LocSizeInBits - ValSizeInBits, DL, VA.getLocVT())); 2929 } 2930 2931 switch (VA.getLocInfo()) { 2932 default: 2933 llvm_unreachable("Unknown loc info!"); 2934 case CCValAssign::Full: 2935 break; 2936 case CCValAssign::BCvt: 2937 Val = DAG.getNode(ISD::BITCAST, DL, VA.getValVT(), Val); 2938 break; 2939 case CCValAssign::AExt: 2940 case CCValAssign::AExtUpper: 2941 Val = DAG.getNode(ISD::TRUNCATE, DL, VA.getValVT(), Val); 2942 break; 2943 case CCValAssign::ZExt: 2944 case CCValAssign::ZExtUpper: 2945 Val = DAG.getNode(ISD::AssertZext, DL, VA.getLocVT(), Val, 2946 DAG.getValueType(VA.getValVT())); 2947 Val = DAG.getNode(ISD::TRUNCATE, DL, VA.getValVT(), Val); 2948 break; 2949 case CCValAssign::SExt: 2950 case CCValAssign::SExtUpper: 2951 Val = DAG.getNode(ISD::AssertSext, DL, VA.getLocVT(), Val, 2952 DAG.getValueType(VA.getValVT())); 2953 Val = DAG.getNode(ISD::TRUNCATE, DL, VA.getValVT(), Val); 2954 break; 2955 } 2956 2957 InVals.push_back(Val); 2958 } 2959 2960 return Chain; 2961 } 2962 2963 static SDValue UnpackFromArgumentSlot(SDValue Val, const CCValAssign &VA, 2964 EVT ArgVT, const SDLoc &DL, 2965 SelectionDAG &DAG) { 2966 MVT LocVT = VA.getLocVT(); 2967 EVT ValVT = VA.getValVT(); 2968 2969 // Shift into the upper bits if necessary. 2970 switch (VA.getLocInfo()) { 2971 default: 2972 break; 2973 case CCValAssign::AExtUpper: 2974 case CCValAssign::SExtUpper: 2975 case CCValAssign::ZExtUpper: { 2976 unsigned ValSizeInBits = ArgVT.getSizeInBits(); 2977 unsigned LocSizeInBits = VA.getLocVT().getSizeInBits(); 2978 unsigned Opcode = 2979 VA.getLocInfo() == CCValAssign::ZExtUpper ? ISD::SRL : ISD::SRA; 2980 Val = DAG.getNode( 2981 Opcode, DL, VA.getLocVT(), Val, 2982 DAG.getConstant(LocSizeInBits - ValSizeInBits, DL, VA.getLocVT())); 2983 break; 2984 } 2985 } 2986 2987 // If this is an value smaller than the argument slot size (32-bit for O32, 2988 // 64-bit for N32/N64), it has been promoted in some way to the argument slot 2989 // size. Extract the value and insert any appropriate assertions regarding 2990 // sign/zero extension. 2991 switch (VA.getLocInfo()) { 2992 default: 2993 llvm_unreachable("Unknown loc info!"); 2994 case CCValAssign::Full: 2995 break; 2996 case CCValAssign::AExtUpper: 2997 case CCValAssign::AExt: 2998 Val = DAG.getNode(ISD::TRUNCATE, DL, ValVT, Val); 2999 break; 3000 case CCValAssign::SExtUpper: 3001 case CCValAssign::SExt: 3002 Val = DAG.getNode(ISD::AssertSext, DL, LocVT, Val, DAG.getValueType(ValVT)); 3003 Val = DAG.getNode(ISD::TRUNCATE, DL, ValVT, Val); 3004 break; 3005 case CCValAssign::ZExtUpper: 3006 case CCValAssign::ZExt: 3007 Val = DAG.getNode(ISD::AssertZext, DL, LocVT, Val, DAG.getValueType(ValVT)); 3008 Val = DAG.getNode(ISD::TRUNCATE, DL, ValVT, Val); 3009 break; 3010 case CCValAssign::BCvt: 3011 Val = DAG.getNode(ISD::BITCAST, DL, ValVT, Val); 3012 break; 3013 } 3014 3015 return Val; 3016 } 3017 3018 //===----------------------------------------------------------------------===// 3019 // Formal Arguments Calling Convention Implementation 3020 //===----------------------------------------------------------------------===// 3021 /// LowerFormalArguments - transform physical registers into virtual registers 3022 /// and generate load operations for arguments places on the stack. 3023 SDValue MipsTargetLowering::LowerFormalArguments( 3024 SDValue Chain, CallingConv::ID CallConv, bool IsVarArg, 3025 const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &DL, 3026 SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const { 3027 MachineFunction &MF = DAG.getMachineFunction(); 3028 MachineFrameInfo &MFI = MF.getFrameInfo(); 3029 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>(); 3030 3031 MipsFI->setVarArgsFrameIndex(0); 3032 3033 // Used with vargs to acumulate store chains. 3034 std::vector<SDValue> OutChains; 3035 3036 // Assign locations to all of the incoming arguments. 3037 SmallVector<CCValAssign, 16> ArgLocs; 3038 MipsCCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), ArgLocs, 3039 *DAG.getContext()); 3040 CCInfo.AllocateStack(ABI.GetCalleeAllocdArgSizeInBytes(CallConv), 1); 3041 const Function *Func = DAG.getMachineFunction().getFunction(); 3042 Function::const_arg_iterator FuncArg = Func->arg_begin(); 3043 3044 if (Func->hasFnAttribute("interrupt") && !Func->arg_empty()) 3045 report_fatal_error( 3046 "Functions with the interrupt attribute cannot have arguments!"); 3047 3048 CCInfo.AnalyzeFormalArguments(Ins, CC_Mips_FixedArg); 3049 MipsFI->setFormalArgInfo(CCInfo.getNextStackOffset(), 3050 CCInfo.getInRegsParamsCount() > 0); 3051 3052 unsigned CurArgIdx = 0; 3053 CCInfo.rewindByValRegsInfo(); 3054 3055 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { 3056 CCValAssign &VA = ArgLocs[i]; 3057 if (Ins[i].isOrigArg()) { 3058 std::advance(FuncArg, Ins[i].getOrigArgIndex() - CurArgIdx); 3059 CurArgIdx = Ins[i].getOrigArgIndex(); 3060 } 3061 EVT ValVT = VA.getValVT(); 3062 ISD::ArgFlagsTy Flags = Ins[i].Flags; 3063 bool IsRegLoc = VA.isRegLoc(); 3064 3065 if (Flags.isByVal()) { 3066 assert(Ins[i].isOrigArg() && "Byval arguments cannot be implicit"); 3067 unsigned FirstByValReg, LastByValReg; 3068 unsigned ByValIdx = CCInfo.getInRegsParamsProcessed(); 3069 CCInfo.getInRegsParamInfo(ByValIdx, FirstByValReg, LastByValReg); 3070 3071 assert(Flags.getByValSize() && 3072 "ByVal args of size 0 should have been ignored by front-end."); 3073 assert(ByValIdx < CCInfo.getInRegsParamsCount()); 3074 copyByValRegs(Chain, DL, OutChains, DAG, Flags, InVals, &*FuncArg, 3075 FirstByValReg, LastByValReg, VA, CCInfo); 3076 CCInfo.nextInRegsParam(); 3077 continue; 3078 } 3079 3080 // Arguments stored on registers 3081 if (IsRegLoc) { 3082 MVT RegVT = VA.getLocVT(); 3083 unsigned ArgReg = VA.getLocReg(); 3084 const TargetRegisterClass *RC = getRegClassFor(RegVT); 3085 3086 // Transform the arguments stored on 3087 // physical registers into virtual ones 3088 unsigned Reg = addLiveIn(DAG.getMachineFunction(), ArgReg, RC); 3089 SDValue ArgValue = DAG.getCopyFromReg(Chain, DL, Reg, RegVT); 3090 3091 ArgValue = UnpackFromArgumentSlot(ArgValue, VA, Ins[i].ArgVT, DL, DAG); 3092 3093 // Handle floating point arguments passed in integer registers and 3094 // long double arguments passed in floating point registers. 3095 if ((RegVT == MVT::i32 && ValVT == MVT::f32) || 3096 (RegVT == MVT::i64 && ValVT == MVT::f64) || 3097 (RegVT == MVT::f64 && ValVT == MVT::i64)) 3098 ArgValue = DAG.getNode(ISD::BITCAST, DL, ValVT, ArgValue); 3099 else if (ABI.IsO32() && RegVT == MVT::i32 && 3100 ValVT == MVT::f64) { 3101 unsigned Reg2 = addLiveIn(DAG.getMachineFunction(), 3102 getNextIntArgReg(ArgReg), RC); 3103 SDValue ArgValue2 = DAG.getCopyFromReg(Chain, DL, Reg2, RegVT); 3104 if (!Subtarget.isLittle()) 3105 std::swap(ArgValue, ArgValue2); 3106 ArgValue = DAG.getNode(MipsISD::BuildPairF64, DL, MVT::f64, 3107 ArgValue, ArgValue2); 3108 } 3109 3110 InVals.push_back(ArgValue); 3111 } else { // VA.isRegLoc() 3112 MVT LocVT = VA.getLocVT(); 3113 3114 if (ABI.IsO32()) { 3115 // We ought to be able to use LocVT directly but O32 sets it to i32 3116 // when allocating floating point values to integer registers. 3117 // This shouldn't influence how we load the value into registers unless 3118 // we are targeting softfloat. 3119 if (VA.getValVT().isFloatingPoint() && !Subtarget.useSoftFloat()) 3120 LocVT = VA.getValVT(); 3121 } 3122 3123 // sanity check 3124 assert(VA.isMemLoc()); 3125 3126 // The stack pointer offset is relative to the caller stack frame. 3127 int FI = MFI.CreateFixedObject(LocVT.getSizeInBits() / 8, 3128 VA.getLocMemOffset(), true); 3129 3130 // Create load nodes to retrieve arguments from the stack 3131 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy(DAG.getDataLayout())); 3132 SDValue ArgValue = DAG.getLoad( 3133 LocVT, DL, Chain, FIN, 3134 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), FI)); 3135 OutChains.push_back(ArgValue.getValue(1)); 3136 3137 ArgValue = UnpackFromArgumentSlot(ArgValue, VA, Ins[i].ArgVT, DL, DAG); 3138 3139 InVals.push_back(ArgValue); 3140 } 3141 } 3142 3143 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { 3144 // The mips ABIs for returning structs by value requires that we copy 3145 // the sret argument into $v0 for the return. Save the argument into 3146 // a virtual register so that we can access it from the return points. 3147 if (Ins[i].Flags.isSRet()) { 3148 unsigned Reg = MipsFI->getSRetReturnReg(); 3149 if (!Reg) { 3150 Reg = MF.getRegInfo().createVirtualRegister( 3151 getRegClassFor(ABI.IsN64() ? MVT::i64 : MVT::i32)); 3152 MipsFI->setSRetReturnReg(Reg); 3153 } 3154 SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), DL, Reg, InVals[i]); 3155 Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, Copy, Chain); 3156 break; 3157 } 3158 } 3159 3160 if (IsVarArg) 3161 writeVarArgRegs(OutChains, Chain, DL, DAG, CCInfo); 3162 3163 // All stores are grouped in one node to allow the matching between 3164 // the size of Ins and InVals. This only happens when on varg functions 3165 if (!OutChains.empty()) { 3166 OutChains.push_back(Chain); 3167 Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, OutChains); 3168 } 3169 3170 return Chain; 3171 } 3172 3173 //===----------------------------------------------------------------------===// 3174 // Return Value Calling Convention Implementation 3175 //===----------------------------------------------------------------------===// 3176 3177 bool 3178 MipsTargetLowering::CanLowerReturn(CallingConv::ID CallConv, 3179 MachineFunction &MF, bool IsVarArg, 3180 const SmallVectorImpl<ISD::OutputArg> &Outs, 3181 LLVMContext &Context) const { 3182 SmallVector<CCValAssign, 16> RVLocs; 3183 MipsCCState CCInfo(CallConv, IsVarArg, MF, RVLocs, Context); 3184 return CCInfo.CheckReturn(Outs, RetCC_Mips); 3185 } 3186 3187 bool 3188 MipsTargetLowering::shouldSignExtendTypeInLibCall(EVT Type, bool IsSigned) const { 3189 if (Subtarget.hasMips3() && Subtarget.useSoftFloat()) { 3190 if (Type == MVT::i32) 3191 return true; 3192 } 3193 return IsSigned; 3194 } 3195 3196 SDValue 3197 MipsTargetLowering::LowerInterruptReturn(SmallVectorImpl<SDValue> &RetOps, 3198 const SDLoc &DL, 3199 SelectionDAG &DAG) const { 3200 3201 MachineFunction &MF = DAG.getMachineFunction(); 3202 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>(); 3203 3204 MipsFI->setISR(); 3205 3206 return DAG.getNode(MipsISD::ERet, DL, MVT::Other, RetOps); 3207 } 3208 3209 SDValue 3210 MipsTargetLowering::LowerReturn(SDValue Chain, CallingConv::ID CallConv, 3211 bool IsVarArg, 3212 const SmallVectorImpl<ISD::OutputArg> &Outs, 3213 const SmallVectorImpl<SDValue> &OutVals, 3214 const SDLoc &DL, SelectionDAG &DAG) const { 3215 // CCValAssign - represent the assignment of 3216 // the return value to a location 3217 SmallVector<CCValAssign, 16> RVLocs; 3218 MachineFunction &MF = DAG.getMachineFunction(); 3219 3220 // CCState - Info about the registers and stack slot. 3221 MipsCCState CCInfo(CallConv, IsVarArg, MF, RVLocs, *DAG.getContext()); 3222 3223 // Analyze return values. 3224 CCInfo.AnalyzeReturn(Outs, RetCC_Mips); 3225 3226 SDValue Flag; 3227 SmallVector<SDValue, 4> RetOps(1, Chain); 3228 3229 // Copy the result values into the output registers. 3230 for (unsigned i = 0; i != RVLocs.size(); ++i) { 3231 SDValue Val = OutVals[i]; 3232 CCValAssign &VA = RVLocs[i]; 3233 assert(VA.isRegLoc() && "Can only return in registers!"); 3234 bool UseUpperBits = false; 3235 3236 switch (VA.getLocInfo()) { 3237 default: 3238 llvm_unreachable("Unknown loc info!"); 3239 case CCValAssign::Full: 3240 break; 3241 case CCValAssign::BCvt: 3242 Val = DAG.getNode(ISD::BITCAST, DL, VA.getLocVT(), Val); 3243 break; 3244 case CCValAssign::AExtUpper: 3245 UseUpperBits = true; 3246 LLVM_FALLTHROUGH; 3247 case CCValAssign::AExt: 3248 Val = DAG.getNode(ISD::ANY_EXTEND, DL, VA.getLocVT(), Val); 3249 break; 3250 case CCValAssign::ZExtUpper: 3251 UseUpperBits = true; 3252 LLVM_FALLTHROUGH; 3253 case CCValAssign::ZExt: 3254 Val = DAG.getNode(ISD::ZERO_EXTEND, DL, VA.getLocVT(), Val); 3255 break; 3256 case CCValAssign::SExtUpper: 3257 UseUpperBits = true; 3258 LLVM_FALLTHROUGH; 3259 case CCValAssign::SExt: 3260 Val = DAG.getNode(ISD::SIGN_EXTEND, DL, VA.getLocVT(), Val); 3261 break; 3262 } 3263 3264 if (UseUpperBits) { 3265 unsigned ValSizeInBits = Outs[i].ArgVT.getSizeInBits(); 3266 unsigned LocSizeInBits = VA.getLocVT().getSizeInBits(); 3267 Val = DAG.getNode( 3268 ISD::SHL, DL, VA.getLocVT(), Val, 3269 DAG.getConstant(LocSizeInBits - ValSizeInBits, DL, VA.getLocVT())); 3270 } 3271 3272 Chain = DAG.getCopyToReg(Chain, DL, VA.getLocReg(), Val, Flag); 3273 3274 // Guarantee that all emitted copies are stuck together with flags. 3275 Flag = Chain.getValue(1); 3276 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT())); 3277 } 3278 3279 // The mips ABIs for returning structs by value requires that we copy 3280 // the sret argument into $v0 for the return. We saved the argument into 3281 // a virtual register in the entry block, so now we copy the value out 3282 // and into $v0. 3283 if (MF.getFunction()->hasStructRetAttr()) { 3284 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>(); 3285 unsigned Reg = MipsFI->getSRetReturnReg(); 3286 3287 if (!Reg) 3288 llvm_unreachable("sret virtual register not created in the entry block"); 3289 SDValue Val = 3290 DAG.getCopyFromReg(Chain, DL, Reg, getPointerTy(DAG.getDataLayout())); 3291 unsigned V0 = ABI.IsN64() ? Mips::V0_64 : Mips::V0; 3292 3293 Chain = DAG.getCopyToReg(Chain, DL, V0, Val, Flag); 3294 Flag = Chain.getValue(1); 3295 RetOps.push_back(DAG.getRegister(V0, getPointerTy(DAG.getDataLayout()))); 3296 } 3297 3298 RetOps[0] = Chain; // Update chain. 3299 3300 // Add the flag if we have it. 3301 if (Flag.getNode()) 3302 RetOps.push_back(Flag); 3303 3304 // ISRs must use "eret". 3305 if (DAG.getMachineFunction().getFunction()->hasFnAttribute("interrupt")) 3306 return LowerInterruptReturn(RetOps, DL, DAG); 3307 3308 // Standard return on Mips is a "jr $ra" 3309 return DAG.getNode(MipsISD::Ret, DL, MVT::Other, RetOps); 3310 } 3311 3312 //===----------------------------------------------------------------------===// 3313 // Mips Inline Assembly Support 3314 //===----------------------------------------------------------------------===// 3315 3316 /// getConstraintType - Given a constraint letter, return the type of 3317 /// constraint it is for this target. 3318 MipsTargetLowering::ConstraintType 3319 MipsTargetLowering::getConstraintType(StringRef Constraint) const { 3320 // Mips specific constraints 3321 // GCC config/mips/constraints.md 3322 // 3323 // 'd' : An address register. Equivalent to r 3324 // unless generating MIPS16 code. 3325 // 'y' : Equivalent to r; retained for 3326 // backwards compatibility. 3327 // 'c' : A register suitable for use in an indirect 3328 // jump. This will always be $25 for -mabicalls. 3329 // 'l' : The lo register. 1 word storage. 3330 // 'x' : The hilo register pair. Double word storage. 3331 if (Constraint.size() == 1) { 3332 switch (Constraint[0]) { 3333 default : break; 3334 case 'd': 3335 case 'y': 3336 case 'f': 3337 case 'c': 3338 case 'l': 3339 case 'x': 3340 return C_RegisterClass; 3341 case 'R': 3342 return C_Memory; 3343 } 3344 } 3345 3346 if (Constraint == "ZC") 3347 return C_Memory; 3348 3349 return TargetLowering::getConstraintType(Constraint); 3350 } 3351 3352 /// Examine constraint type and operand type and determine a weight value. 3353 /// This object must already have been set up with the operand type 3354 /// and the current alternative constraint selected. 3355 TargetLowering::ConstraintWeight 3356 MipsTargetLowering::getSingleConstraintMatchWeight( 3357 AsmOperandInfo &info, const char *constraint) const { 3358 ConstraintWeight weight = CW_Invalid; 3359 Value *CallOperandVal = info.CallOperandVal; 3360 // If we don't have a value, we can't do a match, 3361 // but allow it at the lowest weight. 3362 if (!CallOperandVal) 3363 return CW_Default; 3364 Type *type = CallOperandVal->getType(); 3365 // Look at the constraint type. 3366 switch (*constraint) { 3367 default: 3368 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint); 3369 break; 3370 case 'd': 3371 case 'y': 3372 if (type->isIntegerTy()) 3373 weight = CW_Register; 3374 break; 3375 case 'f': // FPU or MSA register 3376 if (Subtarget.hasMSA() && type->isVectorTy() && 3377 cast<VectorType>(type)->getBitWidth() == 128) 3378 weight = CW_Register; 3379 else if (type->isFloatTy()) 3380 weight = CW_Register; 3381 break; 3382 case 'c': // $25 for indirect jumps 3383 case 'l': // lo register 3384 case 'x': // hilo register pair 3385 if (type->isIntegerTy()) 3386 weight = CW_SpecificReg; 3387 break; 3388 case 'I': // signed 16 bit immediate 3389 case 'J': // integer zero 3390 case 'K': // unsigned 16 bit immediate 3391 case 'L': // signed 32 bit immediate where lower 16 bits are 0 3392 case 'N': // immediate in the range of -65535 to -1 (inclusive) 3393 case 'O': // signed 15 bit immediate (+- 16383) 3394 case 'P': // immediate in the range of 65535 to 1 (inclusive) 3395 if (isa<ConstantInt>(CallOperandVal)) 3396 weight = CW_Constant; 3397 break; 3398 case 'R': 3399 weight = CW_Memory; 3400 break; 3401 } 3402 return weight; 3403 } 3404 3405 /// This is a helper function to parse a physical register string and split it 3406 /// into non-numeric and numeric parts (Prefix and Reg). The first boolean flag 3407 /// that is returned indicates whether parsing was successful. The second flag 3408 /// is true if the numeric part exists. 3409 static std::pair<bool, bool> parsePhysicalReg(StringRef C, StringRef &Prefix, 3410 unsigned long long &Reg) { 3411 if (C.front() != '{' || C.back() != '}') 3412 return std::make_pair(false, false); 3413 3414 // Search for the first numeric character. 3415 StringRef::const_iterator I, B = C.begin() + 1, E = C.end() - 1; 3416 I = std::find_if(B, E, isdigit); 3417 3418 Prefix = StringRef(B, I - B); 3419 3420 // The second flag is set to false if no numeric characters were found. 3421 if (I == E) 3422 return std::make_pair(true, false); 3423 3424 // Parse the numeric characters. 3425 return std::make_pair(!getAsUnsignedInteger(StringRef(I, E - I), 10, Reg), 3426 true); 3427 } 3428 3429 std::pair<unsigned, const TargetRegisterClass *> MipsTargetLowering:: 3430 parseRegForInlineAsmConstraint(StringRef C, MVT VT) const { 3431 const TargetRegisterInfo *TRI = 3432 Subtarget.getRegisterInfo(); 3433 const TargetRegisterClass *RC; 3434 StringRef Prefix; 3435 unsigned long long Reg; 3436 3437 std::pair<bool, bool> R = parsePhysicalReg(C, Prefix, Reg); 3438 3439 if (!R.first) 3440 return std::make_pair(0U, nullptr); 3441 3442 if ((Prefix == "hi" || Prefix == "lo")) { // Parse hi/lo. 3443 // No numeric characters follow "hi" or "lo". 3444 if (R.second) 3445 return std::make_pair(0U, nullptr); 3446 3447 RC = TRI->getRegClass(Prefix == "hi" ? 3448 Mips::HI32RegClassID : Mips::LO32RegClassID); 3449 return std::make_pair(*(RC->begin()), RC); 3450 } else if (Prefix.startswith("$msa")) { 3451 // Parse $msa(ir|csr|access|save|modify|request|map|unmap) 3452 3453 // No numeric characters follow the name. 3454 if (R.second) 3455 return std::make_pair(0U, nullptr); 3456 3457 Reg = StringSwitch<unsigned long long>(Prefix) 3458 .Case("$msair", Mips::MSAIR) 3459 .Case("$msacsr", Mips::MSACSR) 3460 .Case("$msaaccess", Mips::MSAAccess) 3461 .Case("$msasave", Mips::MSASave) 3462 .Case("$msamodify", Mips::MSAModify) 3463 .Case("$msarequest", Mips::MSARequest) 3464 .Case("$msamap", Mips::MSAMap) 3465 .Case("$msaunmap", Mips::MSAUnmap) 3466 .Default(0); 3467 3468 if (!Reg) 3469 return std::make_pair(0U, nullptr); 3470 3471 RC = TRI->getRegClass(Mips::MSACtrlRegClassID); 3472 return std::make_pair(Reg, RC); 3473 } 3474 3475 if (!R.second) 3476 return std::make_pair(0U, nullptr); 3477 3478 if (Prefix == "$f") { // Parse $f0-$f31. 3479 // If the size of FP registers is 64-bit or Reg is an even number, select 3480 // the 64-bit register class. Otherwise, select the 32-bit register class. 3481 if (VT == MVT::Other) 3482 VT = (Subtarget.isFP64bit() || !(Reg % 2)) ? MVT::f64 : MVT::f32; 3483 3484 RC = getRegClassFor(VT); 3485 3486 if (RC == &Mips::AFGR64RegClass) { 3487 assert(Reg % 2 == 0); 3488 Reg >>= 1; 3489 } 3490 } else if (Prefix == "$fcc") // Parse $fcc0-$fcc7. 3491 RC = TRI->getRegClass(Mips::FCCRegClassID); 3492 else if (Prefix == "$w") { // Parse $w0-$w31. 3493 RC = getRegClassFor((VT == MVT::Other) ? MVT::v16i8 : VT); 3494 } else { // Parse $0-$31. 3495 assert(Prefix == "$"); 3496 RC = getRegClassFor((VT == MVT::Other) ? MVT::i32 : VT); 3497 } 3498 3499 assert(Reg < RC->getNumRegs()); 3500 return std::make_pair(*(RC->begin() + Reg), RC); 3501 } 3502 3503 /// Given a register class constraint, like 'r', if this corresponds directly 3504 /// to an LLVM register class, return a register of 0 and the register class 3505 /// pointer. 3506 std::pair<unsigned, const TargetRegisterClass *> 3507 MipsTargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, 3508 StringRef Constraint, 3509 MVT VT) const { 3510 if (Constraint.size() == 1) { 3511 switch (Constraint[0]) { 3512 case 'd': // Address register. Same as 'r' unless generating MIPS16 code. 3513 case 'y': // Same as 'r'. Exists for compatibility. 3514 case 'r': 3515 if (VT == MVT::i32 || VT == MVT::i16 || VT == MVT::i8) { 3516 if (Subtarget.inMips16Mode()) 3517 return std::make_pair(0U, &Mips::CPU16RegsRegClass); 3518 return std::make_pair(0U, &Mips::GPR32RegClass); 3519 } 3520 if (VT == MVT::i64 && !Subtarget.isGP64bit()) 3521 return std::make_pair(0U, &Mips::GPR32RegClass); 3522 if (VT == MVT::i64 && Subtarget.isGP64bit()) 3523 return std::make_pair(0U, &Mips::GPR64RegClass); 3524 // This will generate an error message 3525 return std::make_pair(0U, nullptr); 3526 case 'f': // FPU or MSA register 3527 if (VT == MVT::v16i8) 3528 return std::make_pair(0U, &Mips::MSA128BRegClass); 3529 else if (VT == MVT::v8i16 || VT == MVT::v8f16) 3530 return std::make_pair(0U, &Mips::MSA128HRegClass); 3531 else if (VT == MVT::v4i32 || VT == MVT::v4f32) 3532 return std::make_pair(0U, &Mips::MSA128WRegClass); 3533 else if (VT == MVT::v2i64 || VT == MVT::v2f64) 3534 return std::make_pair(0U, &Mips::MSA128DRegClass); 3535 else if (VT == MVT::f32) 3536 return std::make_pair(0U, &Mips::FGR32RegClass); 3537 else if ((VT == MVT::f64) && (!Subtarget.isSingleFloat())) { 3538 if (Subtarget.isFP64bit()) 3539 return std::make_pair(0U, &Mips::FGR64RegClass); 3540 return std::make_pair(0U, &Mips::AFGR64RegClass); 3541 } 3542 break; 3543 case 'c': // register suitable for indirect jump 3544 if (VT == MVT::i32) 3545 return std::make_pair((unsigned)Mips::T9, &Mips::GPR32RegClass); 3546 assert(VT == MVT::i64 && "Unexpected type."); 3547 return std::make_pair((unsigned)Mips::T9_64, &Mips::GPR64RegClass); 3548 case 'l': // register suitable for indirect jump 3549 if (VT == MVT::i32) 3550 return std::make_pair((unsigned)Mips::LO0, &Mips::LO32RegClass); 3551 return std::make_pair((unsigned)Mips::LO0_64, &Mips::LO64RegClass); 3552 case 'x': // register suitable for indirect jump 3553 // Fixme: Not triggering the use of both hi and low 3554 // This will generate an error message 3555 return std::make_pair(0U, nullptr); 3556 } 3557 } 3558 3559 std::pair<unsigned, const TargetRegisterClass *> R; 3560 R = parseRegForInlineAsmConstraint(Constraint, VT); 3561 3562 if (R.second) 3563 return R; 3564 3565 return TargetLowering::getRegForInlineAsmConstraint(TRI, Constraint, VT); 3566 } 3567 3568 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops 3569 /// vector. If it is invalid, don't add anything to Ops. 3570 void MipsTargetLowering::LowerAsmOperandForConstraint(SDValue Op, 3571 std::string &Constraint, 3572 std::vector<SDValue>&Ops, 3573 SelectionDAG &DAG) const { 3574 SDLoc DL(Op); 3575 SDValue Result; 3576 3577 // Only support length 1 constraints for now. 3578 if (Constraint.length() > 1) return; 3579 3580 char ConstraintLetter = Constraint[0]; 3581 switch (ConstraintLetter) { 3582 default: break; // This will fall through to the generic implementation 3583 case 'I': // Signed 16 bit constant 3584 // If this fails, the parent routine will give an error 3585 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 3586 EVT Type = Op.getValueType(); 3587 int64_t Val = C->getSExtValue(); 3588 if (isInt<16>(Val)) { 3589 Result = DAG.getTargetConstant(Val, DL, Type); 3590 break; 3591 } 3592 } 3593 return; 3594 case 'J': // integer zero 3595 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 3596 EVT Type = Op.getValueType(); 3597 int64_t Val = C->getZExtValue(); 3598 if (Val == 0) { 3599 Result = DAG.getTargetConstant(0, DL, Type); 3600 break; 3601 } 3602 } 3603 return; 3604 case 'K': // unsigned 16 bit immediate 3605 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 3606 EVT Type = Op.getValueType(); 3607 uint64_t Val = (uint64_t)C->getZExtValue(); 3608 if (isUInt<16>(Val)) { 3609 Result = DAG.getTargetConstant(Val, DL, Type); 3610 break; 3611 } 3612 } 3613 return; 3614 case 'L': // signed 32 bit immediate where lower 16 bits are 0 3615 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 3616 EVT Type = Op.getValueType(); 3617 int64_t Val = C->getSExtValue(); 3618 if ((isInt<32>(Val)) && ((Val & 0xffff) == 0)){ 3619 Result = DAG.getTargetConstant(Val, DL, Type); 3620 break; 3621 } 3622 } 3623 return; 3624 case 'N': // immediate in the range of -65535 to -1 (inclusive) 3625 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 3626 EVT Type = Op.getValueType(); 3627 int64_t Val = C->getSExtValue(); 3628 if ((Val >= -65535) && (Val <= -1)) { 3629 Result = DAG.getTargetConstant(Val, DL, Type); 3630 break; 3631 } 3632 } 3633 return; 3634 case 'O': // signed 15 bit immediate 3635 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 3636 EVT Type = Op.getValueType(); 3637 int64_t Val = C->getSExtValue(); 3638 if ((isInt<15>(Val))) { 3639 Result = DAG.getTargetConstant(Val, DL, Type); 3640 break; 3641 } 3642 } 3643 return; 3644 case 'P': // immediate in the range of 1 to 65535 (inclusive) 3645 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 3646 EVT Type = Op.getValueType(); 3647 int64_t Val = C->getSExtValue(); 3648 if ((Val <= 65535) && (Val >= 1)) { 3649 Result = DAG.getTargetConstant(Val, DL, Type); 3650 break; 3651 } 3652 } 3653 return; 3654 } 3655 3656 if (Result.getNode()) { 3657 Ops.push_back(Result); 3658 return; 3659 } 3660 3661 TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG); 3662 } 3663 3664 bool MipsTargetLowering::isLegalAddressingMode(const DataLayout &DL, 3665 const AddrMode &AM, Type *Ty, 3666 unsigned AS) const { 3667 // No global is ever allowed as a base. 3668 if (AM.BaseGV) 3669 return false; 3670 3671 switch (AM.Scale) { 3672 case 0: // "r+i" or just "i", depending on HasBaseReg. 3673 break; 3674 case 1: 3675 if (!AM.HasBaseReg) // allow "r+i". 3676 break; 3677 return false; // disallow "r+r" or "r+r+i". 3678 default: 3679 return false; 3680 } 3681 3682 return true; 3683 } 3684 3685 bool 3686 MipsTargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const { 3687 // The Mips target isn't yet aware of offsets. 3688 return false; 3689 } 3690 3691 EVT MipsTargetLowering::getOptimalMemOpType(uint64_t Size, unsigned DstAlign, 3692 unsigned SrcAlign, 3693 bool IsMemset, bool ZeroMemset, 3694 bool MemcpyStrSrc, 3695 MachineFunction &MF) const { 3696 if (Subtarget.hasMips64()) 3697 return MVT::i64; 3698 3699 return MVT::i32; 3700 } 3701 3702 bool MipsTargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const { 3703 if (VT != MVT::f32 && VT != MVT::f64) 3704 return false; 3705 if (Imm.isNegZero()) 3706 return false; 3707 return Imm.isZero(); 3708 } 3709 3710 unsigned MipsTargetLowering::getJumpTableEncoding() const { 3711 if (ABI.IsN64()) 3712 return MachineJumpTableInfo::EK_GPRel64BlockAddress; 3713 3714 return TargetLowering::getJumpTableEncoding(); 3715 } 3716 3717 bool MipsTargetLowering::useSoftFloat() const { 3718 return Subtarget.useSoftFloat(); 3719 } 3720 3721 void MipsTargetLowering::copyByValRegs( 3722 SDValue Chain, const SDLoc &DL, std::vector<SDValue> &OutChains, 3723 SelectionDAG &DAG, const ISD::ArgFlagsTy &Flags, 3724 SmallVectorImpl<SDValue> &InVals, const Argument *FuncArg, 3725 unsigned FirstReg, unsigned LastReg, const CCValAssign &VA, 3726 MipsCCState &State) const { 3727 MachineFunction &MF = DAG.getMachineFunction(); 3728 MachineFrameInfo &MFI = MF.getFrameInfo(); 3729 unsigned GPRSizeInBytes = Subtarget.getGPRSizeInBytes(); 3730 unsigned NumRegs = LastReg - FirstReg; 3731 unsigned RegAreaSize = NumRegs * GPRSizeInBytes; 3732 unsigned FrameObjSize = std::max(Flags.getByValSize(), RegAreaSize); 3733 int FrameObjOffset; 3734 ArrayRef<MCPhysReg> ByValArgRegs = ABI.GetByValArgRegs(); 3735 3736 if (RegAreaSize) 3737 FrameObjOffset = 3738 (int)ABI.GetCalleeAllocdArgSizeInBytes(State.getCallingConv()) - 3739 (int)((ByValArgRegs.size() - FirstReg) * GPRSizeInBytes); 3740 else 3741 FrameObjOffset = VA.getLocMemOffset(); 3742 3743 // Create frame object. 3744 EVT PtrTy = getPointerTy(DAG.getDataLayout()); 3745 int FI = MFI.CreateFixedObject(FrameObjSize, FrameObjOffset, true); 3746 SDValue FIN = DAG.getFrameIndex(FI, PtrTy); 3747 InVals.push_back(FIN); 3748 3749 if (!NumRegs) 3750 return; 3751 3752 // Copy arg registers. 3753 MVT RegTy = MVT::getIntegerVT(GPRSizeInBytes * 8); 3754 const TargetRegisterClass *RC = getRegClassFor(RegTy); 3755 3756 for (unsigned I = 0; I < NumRegs; ++I) { 3757 unsigned ArgReg = ByValArgRegs[FirstReg + I]; 3758 unsigned VReg = addLiveIn(MF, ArgReg, RC); 3759 unsigned Offset = I * GPRSizeInBytes; 3760 SDValue StorePtr = DAG.getNode(ISD::ADD, DL, PtrTy, FIN, 3761 DAG.getConstant(Offset, DL, PtrTy)); 3762 SDValue Store = DAG.getStore(Chain, DL, DAG.getRegister(VReg, RegTy), 3763 StorePtr, MachinePointerInfo(FuncArg, Offset)); 3764 OutChains.push_back(Store); 3765 } 3766 } 3767 3768 // Copy byVal arg to registers and stack. 3769 void MipsTargetLowering::passByValArg( 3770 SDValue Chain, const SDLoc &DL, 3771 std::deque<std::pair<unsigned, SDValue>> &RegsToPass, 3772 SmallVectorImpl<SDValue> &MemOpChains, SDValue StackPtr, 3773 MachineFrameInfo &MFI, SelectionDAG &DAG, SDValue Arg, unsigned FirstReg, 3774 unsigned LastReg, const ISD::ArgFlagsTy &Flags, bool isLittle, 3775 const CCValAssign &VA) const { 3776 unsigned ByValSizeInBytes = Flags.getByValSize(); 3777 unsigned OffsetInBytes = 0; // From beginning of struct 3778 unsigned RegSizeInBytes = Subtarget.getGPRSizeInBytes(); 3779 unsigned Alignment = std::min(Flags.getByValAlign(), RegSizeInBytes); 3780 EVT PtrTy = getPointerTy(DAG.getDataLayout()), 3781 RegTy = MVT::getIntegerVT(RegSizeInBytes * 8); 3782 unsigned NumRegs = LastReg - FirstReg; 3783 3784 if (NumRegs) { 3785 ArrayRef<MCPhysReg> ArgRegs = ABI.GetByValArgRegs(); 3786 bool LeftoverBytes = (NumRegs * RegSizeInBytes > ByValSizeInBytes); 3787 unsigned I = 0; 3788 3789 // Copy words to registers. 3790 for (; I < NumRegs - LeftoverBytes; ++I, OffsetInBytes += RegSizeInBytes) { 3791 SDValue LoadPtr = DAG.getNode(ISD::ADD, DL, PtrTy, Arg, 3792 DAG.getConstant(OffsetInBytes, DL, PtrTy)); 3793 SDValue LoadVal = DAG.getLoad(RegTy, DL, Chain, LoadPtr, 3794 MachinePointerInfo(), Alignment); 3795 MemOpChains.push_back(LoadVal.getValue(1)); 3796 unsigned ArgReg = ArgRegs[FirstReg + I]; 3797 RegsToPass.push_back(std::make_pair(ArgReg, LoadVal)); 3798 } 3799 3800 // Return if the struct has been fully copied. 3801 if (ByValSizeInBytes == OffsetInBytes) 3802 return; 3803 3804 // Copy the remainder of the byval argument with sub-word loads and shifts. 3805 if (LeftoverBytes) { 3806 SDValue Val; 3807 3808 for (unsigned LoadSizeInBytes = RegSizeInBytes / 2, TotalBytesLoaded = 0; 3809 OffsetInBytes < ByValSizeInBytes; LoadSizeInBytes /= 2) { 3810 unsigned RemainingSizeInBytes = ByValSizeInBytes - OffsetInBytes; 3811 3812 if (RemainingSizeInBytes < LoadSizeInBytes) 3813 continue; 3814 3815 // Load subword. 3816 SDValue LoadPtr = DAG.getNode(ISD::ADD, DL, PtrTy, Arg, 3817 DAG.getConstant(OffsetInBytes, DL, 3818 PtrTy)); 3819 SDValue LoadVal = DAG.getExtLoad( 3820 ISD::ZEXTLOAD, DL, RegTy, Chain, LoadPtr, MachinePointerInfo(), 3821 MVT::getIntegerVT(LoadSizeInBytes * 8), Alignment); 3822 MemOpChains.push_back(LoadVal.getValue(1)); 3823 3824 // Shift the loaded value. 3825 unsigned Shamt; 3826 3827 if (isLittle) 3828 Shamt = TotalBytesLoaded * 8; 3829 else 3830 Shamt = (RegSizeInBytes - (TotalBytesLoaded + LoadSizeInBytes)) * 8; 3831 3832 SDValue Shift = DAG.getNode(ISD::SHL, DL, RegTy, LoadVal, 3833 DAG.getConstant(Shamt, DL, MVT::i32)); 3834 3835 if (Val.getNode()) 3836 Val = DAG.getNode(ISD::OR, DL, RegTy, Val, Shift); 3837 else 3838 Val = Shift; 3839 3840 OffsetInBytes += LoadSizeInBytes; 3841 TotalBytesLoaded += LoadSizeInBytes; 3842 Alignment = std::min(Alignment, LoadSizeInBytes); 3843 } 3844 3845 unsigned ArgReg = ArgRegs[FirstReg + I]; 3846 RegsToPass.push_back(std::make_pair(ArgReg, Val)); 3847 return; 3848 } 3849 } 3850 3851 // Copy remainder of byval arg to it with memcpy. 3852 unsigned MemCpySize = ByValSizeInBytes - OffsetInBytes; 3853 SDValue Src = DAG.getNode(ISD::ADD, DL, PtrTy, Arg, 3854 DAG.getConstant(OffsetInBytes, DL, PtrTy)); 3855 SDValue Dst = DAG.getNode(ISD::ADD, DL, PtrTy, StackPtr, 3856 DAG.getIntPtrConstant(VA.getLocMemOffset(), DL)); 3857 Chain = DAG.getMemcpy(Chain, DL, Dst, Src, 3858 DAG.getConstant(MemCpySize, DL, PtrTy), 3859 Alignment, /*isVolatile=*/false, /*AlwaysInline=*/false, 3860 /*isTailCall=*/false, 3861 MachinePointerInfo(), MachinePointerInfo()); 3862 MemOpChains.push_back(Chain); 3863 } 3864 3865 void MipsTargetLowering::writeVarArgRegs(std::vector<SDValue> &OutChains, 3866 SDValue Chain, const SDLoc &DL, 3867 SelectionDAG &DAG, 3868 CCState &State) const { 3869 ArrayRef<MCPhysReg> ArgRegs = ABI.GetVarArgRegs(); 3870 unsigned Idx = State.getFirstUnallocated(ArgRegs); 3871 unsigned RegSizeInBytes = Subtarget.getGPRSizeInBytes(); 3872 MVT RegTy = MVT::getIntegerVT(RegSizeInBytes * 8); 3873 const TargetRegisterClass *RC = getRegClassFor(RegTy); 3874 MachineFunction &MF = DAG.getMachineFunction(); 3875 MachineFrameInfo &MFI = MF.getFrameInfo(); 3876 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>(); 3877 3878 // Offset of the first variable argument from stack pointer. 3879 int VaArgOffset; 3880 3881 if (ArgRegs.size() == Idx) 3882 VaArgOffset = alignTo(State.getNextStackOffset(), RegSizeInBytes); 3883 else { 3884 VaArgOffset = 3885 (int)ABI.GetCalleeAllocdArgSizeInBytes(State.getCallingConv()) - 3886 (int)(RegSizeInBytes * (ArgRegs.size() - Idx)); 3887 } 3888 3889 // Record the frame index of the first variable argument 3890 // which is a value necessary to VASTART. 3891 int FI = MFI.CreateFixedObject(RegSizeInBytes, VaArgOffset, true); 3892 MipsFI->setVarArgsFrameIndex(FI); 3893 3894 // Copy the integer registers that have not been used for argument passing 3895 // to the argument register save area. For O32, the save area is allocated 3896 // in the caller's stack frame, while for N32/64, it is allocated in the 3897 // callee's stack frame. 3898 for (unsigned I = Idx; I < ArgRegs.size(); 3899 ++I, VaArgOffset += RegSizeInBytes) { 3900 unsigned Reg = addLiveIn(MF, ArgRegs[I], RC); 3901 SDValue ArgValue = DAG.getCopyFromReg(Chain, DL, Reg, RegTy); 3902 FI = MFI.CreateFixedObject(RegSizeInBytes, VaArgOffset, true); 3903 SDValue PtrOff = DAG.getFrameIndex(FI, getPointerTy(DAG.getDataLayout())); 3904 SDValue Store = 3905 DAG.getStore(Chain, DL, ArgValue, PtrOff, MachinePointerInfo()); 3906 cast<StoreSDNode>(Store.getNode())->getMemOperand()->setValue( 3907 (Value *)nullptr); 3908 OutChains.push_back(Store); 3909 } 3910 } 3911 3912 void MipsTargetLowering::HandleByVal(CCState *State, unsigned &Size, 3913 unsigned Align) const { 3914 const TargetFrameLowering *TFL = Subtarget.getFrameLowering(); 3915 3916 assert(Size && "Byval argument's size shouldn't be 0."); 3917 3918 Align = std::min(Align, TFL->getStackAlignment()); 3919 3920 unsigned FirstReg = 0; 3921 unsigned NumRegs = 0; 3922 3923 if (State->getCallingConv() != CallingConv::Fast) { 3924 unsigned RegSizeInBytes = Subtarget.getGPRSizeInBytes(); 3925 ArrayRef<MCPhysReg> IntArgRegs = ABI.GetByValArgRegs(); 3926 // FIXME: The O32 case actually describes no shadow registers. 3927 const MCPhysReg *ShadowRegs = 3928 ABI.IsO32() ? IntArgRegs.data() : Mips64DPRegs; 3929 3930 // We used to check the size as well but we can't do that anymore since 3931 // CCState::HandleByVal() rounds up the size after calling this function. 3932 assert(!(Align % RegSizeInBytes) && 3933 "Byval argument's alignment should be a multiple of" 3934 "RegSizeInBytes."); 3935 3936 FirstReg = State->getFirstUnallocated(IntArgRegs); 3937 3938 // If Align > RegSizeInBytes, the first arg register must be even. 3939 // FIXME: This condition happens to do the right thing but it's not the 3940 // right way to test it. We want to check that the stack frame offset 3941 // of the register is aligned. 3942 if ((Align > RegSizeInBytes) && (FirstReg % 2)) { 3943 State->AllocateReg(IntArgRegs[FirstReg], ShadowRegs[FirstReg]); 3944 ++FirstReg; 3945 } 3946 3947 // Mark the registers allocated. 3948 Size = alignTo(Size, RegSizeInBytes); 3949 for (unsigned I = FirstReg; Size > 0 && (I < IntArgRegs.size()); 3950 Size -= RegSizeInBytes, ++I, ++NumRegs) 3951 State->AllocateReg(IntArgRegs[I], ShadowRegs[I]); 3952 } 3953 3954 State->addInRegsParamInfo(FirstReg, FirstReg + NumRegs); 3955 } 3956 3957 MachineBasicBlock *MipsTargetLowering::emitPseudoSELECT(MachineInstr &MI, 3958 MachineBasicBlock *BB, 3959 bool isFPCmp, 3960 unsigned Opc) const { 3961 assert(!(Subtarget.hasMips4() || Subtarget.hasMips32()) && 3962 "Subtarget already supports SELECT nodes with the use of" 3963 "conditional-move instructions."); 3964 3965 const TargetInstrInfo *TII = 3966 Subtarget.getInstrInfo(); 3967 DebugLoc DL = MI.getDebugLoc(); 3968 3969 // To "insert" a SELECT instruction, we actually have to insert the 3970 // diamond control-flow pattern. The incoming instruction knows the 3971 // destination vreg to set, the condition code register to branch on, the 3972 // true/false values to select between, and a branch opcode to use. 3973 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 3974 MachineFunction::iterator It = ++BB->getIterator(); 3975 3976 // thisMBB: 3977 // ... 3978 // TrueVal = ... 3979 // setcc r1, r2, r3 3980 // bNE r1, r0, copy1MBB 3981 // fallthrough --> copy0MBB 3982 MachineBasicBlock *thisMBB = BB; 3983 MachineFunction *F = BB->getParent(); 3984 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB); 3985 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB); 3986 F->insert(It, copy0MBB); 3987 F->insert(It, sinkMBB); 3988 3989 // Transfer the remainder of BB and its successor edges to sinkMBB. 3990 sinkMBB->splice(sinkMBB->begin(), BB, 3991 std::next(MachineBasicBlock::iterator(MI)), BB->end()); 3992 sinkMBB->transferSuccessorsAndUpdatePHIs(BB); 3993 3994 // Next, add the true and fallthrough blocks as its successors. 3995 BB->addSuccessor(copy0MBB); 3996 BB->addSuccessor(sinkMBB); 3997 3998 if (isFPCmp) { 3999 // bc1[tf] cc, sinkMBB 4000 BuildMI(BB, DL, TII->get(Opc)) 4001 .addReg(MI.getOperand(1).getReg()) 4002 .addMBB(sinkMBB); 4003 } else { 4004 // bne rs, $0, sinkMBB 4005 BuildMI(BB, DL, TII->get(Opc)) 4006 .addReg(MI.getOperand(1).getReg()) 4007 .addReg(Mips::ZERO) 4008 .addMBB(sinkMBB); 4009 } 4010 4011 // copy0MBB: 4012 // %FalseValue = ... 4013 // # fallthrough to sinkMBB 4014 BB = copy0MBB; 4015 4016 // Update machine-CFG edges 4017 BB->addSuccessor(sinkMBB); 4018 4019 // sinkMBB: 4020 // %Result = phi [ %TrueValue, thisMBB ], [ %FalseValue, copy0MBB ] 4021 // ... 4022 BB = sinkMBB; 4023 4024 BuildMI(*BB, BB->begin(), DL, TII->get(Mips::PHI), MI.getOperand(0).getReg()) 4025 .addReg(MI.getOperand(2).getReg()) 4026 .addMBB(thisMBB) 4027 .addReg(MI.getOperand(3).getReg()) 4028 .addMBB(copy0MBB); 4029 4030 MI.eraseFromParent(); // The pseudo instruction is gone now. 4031 4032 return BB; 4033 } 4034 4035 // FIXME? Maybe this could be a TableGen attribute on some registers and 4036 // this table could be generated automatically from RegInfo. 4037 unsigned MipsTargetLowering::getRegisterByName(const char* RegName, EVT VT, 4038 SelectionDAG &DAG) const { 4039 // Named registers is expected to be fairly rare. For now, just support $28 4040 // since the linux kernel uses it. 4041 if (Subtarget.isGP64bit()) { 4042 unsigned Reg = StringSwitch<unsigned>(RegName) 4043 .Case("$28", Mips::GP_64) 4044 .Default(0); 4045 if (Reg) 4046 return Reg; 4047 } else { 4048 unsigned Reg = StringSwitch<unsigned>(RegName) 4049 .Case("$28", Mips::GP) 4050 .Default(0); 4051 if (Reg) 4052 return Reg; 4053 } 4054 report_fatal_error("Invalid register name global variable"); 4055 } 4056