1 //===- MipsISelLowering.cpp - Mips DAG Lowering Implementation ------------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file defines the interfaces that Mips uses to lower LLVM code into a 11 // selection DAG. 12 // 13 //===----------------------------------------------------------------------===// 14 15 #include "MipsISelLowering.h" 16 #include "InstPrinter/MipsInstPrinter.h" 17 #include "MCTargetDesc/MipsBaseInfo.h" 18 #include "MCTargetDesc/MipsMCTargetDesc.h" 19 #include "MipsCCState.h" 20 #include "MipsInstrInfo.h" 21 #include "MipsMachineFunction.h" 22 #include "MipsRegisterInfo.h" 23 #include "MipsSubtarget.h" 24 #include "MipsTargetMachine.h" 25 #include "MipsTargetObjectFile.h" 26 #include "llvm/ADT/APFloat.h" 27 #include "llvm/ADT/ArrayRef.h" 28 #include "llvm/ADT/SmallVector.h" 29 #include "llvm/ADT/Statistic.h" 30 #include "llvm/ADT/StringRef.h" 31 #include "llvm/ADT/StringSwitch.h" 32 #include "llvm/CodeGen/CallingConvLower.h" 33 #include "llvm/CodeGen/FunctionLoweringInfo.h" 34 #include "llvm/CodeGen/ISDOpcodes.h" 35 #include "llvm/CodeGen/MachineBasicBlock.h" 36 #include "llvm/CodeGen/MachineFrameInfo.h" 37 #include "llvm/CodeGen/MachineFunction.h" 38 #include "llvm/CodeGen/MachineInstr.h" 39 #include "llvm/CodeGen/MachineInstrBuilder.h" 40 #include "llvm/CodeGen/MachineJumpTableInfo.h" 41 #include "llvm/CodeGen/MachineMemOperand.h" 42 #include "llvm/CodeGen/MachineOperand.h" 43 #include "llvm/CodeGen/MachineRegisterInfo.h" 44 #include "llvm/CodeGen/RuntimeLibcalls.h" 45 #include "llvm/CodeGen/SelectionDAG.h" 46 #include "llvm/CodeGen/SelectionDAGNodes.h" 47 #include "llvm/CodeGen/TargetFrameLowering.h" 48 #include "llvm/CodeGen/TargetInstrInfo.h" 49 #include "llvm/CodeGen/TargetRegisterInfo.h" 50 #include "llvm/CodeGen/ValueTypes.h" 51 #include "llvm/IR/CallingConv.h" 52 #include "llvm/IR/Constants.h" 53 #include "llvm/IR/DataLayout.h" 54 #include "llvm/IR/DebugLoc.h" 55 #include "llvm/IR/DerivedTypes.h" 56 #include "llvm/IR/Function.h" 57 #include "llvm/IR/GlobalValue.h" 58 #include "llvm/IR/Type.h" 59 #include "llvm/IR/Value.h" 60 #include "llvm/MC/MCRegisterInfo.h" 61 #include "llvm/Support/Casting.h" 62 #include "llvm/Support/CodeGen.h" 63 #include "llvm/Support/CommandLine.h" 64 #include "llvm/Support/Compiler.h" 65 #include "llvm/Support/ErrorHandling.h" 66 #include "llvm/Support/MachineValueType.h" 67 #include "llvm/Support/MathExtras.h" 68 #include "llvm/Target/TargetMachine.h" 69 #include "llvm/Target/TargetOptions.h" 70 #include <algorithm> 71 #include <cassert> 72 #include <cctype> 73 #include <cstdint> 74 #include <deque> 75 #include <iterator> 76 #include <utility> 77 #include <vector> 78 79 using namespace llvm; 80 81 #define DEBUG_TYPE "mips-lower" 82 83 STATISTIC(NumTailCalls, "Number of tail calls"); 84 85 static cl::opt<bool> 86 LargeGOT("mxgot", cl::Hidden, 87 cl::desc("MIPS: Enable GOT larger than 64k."), cl::init(false)); 88 89 static cl::opt<bool> 90 NoZeroDivCheck("mno-check-zero-division", cl::Hidden, 91 cl::desc("MIPS: Don't trap on integer division by zero."), 92 cl::init(false)); 93 94 static const MCPhysReg Mips64DPRegs[8] = { 95 Mips::D12_64, Mips::D13_64, Mips::D14_64, Mips::D15_64, 96 Mips::D16_64, Mips::D17_64, Mips::D18_64, Mips::D19_64 97 }; 98 99 // If I is a shifted mask, set the size (Size) and the first bit of the 100 // mask (Pos), and return true. 101 // For example, if I is 0x003ff800, (Pos, Size) = (11, 11). 102 static bool isShiftedMask(uint64_t I, uint64_t &Pos, uint64_t &Size) { 103 if (!isShiftedMask_64(I)) 104 return false; 105 106 Size = countPopulation(I); 107 Pos = countTrailingZeros(I); 108 return true; 109 } 110 111 // The MIPS MSA ABI passes vector arguments in the integer register set. 112 // The number of integer registers used is dependant on the ABI used. 113 MVT MipsTargetLowering::getRegisterTypeForCallingConv(LLVMContext &Context, 114 CallingConv::ID CC, 115 EVT VT) const { 116 if (VT.isVector()) { 117 if (Subtarget.isABI_O32()) { 118 return MVT::i32; 119 } else { 120 return (VT.getSizeInBits() == 32) ? MVT::i32 : MVT::i64; 121 } 122 } 123 return MipsTargetLowering::getRegisterType(Context, VT); 124 } 125 126 unsigned MipsTargetLowering::getNumRegistersForCallingConv(LLVMContext &Context, 127 CallingConv::ID CC, 128 EVT VT) const { 129 if (VT.isVector()) 130 return std::max((VT.getSizeInBits() / (Subtarget.isABI_O32() ? 32 : 64)), 131 1U); 132 return MipsTargetLowering::getNumRegisters(Context, VT); 133 } 134 135 unsigned MipsTargetLowering::getVectorTypeBreakdownForCallingConv( 136 LLVMContext &Context, CallingConv::ID CC, EVT VT, EVT &IntermediateVT, 137 unsigned &NumIntermediates, MVT &RegisterVT) const { 138 // Break down vector types to either 2 i64s or 4 i32s. 139 RegisterVT = getRegisterTypeForCallingConv(Context, CC, VT); 140 IntermediateVT = RegisterVT; 141 NumIntermediates = VT.getSizeInBits() < RegisterVT.getSizeInBits() 142 ? VT.getVectorNumElements() 143 : VT.getSizeInBits() / RegisterVT.getSizeInBits(); 144 145 return NumIntermediates; 146 } 147 148 SDValue MipsTargetLowering::getGlobalReg(SelectionDAG &DAG, EVT Ty) const { 149 MipsFunctionInfo *FI = DAG.getMachineFunction().getInfo<MipsFunctionInfo>(); 150 return DAG.getRegister(FI->getGlobalBaseReg(), Ty); 151 } 152 153 SDValue MipsTargetLowering::getTargetNode(GlobalAddressSDNode *N, EVT Ty, 154 SelectionDAG &DAG, 155 unsigned Flag) const { 156 return DAG.getTargetGlobalAddress(N->getGlobal(), SDLoc(N), Ty, 0, Flag); 157 } 158 159 SDValue MipsTargetLowering::getTargetNode(ExternalSymbolSDNode *N, EVT Ty, 160 SelectionDAG &DAG, 161 unsigned Flag) const { 162 return DAG.getTargetExternalSymbol(N->getSymbol(), Ty, Flag); 163 } 164 165 SDValue MipsTargetLowering::getTargetNode(BlockAddressSDNode *N, EVT Ty, 166 SelectionDAG &DAG, 167 unsigned Flag) const { 168 return DAG.getTargetBlockAddress(N->getBlockAddress(), Ty, 0, Flag); 169 } 170 171 SDValue MipsTargetLowering::getTargetNode(JumpTableSDNode *N, EVT Ty, 172 SelectionDAG &DAG, 173 unsigned Flag) const { 174 return DAG.getTargetJumpTable(N->getIndex(), Ty, Flag); 175 } 176 177 SDValue MipsTargetLowering::getTargetNode(ConstantPoolSDNode *N, EVT Ty, 178 SelectionDAG &DAG, 179 unsigned Flag) const { 180 return DAG.getTargetConstantPool(N->getConstVal(), Ty, N->getAlignment(), 181 N->getOffset(), Flag); 182 } 183 184 const char *MipsTargetLowering::getTargetNodeName(unsigned Opcode) const { 185 switch ((MipsISD::NodeType)Opcode) { 186 case MipsISD::FIRST_NUMBER: break; 187 case MipsISD::JmpLink: return "MipsISD::JmpLink"; 188 case MipsISD::TailCall: return "MipsISD::TailCall"; 189 case MipsISD::Highest: return "MipsISD::Highest"; 190 case MipsISD::Higher: return "MipsISD::Higher"; 191 case MipsISD::Hi: return "MipsISD::Hi"; 192 case MipsISD::Lo: return "MipsISD::Lo"; 193 case MipsISD::GotHi: return "MipsISD::GotHi"; 194 case MipsISD::TlsHi: return "MipsISD::TlsHi"; 195 case MipsISD::GPRel: return "MipsISD::GPRel"; 196 case MipsISD::ThreadPointer: return "MipsISD::ThreadPointer"; 197 case MipsISD::Ret: return "MipsISD::Ret"; 198 case MipsISD::ERet: return "MipsISD::ERet"; 199 case MipsISD::EH_RETURN: return "MipsISD::EH_RETURN"; 200 case MipsISD::FMS: return "MipsISD::FMS"; 201 case MipsISD::FPBrcond: return "MipsISD::FPBrcond"; 202 case MipsISD::FPCmp: return "MipsISD::FPCmp"; 203 case MipsISD::FSELECT: return "MipsISD::FSELECT"; 204 case MipsISD::MTC1_D64: return "MipsISD::MTC1_D64"; 205 case MipsISD::CMovFP_T: return "MipsISD::CMovFP_T"; 206 case MipsISD::CMovFP_F: return "MipsISD::CMovFP_F"; 207 case MipsISD::TruncIntFP: return "MipsISD::TruncIntFP"; 208 case MipsISD::MFHI: return "MipsISD::MFHI"; 209 case MipsISD::MFLO: return "MipsISD::MFLO"; 210 case MipsISD::MTLOHI: return "MipsISD::MTLOHI"; 211 case MipsISD::Mult: return "MipsISD::Mult"; 212 case MipsISD::Multu: return "MipsISD::Multu"; 213 case MipsISD::MAdd: return "MipsISD::MAdd"; 214 case MipsISD::MAddu: return "MipsISD::MAddu"; 215 case MipsISD::MSub: return "MipsISD::MSub"; 216 case MipsISD::MSubu: return "MipsISD::MSubu"; 217 case MipsISD::DivRem: return "MipsISD::DivRem"; 218 case MipsISD::DivRemU: return "MipsISD::DivRemU"; 219 case MipsISD::DivRem16: return "MipsISD::DivRem16"; 220 case MipsISD::DivRemU16: return "MipsISD::DivRemU16"; 221 case MipsISD::BuildPairF64: return "MipsISD::BuildPairF64"; 222 case MipsISD::ExtractElementF64: return "MipsISD::ExtractElementF64"; 223 case MipsISD::Wrapper: return "MipsISD::Wrapper"; 224 case MipsISD::DynAlloc: return "MipsISD::DynAlloc"; 225 case MipsISD::Sync: return "MipsISD::Sync"; 226 case MipsISD::Ext: return "MipsISD::Ext"; 227 case MipsISD::Ins: return "MipsISD::Ins"; 228 case MipsISD::CIns: return "MipsISD::CIns"; 229 case MipsISD::LWL: return "MipsISD::LWL"; 230 case MipsISD::LWR: return "MipsISD::LWR"; 231 case MipsISD::SWL: return "MipsISD::SWL"; 232 case MipsISD::SWR: return "MipsISD::SWR"; 233 case MipsISD::LDL: return "MipsISD::LDL"; 234 case MipsISD::LDR: return "MipsISD::LDR"; 235 case MipsISD::SDL: return "MipsISD::SDL"; 236 case MipsISD::SDR: return "MipsISD::SDR"; 237 case MipsISD::EXTP: return "MipsISD::EXTP"; 238 case MipsISD::EXTPDP: return "MipsISD::EXTPDP"; 239 case MipsISD::EXTR_S_H: return "MipsISD::EXTR_S_H"; 240 case MipsISD::EXTR_W: return "MipsISD::EXTR_W"; 241 case MipsISD::EXTR_R_W: return "MipsISD::EXTR_R_W"; 242 case MipsISD::EXTR_RS_W: return "MipsISD::EXTR_RS_W"; 243 case MipsISD::SHILO: return "MipsISD::SHILO"; 244 case MipsISD::MTHLIP: return "MipsISD::MTHLIP"; 245 case MipsISD::MULSAQ_S_W_PH: return "MipsISD::MULSAQ_S_W_PH"; 246 case MipsISD::MAQ_S_W_PHL: return "MipsISD::MAQ_S_W_PHL"; 247 case MipsISD::MAQ_S_W_PHR: return "MipsISD::MAQ_S_W_PHR"; 248 case MipsISD::MAQ_SA_W_PHL: return "MipsISD::MAQ_SA_W_PHL"; 249 case MipsISD::MAQ_SA_W_PHR: return "MipsISD::MAQ_SA_W_PHR"; 250 case MipsISD::DPAU_H_QBL: return "MipsISD::DPAU_H_QBL"; 251 case MipsISD::DPAU_H_QBR: return "MipsISD::DPAU_H_QBR"; 252 case MipsISD::DPSU_H_QBL: return "MipsISD::DPSU_H_QBL"; 253 case MipsISD::DPSU_H_QBR: return "MipsISD::DPSU_H_QBR"; 254 case MipsISD::DPAQ_S_W_PH: return "MipsISD::DPAQ_S_W_PH"; 255 case MipsISD::DPSQ_S_W_PH: return "MipsISD::DPSQ_S_W_PH"; 256 case MipsISD::DPAQ_SA_L_W: return "MipsISD::DPAQ_SA_L_W"; 257 case MipsISD::DPSQ_SA_L_W: return "MipsISD::DPSQ_SA_L_W"; 258 case MipsISD::DPA_W_PH: return "MipsISD::DPA_W_PH"; 259 case MipsISD::DPS_W_PH: return "MipsISD::DPS_W_PH"; 260 case MipsISD::DPAQX_S_W_PH: return "MipsISD::DPAQX_S_W_PH"; 261 case MipsISD::DPAQX_SA_W_PH: return "MipsISD::DPAQX_SA_W_PH"; 262 case MipsISD::DPAX_W_PH: return "MipsISD::DPAX_W_PH"; 263 case MipsISD::DPSX_W_PH: return "MipsISD::DPSX_W_PH"; 264 case MipsISD::DPSQX_S_W_PH: return "MipsISD::DPSQX_S_W_PH"; 265 case MipsISD::DPSQX_SA_W_PH: return "MipsISD::DPSQX_SA_W_PH"; 266 case MipsISD::MULSA_W_PH: return "MipsISD::MULSA_W_PH"; 267 case MipsISD::MULT: return "MipsISD::MULT"; 268 case MipsISD::MULTU: return "MipsISD::MULTU"; 269 case MipsISD::MADD_DSP: return "MipsISD::MADD_DSP"; 270 case MipsISD::MADDU_DSP: return "MipsISD::MADDU_DSP"; 271 case MipsISD::MSUB_DSP: return "MipsISD::MSUB_DSP"; 272 case MipsISD::MSUBU_DSP: return "MipsISD::MSUBU_DSP"; 273 case MipsISD::SHLL_DSP: return "MipsISD::SHLL_DSP"; 274 case MipsISD::SHRA_DSP: return "MipsISD::SHRA_DSP"; 275 case MipsISD::SHRL_DSP: return "MipsISD::SHRL_DSP"; 276 case MipsISD::SETCC_DSP: return "MipsISD::SETCC_DSP"; 277 case MipsISD::SELECT_CC_DSP: return "MipsISD::SELECT_CC_DSP"; 278 case MipsISD::VALL_ZERO: return "MipsISD::VALL_ZERO"; 279 case MipsISD::VANY_ZERO: return "MipsISD::VANY_ZERO"; 280 case MipsISD::VALL_NONZERO: return "MipsISD::VALL_NONZERO"; 281 case MipsISD::VANY_NONZERO: return "MipsISD::VANY_NONZERO"; 282 case MipsISD::VCEQ: return "MipsISD::VCEQ"; 283 case MipsISD::VCLE_S: return "MipsISD::VCLE_S"; 284 case MipsISD::VCLE_U: return "MipsISD::VCLE_U"; 285 case MipsISD::VCLT_S: return "MipsISD::VCLT_S"; 286 case MipsISD::VCLT_U: return "MipsISD::VCLT_U"; 287 case MipsISD::VEXTRACT_SEXT_ELT: return "MipsISD::VEXTRACT_SEXT_ELT"; 288 case MipsISD::VEXTRACT_ZEXT_ELT: return "MipsISD::VEXTRACT_ZEXT_ELT"; 289 case MipsISD::VNOR: return "MipsISD::VNOR"; 290 case MipsISD::VSHF: return "MipsISD::VSHF"; 291 case MipsISD::SHF: return "MipsISD::SHF"; 292 case MipsISD::ILVEV: return "MipsISD::ILVEV"; 293 case MipsISD::ILVOD: return "MipsISD::ILVOD"; 294 case MipsISD::ILVL: return "MipsISD::ILVL"; 295 case MipsISD::ILVR: return "MipsISD::ILVR"; 296 case MipsISD::PCKEV: return "MipsISD::PCKEV"; 297 case MipsISD::PCKOD: return "MipsISD::PCKOD"; 298 case MipsISD::INSVE: return "MipsISD::INSVE"; 299 } 300 return nullptr; 301 } 302 303 MipsTargetLowering::MipsTargetLowering(const MipsTargetMachine &TM, 304 const MipsSubtarget &STI) 305 : TargetLowering(TM), Subtarget(STI), ABI(TM.getABI()) { 306 // Mips does not have i1 type, so use i32 for 307 // setcc operations results (slt, sgt, ...). 308 setBooleanContents(ZeroOrOneBooleanContent); 309 setBooleanVectorContents(ZeroOrNegativeOneBooleanContent); 310 // The cmp.cond.fmt instruction in MIPS32r6/MIPS64r6 uses 0 and -1 like MSA 311 // does. Integer booleans still use 0 and 1. 312 if (Subtarget.hasMips32r6()) 313 setBooleanContents(ZeroOrOneBooleanContent, 314 ZeroOrNegativeOneBooleanContent); 315 316 // Load extented operations for i1 types must be promoted 317 for (MVT VT : MVT::integer_valuetypes()) { 318 setLoadExtAction(ISD::EXTLOAD, VT, MVT::i1, Promote); 319 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i1, Promote); 320 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i1, Promote); 321 } 322 323 // MIPS doesn't have extending float->double load/store. Set LoadExtAction 324 // for f32, f16 325 for (MVT VT : MVT::fp_valuetypes()) { 326 setLoadExtAction(ISD::EXTLOAD, VT, MVT::f32, Expand); 327 setLoadExtAction(ISD::EXTLOAD, VT, MVT::f16, Expand); 328 } 329 330 // Set LoadExtAction for f16 vectors to Expand 331 for (MVT VT : MVT::fp_vector_valuetypes()) { 332 MVT F16VT = MVT::getVectorVT(MVT::f16, VT.getVectorNumElements()); 333 if (F16VT.isValid()) 334 setLoadExtAction(ISD::EXTLOAD, VT, F16VT, Expand); 335 } 336 337 setTruncStoreAction(MVT::f32, MVT::f16, Expand); 338 setTruncStoreAction(MVT::f64, MVT::f16, Expand); 339 340 setTruncStoreAction(MVT::f64, MVT::f32, Expand); 341 342 // Used by legalize types to correctly generate the setcc result. 343 // Without this, every float setcc comes with a AND/OR with the result, 344 // we don't want this, since the fpcmp result goes to a flag register, 345 // which is used implicitly by brcond and select operations. 346 AddPromotedToType(ISD::SETCC, MVT::i1, MVT::i32); 347 348 // Mips Custom Operations 349 setOperationAction(ISD::BR_JT, MVT::Other, Expand); 350 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom); 351 setOperationAction(ISD::BlockAddress, MVT::i32, Custom); 352 setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom); 353 setOperationAction(ISD::JumpTable, MVT::i32, Custom); 354 setOperationAction(ISD::ConstantPool, MVT::i32, Custom); 355 setOperationAction(ISD::SELECT, MVT::f32, Custom); 356 setOperationAction(ISD::SELECT, MVT::f64, Custom); 357 setOperationAction(ISD::SELECT, MVT::i32, Custom); 358 setOperationAction(ISD::SETCC, MVT::f32, Custom); 359 setOperationAction(ISD::SETCC, MVT::f64, Custom); 360 setOperationAction(ISD::BRCOND, MVT::Other, Custom); 361 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom); 362 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom); 363 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom); 364 365 if (Subtarget.isGP64bit()) { 366 setOperationAction(ISD::GlobalAddress, MVT::i64, Custom); 367 setOperationAction(ISD::BlockAddress, MVT::i64, Custom); 368 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom); 369 setOperationAction(ISD::JumpTable, MVT::i64, Custom); 370 setOperationAction(ISD::ConstantPool, MVT::i64, Custom); 371 setOperationAction(ISD::SELECT, MVT::i64, Custom); 372 setOperationAction(ISD::LOAD, MVT::i64, Custom); 373 setOperationAction(ISD::STORE, MVT::i64, Custom); 374 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom); 375 setOperationAction(ISD::SHL_PARTS, MVT::i64, Custom); 376 setOperationAction(ISD::SRA_PARTS, MVT::i64, Custom); 377 setOperationAction(ISD::SRL_PARTS, MVT::i64, Custom); 378 } 379 380 if (!Subtarget.isGP64bit()) { 381 setOperationAction(ISD::SHL_PARTS, MVT::i32, Custom); 382 setOperationAction(ISD::SRA_PARTS, MVT::i32, Custom); 383 setOperationAction(ISD::SRL_PARTS, MVT::i32, Custom); 384 } 385 386 setOperationAction(ISD::EH_DWARF_CFA, MVT::i32, Custom); 387 if (Subtarget.isGP64bit()) 388 setOperationAction(ISD::EH_DWARF_CFA, MVT::i64, Custom); 389 390 setOperationAction(ISD::SDIV, MVT::i32, Expand); 391 setOperationAction(ISD::SREM, MVT::i32, Expand); 392 setOperationAction(ISD::UDIV, MVT::i32, Expand); 393 setOperationAction(ISD::UREM, MVT::i32, Expand); 394 setOperationAction(ISD::SDIV, MVT::i64, Expand); 395 setOperationAction(ISD::SREM, MVT::i64, Expand); 396 setOperationAction(ISD::UDIV, MVT::i64, Expand); 397 setOperationAction(ISD::UREM, MVT::i64, Expand); 398 399 // Operations not directly supported by Mips. 400 setOperationAction(ISD::BR_CC, MVT::f32, Expand); 401 setOperationAction(ISD::BR_CC, MVT::f64, Expand); 402 setOperationAction(ISD::BR_CC, MVT::i32, Expand); 403 setOperationAction(ISD::BR_CC, MVT::i64, Expand); 404 setOperationAction(ISD::SELECT_CC, MVT::i32, Expand); 405 setOperationAction(ISD::SELECT_CC, MVT::i64, Expand); 406 setOperationAction(ISD::SELECT_CC, MVT::f32, Expand); 407 setOperationAction(ISD::SELECT_CC, MVT::f64, Expand); 408 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand); 409 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Expand); 410 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand); 411 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Expand); 412 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand); 413 if (Subtarget.hasCnMips()) { 414 setOperationAction(ISD::CTPOP, MVT::i32, Legal); 415 setOperationAction(ISD::CTPOP, MVT::i64, Legal); 416 } else { 417 setOperationAction(ISD::CTPOP, MVT::i32, Expand); 418 setOperationAction(ISD::CTPOP, MVT::i64, Expand); 419 } 420 setOperationAction(ISD::CTTZ, MVT::i32, Expand); 421 setOperationAction(ISD::CTTZ, MVT::i64, Expand); 422 setOperationAction(ISD::ROTL, MVT::i32, Expand); 423 setOperationAction(ISD::ROTL, MVT::i64, Expand); 424 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Expand); 425 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64, Expand); 426 427 if (!Subtarget.hasMips32r2()) 428 setOperationAction(ISD::ROTR, MVT::i32, Expand); 429 430 if (!Subtarget.hasMips64r2()) 431 setOperationAction(ISD::ROTR, MVT::i64, Expand); 432 433 setOperationAction(ISD::FSIN, MVT::f32, Expand); 434 setOperationAction(ISD::FSIN, MVT::f64, Expand); 435 setOperationAction(ISD::FCOS, MVT::f32, Expand); 436 setOperationAction(ISD::FCOS, MVT::f64, Expand); 437 setOperationAction(ISD::FSINCOS, MVT::f32, Expand); 438 setOperationAction(ISD::FSINCOS, MVT::f64, Expand); 439 setOperationAction(ISD::FPOW, MVT::f32, Expand); 440 setOperationAction(ISD::FPOW, MVT::f64, Expand); 441 setOperationAction(ISD::FLOG, MVT::f32, Expand); 442 setOperationAction(ISD::FLOG2, MVT::f32, Expand); 443 setOperationAction(ISD::FLOG10, MVT::f32, Expand); 444 setOperationAction(ISD::FEXP, MVT::f32, Expand); 445 setOperationAction(ISD::FMA, MVT::f32, Expand); 446 setOperationAction(ISD::FMA, MVT::f64, Expand); 447 setOperationAction(ISD::FREM, MVT::f32, Expand); 448 setOperationAction(ISD::FREM, MVT::f64, Expand); 449 450 // Lower f16 conversion operations into library calls 451 setOperationAction(ISD::FP16_TO_FP, MVT::f32, Expand); 452 setOperationAction(ISD::FP_TO_FP16, MVT::f32, Expand); 453 setOperationAction(ISD::FP16_TO_FP, MVT::f64, Expand); 454 setOperationAction(ISD::FP_TO_FP16, MVT::f64, Expand); 455 456 setOperationAction(ISD::EH_RETURN, MVT::Other, Custom); 457 458 setOperationAction(ISD::VASTART, MVT::Other, Custom); 459 setOperationAction(ISD::VAARG, MVT::Other, Custom); 460 setOperationAction(ISD::VACOPY, MVT::Other, Expand); 461 setOperationAction(ISD::VAEND, MVT::Other, Expand); 462 463 // Use the default for now 464 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand); 465 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand); 466 467 if (!Subtarget.isGP64bit()) { 468 setOperationAction(ISD::ATOMIC_LOAD, MVT::i64, Expand); 469 setOperationAction(ISD::ATOMIC_STORE, MVT::i64, Expand); 470 } 471 472 if (!Subtarget.hasMips32r2()) { 473 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8, Expand); 474 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand); 475 } 476 477 // MIPS16 lacks MIPS32's clz and clo instructions. 478 if (!Subtarget.hasMips32() || Subtarget.inMips16Mode()) 479 setOperationAction(ISD::CTLZ, MVT::i32, Expand); 480 if (!Subtarget.hasMips64()) 481 setOperationAction(ISD::CTLZ, MVT::i64, Expand); 482 483 if (!Subtarget.hasMips32r2()) 484 setOperationAction(ISD::BSWAP, MVT::i32, Expand); 485 if (!Subtarget.hasMips64r2()) 486 setOperationAction(ISD::BSWAP, MVT::i64, Expand); 487 488 if (Subtarget.isGP64bit()) { 489 setLoadExtAction(ISD::SEXTLOAD, MVT::i64, MVT::i32, Custom); 490 setLoadExtAction(ISD::ZEXTLOAD, MVT::i64, MVT::i32, Custom); 491 setLoadExtAction(ISD::EXTLOAD, MVT::i64, MVT::i32, Custom); 492 setTruncStoreAction(MVT::i64, MVT::i32, Custom); 493 } 494 495 setOperationAction(ISD::TRAP, MVT::Other, Legal); 496 497 setTargetDAGCombine(ISD::SDIVREM); 498 setTargetDAGCombine(ISD::UDIVREM); 499 setTargetDAGCombine(ISD::SELECT); 500 setTargetDAGCombine(ISD::AND); 501 setTargetDAGCombine(ISD::OR); 502 setTargetDAGCombine(ISD::ADD); 503 setTargetDAGCombine(ISD::SUB); 504 setTargetDAGCombine(ISD::AssertZext); 505 setTargetDAGCombine(ISD::SHL); 506 507 if (ABI.IsO32()) { 508 // These libcalls are not available in 32-bit. 509 setLibcallName(RTLIB::SHL_I128, nullptr); 510 setLibcallName(RTLIB::SRL_I128, nullptr); 511 setLibcallName(RTLIB::SRA_I128, nullptr); 512 } 513 514 setMinFunctionAlignment(Subtarget.isGP64bit() ? 3 : 2); 515 516 // The arguments on the stack are defined in terms of 4-byte slots on O32 517 // and 8-byte slots on N32/N64. 518 setMinStackArgumentAlignment((ABI.IsN32() || ABI.IsN64()) ? 8 : 4); 519 520 setStackPointerRegisterToSaveRestore(ABI.IsN64() ? Mips::SP_64 : Mips::SP); 521 522 MaxStoresPerMemcpy = 16; 523 524 isMicroMips = Subtarget.inMicroMipsMode(); 525 } 526 527 const MipsTargetLowering *MipsTargetLowering::create(const MipsTargetMachine &TM, 528 const MipsSubtarget &STI) { 529 if (STI.inMips16Mode()) 530 return createMips16TargetLowering(TM, STI); 531 532 return createMipsSETargetLowering(TM, STI); 533 } 534 535 // Create a fast isel object. 536 FastISel * 537 MipsTargetLowering::createFastISel(FunctionLoweringInfo &funcInfo, 538 const TargetLibraryInfo *libInfo) const { 539 const MipsTargetMachine &TM = 540 static_cast<const MipsTargetMachine &>(funcInfo.MF->getTarget()); 541 542 // We support only the standard encoding [MIPS32,MIPS32R5] ISAs. 543 bool UseFastISel = TM.Options.EnableFastISel && Subtarget.hasMips32() && 544 !Subtarget.hasMips32r6() && !Subtarget.inMips16Mode() && 545 !Subtarget.inMicroMipsMode(); 546 547 // Disable if either of the following is true: 548 // We do not generate PIC, the ABI is not O32, LargeGOT is being used. 549 if (!TM.isPositionIndependent() || !TM.getABI().IsO32() || LargeGOT) 550 UseFastISel = false; 551 552 return UseFastISel ? Mips::createFastISel(funcInfo, libInfo) : nullptr; 553 } 554 555 EVT MipsTargetLowering::getSetCCResultType(const DataLayout &, LLVMContext &, 556 EVT VT) const { 557 if (!VT.isVector()) 558 return MVT::i32; 559 return VT.changeVectorElementTypeToInteger(); 560 } 561 562 static SDValue performDivRemCombine(SDNode *N, SelectionDAG &DAG, 563 TargetLowering::DAGCombinerInfo &DCI, 564 const MipsSubtarget &Subtarget) { 565 if (DCI.isBeforeLegalizeOps()) 566 return SDValue(); 567 568 EVT Ty = N->getValueType(0); 569 unsigned LO = (Ty == MVT::i32) ? Mips::LO0 : Mips::LO0_64; 570 unsigned HI = (Ty == MVT::i32) ? Mips::HI0 : Mips::HI0_64; 571 unsigned Opc = N->getOpcode() == ISD::SDIVREM ? MipsISD::DivRem16 : 572 MipsISD::DivRemU16; 573 SDLoc DL(N); 574 575 SDValue DivRem = DAG.getNode(Opc, DL, MVT::Glue, 576 N->getOperand(0), N->getOperand(1)); 577 SDValue InChain = DAG.getEntryNode(); 578 SDValue InGlue = DivRem; 579 580 // insert MFLO 581 if (N->hasAnyUseOfValue(0)) { 582 SDValue CopyFromLo = DAG.getCopyFromReg(InChain, DL, LO, Ty, 583 InGlue); 584 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), CopyFromLo); 585 InChain = CopyFromLo.getValue(1); 586 InGlue = CopyFromLo.getValue(2); 587 } 588 589 // insert MFHI 590 if (N->hasAnyUseOfValue(1)) { 591 SDValue CopyFromHi = DAG.getCopyFromReg(InChain, DL, 592 HI, Ty, InGlue); 593 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), CopyFromHi); 594 } 595 596 return SDValue(); 597 } 598 599 static Mips::CondCode condCodeToFCC(ISD::CondCode CC) { 600 switch (CC) { 601 default: llvm_unreachable("Unknown fp condition code!"); 602 case ISD::SETEQ: 603 case ISD::SETOEQ: return Mips::FCOND_OEQ; 604 case ISD::SETUNE: return Mips::FCOND_UNE; 605 case ISD::SETLT: 606 case ISD::SETOLT: return Mips::FCOND_OLT; 607 case ISD::SETGT: 608 case ISD::SETOGT: return Mips::FCOND_OGT; 609 case ISD::SETLE: 610 case ISD::SETOLE: return Mips::FCOND_OLE; 611 case ISD::SETGE: 612 case ISD::SETOGE: return Mips::FCOND_OGE; 613 case ISD::SETULT: return Mips::FCOND_ULT; 614 case ISD::SETULE: return Mips::FCOND_ULE; 615 case ISD::SETUGT: return Mips::FCOND_UGT; 616 case ISD::SETUGE: return Mips::FCOND_UGE; 617 case ISD::SETUO: return Mips::FCOND_UN; 618 case ISD::SETO: return Mips::FCOND_OR; 619 case ISD::SETNE: 620 case ISD::SETONE: return Mips::FCOND_ONE; 621 case ISD::SETUEQ: return Mips::FCOND_UEQ; 622 } 623 } 624 625 /// This function returns true if the floating point conditional branches and 626 /// conditional moves which use condition code CC should be inverted. 627 static bool invertFPCondCodeUser(Mips::CondCode CC) { 628 if (CC >= Mips::FCOND_F && CC <= Mips::FCOND_NGT) 629 return false; 630 631 assert((CC >= Mips::FCOND_T && CC <= Mips::FCOND_GT) && 632 "Illegal Condition Code"); 633 634 return true; 635 } 636 637 // Creates and returns an FPCmp node from a setcc node. 638 // Returns Op if setcc is not a floating point comparison. 639 static SDValue createFPCmp(SelectionDAG &DAG, const SDValue &Op) { 640 // must be a SETCC node 641 if (Op.getOpcode() != ISD::SETCC) 642 return Op; 643 644 SDValue LHS = Op.getOperand(0); 645 646 if (!LHS.getValueType().isFloatingPoint()) 647 return Op; 648 649 SDValue RHS = Op.getOperand(1); 650 SDLoc DL(Op); 651 652 // Assume the 3rd operand is a CondCodeSDNode. Add code to check the type of 653 // node if necessary. 654 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get(); 655 656 return DAG.getNode(MipsISD::FPCmp, DL, MVT::Glue, LHS, RHS, 657 DAG.getConstant(condCodeToFCC(CC), DL, MVT::i32)); 658 } 659 660 // Creates and returns a CMovFPT/F node. 661 static SDValue createCMovFP(SelectionDAG &DAG, SDValue Cond, SDValue True, 662 SDValue False, const SDLoc &DL) { 663 ConstantSDNode *CC = cast<ConstantSDNode>(Cond.getOperand(2)); 664 bool invert = invertFPCondCodeUser((Mips::CondCode)CC->getSExtValue()); 665 SDValue FCC0 = DAG.getRegister(Mips::FCC0, MVT::i32); 666 667 return DAG.getNode((invert ? MipsISD::CMovFP_F : MipsISD::CMovFP_T), DL, 668 True.getValueType(), True, FCC0, False, Cond); 669 } 670 671 static SDValue performSELECTCombine(SDNode *N, SelectionDAG &DAG, 672 TargetLowering::DAGCombinerInfo &DCI, 673 const MipsSubtarget &Subtarget) { 674 if (DCI.isBeforeLegalizeOps()) 675 return SDValue(); 676 677 SDValue SetCC = N->getOperand(0); 678 679 if ((SetCC.getOpcode() != ISD::SETCC) || 680 !SetCC.getOperand(0).getValueType().isInteger()) 681 return SDValue(); 682 683 SDValue False = N->getOperand(2); 684 EVT FalseTy = False.getValueType(); 685 686 if (!FalseTy.isInteger()) 687 return SDValue(); 688 689 ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(False); 690 691 // If the RHS (False) is 0, we swap the order of the operands 692 // of ISD::SELECT (obviously also inverting the condition) so that we can 693 // take advantage of conditional moves using the $0 register. 694 // Example: 695 // return (a != 0) ? x : 0; 696 // load $reg, x 697 // movz $reg, $0, a 698 if (!FalseC) 699 return SDValue(); 700 701 const SDLoc DL(N); 702 703 if (!FalseC->getZExtValue()) { 704 ISD::CondCode CC = cast<CondCodeSDNode>(SetCC.getOperand(2))->get(); 705 SDValue True = N->getOperand(1); 706 707 SetCC = DAG.getSetCC(DL, SetCC.getValueType(), SetCC.getOperand(0), 708 SetCC.getOperand(1), ISD::getSetCCInverse(CC, true)); 709 710 return DAG.getNode(ISD::SELECT, DL, FalseTy, SetCC, False, True); 711 } 712 713 // If both operands are integer constants there's a possibility that we 714 // can do some interesting optimizations. 715 SDValue True = N->getOperand(1); 716 ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(True); 717 718 if (!TrueC || !True.getValueType().isInteger()) 719 return SDValue(); 720 721 // We'll also ignore MVT::i64 operands as this optimizations proves 722 // to be ineffective because of the required sign extensions as the result 723 // of a SETCC operator is always MVT::i32 for non-vector types. 724 if (True.getValueType() == MVT::i64) 725 return SDValue(); 726 727 int64_t Diff = TrueC->getSExtValue() - FalseC->getSExtValue(); 728 729 // 1) (a < x) ? y : y-1 730 // slti $reg1, a, x 731 // addiu $reg2, $reg1, y-1 732 if (Diff == 1) 733 return DAG.getNode(ISD::ADD, DL, SetCC.getValueType(), SetCC, False); 734 735 // 2) (a < x) ? y-1 : y 736 // slti $reg1, a, x 737 // xor $reg1, $reg1, 1 738 // addiu $reg2, $reg1, y-1 739 if (Diff == -1) { 740 ISD::CondCode CC = cast<CondCodeSDNode>(SetCC.getOperand(2))->get(); 741 SetCC = DAG.getSetCC(DL, SetCC.getValueType(), SetCC.getOperand(0), 742 SetCC.getOperand(1), ISD::getSetCCInverse(CC, true)); 743 return DAG.getNode(ISD::ADD, DL, SetCC.getValueType(), SetCC, True); 744 } 745 746 // Could not optimize. 747 return SDValue(); 748 } 749 750 static SDValue performCMovFPCombine(SDNode *N, SelectionDAG &DAG, 751 TargetLowering::DAGCombinerInfo &DCI, 752 const MipsSubtarget &Subtarget) { 753 if (DCI.isBeforeLegalizeOps()) 754 return SDValue(); 755 756 SDValue ValueIfTrue = N->getOperand(0), ValueIfFalse = N->getOperand(2); 757 758 ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(ValueIfFalse); 759 if (!FalseC || FalseC->getZExtValue()) 760 return SDValue(); 761 762 // Since RHS (False) is 0, we swap the order of the True/False operands 763 // (obviously also inverting the condition) so that we can 764 // take advantage of conditional moves using the $0 register. 765 // Example: 766 // return (a != 0) ? x : 0; 767 // load $reg, x 768 // movz $reg, $0, a 769 unsigned Opc = (N->getOpcode() == MipsISD::CMovFP_T) ? MipsISD::CMovFP_F : 770 MipsISD::CMovFP_T; 771 772 SDValue FCC = N->getOperand(1), Glue = N->getOperand(3); 773 return DAG.getNode(Opc, SDLoc(N), ValueIfFalse.getValueType(), 774 ValueIfFalse, FCC, ValueIfTrue, Glue); 775 } 776 777 static SDValue performANDCombine(SDNode *N, SelectionDAG &DAG, 778 TargetLowering::DAGCombinerInfo &DCI, 779 const MipsSubtarget &Subtarget) { 780 if (DCI.isBeforeLegalizeOps() || !Subtarget.hasExtractInsert()) 781 return SDValue(); 782 783 SDValue FirstOperand = N->getOperand(0); 784 unsigned FirstOperandOpc = FirstOperand.getOpcode(); 785 SDValue Mask = N->getOperand(1); 786 EVT ValTy = N->getValueType(0); 787 SDLoc DL(N); 788 789 uint64_t Pos = 0, SMPos, SMSize; 790 ConstantSDNode *CN; 791 SDValue NewOperand; 792 unsigned Opc; 793 794 // Op's second operand must be a shifted mask. 795 if (!(CN = dyn_cast<ConstantSDNode>(Mask)) || 796 !isShiftedMask(CN->getZExtValue(), SMPos, SMSize)) 797 return SDValue(); 798 799 if (FirstOperandOpc == ISD::SRA || FirstOperandOpc == ISD::SRL) { 800 // Pattern match EXT. 801 // $dst = and ((sra or srl) $src , pos), (2**size - 1) 802 // => ext $dst, $src, pos, size 803 804 // The second operand of the shift must be an immediate. 805 if (!(CN = dyn_cast<ConstantSDNode>(FirstOperand.getOperand(1)))) 806 return SDValue(); 807 808 Pos = CN->getZExtValue(); 809 810 // Return if the shifted mask does not start at bit 0 or the sum of its size 811 // and Pos exceeds the word's size. 812 if (SMPos != 0 || Pos + SMSize > ValTy.getSizeInBits()) 813 return SDValue(); 814 815 Opc = MipsISD::Ext; 816 NewOperand = FirstOperand.getOperand(0); 817 } else if (FirstOperandOpc == ISD::SHL && Subtarget.hasCnMips()) { 818 // Pattern match CINS. 819 // $dst = and (shl $src , pos), mask 820 // => cins $dst, $src, pos, size 821 // mask is a shifted mask with consecutive 1's, pos = shift amount, 822 // size = population count. 823 824 // The second operand of the shift must be an immediate. 825 if (!(CN = dyn_cast<ConstantSDNode>(FirstOperand.getOperand(1)))) 826 return SDValue(); 827 828 Pos = CN->getZExtValue(); 829 830 if (SMPos != Pos || Pos >= ValTy.getSizeInBits() || SMSize >= 32 || 831 Pos + SMSize > ValTy.getSizeInBits()) 832 return SDValue(); 833 834 NewOperand = FirstOperand.getOperand(0); 835 // SMSize is 'location' (position) in this case, not size. 836 SMSize--; 837 Opc = MipsISD::CIns; 838 } else { 839 // Pattern match EXT. 840 // $dst = and $src, (2**size - 1) , if size > 16 841 // => ext $dst, $src, pos, size , pos = 0 842 843 // If the mask is <= 0xffff, andi can be used instead. 844 if (CN->getZExtValue() <= 0xffff) 845 return SDValue(); 846 847 // Return if the mask doesn't start at position 0. 848 if (SMPos) 849 return SDValue(); 850 851 Opc = MipsISD::Ext; 852 NewOperand = FirstOperand; 853 } 854 return DAG.getNode(Opc, DL, ValTy, NewOperand, 855 DAG.getConstant(Pos, DL, MVT::i32), 856 DAG.getConstant(SMSize, DL, MVT::i32)); 857 } 858 859 static SDValue performORCombine(SDNode *N, SelectionDAG &DAG, 860 TargetLowering::DAGCombinerInfo &DCI, 861 const MipsSubtarget &Subtarget) { 862 // Pattern match INS. 863 // $dst = or (and $src1 , mask0), (and (shl $src, pos), mask1), 864 // where mask1 = (2**size - 1) << pos, mask0 = ~mask1 865 // => ins $dst, $src, size, pos, $src1 866 if (DCI.isBeforeLegalizeOps() || !Subtarget.hasExtractInsert()) 867 return SDValue(); 868 869 SDValue And0 = N->getOperand(0), And1 = N->getOperand(1); 870 uint64_t SMPos0, SMSize0, SMPos1, SMSize1; 871 ConstantSDNode *CN, *CN1; 872 873 // See if Op's first operand matches (and $src1 , mask0). 874 if (And0.getOpcode() != ISD::AND) 875 return SDValue(); 876 877 if (!(CN = dyn_cast<ConstantSDNode>(And0.getOperand(1))) || 878 !isShiftedMask(~CN->getSExtValue(), SMPos0, SMSize0)) 879 return SDValue(); 880 881 // See if Op's second operand matches (and (shl $src, pos), mask1). 882 if (And1.getOpcode() == ISD::AND && 883 And1.getOperand(0).getOpcode() == ISD::SHL) { 884 885 if (!(CN = dyn_cast<ConstantSDNode>(And1.getOperand(1))) || 886 !isShiftedMask(CN->getZExtValue(), SMPos1, SMSize1)) 887 return SDValue(); 888 889 // The shift masks must have the same position and size. 890 if (SMPos0 != SMPos1 || SMSize0 != SMSize1) 891 return SDValue(); 892 893 SDValue Shl = And1.getOperand(0); 894 895 if (!(CN = dyn_cast<ConstantSDNode>(Shl.getOperand(1)))) 896 return SDValue(); 897 898 unsigned Shamt = CN->getZExtValue(); 899 900 // Return if the shift amount and the first bit position of mask are not the 901 // same. 902 EVT ValTy = N->getValueType(0); 903 if ((Shamt != SMPos0) || (SMPos0 + SMSize0 > ValTy.getSizeInBits())) 904 return SDValue(); 905 906 SDLoc DL(N); 907 return DAG.getNode(MipsISD::Ins, DL, ValTy, Shl.getOperand(0), 908 DAG.getConstant(SMPos0, DL, MVT::i32), 909 DAG.getConstant(SMSize0, DL, MVT::i32), 910 And0.getOperand(0)); 911 } else { 912 // Pattern match DINS. 913 // $dst = or (and $src, mask0), mask1 914 // where mask0 = ((1 << SMSize0) -1) << SMPos0 915 // => dins $dst, $src, pos, size 916 if (~CN->getSExtValue() == ((((int64_t)1 << SMSize0) - 1) << SMPos0) && 917 ((SMSize0 + SMPos0 <= 64 && Subtarget.hasMips64r2()) || 918 (SMSize0 + SMPos0 <= 32))) { 919 // Check if AND instruction has constant as argument 920 bool isConstCase = And1.getOpcode() != ISD::AND; 921 if (And1.getOpcode() == ISD::AND) { 922 if (!(CN1 = dyn_cast<ConstantSDNode>(And1->getOperand(1)))) 923 return SDValue(); 924 } else { 925 if (!(CN1 = dyn_cast<ConstantSDNode>(N->getOperand(1)))) 926 return SDValue(); 927 } 928 // Don't generate INS if constant OR operand doesn't fit into bits 929 // cleared by constant AND operand. 930 if (CN->getSExtValue() & CN1->getSExtValue()) 931 return SDValue(); 932 933 SDLoc DL(N); 934 EVT ValTy = N->getOperand(0)->getValueType(0); 935 SDValue Const1; 936 SDValue SrlX; 937 if (!isConstCase) { 938 Const1 = DAG.getConstant(SMPos0, DL, MVT::i32); 939 SrlX = DAG.getNode(ISD::SRL, DL, And1->getValueType(0), And1, Const1); 940 } 941 return DAG.getNode( 942 MipsISD::Ins, DL, N->getValueType(0), 943 isConstCase 944 ? DAG.getConstant(CN1->getSExtValue() >> SMPos0, DL, ValTy) 945 : SrlX, 946 DAG.getConstant(SMPos0, DL, MVT::i32), 947 DAG.getConstant(ValTy.getSizeInBits() / 8 < 8 ? SMSize0 & 31 948 : SMSize0, 949 DL, MVT::i32), 950 And0->getOperand(0)); 951 952 } 953 return SDValue(); 954 } 955 } 956 957 static SDValue performMADD_MSUBCombine(SDNode *ROOTNode, SelectionDAG &CurDAG, 958 const MipsSubtarget &Subtarget) { 959 // ROOTNode must have a multiplication as an operand for the match to be 960 // successful. 961 if (ROOTNode->getOperand(0).getOpcode() != ISD::MUL && 962 ROOTNode->getOperand(1).getOpcode() != ISD::MUL) 963 return SDValue(); 964 965 // We don't handle vector types here. 966 if (ROOTNode->getValueType(0).isVector()) 967 return SDValue(); 968 969 // For MIPS64, madd / msub instructions are inefficent to use with 64 bit 970 // arithmetic. E.g. 971 // (add (mul a b) c) => 972 // let res = (madd (mthi (drotr c 32))x(mtlo c) a b) in 973 // MIPS64: (or (dsll (mfhi res) 32) (dsrl (dsll (mflo res) 32) 32) 974 // or 975 // MIPS64R2: (dins (mflo res) (mfhi res) 32 32) 976 // 977 // The overhead of setting up the Hi/Lo registers and reassembling the 978 // result makes this a dubious optimzation for MIPS64. The core of the 979 // problem is that Hi/Lo contain the upper and lower 32 bits of the 980 // operand and result. 981 // 982 // It requires a chain of 4 add/mul for MIPS64R2 to get better code 983 // density than doing it naively, 5 for MIPS64. Additionally, using 984 // madd/msub on MIPS64 requires the operands actually be 32 bit sign 985 // extended operands, not true 64 bit values. 986 // 987 // FIXME: For the moment, disable this completely for MIPS64. 988 if (Subtarget.hasMips64()) 989 return SDValue(); 990 991 SDValue Mult = ROOTNode->getOperand(0).getOpcode() == ISD::MUL 992 ? ROOTNode->getOperand(0) 993 : ROOTNode->getOperand(1); 994 995 SDValue AddOperand = ROOTNode->getOperand(0).getOpcode() == ISD::MUL 996 ? ROOTNode->getOperand(1) 997 : ROOTNode->getOperand(0); 998 999 // Transform this to a MADD only if the user of this node is the add. 1000 // If there are other users of the mul, this function returns here. 1001 if (!Mult.hasOneUse()) 1002 return SDValue(); 1003 1004 // maddu and madd are unusual instructions in that on MIPS64 bits 63..31 1005 // must be in canonical form, i.e. sign extended. For MIPS32, the operands 1006 // of the multiply must have 32 or more sign bits, otherwise we cannot 1007 // perform this optimization. We have to check this here as we're performing 1008 // this optimization pre-legalization. 1009 SDValue MultLHS = Mult->getOperand(0); 1010 SDValue MultRHS = Mult->getOperand(1); 1011 1012 bool IsSigned = MultLHS->getOpcode() == ISD::SIGN_EXTEND && 1013 MultRHS->getOpcode() == ISD::SIGN_EXTEND; 1014 bool IsUnsigned = MultLHS->getOpcode() == ISD::ZERO_EXTEND && 1015 MultRHS->getOpcode() == ISD::ZERO_EXTEND; 1016 1017 if (!IsSigned && !IsUnsigned) 1018 return SDValue(); 1019 1020 // Initialize accumulator. 1021 SDLoc DL(ROOTNode); 1022 SDValue TopHalf; 1023 SDValue BottomHalf; 1024 BottomHalf = CurDAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32, AddOperand, 1025 CurDAG.getIntPtrConstant(0, DL)); 1026 1027 TopHalf = CurDAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32, AddOperand, 1028 CurDAG.getIntPtrConstant(1, DL)); 1029 SDValue ACCIn = CurDAG.getNode(MipsISD::MTLOHI, DL, MVT::Untyped, 1030 BottomHalf, 1031 TopHalf); 1032 1033 // Create MipsMAdd(u) / MipsMSub(u) node. 1034 bool IsAdd = ROOTNode->getOpcode() == ISD::ADD; 1035 unsigned Opcode = IsAdd ? (IsUnsigned ? MipsISD::MAddu : MipsISD::MAdd) 1036 : (IsUnsigned ? MipsISD::MSubu : MipsISD::MSub); 1037 SDValue MAddOps[3] = { 1038 CurDAG.getNode(ISD::TRUNCATE, DL, MVT::i32, Mult->getOperand(0)), 1039 CurDAG.getNode(ISD::TRUNCATE, DL, MVT::i32, Mult->getOperand(1)), ACCIn}; 1040 EVT VTs[2] = {MVT::i32, MVT::i32}; 1041 SDValue MAdd = CurDAG.getNode(Opcode, DL, VTs, MAddOps); 1042 1043 SDValue ResLo = CurDAG.getNode(MipsISD::MFLO, DL, MVT::i32, MAdd); 1044 SDValue ResHi = CurDAG.getNode(MipsISD::MFHI, DL, MVT::i32, MAdd); 1045 SDValue Combined = 1046 CurDAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, ResLo, ResHi); 1047 return Combined; 1048 } 1049 1050 static SDValue performSUBCombine(SDNode *N, SelectionDAG &DAG, 1051 TargetLowering::DAGCombinerInfo &DCI, 1052 const MipsSubtarget &Subtarget) { 1053 // (sub v0 (mul v1, v2)) => (msub v1, v2, v0) 1054 if (DCI.isBeforeLegalizeOps()) { 1055 if (Subtarget.hasMips32() && !Subtarget.hasMips32r6() && 1056 !Subtarget.inMips16Mode() && N->getValueType(0) == MVT::i64) 1057 return performMADD_MSUBCombine(N, DAG, Subtarget); 1058 1059 return SDValue(); 1060 } 1061 1062 return SDValue(); 1063 } 1064 1065 static SDValue performADDCombine(SDNode *N, SelectionDAG &DAG, 1066 TargetLowering::DAGCombinerInfo &DCI, 1067 const MipsSubtarget &Subtarget) { 1068 // (add v0 (mul v1, v2)) => (madd v1, v2, v0) 1069 if (DCI.isBeforeLegalizeOps()) { 1070 if (Subtarget.hasMips32() && !Subtarget.hasMips32r6() && 1071 !Subtarget.inMips16Mode() && N->getValueType(0) == MVT::i64) 1072 return performMADD_MSUBCombine(N, DAG, Subtarget); 1073 1074 return SDValue(); 1075 } 1076 1077 // (add v0, (add v1, abs_lo(tjt))) => (add (add v0, v1), abs_lo(tjt)) 1078 SDValue Add = N->getOperand(1); 1079 1080 if (Add.getOpcode() != ISD::ADD) 1081 return SDValue(); 1082 1083 SDValue Lo = Add.getOperand(1); 1084 1085 if ((Lo.getOpcode() != MipsISD::Lo) || 1086 (Lo.getOperand(0).getOpcode() != ISD::TargetJumpTable)) 1087 return SDValue(); 1088 1089 EVT ValTy = N->getValueType(0); 1090 SDLoc DL(N); 1091 1092 SDValue Add1 = DAG.getNode(ISD::ADD, DL, ValTy, N->getOperand(0), 1093 Add.getOperand(0)); 1094 return DAG.getNode(ISD::ADD, DL, ValTy, Add1, Lo); 1095 } 1096 1097 static SDValue performSHLCombine(SDNode *N, SelectionDAG &DAG, 1098 TargetLowering::DAGCombinerInfo &DCI, 1099 const MipsSubtarget &Subtarget) { 1100 // Pattern match CINS. 1101 // $dst = shl (and $src , imm), pos 1102 // => cins $dst, $src, pos, size 1103 1104 if (DCI.isBeforeLegalizeOps() || !Subtarget.hasCnMips()) 1105 return SDValue(); 1106 1107 SDValue FirstOperand = N->getOperand(0); 1108 unsigned FirstOperandOpc = FirstOperand.getOpcode(); 1109 SDValue SecondOperand = N->getOperand(1); 1110 EVT ValTy = N->getValueType(0); 1111 SDLoc DL(N); 1112 1113 uint64_t Pos = 0, SMPos, SMSize; 1114 ConstantSDNode *CN; 1115 SDValue NewOperand; 1116 1117 // The second operand of the shift must be an immediate. 1118 if (!(CN = dyn_cast<ConstantSDNode>(SecondOperand))) 1119 return SDValue(); 1120 1121 Pos = CN->getZExtValue(); 1122 1123 if (Pos >= ValTy.getSizeInBits()) 1124 return SDValue(); 1125 1126 if (FirstOperandOpc != ISD::AND) 1127 return SDValue(); 1128 1129 // AND's second operand must be a shifted mask. 1130 if (!(CN = dyn_cast<ConstantSDNode>(FirstOperand.getOperand(1))) || 1131 !isShiftedMask(CN->getZExtValue(), SMPos, SMSize)) 1132 return SDValue(); 1133 1134 // Return if the shifted mask does not start at bit 0 or the sum of its size 1135 // and Pos exceeds the word's size. 1136 if (SMPos != 0 || SMSize > 32 || Pos + SMSize > ValTy.getSizeInBits()) 1137 return SDValue(); 1138 1139 NewOperand = FirstOperand.getOperand(0); 1140 // SMSize is 'location' (position) in this case, not size. 1141 SMSize--; 1142 1143 return DAG.getNode(MipsISD::CIns, DL, ValTy, NewOperand, 1144 DAG.getConstant(Pos, DL, MVT::i32), 1145 DAG.getConstant(SMSize, DL, MVT::i32)); 1146 } 1147 1148 SDValue MipsTargetLowering::PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) 1149 const { 1150 SelectionDAG &DAG = DCI.DAG; 1151 unsigned Opc = N->getOpcode(); 1152 1153 switch (Opc) { 1154 default: break; 1155 case ISD::SDIVREM: 1156 case ISD::UDIVREM: 1157 return performDivRemCombine(N, DAG, DCI, Subtarget); 1158 case ISD::SELECT: 1159 return performSELECTCombine(N, DAG, DCI, Subtarget); 1160 case MipsISD::CMovFP_F: 1161 case MipsISD::CMovFP_T: 1162 return performCMovFPCombine(N, DAG, DCI, Subtarget); 1163 case ISD::AND: 1164 return performANDCombine(N, DAG, DCI, Subtarget); 1165 case ISD::OR: 1166 return performORCombine(N, DAG, DCI, Subtarget); 1167 case ISD::ADD: 1168 return performADDCombine(N, DAG, DCI, Subtarget); 1169 case ISD::SHL: 1170 return performSHLCombine(N, DAG, DCI, Subtarget); 1171 case ISD::SUB: 1172 return performSUBCombine(N, DAG, DCI, Subtarget); 1173 } 1174 1175 return SDValue(); 1176 } 1177 1178 bool MipsTargetLowering::isCheapToSpeculateCttz() const { 1179 return Subtarget.hasMips32(); 1180 } 1181 1182 bool MipsTargetLowering::isCheapToSpeculateCtlz() const { 1183 return Subtarget.hasMips32(); 1184 } 1185 1186 void 1187 MipsTargetLowering::LowerOperationWrapper(SDNode *N, 1188 SmallVectorImpl<SDValue> &Results, 1189 SelectionDAG &DAG) const { 1190 SDValue Res = LowerOperation(SDValue(N, 0), DAG); 1191 1192 for (unsigned I = 0, E = Res->getNumValues(); I != E; ++I) 1193 Results.push_back(Res.getValue(I)); 1194 } 1195 1196 void 1197 MipsTargetLowering::ReplaceNodeResults(SDNode *N, 1198 SmallVectorImpl<SDValue> &Results, 1199 SelectionDAG &DAG) const { 1200 return LowerOperationWrapper(N, Results, DAG); 1201 } 1202 1203 SDValue MipsTargetLowering:: 1204 LowerOperation(SDValue Op, SelectionDAG &DAG) const 1205 { 1206 switch (Op.getOpcode()) 1207 { 1208 case ISD::BRCOND: return lowerBRCOND(Op, DAG); 1209 case ISD::ConstantPool: return lowerConstantPool(Op, DAG); 1210 case ISD::GlobalAddress: return lowerGlobalAddress(Op, DAG); 1211 case ISD::BlockAddress: return lowerBlockAddress(Op, DAG); 1212 case ISD::GlobalTLSAddress: return lowerGlobalTLSAddress(Op, DAG); 1213 case ISD::JumpTable: return lowerJumpTable(Op, DAG); 1214 case ISD::SELECT: return lowerSELECT(Op, DAG); 1215 case ISD::SETCC: return lowerSETCC(Op, DAG); 1216 case ISD::VASTART: return lowerVASTART(Op, DAG); 1217 case ISD::VAARG: return lowerVAARG(Op, DAG); 1218 case ISD::FCOPYSIGN: return lowerFCOPYSIGN(Op, DAG); 1219 case ISD::FRAMEADDR: return lowerFRAMEADDR(Op, DAG); 1220 case ISD::RETURNADDR: return lowerRETURNADDR(Op, DAG); 1221 case ISD::EH_RETURN: return lowerEH_RETURN(Op, DAG); 1222 case ISD::ATOMIC_FENCE: return lowerATOMIC_FENCE(Op, DAG); 1223 case ISD::SHL_PARTS: return lowerShiftLeftParts(Op, DAG); 1224 case ISD::SRA_PARTS: return lowerShiftRightParts(Op, DAG, true); 1225 case ISD::SRL_PARTS: return lowerShiftRightParts(Op, DAG, false); 1226 case ISD::LOAD: return lowerLOAD(Op, DAG); 1227 case ISD::STORE: return lowerSTORE(Op, DAG); 1228 case ISD::EH_DWARF_CFA: return lowerEH_DWARF_CFA(Op, DAG); 1229 case ISD::FP_TO_SINT: return lowerFP_TO_SINT(Op, DAG); 1230 } 1231 return SDValue(); 1232 } 1233 1234 //===----------------------------------------------------------------------===// 1235 // Lower helper functions 1236 //===----------------------------------------------------------------------===// 1237 1238 // addLiveIn - This helper function adds the specified physical register to the 1239 // MachineFunction as a live in value. It also creates a corresponding 1240 // virtual register for it. 1241 static unsigned 1242 addLiveIn(MachineFunction &MF, unsigned PReg, const TargetRegisterClass *RC) 1243 { 1244 unsigned VReg = MF.getRegInfo().createVirtualRegister(RC); 1245 MF.getRegInfo().addLiveIn(PReg, VReg); 1246 return VReg; 1247 } 1248 1249 static MachineBasicBlock *insertDivByZeroTrap(MachineInstr &MI, 1250 MachineBasicBlock &MBB, 1251 const TargetInstrInfo &TII, 1252 bool Is64Bit, bool IsMicroMips) { 1253 if (NoZeroDivCheck) 1254 return &MBB; 1255 1256 // Insert instruction "teq $divisor_reg, $zero, 7". 1257 MachineBasicBlock::iterator I(MI); 1258 MachineInstrBuilder MIB; 1259 MachineOperand &Divisor = MI.getOperand(2); 1260 MIB = BuildMI(MBB, std::next(I), MI.getDebugLoc(), 1261 TII.get(IsMicroMips ? Mips::TEQ_MM : Mips::TEQ)) 1262 .addReg(Divisor.getReg(), getKillRegState(Divisor.isKill())) 1263 .addReg(Mips::ZERO) 1264 .addImm(7); 1265 1266 // Use the 32-bit sub-register if this is a 64-bit division. 1267 if (Is64Bit) 1268 MIB->getOperand(0).setSubReg(Mips::sub_32); 1269 1270 // Clear Divisor's kill flag. 1271 Divisor.setIsKill(false); 1272 1273 // We would normally delete the original instruction here but in this case 1274 // we only needed to inject an additional instruction rather than replace it. 1275 1276 return &MBB; 1277 } 1278 1279 MachineBasicBlock * 1280 MipsTargetLowering::EmitInstrWithCustomInserter(MachineInstr &MI, 1281 MachineBasicBlock *BB) const { 1282 switch (MI.getOpcode()) { 1283 default: 1284 llvm_unreachable("Unexpected instr type to insert"); 1285 case Mips::ATOMIC_LOAD_ADD_I8: 1286 return emitAtomicBinaryPartword(MI, BB, 1); 1287 case Mips::ATOMIC_LOAD_ADD_I16: 1288 return emitAtomicBinaryPartword(MI, BB, 2); 1289 case Mips::ATOMIC_LOAD_ADD_I32: 1290 return emitAtomicBinary(MI, BB); 1291 case Mips::ATOMIC_LOAD_ADD_I64: 1292 return emitAtomicBinary(MI, BB); 1293 1294 case Mips::ATOMIC_LOAD_AND_I8: 1295 return emitAtomicBinaryPartword(MI, BB, 1); 1296 case Mips::ATOMIC_LOAD_AND_I16: 1297 return emitAtomicBinaryPartword(MI, BB, 2); 1298 case Mips::ATOMIC_LOAD_AND_I32: 1299 return emitAtomicBinary(MI, BB); 1300 case Mips::ATOMIC_LOAD_AND_I64: 1301 return emitAtomicBinary(MI, BB); 1302 1303 case Mips::ATOMIC_LOAD_OR_I8: 1304 return emitAtomicBinaryPartword(MI, BB, 1); 1305 case Mips::ATOMIC_LOAD_OR_I16: 1306 return emitAtomicBinaryPartword(MI, BB, 2); 1307 case Mips::ATOMIC_LOAD_OR_I32: 1308 return emitAtomicBinary(MI, BB); 1309 case Mips::ATOMIC_LOAD_OR_I64: 1310 return emitAtomicBinary(MI, BB); 1311 1312 case Mips::ATOMIC_LOAD_XOR_I8: 1313 return emitAtomicBinaryPartword(MI, BB, 1); 1314 case Mips::ATOMIC_LOAD_XOR_I16: 1315 return emitAtomicBinaryPartword(MI, BB, 2); 1316 case Mips::ATOMIC_LOAD_XOR_I32: 1317 return emitAtomicBinary(MI, BB); 1318 case Mips::ATOMIC_LOAD_XOR_I64: 1319 return emitAtomicBinary(MI, BB); 1320 1321 case Mips::ATOMIC_LOAD_NAND_I8: 1322 return emitAtomicBinaryPartword(MI, BB, 1); 1323 case Mips::ATOMIC_LOAD_NAND_I16: 1324 return emitAtomicBinaryPartword(MI, BB, 2); 1325 case Mips::ATOMIC_LOAD_NAND_I32: 1326 return emitAtomicBinary(MI, BB); 1327 case Mips::ATOMIC_LOAD_NAND_I64: 1328 return emitAtomicBinary(MI, BB); 1329 1330 case Mips::ATOMIC_LOAD_SUB_I8: 1331 return emitAtomicBinaryPartword(MI, BB, 1); 1332 case Mips::ATOMIC_LOAD_SUB_I16: 1333 return emitAtomicBinaryPartword(MI, BB, 2); 1334 case Mips::ATOMIC_LOAD_SUB_I32: 1335 return emitAtomicBinary(MI, BB); 1336 case Mips::ATOMIC_LOAD_SUB_I64: 1337 return emitAtomicBinary(MI, BB); 1338 1339 case Mips::ATOMIC_SWAP_I8: 1340 return emitAtomicBinaryPartword(MI, BB, 1); 1341 case Mips::ATOMIC_SWAP_I16: 1342 return emitAtomicBinaryPartword(MI, BB, 2); 1343 case Mips::ATOMIC_SWAP_I32: 1344 return emitAtomicBinary(MI, BB); 1345 case Mips::ATOMIC_SWAP_I64: 1346 return emitAtomicBinary(MI, BB); 1347 1348 case Mips::ATOMIC_CMP_SWAP_I8: 1349 return emitAtomicCmpSwapPartword(MI, BB, 1); 1350 case Mips::ATOMIC_CMP_SWAP_I16: 1351 return emitAtomicCmpSwapPartword(MI, BB, 2); 1352 case Mips::ATOMIC_CMP_SWAP_I32: 1353 return emitAtomicCmpSwap(MI, BB); 1354 case Mips::ATOMIC_CMP_SWAP_I64: 1355 return emitAtomicCmpSwap(MI, BB); 1356 case Mips::PseudoSDIV: 1357 case Mips::PseudoUDIV: 1358 case Mips::DIV: 1359 case Mips::DIVU: 1360 case Mips::MOD: 1361 case Mips::MODU: 1362 return insertDivByZeroTrap(MI, *BB, *Subtarget.getInstrInfo(), false, 1363 false); 1364 case Mips::SDIV_MM_Pseudo: 1365 case Mips::UDIV_MM_Pseudo: 1366 case Mips::SDIV_MM: 1367 case Mips::UDIV_MM: 1368 case Mips::DIV_MMR6: 1369 case Mips::DIVU_MMR6: 1370 case Mips::MOD_MMR6: 1371 case Mips::MODU_MMR6: 1372 return insertDivByZeroTrap(MI, *BB, *Subtarget.getInstrInfo(), false, true); 1373 case Mips::PseudoDSDIV: 1374 case Mips::PseudoDUDIV: 1375 case Mips::DDIV: 1376 case Mips::DDIVU: 1377 case Mips::DMOD: 1378 case Mips::DMODU: 1379 return insertDivByZeroTrap(MI, *BB, *Subtarget.getInstrInfo(), true, false); 1380 1381 case Mips::PseudoSELECT_I: 1382 case Mips::PseudoSELECT_I64: 1383 case Mips::PseudoSELECT_S: 1384 case Mips::PseudoSELECT_D32: 1385 case Mips::PseudoSELECT_D64: 1386 return emitPseudoSELECT(MI, BB, false, Mips::BNE); 1387 case Mips::PseudoSELECTFP_F_I: 1388 case Mips::PseudoSELECTFP_F_I64: 1389 case Mips::PseudoSELECTFP_F_S: 1390 case Mips::PseudoSELECTFP_F_D32: 1391 case Mips::PseudoSELECTFP_F_D64: 1392 return emitPseudoSELECT(MI, BB, true, Mips::BC1F); 1393 case Mips::PseudoSELECTFP_T_I: 1394 case Mips::PseudoSELECTFP_T_I64: 1395 case Mips::PseudoSELECTFP_T_S: 1396 case Mips::PseudoSELECTFP_T_D32: 1397 case Mips::PseudoSELECTFP_T_D64: 1398 return emitPseudoSELECT(MI, BB, true, Mips::BC1T); 1399 } 1400 } 1401 1402 // This function also handles Mips::ATOMIC_SWAP_I32 (when BinOpcode == 0), and 1403 // Mips::ATOMIC_LOAD_NAND_I32 (when Nand == true) 1404 MachineBasicBlock * 1405 MipsTargetLowering::emitAtomicBinary(MachineInstr &MI, 1406 MachineBasicBlock *BB) const { 1407 1408 MachineFunction *MF = BB->getParent(); 1409 MachineRegisterInfo &RegInfo = MF->getRegInfo(); 1410 const TargetInstrInfo *TII = Subtarget.getInstrInfo(); 1411 DebugLoc DL = MI.getDebugLoc(); 1412 1413 unsigned AtomicOp; 1414 switch (MI.getOpcode()) { 1415 case Mips::ATOMIC_LOAD_ADD_I32: 1416 AtomicOp = Mips::ATOMIC_LOAD_ADD_I32_POSTRA; 1417 break; 1418 case Mips::ATOMIC_LOAD_SUB_I32: 1419 AtomicOp = Mips::ATOMIC_LOAD_SUB_I32_POSTRA; 1420 break; 1421 case Mips::ATOMIC_LOAD_AND_I32: 1422 AtomicOp = Mips::ATOMIC_LOAD_AND_I32_POSTRA; 1423 break; 1424 case Mips::ATOMIC_LOAD_OR_I32: 1425 AtomicOp = Mips::ATOMIC_LOAD_OR_I32_POSTRA; 1426 break; 1427 case Mips::ATOMIC_LOAD_XOR_I32: 1428 AtomicOp = Mips::ATOMIC_LOAD_XOR_I32_POSTRA; 1429 break; 1430 case Mips::ATOMIC_LOAD_NAND_I32: 1431 AtomicOp = Mips::ATOMIC_LOAD_NAND_I32_POSTRA; 1432 break; 1433 case Mips::ATOMIC_SWAP_I32: 1434 AtomicOp = Mips::ATOMIC_SWAP_I32_POSTRA; 1435 break; 1436 case Mips::ATOMIC_LOAD_ADD_I64: 1437 AtomicOp = Mips::ATOMIC_LOAD_ADD_I64_POSTRA; 1438 break; 1439 case Mips::ATOMIC_LOAD_SUB_I64: 1440 AtomicOp = Mips::ATOMIC_LOAD_SUB_I64_POSTRA; 1441 break; 1442 case Mips::ATOMIC_LOAD_AND_I64: 1443 AtomicOp = Mips::ATOMIC_LOAD_AND_I64_POSTRA; 1444 break; 1445 case Mips::ATOMIC_LOAD_OR_I64: 1446 AtomicOp = Mips::ATOMIC_LOAD_OR_I64_POSTRA; 1447 break; 1448 case Mips::ATOMIC_LOAD_XOR_I64: 1449 AtomicOp = Mips::ATOMIC_LOAD_XOR_I64_POSTRA; 1450 break; 1451 case Mips::ATOMIC_LOAD_NAND_I64: 1452 AtomicOp = Mips::ATOMIC_LOAD_NAND_I64_POSTRA; 1453 break; 1454 case Mips::ATOMIC_SWAP_I64: 1455 AtomicOp = Mips::ATOMIC_SWAP_I64_POSTRA; 1456 break; 1457 default: 1458 llvm_unreachable("Unknown pseudo atomic for replacement!"); 1459 } 1460 1461 unsigned OldVal = MI.getOperand(0).getReg(); 1462 unsigned Ptr = MI.getOperand(1).getReg(); 1463 unsigned Incr = MI.getOperand(2).getReg(); 1464 unsigned Scratch = RegInfo.createVirtualRegister(RegInfo.getRegClass(OldVal)); 1465 1466 MachineBasicBlock::iterator II(MI); 1467 1468 // The scratch registers here with the EarlyClobber | Define | Implicit 1469 // flags is used to persuade the register allocator and the machine 1470 // verifier to accept the usage of this register. This has to be a real 1471 // register which has an UNDEF value but is dead after the instruction which 1472 // is unique among the registers chosen for the instruction. 1473 1474 // The EarlyClobber flag has the semantic properties that the operand it is 1475 // attached to is clobbered before the rest of the inputs are read. Hence it 1476 // must be unique among the operands to the instruction. 1477 // The Define flag is needed to coerce the machine verifier that an Undef 1478 // value isn't a problem. 1479 // The Dead flag is needed as the value in scratch isn't used by any other 1480 // instruction. Kill isn't used as Dead is more precise. 1481 // The implicit flag is here due to the interaction between the other flags 1482 // and the machine verifier. 1483 1484 // For correctness purpose, a new pseudo is introduced here. We need this 1485 // new pseudo, so that FastRegisterAllocator does not see an ll/sc sequence 1486 // that is spread over >1 basic blocks. A register allocator which 1487 // introduces (or any codegen infact) a store, can violate the expectations 1488 // of the hardware. 1489 // 1490 // An atomic read-modify-write sequence starts with a linked load 1491 // instruction and ends with a store conditional instruction. The atomic 1492 // read-modify-write sequence fails if any of the following conditions 1493 // occur between the execution of ll and sc: 1494 // * A coherent store is completed by another process or coherent I/O 1495 // module into the block of synchronizable physical memory containing 1496 // the word. The size and alignment of the block is 1497 // implementation-dependent. 1498 // * A coherent store is executed between an LL and SC sequence on the 1499 // same processor to the block of synchornizable physical memory 1500 // containing the word. 1501 // 1502 1503 unsigned PtrCopy = RegInfo.createVirtualRegister(RegInfo.getRegClass(Ptr)); 1504 unsigned IncrCopy = RegInfo.createVirtualRegister(RegInfo.getRegClass(Incr)); 1505 1506 BuildMI(*BB, II, DL, TII->get(Mips::COPY), IncrCopy).addReg(Incr); 1507 BuildMI(*BB, II, DL, TII->get(Mips::COPY), PtrCopy).addReg(Ptr); 1508 1509 BuildMI(*BB, II, DL, TII->get(AtomicOp)) 1510 .addReg(OldVal, RegState::Define | RegState::EarlyClobber) 1511 .addReg(PtrCopy) 1512 .addReg(IncrCopy) 1513 .addReg(Scratch, RegState::Define | RegState::EarlyClobber | 1514 RegState::Implicit | RegState::Dead); 1515 1516 MI.eraseFromParent(); 1517 1518 return BB; 1519 } 1520 1521 MachineBasicBlock *MipsTargetLowering::emitSignExtendToI32InReg( 1522 MachineInstr &MI, MachineBasicBlock *BB, unsigned Size, unsigned DstReg, 1523 unsigned SrcReg) const { 1524 const TargetInstrInfo *TII = Subtarget.getInstrInfo(); 1525 const DebugLoc &DL = MI.getDebugLoc(); 1526 1527 if (Subtarget.hasMips32r2() && Size == 1) { 1528 BuildMI(BB, DL, TII->get(Mips::SEB), DstReg).addReg(SrcReg); 1529 return BB; 1530 } 1531 1532 if (Subtarget.hasMips32r2() && Size == 2) { 1533 BuildMI(BB, DL, TII->get(Mips::SEH), DstReg).addReg(SrcReg); 1534 return BB; 1535 } 1536 1537 MachineFunction *MF = BB->getParent(); 1538 MachineRegisterInfo &RegInfo = MF->getRegInfo(); 1539 const TargetRegisterClass *RC = getRegClassFor(MVT::i32); 1540 unsigned ScrReg = RegInfo.createVirtualRegister(RC); 1541 1542 assert(Size < 32); 1543 int64_t ShiftImm = 32 - (Size * 8); 1544 1545 BuildMI(BB, DL, TII->get(Mips::SLL), ScrReg).addReg(SrcReg).addImm(ShiftImm); 1546 BuildMI(BB, DL, TII->get(Mips::SRA), DstReg).addReg(ScrReg).addImm(ShiftImm); 1547 1548 return BB; 1549 } 1550 1551 MachineBasicBlock *MipsTargetLowering::emitAtomicBinaryPartword( 1552 MachineInstr &MI, MachineBasicBlock *BB, unsigned Size) const { 1553 assert((Size == 1 || Size == 2) && 1554 "Unsupported size for EmitAtomicBinaryPartial."); 1555 1556 MachineFunction *MF = BB->getParent(); 1557 MachineRegisterInfo &RegInfo = MF->getRegInfo(); 1558 const TargetRegisterClass *RC = getRegClassFor(MVT::i32); 1559 const bool ArePtrs64bit = ABI.ArePtrs64bit(); 1560 const TargetRegisterClass *RCp = 1561 getRegClassFor(ArePtrs64bit ? MVT::i64 : MVT::i32); 1562 const TargetInstrInfo *TII = Subtarget.getInstrInfo(); 1563 DebugLoc DL = MI.getDebugLoc(); 1564 1565 unsigned Dest = MI.getOperand(0).getReg(); 1566 unsigned Ptr = MI.getOperand(1).getReg(); 1567 unsigned Incr = MI.getOperand(2).getReg(); 1568 1569 unsigned AlignedAddr = RegInfo.createVirtualRegister(RCp); 1570 unsigned ShiftAmt = RegInfo.createVirtualRegister(RC); 1571 unsigned Mask = RegInfo.createVirtualRegister(RC); 1572 unsigned Mask2 = RegInfo.createVirtualRegister(RC); 1573 unsigned Incr2 = RegInfo.createVirtualRegister(RC); 1574 unsigned MaskLSB2 = RegInfo.createVirtualRegister(RCp); 1575 unsigned PtrLSB2 = RegInfo.createVirtualRegister(RC); 1576 unsigned MaskUpper = RegInfo.createVirtualRegister(RC); 1577 unsigned Scratch = RegInfo.createVirtualRegister(RC); 1578 unsigned Scratch2 = RegInfo.createVirtualRegister(RC); 1579 unsigned Scratch3 = RegInfo.createVirtualRegister(RC); 1580 1581 unsigned AtomicOp = 0; 1582 switch (MI.getOpcode()) { 1583 case Mips::ATOMIC_LOAD_NAND_I8: 1584 AtomicOp = Mips::ATOMIC_LOAD_NAND_I8_POSTRA; 1585 break; 1586 case Mips::ATOMIC_LOAD_NAND_I16: 1587 AtomicOp = Mips::ATOMIC_LOAD_NAND_I16_POSTRA; 1588 break; 1589 case Mips::ATOMIC_SWAP_I8: 1590 AtomicOp = Mips::ATOMIC_SWAP_I8_POSTRA; 1591 break; 1592 case Mips::ATOMIC_SWAP_I16: 1593 AtomicOp = Mips::ATOMIC_SWAP_I16_POSTRA; 1594 break; 1595 case Mips::ATOMIC_LOAD_ADD_I8: 1596 AtomicOp = Mips::ATOMIC_LOAD_ADD_I8_POSTRA; 1597 break; 1598 case Mips::ATOMIC_LOAD_ADD_I16: 1599 AtomicOp = Mips::ATOMIC_LOAD_ADD_I16_POSTRA; 1600 break; 1601 case Mips::ATOMIC_LOAD_SUB_I8: 1602 AtomicOp = Mips::ATOMIC_LOAD_SUB_I8_POSTRA; 1603 break; 1604 case Mips::ATOMIC_LOAD_SUB_I16: 1605 AtomicOp = Mips::ATOMIC_LOAD_SUB_I16_POSTRA; 1606 break; 1607 case Mips::ATOMIC_LOAD_AND_I8: 1608 AtomicOp = Mips::ATOMIC_LOAD_AND_I8_POSTRA; 1609 break; 1610 case Mips::ATOMIC_LOAD_AND_I16: 1611 AtomicOp = Mips::ATOMIC_LOAD_AND_I16_POSTRA; 1612 break; 1613 case Mips::ATOMIC_LOAD_OR_I8: 1614 AtomicOp = Mips::ATOMIC_LOAD_OR_I8_POSTRA; 1615 break; 1616 case Mips::ATOMIC_LOAD_OR_I16: 1617 AtomicOp = Mips::ATOMIC_LOAD_OR_I16_POSTRA; 1618 break; 1619 case Mips::ATOMIC_LOAD_XOR_I8: 1620 AtomicOp = Mips::ATOMIC_LOAD_XOR_I8_POSTRA; 1621 break; 1622 case Mips::ATOMIC_LOAD_XOR_I16: 1623 AtomicOp = Mips::ATOMIC_LOAD_XOR_I16_POSTRA; 1624 break; 1625 default: 1626 llvm_unreachable("Unknown subword atomic pseudo for expansion!"); 1627 } 1628 1629 // insert new blocks after the current block 1630 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 1631 MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB); 1632 MachineFunction::iterator It = ++BB->getIterator(); 1633 MF->insert(It, exitMBB); 1634 1635 // Transfer the remainder of BB and its successor edges to exitMBB. 1636 exitMBB->splice(exitMBB->begin(), BB, 1637 std::next(MachineBasicBlock::iterator(MI)), BB->end()); 1638 exitMBB->transferSuccessorsAndUpdatePHIs(BB); 1639 1640 BB->addSuccessor(exitMBB, BranchProbability::getOne()); 1641 1642 // thisMBB: 1643 // addiu masklsb2,$0,-4 # 0xfffffffc 1644 // and alignedaddr,ptr,masklsb2 1645 // andi ptrlsb2,ptr,3 1646 // sll shiftamt,ptrlsb2,3 1647 // ori maskupper,$0,255 # 0xff 1648 // sll mask,maskupper,shiftamt 1649 // nor mask2,$0,mask 1650 // sll incr2,incr,shiftamt 1651 1652 int64_t MaskImm = (Size == 1) ? 255 : 65535; 1653 BuildMI(BB, DL, TII->get(ABI.GetPtrAddiuOp()), MaskLSB2) 1654 .addReg(ABI.GetNullPtr()).addImm(-4); 1655 BuildMI(BB, DL, TII->get(ABI.GetPtrAndOp()), AlignedAddr) 1656 .addReg(Ptr).addReg(MaskLSB2); 1657 BuildMI(BB, DL, TII->get(Mips::ANDi), PtrLSB2) 1658 .addReg(Ptr, 0, ArePtrs64bit ? Mips::sub_32 : 0).addImm(3); 1659 if (Subtarget.isLittle()) { 1660 BuildMI(BB, DL, TII->get(Mips::SLL), ShiftAmt).addReg(PtrLSB2).addImm(3); 1661 } else { 1662 unsigned Off = RegInfo.createVirtualRegister(RC); 1663 BuildMI(BB, DL, TII->get(Mips::XORi), Off) 1664 .addReg(PtrLSB2).addImm((Size == 1) ? 3 : 2); 1665 BuildMI(BB, DL, TII->get(Mips::SLL), ShiftAmt).addReg(Off).addImm(3); 1666 } 1667 BuildMI(BB, DL, TII->get(Mips::ORi), MaskUpper) 1668 .addReg(Mips::ZERO).addImm(MaskImm); 1669 BuildMI(BB, DL, TII->get(Mips::SLLV), Mask) 1670 .addReg(MaskUpper).addReg(ShiftAmt); 1671 BuildMI(BB, DL, TII->get(Mips::NOR), Mask2).addReg(Mips::ZERO).addReg(Mask); 1672 BuildMI(BB, DL, TII->get(Mips::SLLV), Incr2).addReg(Incr).addReg(ShiftAmt); 1673 1674 1675 // The purposes of the flags on the scratch registers is explained in 1676 // emitAtomicBinary. In summary, we need a scratch register which is going to 1677 // be undef, that is unique among registers chosen for the instruction. 1678 1679 BuildMI(BB, DL, TII->get(AtomicOp)) 1680 .addReg(Dest, RegState::Define | RegState::EarlyClobber) 1681 .addReg(AlignedAddr) 1682 .addReg(Incr2) 1683 .addReg(Mask) 1684 .addReg(Mask2) 1685 .addReg(ShiftAmt) 1686 .addReg(Scratch, RegState::EarlyClobber | RegState::Define | 1687 RegState::Dead | RegState::Implicit) 1688 .addReg(Scratch2, RegState::EarlyClobber | RegState::Define | 1689 RegState::Dead | RegState::Implicit) 1690 .addReg(Scratch3, RegState::EarlyClobber | RegState::Define | 1691 RegState::Dead | RegState::Implicit); 1692 1693 MI.eraseFromParent(); // The instruction is gone now. 1694 1695 return exitMBB; 1696 } 1697 1698 // Lower atomic compare and swap to a pseudo instruction, taking care to 1699 // define a scratch register for the pseudo instruction's expansion. The 1700 // instruction is expanded after the register allocator as to prevent 1701 // the insertion of stores between the linked load and the store conditional. 1702 1703 MachineBasicBlock * 1704 MipsTargetLowering::emitAtomicCmpSwap(MachineInstr &MI, 1705 MachineBasicBlock *BB) const { 1706 1707 assert((MI.getOpcode() == Mips::ATOMIC_CMP_SWAP_I32 || 1708 MI.getOpcode() == Mips::ATOMIC_CMP_SWAP_I64) && 1709 "Unsupported atomic psseudo for EmitAtomicCmpSwap."); 1710 1711 const unsigned Size = MI.getOpcode() == Mips::ATOMIC_CMP_SWAP_I32 ? 4 : 8; 1712 1713 MachineFunction *MF = BB->getParent(); 1714 MachineRegisterInfo &MRI = MF->getRegInfo(); 1715 const TargetRegisterClass *RC = getRegClassFor(MVT::getIntegerVT(Size * 8)); 1716 const TargetInstrInfo *TII = Subtarget.getInstrInfo(); 1717 DebugLoc DL = MI.getDebugLoc(); 1718 1719 unsigned AtomicOp = MI.getOpcode() == Mips::ATOMIC_CMP_SWAP_I32 1720 ? Mips::ATOMIC_CMP_SWAP_I32_POSTRA 1721 : Mips::ATOMIC_CMP_SWAP_I64_POSTRA; 1722 unsigned Dest = MI.getOperand(0).getReg(); 1723 unsigned Ptr = MI.getOperand(1).getReg(); 1724 unsigned OldVal = MI.getOperand(2).getReg(); 1725 unsigned NewVal = MI.getOperand(3).getReg(); 1726 1727 unsigned Scratch = MRI.createVirtualRegister(RC); 1728 MachineBasicBlock::iterator II(MI); 1729 1730 // We need to create copies of the various registers and kill them at the 1731 // atomic pseudo. If the copies are not made, when the atomic is expanded 1732 // after fast register allocation, the spills will end up outside of the 1733 // blocks that their values are defined in, causing livein errors. 1734 1735 unsigned DestCopy = MRI.createVirtualRegister(MRI.getRegClass(Dest)); 1736 unsigned PtrCopy = MRI.createVirtualRegister(MRI.getRegClass(Ptr)); 1737 unsigned OldValCopy = MRI.createVirtualRegister(MRI.getRegClass(OldVal)); 1738 unsigned NewValCopy = MRI.createVirtualRegister(MRI.getRegClass(NewVal)); 1739 1740 BuildMI(*BB, II, DL, TII->get(Mips::COPY), DestCopy).addReg(Dest); 1741 BuildMI(*BB, II, DL, TII->get(Mips::COPY), PtrCopy).addReg(Ptr); 1742 BuildMI(*BB, II, DL, TII->get(Mips::COPY), OldValCopy).addReg(OldVal); 1743 BuildMI(*BB, II, DL, TII->get(Mips::COPY), NewValCopy).addReg(NewVal); 1744 1745 // The purposes of the flags on the scratch registers is explained in 1746 // emitAtomicBinary. In summary, we need a scratch register which is going to 1747 // be undef, that is unique among registers chosen for the instruction. 1748 1749 BuildMI(*BB, II, DL, TII->get(AtomicOp)) 1750 .addReg(Dest, RegState::Define | RegState::EarlyClobber) 1751 .addReg(PtrCopy, RegState::Kill) 1752 .addReg(OldValCopy, RegState::Kill) 1753 .addReg(NewValCopy, RegState::Kill) 1754 .addReg(Scratch, RegState::EarlyClobber | RegState::Define | 1755 RegState::Dead | RegState::Implicit); 1756 1757 MI.eraseFromParent(); // The instruction is gone now. 1758 1759 return BB; 1760 } 1761 1762 MachineBasicBlock *MipsTargetLowering::emitAtomicCmpSwapPartword( 1763 MachineInstr &MI, MachineBasicBlock *BB, unsigned Size) const { 1764 assert((Size == 1 || Size == 2) && 1765 "Unsupported size for EmitAtomicCmpSwapPartial."); 1766 1767 MachineFunction *MF = BB->getParent(); 1768 MachineRegisterInfo &RegInfo = MF->getRegInfo(); 1769 const TargetRegisterClass *RC = getRegClassFor(MVT::i32); 1770 const bool ArePtrs64bit = ABI.ArePtrs64bit(); 1771 const TargetRegisterClass *RCp = 1772 getRegClassFor(ArePtrs64bit ? MVT::i64 : MVT::i32); 1773 const TargetInstrInfo *TII = Subtarget.getInstrInfo(); 1774 DebugLoc DL = MI.getDebugLoc(); 1775 1776 unsigned Dest = MI.getOperand(0).getReg(); 1777 unsigned Ptr = MI.getOperand(1).getReg(); 1778 unsigned CmpVal = MI.getOperand(2).getReg(); 1779 unsigned NewVal = MI.getOperand(3).getReg(); 1780 1781 unsigned AlignedAddr = RegInfo.createVirtualRegister(RCp); 1782 unsigned ShiftAmt = RegInfo.createVirtualRegister(RC); 1783 unsigned Mask = RegInfo.createVirtualRegister(RC); 1784 unsigned Mask2 = RegInfo.createVirtualRegister(RC); 1785 unsigned ShiftedCmpVal = RegInfo.createVirtualRegister(RC); 1786 unsigned ShiftedNewVal = RegInfo.createVirtualRegister(RC); 1787 unsigned MaskLSB2 = RegInfo.createVirtualRegister(RCp); 1788 unsigned PtrLSB2 = RegInfo.createVirtualRegister(RC); 1789 unsigned MaskUpper = RegInfo.createVirtualRegister(RC); 1790 unsigned MaskedCmpVal = RegInfo.createVirtualRegister(RC); 1791 unsigned MaskedNewVal = RegInfo.createVirtualRegister(RC); 1792 unsigned AtomicOp = MI.getOpcode() == Mips::ATOMIC_CMP_SWAP_I8 1793 ? Mips::ATOMIC_CMP_SWAP_I8_POSTRA 1794 : Mips::ATOMIC_CMP_SWAP_I16_POSTRA; 1795 1796 // The scratch registers here with the EarlyClobber | Define | Dead | Implicit 1797 // flags are used to coerce the register allocator and the machine verifier to 1798 // accept the usage of these registers. 1799 // The EarlyClobber flag has the semantic properties that the operand it is 1800 // attached to is clobbered before the rest of the inputs are read. Hence it 1801 // must be unique among the operands to the instruction. 1802 // The Define flag is needed to coerce the machine verifier that an Undef 1803 // value isn't a problem. 1804 // The Dead flag is needed as the value in scratch isn't used by any other 1805 // instruction. Kill isn't used as Dead is more precise. 1806 unsigned Scratch = RegInfo.createVirtualRegister(RC); 1807 unsigned Scratch2 = RegInfo.createVirtualRegister(RC); 1808 1809 // insert new blocks after the current block 1810 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 1811 MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB); 1812 MachineFunction::iterator It = ++BB->getIterator(); 1813 MF->insert(It, exitMBB); 1814 1815 // Transfer the remainder of BB and its successor edges to exitMBB. 1816 exitMBB->splice(exitMBB->begin(), BB, 1817 std::next(MachineBasicBlock::iterator(MI)), BB->end()); 1818 exitMBB->transferSuccessorsAndUpdatePHIs(BB); 1819 1820 BB->addSuccessor(exitMBB, BranchProbability::getOne()); 1821 1822 // thisMBB: 1823 // addiu masklsb2,$0,-4 # 0xfffffffc 1824 // and alignedaddr,ptr,masklsb2 1825 // andi ptrlsb2,ptr,3 1826 // xori ptrlsb2,ptrlsb2,3 # Only for BE 1827 // sll shiftamt,ptrlsb2,3 1828 // ori maskupper,$0,255 # 0xff 1829 // sll mask,maskupper,shiftamt 1830 // nor mask2,$0,mask 1831 // andi maskedcmpval,cmpval,255 1832 // sll shiftedcmpval,maskedcmpval,shiftamt 1833 // andi maskednewval,newval,255 1834 // sll shiftednewval,maskednewval,shiftamt 1835 int64_t MaskImm = (Size == 1) ? 255 : 65535; 1836 BuildMI(BB, DL, TII->get(ArePtrs64bit ? Mips::DADDiu : Mips::ADDiu), MaskLSB2) 1837 .addReg(ABI.GetNullPtr()).addImm(-4); 1838 BuildMI(BB, DL, TII->get(ArePtrs64bit ? Mips::AND64 : Mips::AND), AlignedAddr) 1839 .addReg(Ptr).addReg(MaskLSB2); 1840 BuildMI(BB, DL, TII->get(Mips::ANDi), PtrLSB2) 1841 .addReg(Ptr, 0, ArePtrs64bit ? Mips::sub_32 : 0).addImm(3); 1842 if (Subtarget.isLittle()) { 1843 BuildMI(BB, DL, TII->get(Mips::SLL), ShiftAmt).addReg(PtrLSB2).addImm(3); 1844 } else { 1845 unsigned Off = RegInfo.createVirtualRegister(RC); 1846 BuildMI(BB, DL, TII->get(Mips::XORi), Off) 1847 .addReg(PtrLSB2).addImm((Size == 1) ? 3 : 2); 1848 BuildMI(BB, DL, TII->get(Mips::SLL), ShiftAmt).addReg(Off).addImm(3); 1849 } 1850 BuildMI(BB, DL, TII->get(Mips::ORi), MaskUpper) 1851 .addReg(Mips::ZERO).addImm(MaskImm); 1852 BuildMI(BB, DL, TII->get(Mips::SLLV), Mask) 1853 .addReg(MaskUpper).addReg(ShiftAmt); 1854 BuildMI(BB, DL, TII->get(Mips::NOR), Mask2).addReg(Mips::ZERO).addReg(Mask); 1855 BuildMI(BB, DL, TII->get(Mips::ANDi), MaskedCmpVal) 1856 .addReg(CmpVal).addImm(MaskImm); 1857 BuildMI(BB, DL, TII->get(Mips::SLLV), ShiftedCmpVal) 1858 .addReg(MaskedCmpVal).addReg(ShiftAmt); 1859 BuildMI(BB, DL, TII->get(Mips::ANDi), MaskedNewVal) 1860 .addReg(NewVal).addImm(MaskImm); 1861 BuildMI(BB, DL, TII->get(Mips::SLLV), ShiftedNewVal) 1862 .addReg(MaskedNewVal).addReg(ShiftAmt); 1863 1864 // The purposes of the flags on the scratch registers are explained in 1865 // emitAtomicBinary. In summary, we need a scratch register which is going to 1866 // be undef, that is unique among the register chosen for the instruction. 1867 1868 BuildMI(BB, DL, TII->get(AtomicOp)) 1869 .addReg(Dest, RegState::Define | RegState::EarlyClobber) 1870 .addReg(AlignedAddr) 1871 .addReg(Mask) 1872 .addReg(ShiftedCmpVal) 1873 .addReg(Mask2) 1874 .addReg(ShiftedNewVal) 1875 .addReg(ShiftAmt) 1876 .addReg(Scratch, RegState::EarlyClobber | RegState::Define | 1877 RegState::Dead | RegState::Implicit) 1878 .addReg(Scratch2, RegState::EarlyClobber | RegState::Define | 1879 RegState::Dead | RegState::Implicit); 1880 1881 MI.eraseFromParent(); // The instruction is gone now. 1882 1883 return exitMBB; 1884 } 1885 1886 SDValue MipsTargetLowering::lowerBRCOND(SDValue Op, SelectionDAG &DAG) const { 1887 // The first operand is the chain, the second is the condition, the third is 1888 // the block to branch to if the condition is true. 1889 SDValue Chain = Op.getOperand(0); 1890 SDValue Dest = Op.getOperand(2); 1891 SDLoc DL(Op); 1892 1893 assert(!Subtarget.hasMips32r6() && !Subtarget.hasMips64r6()); 1894 SDValue CondRes = createFPCmp(DAG, Op.getOperand(1)); 1895 1896 // Return if flag is not set by a floating point comparison. 1897 if (CondRes.getOpcode() != MipsISD::FPCmp) 1898 return Op; 1899 1900 SDValue CCNode = CondRes.getOperand(2); 1901 Mips::CondCode CC = 1902 (Mips::CondCode)cast<ConstantSDNode>(CCNode)->getZExtValue(); 1903 unsigned Opc = invertFPCondCodeUser(CC) ? Mips::BRANCH_F : Mips::BRANCH_T; 1904 SDValue BrCode = DAG.getConstant(Opc, DL, MVT::i32); 1905 SDValue FCC0 = DAG.getRegister(Mips::FCC0, MVT::i32); 1906 return DAG.getNode(MipsISD::FPBrcond, DL, Op.getValueType(), Chain, BrCode, 1907 FCC0, Dest, CondRes); 1908 } 1909 1910 SDValue MipsTargetLowering:: 1911 lowerSELECT(SDValue Op, SelectionDAG &DAG) const 1912 { 1913 assert(!Subtarget.hasMips32r6() && !Subtarget.hasMips64r6()); 1914 SDValue Cond = createFPCmp(DAG, Op.getOperand(0)); 1915 1916 // Return if flag is not set by a floating point comparison. 1917 if (Cond.getOpcode() != MipsISD::FPCmp) 1918 return Op; 1919 1920 return createCMovFP(DAG, Cond, Op.getOperand(1), Op.getOperand(2), 1921 SDLoc(Op)); 1922 } 1923 1924 SDValue MipsTargetLowering::lowerSETCC(SDValue Op, SelectionDAG &DAG) const { 1925 assert(!Subtarget.hasMips32r6() && !Subtarget.hasMips64r6()); 1926 SDValue Cond = createFPCmp(DAG, Op); 1927 1928 assert(Cond.getOpcode() == MipsISD::FPCmp && 1929 "Floating point operand expected."); 1930 1931 SDLoc DL(Op); 1932 SDValue True = DAG.getConstant(1, DL, MVT::i32); 1933 SDValue False = DAG.getConstant(0, DL, MVT::i32); 1934 1935 return createCMovFP(DAG, Cond, True, False, DL); 1936 } 1937 1938 SDValue MipsTargetLowering::lowerGlobalAddress(SDValue Op, 1939 SelectionDAG &DAG) const { 1940 EVT Ty = Op.getValueType(); 1941 GlobalAddressSDNode *N = cast<GlobalAddressSDNode>(Op); 1942 const GlobalValue *GV = N->getGlobal(); 1943 1944 if (!isPositionIndependent()) { 1945 const MipsTargetObjectFile *TLOF = 1946 static_cast<const MipsTargetObjectFile *>( 1947 getTargetMachine().getObjFileLowering()); 1948 const GlobalObject *GO = GV->getBaseObject(); 1949 if (GO && TLOF->IsGlobalInSmallSection(GO, getTargetMachine())) 1950 // %gp_rel relocation 1951 return getAddrGPRel(N, SDLoc(N), Ty, DAG, ABI.IsN64()); 1952 1953 // %hi/%lo relocation 1954 return Subtarget.hasSym32() ? getAddrNonPIC(N, SDLoc(N), Ty, DAG) 1955 // %highest/%higher/%hi/%lo relocation 1956 : getAddrNonPICSym64(N, SDLoc(N), Ty, DAG); 1957 } 1958 1959 // Every other architecture would use shouldAssumeDSOLocal in here, but 1960 // mips is special. 1961 // * In PIC code mips requires got loads even for local statics! 1962 // * To save on got entries, for local statics the got entry contains the 1963 // page and an additional add instruction takes care of the low bits. 1964 // * It is legal to access a hidden symbol with a non hidden undefined, 1965 // so one cannot guarantee that all access to a hidden symbol will know 1966 // it is hidden. 1967 // * Mips linkers don't support creating a page and a full got entry for 1968 // the same symbol. 1969 // * Given all that, we have to use a full got entry for hidden symbols :-( 1970 if (GV->hasLocalLinkage()) 1971 return getAddrLocal(N, SDLoc(N), Ty, DAG, ABI.IsN32() || ABI.IsN64()); 1972 1973 if (LargeGOT) 1974 return getAddrGlobalLargeGOT( 1975 N, SDLoc(N), Ty, DAG, MipsII::MO_GOT_HI16, MipsII::MO_GOT_LO16, 1976 DAG.getEntryNode(), 1977 MachinePointerInfo::getGOT(DAG.getMachineFunction())); 1978 1979 return getAddrGlobal( 1980 N, SDLoc(N), Ty, DAG, 1981 (ABI.IsN32() || ABI.IsN64()) ? MipsII::MO_GOT_DISP : MipsII::MO_GOT, 1982 DAG.getEntryNode(), MachinePointerInfo::getGOT(DAG.getMachineFunction())); 1983 } 1984 1985 SDValue MipsTargetLowering::lowerBlockAddress(SDValue Op, 1986 SelectionDAG &DAG) const { 1987 BlockAddressSDNode *N = cast<BlockAddressSDNode>(Op); 1988 EVT Ty = Op.getValueType(); 1989 1990 if (!isPositionIndependent()) 1991 return Subtarget.hasSym32() ? getAddrNonPIC(N, SDLoc(N), Ty, DAG) 1992 : getAddrNonPICSym64(N, SDLoc(N), Ty, DAG); 1993 1994 return getAddrLocal(N, SDLoc(N), Ty, DAG, ABI.IsN32() || ABI.IsN64()); 1995 } 1996 1997 SDValue MipsTargetLowering:: 1998 lowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const 1999 { 2000 // If the relocation model is PIC, use the General Dynamic TLS Model or 2001 // Local Dynamic TLS model, otherwise use the Initial Exec or 2002 // Local Exec TLS Model. 2003 2004 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op); 2005 if (DAG.getTarget().useEmulatedTLS()) 2006 return LowerToTLSEmulatedModel(GA, DAG); 2007 2008 SDLoc DL(GA); 2009 const GlobalValue *GV = GA->getGlobal(); 2010 EVT PtrVT = getPointerTy(DAG.getDataLayout()); 2011 2012 TLSModel::Model model = getTargetMachine().getTLSModel(GV); 2013 2014 if (model == TLSModel::GeneralDynamic || model == TLSModel::LocalDynamic) { 2015 // General Dynamic and Local Dynamic TLS Model. 2016 unsigned Flag = (model == TLSModel::LocalDynamic) ? MipsII::MO_TLSLDM 2017 : MipsII::MO_TLSGD; 2018 2019 SDValue TGA = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, Flag); 2020 SDValue Argument = DAG.getNode(MipsISD::Wrapper, DL, PtrVT, 2021 getGlobalReg(DAG, PtrVT), TGA); 2022 unsigned PtrSize = PtrVT.getSizeInBits(); 2023 IntegerType *PtrTy = Type::getIntNTy(*DAG.getContext(), PtrSize); 2024 2025 SDValue TlsGetAddr = DAG.getExternalSymbol("__tls_get_addr", PtrVT); 2026 2027 ArgListTy Args; 2028 ArgListEntry Entry; 2029 Entry.Node = Argument; 2030 Entry.Ty = PtrTy; 2031 Args.push_back(Entry); 2032 2033 TargetLowering::CallLoweringInfo CLI(DAG); 2034 CLI.setDebugLoc(DL) 2035 .setChain(DAG.getEntryNode()) 2036 .setLibCallee(CallingConv::C, PtrTy, TlsGetAddr, std::move(Args)); 2037 std::pair<SDValue, SDValue> CallResult = LowerCallTo(CLI); 2038 2039 SDValue Ret = CallResult.first; 2040 2041 if (model != TLSModel::LocalDynamic) 2042 return Ret; 2043 2044 SDValue TGAHi = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, 2045 MipsII::MO_DTPREL_HI); 2046 SDValue Hi = DAG.getNode(MipsISD::TlsHi, DL, PtrVT, TGAHi); 2047 SDValue TGALo = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, 2048 MipsII::MO_DTPREL_LO); 2049 SDValue Lo = DAG.getNode(MipsISD::Lo, DL, PtrVT, TGALo); 2050 SDValue Add = DAG.getNode(ISD::ADD, DL, PtrVT, Hi, Ret); 2051 return DAG.getNode(ISD::ADD, DL, PtrVT, Add, Lo); 2052 } 2053 2054 SDValue Offset; 2055 if (model == TLSModel::InitialExec) { 2056 // Initial Exec TLS Model 2057 SDValue TGA = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, 2058 MipsII::MO_GOTTPREL); 2059 TGA = DAG.getNode(MipsISD::Wrapper, DL, PtrVT, getGlobalReg(DAG, PtrVT), 2060 TGA); 2061 Offset = 2062 DAG.getLoad(PtrVT, DL, DAG.getEntryNode(), TGA, MachinePointerInfo()); 2063 } else { 2064 // Local Exec TLS Model 2065 assert(model == TLSModel::LocalExec); 2066 SDValue TGAHi = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, 2067 MipsII::MO_TPREL_HI); 2068 SDValue TGALo = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, 2069 MipsII::MO_TPREL_LO); 2070 SDValue Hi = DAG.getNode(MipsISD::TlsHi, DL, PtrVT, TGAHi); 2071 SDValue Lo = DAG.getNode(MipsISD::Lo, DL, PtrVT, TGALo); 2072 Offset = DAG.getNode(ISD::ADD, DL, PtrVT, Hi, Lo); 2073 } 2074 2075 SDValue ThreadPointer = DAG.getNode(MipsISD::ThreadPointer, DL, PtrVT); 2076 return DAG.getNode(ISD::ADD, DL, PtrVT, ThreadPointer, Offset); 2077 } 2078 2079 SDValue MipsTargetLowering:: 2080 lowerJumpTable(SDValue Op, SelectionDAG &DAG) const 2081 { 2082 JumpTableSDNode *N = cast<JumpTableSDNode>(Op); 2083 EVT Ty = Op.getValueType(); 2084 2085 if (!isPositionIndependent()) 2086 return Subtarget.hasSym32() ? getAddrNonPIC(N, SDLoc(N), Ty, DAG) 2087 : getAddrNonPICSym64(N, SDLoc(N), Ty, DAG); 2088 2089 return getAddrLocal(N, SDLoc(N), Ty, DAG, ABI.IsN32() || ABI.IsN64()); 2090 } 2091 2092 SDValue MipsTargetLowering:: 2093 lowerConstantPool(SDValue Op, SelectionDAG &DAG) const 2094 { 2095 ConstantPoolSDNode *N = cast<ConstantPoolSDNode>(Op); 2096 EVT Ty = Op.getValueType(); 2097 2098 if (!isPositionIndependent()) { 2099 const MipsTargetObjectFile *TLOF = 2100 static_cast<const MipsTargetObjectFile *>( 2101 getTargetMachine().getObjFileLowering()); 2102 2103 if (TLOF->IsConstantInSmallSection(DAG.getDataLayout(), N->getConstVal(), 2104 getTargetMachine())) 2105 // %gp_rel relocation 2106 return getAddrGPRel(N, SDLoc(N), Ty, DAG, ABI.IsN64()); 2107 2108 return Subtarget.hasSym32() ? getAddrNonPIC(N, SDLoc(N), Ty, DAG) 2109 : getAddrNonPICSym64(N, SDLoc(N), Ty, DAG); 2110 } 2111 2112 return getAddrLocal(N, SDLoc(N), Ty, DAG, ABI.IsN32() || ABI.IsN64()); 2113 } 2114 2115 SDValue MipsTargetLowering::lowerVASTART(SDValue Op, SelectionDAG &DAG) const { 2116 MachineFunction &MF = DAG.getMachineFunction(); 2117 MipsFunctionInfo *FuncInfo = MF.getInfo<MipsFunctionInfo>(); 2118 2119 SDLoc DL(Op); 2120 SDValue FI = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), 2121 getPointerTy(MF.getDataLayout())); 2122 2123 // vastart just stores the address of the VarArgsFrameIndex slot into the 2124 // memory location argument. 2125 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue(); 2126 return DAG.getStore(Op.getOperand(0), DL, FI, Op.getOperand(1), 2127 MachinePointerInfo(SV)); 2128 } 2129 2130 SDValue MipsTargetLowering::lowerVAARG(SDValue Op, SelectionDAG &DAG) const { 2131 SDNode *Node = Op.getNode(); 2132 EVT VT = Node->getValueType(0); 2133 SDValue Chain = Node->getOperand(0); 2134 SDValue VAListPtr = Node->getOperand(1); 2135 unsigned Align = Node->getConstantOperandVal(3); 2136 const Value *SV = cast<SrcValueSDNode>(Node->getOperand(2))->getValue(); 2137 SDLoc DL(Node); 2138 unsigned ArgSlotSizeInBytes = (ABI.IsN32() || ABI.IsN64()) ? 8 : 4; 2139 2140 SDValue VAListLoad = DAG.getLoad(getPointerTy(DAG.getDataLayout()), DL, Chain, 2141 VAListPtr, MachinePointerInfo(SV)); 2142 SDValue VAList = VAListLoad; 2143 2144 // Re-align the pointer if necessary. 2145 // It should only ever be necessary for 64-bit types on O32 since the minimum 2146 // argument alignment is the same as the maximum type alignment for N32/N64. 2147 // 2148 // FIXME: We currently align too often. The code generator doesn't notice 2149 // when the pointer is still aligned from the last va_arg (or pair of 2150 // va_args for the i64 on O32 case). 2151 if (Align > getMinStackArgumentAlignment()) { 2152 assert(((Align & (Align-1)) == 0) && "Expected Align to be a power of 2"); 2153 2154 VAList = DAG.getNode(ISD::ADD, DL, VAList.getValueType(), VAList, 2155 DAG.getConstant(Align - 1, DL, VAList.getValueType())); 2156 2157 VAList = DAG.getNode(ISD::AND, DL, VAList.getValueType(), VAList, 2158 DAG.getConstant(-(int64_t)Align, DL, 2159 VAList.getValueType())); 2160 } 2161 2162 // Increment the pointer, VAList, to the next vaarg. 2163 auto &TD = DAG.getDataLayout(); 2164 unsigned ArgSizeInBytes = 2165 TD.getTypeAllocSize(VT.getTypeForEVT(*DAG.getContext())); 2166 SDValue Tmp3 = 2167 DAG.getNode(ISD::ADD, DL, VAList.getValueType(), VAList, 2168 DAG.getConstant(alignTo(ArgSizeInBytes, ArgSlotSizeInBytes), 2169 DL, VAList.getValueType())); 2170 // Store the incremented VAList to the legalized pointer 2171 Chain = DAG.getStore(VAListLoad.getValue(1), DL, Tmp3, VAListPtr, 2172 MachinePointerInfo(SV)); 2173 2174 // In big-endian mode we must adjust the pointer when the load size is smaller 2175 // than the argument slot size. We must also reduce the known alignment to 2176 // match. For example in the N64 ABI, we must add 4 bytes to the offset to get 2177 // the correct half of the slot, and reduce the alignment from 8 (slot 2178 // alignment) down to 4 (type alignment). 2179 if (!Subtarget.isLittle() && ArgSizeInBytes < ArgSlotSizeInBytes) { 2180 unsigned Adjustment = ArgSlotSizeInBytes - ArgSizeInBytes; 2181 VAList = DAG.getNode(ISD::ADD, DL, VAListPtr.getValueType(), VAList, 2182 DAG.getIntPtrConstant(Adjustment, DL)); 2183 } 2184 // Load the actual argument out of the pointer VAList 2185 return DAG.getLoad(VT, DL, Chain, VAList, MachinePointerInfo()); 2186 } 2187 2188 static SDValue lowerFCOPYSIGN32(SDValue Op, SelectionDAG &DAG, 2189 bool HasExtractInsert) { 2190 EVT TyX = Op.getOperand(0).getValueType(); 2191 EVT TyY = Op.getOperand(1).getValueType(); 2192 SDLoc DL(Op); 2193 SDValue Const1 = DAG.getConstant(1, DL, MVT::i32); 2194 SDValue Const31 = DAG.getConstant(31, DL, MVT::i32); 2195 SDValue Res; 2196 2197 // If operand is of type f64, extract the upper 32-bit. Otherwise, bitcast it 2198 // to i32. 2199 SDValue X = (TyX == MVT::f32) ? 2200 DAG.getNode(ISD::BITCAST, DL, MVT::i32, Op.getOperand(0)) : 2201 DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32, Op.getOperand(0), 2202 Const1); 2203 SDValue Y = (TyY == MVT::f32) ? 2204 DAG.getNode(ISD::BITCAST, DL, MVT::i32, Op.getOperand(1)) : 2205 DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32, Op.getOperand(1), 2206 Const1); 2207 2208 if (HasExtractInsert) { 2209 // ext E, Y, 31, 1 ; extract bit31 of Y 2210 // ins X, E, 31, 1 ; insert extracted bit at bit31 of X 2211 SDValue E = DAG.getNode(MipsISD::Ext, DL, MVT::i32, Y, Const31, Const1); 2212 Res = DAG.getNode(MipsISD::Ins, DL, MVT::i32, E, Const31, Const1, X); 2213 } else { 2214 // sll SllX, X, 1 2215 // srl SrlX, SllX, 1 2216 // srl SrlY, Y, 31 2217 // sll SllY, SrlX, 31 2218 // or Or, SrlX, SllY 2219 SDValue SllX = DAG.getNode(ISD::SHL, DL, MVT::i32, X, Const1); 2220 SDValue SrlX = DAG.getNode(ISD::SRL, DL, MVT::i32, SllX, Const1); 2221 SDValue SrlY = DAG.getNode(ISD::SRL, DL, MVT::i32, Y, Const31); 2222 SDValue SllY = DAG.getNode(ISD::SHL, DL, MVT::i32, SrlY, Const31); 2223 Res = DAG.getNode(ISD::OR, DL, MVT::i32, SrlX, SllY); 2224 } 2225 2226 if (TyX == MVT::f32) 2227 return DAG.getNode(ISD::BITCAST, DL, Op.getOperand(0).getValueType(), Res); 2228 2229 SDValue LowX = DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32, 2230 Op.getOperand(0), 2231 DAG.getConstant(0, DL, MVT::i32)); 2232 return DAG.getNode(MipsISD::BuildPairF64, DL, MVT::f64, LowX, Res); 2233 } 2234 2235 static SDValue lowerFCOPYSIGN64(SDValue Op, SelectionDAG &DAG, 2236 bool HasExtractInsert) { 2237 unsigned WidthX = Op.getOperand(0).getValueSizeInBits(); 2238 unsigned WidthY = Op.getOperand(1).getValueSizeInBits(); 2239 EVT TyX = MVT::getIntegerVT(WidthX), TyY = MVT::getIntegerVT(WidthY); 2240 SDLoc DL(Op); 2241 SDValue Const1 = DAG.getConstant(1, DL, MVT::i32); 2242 2243 // Bitcast to integer nodes. 2244 SDValue X = DAG.getNode(ISD::BITCAST, DL, TyX, Op.getOperand(0)); 2245 SDValue Y = DAG.getNode(ISD::BITCAST, DL, TyY, Op.getOperand(1)); 2246 2247 if (HasExtractInsert) { 2248 // ext E, Y, width(Y) - 1, 1 ; extract bit width(Y)-1 of Y 2249 // ins X, E, width(X) - 1, 1 ; insert extracted bit at bit width(X)-1 of X 2250 SDValue E = DAG.getNode(MipsISD::Ext, DL, TyY, Y, 2251 DAG.getConstant(WidthY - 1, DL, MVT::i32), Const1); 2252 2253 if (WidthX > WidthY) 2254 E = DAG.getNode(ISD::ZERO_EXTEND, DL, TyX, E); 2255 else if (WidthY > WidthX) 2256 E = DAG.getNode(ISD::TRUNCATE, DL, TyX, E); 2257 2258 SDValue I = DAG.getNode(MipsISD::Ins, DL, TyX, E, 2259 DAG.getConstant(WidthX - 1, DL, MVT::i32), Const1, 2260 X); 2261 return DAG.getNode(ISD::BITCAST, DL, Op.getOperand(0).getValueType(), I); 2262 } 2263 2264 // (d)sll SllX, X, 1 2265 // (d)srl SrlX, SllX, 1 2266 // (d)srl SrlY, Y, width(Y)-1 2267 // (d)sll SllY, SrlX, width(Y)-1 2268 // or Or, SrlX, SllY 2269 SDValue SllX = DAG.getNode(ISD::SHL, DL, TyX, X, Const1); 2270 SDValue SrlX = DAG.getNode(ISD::SRL, DL, TyX, SllX, Const1); 2271 SDValue SrlY = DAG.getNode(ISD::SRL, DL, TyY, Y, 2272 DAG.getConstant(WidthY - 1, DL, MVT::i32)); 2273 2274 if (WidthX > WidthY) 2275 SrlY = DAG.getNode(ISD::ZERO_EXTEND, DL, TyX, SrlY); 2276 else if (WidthY > WidthX) 2277 SrlY = DAG.getNode(ISD::TRUNCATE, DL, TyX, SrlY); 2278 2279 SDValue SllY = DAG.getNode(ISD::SHL, DL, TyX, SrlY, 2280 DAG.getConstant(WidthX - 1, DL, MVT::i32)); 2281 SDValue Or = DAG.getNode(ISD::OR, DL, TyX, SrlX, SllY); 2282 return DAG.getNode(ISD::BITCAST, DL, Op.getOperand(0).getValueType(), Or); 2283 } 2284 2285 SDValue 2286 MipsTargetLowering::lowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const { 2287 if (Subtarget.isGP64bit()) 2288 return lowerFCOPYSIGN64(Op, DAG, Subtarget.hasExtractInsert()); 2289 2290 return lowerFCOPYSIGN32(Op, DAG, Subtarget.hasExtractInsert()); 2291 } 2292 2293 SDValue MipsTargetLowering:: 2294 lowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const { 2295 // check the depth 2296 assert((cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue() == 0) && 2297 "Frame address can only be determined for current frame."); 2298 2299 MachineFrameInfo &MFI = DAG.getMachineFunction().getFrameInfo(); 2300 MFI.setFrameAddressIsTaken(true); 2301 EVT VT = Op.getValueType(); 2302 SDLoc DL(Op); 2303 SDValue FrameAddr = DAG.getCopyFromReg( 2304 DAG.getEntryNode(), DL, ABI.IsN64() ? Mips::FP_64 : Mips::FP, VT); 2305 return FrameAddr; 2306 } 2307 2308 SDValue MipsTargetLowering::lowerRETURNADDR(SDValue Op, 2309 SelectionDAG &DAG) const { 2310 if (verifyReturnAddressArgumentIsConstant(Op, DAG)) 2311 return SDValue(); 2312 2313 // check the depth 2314 assert((cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue() == 0) && 2315 "Return address can be determined only for current frame."); 2316 2317 MachineFunction &MF = DAG.getMachineFunction(); 2318 MachineFrameInfo &MFI = MF.getFrameInfo(); 2319 MVT VT = Op.getSimpleValueType(); 2320 unsigned RA = ABI.IsN64() ? Mips::RA_64 : Mips::RA; 2321 MFI.setReturnAddressIsTaken(true); 2322 2323 // Return RA, which contains the return address. Mark it an implicit live-in. 2324 unsigned Reg = MF.addLiveIn(RA, getRegClassFor(VT)); 2325 return DAG.getCopyFromReg(DAG.getEntryNode(), SDLoc(Op), Reg, VT); 2326 } 2327 2328 // An EH_RETURN is the result of lowering llvm.eh.return which in turn is 2329 // generated from __builtin_eh_return (offset, handler) 2330 // The effect of this is to adjust the stack pointer by "offset" 2331 // and then branch to "handler". 2332 SDValue MipsTargetLowering::lowerEH_RETURN(SDValue Op, SelectionDAG &DAG) 2333 const { 2334 MachineFunction &MF = DAG.getMachineFunction(); 2335 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>(); 2336 2337 MipsFI->setCallsEhReturn(); 2338 SDValue Chain = Op.getOperand(0); 2339 SDValue Offset = Op.getOperand(1); 2340 SDValue Handler = Op.getOperand(2); 2341 SDLoc DL(Op); 2342 EVT Ty = ABI.IsN64() ? MVT::i64 : MVT::i32; 2343 2344 // Store stack offset in V1, store jump target in V0. Glue CopyToReg and 2345 // EH_RETURN nodes, so that instructions are emitted back-to-back. 2346 unsigned OffsetReg = ABI.IsN64() ? Mips::V1_64 : Mips::V1; 2347 unsigned AddrReg = ABI.IsN64() ? Mips::V0_64 : Mips::V0; 2348 Chain = DAG.getCopyToReg(Chain, DL, OffsetReg, Offset, SDValue()); 2349 Chain = DAG.getCopyToReg(Chain, DL, AddrReg, Handler, Chain.getValue(1)); 2350 return DAG.getNode(MipsISD::EH_RETURN, DL, MVT::Other, Chain, 2351 DAG.getRegister(OffsetReg, Ty), 2352 DAG.getRegister(AddrReg, getPointerTy(MF.getDataLayout())), 2353 Chain.getValue(1)); 2354 } 2355 2356 SDValue MipsTargetLowering::lowerATOMIC_FENCE(SDValue Op, 2357 SelectionDAG &DAG) const { 2358 // FIXME: Need pseudo-fence for 'singlethread' fences 2359 // FIXME: Set SType for weaker fences where supported/appropriate. 2360 unsigned SType = 0; 2361 SDLoc DL(Op); 2362 return DAG.getNode(MipsISD::Sync, DL, MVT::Other, Op.getOperand(0), 2363 DAG.getConstant(SType, DL, MVT::i32)); 2364 } 2365 2366 SDValue MipsTargetLowering::lowerShiftLeftParts(SDValue Op, 2367 SelectionDAG &DAG) const { 2368 SDLoc DL(Op); 2369 MVT VT = Subtarget.isGP64bit() ? MVT::i64 : MVT::i32; 2370 2371 SDValue Lo = Op.getOperand(0), Hi = Op.getOperand(1); 2372 SDValue Shamt = Op.getOperand(2); 2373 // if shamt < (VT.bits): 2374 // lo = (shl lo, shamt) 2375 // hi = (or (shl hi, shamt) (srl (srl lo, 1), ~shamt)) 2376 // else: 2377 // lo = 0 2378 // hi = (shl lo, shamt[4:0]) 2379 SDValue Not = DAG.getNode(ISD::XOR, DL, MVT::i32, Shamt, 2380 DAG.getConstant(-1, DL, MVT::i32)); 2381 SDValue ShiftRight1Lo = DAG.getNode(ISD::SRL, DL, VT, Lo, 2382 DAG.getConstant(1, DL, VT)); 2383 SDValue ShiftRightLo = DAG.getNode(ISD::SRL, DL, VT, ShiftRight1Lo, Not); 2384 SDValue ShiftLeftHi = DAG.getNode(ISD::SHL, DL, VT, Hi, Shamt); 2385 SDValue Or = DAG.getNode(ISD::OR, DL, VT, ShiftLeftHi, ShiftRightLo); 2386 SDValue ShiftLeftLo = DAG.getNode(ISD::SHL, DL, VT, Lo, Shamt); 2387 SDValue Cond = DAG.getNode(ISD::AND, DL, MVT::i32, Shamt, 2388 DAG.getConstant(VT.getSizeInBits(), DL, MVT::i32)); 2389 Lo = DAG.getNode(ISD::SELECT, DL, VT, Cond, 2390 DAG.getConstant(0, DL, VT), ShiftLeftLo); 2391 Hi = DAG.getNode(ISD::SELECT, DL, VT, Cond, ShiftLeftLo, Or); 2392 2393 SDValue Ops[2] = {Lo, Hi}; 2394 return DAG.getMergeValues(Ops, DL); 2395 } 2396 2397 SDValue MipsTargetLowering::lowerShiftRightParts(SDValue Op, SelectionDAG &DAG, 2398 bool IsSRA) const { 2399 SDLoc DL(Op); 2400 SDValue Lo = Op.getOperand(0), Hi = Op.getOperand(1); 2401 SDValue Shamt = Op.getOperand(2); 2402 MVT VT = Subtarget.isGP64bit() ? MVT::i64 : MVT::i32; 2403 2404 // if shamt < (VT.bits): 2405 // lo = (or (shl (shl hi, 1), ~shamt) (srl lo, shamt)) 2406 // if isSRA: 2407 // hi = (sra hi, shamt) 2408 // else: 2409 // hi = (srl hi, shamt) 2410 // else: 2411 // if isSRA: 2412 // lo = (sra hi, shamt[4:0]) 2413 // hi = (sra hi, 31) 2414 // else: 2415 // lo = (srl hi, shamt[4:0]) 2416 // hi = 0 2417 SDValue Not = DAG.getNode(ISD::XOR, DL, MVT::i32, Shamt, 2418 DAG.getConstant(-1, DL, MVT::i32)); 2419 SDValue ShiftLeft1Hi = DAG.getNode(ISD::SHL, DL, VT, Hi, 2420 DAG.getConstant(1, DL, VT)); 2421 SDValue ShiftLeftHi = DAG.getNode(ISD::SHL, DL, VT, ShiftLeft1Hi, Not); 2422 SDValue ShiftRightLo = DAG.getNode(ISD::SRL, DL, VT, Lo, Shamt); 2423 SDValue Or = DAG.getNode(ISD::OR, DL, VT, ShiftLeftHi, ShiftRightLo); 2424 SDValue ShiftRightHi = DAG.getNode(IsSRA ? ISD::SRA : ISD::SRL, 2425 DL, VT, Hi, Shamt); 2426 SDValue Cond = DAG.getNode(ISD::AND, DL, MVT::i32, Shamt, 2427 DAG.getConstant(VT.getSizeInBits(), DL, MVT::i32)); 2428 SDValue Ext = DAG.getNode(ISD::SRA, DL, VT, Hi, 2429 DAG.getConstant(VT.getSizeInBits() - 1, DL, VT)); 2430 Lo = DAG.getNode(ISD::SELECT, DL, VT, Cond, ShiftRightHi, Or); 2431 Hi = DAG.getNode(ISD::SELECT, DL, VT, Cond, 2432 IsSRA ? Ext : DAG.getConstant(0, DL, VT), ShiftRightHi); 2433 2434 SDValue Ops[2] = {Lo, Hi}; 2435 return DAG.getMergeValues(Ops, DL); 2436 } 2437 2438 static SDValue createLoadLR(unsigned Opc, SelectionDAG &DAG, LoadSDNode *LD, 2439 SDValue Chain, SDValue Src, unsigned Offset) { 2440 SDValue Ptr = LD->getBasePtr(); 2441 EVT VT = LD->getValueType(0), MemVT = LD->getMemoryVT(); 2442 EVT BasePtrVT = Ptr.getValueType(); 2443 SDLoc DL(LD); 2444 SDVTList VTList = DAG.getVTList(VT, MVT::Other); 2445 2446 if (Offset) 2447 Ptr = DAG.getNode(ISD::ADD, DL, BasePtrVT, Ptr, 2448 DAG.getConstant(Offset, DL, BasePtrVT)); 2449 2450 SDValue Ops[] = { Chain, Ptr, Src }; 2451 return DAG.getMemIntrinsicNode(Opc, DL, VTList, Ops, MemVT, 2452 LD->getMemOperand()); 2453 } 2454 2455 // Expand an unaligned 32 or 64-bit integer load node. 2456 SDValue MipsTargetLowering::lowerLOAD(SDValue Op, SelectionDAG &DAG) const { 2457 LoadSDNode *LD = cast<LoadSDNode>(Op); 2458 EVT MemVT = LD->getMemoryVT(); 2459 2460 if (Subtarget.systemSupportsUnalignedAccess()) 2461 return Op; 2462 2463 // Return if load is aligned or if MemVT is neither i32 nor i64. 2464 if ((LD->getAlignment() >= MemVT.getSizeInBits() / 8) || 2465 ((MemVT != MVT::i32) && (MemVT != MVT::i64))) 2466 return SDValue(); 2467 2468 bool IsLittle = Subtarget.isLittle(); 2469 EVT VT = Op.getValueType(); 2470 ISD::LoadExtType ExtType = LD->getExtensionType(); 2471 SDValue Chain = LD->getChain(), Undef = DAG.getUNDEF(VT); 2472 2473 assert((VT == MVT::i32) || (VT == MVT::i64)); 2474 2475 // Expand 2476 // (set dst, (i64 (load baseptr))) 2477 // to 2478 // (set tmp, (ldl (add baseptr, 7), undef)) 2479 // (set dst, (ldr baseptr, tmp)) 2480 if ((VT == MVT::i64) && (ExtType == ISD::NON_EXTLOAD)) { 2481 SDValue LDL = createLoadLR(MipsISD::LDL, DAG, LD, Chain, Undef, 2482 IsLittle ? 7 : 0); 2483 return createLoadLR(MipsISD::LDR, DAG, LD, LDL.getValue(1), LDL, 2484 IsLittle ? 0 : 7); 2485 } 2486 2487 SDValue LWL = createLoadLR(MipsISD::LWL, DAG, LD, Chain, Undef, 2488 IsLittle ? 3 : 0); 2489 SDValue LWR = createLoadLR(MipsISD::LWR, DAG, LD, LWL.getValue(1), LWL, 2490 IsLittle ? 0 : 3); 2491 2492 // Expand 2493 // (set dst, (i32 (load baseptr))) or 2494 // (set dst, (i64 (sextload baseptr))) or 2495 // (set dst, (i64 (extload baseptr))) 2496 // to 2497 // (set tmp, (lwl (add baseptr, 3), undef)) 2498 // (set dst, (lwr baseptr, tmp)) 2499 if ((VT == MVT::i32) || (ExtType == ISD::SEXTLOAD) || 2500 (ExtType == ISD::EXTLOAD)) 2501 return LWR; 2502 2503 assert((VT == MVT::i64) && (ExtType == ISD::ZEXTLOAD)); 2504 2505 // Expand 2506 // (set dst, (i64 (zextload baseptr))) 2507 // to 2508 // (set tmp0, (lwl (add baseptr, 3), undef)) 2509 // (set tmp1, (lwr baseptr, tmp0)) 2510 // (set tmp2, (shl tmp1, 32)) 2511 // (set dst, (srl tmp2, 32)) 2512 SDLoc DL(LD); 2513 SDValue Const32 = DAG.getConstant(32, DL, MVT::i32); 2514 SDValue SLL = DAG.getNode(ISD::SHL, DL, MVT::i64, LWR, Const32); 2515 SDValue SRL = DAG.getNode(ISD::SRL, DL, MVT::i64, SLL, Const32); 2516 SDValue Ops[] = { SRL, LWR.getValue(1) }; 2517 return DAG.getMergeValues(Ops, DL); 2518 } 2519 2520 static SDValue createStoreLR(unsigned Opc, SelectionDAG &DAG, StoreSDNode *SD, 2521 SDValue Chain, unsigned Offset) { 2522 SDValue Ptr = SD->getBasePtr(), Value = SD->getValue(); 2523 EVT MemVT = SD->getMemoryVT(), BasePtrVT = Ptr.getValueType(); 2524 SDLoc DL(SD); 2525 SDVTList VTList = DAG.getVTList(MVT::Other); 2526 2527 if (Offset) 2528 Ptr = DAG.getNode(ISD::ADD, DL, BasePtrVT, Ptr, 2529 DAG.getConstant(Offset, DL, BasePtrVT)); 2530 2531 SDValue Ops[] = { Chain, Value, Ptr }; 2532 return DAG.getMemIntrinsicNode(Opc, DL, VTList, Ops, MemVT, 2533 SD->getMemOperand()); 2534 } 2535 2536 // Expand an unaligned 32 or 64-bit integer store node. 2537 static SDValue lowerUnalignedIntStore(StoreSDNode *SD, SelectionDAG &DAG, 2538 bool IsLittle) { 2539 SDValue Value = SD->getValue(), Chain = SD->getChain(); 2540 EVT VT = Value.getValueType(); 2541 2542 // Expand 2543 // (store val, baseptr) or 2544 // (truncstore val, baseptr) 2545 // to 2546 // (swl val, (add baseptr, 3)) 2547 // (swr val, baseptr) 2548 if ((VT == MVT::i32) || SD->isTruncatingStore()) { 2549 SDValue SWL = createStoreLR(MipsISD::SWL, DAG, SD, Chain, 2550 IsLittle ? 3 : 0); 2551 return createStoreLR(MipsISD::SWR, DAG, SD, SWL, IsLittle ? 0 : 3); 2552 } 2553 2554 assert(VT == MVT::i64); 2555 2556 // Expand 2557 // (store val, baseptr) 2558 // to 2559 // (sdl val, (add baseptr, 7)) 2560 // (sdr val, baseptr) 2561 SDValue SDL = createStoreLR(MipsISD::SDL, DAG, SD, Chain, IsLittle ? 7 : 0); 2562 return createStoreLR(MipsISD::SDR, DAG, SD, SDL, IsLittle ? 0 : 7); 2563 } 2564 2565 // Lower (store (fp_to_sint $fp) $ptr) to (store (TruncIntFP $fp), $ptr). 2566 static SDValue lowerFP_TO_SINT_STORE(StoreSDNode *SD, SelectionDAG &DAG) { 2567 SDValue Val = SD->getValue(); 2568 2569 if (Val.getOpcode() != ISD::FP_TO_SINT) 2570 return SDValue(); 2571 2572 EVT FPTy = EVT::getFloatingPointVT(Val.getValueSizeInBits()); 2573 SDValue Tr = DAG.getNode(MipsISD::TruncIntFP, SDLoc(Val), FPTy, 2574 Val.getOperand(0)); 2575 return DAG.getStore(SD->getChain(), SDLoc(SD), Tr, SD->getBasePtr(), 2576 SD->getPointerInfo(), SD->getAlignment(), 2577 SD->getMemOperand()->getFlags()); 2578 } 2579 2580 SDValue MipsTargetLowering::lowerSTORE(SDValue Op, SelectionDAG &DAG) const { 2581 StoreSDNode *SD = cast<StoreSDNode>(Op); 2582 EVT MemVT = SD->getMemoryVT(); 2583 2584 // Lower unaligned integer stores. 2585 if (!Subtarget.systemSupportsUnalignedAccess() && 2586 (SD->getAlignment() < MemVT.getSizeInBits() / 8) && 2587 ((MemVT == MVT::i32) || (MemVT == MVT::i64))) 2588 return lowerUnalignedIntStore(SD, DAG, Subtarget.isLittle()); 2589 2590 return lowerFP_TO_SINT_STORE(SD, DAG); 2591 } 2592 2593 SDValue MipsTargetLowering::lowerEH_DWARF_CFA(SDValue Op, 2594 SelectionDAG &DAG) const { 2595 2596 // Return a fixed StackObject with offset 0 which points to the old stack 2597 // pointer. 2598 MachineFrameInfo &MFI = DAG.getMachineFunction().getFrameInfo(); 2599 EVT ValTy = Op->getValueType(0); 2600 int FI = MFI.CreateFixedObject(Op.getValueSizeInBits() / 8, 0, false); 2601 return DAG.getFrameIndex(FI, ValTy); 2602 } 2603 2604 SDValue MipsTargetLowering::lowerFP_TO_SINT(SDValue Op, 2605 SelectionDAG &DAG) const { 2606 EVT FPTy = EVT::getFloatingPointVT(Op.getValueSizeInBits()); 2607 SDValue Trunc = DAG.getNode(MipsISD::TruncIntFP, SDLoc(Op), FPTy, 2608 Op.getOperand(0)); 2609 return DAG.getNode(ISD::BITCAST, SDLoc(Op), Op.getValueType(), Trunc); 2610 } 2611 2612 //===----------------------------------------------------------------------===// 2613 // Calling Convention Implementation 2614 //===----------------------------------------------------------------------===// 2615 2616 //===----------------------------------------------------------------------===// 2617 // TODO: Implement a generic logic using tblgen that can support this. 2618 // Mips O32 ABI rules: 2619 // --- 2620 // i32 - Passed in A0, A1, A2, A3 and stack 2621 // f32 - Only passed in f32 registers if no int reg has been used yet to hold 2622 // an argument. Otherwise, passed in A1, A2, A3 and stack. 2623 // f64 - Only passed in two aliased f32 registers if no int reg has been used 2624 // yet to hold an argument. Otherwise, use A2, A3 and stack. If A1 is 2625 // not used, it must be shadowed. If only A3 is available, shadow it and 2626 // go to stack. 2627 // vXiX - Received as scalarized i32s, passed in A0 - A3 and the stack. 2628 // vXf32 - Passed in either a pair of registers {A0, A1}, {A2, A3} or {A0 - A3} 2629 // with the remainder spilled to the stack. 2630 // vXf64 - Passed in either {A0, A1, A2, A3} or {A2, A3} and in both cases 2631 // spilling the remainder to the stack. 2632 // 2633 // For vararg functions, all arguments are passed in A0, A1, A2, A3 and stack. 2634 //===----------------------------------------------------------------------===// 2635 2636 static bool CC_MipsO32(unsigned ValNo, MVT ValVT, MVT LocVT, 2637 CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, 2638 CCState &State, ArrayRef<MCPhysReg> F64Regs) { 2639 const MipsSubtarget &Subtarget = static_cast<const MipsSubtarget &>( 2640 State.getMachineFunction().getSubtarget()); 2641 2642 static const MCPhysReg IntRegs[] = { Mips::A0, Mips::A1, Mips::A2, Mips::A3 }; 2643 2644 const MipsCCState * MipsState = static_cast<MipsCCState *>(&State); 2645 2646 static const MCPhysReg F32Regs[] = { Mips::F12, Mips::F14 }; 2647 2648 static const MCPhysReg FloatVectorIntRegs[] = { Mips::A0, Mips::A2 }; 2649 2650 // Do not process byval args here. 2651 if (ArgFlags.isByVal()) 2652 return true; 2653 2654 // Promote i8 and i16 2655 if (ArgFlags.isInReg() && !Subtarget.isLittle()) { 2656 if (LocVT == MVT::i8 || LocVT == MVT::i16 || LocVT == MVT::i32) { 2657 LocVT = MVT::i32; 2658 if (ArgFlags.isSExt()) 2659 LocInfo = CCValAssign::SExtUpper; 2660 else if (ArgFlags.isZExt()) 2661 LocInfo = CCValAssign::ZExtUpper; 2662 else 2663 LocInfo = CCValAssign::AExtUpper; 2664 } 2665 } 2666 2667 // Promote i8 and i16 2668 if (LocVT == MVT::i8 || LocVT == MVT::i16) { 2669 LocVT = MVT::i32; 2670 if (ArgFlags.isSExt()) 2671 LocInfo = CCValAssign::SExt; 2672 else if (ArgFlags.isZExt()) 2673 LocInfo = CCValAssign::ZExt; 2674 else 2675 LocInfo = CCValAssign::AExt; 2676 } 2677 2678 unsigned Reg; 2679 2680 // f32 and f64 are allocated in A0, A1, A2, A3 when either of the following 2681 // is true: function is vararg, argument is 3rd or higher, there is previous 2682 // argument which is not f32 or f64. 2683 bool AllocateFloatsInIntReg = State.isVarArg() || ValNo > 1 || 2684 State.getFirstUnallocated(F32Regs) != ValNo; 2685 unsigned OrigAlign = ArgFlags.getOrigAlign(); 2686 bool isI64 = (ValVT == MVT::i32 && OrigAlign == 8); 2687 bool isVectorFloat = MipsState->WasOriginalArgVectorFloat(ValNo); 2688 2689 // The MIPS vector ABI for floats passes them in a pair of registers 2690 if (ValVT == MVT::i32 && isVectorFloat) { 2691 // This is the start of an vector that was scalarized into an unknown number 2692 // of components. It doesn't matter how many there are. Allocate one of the 2693 // notional 8 byte aligned registers which map onto the argument stack, and 2694 // shadow the register lost to alignment requirements. 2695 if (ArgFlags.isSplit()) { 2696 Reg = State.AllocateReg(FloatVectorIntRegs); 2697 if (Reg == Mips::A2) 2698 State.AllocateReg(Mips::A1); 2699 else if (Reg == 0) 2700 State.AllocateReg(Mips::A3); 2701 } else { 2702 // If we're an intermediate component of the split, we can just attempt to 2703 // allocate a register directly. 2704 Reg = State.AllocateReg(IntRegs); 2705 } 2706 } else if (ValVT == MVT::i32 || (ValVT == MVT::f32 && AllocateFloatsInIntReg)) { 2707 Reg = State.AllocateReg(IntRegs); 2708 // If this is the first part of an i64 arg, 2709 // the allocated register must be either A0 or A2. 2710 if (isI64 && (Reg == Mips::A1 || Reg == Mips::A3)) 2711 Reg = State.AllocateReg(IntRegs); 2712 LocVT = MVT::i32; 2713 } else if (ValVT == MVT::f64 && AllocateFloatsInIntReg) { 2714 // Allocate int register and shadow next int register. If first 2715 // available register is Mips::A1 or Mips::A3, shadow it too. 2716 Reg = State.AllocateReg(IntRegs); 2717 if (Reg == Mips::A1 || Reg == Mips::A3) 2718 Reg = State.AllocateReg(IntRegs); 2719 State.AllocateReg(IntRegs); 2720 LocVT = MVT::i32; 2721 } else if (ValVT.isFloatingPoint() && !AllocateFloatsInIntReg) { 2722 // we are guaranteed to find an available float register 2723 if (ValVT == MVT::f32) { 2724 Reg = State.AllocateReg(F32Regs); 2725 // Shadow int register 2726 State.AllocateReg(IntRegs); 2727 } else { 2728 Reg = State.AllocateReg(F64Regs); 2729 // Shadow int registers 2730 unsigned Reg2 = State.AllocateReg(IntRegs); 2731 if (Reg2 == Mips::A1 || Reg2 == Mips::A3) 2732 State.AllocateReg(IntRegs); 2733 State.AllocateReg(IntRegs); 2734 } 2735 } else 2736 llvm_unreachable("Cannot handle this ValVT."); 2737 2738 if (!Reg) { 2739 unsigned Offset = State.AllocateStack(ValVT.getStoreSize(), OrigAlign); 2740 State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo)); 2741 } else 2742 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); 2743 2744 return false; 2745 } 2746 2747 static bool CC_MipsO32_FP32(unsigned ValNo, MVT ValVT, 2748 MVT LocVT, CCValAssign::LocInfo LocInfo, 2749 ISD::ArgFlagsTy ArgFlags, CCState &State) { 2750 static const MCPhysReg F64Regs[] = { Mips::D6, Mips::D7 }; 2751 2752 return CC_MipsO32(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State, F64Regs); 2753 } 2754 2755 static bool CC_MipsO32_FP64(unsigned ValNo, MVT ValVT, 2756 MVT LocVT, CCValAssign::LocInfo LocInfo, 2757 ISD::ArgFlagsTy ArgFlags, CCState &State) { 2758 static const MCPhysReg F64Regs[] = { Mips::D12_64, Mips::D14_64 }; 2759 2760 return CC_MipsO32(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State, F64Regs); 2761 } 2762 2763 static bool CC_MipsO32(unsigned ValNo, MVT ValVT, MVT LocVT, 2764 CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, 2765 CCState &State) LLVM_ATTRIBUTE_UNUSED; 2766 2767 #include "MipsGenCallingConv.inc" 2768 2769 CCAssignFn *MipsTargetLowering::CCAssignFnForCall() const{ 2770 return CC_Mips; 2771 } 2772 2773 CCAssignFn *MipsTargetLowering::CCAssignFnForReturn() const{ 2774 return RetCC_Mips; 2775 } 2776 //===----------------------------------------------------------------------===// 2777 // Call Calling Convention Implementation 2778 //===----------------------------------------------------------------------===// 2779 2780 // Return next O32 integer argument register. 2781 static unsigned getNextIntArgReg(unsigned Reg) { 2782 assert((Reg == Mips::A0) || (Reg == Mips::A2)); 2783 return (Reg == Mips::A0) ? Mips::A1 : Mips::A3; 2784 } 2785 2786 SDValue MipsTargetLowering::passArgOnStack(SDValue StackPtr, unsigned Offset, 2787 SDValue Chain, SDValue Arg, 2788 const SDLoc &DL, bool IsTailCall, 2789 SelectionDAG &DAG) const { 2790 if (!IsTailCall) { 2791 SDValue PtrOff = 2792 DAG.getNode(ISD::ADD, DL, getPointerTy(DAG.getDataLayout()), StackPtr, 2793 DAG.getIntPtrConstant(Offset, DL)); 2794 return DAG.getStore(Chain, DL, Arg, PtrOff, MachinePointerInfo()); 2795 } 2796 2797 MachineFrameInfo &MFI = DAG.getMachineFunction().getFrameInfo(); 2798 int FI = MFI.CreateFixedObject(Arg.getValueSizeInBits() / 8, Offset, false); 2799 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy(DAG.getDataLayout())); 2800 return DAG.getStore(Chain, DL, Arg, FIN, MachinePointerInfo(), 2801 /* Alignment = */ 0, MachineMemOperand::MOVolatile); 2802 } 2803 2804 void MipsTargetLowering:: 2805 getOpndList(SmallVectorImpl<SDValue> &Ops, 2806 std::deque<std::pair<unsigned, SDValue>> &RegsToPass, 2807 bool IsPICCall, bool GlobalOrExternal, bool InternalLinkage, 2808 bool IsCallReloc, CallLoweringInfo &CLI, SDValue Callee, 2809 SDValue Chain) const { 2810 // Insert node "GP copy globalreg" before call to function. 2811 // 2812 // R_MIPS_CALL* operators (emitted when non-internal functions are called 2813 // in PIC mode) allow symbols to be resolved via lazy binding. 2814 // The lazy binding stub requires GP to point to the GOT. 2815 // Note that we don't need GP to point to the GOT for indirect calls 2816 // (when R_MIPS_CALL* is not used for the call) because Mips linker generates 2817 // lazy binding stub for a function only when R_MIPS_CALL* are the only relocs 2818 // used for the function (that is, Mips linker doesn't generate lazy binding 2819 // stub for a function whose address is taken in the program). 2820 if (IsPICCall && !InternalLinkage && IsCallReloc) { 2821 unsigned GPReg = ABI.IsN64() ? Mips::GP_64 : Mips::GP; 2822 EVT Ty = ABI.IsN64() ? MVT::i64 : MVT::i32; 2823 RegsToPass.push_back(std::make_pair(GPReg, getGlobalReg(CLI.DAG, Ty))); 2824 } 2825 2826 // Build a sequence of copy-to-reg nodes chained together with token 2827 // chain and flag operands which copy the outgoing args into registers. 2828 // The InFlag in necessary since all emitted instructions must be 2829 // stuck together. 2830 SDValue InFlag; 2831 2832 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) { 2833 Chain = CLI.DAG.getCopyToReg(Chain, CLI.DL, RegsToPass[i].first, 2834 RegsToPass[i].second, InFlag); 2835 InFlag = Chain.getValue(1); 2836 } 2837 2838 // Add argument registers to the end of the list so that they are 2839 // known live into the call. 2840 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) 2841 Ops.push_back(CLI.DAG.getRegister(RegsToPass[i].first, 2842 RegsToPass[i].second.getValueType())); 2843 2844 // Add a register mask operand representing the call-preserved registers. 2845 const TargetRegisterInfo *TRI = Subtarget.getRegisterInfo(); 2846 const uint32_t *Mask = 2847 TRI->getCallPreservedMask(CLI.DAG.getMachineFunction(), CLI.CallConv); 2848 assert(Mask && "Missing call preserved mask for calling convention"); 2849 if (Subtarget.inMips16HardFloat()) { 2850 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(CLI.Callee)) { 2851 StringRef Sym = G->getGlobal()->getName(); 2852 Function *F = G->getGlobal()->getParent()->getFunction(Sym); 2853 if (F && F->hasFnAttribute("__Mips16RetHelper")) { 2854 Mask = MipsRegisterInfo::getMips16RetHelperMask(); 2855 } 2856 } 2857 } 2858 Ops.push_back(CLI.DAG.getRegisterMask(Mask)); 2859 2860 if (InFlag.getNode()) 2861 Ops.push_back(InFlag); 2862 } 2863 2864 /// LowerCall - functions arguments are copied from virtual regs to 2865 /// (physical regs)/(stack frame), CALLSEQ_START and CALLSEQ_END are emitted. 2866 SDValue 2867 MipsTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI, 2868 SmallVectorImpl<SDValue> &InVals) const { 2869 SelectionDAG &DAG = CLI.DAG; 2870 SDLoc DL = CLI.DL; 2871 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs; 2872 SmallVectorImpl<SDValue> &OutVals = CLI.OutVals; 2873 SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins; 2874 SDValue Chain = CLI.Chain; 2875 SDValue Callee = CLI.Callee; 2876 bool &IsTailCall = CLI.IsTailCall; 2877 CallingConv::ID CallConv = CLI.CallConv; 2878 bool IsVarArg = CLI.IsVarArg; 2879 2880 MachineFunction &MF = DAG.getMachineFunction(); 2881 MachineFrameInfo &MFI = MF.getFrameInfo(); 2882 const TargetFrameLowering *TFL = Subtarget.getFrameLowering(); 2883 MipsFunctionInfo *FuncInfo = MF.getInfo<MipsFunctionInfo>(); 2884 bool IsPIC = isPositionIndependent(); 2885 2886 // Analyze operands of the call, assigning locations to each operand. 2887 SmallVector<CCValAssign, 16> ArgLocs; 2888 MipsCCState CCInfo( 2889 CallConv, IsVarArg, DAG.getMachineFunction(), ArgLocs, *DAG.getContext(), 2890 MipsCCState::getSpecialCallingConvForCallee(Callee.getNode(), Subtarget)); 2891 2892 const ExternalSymbolSDNode *ES = 2893 dyn_cast_or_null<const ExternalSymbolSDNode>(Callee.getNode()); 2894 2895 // There is one case where CALLSEQ_START..CALLSEQ_END can be nested, which 2896 // is during the lowering of a call with a byval argument which produces 2897 // a call to memcpy. For the O32 case, this causes the caller to allocate 2898 // stack space for the reserved argument area for the callee, then recursively 2899 // again for the memcpy call. In the NEWABI case, this doesn't occur as those 2900 // ABIs mandate that the callee allocates the reserved argument area. We do 2901 // still produce nested CALLSEQ_START..CALLSEQ_END with zero space though. 2902 // 2903 // If the callee has a byval argument and memcpy is used, we are mandated 2904 // to already have produced a reserved argument area for the callee for O32. 2905 // Therefore, the reserved argument area can be reused for both calls. 2906 // 2907 // Other cases of calling memcpy cannot have a chain with a CALLSEQ_START 2908 // present, as we have yet to hook that node onto the chain. 2909 // 2910 // Hence, the CALLSEQ_START and CALLSEQ_END nodes can be eliminated in this 2911 // case. GCC does a similar trick, in that wherever possible, it calculates 2912 // the maximum out going argument area (including the reserved area), and 2913 // preallocates the stack space on entrance to the caller. 2914 // 2915 // FIXME: We should do the same for efficency and space. 2916 2917 // Note: The check on the calling convention below must match 2918 // MipsABIInfo::GetCalleeAllocdArgSizeInBytes(). 2919 bool MemcpyInByVal = ES && 2920 StringRef(ES->getSymbol()) == StringRef("memcpy") && 2921 CallConv != CallingConv::Fast && 2922 Chain.getOpcode() == ISD::CALLSEQ_START; 2923 2924 // Allocate the reserved argument area. It seems strange to do this from the 2925 // caller side but removing it breaks the frame size calculation. 2926 unsigned ReservedArgArea = 2927 MemcpyInByVal ? 0 : ABI.GetCalleeAllocdArgSizeInBytes(CallConv); 2928 CCInfo.AllocateStack(ReservedArgArea, 1); 2929 2930 CCInfo.AnalyzeCallOperands(Outs, CC_Mips, CLI.getArgs(), 2931 ES ? ES->getSymbol() : nullptr); 2932 2933 // Get a count of how many bytes are to be pushed on the stack. 2934 unsigned NextStackOffset = CCInfo.getNextStackOffset(); 2935 2936 // Check if it's really possible to do a tail call. Restrict it to functions 2937 // that are part of this compilation unit. 2938 bool InternalLinkage = false; 2939 if (IsTailCall) { 2940 IsTailCall = isEligibleForTailCallOptimization( 2941 CCInfo, NextStackOffset, *MF.getInfo<MipsFunctionInfo>()); 2942 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) { 2943 InternalLinkage = G->getGlobal()->hasInternalLinkage(); 2944 IsTailCall &= (InternalLinkage || G->getGlobal()->hasLocalLinkage() || 2945 G->getGlobal()->hasPrivateLinkage() || 2946 G->getGlobal()->hasHiddenVisibility() || 2947 G->getGlobal()->hasProtectedVisibility()); 2948 } 2949 } 2950 if (!IsTailCall && CLI.CS && CLI.CS.isMustTailCall()) 2951 report_fatal_error("failed to perform tail call elimination on a call " 2952 "site marked musttail"); 2953 2954 if (IsTailCall) 2955 ++NumTailCalls; 2956 2957 // Chain is the output chain of the last Load/Store or CopyToReg node. 2958 // ByValChain is the output chain of the last Memcpy node created for copying 2959 // byval arguments to the stack. 2960 unsigned StackAlignment = TFL->getStackAlignment(); 2961 NextStackOffset = alignTo(NextStackOffset, StackAlignment); 2962 SDValue NextStackOffsetVal = DAG.getIntPtrConstant(NextStackOffset, DL, true); 2963 2964 if (!(IsTailCall || MemcpyInByVal)) 2965 Chain = DAG.getCALLSEQ_START(Chain, NextStackOffset, 0, DL); 2966 2967 SDValue StackPtr = 2968 DAG.getCopyFromReg(Chain, DL, ABI.IsN64() ? Mips::SP_64 : Mips::SP, 2969 getPointerTy(DAG.getDataLayout())); 2970 2971 std::deque<std::pair<unsigned, SDValue>> RegsToPass; 2972 SmallVector<SDValue, 8> MemOpChains; 2973 2974 CCInfo.rewindByValRegsInfo(); 2975 2976 // Walk the register/memloc assignments, inserting copies/loads. 2977 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { 2978 SDValue Arg = OutVals[i]; 2979 CCValAssign &VA = ArgLocs[i]; 2980 MVT ValVT = VA.getValVT(), LocVT = VA.getLocVT(); 2981 ISD::ArgFlagsTy Flags = Outs[i].Flags; 2982 bool UseUpperBits = false; 2983 2984 // ByVal Arg. 2985 if (Flags.isByVal()) { 2986 unsigned FirstByValReg, LastByValReg; 2987 unsigned ByValIdx = CCInfo.getInRegsParamsProcessed(); 2988 CCInfo.getInRegsParamInfo(ByValIdx, FirstByValReg, LastByValReg); 2989 2990 assert(Flags.getByValSize() && 2991 "ByVal args of size 0 should have been ignored by front-end."); 2992 assert(ByValIdx < CCInfo.getInRegsParamsCount()); 2993 assert(!IsTailCall && 2994 "Do not tail-call optimize if there is a byval argument."); 2995 passByValArg(Chain, DL, RegsToPass, MemOpChains, StackPtr, MFI, DAG, Arg, 2996 FirstByValReg, LastByValReg, Flags, Subtarget.isLittle(), 2997 VA); 2998 CCInfo.nextInRegsParam(); 2999 continue; 3000 } 3001 3002 // Promote the value if needed. 3003 switch (VA.getLocInfo()) { 3004 default: 3005 llvm_unreachable("Unknown loc info!"); 3006 case CCValAssign::Full: 3007 if (VA.isRegLoc()) { 3008 if ((ValVT == MVT::f32 && LocVT == MVT::i32) || 3009 (ValVT == MVT::f64 && LocVT == MVT::i64) || 3010 (ValVT == MVT::i64 && LocVT == MVT::f64)) 3011 Arg = DAG.getNode(ISD::BITCAST, DL, LocVT, Arg); 3012 else if (ValVT == MVT::f64 && LocVT == MVT::i32) { 3013 SDValue Lo = DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32, 3014 Arg, DAG.getConstant(0, DL, MVT::i32)); 3015 SDValue Hi = DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32, 3016 Arg, DAG.getConstant(1, DL, MVT::i32)); 3017 if (!Subtarget.isLittle()) 3018 std::swap(Lo, Hi); 3019 unsigned LocRegLo = VA.getLocReg(); 3020 unsigned LocRegHigh = getNextIntArgReg(LocRegLo); 3021 RegsToPass.push_back(std::make_pair(LocRegLo, Lo)); 3022 RegsToPass.push_back(std::make_pair(LocRegHigh, Hi)); 3023 continue; 3024 } 3025 } 3026 break; 3027 case CCValAssign::BCvt: 3028 Arg = DAG.getNode(ISD::BITCAST, DL, LocVT, Arg); 3029 break; 3030 case CCValAssign::SExtUpper: 3031 UseUpperBits = true; 3032 LLVM_FALLTHROUGH; 3033 case CCValAssign::SExt: 3034 Arg = DAG.getNode(ISD::SIGN_EXTEND, DL, LocVT, Arg); 3035 break; 3036 case CCValAssign::ZExtUpper: 3037 UseUpperBits = true; 3038 LLVM_FALLTHROUGH; 3039 case CCValAssign::ZExt: 3040 Arg = DAG.getNode(ISD::ZERO_EXTEND, DL, LocVT, Arg); 3041 break; 3042 case CCValAssign::AExtUpper: 3043 UseUpperBits = true; 3044 LLVM_FALLTHROUGH; 3045 case CCValAssign::AExt: 3046 Arg = DAG.getNode(ISD::ANY_EXTEND, DL, LocVT, Arg); 3047 break; 3048 } 3049 3050 if (UseUpperBits) { 3051 unsigned ValSizeInBits = Outs[i].ArgVT.getSizeInBits(); 3052 unsigned LocSizeInBits = VA.getLocVT().getSizeInBits(); 3053 Arg = DAG.getNode( 3054 ISD::SHL, DL, VA.getLocVT(), Arg, 3055 DAG.getConstant(LocSizeInBits - ValSizeInBits, DL, VA.getLocVT())); 3056 } 3057 3058 // Arguments that can be passed on register must be kept at 3059 // RegsToPass vector 3060 if (VA.isRegLoc()) { 3061 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg)); 3062 continue; 3063 } 3064 3065 // Register can't get to this point... 3066 assert(VA.isMemLoc()); 3067 3068 // emit ISD::STORE whichs stores the 3069 // parameter value to a stack Location 3070 MemOpChains.push_back(passArgOnStack(StackPtr, VA.getLocMemOffset(), 3071 Chain, Arg, DL, IsTailCall, DAG)); 3072 } 3073 3074 // Transform all store nodes into one single node because all store 3075 // nodes are independent of each other. 3076 if (!MemOpChains.empty()) 3077 Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, MemOpChains); 3078 3079 // If the callee is a GlobalAddress/ExternalSymbol node (quite common, every 3080 // direct call is) turn it into a TargetGlobalAddress/TargetExternalSymbol 3081 // node so that legalize doesn't hack it. 3082 3083 EVT Ty = Callee.getValueType(); 3084 bool GlobalOrExternal = false, IsCallReloc = false; 3085 3086 // The long-calls feature is ignored in case of PIC. 3087 // While we do not support -mshared / -mno-shared properly, 3088 // ignore long-calls in case of -mabicalls too. 3089 if (!Subtarget.isABICalls() && !IsPIC) { 3090 // If the function should be called using "long call", 3091 // get its address into a register to prevent using 3092 // of the `jal` instruction for the direct call. 3093 if (auto *N = dyn_cast<ExternalSymbolSDNode>(Callee)) { 3094 if (Subtarget.useLongCalls()) 3095 Callee = Subtarget.hasSym32() 3096 ? getAddrNonPIC(N, SDLoc(N), Ty, DAG) 3097 : getAddrNonPICSym64(N, SDLoc(N), Ty, DAG); 3098 } else if (auto *N = dyn_cast<GlobalAddressSDNode>(Callee)) { 3099 bool UseLongCalls = Subtarget.useLongCalls(); 3100 // If the function has long-call/far/near attribute 3101 // it overrides command line switch pased to the backend. 3102 if (auto *F = dyn_cast<Function>(N->getGlobal())) { 3103 if (F->hasFnAttribute("long-call")) 3104 UseLongCalls = true; 3105 else if (F->hasFnAttribute("short-call")) 3106 UseLongCalls = false; 3107 } 3108 if (UseLongCalls) 3109 Callee = Subtarget.hasSym32() 3110 ? getAddrNonPIC(N, SDLoc(N), Ty, DAG) 3111 : getAddrNonPICSym64(N, SDLoc(N), Ty, DAG); 3112 } 3113 } 3114 3115 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) { 3116 if (IsPIC) { 3117 const GlobalValue *Val = G->getGlobal(); 3118 InternalLinkage = Val->hasInternalLinkage(); 3119 3120 if (InternalLinkage) 3121 Callee = getAddrLocal(G, DL, Ty, DAG, ABI.IsN32() || ABI.IsN64()); 3122 else if (LargeGOT) { 3123 Callee = getAddrGlobalLargeGOT(G, DL, Ty, DAG, MipsII::MO_CALL_HI16, 3124 MipsII::MO_CALL_LO16, Chain, 3125 FuncInfo->callPtrInfo(Val)); 3126 IsCallReloc = true; 3127 } else { 3128 Callee = getAddrGlobal(G, DL, Ty, DAG, MipsII::MO_GOT_CALL, Chain, 3129 FuncInfo->callPtrInfo(Val)); 3130 IsCallReloc = true; 3131 } 3132 } else 3133 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), DL, 3134 getPointerTy(DAG.getDataLayout()), 0, 3135 MipsII::MO_NO_FLAG); 3136 GlobalOrExternal = true; 3137 } 3138 else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) { 3139 const char *Sym = S->getSymbol(); 3140 3141 if (!IsPIC) // static 3142 Callee = DAG.getTargetExternalSymbol( 3143 Sym, getPointerTy(DAG.getDataLayout()), MipsII::MO_NO_FLAG); 3144 else if (LargeGOT) { 3145 Callee = getAddrGlobalLargeGOT(S, DL, Ty, DAG, MipsII::MO_CALL_HI16, 3146 MipsII::MO_CALL_LO16, Chain, 3147 FuncInfo->callPtrInfo(Sym)); 3148 IsCallReloc = true; 3149 } else { // PIC 3150 Callee = getAddrGlobal(S, DL, Ty, DAG, MipsII::MO_GOT_CALL, Chain, 3151 FuncInfo->callPtrInfo(Sym)); 3152 IsCallReloc = true; 3153 } 3154 3155 GlobalOrExternal = true; 3156 } 3157 3158 SmallVector<SDValue, 8> Ops(1, Chain); 3159 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue); 3160 3161 getOpndList(Ops, RegsToPass, IsPIC, GlobalOrExternal, InternalLinkage, 3162 IsCallReloc, CLI, Callee, Chain); 3163 3164 if (IsTailCall) { 3165 MF.getFrameInfo().setHasTailCall(); 3166 return DAG.getNode(MipsISD::TailCall, DL, MVT::Other, Ops); 3167 } 3168 3169 Chain = DAG.getNode(MipsISD::JmpLink, DL, NodeTys, Ops); 3170 SDValue InFlag = Chain.getValue(1); 3171 3172 // Create the CALLSEQ_END node in the case of where it is not a call to 3173 // memcpy. 3174 if (!(MemcpyInByVal)) { 3175 Chain = DAG.getCALLSEQ_END(Chain, NextStackOffsetVal, 3176 DAG.getIntPtrConstant(0, DL, true), InFlag, DL); 3177 InFlag = Chain.getValue(1); 3178 } 3179 3180 // Handle result values, copying them out of physregs into vregs that we 3181 // return. 3182 return LowerCallResult(Chain, InFlag, CallConv, IsVarArg, Ins, DL, DAG, 3183 InVals, CLI); 3184 } 3185 3186 /// LowerCallResult - Lower the result values of a call into the 3187 /// appropriate copies out of appropriate physical registers. 3188 SDValue MipsTargetLowering::LowerCallResult( 3189 SDValue Chain, SDValue InFlag, CallingConv::ID CallConv, bool IsVarArg, 3190 const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &DL, 3191 SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals, 3192 TargetLowering::CallLoweringInfo &CLI) const { 3193 // Assign locations to each value returned by this call. 3194 SmallVector<CCValAssign, 16> RVLocs; 3195 MipsCCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), RVLocs, 3196 *DAG.getContext()); 3197 3198 const ExternalSymbolSDNode *ES = 3199 dyn_cast_or_null<const ExternalSymbolSDNode>(CLI.Callee.getNode()); 3200 CCInfo.AnalyzeCallResult(Ins, RetCC_Mips, CLI.RetTy, 3201 ES ? ES->getSymbol() : nullptr); 3202 3203 // Copy all of the result registers out of their specified physreg. 3204 for (unsigned i = 0; i != RVLocs.size(); ++i) { 3205 CCValAssign &VA = RVLocs[i]; 3206 assert(VA.isRegLoc() && "Can only return in registers!"); 3207 3208 SDValue Val = DAG.getCopyFromReg(Chain, DL, RVLocs[i].getLocReg(), 3209 RVLocs[i].getLocVT(), InFlag); 3210 Chain = Val.getValue(1); 3211 InFlag = Val.getValue(2); 3212 3213 if (VA.isUpperBitsInLoc()) { 3214 unsigned ValSizeInBits = Ins[i].ArgVT.getSizeInBits(); 3215 unsigned LocSizeInBits = VA.getLocVT().getSizeInBits(); 3216 unsigned Shift = 3217 VA.getLocInfo() == CCValAssign::ZExtUpper ? ISD::SRL : ISD::SRA; 3218 Val = DAG.getNode( 3219 Shift, DL, VA.getLocVT(), Val, 3220 DAG.getConstant(LocSizeInBits - ValSizeInBits, DL, VA.getLocVT())); 3221 } 3222 3223 switch (VA.getLocInfo()) { 3224 default: 3225 llvm_unreachable("Unknown loc info!"); 3226 case CCValAssign::Full: 3227 break; 3228 case CCValAssign::BCvt: 3229 Val = DAG.getNode(ISD::BITCAST, DL, VA.getValVT(), Val); 3230 break; 3231 case CCValAssign::AExt: 3232 case CCValAssign::AExtUpper: 3233 Val = DAG.getNode(ISD::TRUNCATE, DL, VA.getValVT(), Val); 3234 break; 3235 case CCValAssign::ZExt: 3236 case CCValAssign::ZExtUpper: 3237 Val = DAG.getNode(ISD::AssertZext, DL, VA.getLocVT(), Val, 3238 DAG.getValueType(VA.getValVT())); 3239 Val = DAG.getNode(ISD::TRUNCATE, DL, VA.getValVT(), Val); 3240 break; 3241 case CCValAssign::SExt: 3242 case CCValAssign::SExtUpper: 3243 Val = DAG.getNode(ISD::AssertSext, DL, VA.getLocVT(), Val, 3244 DAG.getValueType(VA.getValVT())); 3245 Val = DAG.getNode(ISD::TRUNCATE, DL, VA.getValVT(), Val); 3246 break; 3247 } 3248 3249 InVals.push_back(Val); 3250 } 3251 3252 return Chain; 3253 } 3254 3255 static SDValue UnpackFromArgumentSlot(SDValue Val, const CCValAssign &VA, 3256 EVT ArgVT, const SDLoc &DL, 3257 SelectionDAG &DAG) { 3258 MVT LocVT = VA.getLocVT(); 3259 EVT ValVT = VA.getValVT(); 3260 3261 // Shift into the upper bits if necessary. 3262 switch (VA.getLocInfo()) { 3263 default: 3264 break; 3265 case CCValAssign::AExtUpper: 3266 case CCValAssign::SExtUpper: 3267 case CCValAssign::ZExtUpper: { 3268 unsigned ValSizeInBits = ArgVT.getSizeInBits(); 3269 unsigned LocSizeInBits = VA.getLocVT().getSizeInBits(); 3270 unsigned Opcode = 3271 VA.getLocInfo() == CCValAssign::ZExtUpper ? ISD::SRL : ISD::SRA; 3272 Val = DAG.getNode( 3273 Opcode, DL, VA.getLocVT(), Val, 3274 DAG.getConstant(LocSizeInBits - ValSizeInBits, DL, VA.getLocVT())); 3275 break; 3276 } 3277 } 3278 3279 // If this is an value smaller than the argument slot size (32-bit for O32, 3280 // 64-bit for N32/N64), it has been promoted in some way to the argument slot 3281 // size. Extract the value and insert any appropriate assertions regarding 3282 // sign/zero extension. 3283 switch (VA.getLocInfo()) { 3284 default: 3285 llvm_unreachable("Unknown loc info!"); 3286 case CCValAssign::Full: 3287 break; 3288 case CCValAssign::AExtUpper: 3289 case CCValAssign::AExt: 3290 Val = DAG.getNode(ISD::TRUNCATE, DL, ValVT, Val); 3291 break; 3292 case CCValAssign::SExtUpper: 3293 case CCValAssign::SExt: 3294 Val = DAG.getNode(ISD::AssertSext, DL, LocVT, Val, DAG.getValueType(ValVT)); 3295 Val = DAG.getNode(ISD::TRUNCATE, DL, ValVT, Val); 3296 break; 3297 case CCValAssign::ZExtUpper: 3298 case CCValAssign::ZExt: 3299 Val = DAG.getNode(ISD::AssertZext, DL, LocVT, Val, DAG.getValueType(ValVT)); 3300 Val = DAG.getNode(ISD::TRUNCATE, DL, ValVT, Val); 3301 break; 3302 case CCValAssign::BCvt: 3303 Val = DAG.getNode(ISD::BITCAST, DL, ValVT, Val); 3304 break; 3305 } 3306 3307 return Val; 3308 } 3309 3310 //===----------------------------------------------------------------------===// 3311 // Formal Arguments Calling Convention Implementation 3312 //===----------------------------------------------------------------------===// 3313 /// LowerFormalArguments - transform physical registers into virtual registers 3314 /// and generate load operations for arguments places on the stack. 3315 SDValue MipsTargetLowering::LowerFormalArguments( 3316 SDValue Chain, CallingConv::ID CallConv, bool IsVarArg, 3317 const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &DL, 3318 SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const { 3319 MachineFunction &MF = DAG.getMachineFunction(); 3320 MachineFrameInfo &MFI = MF.getFrameInfo(); 3321 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>(); 3322 3323 MipsFI->setVarArgsFrameIndex(0); 3324 3325 // Used with vargs to acumulate store chains. 3326 std::vector<SDValue> OutChains; 3327 3328 // Assign locations to all of the incoming arguments. 3329 SmallVector<CCValAssign, 16> ArgLocs; 3330 MipsCCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), ArgLocs, 3331 *DAG.getContext()); 3332 CCInfo.AllocateStack(ABI.GetCalleeAllocdArgSizeInBytes(CallConv), 1); 3333 const Function &Func = DAG.getMachineFunction().getFunction(); 3334 Function::const_arg_iterator FuncArg = Func.arg_begin(); 3335 3336 if (Func.hasFnAttribute("interrupt") && !Func.arg_empty()) 3337 report_fatal_error( 3338 "Functions with the interrupt attribute cannot have arguments!"); 3339 3340 CCInfo.AnalyzeFormalArguments(Ins, CC_Mips_FixedArg); 3341 MipsFI->setFormalArgInfo(CCInfo.getNextStackOffset(), 3342 CCInfo.getInRegsParamsCount() > 0); 3343 3344 unsigned CurArgIdx = 0; 3345 CCInfo.rewindByValRegsInfo(); 3346 3347 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { 3348 CCValAssign &VA = ArgLocs[i]; 3349 if (Ins[i].isOrigArg()) { 3350 std::advance(FuncArg, Ins[i].getOrigArgIndex() - CurArgIdx); 3351 CurArgIdx = Ins[i].getOrigArgIndex(); 3352 } 3353 EVT ValVT = VA.getValVT(); 3354 ISD::ArgFlagsTy Flags = Ins[i].Flags; 3355 bool IsRegLoc = VA.isRegLoc(); 3356 3357 if (Flags.isByVal()) { 3358 assert(Ins[i].isOrigArg() && "Byval arguments cannot be implicit"); 3359 unsigned FirstByValReg, LastByValReg; 3360 unsigned ByValIdx = CCInfo.getInRegsParamsProcessed(); 3361 CCInfo.getInRegsParamInfo(ByValIdx, FirstByValReg, LastByValReg); 3362 3363 assert(Flags.getByValSize() && 3364 "ByVal args of size 0 should have been ignored by front-end."); 3365 assert(ByValIdx < CCInfo.getInRegsParamsCount()); 3366 copyByValRegs(Chain, DL, OutChains, DAG, Flags, InVals, &*FuncArg, 3367 FirstByValReg, LastByValReg, VA, CCInfo); 3368 CCInfo.nextInRegsParam(); 3369 continue; 3370 } 3371 3372 // Arguments stored on registers 3373 if (IsRegLoc) { 3374 MVT RegVT = VA.getLocVT(); 3375 unsigned ArgReg = VA.getLocReg(); 3376 const TargetRegisterClass *RC = getRegClassFor(RegVT); 3377 3378 // Transform the arguments stored on 3379 // physical registers into virtual ones 3380 unsigned Reg = addLiveIn(DAG.getMachineFunction(), ArgReg, RC); 3381 SDValue ArgValue = DAG.getCopyFromReg(Chain, DL, Reg, RegVT); 3382 3383 ArgValue = UnpackFromArgumentSlot(ArgValue, VA, Ins[i].ArgVT, DL, DAG); 3384 3385 // Handle floating point arguments passed in integer registers and 3386 // long double arguments passed in floating point registers. 3387 if ((RegVT == MVT::i32 && ValVT == MVT::f32) || 3388 (RegVT == MVT::i64 && ValVT == MVT::f64) || 3389 (RegVT == MVT::f64 && ValVT == MVT::i64)) 3390 ArgValue = DAG.getNode(ISD::BITCAST, DL, ValVT, ArgValue); 3391 else if (ABI.IsO32() && RegVT == MVT::i32 && 3392 ValVT == MVT::f64) { 3393 unsigned Reg2 = addLiveIn(DAG.getMachineFunction(), 3394 getNextIntArgReg(ArgReg), RC); 3395 SDValue ArgValue2 = DAG.getCopyFromReg(Chain, DL, Reg2, RegVT); 3396 if (!Subtarget.isLittle()) 3397 std::swap(ArgValue, ArgValue2); 3398 ArgValue = DAG.getNode(MipsISD::BuildPairF64, DL, MVT::f64, 3399 ArgValue, ArgValue2); 3400 } 3401 3402 InVals.push_back(ArgValue); 3403 } else { // VA.isRegLoc() 3404 MVT LocVT = VA.getLocVT(); 3405 3406 if (ABI.IsO32()) { 3407 // We ought to be able to use LocVT directly but O32 sets it to i32 3408 // when allocating floating point values to integer registers. 3409 // This shouldn't influence how we load the value into registers unless 3410 // we are targeting softfloat. 3411 if (VA.getValVT().isFloatingPoint() && !Subtarget.useSoftFloat()) 3412 LocVT = VA.getValVT(); 3413 } 3414 3415 // sanity check 3416 assert(VA.isMemLoc()); 3417 3418 // The stack pointer offset is relative to the caller stack frame. 3419 int FI = MFI.CreateFixedObject(LocVT.getSizeInBits() / 8, 3420 VA.getLocMemOffset(), true); 3421 3422 // Create load nodes to retrieve arguments from the stack 3423 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy(DAG.getDataLayout())); 3424 SDValue ArgValue = DAG.getLoad( 3425 LocVT, DL, Chain, FIN, 3426 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), FI)); 3427 OutChains.push_back(ArgValue.getValue(1)); 3428 3429 ArgValue = UnpackFromArgumentSlot(ArgValue, VA, Ins[i].ArgVT, DL, DAG); 3430 3431 InVals.push_back(ArgValue); 3432 } 3433 } 3434 3435 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { 3436 // The mips ABIs for returning structs by value requires that we copy 3437 // the sret argument into $v0 for the return. Save the argument into 3438 // a virtual register so that we can access it from the return points. 3439 if (Ins[i].Flags.isSRet()) { 3440 unsigned Reg = MipsFI->getSRetReturnReg(); 3441 if (!Reg) { 3442 Reg = MF.getRegInfo().createVirtualRegister( 3443 getRegClassFor(ABI.IsN64() ? MVT::i64 : MVT::i32)); 3444 MipsFI->setSRetReturnReg(Reg); 3445 } 3446 SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), DL, Reg, InVals[i]); 3447 Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, Copy, Chain); 3448 break; 3449 } 3450 } 3451 3452 if (IsVarArg) 3453 writeVarArgRegs(OutChains, Chain, DL, DAG, CCInfo); 3454 3455 // All stores are grouped in one node to allow the matching between 3456 // the size of Ins and InVals. This only happens when on varg functions 3457 if (!OutChains.empty()) { 3458 OutChains.push_back(Chain); 3459 Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, OutChains); 3460 } 3461 3462 return Chain; 3463 } 3464 3465 //===----------------------------------------------------------------------===// 3466 // Return Value Calling Convention Implementation 3467 //===----------------------------------------------------------------------===// 3468 3469 bool 3470 MipsTargetLowering::CanLowerReturn(CallingConv::ID CallConv, 3471 MachineFunction &MF, bool IsVarArg, 3472 const SmallVectorImpl<ISD::OutputArg> &Outs, 3473 LLVMContext &Context) const { 3474 SmallVector<CCValAssign, 16> RVLocs; 3475 MipsCCState CCInfo(CallConv, IsVarArg, MF, RVLocs, Context); 3476 return CCInfo.CheckReturn(Outs, RetCC_Mips); 3477 } 3478 3479 bool 3480 MipsTargetLowering::shouldSignExtendTypeInLibCall(EVT Type, bool IsSigned) const { 3481 if ((ABI.IsN32() || ABI.IsN64()) && Type == MVT::i32) 3482 return true; 3483 3484 return IsSigned; 3485 } 3486 3487 SDValue 3488 MipsTargetLowering::LowerInterruptReturn(SmallVectorImpl<SDValue> &RetOps, 3489 const SDLoc &DL, 3490 SelectionDAG &DAG) const { 3491 MachineFunction &MF = DAG.getMachineFunction(); 3492 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>(); 3493 3494 MipsFI->setISR(); 3495 3496 return DAG.getNode(MipsISD::ERet, DL, MVT::Other, RetOps); 3497 } 3498 3499 SDValue 3500 MipsTargetLowering::LowerReturn(SDValue Chain, CallingConv::ID CallConv, 3501 bool IsVarArg, 3502 const SmallVectorImpl<ISD::OutputArg> &Outs, 3503 const SmallVectorImpl<SDValue> &OutVals, 3504 const SDLoc &DL, SelectionDAG &DAG) const { 3505 // CCValAssign - represent the assignment of 3506 // the return value to a location 3507 SmallVector<CCValAssign, 16> RVLocs; 3508 MachineFunction &MF = DAG.getMachineFunction(); 3509 3510 // CCState - Info about the registers and stack slot. 3511 MipsCCState CCInfo(CallConv, IsVarArg, MF, RVLocs, *DAG.getContext()); 3512 3513 // Analyze return values. 3514 CCInfo.AnalyzeReturn(Outs, RetCC_Mips); 3515 3516 SDValue Flag; 3517 SmallVector<SDValue, 4> RetOps(1, Chain); 3518 3519 // Copy the result values into the output registers. 3520 for (unsigned i = 0; i != RVLocs.size(); ++i) { 3521 SDValue Val = OutVals[i]; 3522 CCValAssign &VA = RVLocs[i]; 3523 assert(VA.isRegLoc() && "Can only return in registers!"); 3524 bool UseUpperBits = false; 3525 3526 switch (VA.getLocInfo()) { 3527 default: 3528 llvm_unreachable("Unknown loc info!"); 3529 case CCValAssign::Full: 3530 break; 3531 case CCValAssign::BCvt: 3532 Val = DAG.getNode(ISD::BITCAST, DL, VA.getLocVT(), Val); 3533 break; 3534 case CCValAssign::AExtUpper: 3535 UseUpperBits = true; 3536 LLVM_FALLTHROUGH; 3537 case CCValAssign::AExt: 3538 Val = DAG.getNode(ISD::ANY_EXTEND, DL, VA.getLocVT(), Val); 3539 break; 3540 case CCValAssign::ZExtUpper: 3541 UseUpperBits = true; 3542 LLVM_FALLTHROUGH; 3543 case CCValAssign::ZExt: 3544 Val = DAG.getNode(ISD::ZERO_EXTEND, DL, VA.getLocVT(), Val); 3545 break; 3546 case CCValAssign::SExtUpper: 3547 UseUpperBits = true; 3548 LLVM_FALLTHROUGH; 3549 case CCValAssign::SExt: 3550 Val = DAG.getNode(ISD::SIGN_EXTEND, DL, VA.getLocVT(), Val); 3551 break; 3552 } 3553 3554 if (UseUpperBits) { 3555 unsigned ValSizeInBits = Outs[i].ArgVT.getSizeInBits(); 3556 unsigned LocSizeInBits = VA.getLocVT().getSizeInBits(); 3557 Val = DAG.getNode( 3558 ISD::SHL, DL, VA.getLocVT(), Val, 3559 DAG.getConstant(LocSizeInBits - ValSizeInBits, DL, VA.getLocVT())); 3560 } 3561 3562 Chain = DAG.getCopyToReg(Chain, DL, VA.getLocReg(), Val, Flag); 3563 3564 // Guarantee that all emitted copies are stuck together with flags. 3565 Flag = Chain.getValue(1); 3566 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT())); 3567 } 3568 3569 // The mips ABIs for returning structs by value requires that we copy 3570 // the sret argument into $v0 for the return. We saved the argument into 3571 // a virtual register in the entry block, so now we copy the value out 3572 // and into $v0. 3573 if (MF.getFunction().hasStructRetAttr()) { 3574 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>(); 3575 unsigned Reg = MipsFI->getSRetReturnReg(); 3576 3577 if (!Reg) 3578 llvm_unreachable("sret virtual register not created in the entry block"); 3579 SDValue Val = 3580 DAG.getCopyFromReg(Chain, DL, Reg, getPointerTy(DAG.getDataLayout())); 3581 unsigned V0 = ABI.IsN64() ? Mips::V0_64 : Mips::V0; 3582 3583 Chain = DAG.getCopyToReg(Chain, DL, V0, Val, Flag); 3584 Flag = Chain.getValue(1); 3585 RetOps.push_back(DAG.getRegister(V0, getPointerTy(DAG.getDataLayout()))); 3586 } 3587 3588 RetOps[0] = Chain; // Update chain. 3589 3590 // Add the flag if we have it. 3591 if (Flag.getNode()) 3592 RetOps.push_back(Flag); 3593 3594 // ISRs must use "eret". 3595 if (DAG.getMachineFunction().getFunction().hasFnAttribute("interrupt")) 3596 return LowerInterruptReturn(RetOps, DL, DAG); 3597 3598 // Standard return on Mips is a "jr $ra" 3599 return DAG.getNode(MipsISD::Ret, DL, MVT::Other, RetOps); 3600 } 3601 3602 //===----------------------------------------------------------------------===// 3603 // Mips Inline Assembly Support 3604 //===----------------------------------------------------------------------===// 3605 3606 /// getConstraintType - Given a constraint letter, return the type of 3607 /// constraint it is for this target. 3608 MipsTargetLowering::ConstraintType 3609 MipsTargetLowering::getConstraintType(StringRef Constraint) const { 3610 // Mips specific constraints 3611 // GCC config/mips/constraints.md 3612 // 3613 // 'd' : An address register. Equivalent to r 3614 // unless generating MIPS16 code. 3615 // 'y' : Equivalent to r; retained for 3616 // backwards compatibility. 3617 // 'c' : A register suitable for use in an indirect 3618 // jump. This will always be $25 for -mabicalls. 3619 // 'l' : The lo register. 1 word storage. 3620 // 'x' : The hilo register pair. Double word storage. 3621 if (Constraint.size() == 1) { 3622 switch (Constraint[0]) { 3623 default : break; 3624 case 'd': 3625 case 'y': 3626 case 'f': 3627 case 'c': 3628 case 'l': 3629 case 'x': 3630 return C_RegisterClass; 3631 case 'R': 3632 return C_Memory; 3633 } 3634 } 3635 3636 if (Constraint == "ZC") 3637 return C_Memory; 3638 3639 return TargetLowering::getConstraintType(Constraint); 3640 } 3641 3642 /// Examine constraint type and operand type and determine a weight value. 3643 /// This object must already have been set up with the operand type 3644 /// and the current alternative constraint selected. 3645 TargetLowering::ConstraintWeight 3646 MipsTargetLowering::getSingleConstraintMatchWeight( 3647 AsmOperandInfo &info, const char *constraint) const { 3648 ConstraintWeight weight = CW_Invalid; 3649 Value *CallOperandVal = info.CallOperandVal; 3650 // If we don't have a value, we can't do a match, 3651 // but allow it at the lowest weight. 3652 if (!CallOperandVal) 3653 return CW_Default; 3654 Type *type = CallOperandVal->getType(); 3655 // Look at the constraint type. 3656 switch (*constraint) { 3657 default: 3658 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint); 3659 break; 3660 case 'd': 3661 case 'y': 3662 if (type->isIntegerTy()) 3663 weight = CW_Register; 3664 break; 3665 case 'f': // FPU or MSA register 3666 if (Subtarget.hasMSA() && type->isVectorTy() && 3667 cast<VectorType>(type)->getBitWidth() == 128) 3668 weight = CW_Register; 3669 else if (type->isFloatTy()) 3670 weight = CW_Register; 3671 break; 3672 case 'c': // $25 for indirect jumps 3673 case 'l': // lo register 3674 case 'x': // hilo register pair 3675 if (type->isIntegerTy()) 3676 weight = CW_SpecificReg; 3677 break; 3678 case 'I': // signed 16 bit immediate 3679 case 'J': // integer zero 3680 case 'K': // unsigned 16 bit immediate 3681 case 'L': // signed 32 bit immediate where lower 16 bits are 0 3682 case 'N': // immediate in the range of -65535 to -1 (inclusive) 3683 case 'O': // signed 15 bit immediate (+- 16383) 3684 case 'P': // immediate in the range of 65535 to 1 (inclusive) 3685 if (isa<ConstantInt>(CallOperandVal)) 3686 weight = CW_Constant; 3687 break; 3688 case 'R': 3689 weight = CW_Memory; 3690 break; 3691 } 3692 return weight; 3693 } 3694 3695 /// This is a helper function to parse a physical register string and split it 3696 /// into non-numeric and numeric parts (Prefix and Reg). The first boolean flag 3697 /// that is returned indicates whether parsing was successful. The second flag 3698 /// is true if the numeric part exists. 3699 static std::pair<bool, bool> parsePhysicalReg(StringRef C, StringRef &Prefix, 3700 unsigned long long &Reg) { 3701 if (C.front() != '{' || C.back() != '}') 3702 return std::make_pair(false, false); 3703 3704 // Search for the first numeric character. 3705 StringRef::const_iterator I, B = C.begin() + 1, E = C.end() - 1; 3706 I = std::find_if(B, E, isdigit); 3707 3708 Prefix = StringRef(B, I - B); 3709 3710 // The second flag is set to false if no numeric characters were found. 3711 if (I == E) 3712 return std::make_pair(true, false); 3713 3714 // Parse the numeric characters. 3715 return std::make_pair(!getAsUnsignedInteger(StringRef(I, E - I), 10, Reg), 3716 true); 3717 } 3718 3719 EVT MipsTargetLowering::getTypeForExtReturn(LLVMContext &Context, EVT VT, 3720 ISD::NodeType) const { 3721 bool Cond = !Subtarget.isABI_O32() && VT.getSizeInBits() == 32; 3722 EVT MinVT = getRegisterType(Context, Cond ? MVT::i64 : MVT::i32); 3723 return VT.bitsLT(MinVT) ? MinVT : VT; 3724 } 3725 3726 std::pair<unsigned, const TargetRegisterClass *> MipsTargetLowering:: 3727 parseRegForInlineAsmConstraint(StringRef C, MVT VT) const { 3728 const TargetRegisterInfo *TRI = 3729 Subtarget.getRegisterInfo(); 3730 const TargetRegisterClass *RC; 3731 StringRef Prefix; 3732 unsigned long long Reg; 3733 3734 std::pair<bool, bool> R = parsePhysicalReg(C, Prefix, Reg); 3735 3736 if (!R.first) 3737 return std::make_pair(0U, nullptr); 3738 3739 if ((Prefix == "hi" || Prefix == "lo")) { // Parse hi/lo. 3740 // No numeric characters follow "hi" or "lo". 3741 if (R.second) 3742 return std::make_pair(0U, nullptr); 3743 3744 RC = TRI->getRegClass(Prefix == "hi" ? 3745 Mips::HI32RegClassID : Mips::LO32RegClassID); 3746 return std::make_pair(*(RC->begin()), RC); 3747 } else if (Prefix.startswith("$msa")) { 3748 // Parse $msa(ir|csr|access|save|modify|request|map|unmap) 3749 3750 // No numeric characters follow the name. 3751 if (R.second) 3752 return std::make_pair(0U, nullptr); 3753 3754 Reg = StringSwitch<unsigned long long>(Prefix) 3755 .Case("$msair", Mips::MSAIR) 3756 .Case("$msacsr", Mips::MSACSR) 3757 .Case("$msaaccess", Mips::MSAAccess) 3758 .Case("$msasave", Mips::MSASave) 3759 .Case("$msamodify", Mips::MSAModify) 3760 .Case("$msarequest", Mips::MSARequest) 3761 .Case("$msamap", Mips::MSAMap) 3762 .Case("$msaunmap", Mips::MSAUnmap) 3763 .Default(0); 3764 3765 if (!Reg) 3766 return std::make_pair(0U, nullptr); 3767 3768 RC = TRI->getRegClass(Mips::MSACtrlRegClassID); 3769 return std::make_pair(Reg, RC); 3770 } 3771 3772 if (!R.second) 3773 return std::make_pair(0U, nullptr); 3774 3775 if (Prefix == "$f") { // Parse $f0-$f31. 3776 // If the size of FP registers is 64-bit or Reg is an even number, select 3777 // the 64-bit register class. Otherwise, select the 32-bit register class. 3778 if (VT == MVT::Other) 3779 VT = (Subtarget.isFP64bit() || !(Reg % 2)) ? MVT::f64 : MVT::f32; 3780 3781 RC = getRegClassFor(VT); 3782 3783 if (RC == &Mips::AFGR64RegClass) { 3784 assert(Reg % 2 == 0); 3785 Reg >>= 1; 3786 } 3787 } else if (Prefix == "$fcc") // Parse $fcc0-$fcc7. 3788 RC = TRI->getRegClass(Mips::FCCRegClassID); 3789 else if (Prefix == "$w") { // Parse $w0-$w31. 3790 RC = getRegClassFor((VT == MVT::Other) ? MVT::v16i8 : VT); 3791 } else { // Parse $0-$31. 3792 assert(Prefix == "$"); 3793 RC = getRegClassFor((VT == MVT::Other) ? MVT::i32 : VT); 3794 } 3795 3796 assert(Reg < RC->getNumRegs()); 3797 return std::make_pair(*(RC->begin() + Reg), RC); 3798 } 3799 3800 /// Given a register class constraint, like 'r', if this corresponds directly 3801 /// to an LLVM register class, return a register of 0 and the register class 3802 /// pointer. 3803 std::pair<unsigned, const TargetRegisterClass *> 3804 MipsTargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, 3805 StringRef Constraint, 3806 MVT VT) const { 3807 if (Constraint.size() == 1) { 3808 switch (Constraint[0]) { 3809 case 'd': // Address register. Same as 'r' unless generating MIPS16 code. 3810 case 'y': // Same as 'r'. Exists for compatibility. 3811 case 'r': 3812 if (VT == MVT::i32 || VT == MVT::i16 || VT == MVT::i8) { 3813 if (Subtarget.inMips16Mode()) 3814 return std::make_pair(0U, &Mips::CPU16RegsRegClass); 3815 return std::make_pair(0U, &Mips::GPR32RegClass); 3816 } 3817 if (VT == MVT::i64 && !Subtarget.isGP64bit()) 3818 return std::make_pair(0U, &Mips::GPR32RegClass); 3819 if (VT == MVT::i64 && Subtarget.isGP64bit()) 3820 return std::make_pair(0U, &Mips::GPR64RegClass); 3821 // This will generate an error message 3822 return std::make_pair(0U, nullptr); 3823 case 'f': // FPU or MSA register 3824 if (VT == MVT::v16i8) 3825 return std::make_pair(0U, &Mips::MSA128BRegClass); 3826 else if (VT == MVT::v8i16 || VT == MVT::v8f16) 3827 return std::make_pair(0U, &Mips::MSA128HRegClass); 3828 else if (VT == MVT::v4i32 || VT == MVT::v4f32) 3829 return std::make_pair(0U, &Mips::MSA128WRegClass); 3830 else if (VT == MVT::v2i64 || VT == MVT::v2f64) 3831 return std::make_pair(0U, &Mips::MSA128DRegClass); 3832 else if (VT == MVT::f32) 3833 return std::make_pair(0U, &Mips::FGR32RegClass); 3834 else if ((VT == MVT::f64) && (!Subtarget.isSingleFloat())) { 3835 if (Subtarget.isFP64bit()) 3836 return std::make_pair(0U, &Mips::FGR64RegClass); 3837 return std::make_pair(0U, &Mips::AFGR64RegClass); 3838 } 3839 break; 3840 case 'c': // register suitable for indirect jump 3841 if (VT == MVT::i32) 3842 return std::make_pair((unsigned)Mips::T9, &Mips::GPR32RegClass); 3843 if (VT == MVT::i64) 3844 return std::make_pair((unsigned)Mips::T9_64, &Mips::GPR64RegClass); 3845 // This will generate an error message 3846 return std::make_pair(0U, nullptr); 3847 case 'l': // use the `lo` register to store values 3848 // that are no bigger than a word 3849 if (VT == MVT::i32 || VT == MVT::i16 || VT == MVT::i8) 3850 return std::make_pair((unsigned)Mips::LO0, &Mips::LO32RegClass); 3851 return std::make_pair((unsigned)Mips::LO0_64, &Mips::LO64RegClass); 3852 case 'x': // use the concatenated `hi` and `lo` registers 3853 // to store doubleword values 3854 // Fixme: Not triggering the use of both hi and low 3855 // This will generate an error message 3856 return std::make_pair(0U, nullptr); 3857 } 3858 } 3859 3860 std::pair<unsigned, const TargetRegisterClass *> R; 3861 R = parseRegForInlineAsmConstraint(Constraint, VT); 3862 3863 if (R.second) 3864 return R; 3865 3866 return TargetLowering::getRegForInlineAsmConstraint(TRI, Constraint, VT); 3867 } 3868 3869 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops 3870 /// vector. If it is invalid, don't add anything to Ops. 3871 void MipsTargetLowering::LowerAsmOperandForConstraint(SDValue Op, 3872 std::string &Constraint, 3873 std::vector<SDValue>&Ops, 3874 SelectionDAG &DAG) const { 3875 SDLoc DL(Op); 3876 SDValue Result; 3877 3878 // Only support length 1 constraints for now. 3879 if (Constraint.length() > 1) return; 3880 3881 char ConstraintLetter = Constraint[0]; 3882 switch (ConstraintLetter) { 3883 default: break; // This will fall through to the generic implementation 3884 case 'I': // Signed 16 bit constant 3885 // If this fails, the parent routine will give an error 3886 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 3887 EVT Type = Op.getValueType(); 3888 int64_t Val = C->getSExtValue(); 3889 if (isInt<16>(Val)) { 3890 Result = DAG.getTargetConstant(Val, DL, Type); 3891 break; 3892 } 3893 } 3894 return; 3895 case 'J': // integer zero 3896 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 3897 EVT Type = Op.getValueType(); 3898 int64_t Val = C->getZExtValue(); 3899 if (Val == 0) { 3900 Result = DAG.getTargetConstant(0, DL, Type); 3901 break; 3902 } 3903 } 3904 return; 3905 case 'K': // unsigned 16 bit immediate 3906 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 3907 EVT Type = Op.getValueType(); 3908 uint64_t Val = (uint64_t)C->getZExtValue(); 3909 if (isUInt<16>(Val)) { 3910 Result = DAG.getTargetConstant(Val, DL, Type); 3911 break; 3912 } 3913 } 3914 return; 3915 case 'L': // signed 32 bit immediate where lower 16 bits are 0 3916 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 3917 EVT Type = Op.getValueType(); 3918 int64_t Val = C->getSExtValue(); 3919 if ((isInt<32>(Val)) && ((Val & 0xffff) == 0)){ 3920 Result = DAG.getTargetConstant(Val, DL, Type); 3921 break; 3922 } 3923 } 3924 return; 3925 case 'N': // immediate in the range of -65535 to -1 (inclusive) 3926 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 3927 EVT Type = Op.getValueType(); 3928 int64_t Val = C->getSExtValue(); 3929 if ((Val >= -65535) && (Val <= -1)) { 3930 Result = DAG.getTargetConstant(Val, DL, Type); 3931 break; 3932 } 3933 } 3934 return; 3935 case 'O': // signed 15 bit immediate 3936 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 3937 EVT Type = Op.getValueType(); 3938 int64_t Val = C->getSExtValue(); 3939 if ((isInt<15>(Val))) { 3940 Result = DAG.getTargetConstant(Val, DL, Type); 3941 break; 3942 } 3943 } 3944 return; 3945 case 'P': // immediate in the range of 1 to 65535 (inclusive) 3946 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 3947 EVT Type = Op.getValueType(); 3948 int64_t Val = C->getSExtValue(); 3949 if ((Val <= 65535) && (Val >= 1)) { 3950 Result = DAG.getTargetConstant(Val, DL, Type); 3951 break; 3952 } 3953 } 3954 return; 3955 } 3956 3957 if (Result.getNode()) { 3958 Ops.push_back(Result); 3959 return; 3960 } 3961 3962 TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG); 3963 } 3964 3965 bool MipsTargetLowering::isLegalAddressingMode(const DataLayout &DL, 3966 const AddrMode &AM, Type *Ty, 3967 unsigned AS, Instruction *I) const { 3968 // No global is ever allowed as a base. 3969 if (AM.BaseGV) 3970 return false; 3971 3972 switch (AM.Scale) { 3973 case 0: // "r+i" or just "i", depending on HasBaseReg. 3974 break; 3975 case 1: 3976 if (!AM.HasBaseReg) // allow "r+i". 3977 break; 3978 return false; // disallow "r+r" or "r+r+i". 3979 default: 3980 return false; 3981 } 3982 3983 return true; 3984 } 3985 3986 bool 3987 MipsTargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const { 3988 // The Mips target isn't yet aware of offsets. 3989 return false; 3990 } 3991 3992 EVT MipsTargetLowering::getOptimalMemOpType(uint64_t Size, unsigned DstAlign, 3993 unsigned SrcAlign, 3994 bool IsMemset, bool ZeroMemset, 3995 bool MemcpyStrSrc, 3996 MachineFunction &MF) const { 3997 if (Subtarget.hasMips64()) 3998 return MVT::i64; 3999 4000 return MVT::i32; 4001 } 4002 4003 bool MipsTargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const { 4004 if (VT != MVT::f32 && VT != MVT::f64) 4005 return false; 4006 if (Imm.isNegZero()) 4007 return false; 4008 return Imm.isZero(); 4009 } 4010 4011 unsigned MipsTargetLowering::getJumpTableEncoding() const { 4012 4013 // FIXME: For space reasons this should be: EK_GPRel32BlockAddress. 4014 if (ABI.IsN64() && isPositionIndependent()) 4015 return MachineJumpTableInfo::EK_GPRel64BlockAddress; 4016 4017 return TargetLowering::getJumpTableEncoding(); 4018 } 4019 4020 bool MipsTargetLowering::useSoftFloat() const { 4021 return Subtarget.useSoftFloat(); 4022 } 4023 4024 void MipsTargetLowering::copyByValRegs( 4025 SDValue Chain, const SDLoc &DL, std::vector<SDValue> &OutChains, 4026 SelectionDAG &DAG, const ISD::ArgFlagsTy &Flags, 4027 SmallVectorImpl<SDValue> &InVals, const Argument *FuncArg, 4028 unsigned FirstReg, unsigned LastReg, const CCValAssign &VA, 4029 MipsCCState &State) const { 4030 MachineFunction &MF = DAG.getMachineFunction(); 4031 MachineFrameInfo &MFI = MF.getFrameInfo(); 4032 unsigned GPRSizeInBytes = Subtarget.getGPRSizeInBytes(); 4033 unsigned NumRegs = LastReg - FirstReg; 4034 unsigned RegAreaSize = NumRegs * GPRSizeInBytes; 4035 unsigned FrameObjSize = std::max(Flags.getByValSize(), RegAreaSize); 4036 int FrameObjOffset; 4037 ArrayRef<MCPhysReg> ByValArgRegs = ABI.GetByValArgRegs(); 4038 4039 if (RegAreaSize) 4040 FrameObjOffset = 4041 (int)ABI.GetCalleeAllocdArgSizeInBytes(State.getCallingConv()) - 4042 (int)((ByValArgRegs.size() - FirstReg) * GPRSizeInBytes); 4043 else 4044 FrameObjOffset = VA.getLocMemOffset(); 4045 4046 // Create frame object. 4047 EVT PtrTy = getPointerTy(DAG.getDataLayout()); 4048 // Make the fixed object stored to mutable so that the load instructions 4049 // referencing it have their memory dependencies added. 4050 // Set the frame object as isAliased which clears the underlying objects 4051 // vector in ScheduleDAGInstrs::buildSchedGraph() resulting in addition of all 4052 // stores as dependencies for loads referencing this fixed object. 4053 int FI = MFI.CreateFixedObject(FrameObjSize, FrameObjOffset, false, true); 4054 SDValue FIN = DAG.getFrameIndex(FI, PtrTy); 4055 InVals.push_back(FIN); 4056 4057 if (!NumRegs) 4058 return; 4059 4060 // Copy arg registers. 4061 MVT RegTy = MVT::getIntegerVT(GPRSizeInBytes * 8); 4062 const TargetRegisterClass *RC = getRegClassFor(RegTy); 4063 4064 for (unsigned I = 0; I < NumRegs; ++I) { 4065 unsigned ArgReg = ByValArgRegs[FirstReg + I]; 4066 unsigned VReg = addLiveIn(MF, ArgReg, RC); 4067 unsigned Offset = I * GPRSizeInBytes; 4068 SDValue StorePtr = DAG.getNode(ISD::ADD, DL, PtrTy, FIN, 4069 DAG.getConstant(Offset, DL, PtrTy)); 4070 SDValue Store = DAG.getStore(Chain, DL, DAG.getRegister(VReg, RegTy), 4071 StorePtr, MachinePointerInfo(FuncArg, Offset)); 4072 OutChains.push_back(Store); 4073 } 4074 } 4075 4076 // Copy byVal arg to registers and stack. 4077 void MipsTargetLowering::passByValArg( 4078 SDValue Chain, const SDLoc &DL, 4079 std::deque<std::pair<unsigned, SDValue>> &RegsToPass, 4080 SmallVectorImpl<SDValue> &MemOpChains, SDValue StackPtr, 4081 MachineFrameInfo &MFI, SelectionDAG &DAG, SDValue Arg, unsigned FirstReg, 4082 unsigned LastReg, const ISD::ArgFlagsTy &Flags, bool isLittle, 4083 const CCValAssign &VA) const { 4084 unsigned ByValSizeInBytes = Flags.getByValSize(); 4085 unsigned OffsetInBytes = 0; // From beginning of struct 4086 unsigned RegSizeInBytes = Subtarget.getGPRSizeInBytes(); 4087 unsigned Alignment = std::min(Flags.getByValAlign(), RegSizeInBytes); 4088 EVT PtrTy = getPointerTy(DAG.getDataLayout()), 4089 RegTy = MVT::getIntegerVT(RegSizeInBytes * 8); 4090 unsigned NumRegs = LastReg - FirstReg; 4091 4092 if (NumRegs) { 4093 ArrayRef<MCPhysReg> ArgRegs = ABI.GetByValArgRegs(); 4094 bool LeftoverBytes = (NumRegs * RegSizeInBytes > ByValSizeInBytes); 4095 unsigned I = 0; 4096 4097 // Copy words to registers. 4098 for (; I < NumRegs - LeftoverBytes; ++I, OffsetInBytes += RegSizeInBytes) { 4099 SDValue LoadPtr = DAG.getNode(ISD::ADD, DL, PtrTy, Arg, 4100 DAG.getConstant(OffsetInBytes, DL, PtrTy)); 4101 SDValue LoadVal = DAG.getLoad(RegTy, DL, Chain, LoadPtr, 4102 MachinePointerInfo(), Alignment); 4103 MemOpChains.push_back(LoadVal.getValue(1)); 4104 unsigned ArgReg = ArgRegs[FirstReg + I]; 4105 RegsToPass.push_back(std::make_pair(ArgReg, LoadVal)); 4106 } 4107 4108 // Return if the struct has been fully copied. 4109 if (ByValSizeInBytes == OffsetInBytes) 4110 return; 4111 4112 // Copy the remainder of the byval argument with sub-word loads and shifts. 4113 if (LeftoverBytes) { 4114 SDValue Val; 4115 4116 for (unsigned LoadSizeInBytes = RegSizeInBytes / 2, TotalBytesLoaded = 0; 4117 OffsetInBytes < ByValSizeInBytes; LoadSizeInBytes /= 2) { 4118 unsigned RemainingSizeInBytes = ByValSizeInBytes - OffsetInBytes; 4119 4120 if (RemainingSizeInBytes < LoadSizeInBytes) 4121 continue; 4122 4123 // Load subword. 4124 SDValue LoadPtr = DAG.getNode(ISD::ADD, DL, PtrTy, Arg, 4125 DAG.getConstant(OffsetInBytes, DL, 4126 PtrTy)); 4127 SDValue LoadVal = DAG.getExtLoad( 4128 ISD::ZEXTLOAD, DL, RegTy, Chain, LoadPtr, MachinePointerInfo(), 4129 MVT::getIntegerVT(LoadSizeInBytes * 8), Alignment); 4130 MemOpChains.push_back(LoadVal.getValue(1)); 4131 4132 // Shift the loaded value. 4133 unsigned Shamt; 4134 4135 if (isLittle) 4136 Shamt = TotalBytesLoaded * 8; 4137 else 4138 Shamt = (RegSizeInBytes - (TotalBytesLoaded + LoadSizeInBytes)) * 8; 4139 4140 SDValue Shift = DAG.getNode(ISD::SHL, DL, RegTy, LoadVal, 4141 DAG.getConstant(Shamt, DL, MVT::i32)); 4142 4143 if (Val.getNode()) 4144 Val = DAG.getNode(ISD::OR, DL, RegTy, Val, Shift); 4145 else 4146 Val = Shift; 4147 4148 OffsetInBytes += LoadSizeInBytes; 4149 TotalBytesLoaded += LoadSizeInBytes; 4150 Alignment = std::min(Alignment, LoadSizeInBytes); 4151 } 4152 4153 unsigned ArgReg = ArgRegs[FirstReg + I]; 4154 RegsToPass.push_back(std::make_pair(ArgReg, Val)); 4155 return; 4156 } 4157 } 4158 4159 // Copy remainder of byval arg to it with memcpy. 4160 unsigned MemCpySize = ByValSizeInBytes - OffsetInBytes; 4161 SDValue Src = DAG.getNode(ISD::ADD, DL, PtrTy, Arg, 4162 DAG.getConstant(OffsetInBytes, DL, PtrTy)); 4163 SDValue Dst = DAG.getNode(ISD::ADD, DL, PtrTy, StackPtr, 4164 DAG.getIntPtrConstant(VA.getLocMemOffset(), DL)); 4165 Chain = DAG.getMemcpy(Chain, DL, Dst, Src, 4166 DAG.getConstant(MemCpySize, DL, PtrTy), 4167 Alignment, /*isVolatile=*/false, /*AlwaysInline=*/false, 4168 /*isTailCall=*/false, 4169 MachinePointerInfo(), MachinePointerInfo()); 4170 MemOpChains.push_back(Chain); 4171 } 4172 4173 void MipsTargetLowering::writeVarArgRegs(std::vector<SDValue> &OutChains, 4174 SDValue Chain, const SDLoc &DL, 4175 SelectionDAG &DAG, 4176 CCState &State) const { 4177 ArrayRef<MCPhysReg> ArgRegs = ABI.GetVarArgRegs(); 4178 unsigned Idx = State.getFirstUnallocated(ArgRegs); 4179 unsigned RegSizeInBytes = Subtarget.getGPRSizeInBytes(); 4180 MVT RegTy = MVT::getIntegerVT(RegSizeInBytes * 8); 4181 const TargetRegisterClass *RC = getRegClassFor(RegTy); 4182 MachineFunction &MF = DAG.getMachineFunction(); 4183 MachineFrameInfo &MFI = MF.getFrameInfo(); 4184 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>(); 4185 4186 // Offset of the first variable argument from stack pointer. 4187 int VaArgOffset; 4188 4189 if (ArgRegs.size() == Idx) 4190 VaArgOffset = alignTo(State.getNextStackOffset(), RegSizeInBytes); 4191 else { 4192 VaArgOffset = 4193 (int)ABI.GetCalleeAllocdArgSizeInBytes(State.getCallingConv()) - 4194 (int)(RegSizeInBytes * (ArgRegs.size() - Idx)); 4195 } 4196 4197 // Record the frame index of the first variable argument 4198 // which is a value necessary to VASTART. 4199 int FI = MFI.CreateFixedObject(RegSizeInBytes, VaArgOffset, true); 4200 MipsFI->setVarArgsFrameIndex(FI); 4201 4202 // Copy the integer registers that have not been used for argument passing 4203 // to the argument register save area. For O32, the save area is allocated 4204 // in the caller's stack frame, while for N32/64, it is allocated in the 4205 // callee's stack frame. 4206 for (unsigned I = Idx; I < ArgRegs.size(); 4207 ++I, VaArgOffset += RegSizeInBytes) { 4208 unsigned Reg = addLiveIn(MF, ArgRegs[I], RC); 4209 SDValue ArgValue = DAG.getCopyFromReg(Chain, DL, Reg, RegTy); 4210 FI = MFI.CreateFixedObject(RegSizeInBytes, VaArgOffset, true); 4211 SDValue PtrOff = DAG.getFrameIndex(FI, getPointerTy(DAG.getDataLayout())); 4212 SDValue Store = 4213 DAG.getStore(Chain, DL, ArgValue, PtrOff, MachinePointerInfo()); 4214 cast<StoreSDNode>(Store.getNode())->getMemOperand()->setValue( 4215 (Value *)nullptr); 4216 OutChains.push_back(Store); 4217 } 4218 } 4219 4220 void MipsTargetLowering::HandleByVal(CCState *State, unsigned &Size, 4221 unsigned Align) const { 4222 const TargetFrameLowering *TFL = Subtarget.getFrameLowering(); 4223 4224 assert(Size && "Byval argument's size shouldn't be 0."); 4225 4226 Align = std::min(Align, TFL->getStackAlignment()); 4227 4228 unsigned FirstReg = 0; 4229 unsigned NumRegs = 0; 4230 4231 if (State->getCallingConv() != CallingConv::Fast) { 4232 unsigned RegSizeInBytes = Subtarget.getGPRSizeInBytes(); 4233 ArrayRef<MCPhysReg> IntArgRegs = ABI.GetByValArgRegs(); 4234 // FIXME: The O32 case actually describes no shadow registers. 4235 const MCPhysReg *ShadowRegs = 4236 ABI.IsO32() ? IntArgRegs.data() : Mips64DPRegs; 4237 4238 // We used to check the size as well but we can't do that anymore since 4239 // CCState::HandleByVal() rounds up the size after calling this function. 4240 assert(!(Align % RegSizeInBytes) && 4241 "Byval argument's alignment should be a multiple of" 4242 "RegSizeInBytes."); 4243 4244 FirstReg = State->getFirstUnallocated(IntArgRegs); 4245 4246 // If Align > RegSizeInBytes, the first arg register must be even. 4247 // FIXME: This condition happens to do the right thing but it's not the 4248 // right way to test it. We want to check that the stack frame offset 4249 // of the register is aligned. 4250 if ((Align > RegSizeInBytes) && (FirstReg % 2)) { 4251 State->AllocateReg(IntArgRegs[FirstReg], ShadowRegs[FirstReg]); 4252 ++FirstReg; 4253 } 4254 4255 // Mark the registers allocated. 4256 Size = alignTo(Size, RegSizeInBytes); 4257 for (unsigned I = FirstReg; Size > 0 && (I < IntArgRegs.size()); 4258 Size -= RegSizeInBytes, ++I, ++NumRegs) 4259 State->AllocateReg(IntArgRegs[I], ShadowRegs[I]); 4260 } 4261 4262 State->addInRegsParamInfo(FirstReg, FirstReg + NumRegs); 4263 } 4264 4265 MachineBasicBlock *MipsTargetLowering::emitPseudoSELECT(MachineInstr &MI, 4266 MachineBasicBlock *BB, 4267 bool isFPCmp, 4268 unsigned Opc) const { 4269 assert(!(Subtarget.hasMips4() || Subtarget.hasMips32()) && 4270 "Subtarget already supports SELECT nodes with the use of" 4271 "conditional-move instructions."); 4272 4273 const TargetInstrInfo *TII = 4274 Subtarget.getInstrInfo(); 4275 DebugLoc DL = MI.getDebugLoc(); 4276 4277 // To "insert" a SELECT instruction, we actually have to insert the 4278 // diamond control-flow pattern. The incoming instruction knows the 4279 // destination vreg to set, the condition code register to branch on, the 4280 // true/false values to select between, and a branch opcode to use. 4281 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 4282 MachineFunction::iterator It = ++BB->getIterator(); 4283 4284 // thisMBB: 4285 // ... 4286 // TrueVal = ... 4287 // setcc r1, r2, r3 4288 // bNE r1, r0, copy1MBB 4289 // fallthrough --> copy0MBB 4290 MachineBasicBlock *thisMBB = BB; 4291 MachineFunction *F = BB->getParent(); 4292 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB); 4293 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB); 4294 F->insert(It, copy0MBB); 4295 F->insert(It, sinkMBB); 4296 4297 // Transfer the remainder of BB and its successor edges to sinkMBB. 4298 sinkMBB->splice(sinkMBB->begin(), BB, 4299 std::next(MachineBasicBlock::iterator(MI)), BB->end()); 4300 sinkMBB->transferSuccessorsAndUpdatePHIs(BB); 4301 4302 // Next, add the true and fallthrough blocks as its successors. 4303 BB->addSuccessor(copy0MBB); 4304 BB->addSuccessor(sinkMBB); 4305 4306 if (isFPCmp) { 4307 // bc1[tf] cc, sinkMBB 4308 BuildMI(BB, DL, TII->get(Opc)) 4309 .addReg(MI.getOperand(1).getReg()) 4310 .addMBB(sinkMBB); 4311 } else { 4312 // bne rs, $0, sinkMBB 4313 BuildMI(BB, DL, TII->get(Opc)) 4314 .addReg(MI.getOperand(1).getReg()) 4315 .addReg(Mips::ZERO) 4316 .addMBB(sinkMBB); 4317 } 4318 4319 // copy0MBB: 4320 // %FalseValue = ... 4321 // # fallthrough to sinkMBB 4322 BB = copy0MBB; 4323 4324 // Update machine-CFG edges 4325 BB->addSuccessor(sinkMBB); 4326 4327 // sinkMBB: 4328 // %Result = phi [ %TrueValue, thisMBB ], [ %FalseValue, copy0MBB ] 4329 // ... 4330 BB = sinkMBB; 4331 4332 BuildMI(*BB, BB->begin(), DL, TII->get(Mips::PHI), MI.getOperand(0).getReg()) 4333 .addReg(MI.getOperand(2).getReg()) 4334 .addMBB(thisMBB) 4335 .addReg(MI.getOperand(3).getReg()) 4336 .addMBB(copy0MBB); 4337 4338 MI.eraseFromParent(); // The pseudo instruction is gone now. 4339 4340 return BB; 4341 } 4342 4343 // FIXME? Maybe this could be a TableGen attribute on some registers and 4344 // this table could be generated automatically from RegInfo. 4345 unsigned MipsTargetLowering::getRegisterByName(const char* RegName, EVT VT, 4346 SelectionDAG &DAG) const { 4347 // Named registers is expected to be fairly rare. For now, just support $28 4348 // since the linux kernel uses it. 4349 if (Subtarget.isGP64bit()) { 4350 unsigned Reg = StringSwitch<unsigned>(RegName) 4351 .Case("$28", Mips::GP_64) 4352 .Default(0); 4353 if (Reg) 4354 return Reg; 4355 } else { 4356 unsigned Reg = StringSwitch<unsigned>(RegName) 4357 .Case("$28", Mips::GP) 4358 .Default(0); 4359 if (Reg) 4360 return Reg; 4361 } 4362 report_fatal_error("Invalid register name global variable"); 4363 } 4364