1 //===-- MipsISelLowering.cpp - Mips DAG Lowering Implementation -----------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file defines the interfaces that Mips uses to lower LLVM code into a 11 // selection DAG. 12 // 13 //===----------------------------------------------------------------------===// 14 #include "MipsISelLowering.h" 15 #include "InstPrinter/MipsInstPrinter.h" 16 #include "MCTargetDesc/MipsBaseInfo.h" 17 #include "MipsCCState.h" 18 #include "MipsMachineFunction.h" 19 #include "MipsSubtarget.h" 20 #include "MipsTargetMachine.h" 21 #include "MipsTargetObjectFile.h" 22 #include "llvm/ADT/Statistic.h" 23 #include "llvm/ADT/StringSwitch.h" 24 #include "llvm/CodeGen/CallingConvLower.h" 25 #include "llvm/CodeGen/MachineFrameInfo.h" 26 #include "llvm/CodeGen/MachineFunction.h" 27 #include "llvm/CodeGen/MachineInstrBuilder.h" 28 #include "llvm/CodeGen/MachineJumpTableInfo.h" 29 #include "llvm/CodeGen/MachineRegisterInfo.h" 30 #include "llvm/CodeGen/SelectionDAGISel.h" 31 #include "llvm/CodeGen/ValueTypes.h" 32 #include "llvm/IR/CallingConv.h" 33 #include "llvm/IR/DerivedTypes.h" 34 #include "llvm/IR/GlobalVariable.h" 35 #include "llvm/Support/CommandLine.h" 36 #include "llvm/Support/Debug.h" 37 #include "llvm/Support/ErrorHandling.h" 38 #include "llvm/Support/raw_ostream.h" 39 #include <cctype> 40 41 using namespace llvm; 42 43 #define DEBUG_TYPE "mips-lower" 44 45 STATISTIC(NumTailCalls, "Number of tail calls"); 46 47 static cl::opt<bool> 48 LargeGOT("mxgot", cl::Hidden, 49 cl::desc("MIPS: Enable GOT larger than 64k."), cl::init(false)); 50 51 static cl::opt<bool> 52 NoZeroDivCheck("mno-check-zero-division", cl::Hidden, 53 cl::desc("MIPS: Don't trap on integer division by zero."), 54 cl::init(false)); 55 56 cl::opt<bool> 57 EnableMipsFastISel("mips-fast-isel", cl::Hidden, 58 cl::desc("Allow mips-fast-isel to be used"), 59 cl::init(false)); 60 61 static const MCPhysReg Mips64DPRegs[8] = { 62 Mips::D12_64, Mips::D13_64, Mips::D14_64, Mips::D15_64, 63 Mips::D16_64, Mips::D17_64, Mips::D18_64, Mips::D19_64 64 }; 65 66 // If I is a shifted mask, set the size (Size) and the first bit of the 67 // mask (Pos), and return true. 68 // For example, if I is 0x003ff800, (Pos, Size) = (11, 11). 69 static bool isShiftedMask(uint64_t I, uint64_t &Pos, uint64_t &Size) { 70 if (!isShiftedMask_64(I)) 71 return false; 72 73 Size = countPopulation(I); 74 Pos = countTrailingZeros(I); 75 return true; 76 } 77 78 SDValue MipsTargetLowering::getGlobalReg(SelectionDAG &DAG, EVT Ty) const { 79 MipsFunctionInfo *FI = DAG.getMachineFunction().getInfo<MipsFunctionInfo>(); 80 return DAG.getRegister(FI->getGlobalBaseReg(), Ty); 81 } 82 83 SDValue MipsTargetLowering::getTargetNode(GlobalAddressSDNode *N, EVT Ty, 84 SelectionDAG &DAG, 85 unsigned Flag) const { 86 return DAG.getTargetGlobalAddress(N->getGlobal(), SDLoc(N), Ty, 0, Flag); 87 } 88 89 SDValue MipsTargetLowering::getTargetNode(ExternalSymbolSDNode *N, EVT Ty, 90 SelectionDAG &DAG, 91 unsigned Flag) const { 92 return DAG.getTargetExternalSymbol(N->getSymbol(), Ty, Flag); 93 } 94 95 SDValue MipsTargetLowering::getTargetNode(BlockAddressSDNode *N, EVT Ty, 96 SelectionDAG &DAG, 97 unsigned Flag) const { 98 return DAG.getTargetBlockAddress(N->getBlockAddress(), Ty, 0, Flag); 99 } 100 101 SDValue MipsTargetLowering::getTargetNode(JumpTableSDNode *N, EVT Ty, 102 SelectionDAG &DAG, 103 unsigned Flag) const { 104 return DAG.getTargetJumpTable(N->getIndex(), Ty, Flag); 105 } 106 107 SDValue MipsTargetLowering::getTargetNode(ConstantPoolSDNode *N, EVT Ty, 108 SelectionDAG &DAG, 109 unsigned Flag) const { 110 return DAG.getTargetConstantPool(N->getConstVal(), Ty, N->getAlignment(), 111 N->getOffset(), Flag); 112 } 113 114 const char *MipsTargetLowering::getTargetNodeName(unsigned Opcode) const { 115 switch ((MipsISD::NodeType)Opcode) { 116 case MipsISD::FIRST_NUMBER: break; 117 case MipsISD::JmpLink: return "MipsISD::JmpLink"; 118 case MipsISD::TailCall: return "MipsISD::TailCall"; 119 case MipsISD::Hi: return "MipsISD::Hi"; 120 case MipsISD::Lo: return "MipsISD::Lo"; 121 case MipsISD::GPRel: return "MipsISD::GPRel"; 122 case MipsISD::ThreadPointer: return "MipsISD::ThreadPointer"; 123 case MipsISD::Ret: return "MipsISD::Ret"; 124 case MipsISD::EH_RETURN: return "MipsISD::EH_RETURN"; 125 case MipsISD::FPBrcond: return "MipsISD::FPBrcond"; 126 case MipsISD::FPCmp: return "MipsISD::FPCmp"; 127 case MipsISD::CMovFP_T: return "MipsISD::CMovFP_T"; 128 case MipsISD::CMovFP_F: return "MipsISD::CMovFP_F"; 129 case MipsISD::TruncIntFP: return "MipsISD::TruncIntFP"; 130 case MipsISD::MFHI: return "MipsISD::MFHI"; 131 case MipsISD::MFLO: return "MipsISD::MFLO"; 132 case MipsISD::MTLOHI: return "MipsISD::MTLOHI"; 133 case MipsISD::Mult: return "MipsISD::Mult"; 134 case MipsISD::Multu: return "MipsISD::Multu"; 135 case MipsISD::MAdd: return "MipsISD::MAdd"; 136 case MipsISD::MAddu: return "MipsISD::MAddu"; 137 case MipsISD::MSub: return "MipsISD::MSub"; 138 case MipsISD::MSubu: return "MipsISD::MSubu"; 139 case MipsISD::DivRem: return "MipsISD::DivRem"; 140 case MipsISD::DivRemU: return "MipsISD::DivRemU"; 141 case MipsISD::DivRem16: return "MipsISD::DivRem16"; 142 case MipsISD::DivRemU16: return "MipsISD::DivRemU16"; 143 case MipsISD::BuildPairF64: return "MipsISD::BuildPairF64"; 144 case MipsISD::ExtractElementF64: return "MipsISD::ExtractElementF64"; 145 case MipsISD::Wrapper: return "MipsISD::Wrapper"; 146 case MipsISD::DynAlloc: return "MipsISD::DynAlloc"; 147 case MipsISD::Sync: return "MipsISD::Sync"; 148 case MipsISD::Ext: return "MipsISD::Ext"; 149 case MipsISD::Ins: return "MipsISD::Ins"; 150 case MipsISD::LWL: return "MipsISD::LWL"; 151 case MipsISD::LWR: return "MipsISD::LWR"; 152 case MipsISD::SWL: return "MipsISD::SWL"; 153 case MipsISD::SWR: return "MipsISD::SWR"; 154 case MipsISD::LDL: return "MipsISD::LDL"; 155 case MipsISD::LDR: return "MipsISD::LDR"; 156 case MipsISD::SDL: return "MipsISD::SDL"; 157 case MipsISD::SDR: return "MipsISD::SDR"; 158 case MipsISD::EXTP: return "MipsISD::EXTP"; 159 case MipsISD::EXTPDP: return "MipsISD::EXTPDP"; 160 case MipsISD::EXTR_S_H: return "MipsISD::EXTR_S_H"; 161 case MipsISD::EXTR_W: return "MipsISD::EXTR_W"; 162 case MipsISD::EXTR_R_W: return "MipsISD::EXTR_R_W"; 163 case MipsISD::EXTR_RS_W: return "MipsISD::EXTR_RS_W"; 164 case MipsISD::SHILO: return "MipsISD::SHILO"; 165 case MipsISD::MTHLIP: return "MipsISD::MTHLIP"; 166 case MipsISD::MULSAQ_S_W_PH: return "MipsISD::MULSAQ_S_W_PH"; 167 case MipsISD::MAQ_S_W_PHL: return "MipsISD::MAQ_S_W_PHL"; 168 case MipsISD::MAQ_S_W_PHR: return "MipsISD::MAQ_S_W_PHR"; 169 case MipsISD::MAQ_SA_W_PHL: return "MipsISD::MAQ_SA_W_PHL"; 170 case MipsISD::MAQ_SA_W_PHR: return "MipsISD::MAQ_SA_W_PHR"; 171 case MipsISD::DPAU_H_QBL: return "MipsISD::DPAU_H_QBL"; 172 case MipsISD::DPAU_H_QBR: return "MipsISD::DPAU_H_QBR"; 173 case MipsISD::DPSU_H_QBL: return "MipsISD::DPSU_H_QBL"; 174 case MipsISD::DPSU_H_QBR: return "MipsISD::DPSU_H_QBR"; 175 case MipsISD::DPAQ_S_W_PH: return "MipsISD::DPAQ_S_W_PH"; 176 case MipsISD::DPSQ_S_W_PH: return "MipsISD::DPSQ_S_W_PH"; 177 case MipsISD::DPAQ_SA_L_W: return "MipsISD::DPAQ_SA_L_W"; 178 case MipsISD::DPSQ_SA_L_W: return "MipsISD::DPSQ_SA_L_W"; 179 case MipsISD::DPA_W_PH: return "MipsISD::DPA_W_PH"; 180 case MipsISD::DPS_W_PH: return "MipsISD::DPS_W_PH"; 181 case MipsISD::DPAQX_S_W_PH: return "MipsISD::DPAQX_S_W_PH"; 182 case MipsISD::DPAQX_SA_W_PH: return "MipsISD::DPAQX_SA_W_PH"; 183 case MipsISD::DPAX_W_PH: return "MipsISD::DPAX_W_PH"; 184 case MipsISD::DPSX_W_PH: return "MipsISD::DPSX_W_PH"; 185 case MipsISD::DPSQX_S_W_PH: return "MipsISD::DPSQX_S_W_PH"; 186 case MipsISD::DPSQX_SA_W_PH: return "MipsISD::DPSQX_SA_W_PH"; 187 case MipsISD::MULSA_W_PH: return "MipsISD::MULSA_W_PH"; 188 case MipsISD::MULT: return "MipsISD::MULT"; 189 case MipsISD::MULTU: return "MipsISD::MULTU"; 190 case MipsISD::MADD_DSP: return "MipsISD::MADD_DSP"; 191 case MipsISD::MADDU_DSP: return "MipsISD::MADDU_DSP"; 192 case MipsISD::MSUB_DSP: return "MipsISD::MSUB_DSP"; 193 case MipsISD::MSUBU_DSP: return "MipsISD::MSUBU_DSP"; 194 case MipsISD::SHLL_DSP: return "MipsISD::SHLL_DSP"; 195 case MipsISD::SHRA_DSP: return "MipsISD::SHRA_DSP"; 196 case MipsISD::SHRL_DSP: return "MipsISD::SHRL_DSP"; 197 case MipsISD::SETCC_DSP: return "MipsISD::SETCC_DSP"; 198 case MipsISD::SELECT_CC_DSP: return "MipsISD::SELECT_CC_DSP"; 199 case MipsISD::VALL_ZERO: return "MipsISD::VALL_ZERO"; 200 case MipsISD::VANY_ZERO: return "MipsISD::VANY_ZERO"; 201 case MipsISD::VALL_NONZERO: return "MipsISD::VALL_NONZERO"; 202 case MipsISD::VANY_NONZERO: return "MipsISD::VANY_NONZERO"; 203 case MipsISD::VCEQ: return "MipsISD::VCEQ"; 204 case MipsISD::VCLE_S: return "MipsISD::VCLE_S"; 205 case MipsISD::VCLE_U: return "MipsISD::VCLE_U"; 206 case MipsISD::VCLT_S: return "MipsISD::VCLT_S"; 207 case MipsISD::VCLT_U: return "MipsISD::VCLT_U"; 208 case MipsISD::VSMAX: return "MipsISD::VSMAX"; 209 case MipsISD::VSMIN: return "MipsISD::VSMIN"; 210 case MipsISD::VUMAX: return "MipsISD::VUMAX"; 211 case MipsISD::VUMIN: return "MipsISD::VUMIN"; 212 case MipsISD::VEXTRACT_SEXT_ELT: return "MipsISD::VEXTRACT_SEXT_ELT"; 213 case MipsISD::VEXTRACT_ZEXT_ELT: return "MipsISD::VEXTRACT_ZEXT_ELT"; 214 case MipsISD::VNOR: return "MipsISD::VNOR"; 215 case MipsISD::VSHF: return "MipsISD::VSHF"; 216 case MipsISD::SHF: return "MipsISD::SHF"; 217 case MipsISD::ILVEV: return "MipsISD::ILVEV"; 218 case MipsISD::ILVOD: return "MipsISD::ILVOD"; 219 case MipsISD::ILVL: return "MipsISD::ILVL"; 220 case MipsISD::ILVR: return "MipsISD::ILVR"; 221 case MipsISD::PCKEV: return "MipsISD::PCKEV"; 222 case MipsISD::PCKOD: return "MipsISD::PCKOD"; 223 case MipsISD::INSVE: return "MipsISD::INSVE"; 224 } 225 return nullptr; 226 } 227 228 MipsTargetLowering::MipsTargetLowering(const MipsTargetMachine &TM, 229 const MipsSubtarget &STI) 230 : TargetLowering(TM), Subtarget(STI), ABI(TM.getABI()) { 231 // Mips does not have i1 type, so use i32 for 232 // setcc operations results (slt, sgt, ...). 233 setBooleanContents(ZeroOrOneBooleanContent); 234 setBooleanVectorContents(ZeroOrNegativeOneBooleanContent); 235 // The cmp.cond.fmt instruction in MIPS32r6/MIPS64r6 uses 0 and -1 like MSA 236 // does. Integer booleans still use 0 and 1. 237 if (Subtarget.hasMips32r6()) 238 setBooleanContents(ZeroOrOneBooleanContent, 239 ZeroOrNegativeOneBooleanContent); 240 241 // Load extented operations for i1 types must be promoted 242 for (MVT VT : MVT::integer_valuetypes()) { 243 setLoadExtAction(ISD::EXTLOAD, VT, MVT::i1, Promote); 244 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i1, Promote); 245 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i1, Promote); 246 } 247 248 // MIPS doesn't have extending float->double load/store. Set LoadExtAction 249 // for f32, f16 250 for (MVT VT : MVT::fp_valuetypes()) { 251 setLoadExtAction(ISD::EXTLOAD, VT, MVT::f32, Expand); 252 setLoadExtAction(ISD::EXTLOAD, VT, MVT::f16, Expand); 253 } 254 255 // Set LoadExtAction for f16 vectors to Expand 256 for (MVT VT : MVT::fp_vector_valuetypes()) { 257 MVT F16VT = MVT::getVectorVT(MVT::f16, VT.getVectorNumElements()); 258 if (F16VT.isValid()) 259 setLoadExtAction(ISD::EXTLOAD, VT, F16VT, Expand); 260 } 261 262 setTruncStoreAction(MVT::f32, MVT::f16, Expand); 263 setTruncStoreAction(MVT::f64, MVT::f16, Expand); 264 265 setTruncStoreAction(MVT::f64, MVT::f32, Expand); 266 267 // Used by legalize types to correctly generate the setcc result. 268 // Without this, every float setcc comes with a AND/OR with the result, 269 // we don't want this, since the fpcmp result goes to a flag register, 270 // which is used implicitly by brcond and select operations. 271 AddPromotedToType(ISD::SETCC, MVT::i1, MVT::i32); 272 273 // Mips Custom Operations 274 setOperationAction(ISD::BR_JT, MVT::Other, Custom); 275 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom); 276 setOperationAction(ISD::BlockAddress, MVT::i32, Custom); 277 setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom); 278 setOperationAction(ISD::JumpTable, MVT::i32, Custom); 279 setOperationAction(ISD::ConstantPool, MVT::i32, Custom); 280 setOperationAction(ISD::SELECT, MVT::f32, Custom); 281 setOperationAction(ISD::SELECT, MVT::f64, Custom); 282 setOperationAction(ISD::SELECT, MVT::i32, Custom); 283 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom); 284 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom); 285 setOperationAction(ISD::SETCC, MVT::f32, Custom); 286 setOperationAction(ISD::SETCC, MVT::f64, Custom); 287 setOperationAction(ISD::BRCOND, MVT::Other, Custom); 288 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom); 289 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom); 290 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom); 291 292 if (Subtarget.isGP64bit()) { 293 setOperationAction(ISD::GlobalAddress, MVT::i64, Custom); 294 setOperationAction(ISD::BlockAddress, MVT::i64, Custom); 295 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom); 296 setOperationAction(ISD::JumpTable, MVT::i64, Custom); 297 setOperationAction(ISD::ConstantPool, MVT::i64, Custom); 298 setOperationAction(ISD::SELECT, MVT::i64, Custom); 299 setOperationAction(ISD::LOAD, MVT::i64, Custom); 300 setOperationAction(ISD::STORE, MVT::i64, Custom); 301 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom); 302 setOperationAction(ISD::SHL_PARTS, MVT::i64, Custom); 303 setOperationAction(ISD::SRA_PARTS, MVT::i64, Custom); 304 setOperationAction(ISD::SRL_PARTS, MVT::i64, Custom); 305 } 306 307 if (!Subtarget.isGP64bit()) { 308 setOperationAction(ISD::SHL_PARTS, MVT::i32, Custom); 309 setOperationAction(ISD::SRA_PARTS, MVT::i32, Custom); 310 setOperationAction(ISD::SRL_PARTS, MVT::i32, Custom); 311 } 312 313 setOperationAction(ISD::ADD, MVT::i32, Custom); 314 if (Subtarget.isGP64bit()) 315 setOperationAction(ISD::ADD, MVT::i64, Custom); 316 317 setOperationAction(ISD::SDIV, MVT::i32, Expand); 318 setOperationAction(ISD::SREM, MVT::i32, Expand); 319 setOperationAction(ISD::UDIV, MVT::i32, Expand); 320 setOperationAction(ISD::UREM, MVT::i32, Expand); 321 setOperationAction(ISD::SDIV, MVT::i64, Expand); 322 setOperationAction(ISD::SREM, MVT::i64, Expand); 323 setOperationAction(ISD::UDIV, MVT::i64, Expand); 324 setOperationAction(ISD::UREM, MVT::i64, Expand); 325 326 // Operations not directly supported by Mips. 327 setOperationAction(ISD::BR_CC, MVT::f32, Expand); 328 setOperationAction(ISD::BR_CC, MVT::f64, Expand); 329 setOperationAction(ISD::BR_CC, MVT::i32, Expand); 330 setOperationAction(ISD::BR_CC, MVT::i64, Expand); 331 setOperationAction(ISD::SELECT_CC, MVT::i32, Expand); 332 setOperationAction(ISD::SELECT_CC, MVT::i64, Expand); 333 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand); 334 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Expand); 335 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand); 336 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Expand); 337 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand); 338 if (Subtarget.hasCnMips()) { 339 setOperationAction(ISD::CTPOP, MVT::i32, Legal); 340 setOperationAction(ISD::CTPOP, MVT::i64, Legal); 341 } else { 342 setOperationAction(ISD::CTPOP, MVT::i32, Expand); 343 setOperationAction(ISD::CTPOP, MVT::i64, Expand); 344 } 345 setOperationAction(ISD::CTTZ, MVT::i32, Expand); 346 setOperationAction(ISD::CTTZ, MVT::i64, Expand); 347 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32, Expand); 348 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i64, Expand); 349 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32, Expand); 350 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Expand); 351 setOperationAction(ISD::ROTL, MVT::i32, Expand); 352 setOperationAction(ISD::ROTL, MVT::i64, Expand); 353 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Expand); 354 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64, Expand); 355 356 if (!Subtarget.hasMips32r2()) 357 setOperationAction(ISD::ROTR, MVT::i32, Expand); 358 359 if (!Subtarget.hasMips64r2()) 360 setOperationAction(ISD::ROTR, MVT::i64, Expand); 361 362 setOperationAction(ISD::FSIN, MVT::f32, Expand); 363 setOperationAction(ISD::FSIN, MVT::f64, Expand); 364 setOperationAction(ISD::FCOS, MVT::f32, Expand); 365 setOperationAction(ISD::FCOS, MVT::f64, Expand); 366 setOperationAction(ISD::FSINCOS, MVT::f32, Expand); 367 setOperationAction(ISD::FSINCOS, MVT::f64, Expand); 368 setOperationAction(ISD::FPOWI, MVT::f32, Expand); 369 setOperationAction(ISD::FPOW, MVT::f32, Expand); 370 setOperationAction(ISD::FPOW, MVT::f64, Expand); 371 setOperationAction(ISD::FLOG, MVT::f32, Expand); 372 setOperationAction(ISD::FLOG2, MVT::f32, Expand); 373 setOperationAction(ISD::FLOG10, MVT::f32, Expand); 374 setOperationAction(ISD::FEXP, MVT::f32, Expand); 375 setOperationAction(ISD::FMA, MVT::f32, Expand); 376 setOperationAction(ISD::FMA, MVT::f64, Expand); 377 setOperationAction(ISD::FREM, MVT::f32, Expand); 378 setOperationAction(ISD::FREM, MVT::f64, Expand); 379 380 // Lower f16 conversion operations into library calls 381 setOperationAction(ISD::FP16_TO_FP, MVT::f32, Expand); 382 setOperationAction(ISD::FP_TO_FP16, MVT::f32, Expand); 383 setOperationAction(ISD::FP16_TO_FP, MVT::f64, Expand); 384 setOperationAction(ISD::FP_TO_FP16, MVT::f64, Expand); 385 386 setOperationAction(ISD::EH_RETURN, MVT::Other, Custom); 387 388 setOperationAction(ISD::VASTART, MVT::Other, Custom); 389 setOperationAction(ISD::VAARG, MVT::Other, Custom); 390 setOperationAction(ISD::VACOPY, MVT::Other, Expand); 391 setOperationAction(ISD::VAEND, MVT::Other, Expand); 392 393 // Use the default for now 394 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand); 395 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand); 396 397 setOperationAction(ISD::ATOMIC_LOAD, MVT::i32, Expand); 398 setOperationAction(ISD::ATOMIC_LOAD, MVT::i64, Expand); 399 setOperationAction(ISD::ATOMIC_STORE, MVT::i32, Expand); 400 setOperationAction(ISD::ATOMIC_STORE, MVT::i64, Expand); 401 402 setInsertFencesForAtomic(true); 403 404 if (!Subtarget.hasMips32r2()) { 405 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8, Expand); 406 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand); 407 } 408 409 // MIPS16 lacks MIPS32's clz and clo instructions. 410 if (!Subtarget.hasMips32() || Subtarget.inMips16Mode()) 411 setOperationAction(ISD::CTLZ, MVT::i32, Expand); 412 if (!Subtarget.hasMips64()) 413 setOperationAction(ISD::CTLZ, MVT::i64, Expand); 414 415 if (!Subtarget.hasMips32r2()) 416 setOperationAction(ISD::BSWAP, MVT::i32, Expand); 417 if (!Subtarget.hasMips64r2()) 418 setOperationAction(ISD::BSWAP, MVT::i64, Expand); 419 420 if (Subtarget.isGP64bit()) { 421 setLoadExtAction(ISD::SEXTLOAD, MVT::i64, MVT::i32, Custom); 422 setLoadExtAction(ISD::ZEXTLOAD, MVT::i64, MVT::i32, Custom); 423 setLoadExtAction(ISD::EXTLOAD, MVT::i64, MVT::i32, Custom); 424 setTruncStoreAction(MVT::i64, MVT::i32, Custom); 425 } 426 427 setOperationAction(ISD::TRAP, MVT::Other, Legal); 428 429 setTargetDAGCombine(ISD::SDIVREM); 430 setTargetDAGCombine(ISD::UDIVREM); 431 setTargetDAGCombine(ISD::SELECT); 432 setTargetDAGCombine(ISD::AND); 433 setTargetDAGCombine(ISD::OR); 434 setTargetDAGCombine(ISD::ADD); 435 436 setMinFunctionAlignment(Subtarget.isGP64bit() ? 3 : 2); 437 438 // The arguments on the stack are defined in terms of 4-byte slots on O32 439 // and 8-byte slots on N32/N64. 440 setMinStackArgumentAlignment((ABI.IsN32() || ABI.IsN64()) ? 8 : 4); 441 442 setStackPointerRegisterToSaveRestore(ABI.IsN64() ? Mips::SP_64 : Mips::SP); 443 444 setExceptionPointerRegister(ABI.IsN64() ? Mips::A0_64 : Mips::A0); 445 setExceptionSelectorRegister(ABI.IsN64() ? Mips::A1_64 : Mips::A1); 446 447 MaxStoresPerMemcpy = 16; 448 449 isMicroMips = Subtarget.inMicroMipsMode(); 450 } 451 452 const MipsTargetLowering *MipsTargetLowering::create(const MipsTargetMachine &TM, 453 const MipsSubtarget &STI) { 454 if (STI.inMips16Mode()) 455 return llvm::createMips16TargetLowering(TM, STI); 456 457 return llvm::createMipsSETargetLowering(TM, STI); 458 } 459 460 // Create a fast isel object. 461 FastISel * 462 MipsTargetLowering::createFastISel(FunctionLoweringInfo &funcInfo, 463 const TargetLibraryInfo *libInfo) const { 464 if (!EnableMipsFastISel) 465 return TargetLowering::createFastISel(funcInfo, libInfo); 466 return Mips::createFastISel(funcInfo, libInfo); 467 } 468 469 EVT MipsTargetLowering::getSetCCResultType(const DataLayout &, LLVMContext &, 470 EVT VT) const { 471 if (!VT.isVector()) 472 return MVT::i32; 473 return VT.changeVectorElementTypeToInteger(); 474 } 475 476 static SDValue performDivRemCombine(SDNode *N, SelectionDAG &DAG, 477 TargetLowering::DAGCombinerInfo &DCI, 478 const MipsSubtarget &Subtarget) { 479 if (DCI.isBeforeLegalizeOps()) 480 return SDValue(); 481 482 EVT Ty = N->getValueType(0); 483 unsigned LO = (Ty == MVT::i32) ? Mips::LO0 : Mips::LO0_64; 484 unsigned HI = (Ty == MVT::i32) ? Mips::HI0 : Mips::HI0_64; 485 unsigned Opc = N->getOpcode() == ISD::SDIVREM ? MipsISD::DivRem16 : 486 MipsISD::DivRemU16; 487 SDLoc DL(N); 488 489 SDValue DivRem = DAG.getNode(Opc, DL, MVT::Glue, 490 N->getOperand(0), N->getOperand(1)); 491 SDValue InChain = DAG.getEntryNode(); 492 SDValue InGlue = DivRem; 493 494 // insert MFLO 495 if (N->hasAnyUseOfValue(0)) { 496 SDValue CopyFromLo = DAG.getCopyFromReg(InChain, DL, LO, Ty, 497 InGlue); 498 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), CopyFromLo); 499 InChain = CopyFromLo.getValue(1); 500 InGlue = CopyFromLo.getValue(2); 501 } 502 503 // insert MFHI 504 if (N->hasAnyUseOfValue(1)) { 505 SDValue CopyFromHi = DAG.getCopyFromReg(InChain, DL, 506 HI, Ty, InGlue); 507 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), CopyFromHi); 508 } 509 510 return SDValue(); 511 } 512 513 static Mips::CondCode condCodeToFCC(ISD::CondCode CC) { 514 switch (CC) { 515 default: llvm_unreachable("Unknown fp condition code!"); 516 case ISD::SETEQ: 517 case ISD::SETOEQ: return Mips::FCOND_OEQ; 518 case ISD::SETUNE: return Mips::FCOND_UNE; 519 case ISD::SETLT: 520 case ISD::SETOLT: return Mips::FCOND_OLT; 521 case ISD::SETGT: 522 case ISD::SETOGT: return Mips::FCOND_OGT; 523 case ISD::SETLE: 524 case ISD::SETOLE: return Mips::FCOND_OLE; 525 case ISD::SETGE: 526 case ISD::SETOGE: return Mips::FCOND_OGE; 527 case ISD::SETULT: return Mips::FCOND_ULT; 528 case ISD::SETULE: return Mips::FCOND_ULE; 529 case ISD::SETUGT: return Mips::FCOND_UGT; 530 case ISD::SETUGE: return Mips::FCOND_UGE; 531 case ISD::SETUO: return Mips::FCOND_UN; 532 case ISD::SETO: return Mips::FCOND_OR; 533 case ISD::SETNE: 534 case ISD::SETONE: return Mips::FCOND_ONE; 535 case ISD::SETUEQ: return Mips::FCOND_UEQ; 536 } 537 } 538 539 540 /// This function returns true if the floating point conditional branches and 541 /// conditional moves which use condition code CC should be inverted. 542 static bool invertFPCondCodeUser(Mips::CondCode CC) { 543 if (CC >= Mips::FCOND_F && CC <= Mips::FCOND_NGT) 544 return false; 545 546 assert((CC >= Mips::FCOND_T && CC <= Mips::FCOND_GT) && 547 "Illegal Condition Code"); 548 549 return true; 550 } 551 552 // Creates and returns an FPCmp node from a setcc node. 553 // Returns Op if setcc is not a floating point comparison. 554 static SDValue createFPCmp(SelectionDAG &DAG, const SDValue &Op) { 555 // must be a SETCC node 556 if (Op.getOpcode() != ISD::SETCC) 557 return Op; 558 559 SDValue LHS = Op.getOperand(0); 560 561 if (!LHS.getValueType().isFloatingPoint()) 562 return Op; 563 564 SDValue RHS = Op.getOperand(1); 565 SDLoc DL(Op); 566 567 // Assume the 3rd operand is a CondCodeSDNode. Add code to check the type of 568 // node if necessary. 569 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get(); 570 571 return DAG.getNode(MipsISD::FPCmp, DL, MVT::Glue, LHS, RHS, 572 DAG.getConstant(condCodeToFCC(CC), DL, MVT::i32)); 573 } 574 575 // Creates and returns a CMovFPT/F node. 576 static SDValue createCMovFP(SelectionDAG &DAG, SDValue Cond, SDValue True, 577 SDValue False, SDLoc DL) { 578 ConstantSDNode *CC = cast<ConstantSDNode>(Cond.getOperand(2)); 579 bool invert = invertFPCondCodeUser((Mips::CondCode)CC->getSExtValue()); 580 SDValue FCC0 = DAG.getRegister(Mips::FCC0, MVT::i32); 581 582 return DAG.getNode((invert ? MipsISD::CMovFP_F : MipsISD::CMovFP_T), DL, 583 True.getValueType(), True, FCC0, False, Cond); 584 } 585 586 static SDValue performSELECTCombine(SDNode *N, SelectionDAG &DAG, 587 TargetLowering::DAGCombinerInfo &DCI, 588 const MipsSubtarget &Subtarget) { 589 if (DCI.isBeforeLegalizeOps()) 590 return SDValue(); 591 592 SDValue SetCC = N->getOperand(0); 593 594 if ((SetCC.getOpcode() != ISD::SETCC) || 595 !SetCC.getOperand(0).getValueType().isInteger()) 596 return SDValue(); 597 598 SDValue False = N->getOperand(2); 599 EVT FalseTy = False.getValueType(); 600 601 if (!FalseTy.isInteger()) 602 return SDValue(); 603 604 ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(False); 605 606 // If the RHS (False) is 0, we swap the order of the operands 607 // of ISD::SELECT (obviously also inverting the condition) so that we can 608 // take advantage of conditional moves using the $0 register. 609 // Example: 610 // return (a != 0) ? x : 0; 611 // load $reg, x 612 // movz $reg, $0, a 613 if (!FalseC) 614 return SDValue(); 615 616 const SDLoc DL(N); 617 618 if (!FalseC->getZExtValue()) { 619 ISD::CondCode CC = cast<CondCodeSDNode>(SetCC.getOperand(2))->get(); 620 SDValue True = N->getOperand(1); 621 622 SetCC = DAG.getSetCC(DL, SetCC.getValueType(), SetCC.getOperand(0), 623 SetCC.getOperand(1), ISD::getSetCCInverse(CC, true)); 624 625 return DAG.getNode(ISD::SELECT, DL, FalseTy, SetCC, False, True); 626 } 627 628 // If both operands are integer constants there's a possibility that we 629 // can do some interesting optimizations. 630 SDValue True = N->getOperand(1); 631 ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(True); 632 633 if (!TrueC || !True.getValueType().isInteger()) 634 return SDValue(); 635 636 // We'll also ignore MVT::i64 operands as this optimizations proves 637 // to be ineffective because of the required sign extensions as the result 638 // of a SETCC operator is always MVT::i32 for non-vector types. 639 if (True.getValueType() == MVT::i64) 640 return SDValue(); 641 642 int64_t Diff = TrueC->getSExtValue() - FalseC->getSExtValue(); 643 644 // 1) (a < x) ? y : y-1 645 // slti $reg1, a, x 646 // addiu $reg2, $reg1, y-1 647 if (Diff == 1) 648 return DAG.getNode(ISD::ADD, DL, SetCC.getValueType(), SetCC, False); 649 650 // 2) (a < x) ? y-1 : y 651 // slti $reg1, a, x 652 // xor $reg1, $reg1, 1 653 // addiu $reg2, $reg1, y-1 654 if (Diff == -1) { 655 ISD::CondCode CC = cast<CondCodeSDNode>(SetCC.getOperand(2))->get(); 656 SetCC = DAG.getSetCC(DL, SetCC.getValueType(), SetCC.getOperand(0), 657 SetCC.getOperand(1), ISD::getSetCCInverse(CC, true)); 658 return DAG.getNode(ISD::ADD, DL, SetCC.getValueType(), SetCC, True); 659 } 660 661 // Couldn't optimize. 662 return SDValue(); 663 } 664 665 static SDValue performCMovFPCombine(SDNode *N, SelectionDAG &DAG, 666 TargetLowering::DAGCombinerInfo &DCI, 667 const MipsSubtarget &Subtarget) { 668 if (DCI.isBeforeLegalizeOps()) 669 return SDValue(); 670 671 SDValue ValueIfTrue = N->getOperand(0), ValueIfFalse = N->getOperand(2); 672 673 ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(ValueIfFalse); 674 if (!FalseC || FalseC->getZExtValue()) 675 return SDValue(); 676 677 // Since RHS (False) is 0, we swap the order of the True/False operands 678 // (obviously also inverting the condition) so that we can 679 // take advantage of conditional moves using the $0 register. 680 // Example: 681 // return (a != 0) ? x : 0; 682 // load $reg, x 683 // movz $reg, $0, a 684 unsigned Opc = (N->getOpcode() == MipsISD::CMovFP_T) ? MipsISD::CMovFP_F : 685 MipsISD::CMovFP_T; 686 687 SDValue FCC = N->getOperand(1), Glue = N->getOperand(3); 688 return DAG.getNode(Opc, SDLoc(N), ValueIfFalse.getValueType(), 689 ValueIfFalse, FCC, ValueIfTrue, Glue); 690 } 691 692 static SDValue performANDCombine(SDNode *N, SelectionDAG &DAG, 693 TargetLowering::DAGCombinerInfo &DCI, 694 const MipsSubtarget &Subtarget) { 695 // Pattern match EXT. 696 // $dst = and ((sra or srl) $src , pos), (2**size - 1) 697 // => ext $dst, $src, size, pos 698 if (DCI.isBeforeLegalizeOps() || !Subtarget.hasExtractInsert()) 699 return SDValue(); 700 701 SDValue ShiftRight = N->getOperand(0), Mask = N->getOperand(1); 702 unsigned ShiftRightOpc = ShiftRight.getOpcode(); 703 704 // Op's first operand must be a shift right. 705 if (ShiftRightOpc != ISD::SRA && ShiftRightOpc != ISD::SRL) 706 return SDValue(); 707 708 // The second operand of the shift must be an immediate. 709 ConstantSDNode *CN; 710 if (!(CN = dyn_cast<ConstantSDNode>(ShiftRight.getOperand(1)))) 711 return SDValue(); 712 713 uint64_t Pos = CN->getZExtValue(); 714 uint64_t SMPos, SMSize; 715 716 // Op's second operand must be a shifted mask. 717 if (!(CN = dyn_cast<ConstantSDNode>(Mask)) || 718 !isShiftedMask(CN->getZExtValue(), SMPos, SMSize)) 719 return SDValue(); 720 721 // Return if the shifted mask does not start at bit 0 or the sum of its size 722 // and Pos exceeds the word's size. 723 EVT ValTy = N->getValueType(0); 724 if (SMPos != 0 || Pos + SMSize > ValTy.getSizeInBits()) 725 return SDValue(); 726 727 SDLoc DL(N); 728 return DAG.getNode(MipsISD::Ext, DL, ValTy, 729 ShiftRight.getOperand(0), 730 DAG.getConstant(Pos, DL, MVT::i32), 731 DAG.getConstant(SMSize, DL, MVT::i32)); 732 } 733 734 static SDValue performORCombine(SDNode *N, SelectionDAG &DAG, 735 TargetLowering::DAGCombinerInfo &DCI, 736 const MipsSubtarget &Subtarget) { 737 // Pattern match INS. 738 // $dst = or (and $src1 , mask0), (and (shl $src, pos), mask1), 739 // where mask1 = (2**size - 1) << pos, mask0 = ~mask1 740 // => ins $dst, $src, size, pos, $src1 741 if (DCI.isBeforeLegalizeOps() || !Subtarget.hasExtractInsert()) 742 return SDValue(); 743 744 SDValue And0 = N->getOperand(0), And1 = N->getOperand(1); 745 uint64_t SMPos0, SMSize0, SMPos1, SMSize1; 746 ConstantSDNode *CN; 747 748 // See if Op's first operand matches (and $src1 , mask0). 749 if (And0.getOpcode() != ISD::AND) 750 return SDValue(); 751 752 if (!(CN = dyn_cast<ConstantSDNode>(And0.getOperand(1))) || 753 !isShiftedMask(~CN->getSExtValue(), SMPos0, SMSize0)) 754 return SDValue(); 755 756 // See if Op's second operand matches (and (shl $src, pos), mask1). 757 if (And1.getOpcode() != ISD::AND) 758 return SDValue(); 759 760 if (!(CN = dyn_cast<ConstantSDNode>(And1.getOperand(1))) || 761 !isShiftedMask(CN->getZExtValue(), SMPos1, SMSize1)) 762 return SDValue(); 763 764 // The shift masks must have the same position and size. 765 if (SMPos0 != SMPos1 || SMSize0 != SMSize1) 766 return SDValue(); 767 768 SDValue Shl = And1.getOperand(0); 769 if (Shl.getOpcode() != ISD::SHL) 770 return SDValue(); 771 772 if (!(CN = dyn_cast<ConstantSDNode>(Shl.getOperand(1)))) 773 return SDValue(); 774 775 unsigned Shamt = CN->getZExtValue(); 776 777 // Return if the shift amount and the first bit position of mask are not the 778 // same. 779 EVT ValTy = N->getValueType(0); 780 if ((Shamt != SMPos0) || (SMPos0 + SMSize0 > ValTy.getSizeInBits())) 781 return SDValue(); 782 783 SDLoc DL(N); 784 return DAG.getNode(MipsISD::Ins, DL, ValTy, Shl.getOperand(0), 785 DAG.getConstant(SMPos0, DL, MVT::i32), 786 DAG.getConstant(SMSize0, DL, MVT::i32), 787 And0.getOperand(0)); 788 } 789 790 static SDValue performADDCombine(SDNode *N, SelectionDAG &DAG, 791 TargetLowering::DAGCombinerInfo &DCI, 792 const MipsSubtarget &Subtarget) { 793 // (add v0, (add v1, abs_lo(tjt))) => (add (add v0, v1), abs_lo(tjt)) 794 795 if (DCI.isBeforeLegalizeOps()) 796 return SDValue(); 797 798 SDValue Add = N->getOperand(1); 799 800 if (Add.getOpcode() != ISD::ADD) 801 return SDValue(); 802 803 SDValue Lo = Add.getOperand(1); 804 805 if ((Lo.getOpcode() != MipsISD::Lo) || 806 (Lo.getOperand(0).getOpcode() != ISD::TargetJumpTable)) 807 return SDValue(); 808 809 EVT ValTy = N->getValueType(0); 810 SDLoc DL(N); 811 812 SDValue Add1 = DAG.getNode(ISD::ADD, DL, ValTy, N->getOperand(0), 813 Add.getOperand(0)); 814 return DAG.getNode(ISD::ADD, DL, ValTy, Add1, Lo); 815 } 816 817 SDValue MipsTargetLowering::PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) 818 const { 819 SelectionDAG &DAG = DCI.DAG; 820 unsigned Opc = N->getOpcode(); 821 822 switch (Opc) { 823 default: break; 824 case ISD::SDIVREM: 825 case ISD::UDIVREM: 826 return performDivRemCombine(N, DAG, DCI, Subtarget); 827 case ISD::SELECT: 828 return performSELECTCombine(N, DAG, DCI, Subtarget); 829 case MipsISD::CMovFP_F: 830 case MipsISD::CMovFP_T: 831 return performCMovFPCombine(N, DAG, DCI, Subtarget); 832 case ISD::AND: 833 return performANDCombine(N, DAG, DCI, Subtarget); 834 case ISD::OR: 835 return performORCombine(N, DAG, DCI, Subtarget); 836 case ISD::ADD: 837 return performADDCombine(N, DAG, DCI, Subtarget); 838 } 839 840 return SDValue(); 841 } 842 843 void 844 MipsTargetLowering::LowerOperationWrapper(SDNode *N, 845 SmallVectorImpl<SDValue> &Results, 846 SelectionDAG &DAG) const { 847 SDValue Res = LowerOperation(SDValue(N, 0), DAG); 848 849 for (unsigned I = 0, E = Res->getNumValues(); I != E; ++I) 850 Results.push_back(Res.getValue(I)); 851 } 852 853 void 854 MipsTargetLowering::ReplaceNodeResults(SDNode *N, 855 SmallVectorImpl<SDValue> &Results, 856 SelectionDAG &DAG) const { 857 return LowerOperationWrapper(N, Results, DAG); 858 } 859 860 SDValue MipsTargetLowering:: 861 LowerOperation(SDValue Op, SelectionDAG &DAG) const 862 { 863 switch (Op.getOpcode()) 864 { 865 case ISD::BR_JT: return lowerBR_JT(Op, DAG); 866 case ISD::BRCOND: return lowerBRCOND(Op, DAG); 867 case ISD::ConstantPool: return lowerConstantPool(Op, DAG); 868 case ISD::GlobalAddress: return lowerGlobalAddress(Op, DAG); 869 case ISD::BlockAddress: return lowerBlockAddress(Op, DAG); 870 case ISD::GlobalTLSAddress: return lowerGlobalTLSAddress(Op, DAG); 871 case ISD::JumpTable: return lowerJumpTable(Op, DAG); 872 case ISD::SELECT: return lowerSELECT(Op, DAG); 873 case ISD::SELECT_CC: return lowerSELECT_CC(Op, DAG); 874 case ISD::SETCC: return lowerSETCC(Op, DAG); 875 case ISD::VASTART: return lowerVASTART(Op, DAG); 876 case ISD::VAARG: return lowerVAARG(Op, DAG); 877 case ISD::FCOPYSIGN: return lowerFCOPYSIGN(Op, DAG); 878 case ISD::FRAMEADDR: return lowerFRAMEADDR(Op, DAG); 879 case ISD::RETURNADDR: return lowerRETURNADDR(Op, DAG); 880 case ISD::EH_RETURN: return lowerEH_RETURN(Op, DAG); 881 case ISD::ATOMIC_FENCE: return lowerATOMIC_FENCE(Op, DAG); 882 case ISD::SHL_PARTS: return lowerShiftLeftParts(Op, DAG); 883 case ISD::SRA_PARTS: return lowerShiftRightParts(Op, DAG, true); 884 case ISD::SRL_PARTS: return lowerShiftRightParts(Op, DAG, false); 885 case ISD::LOAD: return lowerLOAD(Op, DAG); 886 case ISD::STORE: return lowerSTORE(Op, DAG); 887 case ISD::ADD: return lowerADD(Op, DAG); 888 case ISD::FP_TO_SINT: return lowerFP_TO_SINT(Op, DAG); 889 } 890 return SDValue(); 891 } 892 893 //===----------------------------------------------------------------------===// 894 // Lower helper functions 895 //===----------------------------------------------------------------------===// 896 897 // addLiveIn - This helper function adds the specified physical register to the 898 // MachineFunction as a live in value. It also creates a corresponding 899 // virtual register for it. 900 static unsigned 901 addLiveIn(MachineFunction &MF, unsigned PReg, const TargetRegisterClass *RC) 902 { 903 unsigned VReg = MF.getRegInfo().createVirtualRegister(RC); 904 MF.getRegInfo().addLiveIn(PReg, VReg); 905 return VReg; 906 } 907 908 static MachineBasicBlock *insertDivByZeroTrap(MachineInstr *MI, 909 MachineBasicBlock &MBB, 910 const TargetInstrInfo &TII, 911 bool Is64Bit) { 912 if (NoZeroDivCheck) 913 return &MBB; 914 915 // Insert instruction "teq $divisor_reg, $zero, 7". 916 MachineBasicBlock::iterator I(MI); 917 MachineInstrBuilder MIB; 918 MachineOperand &Divisor = MI->getOperand(2); 919 MIB = BuildMI(MBB, std::next(I), MI->getDebugLoc(), TII.get(Mips::TEQ)) 920 .addReg(Divisor.getReg(), getKillRegState(Divisor.isKill())) 921 .addReg(Mips::ZERO).addImm(7); 922 923 // Use the 32-bit sub-register if this is a 64-bit division. 924 if (Is64Bit) 925 MIB->getOperand(0).setSubReg(Mips::sub_32); 926 927 // Clear Divisor's kill flag. 928 Divisor.setIsKill(false); 929 930 // We would normally delete the original instruction here but in this case 931 // we only needed to inject an additional instruction rather than replace it. 932 933 return &MBB; 934 } 935 936 MachineBasicBlock * 937 MipsTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI, 938 MachineBasicBlock *BB) const { 939 switch (MI->getOpcode()) { 940 default: 941 llvm_unreachable("Unexpected instr type to insert"); 942 case Mips::ATOMIC_LOAD_ADD_I8: 943 return emitAtomicBinaryPartword(MI, BB, 1, Mips::ADDu); 944 case Mips::ATOMIC_LOAD_ADD_I16: 945 return emitAtomicBinaryPartword(MI, BB, 2, Mips::ADDu); 946 case Mips::ATOMIC_LOAD_ADD_I32: 947 return emitAtomicBinary(MI, BB, 4, Mips::ADDu); 948 case Mips::ATOMIC_LOAD_ADD_I64: 949 return emitAtomicBinary(MI, BB, 8, Mips::DADDu); 950 951 case Mips::ATOMIC_LOAD_AND_I8: 952 return emitAtomicBinaryPartword(MI, BB, 1, Mips::AND); 953 case Mips::ATOMIC_LOAD_AND_I16: 954 return emitAtomicBinaryPartword(MI, BB, 2, Mips::AND); 955 case Mips::ATOMIC_LOAD_AND_I32: 956 return emitAtomicBinary(MI, BB, 4, Mips::AND); 957 case Mips::ATOMIC_LOAD_AND_I64: 958 return emitAtomicBinary(MI, BB, 8, Mips::AND64); 959 960 case Mips::ATOMIC_LOAD_OR_I8: 961 return emitAtomicBinaryPartword(MI, BB, 1, Mips::OR); 962 case Mips::ATOMIC_LOAD_OR_I16: 963 return emitAtomicBinaryPartword(MI, BB, 2, Mips::OR); 964 case Mips::ATOMIC_LOAD_OR_I32: 965 return emitAtomicBinary(MI, BB, 4, Mips::OR); 966 case Mips::ATOMIC_LOAD_OR_I64: 967 return emitAtomicBinary(MI, BB, 8, Mips::OR64); 968 969 case Mips::ATOMIC_LOAD_XOR_I8: 970 return emitAtomicBinaryPartword(MI, BB, 1, Mips::XOR); 971 case Mips::ATOMIC_LOAD_XOR_I16: 972 return emitAtomicBinaryPartword(MI, BB, 2, Mips::XOR); 973 case Mips::ATOMIC_LOAD_XOR_I32: 974 return emitAtomicBinary(MI, BB, 4, Mips::XOR); 975 case Mips::ATOMIC_LOAD_XOR_I64: 976 return emitAtomicBinary(MI, BB, 8, Mips::XOR64); 977 978 case Mips::ATOMIC_LOAD_NAND_I8: 979 return emitAtomicBinaryPartword(MI, BB, 1, 0, true); 980 case Mips::ATOMIC_LOAD_NAND_I16: 981 return emitAtomicBinaryPartword(MI, BB, 2, 0, true); 982 case Mips::ATOMIC_LOAD_NAND_I32: 983 return emitAtomicBinary(MI, BB, 4, 0, true); 984 case Mips::ATOMIC_LOAD_NAND_I64: 985 return emitAtomicBinary(MI, BB, 8, 0, true); 986 987 case Mips::ATOMIC_LOAD_SUB_I8: 988 return emitAtomicBinaryPartword(MI, BB, 1, Mips::SUBu); 989 case Mips::ATOMIC_LOAD_SUB_I16: 990 return emitAtomicBinaryPartword(MI, BB, 2, Mips::SUBu); 991 case Mips::ATOMIC_LOAD_SUB_I32: 992 return emitAtomicBinary(MI, BB, 4, Mips::SUBu); 993 case Mips::ATOMIC_LOAD_SUB_I64: 994 return emitAtomicBinary(MI, BB, 8, Mips::DSUBu); 995 996 case Mips::ATOMIC_SWAP_I8: 997 return emitAtomicBinaryPartword(MI, BB, 1, 0); 998 case Mips::ATOMIC_SWAP_I16: 999 return emitAtomicBinaryPartword(MI, BB, 2, 0); 1000 case Mips::ATOMIC_SWAP_I32: 1001 return emitAtomicBinary(MI, BB, 4, 0); 1002 case Mips::ATOMIC_SWAP_I64: 1003 return emitAtomicBinary(MI, BB, 8, 0); 1004 1005 case Mips::ATOMIC_CMP_SWAP_I8: 1006 return emitAtomicCmpSwapPartword(MI, BB, 1); 1007 case Mips::ATOMIC_CMP_SWAP_I16: 1008 return emitAtomicCmpSwapPartword(MI, BB, 2); 1009 case Mips::ATOMIC_CMP_SWAP_I32: 1010 return emitAtomicCmpSwap(MI, BB, 4); 1011 case Mips::ATOMIC_CMP_SWAP_I64: 1012 return emitAtomicCmpSwap(MI, BB, 8); 1013 case Mips::PseudoSDIV: 1014 case Mips::PseudoUDIV: 1015 case Mips::DIV: 1016 case Mips::DIVU: 1017 case Mips::MOD: 1018 case Mips::MODU: 1019 return insertDivByZeroTrap(MI, *BB, *Subtarget.getInstrInfo(), false); 1020 case Mips::PseudoDSDIV: 1021 case Mips::PseudoDUDIV: 1022 case Mips::DDIV: 1023 case Mips::DDIVU: 1024 case Mips::DMOD: 1025 case Mips::DMODU: 1026 return insertDivByZeroTrap(MI, *BB, *Subtarget.getInstrInfo(), true); 1027 case Mips::SEL_D: 1028 return emitSEL_D(MI, BB); 1029 1030 case Mips::PseudoSELECT_I: 1031 case Mips::PseudoSELECT_I64: 1032 case Mips::PseudoSELECT_S: 1033 case Mips::PseudoSELECT_D32: 1034 case Mips::PseudoSELECT_D64: 1035 return emitPseudoSELECT(MI, BB, false, Mips::BNE); 1036 case Mips::PseudoSELECTFP_F_I: 1037 case Mips::PseudoSELECTFP_F_I64: 1038 case Mips::PseudoSELECTFP_F_S: 1039 case Mips::PseudoSELECTFP_F_D32: 1040 case Mips::PseudoSELECTFP_F_D64: 1041 return emitPseudoSELECT(MI, BB, true, Mips::BC1F); 1042 case Mips::PseudoSELECTFP_T_I: 1043 case Mips::PseudoSELECTFP_T_I64: 1044 case Mips::PseudoSELECTFP_T_S: 1045 case Mips::PseudoSELECTFP_T_D32: 1046 case Mips::PseudoSELECTFP_T_D64: 1047 return emitPseudoSELECT(MI, BB, true, Mips::BC1T); 1048 } 1049 } 1050 1051 // This function also handles Mips::ATOMIC_SWAP_I32 (when BinOpcode == 0), and 1052 // Mips::ATOMIC_LOAD_NAND_I32 (when Nand == true) 1053 MachineBasicBlock * 1054 MipsTargetLowering::emitAtomicBinary(MachineInstr *MI, MachineBasicBlock *BB, 1055 unsigned Size, unsigned BinOpcode, 1056 bool Nand) const { 1057 assert((Size == 4 || Size == 8) && "Unsupported size for EmitAtomicBinary."); 1058 1059 MachineFunction *MF = BB->getParent(); 1060 MachineRegisterInfo &RegInfo = MF->getRegInfo(); 1061 const TargetRegisterClass *RC = getRegClassFor(MVT::getIntegerVT(Size * 8)); 1062 const TargetInstrInfo *TII = Subtarget.getInstrInfo(); 1063 DebugLoc DL = MI->getDebugLoc(); 1064 unsigned LL, SC, AND, NOR, ZERO, BEQ; 1065 1066 if (Size == 4) { 1067 if (isMicroMips) { 1068 LL = Mips::LL_MM; 1069 SC = Mips::SC_MM; 1070 } else { 1071 LL = Subtarget.hasMips32r6() ? Mips::LL_R6 : Mips::LL; 1072 SC = Subtarget.hasMips32r6() ? Mips::SC_R6 : Mips::SC; 1073 } 1074 AND = Mips::AND; 1075 NOR = Mips::NOR; 1076 ZERO = Mips::ZERO; 1077 BEQ = Mips::BEQ; 1078 } else { 1079 LL = Subtarget.hasMips64r6() ? Mips::LLD_R6 : Mips::LLD; 1080 SC = Subtarget.hasMips64r6() ? Mips::SCD_R6 : Mips::SCD; 1081 AND = Mips::AND64; 1082 NOR = Mips::NOR64; 1083 ZERO = Mips::ZERO_64; 1084 BEQ = Mips::BEQ64; 1085 } 1086 1087 unsigned OldVal = MI->getOperand(0).getReg(); 1088 unsigned Ptr = MI->getOperand(1).getReg(); 1089 unsigned Incr = MI->getOperand(2).getReg(); 1090 1091 unsigned StoreVal = RegInfo.createVirtualRegister(RC); 1092 unsigned AndRes = RegInfo.createVirtualRegister(RC); 1093 unsigned Success = RegInfo.createVirtualRegister(RC); 1094 1095 // insert new blocks after the current block 1096 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 1097 MachineBasicBlock *loopMBB = MF->CreateMachineBasicBlock(LLVM_BB); 1098 MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB); 1099 MachineFunction::iterator It = BB; 1100 ++It; 1101 MF->insert(It, loopMBB); 1102 MF->insert(It, exitMBB); 1103 1104 // Transfer the remainder of BB and its successor edges to exitMBB. 1105 exitMBB->splice(exitMBB->begin(), BB, 1106 std::next(MachineBasicBlock::iterator(MI)), BB->end()); 1107 exitMBB->transferSuccessorsAndUpdatePHIs(BB); 1108 1109 // thisMBB: 1110 // ... 1111 // fallthrough --> loopMBB 1112 BB->addSuccessor(loopMBB); 1113 loopMBB->addSuccessor(loopMBB); 1114 loopMBB->addSuccessor(exitMBB); 1115 1116 // loopMBB: 1117 // ll oldval, 0(ptr) 1118 // <binop> storeval, oldval, incr 1119 // sc success, storeval, 0(ptr) 1120 // beq success, $0, loopMBB 1121 BB = loopMBB; 1122 BuildMI(BB, DL, TII->get(LL), OldVal).addReg(Ptr).addImm(0); 1123 if (Nand) { 1124 // and andres, oldval, incr 1125 // nor storeval, $0, andres 1126 BuildMI(BB, DL, TII->get(AND), AndRes).addReg(OldVal).addReg(Incr); 1127 BuildMI(BB, DL, TII->get(NOR), StoreVal).addReg(ZERO).addReg(AndRes); 1128 } else if (BinOpcode) { 1129 // <binop> storeval, oldval, incr 1130 BuildMI(BB, DL, TII->get(BinOpcode), StoreVal).addReg(OldVal).addReg(Incr); 1131 } else { 1132 StoreVal = Incr; 1133 } 1134 BuildMI(BB, DL, TII->get(SC), Success).addReg(StoreVal).addReg(Ptr).addImm(0); 1135 BuildMI(BB, DL, TII->get(BEQ)).addReg(Success).addReg(ZERO).addMBB(loopMBB); 1136 1137 MI->eraseFromParent(); // The instruction is gone now. 1138 1139 return exitMBB; 1140 } 1141 1142 MachineBasicBlock *MipsTargetLowering::emitSignExtendToI32InReg( 1143 MachineInstr *MI, MachineBasicBlock *BB, unsigned Size, unsigned DstReg, 1144 unsigned SrcReg) const { 1145 const TargetInstrInfo *TII = Subtarget.getInstrInfo(); 1146 DebugLoc DL = MI->getDebugLoc(); 1147 1148 if (Subtarget.hasMips32r2() && Size == 1) { 1149 BuildMI(BB, DL, TII->get(Mips::SEB), DstReg).addReg(SrcReg); 1150 return BB; 1151 } 1152 1153 if (Subtarget.hasMips32r2() && Size == 2) { 1154 BuildMI(BB, DL, TII->get(Mips::SEH), DstReg).addReg(SrcReg); 1155 return BB; 1156 } 1157 1158 MachineFunction *MF = BB->getParent(); 1159 MachineRegisterInfo &RegInfo = MF->getRegInfo(); 1160 const TargetRegisterClass *RC = getRegClassFor(MVT::i32); 1161 unsigned ScrReg = RegInfo.createVirtualRegister(RC); 1162 1163 assert(Size < 32); 1164 int64_t ShiftImm = 32 - (Size * 8); 1165 1166 BuildMI(BB, DL, TII->get(Mips::SLL), ScrReg).addReg(SrcReg).addImm(ShiftImm); 1167 BuildMI(BB, DL, TII->get(Mips::SRA), DstReg).addReg(ScrReg).addImm(ShiftImm); 1168 1169 return BB; 1170 } 1171 1172 MachineBasicBlock *MipsTargetLowering::emitAtomicBinaryPartword( 1173 MachineInstr *MI, MachineBasicBlock *BB, unsigned Size, unsigned BinOpcode, 1174 bool Nand) const { 1175 assert((Size == 1 || Size == 2) && 1176 "Unsupported size for EmitAtomicBinaryPartial."); 1177 1178 MachineFunction *MF = BB->getParent(); 1179 MachineRegisterInfo &RegInfo = MF->getRegInfo(); 1180 const TargetRegisterClass *RC = getRegClassFor(MVT::i32); 1181 const TargetInstrInfo *TII = Subtarget.getInstrInfo(); 1182 DebugLoc DL = MI->getDebugLoc(); 1183 1184 unsigned Dest = MI->getOperand(0).getReg(); 1185 unsigned Ptr = MI->getOperand(1).getReg(); 1186 unsigned Incr = MI->getOperand(2).getReg(); 1187 1188 unsigned AlignedAddr = RegInfo.createVirtualRegister(RC); 1189 unsigned ShiftAmt = RegInfo.createVirtualRegister(RC); 1190 unsigned Mask = RegInfo.createVirtualRegister(RC); 1191 unsigned Mask2 = RegInfo.createVirtualRegister(RC); 1192 unsigned NewVal = RegInfo.createVirtualRegister(RC); 1193 unsigned OldVal = RegInfo.createVirtualRegister(RC); 1194 unsigned Incr2 = RegInfo.createVirtualRegister(RC); 1195 unsigned MaskLSB2 = RegInfo.createVirtualRegister(RC); 1196 unsigned PtrLSB2 = RegInfo.createVirtualRegister(RC); 1197 unsigned MaskUpper = RegInfo.createVirtualRegister(RC); 1198 unsigned AndRes = RegInfo.createVirtualRegister(RC); 1199 unsigned BinOpRes = RegInfo.createVirtualRegister(RC); 1200 unsigned MaskedOldVal0 = RegInfo.createVirtualRegister(RC); 1201 unsigned StoreVal = RegInfo.createVirtualRegister(RC); 1202 unsigned MaskedOldVal1 = RegInfo.createVirtualRegister(RC); 1203 unsigned SrlRes = RegInfo.createVirtualRegister(RC); 1204 unsigned Success = RegInfo.createVirtualRegister(RC); 1205 1206 // insert new blocks after the current block 1207 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 1208 MachineBasicBlock *loopMBB = MF->CreateMachineBasicBlock(LLVM_BB); 1209 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(LLVM_BB); 1210 MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB); 1211 MachineFunction::iterator It = BB; 1212 ++It; 1213 MF->insert(It, loopMBB); 1214 MF->insert(It, sinkMBB); 1215 MF->insert(It, exitMBB); 1216 1217 // Transfer the remainder of BB and its successor edges to exitMBB. 1218 exitMBB->splice(exitMBB->begin(), BB, 1219 std::next(MachineBasicBlock::iterator(MI)), BB->end()); 1220 exitMBB->transferSuccessorsAndUpdatePHIs(BB); 1221 1222 BB->addSuccessor(loopMBB); 1223 loopMBB->addSuccessor(loopMBB); 1224 loopMBB->addSuccessor(sinkMBB); 1225 sinkMBB->addSuccessor(exitMBB); 1226 1227 // thisMBB: 1228 // addiu masklsb2,$0,-4 # 0xfffffffc 1229 // and alignedaddr,ptr,masklsb2 1230 // andi ptrlsb2,ptr,3 1231 // sll shiftamt,ptrlsb2,3 1232 // ori maskupper,$0,255 # 0xff 1233 // sll mask,maskupper,shiftamt 1234 // nor mask2,$0,mask 1235 // sll incr2,incr,shiftamt 1236 1237 int64_t MaskImm = (Size == 1) ? 255 : 65535; 1238 BuildMI(BB, DL, TII->get(Mips::ADDiu), MaskLSB2) 1239 .addReg(Mips::ZERO).addImm(-4); 1240 BuildMI(BB, DL, TII->get(Mips::AND), AlignedAddr) 1241 .addReg(Ptr).addReg(MaskLSB2); 1242 BuildMI(BB, DL, TII->get(Mips::ANDi), PtrLSB2).addReg(Ptr).addImm(3); 1243 if (Subtarget.isLittle()) { 1244 BuildMI(BB, DL, TII->get(Mips::SLL), ShiftAmt).addReg(PtrLSB2).addImm(3); 1245 } else { 1246 unsigned Off = RegInfo.createVirtualRegister(RC); 1247 BuildMI(BB, DL, TII->get(Mips::XORi), Off) 1248 .addReg(PtrLSB2).addImm((Size == 1) ? 3 : 2); 1249 BuildMI(BB, DL, TII->get(Mips::SLL), ShiftAmt).addReg(Off).addImm(3); 1250 } 1251 BuildMI(BB, DL, TII->get(Mips::ORi), MaskUpper) 1252 .addReg(Mips::ZERO).addImm(MaskImm); 1253 BuildMI(BB, DL, TII->get(Mips::SLLV), Mask) 1254 .addReg(MaskUpper).addReg(ShiftAmt); 1255 BuildMI(BB, DL, TII->get(Mips::NOR), Mask2).addReg(Mips::ZERO).addReg(Mask); 1256 BuildMI(BB, DL, TII->get(Mips::SLLV), Incr2).addReg(Incr).addReg(ShiftAmt); 1257 1258 // atomic.load.binop 1259 // loopMBB: 1260 // ll oldval,0(alignedaddr) 1261 // binop binopres,oldval,incr2 1262 // and newval,binopres,mask 1263 // and maskedoldval0,oldval,mask2 1264 // or storeval,maskedoldval0,newval 1265 // sc success,storeval,0(alignedaddr) 1266 // beq success,$0,loopMBB 1267 1268 // atomic.swap 1269 // loopMBB: 1270 // ll oldval,0(alignedaddr) 1271 // and newval,incr2,mask 1272 // and maskedoldval0,oldval,mask2 1273 // or storeval,maskedoldval0,newval 1274 // sc success,storeval,0(alignedaddr) 1275 // beq success,$0,loopMBB 1276 1277 BB = loopMBB; 1278 unsigned LL = isMicroMips ? Mips::LL_MM : Mips::LL; 1279 BuildMI(BB, DL, TII->get(LL), OldVal).addReg(AlignedAddr).addImm(0); 1280 if (Nand) { 1281 // and andres, oldval, incr2 1282 // nor binopres, $0, andres 1283 // and newval, binopres, mask 1284 BuildMI(BB, DL, TII->get(Mips::AND), AndRes).addReg(OldVal).addReg(Incr2); 1285 BuildMI(BB, DL, TII->get(Mips::NOR), BinOpRes) 1286 .addReg(Mips::ZERO).addReg(AndRes); 1287 BuildMI(BB, DL, TII->get(Mips::AND), NewVal).addReg(BinOpRes).addReg(Mask); 1288 } else if (BinOpcode) { 1289 // <binop> binopres, oldval, incr2 1290 // and newval, binopres, mask 1291 BuildMI(BB, DL, TII->get(BinOpcode), BinOpRes).addReg(OldVal).addReg(Incr2); 1292 BuildMI(BB, DL, TII->get(Mips::AND), NewVal).addReg(BinOpRes).addReg(Mask); 1293 } else { // atomic.swap 1294 // and newval, incr2, mask 1295 BuildMI(BB, DL, TII->get(Mips::AND), NewVal).addReg(Incr2).addReg(Mask); 1296 } 1297 1298 BuildMI(BB, DL, TII->get(Mips::AND), MaskedOldVal0) 1299 .addReg(OldVal).addReg(Mask2); 1300 BuildMI(BB, DL, TII->get(Mips::OR), StoreVal) 1301 .addReg(MaskedOldVal0).addReg(NewVal); 1302 unsigned SC = isMicroMips ? Mips::SC_MM : Mips::SC; 1303 BuildMI(BB, DL, TII->get(SC), Success) 1304 .addReg(StoreVal).addReg(AlignedAddr).addImm(0); 1305 BuildMI(BB, DL, TII->get(Mips::BEQ)) 1306 .addReg(Success).addReg(Mips::ZERO).addMBB(loopMBB); 1307 1308 // sinkMBB: 1309 // and maskedoldval1,oldval,mask 1310 // srl srlres,maskedoldval1,shiftamt 1311 // sign_extend dest,srlres 1312 BB = sinkMBB; 1313 1314 BuildMI(BB, DL, TII->get(Mips::AND), MaskedOldVal1) 1315 .addReg(OldVal).addReg(Mask); 1316 BuildMI(BB, DL, TII->get(Mips::SRLV), SrlRes) 1317 .addReg(MaskedOldVal1).addReg(ShiftAmt); 1318 BB = emitSignExtendToI32InReg(MI, BB, Size, Dest, SrlRes); 1319 1320 MI->eraseFromParent(); // The instruction is gone now. 1321 1322 return exitMBB; 1323 } 1324 1325 MachineBasicBlock * MipsTargetLowering::emitAtomicCmpSwap(MachineInstr *MI, 1326 MachineBasicBlock *BB, 1327 unsigned Size) const { 1328 assert((Size == 4 || Size == 8) && "Unsupported size for EmitAtomicCmpSwap."); 1329 1330 MachineFunction *MF = BB->getParent(); 1331 MachineRegisterInfo &RegInfo = MF->getRegInfo(); 1332 const TargetRegisterClass *RC = getRegClassFor(MVT::getIntegerVT(Size * 8)); 1333 const TargetInstrInfo *TII = Subtarget.getInstrInfo(); 1334 DebugLoc DL = MI->getDebugLoc(); 1335 unsigned LL, SC, ZERO, BNE, BEQ; 1336 1337 if (Size == 4) { 1338 LL = isMicroMips ? Mips::LL_MM : Mips::LL; 1339 SC = isMicroMips ? Mips::SC_MM : Mips::SC; 1340 ZERO = Mips::ZERO; 1341 BNE = Mips::BNE; 1342 BEQ = Mips::BEQ; 1343 } else { 1344 LL = Mips::LLD; 1345 SC = Mips::SCD; 1346 ZERO = Mips::ZERO_64; 1347 BNE = Mips::BNE64; 1348 BEQ = Mips::BEQ64; 1349 } 1350 1351 unsigned Dest = MI->getOperand(0).getReg(); 1352 unsigned Ptr = MI->getOperand(1).getReg(); 1353 unsigned OldVal = MI->getOperand(2).getReg(); 1354 unsigned NewVal = MI->getOperand(3).getReg(); 1355 1356 unsigned Success = RegInfo.createVirtualRegister(RC); 1357 1358 // insert new blocks after the current block 1359 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 1360 MachineBasicBlock *loop1MBB = MF->CreateMachineBasicBlock(LLVM_BB); 1361 MachineBasicBlock *loop2MBB = MF->CreateMachineBasicBlock(LLVM_BB); 1362 MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB); 1363 MachineFunction::iterator It = BB; 1364 ++It; 1365 MF->insert(It, loop1MBB); 1366 MF->insert(It, loop2MBB); 1367 MF->insert(It, exitMBB); 1368 1369 // Transfer the remainder of BB and its successor edges to exitMBB. 1370 exitMBB->splice(exitMBB->begin(), BB, 1371 std::next(MachineBasicBlock::iterator(MI)), BB->end()); 1372 exitMBB->transferSuccessorsAndUpdatePHIs(BB); 1373 1374 // thisMBB: 1375 // ... 1376 // fallthrough --> loop1MBB 1377 BB->addSuccessor(loop1MBB); 1378 loop1MBB->addSuccessor(exitMBB); 1379 loop1MBB->addSuccessor(loop2MBB); 1380 loop2MBB->addSuccessor(loop1MBB); 1381 loop2MBB->addSuccessor(exitMBB); 1382 1383 // loop1MBB: 1384 // ll dest, 0(ptr) 1385 // bne dest, oldval, exitMBB 1386 BB = loop1MBB; 1387 BuildMI(BB, DL, TII->get(LL), Dest).addReg(Ptr).addImm(0); 1388 BuildMI(BB, DL, TII->get(BNE)) 1389 .addReg(Dest).addReg(OldVal).addMBB(exitMBB); 1390 1391 // loop2MBB: 1392 // sc success, newval, 0(ptr) 1393 // beq success, $0, loop1MBB 1394 BB = loop2MBB; 1395 BuildMI(BB, DL, TII->get(SC), Success) 1396 .addReg(NewVal).addReg(Ptr).addImm(0); 1397 BuildMI(BB, DL, TII->get(BEQ)) 1398 .addReg(Success).addReg(ZERO).addMBB(loop1MBB); 1399 1400 MI->eraseFromParent(); // The instruction is gone now. 1401 1402 return exitMBB; 1403 } 1404 1405 MachineBasicBlock * 1406 MipsTargetLowering::emitAtomicCmpSwapPartword(MachineInstr *MI, 1407 MachineBasicBlock *BB, 1408 unsigned Size) const { 1409 assert((Size == 1 || Size == 2) && 1410 "Unsupported size for EmitAtomicCmpSwapPartial."); 1411 1412 MachineFunction *MF = BB->getParent(); 1413 MachineRegisterInfo &RegInfo = MF->getRegInfo(); 1414 const TargetRegisterClass *RC = getRegClassFor(MVT::i32); 1415 const TargetInstrInfo *TII = Subtarget.getInstrInfo(); 1416 DebugLoc DL = MI->getDebugLoc(); 1417 1418 unsigned Dest = MI->getOperand(0).getReg(); 1419 unsigned Ptr = MI->getOperand(1).getReg(); 1420 unsigned CmpVal = MI->getOperand(2).getReg(); 1421 unsigned NewVal = MI->getOperand(3).getReg(); 1422 1423 unsigned AlignedAddr = RegInfo.createVirtualRegister(RC); 1424 unsigned ShiftAmt = RegInfo.createVirtualRegister(RC); 1425 unsigned Mask = RegInfo.createVirtualRegister(RC); 1426 unsigned Mask2 = RegInfo.createVirtualRegister(RC); 1427 unsigned ShiftedCmpVal = RegInfo.createVirtualRegister(RC); 1428 unsigned OldVal = RegInfo.createVirtualRegister(RC); 1429 unsigned MaskedOldVal0 = RegInfo.createVirtualRegister(RC); 1430 unsigned ShiftedNewVal = RegInfo.createVirtualRegister(RC); 1431 unsigned MaskLSB2 = RegInfo.createVirtualRegister(RC); 1432 unsigned PtrLSB2 = RegInfo.createVirtualRegister(RC); 1433 unsigned MaskUpper = RegInfo.createVirtualRegister(RC); 1434 unsigned MaskedCmpVal = RegInfo.createVirtualRegister(RC); 1435 unsigned MaskedNewVal = RegInfo.createVirtualRegister(RC); 1436 unsigned MaskedOldVal1 = RegInfo.createVirtualRegister(RC); 1437 unsigned StoreVal = RegInfo.createVirtualRegister(RC); 1438 unsigned SrlRes = RegInfo.createVirtualRegister(RC); 1439 unsigned Success = RegInfo.createVirtualRegister(RC); 1440 1441 // insert new blocks after the current block 1442 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 1443 MachineBasicBlock *loop1MBB = MF->CreateMachineBasicBlock(LLVM_BB); 1444 MachineBasicBlock *loop2MBB = MF->CreateMachineBasicBlock(LLVM_BB); 1445 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(LLVM_BB); 1446 MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB); 1447 MachineFunction::iterator It = BB; 1448 ++It; 1449 MF->insert(It, loop1MBB); 1450 MF->insert(It, loop2MBB); 1451 MF->insert(It, sinkMBB); 1452 MF->insert(It, exitMBB); 1453 1454 // Transfer the remainder of BB and its successor edges to exitMBB. 1455 exitMBB->splice(exitMBB->begin(), BB, 1456 std::next(MachineBasicBlock::iterator(MI)), BB->end()); 1457 exitMBB->transferSuccessorsAndUpdatePHIs(BB); 1458 1459 BB->addSuccessor(loop1MBB); 1460 loop1MBB->addSuccessor(sinkMBB); 1461 loop1MBB->addSuccessor(loop2MBB); 1462 loop2MBB->addSuccessor(loop1MBB); 1463 loop2MBB->addSuccessor(sinkMBB); 1464 sinkMBB->addSuccessor(exitMBB); 1465 1466 // FIXME: computation of newval2 can be moved to loop2MBB. 1467 // thisMBB: 1468 // addiu masklsb2,$0,-4 # 0xfffffffc 1469 // and alignedaddr,ptr,masklsb2 1470 // andi ptrlsb2,ptr,3 1471 // sll shiftamt,ptrlsb2,3 1472 // ori maskupper,$0,255 # 0xff 1473 // sll mask,maskupper,shiftamt 1474 // nor mask2,$0,mask 1475 // andi maskedcmpval,cmpval,255 1476 // sll shiftedcmpval,maskedcmpval,shiftamt 1477 // andi maskednewval,newval,255 1478 // sll shiftednewval,maskednewval,shiftamt 1479 int64_t MaskImm = (Size == 1) ? 255 : 65535; 1480 BuildMI(BB, DL, TII->get(Mips::ADDiu), MaskLSB2) 1481 .addReg(Mips::ZERO).addImm(-4); 1482 BuildMI(BB, DL, TII->get(Mips::AND), AlignedAddr) 1483 .addReg(Ptr).addReg(MaskLSB2); 1484 BuildMI(BB, DL, TII->get(Mips::ANDi), PtrLSB2).addReg(Ptr).addImm(3); 1485 if (Subtarget.isLittle()) { 1486 BuildMI(BB, DL, TII->get(Mips::SLL), ShiftAmt).addReg(PtrLSB2).addImm(3); 1487 } else { 1488 unsigned Off = RegInfo.createVirtualRegister(RC); 1489 BuildMI(BB, DL, TII->get(Mips::XORi), Off) 1490 .addReg(PtrLSB2).addImm((Size == 1) ? 3 : 2); 1491 BuildMI(BB, DL, TII->get(Mips::SLL), ShiftAmt).addReg(Off).addImm(3); 1492 } 1493 BuildMI(BB, DL, TII->get(Mips::ORi), MaskUpper) 1494 .addReg(Mips::ZERO).addImm(MaskImm); 1495 BuildMI(BB, DL, TII->get(Mips::SLLV), Mask) 1496 .addReg(MaskUpper).addReg(ShiftAmt); 1497 BuildMI(BB, DL, TII->get(Mips::NOR), Mask2).addReg(Mips::ZERO).addReg(Mask); 1498 BuildMI(BB, DL, TII->get(Mips::ANDi), MaskedCmpVal) 1499 .addReg(CmpVal).addImm(MaskImm); 1500 BuildMI(BB, DL, TII->get(Mips::SLLV), ShiftedCmpVal) 1501 .addReg(MaskedCmpVal).addReg(ShiftAmt); 1502 BuildMI(BB, DL, TII->get(Mips::ANDi), MaskedNewVal) 1503 .addReg(NewVal).addImm(MaskImm); 1504 BuildMI(BB, DL, TII->get(Mips::SLLV), ShiftedNewVal) 1505 .addReg(MaskedNewVal).addReg(ShiftAmt); 1506 1507 // loop1MBB: 1508 // ll oldval,0(alginedaddr) 1509 // and maskedoldval0,oldval,mask 1510 // bne maskedoldval0,shiftedcmpval,sinkMBB 1511 BB = loop1MBB; 1512 unsigned LL = isMicroMips ? Mips::LL_MM : Mips::LL; 1513 BuildMI(BB, DL, TII->get(LL), OldVal).addReg(AlignedAddr).addImm(0); 1514 BuildMI(BB, DL, TII->get(Mips::AND), MaskedOldVal0) 1515 .addReg(OldVal).addReg(Mask); 1516 BuildMI(BB, DL, TII->get(Mips::BNE)) 1517 .addReg(MaskedOldVal0).addReg(ShiftedCmpVal).addMBB(sinkMBB); 1518 1519 // loop2MBB: 1520 // and maskedoldval1,oldval,mask2 1521 // or storeval,maskedoldval1,shiftednewval 1522 // sc success,storeval,0(alignedaddr) 1523 // beq success,$0,loop1MBB 1524 BB = loop2MBB; 1525 BuildMI(BB, DL, TII->get(Mips::AND), MaskedOldVal1) 1526 .addReg(OldVal).addReg(Mask2); 1527 BuildMI(BB, DL, TII->get(Mips::OR), StoreVal) 1528 .addReg(MaskedOldVal1).addReg(ShiftedNewVal); 1529 unsigned SC = isMicroMips ? Mips::SC_MM : Mips::SC; 1530 BuildMI(BB, DL, TII->get(SC), Success) 1531 .addReg(StoreVal).addReg(AlignedAddr).addImm(0); 1532 BuildMI(BB, DL, TII->get(Mips::BEQ)) 1533 .addReg(Success).addReg(Mips::ZERO).addMBB(loop1MBB); 1534 1535 // sinkMBB: 1536 // srl srlres,maskedoldval0,shiftamt 1537 // sign_extend dest,srlres 1538 BB = sinkMBB; 1539 1540 BuildMI(BB, DL, TII->get(Mips::SRLV), SrlRes) 1541 .addReg(MaskedOldVal0).addReg(ShiftAmt); 1542 BB = emitSignExtendToI32InReg(MI, BB, Size, Dest, SrlRes); 1543 1544 MI->eraseFromParent(); // The instruction is gone now. 1545 1546 return exitMBB; 1547 } 1548 1549 MachineBasicBlock *MipsTargetLowering::emitSEL_D(MachineInstr *MI, 1550 MachineBasicBlock *BB) const { 1551 MachineFunction *MF = BB->getParent(); 1552 const TargetRegisterInfo *TRI = Subtarget.getRegisterInfo(); 1553 const TargetInstrInfo *TII = Subtarget.getInstrInfo(); 1554 MachineRegisterInfo &RegInfo = MF->getRegInfo(); 1555 DebugLoc DL = MI->getDebugLoc(); 1556 MachineBasicBlock::iterator II(MI); 1557 1558 unsigned Fc = MI->getOperand(1).getReg(); 1559 const auto &FGR64RegClass = TRI->getRegClass(Mips::FGR64RegClassID); 1560 1561 unsigned Fc2 = RegInfo.createVirtualRegister(FGR64RegClass); 1562 1563 BuildMI(*BB, II, DL, TII->get(Mips::SUBREG_TO_REG), Fc2) 1564 .addImm(0) 1565 .addReg(Fc) 1566 .addImm(Mips::sub_lo); 1567 1568 // We don't erase the original instruction, we just replace the condition 1569 // register with the 64-bit super-register. 1570 MI->getOperand(1).setReg(Fc2); 1571 1572 return BB; 1573 } 1574 1575 //===----------------------------------------------------------------------===// 1576 // Misc Lower Operation implementation 1577 //===----------------------------------------------------------------------===// 1578 SDValue MipsTargetLowering::lowerBR_JT(SDValue Op, SelectionDAG &DAG) const { 1579 SDValue Chain = Op.getOperand(0); 1580 SDValue Table = Op.getOperand(1); 1581 SDValue Index = Op.getOperand(2); 1582 SDLoc DL(Op); 1583 auto &TD = DAG.getDataLayout(); 1584 EVT PTy = getPointerTy(TD); 1585 unsigned EntrySize = 1586 DAG.getMachineFunction().getJumpTableInfo()->getEntrySize(TD); 1587 1588 Index = DAG.getNode(ISD::MUL, DL, PTy, Index, 1589 DAG.getConstant(EntrySize, DL, PTy)); 1590 SDValue Addr = DAG.getNode(ISD::ADD, DL, PTy, Index, Table); 1591 1592 EVT MemVT = EVT::getIntegerVT(*DAG.getContext(), EntrySize * 8); 1593 Addr = DAG.getExtLoad(ISD::SEXTLOAD, DL, PTy, Chain, Addr, 1594 MachinePointerInfo::getJumpTable(), MemVT, false, false, 1595 false, 0); 1596 Chain = Addr.getValue(1); 1597 1598 if ((getTargetMachine().getRelocationModel() == Reloc::PIC_) || ABI.IsN64()) { 1599 // For PIC, the sequence is: 1600 // BRIND(load(Jumptable + index) + RelocBase) 1601 // RelocBase can be JumpTable, GOT or some sort of global base. 1602 Addr = DAG.getNode(ISD::ADD, DL, PTy, Addr, 1603 getPICJumpTableRelocBase(Table, DAG)); 1604 } 1605 1606 return DAG.getNode(ISD::BRIND, DL, MVT::Other, Chain, Addr); 1607 } 1608 1609 SDValue MipsTargetLowering::lowerBRCOND(SDValue Op, SelectionDAG &DAG) const { 1610 // The first operand is the chain, the second is the condition, the third is 1611 // the block to branch to if the condition is true. 1612 SDValue Chain = Op.getOperand(0); 1613 SDValue Dest = Op.getOperand(2); 1614 SDLoc DL(Op); 1615 1616 assert(!Subtarget.hasMips32r6() && !Subtarget.hasMips64r6()); 1617 SDValue CondRes = createFPCmp(DAG, Op.getOperand(1)); 1618 1619 // Return if flag is not set by a floating point comparison. 1620 if (CondRes.getOpcode() != MipsISD::FPCmp) 1621 return Op; 1622 1623 SDValue CCNode = CondRes.getOperand(2); 1624 Mips::CondCode CC = 1625 (Mips::CondCode)cast<ConstantSDNode>(CCNode)->getZExtValue(); 1626 unsigned Opc = invertFPCondCodeUser(CC) ? Mips::BRANCH_F : Mips::BRANCH_T; 1627 SDValue BrCode = DAG.getConstant(Opc, DL, MVT::i32); 1628 SDValue FCC0 = DAG.getRegister(Mips::FCC0, MVT::i32); 1629 return DAG.getNode(MipsISD::FPBrcond, DL, Op.getValueType(), Chain, BrCode, 1630 FCC0, Dest, CondRes); 1631 } 1632 1633 SDValue MipsTargetLowering:: 1634 lowerSELECT(SDValue Op, SelectionDAG &DAG) const 1635 { 1636 assert(!Subtarget.hasMips32r6() && !Subtarget.hasMips64r6()); 1637 SDValue Cond = createFPCmp(DAG, Op.getOperand(0)); 1638 1639 // Return if flag is not set by a floating point comparison. 1640 if (Cond.getOpcode() != MipsISD::FPCmp) 1641 return Op; 1642 1643 return createCMovFP(DAG, Cond, Op.getOperand(1), Op.getOperand(2), 1644 SDLoc(Op)); 1645 } 1646 1647 SDValue MipsTargetLowering:: 1648 lowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const 1649 { 1650 SDLoc DL(Op); 1651 EVT Ty = Op.getOperand(0).getValueType(); 1652 SDValue Cond = 1653 DAG.getNode(ISD::SETCC, DL, getSetCCResultType(DAG.getDataLayout(), 1654 *DAG.getContext(), Ty), 1655 Op.getOperand(0), Op.getOperand(1), Op.getOperand(4)); 1656 1657 return DAG.getNode(ISD::SELECT, DL, Op.getValueType(), Cond, Op.getOperand(2), 1658 Op.getOperand(3)); 1659 } 1660 1661 SDValue MipsTargetLowering::lowerSETCC(SDValue Op, SelectionDAG &DAG) const { 1662 assert(!Subtarget.hasMips32r6() && !Subtarget.hasMips64r6()); 1663 SDValue Cond = createFPCmp(DAG, Op); 1664 1665 assert(Cond.getOpcode() == MipsISD::FPCmp && 1666 "Floating point operand expected."); 1667 1668 SDLoc DL(Op); 1669 SDValue True = DAG.getConstant(1, DL, MVT::i32); 1670 SDValue False = DAG.getConstant(0, DL, MVT::i32); 1671 1672 return createCMovFP(DAG, Cond, True, False, DL); 1673 } 1674 1675 SDValue MipsTargetLowering::lowerGlobalAddress(SDValue Op, 1676 SelectionDAG &DAG) const { 1677 EVT Ty = Op.getValueType(); 1678 GlobalAddressSDNode *N = cast<GlobalAddressSDNode>(Op); 1679 const GlobalValue *GV = N->getGlobal(); 1680 1681 if (getTargetMachine().getRelocationModel() != Reloc::PIC_ && !ABI.IsN64()) { 1682 const MipsTargetObjectFile *TLOF = 1683 static_cast<const MipsTargetObjectFile *>( 1684 getTargetMachine().getObjFileLowering()); 1685 if (TLOF->IsGlobalInSmallSection(GV, getTargetMachine())) 1686 // %gp_rel relocation 1687 return getAddrGPRel(N, SDLoc(N), Ty, DAG); 1688 1689 // %hi/%lo relocation 1690 return getAddrNonPIC(N, SDLoc(N), Ty, DAG); 1691 } 1692 1693 if (GV->hasInternalLinkage() || (GV->hasLocalLinkage() && !isa<Function>(GV))) 1694 return getAddrLocal(N, SDLoc(N), Ty, DAG, ABI.IsN32() || ABI.IsN64()); 1695 1696 if (LargeGOT) 1697 return getAddrGlobalLargeGOT(N, SDLoc(N), Ty, DAG, MipsII::MO_GOT_HI16, 1698 MipsII::MO_GOT_LO16, DAG.getEntryNode(), 1699 MachinePointerInfo::getGOT()); 1700 1701 return getAddrGlobal(N, SDLoc(N), Ty, DAG, 1702 (ABI.IsN32() || ABI.IsN64()) ? MipsII::MO_GOT_DISP 1703 : MipsII::MO_GOT16, 1704 DAG.getEntryNode(), MachinePointerInfo::getGOT()); 1705 } 1706 1707 SDValue MipsTargetLowering::lowerBlockAddress(SDValue Op, 1708 SelectionDAG &DAG) const { 1709 BlockAddressSDNode *N = cast<BlockAddressSDNode>(Op); 1710 EVT Ty = Op.getValueType(); 1711 1712 if (getTargetMachine().getRelocationModel() != Reloc::PIC_ && !ABI.IsN64()) 1713 return getAddrNonPIC(N, SDLoc(N), Ty, DAG); 1714 1715 return getAddrLocal(N, SDLoc(N), Ty, DAG, ABI.IsN32() || ABI.IsN64()); 1716 } 1717 1718 SDValue MipsTargetLowering:: 1719 lowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const 1720 { 1721 // If the relocation model is PIC, use the General Dynamic TLS Model or 1722 // Local Dynamic TLS model, otherwise use the Initial Exec or 1723 // Local Exec TLS Model. 1724 1725 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op); 1726 SDLoc DL(GA); 1727 const GlobalValue *GV = GA->getGlobal(); 1728 EVT PtrVT = getPointerTy(DAG.getDataLayout()); 1729 1730 TLSModel::Model model = getTargetMachine().getTLSModel(GV); 1731 1732 if (model == TLSModel::GeneralDynamic || model == TLSModel::LocalDynamic) { 1733 // General Dynamic and Local Dynamic TLS Model. 1734 unsigned Flag = (model == TLSModel::LocalDynamic) ? MipsII::MO_TLSLDM 1735 : MipsII::MO_TLSGD; 1736 1737 SDValue TGA = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, Flag); 1738 SDValue Argument = DAG.getNode(MipsISD::Wrapper, DL, PtrVT, 1739 getGlobalReg(DAG, PtrVT), TGA); 1740 unsigned PtrSize = PtrVT.getSizeInBits(); 1741 IntegerType *PtrTy = Type::getIntNTy(*DAG.getContext(), PtrSize); 1742 1743 SDValue TlsGetAddr = DAG.getExternalSymbol("__tls_get_addr", PtrVT); 1744 1745 ArgListTy Args; 1746 ArgListEntry Entry; 1747 Entry.Node = Argument; 1748 Entry.Ty = PtrTy; 1749 Args.push_back(Entry); 1750 1751 TargetLowering::CallLoweringInfo CLI(DAG); 1752 CLI.setDebugLoc(DL).setChain(DAG.getEntryNode()) 1753 .setCallee(CallingConv::C, PtrTy, TlsGetAddr, std::move(Args), 0); 1754 std::pair<SDValue, SDValue> CallResult = LowerCallTo(CLI); 1755 1756 SDValue Ret = CallResult.first; 1757 1758 if (model != TLSModel::LocalDynamic) 1759 return Ret; 1760 1761 SDValue TGAHi = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, 1762 MipsII::MO_DTPREL_HI); 1763 SDValue Hi = DAG.getNode(MipsISD::Hi, DL, PtrVT, TGAHi); 1764 SDValue TGALo = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, 1765 MipsII::MO_DTPREL_LO); 1766 SDValue Lo = DAG.getNode(MipsISD::Lo, DL, PtrVT, TGALo); 1767 SDValue Add = DAG.getNode(ISD::ADD, DL, PtrVT, Hi, Ret); 1768 return DAG.getNode(ISD::ADD, DL, PtrVT, Add, Lo); 1769 } 1770 1771 SDValue Offset; 1772 if (model == TLSModel::InitialExec) { 1773 // Initial Exec TLS Model 1774 SDValue TGA = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, 1775 MipsII::MO_GOTTPREL); 1776 TGA = DAG.getNode(MipsISD::Wrapper, DL, PtrVT, getGlobalReg(DAG, PtrVT), 1777 TGA); 1778 Offset = DAG.getLoad(PtrVT, DL, 1779 DAG.getEntryNode(), TGA, MachinePointerInfo(), 1780 false, false, false, 0); 1781 } else { 1782 // Local Exec TLS Model 1783 assert(model == TLSModel::LocalExec); 1784 SDValue TGAHi = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, 1785 MipsII::MO_TPREL_HI); 1786 SDValue TGALo = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, 1787 MipsII::MO_TPREL_LO); 1788 SDValue Hi = DAG.getNode(MipsISD::Hi, DL, PtrVT, TGAHi); 1789 SDValue Lo = DAG.getNode(MipsISD::Lo, DL, PtrVT, TGALo); 1790 Offset = DAG.getNode(ISD::ADD, DL, PtrVT, Hi, Lo); 1791 } 1792 1793 SDValue ThreadPointer = DAG.getNode(MipsISD::ThreadPointer, DL, PtrVT); 1794 return DAG.getNode(ISD::ADD, DL, PtrVT, ThreadPointer, Offset); 1795 } 1796 1797 SDValue MipsTargetLowering:: 1798 lowerJumpTable(SDValue Op, SelectionDAG &DAG) const 1799 { 1800 JumpTableSDNode *N = cast<JumpTableSDNode>(Op); 1801 EVT Ty = Op.getValueType(); 1802 1803 if (getTargetMachine().getRelocationModel() != Reloc::PIC_ && !ABI.IsN64()) 1804 return getAddrNonPIC(N, SDLoc(N), Ty, DAG); 1805 1806 return getAddrLocal(N, SDLoc(N), Ty, DAG, ABI.IsN32() || ABI.IsN64()); 1807 } 1808 1809 SDValue MipsTargetLowering:: 1810 lowerConstantPool(SDValue Op, SelectionDAG &DAG) const 1811 { 1812 ConstantPoolSDNode *N = cast<ConstantPoolSDNode>(Op); 1813 EVT Ty = Op.getValueType(); 1814 1815 if (getTargetMachine().getRelocationModel() != Reloc::PIC_ && !ABI.IsN64()) { 1816 const MipsTargetObjectFile *TLOF = 1817 static_cast<const MipsTargetObjectFile *>( 1818 getTargetMachine().getObjFileLowering()); 1819 1820 if (TLOF->IsConstantInSmallSection(N->getConstVal(), getTargetMachine())) 1821 // %gp_rel relocation 1822 return getAddrGPRel(N, SDLoc(N), Ty, DAG); 1823 1824 return getAddrNonPIC(N, SDLoc(N), Ty, DAG); 1825 } 1826 1827 return getAddrLocal(N, SDLoc(N), Ty, DAG, ABI.IsN32() || ABI.IsN64()); 1828 } 1829 1830 SDValue MipsTargetLowering::lowerVASTART(SDValue Op, SelectionDAG &DAG) const { 1831 MachineFunction &MF = DAG.getMachineFunction(); 1832 MipsFunctionInfo *FuncInfo = MF.getInfo<MipsFunctionInfo>(); 1833 1834 SDLoc DL(Op); 1835 SDValue FI = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), 1836 getPointerTy(MF.getDataLayout())); 1837 1838 // vastart just stores the address of the VarArgsFrameIndex slot into the 1839 // memory location argument. 1840 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue(); 1841 return DAG.getStore(Op.getOperand(0), DL, FI, Op.getOperand(1), 1842 MachinePointerInfo(SV), false, false, 0); 1843 } 1844 1845 SDValue MipsTargetLowering::lowerVAARG(SDValue Op, SelectionDAG &DAG) const { 1846 SDNode *Node = Op.getNode(); 1847 EVT VT = Node->getValueType(0); 1848 SDValue Chain = Node->getOperand(0); 1849 SDValue VAListPtr = Node->getOperand(1); 1850 unsigned Align = Node->getConstantOperandVal(3); 1851 const Value *SV = cast<SrcValueSDNode>(Node->getOperand(2))->getValue(); 1852 SDLoc DL(Node); 1853 unsigned ArgSlotSizeInBytes = (ABI.IsN32() || ABI.IsN64()) ? 8 : 4; 1854 1855 SDValue VAListLoad = 1856 DAG.getLoad(getPointerTy(DAG.getDataLayout()), DL, Chain, VAListPtr, 1857 MachinePointerInfo(SV), false, false, false, 0); 1858 SDValue VAList = VAListLoad; 1859 1860 // Re-align the pointer if necessary. 1861 // It should only ever be necessary for 64-bit types on O32 since the minimum 1862 // argument alignment is the same as the maximum type alignment for N32/N64. 1863 // 1864 // FIXME: We currently align too often. The code generator doesn't notice 1865 // when the pointer is still aligned from the last va_arg (or pair of 1866 // va_args for the i64 on O32 case). 1867 if (Align > getMinStackArgumentAlignment()) { 1868 assert(((Align & (Align-1)) == 0) && "Expected Align to be a power of 2"); 1869 1870 VAList = DAG.getNode(ISD::ADD, DL, VAList.getValueType(), VAList, 1871 DAG.getConstant(Align - 1, DL, VAList.getValueType())); 1872 1873 VAList = DAG.getNode(ISD::AND, DL, VAList.getValueType(), VAList, 1874 DAG.getConstant(-(int64_t)Align, DL, 1875 VAList.getValueType())); 1876 } 1877 1878 // Increment the pointer, VAList, to the next vaarg. 1879 auto &TD = DAG.getDataLayout(); 1880 unsigned ArgSizeInBytes = 1881 TD.getTypeAllocSize(VT.getTypeForEVT(*DAG.getContext())); 1882 SDValue Tmp3 = DAG.getNode(ISD::ADD, DL, VAList.getValueType(), VAList, 1883 DAG.getConstant(RoundUpToAlignment(ArgSizeInBytes, 1884 ArgSlotSizeInBytes), 1885 DL, VAList.getValueType())); 1886 // Store the incremented VAList to the legalized pointer 1887 Chain = DAG.getStore(VAListLoad.getValue(1), DL, Tmp3, VAListPtr, 1888 MachinePointerInfo(SV), false, false, 0); 1889 1890 // In big-endian mode we must adjust the pointer when the load size is smaller 1891 // than the argument slot size. We must also reduce the known alignment to 1892 // match. For example in the N64 ABI, we must add 4 bytes to the offset to get 1893 // the correct half of the slot, and reduce the alignment from 8 (slot 1894 // alignment) down to 4 (type alignment). 1895 if (!Subtarget.isLittle() && ArgSizeInBytes < ArgSlotSizeInBytes) { 1896 unsigned Adjustment = ArgSlotSizeInBytes - ArgSizeInBytes; 1897 VAList = DAG.getNode(ISD::ADD, DL, VAListPtr.getValueType(), VAList, 1898 DAG.getIntPtrConstant(Adjustment, DL)); 1899 } 1900 // Load the actual argument out of the pointer VAList 1901 return DAG.getLoad(VT, DL, Chain, VAList, MachinePointerInfo(), false, false, 1902 false, 0); 1903 } 1904 1905 static SDValue lowerFCOPYSIGN32(SDValue Op, SelectionDAG &DAG, 1906 bool HasExtractInsert) { 1907 EVT TyX = Op.getOperand(0).getValueType(); 1908 EVT TyY = Op.getOperand(1).getValueType(); 1909 SDLoc DL(Op); 1910 SDValue Const1 = DAG.getConstant(1, DL, MVT::i32); 1911 SDValue Const31 = DAG.getConstant(31, DL, MVT::i32); 1912 SDValue Res; 1913 1914 // If operand is of type f64, extract the upper 32-bit. Otherwise, bitcast it 1915 // to i32. 1916 SDValue X = (TyX == MVT::f32) ? 1917 DAG.getNode(ISD::BITCAST, DL, MVT::i32, Op.getOperand(0)) : 1918 DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32, Op.getOperand(0), 1919 Const1); 1920 SDValue Y = (TyY == MVT::f32) ? 1921 DAG.getNode(ISD::BITCAST, DL, MVT::i32, Op.getOperand(1)) : 1922 DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32, Op.getOperand(1), 1923 Const1); 1924 1925 if (HasExtractInsert) { 1926 // ext E, Y, 31, 1 ; extract bit31 of Y 1927 // ins X, E, 31, 1 ; insert extracted bit at bit31 of X 1928 SDValue E = DAG.getNode(MipsISD::Ext, DL, MVT::i32, Y, Const31, Const1); 1929 Res = DAG.getNode(MipsISD::Ins, DL, MVT::i32, E, Const31, Const1, X); 1930 } else { 1931 // sll SllX, X, 1 1932 // srl SrlX, SllX, 1 1933 // srl SrlY, Y, 31 1934 // sll SllY, SrlX, 31 1935 // or Or, SrlX, SllY 1936 SDValue SllX = DAG.getNode(ISD::SHL, DL, MVT::i32, X, Const1); 1937 SDValue SrlX = DAG.getNode(ISD::SRL, DL, MVT::i32, SllX, Const1); 1938 SDValue SrlY = DAG.getNode(ISD::SRL, DL, MVT::i32, Y, Const31); 1939 SDValue SllY = DAG.getNode(ISD::SHL, DL, MVT::i32, SrlY, Const31); 1940 Res = DAG.getNode(ISD::OR, DL, MVT::i32, SrlX, SllY); 1941 } 1942 1943 if (TyX == MVT::f32) 1944 return DAG.getNode(ISD::BITCAST, DL, Op.getOperand(0).getValueType(), Res); 1945 1946 SDValue LowX = DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32, 1947 Op.getOperand(0), 1948 DAG.getConstant(0, DL, MVT::i32)); 1949 return DAG.getNode(MipsISD::BuildPairF64, DL, MVT::f64, LowX, Res); 1950 } 1951 1952 static SDValue lowerFCOPYSIGN64(SDValue Op, SelectionDAG &DAG, 1953 bool HasExtractInsert) { 1954 unsigned WidthX = Op.getOperand(0).getValueSizeInBits(); 1955 unsigned WidthY = Op.getOperand(1).getValueSizeInBits(); 1956 EVT TyX = MVT::getIntegerVT(WidthX), TyY = MVT::getIntegerVT(WidthY); 1957 SDLoc DL(Op); 1958 SDValue Const1 = DAG.getConstant(1, DL, MVT::i32); 1959 1960 // Bitcast to integer nodes. 1961 SDValue X = DAG.getNode(ISD::BITCAST, DL, TyX, Op.getOperand(0)); 1962 SDValue Y = DAG.getNode(ISD::BITCAST, DL, TyY, Op.getOperand(1)); 1963 1964 if (HasExtractInsert) { 1965 // ext E, Y, width(Y) - 1, 1 ; extract bit width(Y)-1 of Y 1966 // ins X, E, width(X) - 1, 1 ; insert extracted bit at bit width(X)-1 of X 1967 SDValue E = DAG.getNode(MipsISD::Ext, DL, TyY, Y, 1968 DAG.getConstant(WidthY - 1, DL, MVT::i32), Const1); 1969 1970 if (WidthX > WidthY) 1971 E = DAG.getNode(ISD::ZERO_EXTEND, DL, TyX, E); 1972 else if (WidthY > WidthX) 1973 E = DAG.getNode(ISD::TRUNCATE, DL, TyX, E); 1974 1975 SDValue I = DAG.getNode(MipsISD::Ins, DL, TyX, E, 1976 DAG.getConstant(WidthX - 1, DL, MVT::i32), Const1, 1977 X); 1978 return DAG.getNode(ISD::BITCAST, DL, Op.getOperand(0).getValueType(), I); 1979 } 1980 1981 // (d)sll SllX, X, 1 1982 // (d)srl SrlX, SllX, 1 1983 // (d)srl SrlY, Y, width(Y)-1 1984 // (d)sll SllY, SrlX, width(Y)-1 1985 // or Or, SrlX, SllY 1986 SDValue SllX = DAG.getNode(ISD::SHL, DL, TyX, X, Const1); 1987 SDValue SrlX = DAG.getNode(ISD::SRL, DL, TyX, SllX, Const1); 1988 SDValue SrlY = DAG.getNode(ISD::SRL, DL, TyY, Y, 1989 DAG.getConstant(WidthY - 1, DL, MVT::i32)); 1990 1991 if (WidthX > WidthY) 1992 SrlY = DAG.getNode(ISD::ZERO_EXTEND, DL, TyX, SrlY); 1993 else if (WidthY > WidthX) 1994 SrlY = DAG.getNode(ISD::TRUNCATE, DL, TyX, SrlY); 1995 1996 SDValue SllY = DAG.getNode(ISD::SHL, DL, TyX, SrlY, 1997 DAG.getConstant(WidthX - 1, DL, MVT::i32)); 1998 SDValue Or = DAG.getNode(ISD::OR, DL, TyX, SrlX, SllY); 1999 return DAG.getNode(ISD::BITCAST, DL, Op.getOperand(0).getValueType(), Or); 2000 } 2001 2002 SDValue 2003 MipsTargetLowering::lowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const { 2004 if (Subtarget.isGP64bit()) 2005 return lowerFCOPYSIGN64(Op, DAG, Subtarget.hasExtractInsert()); 2006 2007 return lowerFCOPYSIGN32(Op, DAG, Subtarget.hasExtractInsert()); 2008 } 2009 2010 SDValue MipsTargetLowering:: 2011 lowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const { 2012 // check the depth 2013 assert((cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue() == 0) && 2014 "Frame address can only be determined for current frame."); 2015 2016 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo(); 2017 MFI->setFrameAddressIsTaken(true); 2018 EVT VT = Op.getValueType(); 2019 SDLoc DL(Op); 2020 SDValue FrameAddr = DAG.getCopyFromReg( 2021 DAG.getEntryNode(), DL, ABI.IsN64() ? Mips::FP_64 : Mips::FP, VT); 2022 return FrameAddr; 2023 } 2024 2025 SDValue MipsTargetLowering::lowerRETURNADDR(SDValue Op, 2026 SelectionDAG &DAG) const { 2027 if (verifyReturnAddressArgumentIsConstant(Op, DAG)) 2028 return SDValue(); 2029 2030 // check the depth 2031 assert((cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue() == 0) && 2032 "Return address can be determined only for current frame."); 2033 2034 MachineFunction &MF = DAG.getMachineFunction(); 2035 MachineFrameInfo *MFI = MF.getFrameInfo(); 2036 MVT VT = Op.getSimpleValueType(); 2037 unsigned RA = ABI.IsN64() ? Mips::RA_64 : Mips::RA; 2038 MFI->setReturnAddressIsTaken(true); 2039 2040 // Return RA, which contains the return address. Mark it an implicit live-in. 2041 unsigned Reg = MF.addLiveIn(RA, getRegClassFor(VT)); 2042 return DAG.getCopyFromReg(DAG.getEntryNode(), SDLoc(Op), Reg, VT); 2043 } 2044 2045 // An EH_RETURN is the result of lowering llvm.eh.return which in turn is 2046 // generated from __builtin_eh_return (offset, handler) 2047 // The effect of this is to adjust the stack pointer by "offset" 2048 // and then branch to "handler". 2049 SDValue MipsTargetLowering::lowerEH_RETURN(SDValue Op, SelectionDAG &DAG) 2050 const { 2051 MachineFunction &MF = DAG.getMachineFunction(); 2052 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>(); 2053 2054 MipsFI->setCallsEhReturn(); 2055 SDValue Chain = Op.getOperand(0); 2056 SDValue Offset = Op.getOperand(1); 2057 SDValue Handler = Op.getOperand(2); 2058 SDLoc DL(Op); 2059 EVT Ty = ABI.IsN64() ? MVT::i64 : MVT::i32; 2060 2061 // Store stack offset in V1, store jump target in V0. Glue CopyToReg and 2062 // EH_RETURN nodes, so that instructions are emitted back-to-back. 2063 unsigned OffsetReg = ABI.IsN64() ? Mips::V1_64 : Mips::V1; 2064 unsigned AddrReg = ABI.IsN64() ? Mips::V0_64 : Mips::V0; 2065 Chain = DAG.getCopyToReg(Chain, DL, OffsetReg, Offset, SDValue()); 2066 Chain = DAG.getCopyToReg(Chain, DL, AddrReg, Handler, Chain.getValue(1)); 2067 return DAG.getNode(MipsISD::EH_RETURN, DL, MVT::Other, Chain, 2068 DAG.getRegister(OffsetReg, Ty), 2069 DAG.getRegister(AddrReg, getPointerTy(MF.getDataLayout())), 2070 Chain.getValue(1)); 2071 } 2072 2073 SDValue MipsTargetLowering::lowerATOMIC_FENCE(SDValue Op, 2074 SelectionDAG &DAG) const { 2075 // FIXME: Need pseudo-fence for 'singlethread' fences 2076 // FIXME: Set SType for weaker fences where supported/appropriate. 2077 unsigned SType = 0; 2078 SDLoc DL(Op); 2079 return DAG.getNode(MipsISD::Sync, DL, MVT::Other, Op.getOperand(0), 2080 DAG.getConstant(SType, DL, MVT::i32)); 2081 } 2082 2083 SDValue MipsTargetLowering::lowerShiftLeftParts(SDValue Op, 2084 SelectionDAG &DAG) const { 2085 SDLoc DL(Op); 2086 MVT VT = Subtarget.isGP64bit() ? MVT::i64 : MVT::i32; 2087 2088 SDValue Lo = Op.getOperand(0), Hi = Op.getOperand(1); 2089 SDValue Shamt = Op.getOperand(2); 2090 // if shamt < (VT.bits): 2091 // lo = (shl lo, shamt) 2092 // hi = (or (shl hi, shamt) (srl (srl lo, 1), ~shamt)) 2093 // else: 2094 // lo = 0 2095 // hi = (shl lo, shamt[4:0]) 2096 SDValue Not = DAG.getNode(ISD::XOR, DL, MVT::i32, Shamt, 2097 DAG.getConstant(-1, DL, MVT::i32)); 2098 SDValue ShiftRight1Lo = DAG.getNode(ISD::SRL, DL, VT, Lo, 2099 DAG.getConstant(1, DL, VT)); 2100 SDValue ShiftRightLo = DAG.getNode(ISD::SRL, DL, VT, ShiftRight1Lo, Not); 2101 SDValue ShiftLeftHi = DAG.getNode(ISD::SHL, DL, VT, Hi, Shamt); 2102 SDValue Or = DAG.getNode(ISD::OR, DL, VT, ShiftLeftHi, ShiftRightLo); 2103 SDValue ShiftLeftLo = DAG.getNode(ISD::SHL, DL, VT, Lo, Shamt); 2104 SDValue Cond = DAG.getNode(ISD::AND, DL, MVT::i32, Shamt, 2105 DAG.getConstant(VT.getSizeInBits(), DL, MVT::i32)); 2106 Lo = DAG.getNode(ISD::SELECT, DL, VT, Cond, 2107 DAG.getConstant(0, DL, VT), ShiftLeftLo); 2108 Hi = DAG.getNode(ISD::SELECT, DL, VT, Cond, ShiftLeftLo, Or); 2109 2110 SDValue Ops[2] = {Lo, Hi}; 2111 return DAG.getMergeValues(Ops, DL); 2112 } 2113 2114 SDValue MipsTargetLowering::lowerShiftRightParts(SDValue Op, SelectionDAG &DAG, 2115 bool IsSRA) const { 2116 SDLoc DL(Op); 2117 SDValue Lo = Op.getOperand(0), Hi = Op.getOperand(1); 2118 SDValue Shamt = Op.getOperand(2); 2119 MVT VT = Subtarget.isGP64bit() ? MVT::i64 : MVT::i32; 2120 2121 // if shamt < (VT.bits): 2122 // lo = (or (shl (shl hi, 1), ~shamt) (srl lo, shamt)) 2123 // if isSRA: 2124 // hi = (sra hi, shamt) 2125 // else: 2126 // hi = (srl hi, shamt) 2127 // else: 2128 // if isSRA: 2129 // lo = (sra hi, shamt[4:0]) 2130 // hi = (sra hi, 31) 2131 // else: 2132 // lo = (srl hi, shamt[4:0]) 2133 // hi = 0 2134 SDValue Not = DAG.getNode(ISD::XOR, DL, MVT::i32, Shamt, 2135 DAG.getConstant(-1, DL, MVT::i32)); 2136 SDValue ShiftLeft1Hi = DAG.getNode(ISD::SHL, DL, VT, Hi, 2137 DAG.getConstant(1, DL, VT)); 2138 SDValue ShiftLeftHi = DAG.getNode(ISD::SHL, DL, VT, ShiftLeft1Hi, Not); 2139 SDValue ShiftRightLo = DAG.getNode(ISD::SRL, DL, VT, Lo, Shamt); 2140 SDValue Or = DAG.getNode(ISD::OR, DL, VT, ShiftLeftHi, ShiftRightLo); 2141 SDValue ShiftRightHi = DAG.getNode(IsSRA ? ISD::SRA : ISD::SRL, 2142 DL, VT, Hi, Shamt); 2143 SDValue Cond = DAG.getNode(ISD::AND, DL, MVT::i32, Shamt, 2144 DAG.getConstant(VT.getSizeInBits(), DL, MVT::i32)); 2145 SDValue Ext = DAG.getNode(ISD::SRA, DL, VT, Hi, 2146 DAG.getConstant(VT.getSizeInBits() - 1, DL, VT)); 2147 Lo = DAG.getNode(ISD::SELECT, DL, VT, Cond, ShiftRightHi, Or); 2148 Hi = DAG.getNode(ISD::SELECT, DL, VT, Cond, 2149 IsSRA ? Ext : DAG.getConstant(0, DL, VT), ShiftRightHi); 2150 2151 SDValue Ops[2] = {Lo, Hi}; 2152 return DAG.getMergeValues(Ops, DL); 2153 } 2154 2155 static SDValue createLoadLR(unsigned Opc, SelectionDAG &DAG, LoadSDNode *LD, 2156 SDValue Chain, SDValue Src, unsigned Offset) { 2157 SDValue Ptr = LD->getBasePtr(); 2158 EVT VT = LD->getValueType(0), MemVT = LD->getMemoryVT(); 2159 EVT BasePtrVT = Ptr.getValueType(); 2160 SDLoc DL(LD); 2161 SDVTList VTList = DAG.getVTList(VT, MVT::Other); 2162 2163 if (Offset) 2164 Ptr = DAG.getNode(ISD::ADD, DL, BasePtrVT, Ptr, 2165 DAG.getConstant(Offset, DL, BasePtrVT)); 2166 2167 SDValue Ops[] = { Chain, Ptr, Src }; 2168 return DAG.getMemIntrinsicNode(Opc, DL, VTList, Ops, MemVT, 2169 LD->getMemOperand()); 2170 } 2171 2172 // Expand an unaligned 32 or 64-bit integer load node. 2173 SDValue MipsTargetLowering::lowerLOAD(SDValue Op, SelectionDAG &DAG) const { 2174 LoadSDNode *LD = cast<LoadSDNode>(Op); 2175 EVT MemVT = LD->getMemoryVT(); 2176 2177 if (Subtarget.systemSupportsUnalignedAccess()) 2178 return Op; 2179 2180 // Return if load is aligned or if MemVT is neither i32 nor i64. 2181 if ((LD->getAlignment() >= MemVT.getSizeInBits() / 8) || 2182 ((MemVT != MVT::i32) && (MemVT != MVT::i64))) 2183 return SDValue(); 2184 2185 bool IsLittle = Subtarget.isLittle(); 2186 EVT VT = Op.getValueType(); 2187 ISD::LoadExtType ExtType = LD->getExtensionType(); 2188 SDValue Chain = LD->getChain(), Undef = DAG.getUNDEF(VT); 2189 2190 assert((VT == MVT::i32) || (VT == MVT::i64)); 2191 2192 // Expand 2193 // (set dst, (i64 (load baseptr))) 2194 // to 2195 // (set tmp, (ldl (add baseptr, 7), undef)) 2196 // (set dst, (ldr baseptr, tmp)) 2197 if ((VT == MVT::i64) && (ExtType == ISD::NON_EXTLOAD)) { 2198 SDValue LDL = createLoadLR(MipsISD::LDL, DAG, LD, Chain, Undef, 2199 IsLittle ? 7 : 0); 2200 return createLoadLR(MipsISD::LDR, DAG, LD, LDL.getValue(1), LDL, 2201 IsLittle ? 0 : 7); 2202 } 2203 2204 SDValue LWL = createLoadLR(MipsISD::LWL, DAG, LD, Chain, Undef, 2205 IsLittle ? 3 : 0); 2206 SDValue LWR = createLoadLR(MipsISD::LWR, DAG, LD, LWL.getValue(1), LWL, 2207 IsLittle ? 0 : 3); 2208 2209 // Expand 2210 // (set dst, (i32 (load baseptr))) or 2211 // (set dst, (i64 (sextload baseptr))) or 2212 // (set dst, (i64 (extload baseptr))) 2213 // to 2214 // (set tmp, (lwl (add baseptr, 3), undef)) 2215 // (set dst, (lwr baseptr, tmp)) 2216 if ((VT == MVT::i32) || (ExtType == ISD::SEXTLOAD) || 2217 (ExtType == ISD::EXTLOAD)) 2218 return LWR; 2219 2220 assert((VT == MVT::i64) && (ExtType == ISD::ZEXTLOAD)); 2221 2222 // Expand 2223 // (set dst, (i64 (zextload baseptr))) 2224 // to 2225 // (set tmp0, (lwl (add baseptr, 3), undef)) 2226 // (set tmp1, (lwr baseptr, tmp0)) 2227 // (set tmp2, (shl tmp1, 32)) 2228 // (set dst, (srl tmp2, 32)) 2229 SDLoc DL(LD); 2230 SDValue Const32 = DAG.getConstant(32, DL, MVT::i32); 2231 SDValue SLL = DAG.getNode(ISD::SHL, DL, MVT::i64, LWR, Const32); 2232 SDValue SRL = DAG.getNode(ISD::SRL, DL, MVT::i64, SLL, Const32); 2233 SDValue Ops[] = { SRL, LWR.getValue(1) }; 2234 return DAG.getMergeValues(Ops, DL); 2235 } 2236 2237 static SDValue createStoreLR(unsigned Opc, SelectionDAG &DAG, StoreSDNode *SD, 2238 SDValue Chain, unsigned Offset) { 2239 SDValue Ptr = SD->getBasePtr(), Value = SD->getValue(); 2240 EVT MemVT = SD->getMemoryVT(), BasePtrVT = Ptr.getValueType(); 2241 SDLoc DL(SD); 2242 SDVTList VTList = DAG.getVTList(MVT::Other); 2243 2244 if (Offset) 2245 Ptr = DAG.getNode(ISD::ADD, DL, BasePtrVT, Ptr, 2246 DAG.getConstant(Offset, DL, BasePtrVT)); 2247 2248 SDValue Ops[] = { Chain, Value, Ptr }; 2249 return DAG.getMemIntrinsicNode(Opc, DL, VTList, Ops, MemVT, 2250 SD->getMemOperand()); 2251 } 2252 2253 // Expand an unaligned 32 or 64-bit integer store node. 2254 static SDValue lowerUnalignedIntStore(StoreSDNode *SD, SelectionDAG &DAG, 2255 bool IsLittle) { 2256 SDValue Value = SD->getValue(), Chain = SD->getChain(); 2257 EVT VT = Value.getValueType(); 2258 2259 // Expand 2260 // (store val, baseptr) or 2261 // (truncstore val, baseptr) 2262 // to 2263 // (swl val, (add baseptr, 3)) 2264 // (swr val, baseptr) 2265 if ((VT == MVT::i32) || SD->isTruncatingStore()) { 2266 SDValue SWL = createStoreLR(MipsISD::SWL, DAG, SD, Chain, 2267 IsLittle ? 3 : 0); 2268 return createStoreLR(MipsISD::SWR, DAG, SD, SWL, IsLittle ? 0 : 3); 2269 } 2270 2271 assert(VT == MVT::i64); 2272 2273 // Expand 2274 // (store val, baseptr) 2275 // to 2276 // (sdl val, (add baseptr, 7)) 2277 // (sdr val, baseptr) 2278 SDValue SDL = createStoreLR(MipsISD::SDL, DAG, SD, Chain, IsLittle ? 7 : 0); 2279 return createStoreLR(MipsISD::SDR, DAG, SD, SDL, IsLittle ? 0 : 7); 2280 } 2281 2282 // Lower (store (fp_to_sint $fp) $ptr) to (store (TruncIntFP $fp), $ptr). 2283 static SDValue lowerFP_TO_SINT_STORE(StoreSDNode *SD, SelectionDAG &DAG) { 2284 SDValue Val = SD->getValue(); 2285 2286 if (Val.getOpcode() != ISD::FP_TO_SINT) 2287 return SDValue(); 2288 2289 EVT FPTy = EVT::getFloatingPointVT(Val.getValueSizeInBits()); 2290 SDValue Tr = DAG.getNode(MipsISD::TruncIntFP, SDLoc(Val), FPTy, 2291 Val.getOperand(0)); 2292 2293 return DAG.getStore(SD->getChain(), SDLoc(SD), Tr, SD->getBasePtr(), 2294 SD->getPointerInfo(), SD->isVolatile(), 2295 SD->isNonTemporal(), SD->getAlignment()); 2296 } 2297 2298 SDValue MipsTargetLowering::lowerSTORE(SDValue Op, SelectionDAG &DAG) const { 2299 StoreSDNode *SD = cast<StoreSDNode>(Op); 2300 EVT MemVT = SD->getMemoryVT(); 2301 2302 // Lower unaligned integer stores. 2303 if (!Subtarget.systemSupportsUnalignedAccess() && 2304 (SD->getAlignment() < MemVT.getSizeInBits() / 8) && 2305 ((MemVT == MVT::i32) || (MemVT == MVT::i64))) 2306 return lowerUnalignedIntStore(SD, DAG, Subtarget.isLittle()); 2307 2308 return lowerFP_TO_SINT_STORE(SD, DAG); 2309 } 2310 2311 SDValue MipsTargetLowering::lowerADD(SDValue Op, SelectionDAG &DAG) const { 2312 if (Op->getOperand(0).getOpcode() != ISD::FRAMEADDR 2313 || cast<ConstantSDNode> 2314 (Op->getOperand(0).getOperand(0))->getZExtValue() != 0 2315 || Op->getOperand(1).getOpcode() != ISD::FRAME_TO_ARGS_OFFSET) 2316 return SDValue(); 2317 2318 // The pattern 2319 // (add (frameaddr 0), (frame_to_args_offset)) 2320 // results from lowering llvm.eh.dwarf.cfa intrinsic. Transform it to 2321 // (add FrameObject, 0) 2322 // where FrameObject is a fixed StackObject with offset 0 which points to 2323 // the old stack pointer. 2324 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo(); 2325 EVT ValTy = Op->getValueType(0); 2326 int FI = MFI->CreateFixedObject(Op.getValueSizeInBits() / 8, 0, false); 2327 SDValue InArgsAddr = DAG.getFrameIndex(FI, ValTy); 2328 SDLoc DL(Op); 2329 return DAG.getNode(ISD::ADD, DL, ValTy, InArgsAddr, 2330 DAG.getConstant(0, DL, ValTy)); 2331 } 2332 2333 SDValue MipsTargetLowering::lowerFP_TO_SINT(SDValue Op, 2334 SelectionDAG &DAG) const { 2335 EVT FPTy = EVT::getFloatingPointVT(Op.getValueSizeInBits()); 2336 SDValue Trunc = DAG.getNode(MipsISD::TruncIntFP, SDLoc(Op), FPTy, 2337 Op.getOperand(0)); 2338 return DAG.getNode(ISD::BITCAST, SDLoc(Op), Op.getValueType(), Trunc); 2339 } 2340 2341 //===----------------------------------------------------------------------===// 2342 // Calling Convention Implementation 2343 //===----------------------------------------------------------------------===// 2344 2345 //===----------------------------------------------------------------------===// 2346 // TODO: Implement a generic logic using tblgen that can support this. 2347 // Mips O32 ABI rules: 2348 // --- 2349 // i32 - Passed in A0, A1, A2, A3 and stack 2350 // f32 - Only passed in f32 registers if no int reg has been used yet to hold 2351 // an argument. Otherwise, passed in A1, A2, A3 and stack. 2352 // f64 - Only passed in two aliased f32 registers if no int reg has been used 2353 // yet to hold an argument. Otherwise, use A2, A3 and stack. If A1 is 2354 // not used, it must be shadowed. If only A3 is available, shadow it and 2355 // go to stack. 2356 // 2357 // For vararg functions, all arguments are passed in A0, A1, A2, A3 and stack. 2358 //===----------------------------------------------------------------------===// 2359 2360 static bool CC_MipsO32(unsigned ValNo, MVT ValVT, MVT LocVT, 2361 CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, 2362 CCState &State, ArrayRef<MCPhysReg> F64Regs) { 2363 const MipsSubtarget &Subtarget = static_cast<const MipsSubtarget &>( 2364 State.getMachineFunction().getSubtarget()); 2365 2366 static const MCPhysReg IntRegs[] = { Mips::A0, Mips::A1, Mips::A2, Mips::A3 }; 2367 static const MCPhysReg F32Regs[] = { Mips::F12, Mips::F14 }; 2368 2369 // Do not process byval args here. 2370 if (ArgFlags.isByVal()) 2371 return true; 2372 2373 // Promote i8 and i16 2374 if (ArgFlags.isInReg() && !Subtarget.isLittle()) { 2375 if (LocVT == MVT::i8 || LocVT == MVT::i16 || LocVT == MVT::i32) { 2376 LocVT = MVT::i32; 2377 if (ArgFlags.isSExt()) 2378 LocInfo = CCValAssign::SExtUpper; 2379 else if (ArgFlags.isZExt()) 2380 LocInfo = CCValAssign::ZExtUpper; 2381 else 2382 LocInfo = CCValAssign::AExtUpper; 2383 } 2384 } 2385 2386 // Promote i8 and i16 2387 if (LocVT == MVT::i8 || LocVT == MVT::i16) { 2388 LocVT = MVT::i32; 2389 if (ArgFlags.isSExt()) 2390 LocInfo = CCValAssign::SExt; 2391 else if (ArgFlags.isZExt()) 2392 LocInfo = CCValAssign::ZExt; 2393 else 2394 LocInfo = CCValAssign::AExt; 2395 } 2396 2397 unsigned Reg; 2398 2399 // f32 and f64 are allocated in A0, A1, A2, A3 when either of the following 2400 // is true: function is vararg, argument is 3rd or higher, there is previous 2401 // argument which is not f32 or f64. 2402 bool AllocateFloatsInIntReg = State.isVarArg() || ValNo > 1 || 2403 State.getFirstUnallocated(F32Regs) != ValNo; 2404 unsigned OrigAlign = ArgFlags.getOrigAlign(); 2405 bool isI64 = (ValVT == MVT::i32 && OrigAlign == 8); 2406 2407 if (ValVT == MVT::i32 || (ValVT == MVT::f32 && AllocateFloatsInIntReg)) { 2408 Reg = State.AllocateReg(IntRegs); 2409 // If this is the first part of an i64 arg, 2410 // the allocated register must be either A0 or A2. 2411 if (isI64 && (Reg == Mips::A1 || Reg == Mips::A3)) 2412 Reg = State.AllocateReg(IntRegs); 2413 LocVT = MVT::i32; 2414 } else if (ValVT == MVT::f64 && AllocateFloatsInIntReg) { 2415 // Allocate int register and shadow next int register. If first 2416 // available register is Mips::A1 or Mips::A3, shadow it too. 2417 Reg = State.AllocateReg(IntRegs); 2418 if (Reg == Mips::A1 || Reg == Mips::A3) 2419 Reg = State.AllocateReg(IntRegs); 2420 State.AllocateReg(IntRegs); 2421 LocVT = MVT::i32; 2422 } else if (ValVT.isFloatingPoint() && !AllocateFloatsInIntReg) { 2423 // we are guaranteed to find an available float register 2424 if (ValVT == MVT::f32) { 2425 Reg = State.AllocateReg(F32Regs); 2426 // Shadow int register 2427 State.AllocateReg(IntRegs); 2428 } else { 2429 Reg = State.AllocateReg(F64Regs); 2430 // Shadow int registers 2431 unsigned Reg2 = State.AllocateReg(IntRegs); 2432 if (Reg2 == Mips::A1 || Reg2 == Mips::A3) 2433 State.AllocateReg(IntRegs); 2434 State.AllocateReg(IntRegs); 2435 } 2436 } else 2437 llvm_unreachable("Cannot handle this ValVT."); 2438 2439 if (!Reg) { 2440 unsigned Offset = State.AllocateStack(ValVT.getSizeInBits() >> 3, 2441 OrigAlign); 2442 State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo)); 2443 } else 2444 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); 2445 2446 return false; 2447 } 2448 2449 static bool CC_MipsO32_FP32(unsigned ValNo, MVT ValVT, 2450 MVT LocVT, CCValAssign::LocInfo LocInfo, 2451 ISD::ArgFlagsTy ArgFlags, CCState &State) { 2452 static const MCPhysReg F64Regs[] = { Mips::D6, Mips::D7 }; 2453 2454 return CC_MipsO32(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State, F64Regs); 2455 } 2456 2457 static bool CC_MipsO32_FP64(unsigned ValNo, MVT ValVT, 2458 MVT LocVT, CCValAssign::LocInfo LocInfo, 2459 ISD::ArgFlagsTy ArgFlags, CCState &State) { 2460 static const MCPhysReg F64Regs[] = { Mips::D12_64, Mips::D14_64 }; 2461 2462 return CC_MipsO32(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State, F64Regs); 2463 } 2464 2465 static bool CC_MipsO32(unsigned ValNo, MVT ValVT, MVT LocVT, 2466 CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, 2467 CCState &State) LLVM_ATTRIBUTE_UNUSED; 2468 2469 #include "MipsGenCallingConv.inc" 2470 2471 //===----------------------------------------------------------------------===// 2472 // Call Calling Convention Implementation 2473 //===----------------------------------------------------------------------===// 2474 2475 // Return next O32 integer argument register. 2476 static unsigned getNextIntArgReg(unsigned Reg) { 2477 assert((Reg == Mips::A0) || (Reg == Mips::A2)); 2478 return (Reg == Mips::A0) ? Mips::A1 : Mips::A3; 2479 } 2480 2481 SDValue 2482 MipsTargetLowering::passArgOnStack(SDValue StackPtr, unsigned Offset, 2483 SDValue Chain, SDValue Arg, SDLoc DL, 2484 bool IsTailCall, SelectionDAG &DAG) const { 2485 if (!IsTailCall) { 2486 SDValue PtrOff = 2487 DAG.getNode(ISD::ADD, DL, getPointerTy(DAG.getDataLayout()), StackPtr, 2488 DAG.getIntPtrConstant(Offset, DL)); 2489 return DAG.getStore(Chain, DL, Arg, PtrOff, MachinePointerInfo(), false, 2490 false, 0); 2491 } 2492 2493 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo(); 2494 int FI = MFI->CreateFixedObject(Arg.getValueSizeInBits() / 8, Offset, false); 2495 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy(DAG.getDataLayout())); 2496 return DAG.getStore(Chain, DL, Arg, FIN, MachinePointerInfo(), 2497 /*isVolatile=*/ true, false, 0); 2498 } 2499 2500 void MipsTargetLowering:: 2501 getOpndList(SmallVectorImpl<SDValue> &Ops, 2502 std::deque< std::pair<unsigned, SDValue> > &RegsToPass, 2503 bool IsPICCall, bool GlobalOrExternal, bool InternalLinkage, 2504 bool IsCallReloc, CallLoweringInfo &CLI, SDValue Callee, 2505 SDValue Chain) const { 2506 // Insert node "GP copy globalreg" before call to function. 2507 // 2508 // R_MIPS_CALL* operators (emitted when non-internal functions are called 2509 // in PIC mode) allow symbols to be resolved via lazy binding. 2510 // The lazy binding stub requires GP to point to the GOT. 2511 // Note that we don't need GP to point to the GOT for indirect calls 2512 // (when R_MIPS_CALL* is not used for the call) because Mips linker generates 2513 // lazy binding stub for a function only when R_MIPS_CALL* are the only relocs 2514 // used for the function (that is, Mips linker doesn't generate lazy binding 2515 // stub for a function whose address is taken in the program). 2516 if (IsPICCall && !InternalLinkage && IsCallReloc) { 2517 unsigned GPReg = ABI.IsN64() ? Mips::GP_64 : Mips::GP; 2518 EVT Ty = ABI.IsN64() ? MVT::i64 : MVT::i32; 2519 RegsToPass.push_back(std::make_pair(GPReg, getGlobalReg(CLI.DAG, Ty))); 2520 } 2521 2522 // Build a sequence of copy-to-reg nodes chained together with token 2523 // chain and flag operands which copy the outgoing args into registers. 2524 // The InFlag in necessary since all emitted instructions must be 2525 // stuck together. 2526 SDValue InFlag; 2527 2528 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) { 2529 Chain = CLI.DAG.getCopyToReg(Chain, CLI.DL, RegsToPass[i].first, 2530 RegsToPass[i].second, InFlag); 2531 InFlag = Chain.getValue(1); 2532 } 2533 2534 // Add argument registers to the end of the list so that they are 2535 // known live into the call. 2536 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) 2537 Ops.push_back(CLI.DAG.getRegister(RegsToPass[i].first, 2538 RegsToPass[i].second.getValueType())); 2539 2540 // Add a register mask operand representing the call-preserved registers. 2541 const TargetRegisterInfo *TRI = Subtarget.getRegisterInfo(); 2542 const uint32_t *Mask = 2543 TRI->getCallPreservedMask(CLI.DAG.getMachineFunction(), CLI.CallConv); 2544 assert(Mask && "Missing call preserved mask for calling convention"); 2545 if (Subtarget.inMips16HardFloat()) { 2546 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(CLI.Callee)) { 2547 llvm::StringRef Sym = G->getGlobal()->getName(); 2548 Function *F = G->getGlobal()->getParent()->getFunction(Sym); 2549 if (F && F->hasFnAttribute("__Mips16RetHelper")) { 2550 Mask = MipsRegisterInfo::getMips16RetHelperMask(); 2551 } 2552 } 2553 } 2554 Ops.push_back(CLI.DAG.getRegisterMask(Mask)); 2555 2556 if (InFlag.getNode()) 2557 Ops.push_back(InFlag); 2558 } 2559 2560 /// LowerCall - functions arguments are copied from virtual regs to 2561 /// (physical regs)/(stack frame), CALLSEQ_START and CALLSEQ_END are emitted. 2562 SDValue 2563 MipsTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI, 2564 SmallVectorImpl<SDValue> &InVals) const { 2565 SelectionDAG &DAG = CLI.DAG; 2566 SDLoc DL = CLI.DL; 2567 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs; 2568 SmallVectorImpl<SDValue> &OutVals = CLI.OutVals; 2569 SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins; 2570 SDValue Chain = CLI.Chain; 2571 SDValue Callee = CLI.Callee; 2572 bool &IsTailCall = CLI.IsTailCall; 2573 CallingConv::ID CallConv = CLI.CallConv; 2574 bool IsVarArg = CLI.IsVarArg; 2575 2576 MachineFunction &MF = DAG.getMachineFunction(); 2577 MachineFrameInfo *MFI = MF.getFrameInfo(); 2578 const TargetFrameLowering *TFL = Subtarget.getFrameLowering(); 2579 MipsFunctionInfo *FuncInfo = MF.getInfo<MipsFunctionInfo>(); 2580 bool IsPIC = getTargetMachine().getRelocationModel() == Reloc::PIC_; 2581 2582 // Analyze operands of the call, assigning locations to each operand. 2583 SmallVector<CCValAssign, 16> ArgLocs; 2584 MipsCCState CCInfo( 2585 CallConv, IsVarArg, DAG.getMachineFunction(), ArgLocs, *DAG.getContext(), 2586 MipsCCState::getSpecialCallingConvForCallee(Callee.getNode(), Subtarget)); 2587 2588 // Allocate the reserved argument area. It seems strange to do this from the 2589 // caller side but removing it breaks the frame size calculation. 2590 CCInfo.AllocateStack(ABI.GetCalleeAllocdArgSizeInBytes(CallConv), 1); 2591 2592 CCInfo.AnalyzeCallOperands(Outs, CC_Mips, CLI.getArgs(), Callee.getNode()); 2593 2594 // Get a count of how many bytes are to be pushed on the stack. 2595 unsigned NextStackOffset = CCInfo.getNextStackOffset(); 2596 2597 // Check if it's really possible to do a tail call. 2598 if (IsTailCall) 2599 IsTailCall = isEligibleForTailCallOptimization( 2600 CCInfo, NextStackOffset, *MF.getInfo<MipsFunctionInfo>()); 2601 2602 if (!IsTailCall && CLI.CS && CLI.CS->isMustTailCall()) 2603 report_fatal_error("failed to perform tail call elimination on a call " 2604 "site marked musttail"); 2605 2606 if (IsTailCall) 2607 ++NumTailCalls; 2608 2609 // Chain is the output chain of the last Load/Store or CopyToReg node. 2610 // ByValChain is the output chain of the last Memcpy node created for copying 2611 // byval arguments to the stack. 2612 unsigned StackAlignment = TFL->getStackAlignment(); 2613 NextStackOffset = RoundUpToAlignment(NextStackOffset, StackAlignment); 2614 SDValue NextStackOffsetVal = DAG.getIntPtrConstant(NextStackOffset, DL, true); 2615 2616 if (!IsTailCall) 2617 Chain = DAG.getCALLSEQ_START(Chain, NextStackOffsetVal, DL); 2618 2619 SDValue StackPtr = 2620 DAG.getCopyFromReg(Chain, DL, ABI.IsN64() ? Mips::SP_64 : Mips::SP, 2621 getPointerTy(DAG.getDataLayout())); 2622 2623 // With EABI is it possible to have 16 args on registers. 2624 std::deque< std::pair<unsigned, SDValue> > RegsToPass; 2625 SmallVector<SDValue, 8> MemOpChains; 2626 2627 CCInfo.rewindByValRegsInfo(); 2628 2629 // Walk the register/memloc assignments, inserting copies/loads. 2630 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { 2631 SDValue Arg = OutVals[i]; 2632 CCValAssign &VA = ArgLocs[i]; 2633 MVT ValVT = VA.getValVT(), LocVT = VA.getLocVT(); 2634 ISD::ArgFlagsTy Flags = Outs[i].Flags; 2635 bool UseUpperBits = false; 2636 2637 // ByVal Arg. 2638 if (Flags.isByVal()) { 2639 unsigned FirstByValReg, LastByValReg; 2640 unsigned ByValIdx = CCInfo.getInRegsParamsProcessed(); 2641 CCInfo.getInRegsParamInfo(ByValIdx, FirstByValReg, LastByValReg); 2642 2643 assert(Flags.getByValSize() && 2644 "ByVal args of size 0 should have been ignored by front-end."); 2645 assert(ByValIdx < CCInfo.getInRegsParamsCount()); 2646 assert(!IsTailCall && 2647 "Do not tail-call optimize if there is a byval argument."); 2648 passByValArg(Chain, DL, RegsToPass, MemOpChains, StackPtr, MFI, DAG, Arg, 2649 FirstByValReg, LastByValReg, Flags, Subtarget.isLittle(), 2650 VA); 2651 CCInfo.nextInRegsParam(); 2652 continue; 2653 } 2654 2655 // Promote the value if needed. 2656 switch (VA.getLocInfo()) { 2657 default: 2658 llvm_unreachable("Unknown loc info!"); 2659 case CCValAssign::Full: 2660 if (VA.isRegLoc()) { 2661 if ((ValVT == MVT::f32 && LocVT == MVT::i32) || 2662 (ValVT == MVT::f64 && LocVT == MVT::i64) || 2663 (ValVT == MVT::i64 && LocVT == MVT::f64)) 2664 Arg = DAG.getNode(ISD::BITCAST, DL, LocVT, Arg); 2665 else if (ValVT == MVT::f64 && LocVT == MVT::i32) { 2666 SDValue Lo = DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32, 2667 Arg, DAG.getConstant(0, DL, MVT::i32)); 2668 SDValue Hi = DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32, 2669 Arg, DAG.getConstant(1, DL, MVT::i32)); 2670 if (!Subtarget.isLittle()) 2671 std::swap(Lo, Hi); 2672 unsigned LocRegLo = VA.getLocReg(); 2673 unsigned LocRegHigh = getNextIntArgReg(LocRegLo); 2674 RegsToPass.push_back(std::make_pair(LocRegLo, Lo)); 2675 RegsToPass.push_back(std::make_pair(LocRegHigh, Hi)); 2676 continue; 2677 } 2678 } 2679 break; 2680 case CCValAssign::BCvt: 2681 Arg = DAG.getNode(ISD::BITCAST, DL, LocVT, Arg); 2682 break; 2683 case CCValAssign::SExtUpper: 2684 UseUpperBits = true; 2685 // Fallthrough 2686 case CCValAssign::SExt: 2687 Arg = DAG.getNode(ISD::SIGN_EXTEND, DL, LocVT, Arg); 2688 break; 2689 case CCValAssign::ZExtUpper: 2690 UseUpperBits = true; 2691 // Fallthrough 2692 case CCValAssign::ZExt: 2693 Arg = DAG.getNode(ISD::ZERO_EXTEND, DL, LocVT, Arg); 2694 break; 2695 case CCValAssign::AExtUpper: 2696 UseUpperBits = true; 2697 // Fallthrough 2698 case CCValAssign::AExt: 2699 Arg = DAG.getNode(ISD::ANY_EXTEND, DL, LocVT, Arg); 2700 break; 2701 } 2702 2703 if (UseUpperBits) { 2704 unsigned ValSizeInBits = Outs[i].ArgVT.getSizeInBits(); 2705 unsigned LocSizeInBits = VA.getLocVT().getSizeInBits(); 2706 Arg = DAG.getNode( 2707 ISD::SHL, DL, VA.getLocVT(), Arg, 2708 DAG.getConstant(LocSizeInBits - ValSizeInBits, DL, VA.getLocVT())); 2709 } 2710 2711 // Arguments that can be passed on register must be kept at 2712 // RegsToPass vector 2713 if (VA.isRegLoc()) { 2714 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg)); 2715 continue; 2716 } 2717 2718 // Register can't get to this point... 2719 assert(VA.isMemLoc()); 2720 2721 // emit ISD::STORE whichs stores the 2722 // parameter value to a stack Location 2723 MemOpChains.push_back(passArgOnStack(StackPtr, VA.getLocMemOffset(), 2724 Chain, Arg, DL, IsTailCall, DAG)); 2725 } 2726 2727 // Transform all store nodes into one single node because all store 2728 // nodes are independent of each other. 2729 if (!MemOpChains.empty()) 2730 Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, MemOpChains); 2731 2732 // If the callee is a GlobalAddress/ExternalSymbol node (quite common, every 2733 // direct call is) turn it into a TargetGlobalAddress/TargetExternalSymbol 2734 // node so that legalize doesn't hack it. 2735 bool IsPICCall = (ABI.IsN64() || IsPIC); // true if calls are translated to 2736 // jalr $25 2737 bool GlobalOrExternal = false, InternalLinkage = false, IsCallReloc = false; 2738 SDValue CalleeLo; 2739 EVT Ty = Callee.getValueType(); 2740 2741 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) { 2742 if (IsPICCall) { 2743 const GlobalValue *Val = G->getGlobal(); 2744 InternalLinkage = Val->hasInternalLinkage(); 2745 2746 if (InternalLinkage) 2747 Callee = getAddrLocal(G, DL, Ty, DAG, ABI.IsN32() || ABI.IsN64()); 2748 else if (LargeGOT) { 2749 Callee = getAddrGlobalLargeGOT(G, DL, Ty, DAG, MipsII::MO_CALL_HI16, 2750 MipsII::MO_CALL_LO16, Chain, 2751 FuncInfo->callPtrInfo(Val)); 2752 IsCallReloc = true; 2753 } else { 2754 Callee = getAddrGlobal(G, DL, Ty, DAG, MipsII::MO_GOT_CALL, Chain, 2755 FuncInfo->callPtrInfo(Val)); 2756 IsCallReloc = true; 2757 } 2758 } else 2759 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), DL, 2760 getPointerTy(DAG.getDataLayout()), 0, 2761 MipsII::MO_NO_FLAG); 2762 GlobalOrExternal = true; 2763 } 2764 else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) { 2765 const char *Sym = S->getSymbol(); 2766 2767 if (!ABI.IsN64() && !IsPIC) // !N64 && static 2768 Callee = DAG.getTargetExternalSymbol( 2769 Sym, getPointerTy(DAG.getDataLayout()), MipsII::MO_NO_FLAG); 2770 else if (LargeGOT) { 2771 Callee = getAddrGlobalLargeGOT(S, DL, Ty, DAG, MipsII::MO_CALL_HI16, 2772 MipsII::MO_CALL_LO16, Chain, 2773 FuncInfo->callPtrInfo(Sym)); 2774 IsCallReloc = true; 2775 } else { // N64 || PIC 2776 Callee = getAddrGlobal(S, DL, Ty, DAG, MipsII::MO_GOT_CALL, Chain, 2777 FuncInfo->callPtrInfo(Sym)); 2778 IsCallReloc = true; 2779 } 2780 2781 GlobalOrExternal = true; 2782 } 2783 2784 SmallVector<SDValue, 8> Ops(1, Chain); 2785 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue); 2786 2787 getOpndList(Ops, RegsToPass, IsPICCall, GlobalOrExternal, InternalLinkage, 2788 IsCallReloc, CLI, Callee, Chain); 2789 2790 if (IsTailCall) 2791 return DAG.getNode(MipsISD::TailCall, DL, MVT::Other, Ops); 2792 2793 Chain = DAG.getNode(MipsISD::JmpLink, DL, NodeTys, Ops); 2794 SDValue InFlag = Chain.getValue(1); 2795 2796 // Create the CALLSEQ_END node. 2797 Chain = DAG.getCALLSEQ_END(Chain, NextStackOffsetVal, 2798 DAG.getIntPtrConstant(0, DL, true), InFlag, DL); 2799 InFlag = Chain.getValue(1); 2800 2801 // Handle result values, copying them out of physregs into vregs that we 2802 // return. 2803 return LowerCallResult(Chain, InFlag, CallConv, IsVarArg, Ins, DL, DAG, 2804 InVals, CLI); 2805 } 2806 2807 /// LowerCallResult - Lower the result values of a call into the 2808 /// appropriate copies out of appropriate physical registers. 2809 SDValue MipsTargetLowering::LowerCallResult( 2810 SDValue Chain, SDValue InFlag, CallingConv::ID CallConv, bool IsVarArg, 2811 const SmallVectorImpl<ISD::InputArg> &Ins, SDLoc DL, SelectionDAG &DAG, 2812 SmallVectorImpl<SDValue> &InVals, 2813 TargetLowering::CallLoweringInfo &CLI) const { 2814 // Assign locations to each value returned by this call. 2815 SmallVector<CCValAssign, 16> RVLocs; 2816 MipsCCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), RVLocs, 2817 *DAG.getContext()); 2818 CCInfo.AnalyzeCallResult(Ins, RetCC_Mips, CLI); 2819 2820 // Copy all of the result registers out of their specified physreg. 2821 for (unsigned i = 0; i != RVLocs.size(); ++i) { 2822 CCValAssign &VA = RVLocs[i]; 2823 assert(VA.isRegLoc() && "Can only return in registers!"); 2824 2825 SDValue Val = DAG.getCopyFromReg(Chain, DL, RVLocs[i].getLocReg(), 2826 RVLocs[i].getLocVT(), InFlag); 2827 Chain = Val.getValue(1); 2828 InFlag = Val.getValue(2); 2829 2830 if (VA.isUpperBitsInLoc()) { 2831 unsigned ValSizeInBits = Ins[i].ArgVT.getSizeInBits(); 2832 unsigned LocSizeInBits = VA.getLocVT().getSizeInBits(); 2833 unsigned Shift = 2834 VA.getLocInfo() == CCValAssign::ZExtUpper ? ISD::SRL : ISD::SRA; 2835 Val = DAG.getNode( 2836 Shift, DL, VA.getLocVT(), Val, 2837 DAG.getConstant(LocSizeInBits - ValSizeInBits, DL, VA.getLocVT())); 2838 } 2839 2840 switch (VA.getLocInfo()) { 2841 default: 2842 llvm_unreachable("Unknown loc info!"); 2843 case CCValAssign::Full: 2844 break; 2845 case CCValAssign::BCvt: 2846 Val = DAG.getNode(ISD::BITCAST, DL, VA.getValVT(), Val); 2847 break; 2848 case CCValAssign::AExt: 2849 case CCValAssign::AExtUpper: 2850 Val = DAG.getNode(ISD::TRUNCATE, DL, VA.getValVT(), Val); 2851 break; 2852 case CCValAssign::ZExt: 2853 case CCValAssign::ZExtUpper: 2854 Val = DAG.getNode(ISD::AssertZext, DL, VA.getLocVT(), Val, 2855 DAG.getValueType(VA.getValVT())); 2856 Val = DAG.getNode(ISD::TRUNCATE, DL, VA.getValVT(), Val); 2857 break; 2858 case CCValAssign::SExt: 2859 case CCValAssign::SExtUpper: 2860 Val = DAG.getNode(ISD::AssertSext, DL, VA.getLocVT(), Val, 2861 DAG.getValueType(VA.getValVT())); 2862 Val = DAG.getNode(ISD::TRUNCATE, DL, VA.getValVT(), Val); 2863 break; 2864 } 2865 2866 InVals.push_back(Val); 2867 } 2868 2869 return Chain; 2870 } 2871 2872 static SDValue UnpackFromArgumentSlot(SDValue Val, const CCValAssign &VA, 2873 EVT ArgVT, SDLoc DL, SelectionDAG &DAG) { 2874 MVT LocVT = VA.getLocVT(); 2875 EVT ValVT = VA.getValVT(); 2876 2877 // Shift into the upper bits if necessary. 2878 switch (VA.getLocInfo()) { 2879 default: 2880 break; 2881 case CCValAssign::AExtUpper: 2882 case CCValAssign::SExtUpper: 2883 case CCValAssign::ZExtUpper: { 2884 unsigned ValSizeInBits = ArgVT.getSizeInBits(); 2885 unsigned LocSizeInBits = VA.getLocVT().getSizeInBits(); 2886 unsigned Opcode = 2887 VA.getLocInfo() == CCValAssign::ZExtUpper ? ISD::SRL : ISD::SRA; 2888 Val = DAG.getNode( 2889 Opcode, DL, VA.getLocVT(), Val, 2890 DAG.getConstant(LocSizeInBits - ValSizeInBits, DL, VA.getLocVT())); 2891 break; 2892 } 2893 } 2894 2895 // If this is an value smaller than the argument slot size (32-bit for O32, 2896 // 64-bit for N32/N64), it has been promoted in some way to the argument slot 2897 // size. Extract the value and insert any appropriate assertions regarding 2898 // sign/zero extension. 2899 switch (VA.getLocInfo()) { 2900 default: 2901 llvm_unreachable("Unknown loc info!"); 2902 case CCValAssign::Full: 2903 break; 2904 case CCValAssign::AExtUpper: 2905 case CCValAssign::AExt: 2906 Val = DAG.getNode(ISD::TRUNCATE, DL, ValVT, Val); 2907 break; 2908 case CCValAssign::SExtUpper: 2909 case CCValAssign::SExt: 2910 Val = DAG.getNode(ISD::AssertSext, DL, LocVT, Val, DAG.getValueType(ValVT)); 2911 Val = DAG.getNode(ISD::TRUNCATE, DL, ValVT, Val); 2912 break; 2913 case CCValAssign::ZExtUpper: 2914 case CCValAssign::ZExt: 2915 Val = DAG.getNode(ISD::AssertZext, DL, LocVT, Val, DAG.getValueType(ValVT)); 2916 Val = DAG.getNode(ISD::TRUNCATE, DL, ValVT, Val); 2917 break; 2918 case CCValAssign::BCvt: 2919 Val = DAG.getNode(ISD::BITCAST, DL, ValVT, Val); 2920 break; 2921 } 2922 2923 return Val; 2924 } 2925 2926 //===----------------------------------------------------------------------===// 2927 // Formal Arguments Calling Convention Implementation 2928 //===----------------------------------------------------------------------===// 2929 /// LowerFormalArguments - transform physical registers into virtual registers 2930 /// and generate load operations for arguments places on the stack. 2931 SDValue 2932 MipsTargetLowering::LowerFormalArguments(SDValue Chain, 2933 CallingConv::ID CallConv, 2934 bool IsVarArg, 2935 const SmallVectorImpl<ISD::InputArg> &Ins, 2936 SDLoc DL, SelectionDAG &DAG, 2937 SmallVectorImpl<SDValue> &InVals) 2938 const { 2939 MachineFunction &MF = DAG.getMachineFunction(); 2940 MachineFrameInfo *MFI = MF.getFrameInfo(); 2941 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>(); 2942 2943 MipsFI->setVarArgsFrameIndex(0); 2944 2945 // Used with vargs to acumulate store chains. 2946 std::vector<SDValue> OutChains; 2947 2948 // Assign locations to all of the incoming arguments. 2949 SmallVector<CCValAssign, 16> ArgLocs; 2950 MipsCCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), ArgLocs, 2951 *DAG.getContext()); 2952 CCInfo.AllocateStack(ABI.GetCalleeAllocdArgSizeInBytes(CallConv), 1); 2953 Function::const_arg_iterator FuncArg = 2954 DAG.getMachineFunction().getFunction()->arg_begin(); 2955 2956 CCInfo.AnalyzeFormalArguments(Ins, CC_Mips_FixedArg); 2957 MipsFI->setFormalArgInfo(CCInfo.getNextStackOffset(), 2958 CCInfo.getInRegsParamsCount() > 0); 2959 2960 unsigned CurArgIdx = 0; 2961 CCInfo.rewindByValRegsInfo(); 2962 2963 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { 2964 CCValAssign &VA = ArgLocs[i]; 2965 if (Ins[i].isOrigArg()) { 2966 std::advance(FuncArg, Ins[i].getOrigArgIndex() - CurArgIdx); 2967 CurArgIdx = Ins[i].getOrigArgIndex(); 2968 } 2969 EVT ValVT = VA.getValVT(); 2970 ISD::ArgFlagsTy Flags = Ins[i].Flags; 2971 bool IsRegLoc = VA.isRegLoc(); 2972 2973 if (Flags.isByVal()) { 2974 assert(Ins[i].isOrigArg() && "Byval arguments cannot be implicit"); 2975 unsigned FirstByValReg, LastByValReg; 2976 unsigned ByValIdx = CCInfo.getInRegsParamsProcessed(); 2977 CCInfo.getInRegsParamInfo(ByValIdx, FirstByValReg, LastByValReg); 2978 2979 assert(Flags.getByValSize() && 2980 "ByVal args of size 0 should have been ignored by front-end."); 2981 assert(ByValIdx < CCInfo.getInRegsParamsCount()); 2982 copyByValRegs(Chain, DL, OutChains, DAG, Flags, InVals, &*FuncArg, 2983 FirstByValReg, LastByValReg, VA, CCInfo); 2984 CCInfo.nextInRegsParam(); 2985 continue; 2986 } 2987 2988 // Arguments stored on registers 2989 if (IsRegLoc) { 2990 MVT RegVT = VA.getLocVT(); 2991 unsigned ArgReg = VA.getLocReg(); 2992 const TargetRegisterClass *RC = getRegClassFor(RegVT); 2993 2994 // Transform the arguments stored on 2995 // physical registers into virtual ones 2996 unsigned Reg = addLiveIn(DAG.getMachineFunction(), ArgReg, RC); 2997 SDValue ArgValue = DAG.getCopyFromReg(Chain, DL, Reg, RegVT); 2998 2999 ArgValue = UnpackFromArgumentSlot(ArgValue, VA, Ins[i].ArgVT, DL, DAG); 3000 3001 // Handle floating point arguments passed in integer registers and 3002 // long double arguments passed in floating point registers. 3003 if ((RegVT == MVT::i32 && ValVT == MVT::f32) || 3004 (RegVT == MVT::i64 && ValVT == MVT::f64) || 3005 (RegVT == MVT::f64 && ValVT == MVT::i64)) 3006 ArgValue = DAG.getNode(ISD::BITCAST, DL, ValVT, ArgValue); 3007 else if (ABI.IsO32() && RegVT == MVT::i32 && 3008 ValVT == MVT::f64) { 3009 unsigned Reg2 = addLiveIn(DAG.getMachineFunction(), 3010 getNextIntArgReg(ArgReg), RC); 3011 SDValue ArgValue2 = DAG.getCopyFromReg(Chain, DL, Reg2, RegVT); 3012 if (!Subtarget.isLittle()) 3013 std::swap(ArgValue, ArgValue2); 3014 ArgValue = DAG.getNode(MipsISD::BuildPairF64, DL, MVT::f64, 3015 ArgValue, ArgValue2); 3016 } 3017 3018 InVals.push_back(ArgValue); 3019 } else { // VA.isRegLoc() 3020 MVT LocVT = VA.getLocVT(); 3021 3022 if (ABI.IsO32()) { 3023 // We ought to be able to use LocVT directly but O32 sets it to i32 3024 // when allocating floating point values to integer registers. 3025 // This shouldn't influence how we load the value into registers unless 3026 // we are targetting softfloat. 3027 if (VA.getValVT().isFloatingPoint() && !Subtarget.useSoftFloat()) 3028 LocVT = VA.getValVT(); 3029 } 3030 3031 // sanity check 3032 assert(VA.isMemLoc()); 3033 3034 // The stack pointer offset is relative to the caller stack frame. 3035 int FI = MFI->CreateFixedObject(LocVT.getSizeInBits() / 8, 3036 VA.getLocMemOffset(), true); 3037 3038 // Create load nodes to retrieve arguments from the stack 3039 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy(DAG.getDataLayout())); 3040 SDValue ArgValue = DAG.getLoad(LocVT, DL, Chain, FIN, 3041 MachinePointerInfo::getFixedStack(FI), 3042 false, false, false, 0); 3043 OutChains.push_back(ArgValue.getValue(1)); 3044 3045 ArgValue = UnpackFromArgumentSlot(ArgValue, VA, Ins[i].ArgVT, DL, DAG); 3046 3047 InVals.push_back(ArgValue); 3048 } 3049 } 3050 3051 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { 3052 // The mips ABIs for returning structs by value requires that we copy 3053 // the sret argument into $v0 for the return. Save the argument into 3054 // a virtual register so that we can access it from the return points. 3055 if (Ins[i].Flags.isSRet()) { 3056 unsigned Reg = MipsFI->getSRetReturnReg(); 3057 if (!Reg) { 3058 Reg = MF.getRegInfo().createVirtualRegister( 3059 getRegClassFor(ABI.IsN64() ? MVT::i64 : MVT::i32)); 3060 MipsFI->setSRetReturnReg(Reg); 3061 } 3062 SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), DL, Reg, InVals[i]); 3063 Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, Copy, Chain); 3064 break; 3065 } 3066 } 3067 3068 if (IsVarArg) 3069 writeVarArgRegs(OutChains, Chain, DL, DAG, CCInfo); 3070 3071 // All stores are grouped in one node to allow the matching between 3072 // the size of Ins and InVals. This only happens when on varg functions 3073 if (!OutChains.empty()) { 3074 OutChains.push_back(Chain); 3075 Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, OutChains); 3076 } 3077 3078 return Chain; 3079 } 3080 3081 //===----------------------------------------------------------------------===// 3082 // Return Value Calling Convention Implementation 3083 //===----------------------------------------------------------------------===// 3084 3085 bool 3086 MipsTargetLowering::CanLowerReturn(CallingConv::ID CallConv, 3087 MachineFunction &MF, bool IsVarArg, 3088 const SmallVectorImpl<ISD::OutputArg> &Outs, 3089 LLVMContext &Context) const { 3090 SmallVector<CCValAssign, 16> RVLocs; 3091 MipsCCState CCInfo(CallConv, IsVarArg, MF, RVLocs, Context); 3092 return CCInfo.CheckReturn(Outs, RetCC_Mips); 3093 } 3094 3095 bool 3096 MipsTargetLowering::shouldSignExtendTypeInLibCall(EVT Type, bool IsSigned) const { 3097 if (Subtarget.hasMips3() && Subtarget.useSoftFloat()) { 3098 if (Type == MVT::i32) 3099 return true; 3100 } 3101 return IsSigned; 3102 } 3103 3104 SDValue 3105 MipsTargetLowering::LowerReturn(SDValue Chain, 3106 CallingConv::ID CallConv, bool IsVarArg, 3107 const SmallVectorImpl<ISD::OutputArg> &Outs, 3108 const SmallVectorImpl<SDValue> &OutVals, 3109 SDLoc DL, SelectionDAG &DAG) const { 3110 // CCValAssign - represent the assignment of 3111 // the return value to a location 3112 SmallVector<CCValAssign, 16> RVLocs; 3113 MachineFunction &MF = DAG.getMachineFunction(); 3114 3115 // CCState - Info about the registers and stack slot. 3116 MipsCCState CCInfo(CallConv, IsVarArg, MF, RVLocs, *DAG.getContext()); 3117 3118 // Analyze return values. 3119 CCInfo.AnalyzeReturn(Outs, RetCC_Mips); 3120 3121 SDValue Flag; 3122 SmallVector<SDValue, 4> RetOps(1, Chain); 3123 3124 // Copy the result values into the output registers. 3125 for (unsigned i = 0; i != RVLocs.size(); ++i) { 3126 SDValue Val = OutVals[i]; 3127 CCValAssign &VA = RVLocs[i]; 3128 assert(VA.isRegLoc() && "Can only return in registers!"); 3129 bool UseUpperBits = false; 3130 3131 switch (VA.getLocInfo()) { 3132 default: 3133 llvm_unreachable("Unknown loc info!"); 3134 case CCValAssign::Full: 3135 break; 3136 case CCValAssign::BCvt: 3137 Val = DAG.getNode(ISD::BITCAST, DL, VA.getLocVT(), Val); 3138 break; 3139 case CCValAssign::AExtUpper: 3140 UseUpperBits = true; 3141 // Fallthrough 3142 case CCValAssign::AExt: 3143 Val = DAG.getNode(ISD::ANY_EXTEND, DL, VA.getLocVT(), Val); 3144 break; 3145 case CCValAssign::ZExtUpper: 3146 UseUpperBits = true; 3147 // Fallthrough 3148 case CCValAssign::ZExt: 3149 Val = DAG.getNode(ISD::ZERO_EXTEND, DL, VA.getLocVT(), Val); 3150 break; 3151 case CCValAssign::SExtUpper: 3152 UseUpperBits = true; 3153 // Fallthrough 3154 case CCValAssign::SExt: 3155 Val = DAG.getNode(ISD::SIGN_EXTEND, DL, VA.getLocVT(), Val); 3156 break; 3157 } 3158 3159 if (UseUpperBits) { 3160 unsigned ValSizeInBits = Outs[i].ArgVT.getSizeInBits(); 3161 unsigned LocSizeInBits = VA.getLocVT().getSizeInBits(); 3162 Val = DAG.getNode( 3163 ISD::SHL, DL, VA.getLocVT(), Val, 3164 DAG.getConstant(LocSizeInBits - ValSizeInBits, DL, VA.getLocVT())); 3165 } 3166 3167 Chain = DAG.getCopyToReg(Chain, DL, VA.getLocReg(), Val, Flag); 3168 3169 // Guarantee that all emitted copies are stuck together with flags. 3170 Flag = Chain.getValue(1); 3171 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT())); 3172 } 3173 3174 // The mips ABIs for returning structs by value requires that we copy 3175 // the sret argument into $v0 for the return. We saved the argument into 3176 // a virtual register in the entry block, so now we copy the value out 3177 // and into $v0. 3178 if (MF.getFunction()->hasStructRetAttr()) { 3179 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>(); 3180 unsigned Reg = MipsFI->getSRetReturnReg(); 3181 3182 if (!Reg) 3183 llvm_unreachable("sret virtual register not created in the entry block"); 3184 SDValue Val = 3185 DAG.getCopyFromReg(Chain, DL, Reg, getPointerTy(DAG.getDataLayout())); 3186 unsigned V0 = ABI.IsN64() ? Mips::V0_64 : Mips::V0; 3187 3188 Chain = DAG.getCopyToReg(Chain, DL, V0, Val, Flag); 3189 Flag = Chain.getValue(1); 3190 RetOps.push_back(DAG.getRegister(V0, getPointerTy(DAG.getDataLayout()))); 3191 } 3192 3193 RetOps[0] = Chain; // Update chain. 3194 3195 // Add the flag if we have it. 3196 if (Flag.getNode()) 3197 RetOps.push_back(Flag); 3198 3199 // Return on Mips is always a "jr $ra" 3200 return DAG.getNode(MipsISD::Ret, DL, MVT::Other, RetOps); 3201 } 3202 3203 //===----------------------------------------------------------------------===// 3204 // Mips Inline Assembly Support 3205 //===----------------------------------------------------------------------===// 3206 3207 /// getConstraintType - Given a constraint letter, return the type of 3208 /// constraint it is for this target. 3209 MipsTargetLowering::ConstraintType 3210 MipsTargetLowering::getConstraintType(StringRef Constraint) const { 3211 // Mips specific constraints 3212 // GCC config/mips/constraints.md 3213 // 3214 // 'd' : An address register. Equivalent to r 3215 // unless generating MIPS16 code. 3216 // 'y' : Equivalent to r; retained for 3217 // backwards compatibility. 3218 // 'c' : A register suitable for use in an indirect 3219 // jump. This will always be $25 for -mabicalls. 3220 // 'l' : The lo register. 1 word storage. 3221 // 'x' : The hilo register pair. Double word storage. 3222 if (Constraint.size() == 1) { 3223 switch (Constraint[0]) { 3224 default : break; 3225 case 'd': 3226 case 'y': 3227 case 'f': 3228 case 'c': 3229 case 'l': 3230 case 'x': 3231 return C_RegisterClass; 3232 case 'R': 3233 return C_Memory; 3234 } 3235 } 3236 3237 if (Constraint == "ZC") 3238 return C_Memory; 3239 3240 return TargetLowering::getConstraintType(Constraint); 3241 } 3242 3243 /// Examine constraint type and operand type and determine a weight value. 3244 /// This object must already have been set up with the operand type 3245 /// and the current alternative constraint selected. 3246 TargetLowering::ConstraintWeight 3247 MipsTargetLowering::getSingleConstraintMatchWeight( 3248 AsmOperandInfo &info, const char *constraint) const { 3249 ConstraintWeight weight = CW_Invalid; 3250 Value *CallOperandVal = info.CallOperandVal; 3251 // If we don't have a value, we can't do a match, 3252 // but allow it at the lowest weight. 3253 if (!CallOperandVal) 3254 return CW_Default; 3255 Type *type = CallOperandVal->getType(); 3256 // Look at the constraint type. 3257 switch (*constraint) { 3258 default: 3259 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint); 3260 break; 3261 case 'd': 3262 case 'y': 3263 if (type->isIntegerTy()) 3264 weight = CW_Register; 3265 break; 3266 case 'f': // FPU or MSA register 3267 if (Subtarget.hasMSA() && type->isVectorTy() && 3268 cast<VectorType>(type)->getBitWidth() == 128) 3269 weight = CW_Register; 3270 else if (type->isFloatTy()) 3271 weight = CW_Register; 3272 break; 3273 case 'c': // $25 for indirect jumps 3274 case 'l': // lo register 3275 case 'x': // hilo register pair 3276 if (type->isIntegerTy()) 3277 weight = CW_SpecificReg; 3278 break; 3279 case 'I': // signed 16 bit immediate 3280 case 'J': // integer zero 3281 case 'K': // unsigned 16 bit immediate 3282 case 'L': // signed 32 bit immediate where lower 16 bits are 0 3283 case 'N': // immediate in the range of -65535 to -1 (inclusive) 3284 case 'O': // signed 15 bit immediate (+- 16383) 3285 case 'P': // immediate in the range of 65535 to 1 (inclusive) 3286 if (isa<ConstantInt>(CallOperandVal)) 3287 weight = CW_Constant; 3288 break; 3289 case 'R': 3290 weight = CW_Memory; 3291 break; 3292 } 3293 return weight; 3294 } 3295 3296 /// This is a helper function to parse a physical register string and split it 3297 /// into non-numeric and numeric parts (Prefix and Reg). The first boolean flag 3298 /// that is returned indicates whether parsing was successful. The second flag 3299 /// is true if the numeric part exists. 3300 static std::pair<bool, bool> parsePhysicalReg(StringRef C, StringRef &Prefix, 3301 unsigned long long &Reg) { 3302 if (C.front() != '{' || C.back() != '}') 3303 return std::make_pair(false, false); 3304 3305 // Search for the first numeric character. 3306 StringRef::const_iterator I, B = C.begin() + 1, E = C.end() - 1; 3307 I = std::find_if(B, E, std::ptr_fun(isdigit)); 3308 3309 Prefix = StringRef(B, I - B); 3310 3311 // The second flag is set to false if no numeric characters were found. 3312 if (I == E) 3313 return std::make_pair(true, false); 3314 3315 // Parse the numeric characters. 3316 return std::make_pair(!getAsUnsignedInteger(StringRef(I, E - I), 10, Reg), 3317 true); 3318 } 3319 3320 std::pair<unsigned, const TargetRegisterClass *> MipsTargetLowering:: 3321 parseRegForInlineAsmConstraint(StringRef C, MVT VT) const { 3322 const TargetRegisterInfo *TRI = 3323 Subtarget.getRegisterInfo(); 3324 const TargetRegisterClass *RC; 3325 StringRef Prefix; 3326 unsigned long long Reg; 3327 3328 std::pair<bool, bool> R = parsePhysicalReg(C, Prefix, Reg); 3329 3330 if (!R.first) 3331 return std::make_pair(0U, nullptr); 3332 3333 if ((Prefix == "hi" || Prefix == "lo")) { // Parse hi/lo. 3334 // No numeric characters follow "hi" or "lo". 3335 if (R.second) 3336 return std::make_pair(0U, nullptr); 3337 3338 RC = TRI->getRegClass(Prefix == "hi" ? 3339 Mips::HI32RegClassID : Mips::LO32RegClassID); 3340 return std::make_pair(*(RC->begin()), RC); 3341 } else if (Prefix.startswith("$msa")) { 3342 // Parse $msa(ir|csr|access|save|modify|request|map|unmap) 3343 3344 // No numeric characters follow the name. 3345 if (R.second) 3346 return std::make_pair(0U, nullptr); 3347 3348 Reg = StringSwitch<unsigned long long>(Prefix) 3349 .Case("$msair", Mips::MSAIR) 3350 .Case("$msacsr", Mips::MSACSR) 3351 .Case("$msaaccess", Mips::MSAAccess) 3352 .Case("$msasave", Mips::MSASave) 3353 .Case("$msamodify", Mips::MSAModify) 3354 .Case("$msarequest", Mips::MSARequest) 3355 .Case("$msamap", Mips::MSAMap) 3356 .Case("$msaunmap", Mips::MSAUnmap) 3357 .Default(0); 3358 3359 if (!Reg) 3360 return std::make_pair(0U, nullptr); 3361 3362 RC = TRI->getRegClass(Mips::MSACtrlRegClassID); 3363 return std::make_pair(Reg, RC); 3364 } 3365 3366 if (!R.second) 3367 return std::make_pair(0U, nullptr); 3368 3369 if (Prefix == "$f") { // Parse $f0-$f31. 3370 // If the size of FP registers is 64-bit or Reg is an even number, select 3371 // the 64-bit register class. Otherwise, select the 32-bit register class. 3372 if (VT == MVT::Other) 3373 VT = (Subtarget.isFP64bit() || !(Reg % 2)) ? MVT::f64 : MVT::f32; 3374 3375 RC = getRegClassFor(VT); 3376 3377 if (RC == &Mips::AFGR64RegClass) { 3378 assert(Reg % 2 == 0); 3379 Reg >>= 1; 3380 } 3381 } else if (Prefix == "$fcc") // Parse $fcc0-$fcc7. 3382 RC = TRI->getRegClass(Mips::FCCRegClassID); 3383 else if (Prefix == "$w") { // Parse $w0-$w31. 3384 RC = getRegClassFor((VT == MVT::Other) ? MVT::v16i8 : VT); 3385 } else { // Parse $0-$31. 3386 assert(Prefix == "$"); 3387 RC = getRegClassFor((VT == MVT::Other) ? MVT::i32 : VT); 3388 } 3389 3390 assert(Reg < RC->getNumRegs()); 3391 return std::make_pair(*(RC->begin() + Reg), RC); 3392 } 3393 3394 /// Given a register class constraint, like 'r', if this corresponds directly 3395 /// to an LLVM register class, return a register of 0 and the register class 3396 /// pointer. 3397 std::pair<unsigned, const TargetRegisterClass *> 3398 MipsTargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, 3399 StringRef Constraint, 3400 MVT VT) const { 3401 if (Constraint.size() == 1) { 3402 switch (Constraint[0]) { 3403 case 'd': // Address register. Same as 'r' unless generating MIPS16 code. 3404 case 'y': // Same as 'r'. Exists for compatibility. 3405 case 'r': 3406 if (VT == MVT::i32 || VT == MVT::i16 || VT == MVT::i8) { 3407 if (Subtarget.inMips16Mode()) 3408 return std::make_pair(0U, &Mips::CPU16RegsRegClass); 3409 return std::make_pair(0U, &Mips::GPR32RegClass); 3410 } 3411 if (VT == MVT::i64 && !Subtarget.isGP64bit()) 3412 return std::make_pair(0U, &Mips::GPR32RegClass); 3413 if (VT == MVT::i64 && Subtarget.isGP64bit()) 3414 return std::make_pair(0U, &Mips::GPR64RegClass); 3415 // This will generate an error message 3416 return std::make_pair(0U, nullptr); 3417 case 'f': // FPU or MSA register 3418 if (VT == MVT::v16i8) 3419 return std::make_pair(0U, &Mips::MSA128BRegClass); 3420 else if (VT == MVT::v8i16 || VT == MVT::v8f16) 3421 return std::make_pair(0U, &Mips::MSA128HRegClass); 3422 else if (VT == MVT::v4i32 || VT == MVT::v4f32) 3423 return std::make_pair(0U, &Mips::MSA128WRegClass); 3424 else if (VT == MVT::v2i64 || VT == MVT::v2f64) 3425 return std::make_pair(0U, &Mips::MSA128DRegClass); 3426 else if (VT == MVT::f32) 3427 return std::make_pair(0U, &Mips::FGR32RegClass); 3428 else if ((VT == MVT::f64) && (!Subtarget.isSingleFloat())) { 3429 if (Subtarget.isFP64bit()) 3430 return std::make_pair(0U, &Mips::FGR64RegClass); 3431 return std::make_pair(0U, &Mips::AFGR64RegClass); 3432 } 3433 break; 3434 case 'c': // register suitable for indirect jump 3435 if (VT == MVT::i32) 3436 return std::make_pair((unsigned)Mips::T9, &Mips::GPR32RegClass); 3437 assert(VT == MVT::i64 && "Unexpected type."); 3438 return std::make_pair((unsigned)Mips::T9_64, &Mips::GPR64RegClass); 3439 case 'l': // register suitable for indirect jump 3440 if (VT == MVT::i32) 3441 return std::make_pair((unsigned)Mips::LO0, &Mips::LO32RegClass); 3442 return std::make_pair((unsigned)Mips::LO0_64, &Mips::LO64RegClass); 3443 case 'x': // register suitable for indirect jump 3444 // Fixme: Not triggering the use of both hi and low 3445 // This will generate an error message 3446 return std::make_pair(0U, nullptr); 3447 } 3448 } 3449 3450 std::pair<unsigned, const TargetRegisterClass *> R; 3451 R = parseRegForInlineAsmConstraint(Constraint, VT); 3452 3453 if (R.second) 3454 return R; 3455 3456 return TargetLowering::getRegForInlineAsmConstraint(TRI, Constraint, VT); 3457 } 3458 3459 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops 3460 /// vector. If it is invalid, don't add anything to Ops. 3461 void MipsTargetLowering::LowerAsmOperandForConstraint(SDValue Op, 3462 std::string &Constraint, 3463 std::vector<SDValue>&Ops, 3464 SelectionDAG &DAG) const { 3465 SDLoc DL(Op); 3466 SDValue Result; 3467 3468 // Only support length 1 constraints for now. 3469 if (Constraint.length() > 1) return; 3470 3471 char ConstraintLetter = Constraint[0]; 3472 switch (ConstraintLetter) { 3473 default: break; // This will fall through to the generic implementation 3474 case 'I': // Signed 16 bit constant 3475 // If this fails, the parent routine will give an error 3476 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 3477 EVT Type = Op.getValueType(); 3478 int64_t Val = C->getSExtValue(); 3479 if (isInt<16>(Val)) { 3480 Result = DAG.getTargetConstant(Val, DL, Type); 3481 break; 3482 } 3483 } 3484 return; 3485 case 'J': // integer zero 3486 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 3487 EVT Type = Op.getValueType(); 3488 int64_t Val = C->getZExtValue(); 3489 if (Val == 0) { 3490 Result = DAG.getTargetConstant(0, DL, Type); 3491 break; 3492 } 3493 } 3494 return; 3495 case 'K': // unsigned 16 bit immediate 3496 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 3497 EVT Type = Op.getValueType(); 3498 uint64_t Val = (uint64_t)C->getZExtValue(); 3499 if (isUInt<16>(Val)) { 3500 Result = DAG.getTargetConstant(Val, DL, Type); 3501 break; 3502 } 3503 } 3504 return; 3505 case 'L': // signed 32 bit immediate where lower 16 bits are 0 3506 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 3507 EVT Type = Op.getValueType(); 3508 int64_t Val = C->getSExtValue(); 3509 if ((isInt<32>(Val)) && ((Val & 0xffff) == 0)){ 3510 Result = DAG.getTargetConstant(Val, DL, Type); 3511 break; 3512 } 3513 } 3514 return; 3515 case 'N': // immediate in the range of -65535 to -1 (inclusive) 3516 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 3517 EVT Type = Op.getValueType(); 3518 int64_t Val = C->getSExtValue(); 3519 if ((Val >= -65535) && (Val <= -1)) { 3520 Result = DAG.getTargetConstant(Val, DL, Type); 3521 break; 3522 } 3523 } 3524 return; 3525 case 'O': // signed 15 bit immediate 3526 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 3527 EVT Type = Op.getValueType(); 3528 int64_t Val = C->getSExtValue(); 3529 if ((isInt<15>(Val))) { 3530 Result = DAG.getTargetConstant(Val, DL, Type); 3531 break; 3532 } 3533 } 3534 return; 3535 case 'P': // immediate in the range of 1 to 65535 (inclusive) 3536 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 3537 EVT Type = Op.getValueType(); 3538 int64_t Val = C->getSExtValue(); 3539 if ((Val <= 65535) && (Val >= 1)) { 3540 Result = DAG.getTargetConstant(Val, DL, Type); 3541 break; 3542 } 3543 } 3544 return; 3545 } 3546 3547 if (Result.getNode()) { 3548 Ops.push_back(Result); 3549 return; 3550 } 3551 3552 TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG); 3553 } 3554 3555 bool MipsTargetLowering::isLegalAddressingMode(const DataLayout &DL, 3556 const AddrMode &AM, Type *Ty, 3557 unsigned AS) const { 3558 // No global is ever allowed as a base. 3559 if (AM.BaseGV) 3560 return false; 3561 3562 switch (AM.Scale) { 3563 case 0: // "r+i" or just "i", depending on HasBaseReg. 3564 break; 3565 case 1: 3566 if (!AM.HasBaseReg) // allow "r+i". 3567 break; 3568 return false; // disallow "r+r" or "r+r+i". 3569 default: 3570 return false; 3571 } 3572 3573 return true; 3574 } 3575 3576 bool 3577 MipsTargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const { 3578 // The Mips target isn't yet aware of offsets. 3579 return false; 3580 } 3581 3582 EVT MipsTargetLowering::getOptimalMemOpType(uint64_t Size, unsigned DstAlign, 3583 unsigned SrcAlign, 3584 bool IsMemset, bool ZeroMemset, 3585 bool MemcpyStrSrc, 3586 MachineFunction &MF) const { 3587 if (Subtarget.hasMips64()) 3588 return MVT::i64; 3589 3590 return MVT::i32; 3591 } 3592 3593 bool MipsTargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const { 3594 if (VT != MVT::f32 && VT != MVT::f64) 3595 return false; 3596 if (Imm.isNegZero()) 3597 return false; 3598 return Imm.isZero(); 3599 } 3600 3601 unsigned MipsTargetLowering::getJumpTableEncoding() const { 3602 if (ABI.IsN64()) 3603 return MachineJumpTableInfo::EK_GPRel64BlockAddress; 3604 3605 return TargetLowering::getJumpTableEncoding(); 3606 } 3607 3608 bool MipsTargetLowering::useSoftFloat() const { 3609 return Subtarget.useSoftFloat(); 3610 } 3611 3612 void MipsTargetLowering::copyByValRegs( 3613 SDValue Chain, SDLoc DL, std::vector<SDValue> &OutChains, SelectionDAG &DAG, 3614 const ISD::ArgFlagsTy &Flags, SmallVectorImpl<SDValue> &InVals, 3615 const Argument *FuncArg, unsigned FirstReg, unsigned LastReg, 3616 const CCValAssign &VA, MipsCCState &State) const { 3617 MachineFunction &MF = DAG.getMachineFunction(); 3618 MachineFrameInfo *MFI = MF.getFrameInfo(); 3619 unsigned GPRSizeInBytes = Subtarget.getGPRSizeInBytes(); 3620 unsigned NumRegs = LastReg - FirstReg; 3621 unsigned RegAreaSize = NumRegs * GPRSizeInBytes; 3622 unsigned FrameObjSize = std::max(Flags.getByValSize(), RegAreaSize); 3623 int FrameObjOffset; 3624 ArrayRef<MCPhysReg> ByValArgRegs = ABI.GetByValArgRegs(); 3625 3626 if (RegAreaSize) 3627 FrameObjOffset = 3628 (int)ABI.GetCalleeAllocdArgSizeInBytes(State.getCallingConv()) - 3629 (int)((ByValArgRegs.size() - FirstReg) * GPRSizeInBytes); 3630 else 3631 FrameObjOffset = VA.getLocMemOffset(); 3632 3633 // Create frame object. 3634 EVT PtrTy = getPointerTy(DAG.getDataLayout()); 3635 int FI = MFI->CreateFixedObject(FrameObjSize, FrameObjOffset, true); 3636 SDValue FIN = DAG.getFrameIndex(FI, PtrTy); 3637 InVals.push_back(FIN); 3638 3639 if (!NumRegs) 3640 return; 3641 3642 // Copy arg registers. 3643 MVT RegTy = MVT::getIntegerVT(GPRSizeInBytes * 8); 3644 const TargetRegisterClass *RC = getRegClassFor(RegTy); 3645 3646 for (unsigned I = 0; I < NumRegs; ++I) { 3647 unsigned ArgReg = ByValArgRegs[FirstReg + I]; 3648 unsigned VReg = addLiveIn(MF, ArgReg, RC); 3649 unsigned Offset = I * GPRSizeInBytes; 3650 SDValue StorePtr = DAG.getNode(ISD::ADD, DL, PtrTy, FIN, 3651 DAG.getConstant(Offset, DL, PtrTy)); 3652 SDValue Store = DAG.getStore(Chain, DL, DAG.getRegister(VReg, RegTy), 3653 StorePtr, MachinePointerInfo(FuncArg, Offset), 3654 false, false, 0); 3655 OutChains.push_back(Store); 3656 } 3657 } 3658 3659 // Copy byVal arg to registers and stack. 3660 void MipsTargetLowering::passByValArg( 3661 SDValue Chain, SDLoc DL, 3662 std::deque<std::pair<unsigned, SDValue>> &RegsToPass, 3663 SmallVectorImpl<SDValue> &MemOpChains, SDValue StackPtr, 3664 MachineFrameInfo *MFI, SelectionDAG &DAG, SDValue Arg, unsigned FirstReg, 3665 unsigned LastReg, const ISD::ArgFlagsTy &Flags, bool isLittle, 3666 const CCValAssign &VA) const { 3667 unsigned ByValSizeInBytes = Flags.getByValSize(); 3668 unsigned OffsetInBytes = 0; // From beginning of struct 3669 unsigned RegSizeInBytes = Subtarget.getGPRSizeInBytes(); 3670 unsigned Alignment = std::min(Flags.getByValAlign(), RegSizeInBytes); 3671 EVT PtrTy = getPointerTy(DAG.getDataLayout()), 3672 RegTy = MVT::getIntegerVT(RegSizeInBytes * 8); 3673 unsigned NumRegs = LastReg - FirstReg; 3674 3675 if (NumRegs) { 3676 const ArrayRef<MCPhysReg> ArgRegs = ABI.GetByValArgRegs(); 3677 bool LeftoverBytes = (NumRegs * RegSizeInBytes > ByValSizeInBytes); 3678 unsigned I = 0; 3679 3680 // Copy words to registers. 3681 for (; I < NumRegs - LeftoverBytes; ++I, OffsetInBytes += RegSizeInBytes) { 3682 SDValue LoadPtr = DAG.getNode(ISD::ADD, DL, PtrTy, Arg, 3683 DAG.getConstant(OffsetInBytes, DL, PtrTy)); 3684 SDValue LoadVal = DAG.getLoad(RegTy, DL, Chain, LoadPtr, 3685 MachinePointerInfo(), false, false, false, 3686 Alignment); 3687 MemOpChains.push_back(LoadVal.getValue(1)); 3688 unsigned ArgReg = ArgRegs[FirstReg + I]; 3689 RegsToPass.push_back(std::make_pair(ArgReg, LoadVal)); 3690 } 3691 3692 // Return if the struct has been fully copied. 3693 if (ByValSizeInBytes == OffsetInBytes) 3694 return; 3695 3696 // Copy the remainder of the byval argument with sub-word loads and shifts. 3697 if (LeftoverBytes) { 3698 SDValue Val; 3699 3700 for (unsigned LoadSizeInBytes = RegSizeInBytes / 2, TotalBytesLoaded = 0; 3701 OffsetInBytes < ByValSizeInBytes; LoadSizeInBytes /= 2) { 3702 unsigned RemainingSizeInBytes = ByValSizeInBytes - OffsetInBytes; 3703 3704 if (RemainingSizeInBytes < LoadSizeInBytes) 3705 continue; 3706 3707 // Load subword. 3708 SDValue LoadPtr = DAG.getNode(ISD::ADD, DL, PtrTy, Arg, 3709 DAG.getConstant(OffsetInBytes, DL, 3710 PtrTy)); 3711 SDValue LoadVal = DAG.getExtLoad( 3712 ISD::ZEXTLOAD, DL, RegTy, Chain, LoadPtr, MachinePointerInfo(), 3713 MVT::getIntegerVT(LoadSizeInBytes * 8), false, false, false, 3714 Alignment); 3715 MemOpChains.push_back(LoadVal.getValue(1)); 3716 3717 // Shift the loaded value. 3718 unsigned Shamt; 3719 3720 if (isLittle) 3721 Shamt = TotalBytesLoaded * 8; 3722 else 3723 Shamt = (RegSizeInBytes - (TotalBytesLoaded + LoadSizeInBytes)) * 8; 3724 3725 SDValue Shift = DAG.getNode(ISD::SHL, DL, RegTy, LoadVal, 3726 DAG.getConstant(Shamt, DL, MVT::i32)); 3727 3728 if (Val.getNode()) 3729 Val = DAG.getNode(ISD::OR, DL, RegTy, Val, Shift); 3730 else 3731 Val = Shift; 3732 3733 OffsetInBytes += LoadSizeInBytes; 3734 TotalBytesLoaded += LoadSizeInBytes; 3735 Alignment = std::min(Alignment, LoadSizeInBytes); 3736 } 3737 3738 unsigned ArgReg = ArgRegs[FirstReg + I]; 3739 RegsToPass.push_back(std::make_pair(ArgReg, Val)); 3740 return; 3741 } 3742 } 3743 3744 // Copy remainder of byval arg to it with memcpy. 3745 unsigned MemCpySize = ByValSizeInBytes - OffsetInBytes; 3746 SDValue Src = DAG.getNode(ISD::ADD, DL, PtrTy, Arg, 3747 DAG.getConstant(OffsetInBytes, DL, PtrTy)); 3748 SDValue Dst = DAG.getNode(ISD::ADD, DL, PtrTy, StackPtr, 3749 DAG.getIntPtrConstant(VA.getLocMemOffset(), DL)); 3750 Chain = DAG.getMemcpy(Chain, DL, Dst, Src, 3751 DAG.getConstant(MemCpySize, DL, PtrTy), 3752 Alignment, /*isVolatile=*/false, /*AlwaysInline=*/false, 3753 /*isTailCall=*/false, 3754 MachinePointerInfo(), MachinePointerInfo()); 3755 MemOpChains.push_back(Chain); 3756 } 3757 3758 void MipsTargetLowering::writeVarArgRegs(std::vector<SDValue> &OutChains, 3759 SDValue Chain, SDLoc DL, 3760 SelectionDAG &DAG, 3761 CCState &State) const { 3762 const ArrayRef<MCPhysReg> ArgRegs = ABI.GetVarArgRegs(); 3763 unsigned Idx = State.getFirstUnallocated(ArgRegs); 3764 unsigned RegSizeInBytes = Subtarget.getGPRSizeInBytes(); 3765 MVT RegTy = MVT::getIntegerVT(RegSizeInBytes * 8); 3766 const TargetRegisterClass *RC = getRegClassFor(RegTy); 3767 MachineFunction &MF = DAG.getMachineFunction(); 3768 MachineFrameInfo *MFI = MF.getFrameInfo(); 3769 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>(); 3770 3771 // Offset of the first variable argument from stack pointer. 3772 int VaArgOffset; 3773 3774 if (ArgRegs.size() == Idx) 3775 VaArgOffset = 3776 RoundUpToAlignment(State.getNextStackOffset(), RegSizeInBytes); 3777 else { 3778 VaArgOffset = 3779 (int)ABI.GetCalleeAllocdArgSizeInBytes(State.getCallingConv()) - 3780 (int)(RegSizeInBytes * (ArgRegs.size() - Idx)); 3781 } 3782 3783 // Record the frame index of the first variable argument 3784 // which is a value necessary to VASTART. 3785 int FI = MFI->CreateFixedObject(RegSizeInBytes, VaArgOffset, true); 3786 MipsFI->setVarArgsFrameIndex(FI); 3787 3788 // Copy the integer registers that have not been used for argument passing 3789 // to the argument register save area. For O32, the save area is allocated 3790 // in the caller's stack frame, while for N32/64, it is allocated in the 3791 // callee's stack frame. 3792 for (unsigned I = Idx; I < ArgRegs.size(); 3793 ++I, VaArgOffset += RegSizeInBytes) { 3794 unsigned Reg = addLiveIn(MF, ArgRegs[I], RC); 3795 SDValue ArgValue = DAG.getCopyFromReg(Chain, DL, Reg, RegTy); 3796 FI = MFI->CreateFixedObject(RegSizeInBytes, VaArgOffset, true); 3797 SDValue PtrOff = DAG.getFrameIndex(FI, getPointerTy(DAG.getDataLayout())); 3798 SDValue Store = DAG.getStore(Chain, DL, ArgValue, PtrOff, 3799 MachinePointerInfo(), false, false, 0); 3800 cast<StoreSDNode>(Store.getNode())->getMemOperand()->setValue( 3801 (Value *)nullptr); 3802 OutChains.push_back(Store); 3803 } 3804 } 3805 3806 void MipsTargetLowering::HandleByVal(CCState *State, unsigned &Size, 3807 unsigned Align) const { 3808 const TargetFrameLowering *TFL = Subtarget.getFrameLowering(); 3809 3810 assert(Size && "Byval argument's size shouldn't be 0."); 3811 3812 Align = std::min(Align, TFL->getStackAlignment()); 3813 3814 unsigned FirstReg = 0; 3815 unsigned NumRegs = 0; 3816 3817 if (State->getCallingConv() != CallingConv::Fast) { 3818 unsigned RegSizeInBytes = Subtarget.getGPRSizeInBytes(); 3819 const ArrayRef<MCPhysReg> IntArgRegs = ABI.GetByValArgRegs(); 3820 // FIXME: The O32 case actually describes no shadow registers. 3821 const MCPhysReg *ShadowRegs = 3822 ABI.IsO32() ? IntArgRegs.data() : Mips64DPRegs; 3823 3824 // We used to check the size as well but we can't do that anymore since 3825 // CCState::HandleByVal() rounds up the size after calling this function. 3826 assert(!(Align % RegSizeInBytes) && 3827 "Byval argument's alignment should be a multiple of" 3828 "RegSizeInBytes."); 3829 3830 FirstReg = State->getFirstUnallocated(IntArgRegs); 3831 3832 // If Align > RegSizeInBytes, the first arg register must be even. 3833 // FIXME: This condition happens to do the right thing but it's not the 3834 // right way to test it. We want to check that the stack frame offset 3835 // of the register is aligned. 3836 if ((Align > RegSizeInBytes) && (FirstReg % 2)) { 3837 State->AllocateReg(IntArgRegs[FirstReg], ShadowRegs[FirstReg]); 3838 ++FirstReg; 3839 } 3840 3841 // Mark the registers allocated. 3842 Size = RoundUpToAlignment(Size, RegSizeInBytes); 3843 for (unsigned I = FirstReg; Size > 0 && (I < IntArgRegs.size()); 3844 Size -= RegSizeInBytes, ++I, ++NumRegs) 3845 State->AllocateReg(IntArgRegs[I], ShadowRegs[I]); 3846 } 3847 3848 State->addInRegsParamInfo(FirstReg, FirstReg + NumRegs); 3849 } 3850 3851 MachineBasicBlock * 3852 MipsTargetLowering::emitPseudoSELECT(MachineInstr *MI, MachineBasicBlock *BB, 3853 bool isFPCmp, unsigned Opc) const { 3854 assert(!(Subtarget.hasMips4() || Subtarget.hasMips32()) && 3855 "Subtarget already supports SELECT nodes with the use of" 3856 "conditional-move instructions."); 3857 3858 const TargetInstrInfo *TII = 3859 Subtarget.getInstrInfo(); 3860 DebugLoc DL = MI->getDebugLoc(); 3861 3862 // To "insert" a SELECT instruction, we actually have to insert the 3863 // diamond control-flow pattern. The incoming instruction knows the 3864 // destination vreg to set, the condition code register to branch on, the 3865 // true/false values to select between, and a branch opcode to use. 3866 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 3867 MachineFunction::iterator It = BB; 3868 ++It; 3869 3870 // thisMBB: 3871 // ... 3872 // TrueVal = ... 3873 // setcc r1, r2, r3 3874 // bNE r1, r0, copy1MBB 3875 // fallthrough --> copy0MBB 3876 MachineBasicBlock *thisMBB = BB; 3877 MachineFunction *F = BB->getParent(); 3878 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB); 3879 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB); 3880 F->insert(It, copy0MBB); 3881 F->insert(It, sinkMBB); 3882 3883 // Transfer the remainder of BB and its successor edges to sinkMBB. 3884 sinkMBB->splice(sinkMBB->begin(), BB, 3885 std::next(MachineBasicBlock::iterator(MI)), BB->end()); 3886 sinkMBB->transferSuccessorsAndUpdatePHIs(BB); 3887 3888 // Next, add the true and fallthrough blocks as its successors. 3889 BB->addSuccessor(copy0MBB); 3890 BB->addSuccessor(sinkMBB); 3891 3892 if (isFPCmp) { 3893 // bc1[tf] cc, sinkMBB 3894 BuildMI(BB, DL, TII->get(Opc)) 3895 .addReg(MI->getOperand(1).getReg()) 3896 .addMBB(sinkMBB); 3897 } else { 3898 // bne rs, $0, sinkMBB 3899 BuildMI(BB, DL, TII->get(Opc)) 3900 .addReg(MI->getOperand(1).getReg()) 3901 .addReg(Mips::ZERO) 3902 .addMBB(sinkMBB); 3903 } 3904 3905 // copy0MBB: 3906 // %FalseValue = ... 3907 // # fallthrough to sinkMBB 3908 BB = copy0MBB; 3909 3910 // Update machine-CFG edges 3911 BB->addSuccessor(sinkMBB); 3912 3913 // sinkMBB: 3914 // %Result = phi [ %TrueValue, thisMBB ], [ %FalseValue, copy0MBB ] 3915 // ... 3916 BB = sinkMBB; 3917 3918 BuildMI(*BB, BB->begin(), DL, 3919 TII->get(Mips::PHI), MI->getOperand(0).getReg()) 3920 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB) 3921 .addReg(MI->getOperand(3).getReg()).addMBB(copy0MBB); 3922 3923 MI->eraseFromParent(); // The pseudo instruction is gone now. 3924 3925 return BB; 3926 } 3927 3928 // FIXME? Maybe this could be a TableGen attribute on some registers and 3929 // this table could be generated automatically from RegInfo. 3930 unsigned MipsTargetLowering::getRegisterByName(const char* RegName, EVT VT, 3931 SelectionDAG &DAG) const { 3932 // Named registers is expected to be fairly rare. For now, just support $28 3933 // since the linux kernel uses it. 3934 if (Subtarget.isGP64bit()) { 3935 unsigned Reg = StringSwitch<unsigned>(RegName) 3936 .Case("$28", Mips::GP_64) 3937 .Default(0); 3938 if (Reg) 3939 return Reg; 3940 } else { 3941 unsigned Reg = StringSwitch<unsigned>(RegName) 3942 .Case("$28", Mips::GP) 3943 .Default(0); 3944 if (Reg) 3945 return Reg; 3946 } 3947 report_fatal_error("Invalid register name global variable"); 3948 } 3949