1 //===-- MipsISelLowering.cpp - Mips DAG Lowering Implementation -----------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file defines the interfaces that Mips uses to lower LLVM code into a 11 // selection DAG. 12 // 13 //===----------------------------------------------------------------------===// 14 #include "MipsISelLowering.h" 15 #include "InstPrinter/MipsInstPrinter.h" 16 #include "MCTargetDesc/MipsBaseInfo.h" 17 #include "MipsCCState.h" 18 #include "MipsMachineFunction.h" 19 #include "MipsSubtarget.h" 20 #include "MipsTargetMachine.h" 21 #include "MipsTargetObjectFile.h" 22 #include "llvm/ADT/Statistic.h" 23 #include "llvm/ADT/StringSwitch.h" 24 #include "llvm/CodeGen/CallingConvLower.h" 25 #include "llvm/CodeGen/FunctionLoweringInfo.h" 26 #include "llvm/CodeGen/MachineFrameInfo.h" 27 #include "llvm/CodeGen/MachineFunction.h" 28 #include "llvm/CodeGen/MachineInstrBuilder.h" 29 #include "llvm/CodeGen/MachineJumpTableInfo.h" 30 #include "llvm/CodeGen/MachineRegisterInfo.h" 31 #include "llvm/CodeGen/SelectionDAGISel.h" 32 #include "llvm/CodeGen/ValueTypes.h" 33 #include "llvm/IR/CallingConv.h" 34 #include "llvm/IR/DerivedTypes.h" 35 #include "llvm/IR/GlobalVariable.h" 36 #include "llvm/Support/CommandLine.h" 37 #include "llvm/Support/Debug.h" 38 #include "llvm/Support/ErrorHandling.h" 39 #include "llvm/Support/raw_ostream.h" 40 #include <cctype> 41 42 using namespace llvm; 43 44 #define DEBUG_TYPE "mips-lower" 45 46 STATISTIC(NumTailCalls, "Number of tail calls"); 47 48 static cl::opt<bool> 49 LargeGOT("mxgot", cl::Hidden, 50 cl::desc("MIPS: Enable GOT larger than 64k."), cl::init(false)); 51 52 static cl::opt<bool> 53 NoZeroDivCheck("mno-check-zero-division", cl::Hidden, 54 cl::desc("MIPS: Don't trap on integer division by zero."), 55 cl::init(false)); 56 57 static const MCPhysReg Mips64DPRegs[8] = { 58 Mips::D12_64, Mips::D13_64, Mips::D14_64, Mips::D15_64, 59 Mips::D16_64, Mips::D17_64, Mips::D18_64, Mips::D19_64 60 }; 61 62 // If I is a shifted mask, set the size (Size) and the first bit of the 63 // mask (Pos), and return true. 64 // For example, if I is 0x003ff800, (Pos, Size) = (11, 11). 65 static bool isShiftedMask(uint64_t I, uint64_t &Pos, uint64_t &Size) { 66 if (!isShiftedMask_64(I)) 67 return false; 68 69 Size = countPopulation(I); 70 Pos = countTrailingZeros(I); 71 return true; 72 } 73 74 // The MIPS MSA ABI passes vector arguments in the integer register set. 75 // The number of integer registers used is dependant on the ABI used. 76 MVT MipsTargetLowering::getRegisterTypeForCallingConv(MVT VT) const { 77 if (VT.isVector() && Subtarget.hasMSA()) 78 return Subtarget.isABI_O32() ? MVT::i32 : MVT::i64; 79 return MipsTargetLowering::getRegisterType(VT); 80 } 81 82 MVT MipsTargetLowering::getRegisterTypeForCallingConv(LLVMContext &Context, 83 EVT VT) const { 84 if (VT.isVector()) { 85 if (Subtarget.isABI_O32()) { 86 return MVT::i32; 87 } else { 88 return (VT.getSizeInBits() == 32) ? MVT::i32 : MVT::i64; 89 } 90 } 91 return MipsTargetLowering::getRegisterType(Context, VT); 92 } 93 94 unsigned MipsTargetLowering::getNumRegistersForCallingConv(LLVMContext &Context, 95 EVT VT) const { 96 if (VT.isVector()) 97 return std::max((VT.getSizeInBits() / (Subtarget.isABI_O32() ? 32 : 64)), 98 1U); 99 return MipsTargetLowering::getNumRegisters(Context, VT); 100 } 101 102 unsigned MipsTargetLowering::getVectorTypeBreakdownForCallingConv( 103 LLVMContext &Context, EVT VT, EVT &IntermediateVT, 104 unsigned &NumIntermediates, MVT &RegisterVT) const { 105 106 // Break down vector types to either 2 i64s or 4 i32s. 107 RegisterVT = getRegisterTypeForCallingConv(Context, VT) ; 108 IntermediateVT = RegisterVT; 109 NumIntermediates = VT.getSizeInBits() < RegisterVT.getSizeInBits() 110 ? VT.getVectorNumElements() 111 : VT.getSizeInBits() / RegisterVT.getSizeInBits(); 112 113 return NumIntermediates; 114 } 115 116 SDValue MipsTargetLowering::getGlobalReg(SelectionDAG &DAG, EVT Ty) const { 117 MipsFunctionInfo *FI = DAG.getMachineFunction().getInfo<MipsFunctionInfo>(); 118 return DAG.getRegister(FI->getGlobalBaseReg(), Ty); 119 } 120 121 SDValue MipsTargetLowering::getTargetNode(GlobalAddressSDNode *N, EVT Ty, 122 SelectionDAG &DAG, 123 unsigned Flag) const { 124 return DAG.getTargetGlobalAddress(N->getGlobal(), SDLoc(N), Ty, 0, Flag); 125 } 126 127 SDValue MipsTargetLowering::getTargetNode(ExternalSymbolSDNode *N, EVT Ty, 128 SelectionDAG &DAG, 129 unsigned Flag) const { 130 return DAG.getTargetExternalSymbol(N->getSymbol(), Ty, Flag); 131 } 132 133 SDValue MipsTargetLowering::getTargetNode(BlockAddressSDNode *N, EVT Ty, 134 SelectionDAG &DAG, 135 unsigned Flag) const { 136 return DAG.getTargetBlockAddress(N->getBlockAddress(), Ty, 0, Flag); 137 } 138 139 SDValue MipsTargetLowering::getTargetNode(JumpTableSDNode *N, EVT Ty, 140 SelectionDAG &DAG, 141 unsigned Flag) const { 142 return DAG.getTargetJumpTable(N->getIndex(), Ty, Flag); 143 } 144 145 SDValue MipsTargetLowering::getTargetNode(ConstantPoolSDNode *N, EVT Ty, 146 SelectionDAG &DAG, 147 unsigned Flag) const { 148 return DAG.getTargetConstantPool(N->getConstVal(), Ty, N->getAlignment(), 149 N->getOffset(), Flag); 150 } 151 152 const char *MipsTargetLowering::getTargetNodeName(unsigned Opcode) const { 153 switch ((MipsISD::NodeType)Opcode) { 154 case MipsISD::FIRST_NUMBER: break; 155 case MipsISD::JmpLink: return "MipsISD::JmpLink"; 156 case MipsISD::TailCall: return "MipsISD::TailCall"; 157 case MipsISD::Highest: return "MipsISD::Highest"; 158 case MipsISD::Higher: return "MipsISD::Higher"; 159 case MipsISD::Hi: return "MipsISD::Hi"; 160 case MipsISD::Lo: return "MipsISD::Lo"; 161 case MipsISD::GotHi: return "MipsISD::GotHi"; 162 case MipsISD::GPRel: return "MipsISD::GPRel"; 163 case MipsISD::ThreadPointer: return "MipsISD::ThreadPointer"; 164 case MipsISD::Ret: return "MipsISD::Ret"; 165 case MipsISD::ERet: return "MipsISD::ERet"; 166 case MipsISD::EH_RETURN: return "MipsISD::EH_RETURN"; 167 case MipsISD::FPBrcond: return "MipsISD::FPBrcond"; 168 case MipsISD::FPCmp: return "MipsISD::FPCmp"; 169 case MipsISD::CMovFP_T: return "MipsISD::CMovFP_T"; 170 case MipsISD::CMovFP_F: return "MipsISD::CMovFP_F"; 171 case MipsISD::TruncIntFP: return "MipsISD::TruncIntFP"; 172 case MipsISD::MFHI: return "MipsISD::MFHI"; 173 case MipsISD::MFLO: return "MipsISD::MFLO"; 174 case MipsISD::MTLOHI: return "MipsISD::MTLOHI"; 175 case MipsISD::Mult: return "MipsISD::Mult"; 176 case MipsISD::Multu: return "MipsISD::Multu"; 177 case MipsISD::MAdd: return "MipsISD::MAdd"; 178 case MipsISD::MAddu: return "MipsISD::MAddu"; 179 case MipsISD::MSub: return "MipsISD::MSub"; 180 case MipsISD::MSubu: return "MipsISD::MSubu"; 181 case MipsISD::DivRem: return "MipsISD::DivRem"; 182 case MipsISD::DivRemU: return "MipsISD::DivRemU"; 183 case MipsISD::DivRem16: return "MipsISD::DivRem16"; 184 case MipsISD::DivRemU16: return "MipsISD::DivRemU16"; 185 case MipsISD::BuildPairF64: return "MipsISD::BuildPairF64"; 186 case MipsISD::ExtractElementF64: return "MipsISD::ExtractElementF64"; 187 case MipsISD::Wrapper: return "MipsISD::Wrapper"; 188 case MipsISD::DynAlloc: return "MipsISD::DynAlloc"; 189 case MipsISD::Sync: return "MipsISD::Sync"; 190 case MipsISD::Ext: return "MipsISD::Ext"; 191 case MipsISD::Ins: return "MipsISD::Ins"; 192 case MipsISD::CIns: return "MipsISD::CIns"; 193 case MipsISD::LWL: return "MipsISD::LWL"; 194 case MipsISD::LWR: return "MipsISD::LWR"; 195 case MipsISD::SWL: return "MipsISD::SWL"; 196 case MipsISD::SWR: return "MipsISD::SWR"; 197 case MipsISD::LDL: return "MipsISD::LDL"; 198 case MipsISD::LDR: return "MipsISD::LDR"; 199 case MipsISD::SDL: return "MipsISD::SDL"; 200 case MipsISD::SDR: return "MipsISD::SDR"; 201 case MipsISD::EXTP: return "MipsISD::EXTP"; 202 case MipsISD::EXTPDP: return "MipsISD::EXTPDP"; 203 case MipsISD::EXTR_S_H: return "MipsISD::EXTR_S_H"; 204 case MipsISD::EXTR_W: return "MipsISD::EXTR_W"; 205 case MipsISD::EXTR_R_W: return "MipsISD::EXTR_R_W"; 206 case MipsISD::EXTR_RS_W: return "MipsISD::EXTR_RS_W"; 207 case MipsISD::SHILO: return "MipsISD::SHILO"; 208 case MipsISD::MTHLIP: return "MipsISD::MTHLIP"; 209 case MipsISD::MULSAQ_S_W_PH: return "MipsISD::MULSAQ_S_W_PH"; 210 case MipsISD::MAQ_S_W_PHL: return "MipsISD::MAQ_S_W_PHL"; 211 case MipsISD::MAQ_S_W_PHR: return "MipsISD::MAQ_S_W_PHR"; 212 case MipsISD::MAQ_SA_W_PHL: return "MipsISD::MAQ_SA_W_PHL"; 213 case MipsISD::MAQ_SA_W_PHR: return "MipsISD::MAQ_SA_W_PHR"; 214 case MipsISD::DPAU_H_QBL: return "MipsISD::DPAU_H_QBL"; 215 case MipsISD::DPAU_H_QBR: return "MipsISD::DPAU_H_QBR"; 216 case MipsISD::DPSU_H_QBL: return "MipsISD::DPSU_H_QBL"; 217 case MipsISD::DPSU_H_QBR: return "MipsISD::DPSU_H_QBR"; 218 case MipsISD::DPAQ_S_W_PH: return "MipsISD::DPAQ_S_W_PH"; 219 case MipsISD::DPSQ_S_W_PH: return "MipsISD::DPSQ_S_W_PH"; 220 case MipsISD::DPAQ_SA_L_W: return "MipsISD::DPAQ_SA_L_W"; 221 case MipsISD::DPSQ_SA_L_W: return "MipsISD::DPSQ_SA_L_W"; 222 case MipsISD::DPA_W_PH: return "MipsISD::DPA_W_PH"; 223 case MipsISD::DPS_W_PH: return "MipsISD::DPS_W_PH"; 224 case MipsISD::DPAQX_S_W_PH: return "MipsISD::DPAQX_S_W_PH"; 225 case MipsISD::DPAQX_SA_W_PH: return "MipsISD::DPAQX_SA_W_PH"; 226 case MipsISD::DPAX_W_PH: return "MipsISD::DPAX_W_PH"; 227 case MipsISD::DPSX_W_PH: return "MipsISD::DPSX_W_PH"; 228 case MipsISD::DPSQX_S_W_PH: return "MipsISD::DPSQX_S_W_PH"; 229 case MipsISD::DPSQX_SA_W_PH: return "MipsISD::DPSQX_SA_W_PH"; 230 case MipsISD::MULSA_W_PH: return "MipsISD::MULSA_W_PH"; 231 case MipsISD::MULT: return "MipsISD::MULT"; 232 case MipsISD::MULTU: return "MipsISD::MULTU"; 233 case MipsISD::MADD_DSP: return "MipsISD::MADD_DSP"; 234 case MipsISD::MADDU_DSP: return "MipsISD::MADDU_DSP"; 235 case MipsISD::MSUB_DSP: return "MipsISD::MSUB_DSP"; 236 case MipsISD::MSUBU_DSP: return "MipsISD::MSUBU_DSP"; 237 case MipsISD::SHLL_DSP: return "MipsISD::SHLL_DSP"; 238 case MipsISD::SHRA_DSP: return "MipsISD::SHRA_DSP"; 239 case MipsISD::SHRL_DSP: return "MipsISD::SHRL_DSP"; 240 case MipsISD::SETCC_DSP: return "MipsISD::SETCC_DSP"; 241 case MipsISD::SELECT_CC_DSP: return "MipsISD::SELECT_CC_DSP"; 242 case MipsISD::VALL_ZERO: return "MipsISD::VALL_ZERO"; 243 case MipsISD::VANY_ZERO: return "MipsISD::VANY_ZERO"; 244 case MipsISD::VALL_NONZERO: return "MipsISD::VALL_NONZERO"; 245 case MipsISD::VANY_NONZERO: return "MipsISD::VANY_NONZERO"; 246 case MipsISD::VCEQ: return "MipsISD::VCEQ"; 247 case MipsISD::VCLE_S: return "MipsISD::VCLE_S"; 248 case MipsISD::VCLE_U: return "MipsISD::VCLE_U"; 249 case MipsISD::VCLT_S: return "MipsISD::VCLT_S"; 250 case MipsISD::VCLT_U: return "MipsISD::VCLT_U"; 251 case MipsISD::VSMAX: return "MipsISD::VSMAX"; 252 case MipsISD::VSMIN: return "MipsISD::VSMIN"; 253 case MipsISD::VUMAX: return "MipsISD::VUMAX"; 254 case MipsISD::VUMIN: return "MipsISD::VUMIN"; 255 case MipsISD::VEXTRACT_SEXT_ELT: return "MipsISD::VEXTRACT_SEXT_ELT"; 256 case MipsISD::VEXTRACT_ZEXT_ELT: return "MipsISD::VEXTRACT_ZEXT_ELT"; 257 case MipsISD::VNOR: return "MipsISD::VNOR"; 258 case MipsISD::VSHF: return "MipsISD::VSHF"; 259 case MipsISD::SHF: return "MipsISD::SHF"; 260 case MipsISD::ILVEV: return "MipsISD::ILVEV"; 261 case MipsISD::ILVOD: return "MipsISD::ILVOD"; 262 case MipsISD::ILVL: return "MipsISD::ILVL"; 263 case MipsISD::ILVR: return "MipsISD::ILVR"; 264 case MipsISD::PCKEV: return "MipsISD::PCKEV"; 265 case MipsISD::PCKOD: return "MipsISD::PCKOD"; 266 case MipsISD::INSVE: return "MipsISD::INSVE"; 267 } 268 return nullptr; 269 } 270 271 MipsTargetLowering::MipsTargetLowering(const MipsTargetMachine &TM, 272 const MipsSubtarget &STI) 273 : TargetLowering(TM), Subtarget(STI), ABI(TM.getABI()) { 274 // Mips does not have i1 type, so use i32 for 275 // setcc operations results (slt, sgt, ...). 276 setBooleanContents(ZeroOrOneBooleanContent); 277 setBooleanVectorContents(ZeroOrNegativeOneBooleanContent); 278 // The cmp.cond.fmt instruction in MIPS32r6/MIPS64r6 uses 0 and -1 like MSA 279 // does. Integer booleans still use 0 and 1. 280 if (Subtarget.hasMips32r6()) 281 setBooleanContents(ZeroOrOneBooleanContent, 282 ZeroOrNegativeOneBooleanContent); 283 284 // Load extented operations for i1 types must be promoted 285 for (MVT VT : MVT::integer_valuetypes()) { 286 setLoadExtAction(ISD::EXTLOAD, VT, MVT::i1, Promote); 287 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i1, Promote); 288 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i1, Promote); 289 } 290 291 // MIPS doesn't have extending float->double load/store. Set LoadExtAction 292 // for f32, f16 293 for (MVT VT : MVT::fp_valuetypes()) { 294 setLoadExtAction(ISD::EXTLOAD, VT, MVT::f32, Expand); 295 setLoadExtAction(ISD::EXTLOAD, VT, MVT::f16, Expand); 296 } 297 298 // Set LoadExtAction for f16 vectors to Expand 299 for (MVT VT : MVT::fp_vector_valuetypes()) { 300 MVT F16VT = MVT::getVectorVT(MVT::f16, VT.getVectorNumElements()); 301 if (F16VT.isValid()) 302 setLoadExtAction(ISD::EXTLOAD, VT, F16VT, Expand); 303 } 304 305 setTruncStoreAction(MVT::f32, MVT::f16, Expand); 306 setTruncStoreAction(MVT::f64, MVT::f16, Expand); 307 308 setTruncStoreAction(MVT::f64, MVT::f32, Expand); 309 310 // Used by legalize types to correctly generate the setcc result. 311 // Without this, every float setcc comes with a AND/OR with the result, 312 // we don't want this, since the fpcmp result goes to a flag register, 313 // which is used implicitly by brcond and select operations. 314 AddPromotedToType(ISD::SETCC, MVT::i1, MVT::i32); 315 316 // Mips Custom Operations 317 setOperationAction(ISD::BR_JT, MVT::Other, Expand); 318 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom); 319 setOperationAction(ISD::BlockAddress, MVT::i32, Custom); 320 setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom); 321 setOperationAction(ISD::JumpTable, MVT::i32, Custom); 322 setOperationAction(ISD::ConstantPool, MVT::i32, Custom); 323 setOperationAction(ISD::SELECT, MVT::f32, Custom); 324 setOperationAction(ISD::SELECT, MVT::f64, Custom); 325 setOperationAction(ISD::SELECT, MVT::i32, Custom); 326 setOperationAction(ISD::SETCC, MVT::f32, Custom); 327 setOperationAction(ISD::SETCC, MVT::f64, Custom); 328 setOperationAction(ISD::BRCOND, MVT::Other, Custom); 329 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom); 330 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom); 331 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom); 332 333 if (Subtarget.isGP64bit()) { 334 setOperationAction(ISD::GlobalAddress, MVT::i64, Custom); 335 setOperationAction(ISD::BlockAddress, MVT::i64, Custom); 336 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom); 337 setOperationAction(ISD::JumpTable, MVT::i64, Custom); 338 setOperationAction(ISD::ConstantPool, MVT::i64, Custom); 339 setOperationAction(ISD::SELECT, MVT::i64, Custom); 340 setOperationAction(ISD::LOAD, MVT::i64, Custom); 341 setOperationAction(ISD::STORE, MVT::i64, Custom); 342 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom); 343 setOperationAction(ISD::SHL_PARTS, MVT::i64, Custom); 344 setOperationAction(ISD::SRA_PARTS, MVT::i64, Custom); 345 setOperationAction(ISD::SRL_PARTS, MVT::i64, Custom); 346 } 347 348 if (!Subtarget.isGP64bit()) { 349 setOperationAction(ISD::SHL_PARTS, MVT::i32, Custom); 350 setOperationAction(ISD::SRA_PARTS, MVT::i32, Custom); 351 setOperationAction(ISD::SRL_PARTS, MVT::i32, Custom); 352 } 353 354 setOperationAction(ISD::EH_DWARF_CFA, MVT::i32, Custom); 355 if (Subtarget.isGP64bit()) 356 setOperationAction(ISD::EH_DWARF_CFA, MVT::i64, Custom); 357 358 setOperationAction(ISD::SDIV, MVT::i32, Expand); 359 setOperationAction(ISD::SREM, MVT::i32, Expand); 360 setOperationAction(ISD::UDIV, MVT::i32, Expand); 361 setOperationAction(ISD::UREM, MVT::i32, Expand); 362 setOperationAction(ISD::SDIV, MVT::i64, Expand); 363 setOperationAction(ISD::SREM, MVT::i64, Expand); 364 setOperationAction(ISD::UDIV, MVT::i64, Expand); 365 setOperationAction(ISD::UREM, MVT::i64, Expand); 366 367 // Operations not directly supported by Mips. 368 setOperationAction(ISD::BR_CC, MVT::f32, Expand); 369 setOperationAction(ISD::BR_CC, MVT::f64, Expand); 370 setOperationAction(ISD::BR_CC, MVT::i32, Expand); 371 setOperationAction(ISD::BR_CC, MVT::i64, Expand); 372 setOperationAction(ISD::SELECT_CC, MVT::i32, Expand); 373 setOperationAction(ISD::SELECT_CC, MVT::i64, Expand); 374 setOperationAction(ISD::SELECT_CC, MVT::f32, Expand); 375 setOperationAction(ISD::SELECT_CC, MVT::f64, Expand); 376 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand); 377 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Expand); 378 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand); 379 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Expand); 380 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand); 381 if (Subtarget.hasCnMips()) { 382 setOperationAction(ISD::CTPOP, MVT::i32, Legal); 383 setOperationAction(ISD::CTPOP, MVT::i64, Legal); 384 } else { 385 setOperationAction(ISD::CTPOP, MVT::i32, Expand); 386 setOperationAction(ISD::CTPOP, MVT::i64, Expand); 387 } 388 setOperationAction(ISD::CTTZ, MVT::i32, Expand); 389 setOperationAction(ISD::CTTZ, MVT::i64, Expand); 390 setOperationAction(ISD::ROTL, MVT::i32, Expand); 391 setOperationAction(ISD::ROTL, MVT::i64, Expand); 392 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Expand); 393 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64, Expand); 394 395 if (!Subtarget.hasMips32r2()) 396 setOperationAction(ISD::ROTR, MVT::i32, Expand); 397 398 if (!Subtarget.hasMips64r2()) 399 setOperationAction(ISD::ROTR, MVT::i64, Expand); 400 401 setOperationAction(ISD::FSIN, MVT::f32, Expand); 402 setOperationAction(ISD::FSIN, MVT::f64, Expand); 403 setOperationAction(ISD::FCOS, MVT::f32, Expand); 404 setOperationAction(ISD::FCOS, MVT::f64, Expand); 405 setOperationAction(ISD::FSINCOS, MVT::f32, Expand); 406 setOperationAction(ISD::FSINCOS, MVT::f64, Expand); 407 setOperationAction(ISD::FPOW, MVT::f32, Expand); 408 setOperationAction(ISD::FPOW, MVT::f64, Expand); 409 setOperationAction(ISD::FLOG, MVT::f32, Expand); 410 setOperationAction(ISD::FLOG2, MVT::f32, Expand); 411 setOperationAction(ISD::FLOG10, MVT::f32, Expand); 412 setOperationAction(ISD::FEXP, MVT::f32, Expand); 413 setOperationAction(ISD::FMA, MVT::f32, Expand); 414 setOperationAction(ISD::FMA, MVT::f64, Expand); 415 setOperationAction(ISD::FREM, MVT::f32, Expand); 416 setOperationAction(ISD::FREM, MVT::f64, Expand); 417 418 // Lower f16 conversion operations into library calls 419 setOperationAction(ISD::FP16_TO_FP, MVT::f32, Expand); 420 setOperationAction(ISD::FP_TO_FP16, MVT::f32, Expand); 421 setOperationAction(ISD::FP16_TO_FP, MVT::f64, Expand); 422 setOperationAction(ISD::FP_TO_FP16, MVT::f64, Expand); 423 424 setOperationAction(ISD::EH_RETURN, MVT::Other, Custom); 425 426 setOperationAction(ISD::VASTART, MVT::Other, Custom); 427 setOperationAction(ISD::VAARG, MVT::Other, Custom); 428 setOperationAction(ISD::VACOPY, MVT::Other, Expand); 429 setOperationAction(ISD::VAEND, MVT::Other, Expand); 430 431 // Use the default for now 432 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand); 433 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand); 434 435 if (!Subtarget.isGP64bit()) { 436 setOperationAction(ISD::ATOMIC_LOAD, MVT::i64, Expand); 437 setOperationAction(ISD::ATOMIC_STORE, MVT::i64, Expand); 438 } 439 440 441 if (!Subtarget.hasMips32r2()) { 442 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8, Expand); 443 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand); 444 } 445 446 // MIPS16 lacks MIPS32's clz and clo instructions. 447 if (!Subtarget.hasMips32() || Subtarget.inMips16Mode()) 448 setOperationAction(ISD::CTLZ, MVT::i32, Expand); 449 if (!Subtarget.hasMips64()) 450 setOperationAction(ISD::CTLZ, MVT::i64, Expand); 451 452 if (!Subtarget.hasMips32r2()) 453 setOperationAction(ISD::BSWAP, MVT::i32, Expand); 454 if (!Subtarget.hasMips64r2()) 455 setOperationAction(ISD::BSWAP, MVT::i64, Expand); 456 457 if (Subtarget.isGP64bit()) { 458 setLoadExtAction(ISD::SEXTLOAD, MVT::i64, MVT::i32, Custom); 459 setLoadExtAction(ISD::ZEXTLOAD, MVT::i64, MVT::i32, Custom); 460 setLoadExtAction(ISD::EXTLOAD, MVT::i64, MVT::i32, Custom); 461 setTruncStoreAction(MVT::i64, MVT::i32, Custom); 462 } 463 464 setOperationAction(ISD::TRAP, MVT::Other, Legal); 465 466 setTargetDAGCombine(ISD::SDIVREM); 467 setTargetDAGCombine(ISD::UDIVREM); 468 setTargetDAGCombine(ISD::SELECT); 469 setTargetDAGCombine(ISD::AND); 470 setTargetDAGCombine(ISD::OR); 471 setTargetDAGCombine(ISD::ADD); 472 setTargetDAGCombine(ISD::AssertZext); 473 setTargetDAGCombine(ISD::SHL); 474 475 if (ABI.IsO32()) { 476 // These libcalls are not available in 32-bit. 477 setLibcallName(RTLIB::SHL_I128, nullptr); 478 setLibcallName(RTLIB::SRL_I128, nullptr); 479 setLibcallName(RTLIB::SRA_I128, nullptr); 480 } 481 482 setMinFunctionAlignment(Subtarget.isGP64bit() ? 3 : 2); 483 484 // The arguments on the stack are defined in terms of 4-byte slots on O32 485 // and 8-byte slots on N32/N64. 486 setMinStackArgumentAlignment((ABI.IsN32() || ABI.IsN64()) ? 8 : 4); 487 488 setStackPointerRegisterToSaveRestore(ABI.IsN64() ? Mips::SP_64 : Mips::SP); 489 490 MaxStoresPerMemcpy = 16; 491 492 isMicroMips = Subtarget.inMicroMipsMode(); 493 } 494 495 const MipsTargetLowering *MipsTargetLowering::create(const MipsTargetMachine &TM, 496 const MipsSubtarget &STI) { 497 if (STI.inMips16Mode()) 498 return llvm::createMips16TargetLowering(TM, STI); 499 500 return llvm::createMipsSETargetLowering(TM, STI); 501 } 502 503 // Create a fast isel object. 504 FastISel * 505 MipsTargetLowering::createFastISel(FunctionLoweringInfo &funcInfo, 506 const TargetLibraryInfo *libInfo) const { 507 const MipsTargetMachine &TM = 508 static_cast<const MipsTargetMachine &>(funcInfo.MF->getTarget()); 509 510 // We support only the standard encoding [MIPS32,MIPS32R5] ISAs. 511 bool UseFastISel = TM.Options.EnableFastISel && Subtarget.hasMips32() && 512 !Subtarget.hasMips32r6() && !Subtarget.inMips16Mode() && 513 !Subtarget.inMicroMipsMode(); 514 515 // Disable if either of the following is true: 516 // We do not generate PIC, the ABI is not O32, LargeGOT is being used. 517 if (!TM.isPositionIndependent() || !TM.getABI().IsO32() || LargeGOT) 518 UseFastISel = false; 519 520 return UseFastISel ? Mips::createFastISel(funcInfo, libInfo) : nullptr; 521 } 522 523 EVT MipsTargetLowering::getSetCCResultType(const DataLayout &, LLVMContext &, 524 EVT VT) const { 525 if (!VT.isVector()) 526 return MVT::i32; 527 return VT.changeVectorElementTypeToInteger(); 528 } 529 530 static SDValue performDivRemCombine(SDNode *N, SelectionDAG &DAG, 531 TargetLowering::DAGCombinerInfo &DCI, 532 const MipsSubtarget &Subtarget) { 533 if (DCI.isBeforeLegalizeOps()) 534 return SDValue(); 535 536 EVT Ty = N->getValueType(0); 537 unsigned LO = (Ty == MVT::i32) ? Mips::LO0 : Mips::LO0_64; 538 unsigned HI = (Ty == MVT::i32) ? Mips::HI0 : Mips::HI0_64; 539 unsigned Opc = N->getOpcode() == ISD::SDIVREM ? MipsISD::DivRem16 : 540 MipsISD::DivRemU16; 541 SDLoc DL(N); 542 543 SDValue DivRem = DAG.getNode(Opc, DL, MVT::Glue, 544 N->getOperand(0), N->getOperand(1)); 545 SDValue InChain = DAG.getEntryNode(); 546 SDValue InGlue = DivRem; 547 548 // insert MFLO 549 if (N->hasAnyUseOfValue(0)) { 550 SDValue CopyFromLo = DAG.getCopyFromReg(InChain, DL, LO, Ty, 551 InGlue); 552 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), CopyFromLo); 553 InChain = CopyFromLo.getValue(1); 554 InGlue = CopyFromLo.getValue(2); 555 } 556 557 // insert MFHI 558 if (N->hasAnyUseOfValue(1)) { 559 SDValue CopyFromHi = DAG.getCopyFromReg(InChain, DL, 560 HI, Ty, InGlue); 561 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), CopyFromHi); 562 } 563 564 return SDValue(); 565 } 566 567 static Mips::CondCode condCodeToFCC(ISD::CondCode CC) { 568 switch (CC) { 569 default: llvm_unreachable("Unknown fp condition code!"); 570 case ISD::SETEQ: 571 case ISD::SETOEQ: return Mips::FCOND_OEQ; 572 case ISD::SETUNE: return Mips::FCOND_UNE; 573 case ISD::SETLT: 574 case ISD::SETOLT: return Mips::FCOND_OLT; 575 case ISD::SETGT: 576 case ISD::SETOGT: return Mips::FCOND_OGT; 577 case ISD::SETLE: 578 case ISD::SETOLE: return Mips::FCOND_OLE; 579 case ISD::SETGE: 580 case ISD::SETOGE: return Mips::FCOND_OGE; 581 case ISD::SETULT: return Mips::FCOND_ULT; 582 case ISD::SETULE: return Mips::FCOND_ULE; 583 case ISD::SETUGT: return Mips::FCOND_UGT; 584 case ISD::SETUGE: return Mips::FCOND_UGE; 585 case ISD::SETUO: return Mips::FCOND_UN; 586 case ISD::SETO: return Mips::FCOND_OR; 587 case ISD::SETNE: 588 case ISD::SETONE: return Mips::FCOND_ONE; 589 case ISD::SETUEQ: return Mips::FCOND_UEQ; 590 } 591 } 592 593 594 /// This function returns true if the floating point conditional branches and 595 /// conditional moves which use condition code CC should be inverted. 596 static bool invertFPCondCodeUser(Mips::CondCode CC) { 597 if (CC >= Mips::FCOND_F && CC <= Mips::FCOND_NGT) 598 return false; 599 600 assert((CC >= Mips::FCOND_T && CC <= Mips::FCOND_GT) && 601 "Illegal Condition Code"); 602 603 return true; 604 } 605 606 // Creates and returns an FPCmp node from a setcc node. 607 // Returns Op if setcc is not a floating point comparison. 608 static SDValue createFPCmp(SelectionDAG &DAG, const SDValue &Op) { 609 // must be a SETCC node 610 if (Op.getOpcode() != ISD::SETCC) 611 return Op; 612 613 SDValue LHS = Op.getOperand(0); 614 615 if (!LHS.getValueType().isFloatingPoint()) 616 return Op; 617 618 SDValue RHS = Op.getOperand(1); 619 SDLoc DL(Op); 620 621 // Assume the 3rd operand is a CondCodeSDNode. Add code to check the type of 622 // node if necessary. 623 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get(); 624 625 return DAG.getNode(MipsISD::FPCmp, DL, MVT::Glue, LHS, RHS, 626 DAG.getConstant(condCodeToFCC(CC), DL, MVT::i32)); 627 } 628 629 // Creates and returns a CMovFPT/F node. 630 static SDValue createCMovFP(SelectionDAG &DAG, SDValue Cond, SDValue True, 631 SDValue False, const SDLoc &DL) { 632 ConstantSDNode *CC = cast<ConstantSDNode>(Cond.getOperand(2)); 633 bool invert = invertFPCondCodeUser((Mips::CondCode)CC->getSExtValue()); 634 SDValue FCC0 = DAG.getRegister(Mips::FCC0, MVT::i32); 635 636 return DAG.getNode((invert ? MipsISD::CMovFP_F : MipsISD::CMovFP_T), DL, 637 True.getValueType(), True, FCC0, False, Cond); 638 } 639 640 static SDValue performSELECTCombine(SDNode *N, SelectionDAG &DAG, 641 TargetLowering::DAGCombinerInfo &DCI, 642 const MipsSubtarget &Subtarget) { 643 if (DCI.isBeforeLegalizeOps()) 644 return SDValue(); 645 646 SDValue SetCC = N->getOperand(0); 647 648 if ((SetCC.getOpcode() != ISD::SETCC) || 649 !SetCC.getOperand(0).getValueType().isInteger()) 650 return SDValue(); 651 652 SDValue False = N->getOperand(2); 653 EVT FalseTy = False.getValueType(); 654 655 if (!FalseTy.isInteger()) 656 return SDValue(); 657 658 ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(False); 659 660 // If the RHS (False) is 0, we swap the order of the operands 661 // of ISD::SELECT (obviously also inverting the condition) so that we can 662 // take advantage of conditional moves using the $0 register. 663 // Example: 664 // return (a != 0) ? x : 0; 665 // load $reg, x 666 // movz $reg, $0, a 667 if (!FalseC) 668 return SDValue(); 669 670 const SDLoc DL(N); 671 672 if (!FalseC->getZExtValue()) { 673 ISD::CondCode CC = cast<CondCodeSDNode>(SetCC.getOperand(2))->get(); 674 SDValue True = N->getOperand(1); 675 676 SetCC = DAG.getSetCC(DL, SetCC.getValueType(), SetCC.getOperand(0), 677 SetCC.getOperand(1), ISD::getSetCCInverse(CC, true)); 678 679 return DAG.getNode(ISD::SELECT, DL, FalseTy, SetCC, False, True); 680 } 681 682 // If both operands are integer constants there's a possibility that we 683 // can do some interesting optimizations. 684 SDValue True = N->getOperand(1); 685 ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(True); 686 687 if (!TrueC || !True.getValueType().isInteger()) 688 return SDValue(); 689 690 // We'll also ignore MVT::i64 operands as this optimizations proves 691 // to be ineffective because of the required sign extensions as the result 692 // of a SETCC operator is always MVT::i32 for non-vector types. 693 if (True.getValueType() == MVT::i64) 694 return SDValue(); 695 696 int64_t Diff = TrueC->getSExtValue() - FalseC->getSExtValue(); 697 698 // 1) (a < x) ? y : y-1 699 // slti $reg1, a, x 700 // addiu $reg2, $reg1, y-1 701 if (Diff == 1) 702 return DAG.getNode(ISD::ADD, DL, SetCC.getValueType(), SetCC, False); 703 704 // 2) (a < x) ? y-1 : y 705 // slti $reg1, a, x 706 // xor $reg1, $reg1, 1 707 // addiu $reg2, $reg1, y-1 708 if (Diff == -1) { 709 ISD::CondCode CC = cast<CondCodeSDNode>(SetCC.getOperand(2))->get(); 710 SetCC = DAG.getSetCC(DL, SetCC.getValueType(), SetCC.getOperand(0), 711 SetCC.getOperand(1), ISD::getSetCCInverse(CC, true)); 712 return DAG.getNode(ISD::ADD, DL, SetCC.getValueType(), SetCC, True); 713 } 714 715 // Couldn't optimize. 716 return SDValue(); 717 } 718 719 static SDValue performCMovFPCombine(SDNode *N, SelectionDAG &DAG, 720 TargetLowering::DAGCombinerInfo &DCI, 721 const MipsSubtarget &Subtarget) { 722 if (DCI.isBeforeLegalizeOps()) 723 return SDValue(); 724 725 SDValue ValueIfTrue = N->getOperand(0), ValueIfFalse = N->getOperand(2); 726 727 ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(ValueIfFalse); 728 if (!FalseC || FalseC->getZExtValue()) 729 return SDValue(); 730 731 // Since RHS (False) is 0, we swap the order of the True/False operands 732 // (obviously also inverting the condition) so that we can 733 // take advantage of conditional moves using the $0 register. 734 // Example: 735 // return (a != 0) ? x : 0; 736 // load $reg, x 737 // movz $reg, $0, a 738 unsigned Opc = (N->getOpcode() == MipsISD::CMovFP_T) ? MipsISD::CMovFP_F : 739 MipsISD::CMovFP_T; 740 741 SDValue FCC = N->getOperand(1), Glue = N->getOperand(3); 742 return DAG.getNode(Opc, SDLoc(N), ValueIfFalse.getValueType(), 743 ValueIfFalse, FCC, ValueIfTrue, Glue); 744 } 745 746 static SDValue performANDCombine(SDNode *N, SelectionDAG &DAG, 747 TargetLowering::DAGCombinerInfo &DCI, 748 const MipsSubtarget &Subtarget) { 749 if (DCI.isBeforeLegalizeOps() || !Subtarget.hasExtractInsert()) 750 return SDValue(); 751 752 SDValue FirstOperand = N->getOperand(0); 753 unsigned FirstOperandOpc = FirstOperand.getOpcode(); 754 SDValue Mask = N->getOperand(1); 755 EVT ValTy = N->getValueType(0); 756 SDLoc DL(N); 757 758 uint64_t Pos = 0, SMPos, SMSize; 759 ConstantSDNode *CN; 760 SDValue NewOperand; 761 unsigned Opc; 762 763 // Op's second operand must be a shifted mask. 764 if (!(CN = dyn_cast<ConstantSDNode>(Mask)) || 765 !isShiftedMask(CN->getZExtValue(), SMPos, SMSize)) 766 return SDValue(); 767 768 if (FirstOperandOpc == ISD::SRA || FirstOperandOpc == ISD::SRL) { 769 // Pattern match EXT. 770 // $dst = and ((sra or srl) $src , pos), (2**size - 1) 771 // => ext $dst, $src, pos, size 772 773 // The second operand of the shift must be an immediate. 774 if (!(CN = dyn_cast<ConstantSDNode>(FirstOperand.getOperand(1)))) 775 return SDValue(); 776 777 Pos = CN->getZExtValue(); 778 779 // Return if the shifted mask does not start at bit 0 or the sum of its size 780 // and Pos exceeds the word's size. 781 if (SMPos != 0 || Pos + SMSize > ValTy.getSizeInBits()) 782 return SDValue(); 783 784 Opc = MipsISD::Ext; 785 NewOperand = FirstOperand.getOperand(0); 786 } else if (FirstOperandOpc == ISD::SHL && Subtarget.hasCnMips()) { 787 // Pattern match CINS. 788 // $dst = and (shl $src , pos), mask 789 // => cins $dst, $src, pos, size 790 // mask is a shifted mask with consecutive 1's, pos = shift amount, 791 // size = population count. 792 793 // The second operand of the shift must be an immediate. 794 if (!(CN = dyn_cast<ConstantSDNode>(FirstOperand.getOperand(1)))) 795 return SDValue(); 796 797 Pos = CN->getZExtValue(); 798 799 if (SMPos != Pos || Pos >= ValTy.getSizeInBits() || SMSize >= 32 || 800 Pos + SMSize > ValTy.getSizeInBits()) 801 return SDValue(); 802 803 NewOperand = FirstOperand.getOperand(0); 804 // SMSize is 'location' (position) in this case, not size. 805 SMSize--; 806 Opc = MipsISD::CIns; 807 } else { 808 // Pattern match EXT. 809 // $dst = and $src, (2**size - 1) , if size > 16 810 // => ext $dst, $src, pos, size , pos = 0 811 812 // If the mask is <= 0xffff, andi can be used instead. 813 if (CN->getZExtValue() <= 0xffff) 814 return SDValue(); 815 816 // Return if the mask doesn't start at position 0. 817 if (SMPos) 818 return SDValue(); 819 820 Opc = MipsISD::Ext; 821 NewOperand = FirstOperand; 822 } 823 return DAG.getNode(Opc, DL, ValTy, NewOperand, 824 DAG.getConstant(Pos, DL, MVT::i32), 825 DAG.getConstant(SMSize, DL, MVT::i32)); 826 } 827 828 static SDValue performORCombine(SDNode *N, SelectionDAG &DAG, 829 TargetLowering::DAGCombinerInfo &DCI, 830 const MipsSubtarget &Subtarget) { 831 // Pattern match INS. 832 // $dst = or (and $src1 , mask0), (and (shl $src, pos), mask1), 833 // where mask1 = (2**size - 1) << pos, mask0 = ~mask1 834 // => ins $dst, $src, size, pos, $src1 835 if (DCI.isBeforeLegalizeOps() || !Subtarget.hasExtractInsert()) 836 return SDValue(); 837 838 SDValue And0 = N->getOperand(0), And1 = N->getOperand(1); 839 uint64_t SMPos0, SMSize0, SMPos1, SMSize1; 840 ConstantSDNode *CN, *CN1; 841 842 // See if Op's first operand matches (and $src1 , mask0). 843 if (And0.getOpcode() != ISD::AND) 844 return SDValue(); 845 846 if (!(CN = dyn_cast<ConstantSDNode>(And0.getOperand(1))) || 847 !isShiftedMask(~CN->getSExtValue(), SMPos0, SMSize0)) 848 return SDValue(); 849 850 // See if Op's second operand matches (and (shl $src, pos), mask1). 851 if (And1.getOpcode() == ISD::AND && 852 And1.getOperand(0).getOpcode() == ISD::SHL) { 853 854 if (!(CN = dyn_cast<ConstantSDNode>(And1.getOperand(1))) || 855 !isShiftedMask(CN->getZExtValue(), SMPos1, SMSize1)) 856 return SDValue(); 857 858 // The shift masks must have the same position and size. 859 if (SMPos0 != SMPos1 || SMSize0 != SMSize1) 860 return SDValue(); 861 862 SDValue Shl = And1.getOperand(0); 863 864 if (!(CN = dyn_cast<ConstantSDNode>(Shl.getOperand(1)))) 865 return SDValue(); 866 867 unsigned Shamt = CN->getZExtValue(); 868 869 // Return if the shift amount and the first bit position of mask are not the 870 // same. 871 EVT ValTy = N->getValueType(0); 872 if ((Shamt != SMPos0) || (SMPos0 + SMSize0 > ValTy.getSizeInBits())) 873 return SDValue(); 874 875 SDLoc DL(N); 876 return DAG.getNode(MipsISD::Ins, DL, ValTy, Shl.getOperand(0), 877 DAG.getConstant(SMPos0, DL, MVT::i32), 878 DAG.getConstant(SMSize0, DL, MVT::i32), 879 And0.getOperand(0)); 880 } else { 881 // Pattern match DINS. 882 // $dst = or (and $src, mask0), mask1 883 // where mask0 = ((1 << SMSize0) -1) << SMPos0 884 // => dins $dst, $src, pos, size 885 if (~CN->getSExtValue() == ((((int64_t)1 << SMSize0) - 1) << SMPos0) && 886 ((SMSize0 + SMPos0 <= 64 && Subtarget.hasMips64r2()) || 887 (SMSize0 + SMPos0 <= 32))) { 888 // Check if AND instruction has constant as argument 889 bool isConstCase = And1.getOpcode() != ISD::AND; 890 if (And1.getOpcode() == ISD::AND) { 891 if (!(CN1 = dyn_cast<ConstantSDNode>(And1->getOperand(1)))) 892 return SDValue(); 893 } else { 894 if (!(CN1 = dyn_cast<ConstantSDNode>(N->getOperand(1)))) 895 return SDValue(); 896 } 897 // Don't generate INS if constant OR operand doesn't fit into bits 898 // cleared by constant AND operand. 899 if (CN->getSExtValue() & CN1->getSExtValue()) 900 return SDValue(); 901 902 SDLoc DL(N); 903 EVT ValTy = N->getOperand(0)->getValueType(0); 904 SDValue Const1; 905 SDValue SrlX; 906 if (!isConstCase) { 907 Const1 = DAG.getConstant(SMPos0, DL, MVT::i32); 908 SrlX = DAG.getNode(ISD::SRL, DL, And1->getValueType(0), And1, Const1); 909 } 910 return DAG.getNode( 911 MipsISD::Ins, DL, N->getValueType(0), 912 isConstCase 913 ? DAG.getConstant(CN1->getSExtValue() >> SMPos0, DL, ValTy) 914 : SrlX, 915 DAG.getConstant(SMPos0, DL, MVT::i32), 916 DAG.getConstant(ValTy.getSizeInBits() / 8 < 8 ? SMSize0 & 31 917 : SMSize0, 918 DL, MVT::i32), 919 And0->getOperand(0)); 920 921 } 922 return SDValue(); 923 } 924 } 925 926 static SDValue performADDCombine(SDNode *N, SelectionDAG &DAG, 927 TargetLowering::DAGCombinerInfo &DCI, 928 const MipsSubtarget &Subtarget) { 929 // (add v0, (add v1, abs_lo(tjt))) => (add (add v0, v1), abs_lo(tjt)) 930 931 if (DCI.isBeforeLegalizeOps()) 932 return SDValue(); 933 934 SDValue Add = N->getOperand(1); 935 936 if (Add.getOpcode() != ISD::ADD) 937 return SDValue(); 938 939 SDValue Lo = Add.getOperand(1); 940 941 if ((Lo.getOpcode() != MipsISD::Lo) || 942 (Lo.getOperand(0).getOpcode() != ISD::TargetJumpTable)) 943 return SDValue(); 944 945 EVT ValTy = N->getValueType(0); 946 SDLoc DL(N); 947 948 SDValue Add1 = DAG.getNode(ISD::ADD, DL, ValTy, N->getOperand(0), 949 Add.getOperand(0)); 950 return DAG.getNode(ISD::ADD, DL, ValTy, Add1, Lo); 951 } 952 953 static SDValue performAssertZextCombine(SDNode *N, SelectionDAG &DAG, 954 TargetLowering::DAGCombinerInfo &DCI, 955 const MipsSubtarget &Subtarget) { 956 SDValue N0 = N->getOperand(0); 957 EVT NarrowerVT = cast<VTSDNode>(N->getOperand(1))->getVT(); 958 959 if (N0.getOpcode() != ISD::TRUNCATE) 960 return SDValue(); 961 962 if (N0.getOperand(0).getOpcode() != ISD::AssertZext) 963 return SDValue(); 964 965 // fold (AssertZext (trunc (AssertZext x))) -> (trunc (AssertZext x)) 966 // if the type of the extension of the innermost AssertZext node is 967 // smaller from that of the outermost node, eg: 968 // (AssertZext:i32 (trunc:i32 (AssertZext:i64 X, i32)), i8) 969 // -> (trunc:i32 (AssertZext X, i8)) 970 SDValue WiderAssertZext = N0.getOperand(0); 971 EVT WiderVT = cast<VTSDNode>(WiderAssertZext->getOperand(1))->getVT(); 972 973 if (NarrowerVT.bitsLT(WiderVT)) { 974 SDValue NewAssertZext = DAG.getNode( 975 ISD::AssertZext, SDLoc(N), WiderAssertZext.getValueType(), 976 WiderAssertZext.getOperand(0), DAG.getValueType(NarrowerVT)); 977 return DAG.getNode(ISD::TRUNCATE, SDLoc(N), N->getValueType(0), 978 NewAssertZext); 979 } 980 981 return SDValue(); 982 } 983 984 985 static SDValue performSHLCombine(SDNode *N, SelectionDAG &DAG, 986 TargetLowering::DAGCombinerInfo &DCI, 987 const MipsSubtarget &Subtarget) { 988 // Pattern match CINS. 989 // $dst = shl (and $src , imm), pos 990 // => cins $dst, $src, pos, size 991 992 if (DCI.isBeforeLegalizeOps() || !Subtarget.hasCnMips()) 993 return SDValue(); 994 995 SDValue FirstOperand = N->getOperand(0); 996 unsigned FirstOperandOpc = FirstOperand.getOpcode(); 997 SDValue SecondOperand = N->getOperand(1); 998 EVT ValTy = N->getValueType(0); 999 SDLoc DL(N); 1000 1001 uint64_t Pos = 0, SMPos, SMSize; 1002 ConstantSDNode *CN; 1003 SDValue NewOperand; 1004 1005 // The second operand of the shift must be an immediate. 1006 if (!(CN = dyn_cast<ConstantSDNode>(SecondOperand))) 1007 return SDValue(); 1008 1009 Pos = CN->getZExtValue(); 1010 1011 if (Pos >= ValTy.getSizeInBits()) 1012 return SDValue(); 1013 1014 if (FirstOperandOpc != ISD::AND) 1015 return SDValue(); 1016 1017 // AND's second operand must be a shifted mask. 1018 if (!(CN = dyn_cast<ConstantSDNode>(FirstOperand.getOperand(1))) || 1019 !isShiftedMask(CN->getZExtValue(), SMPos, SMSize)) 1020 return SDValue(); 1021 1022 // Return if the shifted mask does not start at bit 0 or the sum of its size 1023 // and Pos exceeds the word's size. 1024 if (SMPos != 0 || SMSize > 32 || Pos + SMSize > ValTy.getSizeInBits()) 1025 return SDValue(); 1026 1027 NewOperand = FirstOperand.getOperand(0); 1028 // SMSize is 'location' (position) in this case, not size. 1029 SMSize--; 1030 1031 return DAG.getNode(MipsISD::CIns, DL, ValTy, NewOperand, 1032 DAG.getConstant(Pos, DL, MVT::i32), 1033 DAG.getConstant(SMSize, DL, MVT::i32)); 1034 } 1035 1036 SDValue MipsTargetLowering::PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) 1037 const { 1038 SelectionDAG &DAG = DCI.DAG; 1039 unsigned Opc = N->getOpcode(); 1040 1041 switch (Opc) { 1042 default: break; 1043 case ISD::SDIVREM: 1044 case ISD::UDIVREM: 1045 return performDivRemCombine(N, DAG, DCI, Subtarget); 1046 case ISD::SELECT: 1047 return performSELECTCombine(N, DAG, DCI, Subtarget); 1048 case MipsISD::CMovFP_F: 1049 case MipsISD::CMovFP_T: 1050 return performCMovFPCombine(N, DAG, DCI, Subtarget); 1051 case ISD::AND: 1052 return performANDCombine(N, DAG, DCI, Subtarget); 1053 case ISD::OR: 1054 return performORCombine(N, DAG, DCI, Subtarget); 1055 case ISD::ADD: 1056 return performADDCombine(N, DAG, DCI, Subtarget); 1057 case ISD::AssertZext: 1058 return performAssertZextCombine(N, DAG, DCI, Subtarget); 1059 case ISD::SHL: 1060 return performSHLCombine(N, DAG, DCI, Subtarget); 1061 } 1062 1063 return SDValue(); 1064 } 1065 1066 bool MipsTargetLowering::isCheapToSpeculateCttz() const { 1067 return Subtarget.hasMips32(); 1068 } 1069 1070 bool MipsTargetLowering::isCheapToSpeculateCtlz() const { 1071 return Subtarget.hasMips32(); 1072 } 1073 1074 void 1075 MipsTargetLowering::LowerOperationWrapper(SDNode *N, 1076 SmallVectorImpl<SDValue> &Results, 1077 SelectionDAG &DAG) const { 1078 SDValue Res = LowerOperation(SDValue(N, 0), DAG); 1079 1080 for (unsigned I = 0, E = Res->getNumValues(); I != E; ++I) 1081 Results.push_back(Res.getValue(I)); 1082 } 1083 1084 void 1085 MipsTargetLowering::ReplaceNodeResults(SDNode *N, 1086 SmallVectorImpl<SDValue> &Results, 1087 SelectionDAG &DAG) const { 1088 return LowerOperationWrapper(N, Results, DAG); 1089 } 1090 1091 SDValue MipsTargetLowering:: 1092 LowerOperation(SDValue Op, SelectionDAG &DAG) const 1093 { 1094 switch (Op.getOpcode()) 1095 { 1096 case ISD::BRCOND: return lowerBRCOND(Op, DAG); 1097 case ISD::ConstantPool: return lowerConstantPool(Op, DAG); 1098 case ISD::GlobalAddress: return lowerGlobalAddress(Op, DAG); 1099 case ISD::BlockAddress: return lowerBlockAddress(Op, DAG); 1100 case ISD::GlobalTLSAddress: return lowerGlobalTLSAddress(Op, DAG); 1101 case ISD::JumpTable: return lowerJumpTable(Op, DAG); 1102 case ISD::SELECT: return lowerSELECT(Op, DAG); 1103 case ISD::SETCC: return lowerSETCC(Op, DAG); 1104 case ISD::VASTART: return lowerVASTART(Op, DAG); 1105 case ISD::VAARG: return lowerVAARG(Op, DAG); 1106 case ISD::FCOPYSIGN: return lowerFCOPYSIGN(Op, DAG); 1107 case ISD::FRAMEADDR: return lowerFRAMEADDR(Op, DAG); 1108 case ISD::RETURNADDR: return lowerRETURNADDR(Op, DAG); 1109 case ISD::EH_RETURN: return lowerEH_RETURN(Op, DAG); 1110 case ISD::ATOMIC_FENCE: return lowerATOMIC_FENCE(Op, DAG); 1111 case ISD::SHL_PARTS: return lowerShiftLeftParts(Op, DAG); 1112 case ISD::SRA_PARTS: return lowerShiftRightParts(Op, DAG, true); 1113 case ISD::SRL_PARTS: return lowerShiftRightParts(Op, DAG, false); 1114 case ISD::LOAD: return lowerLOAD(Op, DAG); 1115 case ISD::STORE: return lowerSTORE(Op, DAG); 1116 case ISD::EH_DWARF_CFA: return lowerEH_DWARF_CFA(Op, DAG); 1117 case ISD::FP_TO_SINT: return lowerFP_TO_SINT(Op, DAG); 1118 } 1119 return SDValue(); 1120 } 1121 1122 //===----------------------------------------------------------------------===// 1123 // Lower helper functions 1124 //===----------------------------------------------------------------------===// 1125 1126 // addLiveIn - This helper function adds the specified physical register to the 1127 // MachineFunction as a live in value. It also creates a corresponding 1128 // virtual register for it. 1129 static unsigned 1130 addLiveIn(MachineFunction &MF, unsigned PReg, const TargetRegisterClass *RC) 1131 { 1132 unsigned VReg = MF.getRegInfo().createVirtualRegister(RC); 1133 MF.getRegInfo().addLiveIn(PReg, VReg); 1134 return VReg; 1135 } 1136 1137 static MachineBasicBlock *insertDivByZeroTrap(MachineInstr &MI, 1138 MachineBasicBlock &MBB, 1139 const TargetInstrInfo &TII, 1140 bool Is64Bit, bool IsMicroMips) { 1141 if (NoZeroDivCheck) 1142 return &MBB; 1143 1144 // Insert instruction "teq $divisor_reg, $zero, 7". 1145 MachineBasicBlock::iterator I(MI); 1146 MachineInstrBuilder MIB; 1147 MachineOperand &Divisor = MI.getOperand(2); 1148 MIB = BuildMI(MBB, std::next(I), MI.getDebugLoc(), 1149 TII.get(IsMicroMips ? Mips::TEQ_MM : Mips::TEQ)) 1150 .addReg(Divisor.getReg(), getKillRegState(Divisor.isKill())) 1151 .addReg(Mips::ZERO) 1152 .addImm(7); 1153 1154 // Use the 32-bit sub-register if this is a 64-bit division. 1155 if (Is64Bit) 1156 MIB->getOperand(0).setSubReg(Mips::sub_32); 1157 1158 // Clear Divisor's kill flag. 1159 Divisor.setIsKill(false); 1160 1161 // We would normally delete the original instruction here but in this case 1162 // we only needed to inject an additional instruction rather than replace it. 1163 1164 return &MBB; 1165 } 1166 1167 MachineBasicBlock * 1168 MipsTargetLowering::EmitInstrWithCustomInserter(MachineInstr &MI, 1169 MachineBasicBlock *BB) const { 1170 switch (MI.getOpcode()) { 1171 default: 1172 llvm_unreachable("Unexpected instr type to insert"); 1173 case Mips::ATOMIC_LOAD_ADD_I8: 1174 return emitAtomicBinaryPartword(MI, BB, 1, Mips::ADDu); 1175 case Mips::ATOMIC_LOAD_ADD_I16: 1176 return emitAtomicBinaryPartword(MI, BB, 2, Mips::ADDu); 1177 case Mips::ATOMIC_LOAD_ADD_I32: 1178 return emitAtomicBinary(MI, BB, 4, Mips::ADDu); 1179 case Mips::ATOMIC_LOAD_ADD_I64: 1180 return emitAtomicBinary(MI, BB, 8, Mips::DADDu); 1181 1182 case Mips::ATOMIC_LOAD_AND_I8: 1183 return emitAtomicBinaryPartword(MI, BB, 1, Mips::AND); 1184 case Mips::ATOMIC_LOAD_AND_I16: 1185 return emitAtomicBinaryPartword(MI, BB, 2, Mips::AND); 1186 case Mips::ATOMIC_LOAD_AND_I32: 1187 return emitAtomicBinary(MI, BB, 4, Mips::AND); 1188 case Mips::ATOMIC_LOAD_AND_I64: 1189 return emitAtomicBinary(MI, BB, 8, Mips::AND64); 1190 1191 case Mips::ATOMIC_LOAD_OR_I8: 1192 return emitAtomicBinaryPartword(MI, BB, 1, Mips::OR); 1193 case Mips::ATOMIC_LOAD_OR_I16: 1194 return emitAtomicBinaryPartword(MI, BB, 2, Mips::OR); 1195 case Mips::ATOMIC_LOAD_OR_I32: 1196 return emitAtomicBinary(MI, BB, 4, Mips::OR); 1197 case Mips::ATOMIC_LOAD_OR_I64: 1198 return emitAtomicBinary(MI, BB, 8, Mips::OR64); 1199 1200 case Mips::ATOMIC_LOAD_XOR_I8: 1201 return emitAtomicBinaryPartword(MI, BB, 1, Mips::XOR); 1202 case Mips::ATOMIC_LOAD_XOR_I16: 1203 return emitAtomicBinaryPartword(MI, BB, 2, Mips::XOR); 1204 case Mips::ATOMIC_LOAD_XOR_I32: 1205 return emitAtomicBinary(MI, BB, 4, Mips::XOR); 1206 case Mips::ATOMIC_LOAD_XOR_I64: 1207 return emitAtomicBinary(MI, BB, 8, Mips::XOR64); 1208 1209 case Mips::ATOMIC_LOAD_NAND_I8: 1210 return emitAtomicBinaryPartword(MI, BB, 1, 0, true); 1211 case Mips::ATOMIC_LOAD_NAND_I16: 1212 return emitAtomicBinaryPartword(MI, BB, 2, 0, true); 1213 case Mips::ATOMIC_LOAD_NAND_I32: 1214 return emitAtomicBinary(MI, BB, 4, 0, true); 1215 case Mips::ATOMIC_LOAD_NAND_I64: 1216 return emitAtomicBinary(MI, BB, 8, 0, true); 1217 1218 case Mips::ATOMIC_LOAD_SUB_I8: 1219 return emitAtomicBinaryPartword(MI, BB, 1, Mips::SUBu); 1220 case Mips::ATOMIC_LOAD_SUB_I16: 1221 return emitAtomicBinaryPartword(MI, BB, 2, Mips::SUBu); 1222 case Mips::ATOMIC_LOAD_SUB_I32: 1223 return emitAtomicBinary(MI, BB, 4, Mips::SUBu); 1224 case Mips::ATOMIC_LOAD_SUB_I64: 1225 return emitAtomicBinary(MI, BB, 8, Mips::DSUBu); 1226 1227 case Mips::ATOMIC_SWAP_I8: 1228 return emitAtomicBinaryPartword(MI, BB, 1, 0); 1229 case Mips::ATOMIC_SWAP_I16: 1230 return emitAtomicBinaryPartword(MI, BB, 2, 0); 1231 case Mips::ATOMIC_SWAP_I32: 1232 return emitAtomicBinary(MI, BB, 4, 0); 1233 case Mips::ATOMIC_SWAP_I64: 1234 return emitAtomicBinary(MI, BB, 8, 0); 1235 1236 case Mips::ATOMIC_CMP_SWAP_I8: 1237 return emitAtomicCmpSwapPartword(MI, BB, 1); 1238 case Mips::ATOMIC_CMP_SWAP_I16: 1239 return emitAtomicCmpSwapPartword(MI, BB, 2); 1240 case Mips::ATOMIC_CMP_SWAP_I32: 1241 return emitAtomicCmpSwap(MI, BB, 4); 1242 case Mips::ATOMIC_CMP_SWAP_I64: 1243 return emitAtomicCmpSwap(MI, BB, 8); 1244 case Mips::PseudoSDIV: 1245 case Mips::PseudoUDIV: 1246 case Mips::DIV: 1247 case Mips::DIVU: 1248 case Mips::MOD: 1249 case Mips::MODU: 1250 return insertDivByZeroTrap(MI, *BB, *Subtarget.getInstrInfo(), false, 1251 false); 1252 case Mips::SDIV_MM_Pseudo: 1253 case Mips::UDIV_MM_Pseudo: 1254 case Mips::SDIV_MM: 1255 case Mips::UDIV_MM: 1256 case Mips::DIV_MMR6: 1257 case Mips::DIVU_MMR6: 1258 case Mips::MOD_MMR6: 1259 case Mips::MODU_MMR6: 1260 return insertDivByZeroTrap(MI, *BB, *Subtarget.getInstrInfo(), false, true); 1261 case Mips::PseudoDSDIV: 1262 case Mips::PseudoDUDIV: 1263 case Mips::DDIV: 1264 case Mips::DDIVU: 1265 case Mips::DMOD: 1266 case Mips::DMODU: 1267 return insertDivByZeroTrap(MI, *BB, *Subtarget.getInstrInfo(), true, false); 1268 case Mips::DDIV_MM64R6: 1269 case Mips::DDIVU_MM64R6: 1270 case Mips::DMOD_MM64R6: 1271 case Mips::DMODU_MM64R6: 1272 return insertDivByZeroTrap(MI, *BB, *Subtarget.getInstrInfo(), true, true); 1273 case Mips::SEL_D: 1274 case Mips::SEL_D_MMR6: 1275 return emitSEL_D(MI, BB); 1276 1277 case Mips::PseudoSELECT_I: 1278 case Mips::PseudoSELECT_I64: 1279 case Mips::PseudoSELECT_S: 1280 case Mips::PseudoSELECT_D32: 1281 case Mips::PseudoSELECT_D64: 1282 return emitPseudoSELECT(MI, BB, false, Mips::BNE); 1283 case Mips::PseudoSELECTFP_F_I: 1284 case Mips::PseudoSELECTFP_F_I64: 1285 case Mips::PseudoSELECTFP_F_S: 1286 case Mips::PseudoSELECTFP_F_D32: 1287 case Mips::PseudoSELECTFP_F_D64: 1288 return emitPseudoSELECT(MI, BB, true, Mips::BC1F); 1289 case Mips::PseudoSELECTFP_T_I: 1290 case Mips::PseudoSELECTFP_T_I64: 1291 case Mips::PseudoSELECTFP_T_S: 1292 case Mips::PseudoSELECTFP_T_D32: 1293 case Mips::PseudoSELECTFP_T_D64: 1294 return emitPseudoSELECT(MI, BB, true, Mips::BC1T); 1295 } 1296 } 1297 1298 // This function also handles Mips::ATOMIC_SWAP_I32 (when BinOpcode == 0), and 1299 // Mips::ATOMIC_LOAD_NAND_I32 (when Nand == true) 1300 MachineBasicBlock *MipsTargetLowering::emitAtomicBinary(MachineInstr &MI, 1301 MachineBasicBlock *BB, 1302 unsigned Size, 1303 unsigned BinOpcode, 1304 bool Nand) const { 1305 assert((Size == 4 || Size == 8) && "Unsupported size for EmitAtomicBinary."); 1306 1307 MachineFunction *MF = BB->getParent(); 1308 MachineRegisterInfo &RegInfo = MF->getRegInfo(); 1309 const TargetRegisterClass *RC = getRegClassFor(MVT::getIntegerVT(Size * 8)); 1310 const TargetInstrInfo *TII = Subtarget.getInstrInfo(); 1311 const bool ArePtrs64bit = ABI.ArePtrs64bit(); 1312 DebugLoc DL = MI.getDebugLoc(); 1313 unsigned LL, SC, AND, NOR, ZERO, BEQ; 1314 1315 if (Size == 4) { 1316 if (isMicroMips) { 1317 LL = Mips::LL_MM; 1318 SC = Mips::SC_MM; 1319 } else { 1320 LL = Subtarget.hasMips32r6() 1321 ? (ArePtrs64bit ? Mips::LL64_R6 : Mips::LL_R6) 1322 : (ArePtrs64bit ? Mips::LL64 : Mips::LL); 1323 SC = Subtarget.hasMips32r6() 1324 ? (ArePtrs64bit ? Mips::SC64_R6 : Mips::SC_R6) 1325 : (ArePtrs64bit ? Mips::SC64 : Mips::SC); 1326 } 1327 1328 AND = Mips::AND; 1329 NOR = Mips::NOR; 1330 ZERO = Mips::ZERO; 1331 BEQ = Mips::BEQ; 1332 } else { 1333 LL = Subtarget.hasMips64r6() ? Mips::LLD_R6 : Mips::LLD; 1334 SC = Subtarget.hasMips64r6() ? Mips::SCD_R6 : Mips::SCD; 1335 AND = Mips::AND64; 1336 NOR = Mips::NOR64; 1337 ZERO = Mips::ZERO_64; 1338 BEQ = Mips::BEQ64; 1339 } 1340 1341 unsigned OldVal = MI.getOperand(0).getReg(); 1342 unsigned Ptr = MI.getOperand(1).getReg(); 1343 unsigned Incr = MI.getOperand(2).getReg(); 1344 1345 unsigned StoreVal = RegInfo.createVirtualRegister(RC); 1346 unsigned AndRes = RegInfo.createVirtualRegister(RC); 1347 unsigned Success = RegInfo.createVirtualRegister(RC); 1348 1349 // insert new blocks after the current block 1350 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 1351 MachineBasicBlock *loopMBB = MF->CreateMachineBasicBlock(LLVM_BB); 1352 MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB); 1353 MachineFunction::iterator It = ++BB->getIterator(); 1354 MF->insert(It, loopMBB); 1355 MF->insert(It, exitMBB); 1356 1357 // Transfer the remainder of BB and its successor edges to exitMBB. 1358 exitMBB->splice(exitMBB->begin(), BB, 1359 std::next(MachineBasicBlock::iterator(MI)), BB->end()); 1360 exitMBB->transferSuccessorsAndUpdatePHIs(BB); 1361 1362 // thisMBB: 1363 // ... 1364 // fallthrough --> loopMBB 1365 BB->addSuccessor(loopMBB); 1366 loopMBB->addSuccessor(loopMBB); 1367 loopMBB->addSuccessor(exitMBB); 1368 1369 // loopMBB: 1370 // ll oldval, 0(ptr) 1371 // <binop> storeval, oldval, incr 1372 // sc success, storeval, 0(ptr) 1373 // beq success, $0, loopMBB 1374 BB = loopMBB; 1375 BuildMI(BB, DL, TII->get(LL), OldVal).addReg(Ptr).addImm(0); 1376 if (Nand) { 1377 // and andres, oldval, incr 1378 // nor storeval, $0, andres 1379 BuildMI(BB, DL, TII->get(AND), AndRes).addReg(OldVal).addReg(Incr); 1380 BuildMI(BB, DL, TII->get(NOR), StoreVal).addReg(ZERO).addReg(AndRes); 1381 } else if (BinOpcode) { 1382 // <binop> storeval, oldval, incr 1383 BuildMI(BB, DL, TII->get(BinOpcode), StoreVal).addReg(OldVal).addReg(Incr); 1384 } else { 1385 StoreVal = Incr; 1386 } 1387 BuildMI(BB, DL, TII->get(SC), Success).addReg(StoreVal).addReg(Ptr).addImm(0); 1388 BuildMI(BB, DL, TII->get(BEQ)).addReg(Success).addReg(ZERO).addMBB(loopMBB); 1389 1390 MI.eraseFromParent(); // The instruction is gone now. 1391 1392 return exitMBB; 1393 } 1394 1395 MachineBasicBlock *MipsTargetLowering::emitSignExtendToI32InReg( 1396 MachineInstr &MI, MachineBasicBlock *BB, unsigned Size, unsigned DstReg, 1397 unsigned SrcReg) const { 1398 const TargetInstrInfo *TII = Subtarget.getInstrInfo(); 1399 const DebugLoc &DL = MI.getDebugLoc(); 1400 1401 if (Subtarget.hasMips32r2() && Size == 1) { 1402 BuildMI(BB, DL, TII->get(Mips::SEB), DstReg).addReg(SrcReg); 1403 return BB; 1404 } 1405 1406 if (Subtarget.hasMips32r2() && Size == 2) { 1407 BuildMI(BB, DL, TII->get(Mips::SEH), DstReg).addReg(SrcReg); 1408 return BB; 1409 } 1410 1411 MachineFunction *MF = BB->getParent(); 1412 MachineRegisterInfo &RegInfo = MF->getRegInfo(); 1413 const TargetRegisterClass *RC = getRegClassFor(MVT::i32); 1414 unsigned ScrReg = RegInfo.createVirtualRegister(RC); 1415 1416 assert(Size < 32); 1417 int64_t ShiftImm = 32 - (Size * 8); 1418 1419 BuildMI(BB, DL, TII->get(Mips::SLL), ScrReg).addReg(SrcReg).addImm(ShiftImm); 1420 BuildMI(BB, DL, TII->get(Mips::SRA), DstReg).addReg(ScrReg).addImm(ShiftImm); 1421 1422 return BB; 1423 } 1424 1425 MachineBasicBlock *MipsTargetLowering::emitAtomicBinaryPartword( 1426 MachineInstr &MI, MachineBasicBlock *BB, unsigned Size, unsigned BinOpcode, 1427 bool Nand) const { 1428 assert((Size == 1 || Size == 2) && 1429 "Unsupported size for EmitAtomicBinaryPartial."); 1430 1431 MachineFunction *MF = BB->getParent(); 1432 MachineRegisterInfo &RegInfo = MF->getRegInfo(); 1433 const TargetRegisterClass *RC = getRegClassFor(MVT::i32); 1434 const bool ArePtrs64bit = ABI.ArePtrs64bit(); 1435 const TargetRegisterClass *RCp = 1436 getRegClassFor(ArePtrs64bit ? MVT::i64 : MVT::i32); 1437 const TargetInstrInfo *TII = Subtarget.getInstrInfo(); 1438 DebugLoc DL = MI.getDebugLoc(); 1439 1440 unsigned Dest = MI.getOperand(0).getReg(); 1441 unsigned Ptr = MI.getOperand(1).getReg(); 1442 unsigned Incr = MI.getOperand(2).getReg(); 1443 1444 unsigned AlignedAddr = RegInfo.createVirtualRegister(RCp); 1445 unsigned ShiftAmt = RegInfo.createVirtualRegister(RC); 1446 unsigned Mask = RegInfo.createVirtualRegister(RC); 1447 unsigned Mask2 = RegInfo.createVirtualRegister(RC); 1448 unsigned NewVal = RegInfo.createVirtualRegister(RC); 1449 unsigned OldVal = RegInfo.createVirtualRegister(RC); 1450 unsigned Incr2 = RegInfo.createVirtualRegister(RC); 1451 unsigned MaskLSB2 = RegInfo.createVirtualRegister(RCp); 1452 unsigned PtrLSB2 = RegInfo.createVirtualRegister(RC); 1453 unsigned MaskUpper = RegInfo.createVirtualRegister(RC); 1454 unsigned AndRes = RegInfo.createVirtualRegister(RC); 1455 unsigned BinOpRes = RegInfo.createVirtualRegister(RC); 1456 unsigned MaskedOldVal0 = RegInfo.createVirtualRegister(RC); 1457 unsigned StoreVal = RegInfo.createVirtualRegister(RC); 1458 unsigned MaskedOldVal1 = RegInfo.createVirtualRegister(RC); 1459 unsigned SrlRes = RegInfo.createVirtualRegister(RC); 1460 unsigned Success = RegInfo.createVirtualRegister(RC); 1461 1462 unsigned LL, SC; 1463 if (isMicroMips) { 1464 LL = Mips::LL_MM; 1465 SC = Mips::SC_MM; 1466 } else { 1467 LL = Subtarget.hasMips32r6() ? (ArePtrs64bit ? Mips::LL64_R6 : Mips::LL_R6) 1468 : (ArePtrs64bit ? Mips::LL64 : Mips::LL); 1469 SC = Subtarget.hasMips32r6() ? (ArePtrs64bit ? Mips::SC64_R6 : Mips::SC_R6) 1470 : (ArePtrs64bit ? Mips::SC64 : Mips::SC); 1471 } 1472 1473 // insert new blocks after the current block 1474 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 1475 MachineBasicBlock *loopMBB = MF->CreateMachineBasicBlock(LLVM_BB); 1476 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(LLVM_BB); 1477 MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB); 1478 MachineFunction::iterator It = ++BB->getIterator(); 1479 MF->insert(It, loopMBB); 1480 MF->insert(It, sinkMBB); 1481 MF->insert(It, exitMBB); 1482 1483 // Transfer the remainder of BB and its successor edges to exitMBB. 1484 exitMBB->splice(exitMBB->begin(), BB, 1485 std::next(MachineBasicBlock::iterator(MI)), BB->end()); 1486 exitMBB->transferSuccessorsAndUpdatePHIs(BB); 1487 1488 BB->addSuccessor(loopMBB); 1489 loopMBB->addSuccessor(loopMBB); 1490 loopMBB->addSuccessor(sinkMBB); 1491 sinkMBB->addSuccessor(exitMBB); 1492 1493 // thisMBB: 1494 // addiu masklsb2,$0,-4 # 0xfffffffc 1495 // and alignedaddr,ptr,masklsb2 1496 // andi ptrlsb2,ptr,3 1497 // sll shiftamt,ptrlsb2,3 1498 // ori maskupper,$0,255 # 0xff 1499 // sll mask,maskupper,shiftamt 1500 // nor mask2,$0,mask 1501 // sll incr2,incr,shiftamt 1502 1503 int64_t MaskImm = (Size == 1) ? 255 : 65535; 1504 BuildMI(BB, DL, TII->get(ABI.GetPtrAddiuOp()), MaskLSB2) 1505 .addReg(ABI.GetNullPtr()).addImm(-4); 1506 BuildMI(BB, DL, TII->get(ABI.GetPtrAndOp()), AlignedAddr) 1507 .addReg(Ptr).addReg(MaskLSB2); 1508 BuildMI(BB, DL, TII->get(Mips::ANDi), PtrLSB2) 1509 .addReg(Ptr, 0, ArePtrs64bit ? Mips::sub_32 : 0).addImm(3); 1510 if (Subtarget.isLittle()) { 1511 BuildMI(BB, DL, TII->get(Mips::SLL), ShiftAmt).addReg(PtrLSB2).addImm(3); 1512 } else { 1513 unsigned Off = RegInfo.createVirtualRegister(RC); 1514 BuildMI(BB, DL, TII->get(Mips::XORi), Off) 1515 .addReg(PtrLSB2).addImm((Size == 1) ? 3 : 2); 1516 BuildMI(BB, DL, TII->get(Mips::SLL), ShiftAmt).addReg(Off).addImm(3); 1517 } 1518 BuildMI(BB, DL, TII->get(Mips::ORi), MaskUpper) 1519 .addReg(Mips::ZERO).addImm(MaskImm); 1520 BuildMI(BB, DL, TII->get(Mips::SLLV), Mask) 1521 .addReg(MaskUpper).addReg(ShiftAmt); 1522 BuildMI(BB, DL, TII->get(Mips::NOR), Mask2).addReg(Mips::ZERO).addReg(Mask); 1523 BuildMI(BB, DL, TII->get(Mips::SLLV), Incr2).addReg(Incr).addReg(ShiftAmt); 1524 1525 // atomic.load.binop 1526 // loopMBB: 1527 // ll oldval,0(alignedaddr) 1528 // binop binopres,oldval,incr2 1529 // and newval,binopres,mask 1530 // and maskedoldval0,oldval,mask2 1531 // or storeval,maskedoldval0,newval 1532 // sc success,storeval,0(alignedaddr) 1533 // beq success,$0,loopMBB 1534 1535 // atomic.swap 1536 // loopMBB: 1537 // ll oldval,0(alignedaddr) 1538 // and newval,incr2,mask 1539 // and maskedoldval0,oldval,mask2 1540 // or storeval,maskedoldval0,newval 1541 // sc success,storeval,0(alignedaddr) 1542 // beq success,$0,loopMBB 1543 1544 BB = loopMBB; 1545 BuildMI(BB, DL, TII->get(LL), OldVal).addReg(AlignedAddr).addImm(0); 1546 if (Nand) { 1547 // and andres, oldval, incr2 1548 // nor binopres, $0, andres 1549 // and newval, binopres, mask 1550 BuildMI(BB, DL, TII->get(Mips::AND), AndRes).addReg(OldVal).addReg(Incr2); 1551 BuildMI(BB, DL, TII->get(Mips::NOR), BinOpRes) 1552 .addReg(Mips::ZERO).addReg(AndRes); 1553 BuildMI(BB, DL, TII->get(Mips::AND), NewVal).addReg(BinOpRes).addReg(Mask); 1554 } else if (BinOpcode) { 1555 // <binop> binopres, oldval, incr2 1556 // and newval, binopres, mask 1557 BuildMI(BB, DL, TII->get(BinOpcode), BinOpRes).addReg(OldVal).addReg(Incr2); 1558 BuildMI(BB, DL, TII->get(Mips::AND), NewVal).addReg(BinOpRes).addReg(Mask); 1559 } else { // atomic.swap 1560 // and newval, incr2, mask 1561 BuildMI(BB, DL, TII->get(Mips::AND), NewVal).addReg(Incr2).addReg(Mask); 1562 } 1563 1564 BuildMI(BB, DL, TII->get(Mips::AND), MaskedOldVal0) 1565 .addReg(OldVal).addReg(Mask2); 1566 BuildMI(BB, DL, TII->get(Mips::OR), StoreVal) 1567 .addReg(MaskedOldVal0).addReg(NewVal); 1568 BuildMI(BB, DL, TII->get(SC), Success) 1569 .addReg(StoreVal).addReg(AlignedAddr).addImm(0); 1570 BuildMI(BB, DL, TII->get(Mips::BEQ)) 1571 .addReg(Success).addReg(Mips::ZERO).addMBB(loopMBB); 1572 1573 // sinkMBB: 1574 // and maskedoldval1,oldval,mask 1575 // srl srlres,maskedoldval1,shiftamt 1576 // sign_extend dest,srlres 1577 BB = sinkMBB; 1578 1579 BuildMI(BB, DL, TII->get(Mips::AND), MaskedOldVal1) 1580 .addReg(OldVal).addReg(Mask); 1581 BuildMI(BB, DL, TII->get(Mips::SRLV), SrlRes) 1582 .addReg(MaskedOldVal1).addReg(ShiftAmt); 1583 BB = emitSignExtendToI32InReg(MI, BB, Size, Dest, SrlRes); 1584 1585 MI.eraseFromParent(); // The instruction is gone now. 1586 1587 return exitMBB; 1588 } 1589 1590 MachineBasicBlock *MipsTargetLowering::emitAtomicCmpSwap(MachineInstr &MI, 1591 MachineBasicBlock *BB, 1592 unsigned Size) const { 1593 assert((Size == 4 || Size == 8) && "Unsupported size for EmitAtomicCmpSwap."); 1594 1595 MachineFunction *MF = BB->getParent(); 1596 MachineRegisterInfo &RegInfo = MF->getRegInfo(); 1597 const TargetRegisterClass *RC = getRegClassFor(MVT::getIntegerVT(Size * 8)); 1598 const TargetInstrInfo *TII = Subtarget.getInstrInfo(); 1599 const bool ArePtrs64bit = ABI.ArePtrs64bit(); 1600 DebugLoc DL = MI.getDebugLoc(); 1601 unsigned LL, SC, ZERO, BNE, BEQ; 1602 1603 if (Size == 4) { 1604 if (isMicroMips) { 1605 LL = Mips::LL_MM; 1606 SC = Mips::SC_MM; 1607 } else { 1608 LL = Subtarget.hasMips32r6() 1609 ? (ArePtrs64bit ? Mips::LL64_R6 : Mips::LL_R6) 1610 : (ArePtrs64bit ? Mips::LL64 : Mips::LL); 1611 SC = Subtarget.hasMips32r6() 1612 ? (ArePtrs64bit ? Mips::SC64_R6 : Mips::SC_R6) 1613 : (ArePtrs64bit ? Mips::SC64 : Mips::SC); 1614 } 1615 1616 ZERO = Mips::ZERO; 1617 BNE = Mips::BNE; 1618 BEQ = Mips::BEQ; 1619 } else { 1620 LL = Subtarget.hasMips64r6() ? Mips::LLD_R6 : Mips::LLD; 1621 SC = Subtarget.hasMips64r6() ? Mips::SCD_R6 : Mips::SCD; 1622 ZERO = Mips::ZERO_64; 1623 BNE = Mips::BNE64; 1624 BEQ = Mips::BEQ64; 1625 } 1626 1627 unsigned Dest = MI.getOperand(0).getReg(); 1628 unsigned Ptr = MI.getOperand(1).getReg(); 1629 unsigned OldVal = MI.getOperand(2).getReg(); 1630 unsigned NewVal = MI.getOperand(3).getReg(); 1631 1632 unsigned Success = RegInfo.createVirtualRegister(RC); 1633 1634 // insert new blocks after the current block 1635 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 1636 MachineBasicBlock *loop1MBB = MF->CreateMachineBasicBlock(LLVM_BB); 1637 MachineBasicBlock *loop2MBB = MF->CreateMachineBasicBlock(LLVM_BB); 1638 MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB); 1639 MachineFunction::iterator It = ++BB->getIterator(); 1640 MF->insert(It, loop1MBB); 1641 MF->insert(It, loop2MBB); 1642 MF->insert(It, exitMBB); 1643 1644 // Transfer the remainder of BB and its successor edges to exitMBB. 1645 exitMBB->splice(exitMBB->begin(), BB, 1646 std::next(MachineBasicBlock::iterator(MI)), BB->end()); 1647 exitMBB->transferSuccessorsAndUpdatePHIs(BB); 1648 1649 // thisMBB: 1650 // ... 1651 // fallthrough --> loop1MBB 1652 BB->addSuccessor(loop1MBB); 1653 loop1MBB->addSuccessor(exitMBB); 1654 loop1MBB->addSuccessor(loop2MBB); 1655 loop2MBB->addSuccessor(loop1MBB); 1656 loop2MBB->addSuccessor(exitMBB); 1657 1658 // loop1MBB: 1659 // ll dest, 0(ptr) 1660 // bne dest, oldval, exitMBB 1661 BB = loop1MBB; 1662 BuildMI(BB, DL, TII->get(LL), Dest).addReg(Ptr).addImm(0); 1663 BuildMI(BB, DL, TII->get(BNE)) 1664 .addReg(Dest).addReg(OldVal).addMBB(exitMBB); 1665 1666 // loop2MBB: 1667 // sc success, newval, 0(ptr) 1668 // beq success, $0, loop1MBB 1669 BB = loop2MBB; 1670 BuildMI(BB, DL, TII->get(SC), Success) 1671 .addReg(NewVal).addReg(Ptr).addImm(0); 1672 BuildMI(BB, DL, TII->get(BEQ)) 1673 .addReg(Success).addReg(ZERO).addMBB(loop1MBB); 1674 1675 MI.eraseFromParent(); // The instruction is gone now. 1676 1677 return exitMBB; 1678 } 1679 1680 MachineBasicBlock *MipsTargetLowering::emitAtomicCmpSwapPartword( 1681 MachineInstr &MI, MachineBasicBlock *BB, unsigned Size) const { 1682 assert((Size == 1 || Size == 2) && 1683 "Unsupported size for EmitAtomicCmpSwapPartial."); 1684 1685 MachineFunction *MF = BB->getParent(); 1686 MachineRegisterInfo &RegInfo = MF->getRegInfo(); 1687 const TargetRegisterClass *RC = getRegClassFor(MVT::i32); 1688 const bool ArePtrs64bit = ABI.ArePtrs64bit(); 1689 const TargetRegisterClass *RCp = 1690 getRegClassFor(ArePtrs64bit ? MVT::i64 : MVT::i32); 1691 const TargetInstrInfo *TII = Subtarget.getInstrInfo(); 1692 DebugLoc DL = MI.getDebugLoc(); 1693 1694 unsigned Dest = MI.getOperand(0).getReg(); 1695 unsigned Ptr = MI.getOperand(1).getReg(); 1696 unsigned CmpVal = MI.getOperand(2).getReg(); 1697 unsigned NewVal = MI.getOperand(3).getReg(); 1698 1699 unsigned AlignedAddr = RegInfo.createVirtualRegister(RCp); 1700 unsigned ShiftAmt = RegInfo.createVirtualRegister(RC); 1701 unsigned Mask = RegInfo.createVirtualRegister(RC); 1702 unsigned Mask2 = RegInfo.createVirtualRegister(RC); 1703 unsigned ShiftedCmpVal = RegInfo.createVirtualRegister(RC); 1704 unsigned OldVal = RegInfo.createVirtualRegister(RC); 1705 unsigned MaskedOldVal0 = RegInfo.createVirtualRegister(RC); 1706 unsigned ShiftedNewVal = RegInfo.createVirtualRegister(RC); 1707 unsigned MaskLSB2 = RegInfo.createVirtualRegister(RCp); 1708 unsigned PtrLSB2 = RegInfo.createVirtualRegister(RC); 1709 unsigned MaskUpper = RegInfo.createVirtualRegister(RC); 1710 unsigned MaskedCmpVal = RegInfo.createVirtualRegister(RC); 1711 unsigned MaskedNewVal = RegInfo.createVirtualRegister(RC); 1712 unsigned MaskedOldVal1 = RegInfo.createVirtualRegister(RC); 1713 unsigned StoreVal = RegInfo.createVirtualRegister(RC); 1714 unsigned SrlRes = RegInfo.createVirtualRegister(RC); 1715 unsigned Success = RegInfo.createVirtualRegister(RC); 1716 unsigned LL, SC; 1717 1718 if (isMicroMips) { 1719 LL = Mips::LL_MM; 1720 SC = Mips::SC_MM; 1721 } else { 1722 LL = Subtarget.hasMips32r6() ? (ArePtrs64bit ? Mips::LL64_R6 : Mips::LL_R6) 1723 : (ArePtrs64bit ? Mips::LL64 : Mips::LL); 1724 SC = Subtarget.hasMips32r6() ? (ArePtrs64bit ? Mips::SC64_R6 : Mips::SC_R6) 1725 : (ArePtrs64bit ? Mips::SC64 : Mips::SC); 1726 } 1727 1728 // insert new blocks after the current block 1729 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 1730 MachineBasicBlock *loop1MBB = MF->CreateMachineBasicBlock(LLVM_BB); 1731 MachineBasicBlock *loop2MBB = MF->CreateMachineBasicBlock(LLVM_BB); 1732 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(LLVM_BB); 1733 MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB); 1734 MachineFunction::iterator It = ++BB->getIterator(); 1735 MF->insert(It, loop1MBB); 1736 MF->insert(It, loop2MBB); 1737 MF->insert(It, sinkMBB); 1738 MF->insert(It, exitMBB); 1739 1740 // Transfer the remainder of BB and its successor edges to exitMBB. 1741 exitMBB->splice(exitMBB->begin(), BB, 1742 std::next(MachineBasicBlock::iterator(MI)), BB->end()); 1743 exitMBB->transferSuccessorsAndUpdatePHIs(BB); 1744 1745 BB->addSuccessor(loop1MBB); 1746 loop1MBB->addSuccessor(sinkMBB); 1747 loop1MBB->addSuccessor(loop2MBB); 1748 loop2MBB->addSuccessor(loop1MBB); 1749 loop2MBB->addSuccessor(sinkMBB); 1750 sinkMBB->addSuccessor(exitMBB); 1751 1752 // FIXME: computation of newval2 can be moved to loop2MBB. 1753 // thisMBB: 1754 // addiu masklsb2,$0,-4 # 0xfffffffc 1755 // and alignedaddr,ptr,masklsb2 1756 // andi ptrlsb2,ptr,3 1757 // xori ptrlsb2,ptrlsb2,3 # Only for BE 1758 // sll shiftamt,ptrlsb2,3 1759 // ori maskupper,$0,255 # 0xff 1760 // sll mask,maskupper,shiftamt 1761 // nor mask2,$0,mask 1762 // andi maskedcmpval,cmpval,255 1763 // sll shiftedcmpval,maskedcmpval,shiftamt 1764 // andi maskednewval,newval,255 1765 // sll shiftednewval,maskednewval,shiftamt 1766 int64_t MaskImm = (Size == 1) ? 255 : 65535; 1767 BuildMI(BB, DL, TII->get(ArePtrs64bit ? Mips::DADDiu : Mips::ADDiu), MaskLSB2) 1768 .addReg(ABI.GetNullPtr()).addImm(-4); 1769 BuildMI(BB, DL, TII->get(ArePtrs64bit ? Mips::AND64 : Mips::AND), AlignedAddr) 1770 .addReg(Ptr).addReg(MaskLSB2); 1771 BuildMI(BB, DL, TII->get(Mips::ANDi), PtrLSB2) 1772 .addReg(Ptr, 0, ArePtrs64bit ? Mips::sub_32 : 0).addImm(3); 1773 if (Subtarget.isLittle()) { 1774 BuildMI(BB, DL, TII->get(Mips::SLL), ShiftAmt).addReg(PtrLSB2).addImm(3); 1775 } else { 1776 unsigned Off = RegInfo.createVirtualRegister(RC); 1777 BuildMI(BB, DL, TII->get(Mips::XORi), Off) 1778 .addReg(PtrLSB2).addImm((Size == 1) ? 3 : 2); 1779 BuildMI(BB, DL, TII->get(Mips::SLL), ShiftAmt).addReg(Off).addImm(3); 1780 } 1781 BuildMI(BB, DL, TII->get(Mips::ORi), MaskUpper) 1782 .addReg(Mips::ZERO).addImm(MaskImm); 1783 BuildMI(BB, DL, TII->get(Mips::SLLV), Mask) 1784 .addReg(MaskUpper).addReg(ShiftAmt); 1785 BuildMI(BB, DL, TII->get(Mips::NOR), Mask2).addReg(Mips::ZERO).addReg(Mask); 1786 BuildMI(BB, DL, TII->get(Mips::ANDi), MaskedCmpVal) 1787 .addReg(CmpVal).addImm(MaskImm); 1788 BuildMI(BB, DL, TII->get(Mips::SLLV), ShiftedCmpVal) 1789 .addReg(MaskedCmpVal).addReg(ShiftAmt); 1790 BuildMI(BB, DL, TII->get(Mips::ANDi), MaskedNewVal) 1791 .addReg(NewVal).addImm(MaskImm); 1792 BuildMI(BB, DL, TII->get(Mips::SLLV), ShiftedNewVal) 1793 .addReg(MaskedNewVal).addReg(ShiftAmt); 1794 1795 // loop1MBB: 1796 // ll oldval,0(alginedaddr) 1797 // and maskedoldval0,oldval,mask 1798 // bne maskedoldval0,shiftedcmpval,sinkMBB 1799 BB = loop1MBB; 1800 BuildMI(BB, DL, TII->get(LL), OldVal).addReg(AlignedAddr).addImm(0); 1801 BuildMI(BB, DL, TII->get(Mips::AND), MaskedOldVal0) 1802 .addReg(OldVal).addReg(Mask); 1803 BuildMI(BB, DL, TII->get(Mips::BNE)) 1804 .addReg(MaskedOldVal0).addReg(ShiftedCmpVal).addMBB(sinkMBB); 1805 1806 // loop2MBB: 1807 // and maskedoldval1,oldval,mask2 1808 // or storeval,maskedoldval1,shiftednewval 1809 // sc success,storeval,0(alignedaddr) 1810 // beq success,$0,loop1MBB 1811 BB = loop2MBB; 1812 BuildMI(BB, DL, TII->get(Mips::AND), MaskedOldVal1) 1813 .addReg(OldVal).addReg(Mask2); 1814 BuildMI(BB, DL, TII->get(Mips::OR), StoreVal) 1815 .addReg(MaskedOldVal1).addReg(ShiftedNewVal); 1816 BuildMI(BB, DL, TII->get(SC), Success) 1817 .addReg(StoreVal).addReg(AlignedAddr).addImm(0); 1818 BuildMI(BB, DL, TII->get(Mips::BEQ)) 1819 .addReg(Success).addReg(Mips::ZERO).addMBB(loop1MBB); 1820 1821 // sinkMBB: 1822 // srl srlres,maskedoldval0,shiftamt 1823 // sign_extend dest,srlres 1824 BB = sinkMBB; 1825 1826 BuildMI(BB, DL, TII->get(Mips::SRLV), SrlRes) 1827 .addReg(MaskedOldVal0).addReg(ShiftAmt); 1828 BB = emitSignExtendToI32InReg(MI, BB, Size, Dest, SrlRes); 1829 1830 MI.eraseFromParent(); // The instruction is gone now. 1831 1832 return exitMBB; 1833 } 1834 1835 MachineBasicBlock *MipsTargetLowering::emitSEL_D(MachineInstr &MI, 1836 MachineBasicBlock *BB) const { 1837 MachineFunction *MF = BB->getParent(); 1838 const TargetRegisterInfo *TRI = Subtarget.getRegisterInfo(); 1839 const TargetInstrInfo *TII = Subtarget.getInstrInfo(); 1840 MachineRegisterInfo &RegInfo = MF->getRegInfo(); 1841 DebugLoc DL = MI.getDebugLoc(); 1842 MachineBasicBlock::iterator II(MI); 1843 1844 unsigned Fc = MI.getOperand(1).getReg(); 1845 const auto &FGR64RegClass = TRI->getRegClass(Mips::FGR64RegClassID); 1846 1847 unsigned Fc2 = RegInfo.createVirtualRegister(FGR64RegClass); 1848 1849 BuildMI(*BB, II, DL, TII->get(Mips::SUBREG_TO_REG), Fc2) 1850 .addImm(0) 1851 .addReg(Fc) 1852 .addImm(Mips::sub_lo); 1853 1854 // We don't erase the original instruction, we just replace the condition 1855 // register with the 64-bit super-register. 1856 MI.getOperand(1).setReg(Fc2); 1857 1858 return BB; 1859 } 1860 1861 SDValue MipsTargetLowering::lowerBRCOND(SDValue Op, SelectionDAG &DAG) const { 1862 // The first operand is the chain, the second is the condition, the third is 1863 // the block to branch to if the condition is true. 1864 SDValue Chain = Op.getOperand(0); 1865 SDValue Dest = Op.getOperand(2); 1866 SDLoc DL(Op); 1867 1868 assert(!Subtarget.hasMips32r6() && !Subtarget.hasMips64r6()); 1869 SDValue CondRes = createFPCmp(DAG, Op.getOperand(1)); 1870 1871 // Return if flag is not set by a floating point comparison. 1872 if (CondRes.getOpcode() != MipsISD::FPCmp) 1873 return Op; 1874 1875 SDValue CCNode = CondRes.getOperand(2); 1876 Mips::CondCode CC = 1877 (Mips::CondCode)cast<ConstantSDNode>(CCNode)->getZExtValue(); 1878 unsigned Opc = invertFPCondCodeUser(CC) ? Mips::BRANCH_F : Mips::BRANCH_T; 1879 SDValue BrCode = DAG.getConstant(Opc, DL, MVT::i32); 1880 SDValue FCC0 = DAG.getRegister(Mips::FCC0, MVT::i32); 1881 return DAG.getNode(MipsISD::FPBrcond, DL, Op.getValueType(), Chain, BrCode, 1882 FCC0, Dest, CondRes); 1883 } 1884 1885 SDValue MipsTargetLowering:: 1886 lowerSELECT(SDValue Op, SelectionDAG &DAG) const 1887 { 1888 assert(!Subtarget.hasMips32r6() && !Subtarget.hasMips64r6()); 1889 SDValue Cond = createFPCmp(DAG, Op.getOperand(0)); 1890 1891 // Return if flag is not set by a floating point comparison. 1892 if (Cond.getOpcode() != MipsISD::FPCmp) 1893 return Op; 1894 1895 return createCMovFP(DAG, Cond, Op.getOperand(1), Op.getOperand(2), 1896 SDLoc(Op)); 1897 } 1898 1899 SDValue MipsTargetLowering::lowerSETCC(SDValue Op, SelectionDAG &DAG) const { 1900 assert(!Subtarget.hasMips32r6() && !Subtarget.hasMips64r6()); 1901 SDValue Cond = createFPCmp(DAG, Op); 1902 1903 assert(Cond.getOpcode() == MipsISD::FPCmp && 1904 "Floating point operand expected."); 1905 1906 SDLoc DL(Op); 1907 SDValue True = DAG.getConstant(1, DL, MVT::i32); 1908 SDValue False = DAG.getConstant(0, DL, MVT::i32); 1909 1910 return createCMovFP(DAG, Cond, True, False, DL); 1911 } 1912 1913 SDValue MipsTargetLowering::lowerGlobalAddress(SDValue Op, 1914 SelectionDAG &DAG) const { 1915 EVT Ty = Op.getValueType(); 1916 GlobalAddressSDNode *N = cast<GlobalAddressSDNode>(Op); 1917 const GlobalValue *GV = N->getGlobal(); 1918 1919 if (!isPositionIndependent()) { 1920 const MipsTargetObjectFile *TLOF = 1921 static_cast<const MipsTargetObjectFile *>( 1922 getTargetMachine().getObjFileLowering()); 1923 const GlobalObject *GO = GV->getBaseObject(); 1924 if (GO && TLOF->IsGlobalInSmallSection(GO, getTargetMachine())) 1925 // %gp_rel relocation 1926 return getAddrGPRel(N, SDLoc(N), Ty, DAG); 1927 1928 // %hi/%lo relocation 1929 return Subtarget.hasSym32() ? getAddrNonPIC(N, SDLoc(N), Ty, DAG) 1930 // %highest/%higher/%hi/%lo relocation 1931 : getAddrNonPICSym64(N, SDLoc(N), Ty, DAG); 1932 } 1933 1934 // Every other architecture would use shouldAssumeDSOLocal in here, but 1935 // mips is special. 1936 // * In PIC code mips requires got loads even for local statics! 1937 // * To save on got entries, for local statics the got entry contains the 1938 // page and an additional add instruction takes care of the low bits. 1939 // * It is legal to access a hidden symbol with a non hidden undefined, 1940 // so one cannot guarantee that all access to a hidden symbol will know 1941 // it is hidden. 1942 // * Mips linkers don't support creating a page and a full got entry for 1943 // the same symbol. 1944 // * Given all that, we have to use a full got entry for hidden symbols :-( 1945 if (GV->hasLocalLinkage()) 1946 return getAddrLocal(N, SDLoc(N), Ty, DAG, ABI.IsN32() || ABI.IsN64()); 1947 1948 if (LargeGOT) 1949 return getAddrGlobalLargeGOT( 1950 N, SDLoc(N), Ty, DAG, MipsII::MO_GOT_HI16, MipsII::MO_GOT_LO16, 1951 DAG.getEntryNode(), 1952 MachinePointerInfo::getGOT(DAG.getMachineFunction())); 1953 1954 return getAddrGlobal( 1955 N, SDLoc(N), Ty, DAG, 1956 (ABI.IsN32() || ABI.IsN64()) ? MipsII::MO_GOT_DISP : MipsII::MO_GOT, 1957 DAG.getEntryNode(), MachinePointerInfo::getGOT(DAG.getMachineFunction())); 1958 } 1959 1960 SDValue MipsTargetLowering::lowerBlockAddress(SDValue Op, 1961 SelectionDAG &DAG) const { 1962 BlockAddressSDNode *N = cast<BlockAddressSDNode>(Op); 1963 EVT Ty = Op.getValueType(); 1964 1965 if (!isPositionIndependent()) 1966 return Subtarget.hasSym32() ? getAddrNonPIC(N, SDLoc(N), Ty, DAG) 1967 : getAddrNonPICSym64(N, SDLoc(N), Ty, DAG); 1968 1969 return getAddrLocal(N, SDLoc(N), Ty, DAG, ABI.IsN32() || ABI.IsN64()); 1970 } 1971 1972 SDValue MipsTargetLowering:: 1973 lowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const 1974 { 1975 // If the relocation model is PIC, use the General Dynamic TLS Model or 1976 // Local Dynamic TLS model, otherwise use the Initial Exec or 1977 // Local Exec TLS Model. 1978 1979 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op); 1980 if (DAG.getTarget().Options.EmulatedTLS) 1981 return LowerToTLSEmulatedModel(GA, DAG); 1982 1983 SDLoc DL(GA); 1984 const GlobalValue *GV = GA->getGlobal(); 1985 EVT PtrVT = getPointerTy(DAG.getDataLayout()); 1986 1987 TLSModel::Model model = getTargetMachine().getTLSModel(GV); 1988 1989 if (model == TLSModel::GeneralDynamic || model == TLSModel::LocalDynamic) { 1990 // General Dynamic and Local Dynamic TLS Model. 1991 unsigned Flag = (model == TLSModel::LocalDynamic) ? MipsII::MO_TLSLDM 1992 : MipsII::MO_TLSGD; 1993 1994 SDValue TGA = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, Flag); 1995 SDValue Argument = DAG.getNode(MipsISD::Wrapper, DL, PtrVT, 1996 getGlobalReg(DAG, PtrVT), TGA); 1997 unsigned PtrSize = PtrVT.getSizeInBits(); 1998 IntegerType *PtrTy = Type::getIntNTy(*DAG.getContext(), PtrSize); 1999 2000 SDValue TlsGetAddr = DAG.getExternalSymbol("__tls_get_addr", PtrVT); 2001 2002 ArgListTy Args; 2003 ArgListEntry Entry; 2004 Entry.Node = Argument; 2005 Entry.Ty = PtrTy; 2006 Args.push_back(Entry); 2007 2008 TargetLowering::CallLoweringInfo CLI(DAG); 2009 CLI.setDebugLoc(DL) 2010 .setChain(DAG.getEntryNode()) 2011 .setLibCallee(CallingConv::C, PtrTy, TlsGetAddr, std::move(Args)); 2012 std::pair<SDValue, SDValue> CallResult = LowerCallTo(CLI); 2013 2014 SDValue Ret = CallResult.first; 2015 2016 if (model != TLSModel::LocalDynamic) 2017 return Ret; 2018 2019 SDValue TGAHi = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, 2020 MipsII::MO_DTPREL_HI); 2021 SDValue Hi = DAG.getNode(MipsISD::Hi, DL, PtrVT, TGAHi); 2022 SDValue TGALo = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, 2023 MipsII::MO_DTPREL_LO); 2024 SDValue Lo = DAG.getNode(MipsISD::Lo, DL, PtrVT, TGALo); 2025 SDValue Add = DAG.getNode(ISD::ADD, DL, PtrVT, Hi, Ret); 2026 return DAG.getNode(ISD::ADD, DL, PtrVT, Add, Lo); 2027 } 2028 2029 SDValue Offset; 2030 if (model == TLSModel::InitialExec) { 2031 // Initial Exec TLS Model 2032 SDValue TGA = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, 2033 MipsII::MO_GOTTPREL); 2034 TGA = DAG.getNode(MipsISD::Wrapper, DL, PtrVT, getGlobalReg(DAG, PtrVT), 2035 TGA); 2036 Offset = 2037 DAG.getLoad(PtrVT, DL, DAG.getEntryNode(), TGA, MachinePointerInfo()); 2038 } else { 2039 // Local Exec TLS Model 2040 assert(model == TLSModel::LocalExec); 2041 SDValue TGAHi = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, 2042 MipsII::MO_TPREL_HI); 2043 SDValue TGALo = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, 2044 MipsII::MO_TPREL_LO); 2045 SDValue Hi = DAG.getNode(MipsISD::Hi, DL, PtrVT, TGAHi); 2046 SDValue Lo = DAG.getNode(MipsISD::Lo, DL, PtrVT, TGALo); 2047 Offset = DAG.getNode(ISD::ADD, DL, PtrVT, Hi, Lo); 2048 } 2049 2050 SDValue ThreadPointer = DAG.getNode(MipsISD::ThreadPointer, DL, PtrVT); 2051 return DAG.getNode(ISD::ADD, DL, PtrVT, ThreadPointer, Offset); 2052 } 2053 2054 SDValue MipsTargetLowering:: 2055 lowerJumpTable(SDValue Op, SelectionDAG &DAG) const 2056 { 2057 JumpTableSDNode *N = cast<JumpTableSDNode>(Op); 2058 EVT Ty = Op.getValueType(); 2059 2060 if (!isPositionIndependent()) 2061 return Subtarget.hasSym32() ? getAddrNonPIC(N, SDLoc(N), Ty, DAG) 2062 : getAddrNonPICSym64(N, SDLoc(N), Ty, DAG); 2063 2064 return getAddrLocal(N, SDLoc(N), Ty, DAG, ABI.IsN32() || ABI.IsN64()); 2065 } 2066 2067 SDValue MipsTargetLowering:: 2068 lowerConstantPool(SDValue Op, SelectionDAG &DAG) const 2069 { 2070 ConstantPoolSDNode *N = cast<ConstantPoolSDNode>(Op); 2071 EVT Ty = Op.getValueType(); 2072 2073 if (!isPositionIndependent()) { 2074 const MipsTargetObjectFile *TLOF = 2075 static_cast<const MipsTargetObjectFile *>( 2076 getTargetMachine().getObjFileLowering()); 2077 2078 if (TLOF->IsConstantInSmallSection(DAG.getDataLayout(), N->getConstVal(), 2079 getTargetMachine())) 2080 // %gp_rel relocation 2081 return getAddrGPRel(N, SDLoc(N), Ty, DAG); 2082 2083 return Subtarget.hasSym32() ? getAddrNonPIC(N, SDLoc(N), Ty, DAG) 2084 : getAddrNonPICSym64(N, SDLoc(N), Ty, DAG); 2085 } 2086 2087 return getAddrLocal(N, SDLoc(N), Ty, DAG, ABI.IsN32() || ABI.IsN64()); 2088 } 2089 2090 SDValue MipsTargetLowering::lowerVASTART(SDValue Op, SelectionDAG &DAG) const { 2091 MachineFunction &MF = DAG.getMachineFunction(); 2092 MipsFunctionInfo *FuncInfo = MF.getInfo<MipsFunctionInfo>(); 2093 2094 SDLoc DL(Op); 2095 SDValue FI = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), 2096 getPointerTy(MF.getDataLayout())); 2097 2098 // vastart just stores the address of the VarArgsFrameIndex slot into the 2099 // memory location argument. 2100 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue(); 2101 return DAG.getStore(Op.getOperand(0), DL, FI, Op.getOperand(1), 2102 MachinePointerInfo(SV)); 2103 } 2104 2105 SDValue MipsTargetLowering::lowerVAARG(SDValue Op, SelectionDAG &DAG) const { 2106 SDNode *Node = Op.getNode(); 2107 EVT VT = Node->getValueType(0); 2108 SDValue Chain = Node->getOperand(0); 2109 SDValue VAListPtr = Node->getOperand(1); 2110 unsigned Align = Node->getConstantOperandVal(3); 2111 const Value *SV = cast<SrcValueSDNode>(Node->getOperand(2))->getValue(); 2112 SDLoc DL(Node); 2113 unsigned ArgSlotSizeInBytes = (ABI.IsN32() || ABI.IsN64()) ? 8 : 4; 2114 2115 SDValue VAListLoad = DAG.getLoad(getPointerTy(DAG.getDataLayout()), DL, Chain, 2116 VAListPtr, MachinePointerInfo(SV)); 2117 SDValue VAList = VAListLoad; 2118 2119 // Re-align the pointer if necessary. 2120 // It should only ever be necessary for 64-bit types on O32 since the minimum 2121 // argument alignment is the same as the maximum type alignment for N32/N64. 2122 // 2123 // FIXME: We currently align too often. The code generator doesn't notice 2124 // when the pointer is still aligned from the last va_arg (or pair of 2125 // va_args for the i64 on O32 case). 2126 if (Align > getMinStackArgumentAlignment()) { 2127 assert(((Align & (Align-1)) == 0) && "Expected Align to be a power of 2"); 2128 2129 VAList = DAG.getNode(ISD::ADD, DL, VAList.getValueType(), VAList, 2130 DAG.getConstant(Align - 1, DL, VAList.getValueType())); 2131 2132 VAList = DAG.getNode(ISD::AND, DL, VAList.getValueType(), VAList, 2133 DAG.getConstant(-(int64_t)Align, DL, 2134 VAList.getValueType())); 2135 } 2136 2137 // Increment the pointer, VAList, to the next vaarg. 2138 auto &TD = DAG.getDataLayout(); 2139 unsigned ArgSizeInBytes = 2140 TD.getTypeAllocSize(VT.getTypeForEVT(*DAG.getContext())); 2141 SDValue Tmp3 = 2142 DAG.getNode(ISD::ADD, DL, VAList.getValueType(), VAList, 2143 DAG.getConstant(alignTo(ArgSizeInBytes, ArgSlotSizeInBytes), 2144 DL, VAList.getValueType())); 2145 // Store the incremented VAList to the legalized pointer 2146 Chain = DAG.getStore(VAListLoad.getValue(1), DL, Tmp3, VAListPtr, 2147 MachinePointerInfo(SV)); 2148 2149 // In big-endian mode we must adjust the pointer when the load size is smaller 2150 // than the argument slot size. We must also reduce the known alignment to 2151 // match. For example in the N64 ABI, we must add 4 bytes to the offset to get 2152 // the correct half of the slot, and reduce the alignment from 8 (slot 2153 // alignment) down to 4 (type alignment). 2154 if (!Subtarget.isLittle() && ArgSizeInBytes < ArgSlotSizeInBytes) { 2155 unsigned Adjustment = ArgSlotSizeInBytes - ArgSizeInBytes; 2156 VAList = DAG.getNode(ISD::ADD, DL, VAListPtr.getValueType(), VAList, 2157 DAG.getIntPtrConstant(Adjustment, DL)); 2158 } 2159 // Load the actual argument out of the pointer VAList 2160 return DAG.getLoad(VT, DL, Chain, VAList, MachinePointerInfo()); 2161 } 2162 2163 static SDValue lowerFCOPYSIGN32(SDValue Op, SelectionDAG &DAG, 2164 bool HasExtractInsert) { 2165 EVT TyX = Op.getOperand(0).getValueType(); 2166 EVT TyY = Op.getOperand(1).getValueType(); 2167 SDLoc DL(Op); 2168 SDValue Const1 = DAG.getConstant(1, DL, MVT::i32); 2169 SDValue Const31 = DAG.getConstant(31, DL, MVT::i32); 2170 SDValue Res; 2171 2172 // If operand is of type f64, extract the upper 32-bit. Otherwise, bitcast it 2173 // to i32. 2174 SDValue X = (TyX == MVT::f32) ? 2175 DAG.getNode(ISD::BITCAST, DL, MVT::i32, Op.getOperand(0)) : 2176 DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32, Op.getOperand(0), 2177 Const1); 2178 SDValue Y = (TyY == MVT::f32) ? 2179 DAG.getNode(ISD::BITCAST, DL, MVT::i32, Op.getOperand(1)) : 2180 DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32, Op.getOperand(1), 2181 Const1); 2182 2183 if (HasExtractInsert) { 2184 // ext E, Y, 31, 1 ; extract bit31 of Y 2185 // ins X, E, 31, 1 ; insert extracted bit at bit31 of X 2186 SDValue E = DAG.getNode(MipsISD::Ext, DL, MVT::i32, Y, Const31, Const1); 2187 Res = DAG.getNode(MipsISD::Ins, DL, MVT::i32, E, Const31, Const1, X); 2188 } else { 2189 // sll SllX, X, 1 2190 // srl SrlX, SllX, 1 2191 // srl SrlY, Y, 31 2192 // sll SllY, SrlX, 31 2193 // or Or, SrlX, SllY 2194 SDValue SllX = DAG.getNode(ISD::SHL, DL, MVT::i32, X, Const1); 2195 SDValue SrlX = DAG.getNode(ISD::SRL, DL, MVT::i32, SllX, Const1); 2196 SDValue SrlY = DAG.getNode(ISD::SRL, DL, MVT::i32, Y, Const31); 2197 SDValue SllY = DAG.getNode(ISD::SHL, DL, MVT::i32, SrlY, Const31); 2198 Res = DAG.getNode(ISD::OR, DL, MVT::i32, SrlX, SllY); 2199 } 2200 2201 if (TyX == MVT::f32) 2202 return DAG.getNode(ISD::BITCAST, DL, Op.getOperand(0).getValueType(), Res); 2203 2204 SDValue LowX = DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32, 2205 Op.getOperand(0), 2206 DAG.getConstant(0, DL, MVT::i32)); 2207 return DAG.getNode(MipsISD::BuildPairF64, DL, MVT::f64, LowX, Res); 2208 } 2209 2210 static SDValue lowerFCOPYSIGN64(SDValue Op, SelectionDAG &DAG, 2211 bool HasExtractInsert) { 2212 unsigned WidthX = Op.getOperand(0).getValueSizeInBits(); 2213 unsigned WidthY = Op.getOperand(1).getValueSizeInBits(); 2214 EVT TyX = MVT::getIntegerVT(WidthX), TyY = MVT::getIntegerVT(WidthY); 2215 SDLoc DL(Op); 2216 SDValue Const1 = DAG.getConstant(1, DL, MVT::i32); 2217 2218 // Bitcast to integer nodes. 2219 SDValue X = DAG.getNode(ISD::BITCAST, DL, TyX, Op.getOperand(0)); 2220 SDValue Y = DAG.getNode(ISD::BITCAST, DL, TyY, Op.getOperand(1)); 2221 2222 if (HasExtractInsert) { 2223 // ext E, Y, width(Y) - 1, 1 ; extract bit width(Y)-1 of Y 2224 // ins X, E, width(X) - 1, 1 ; insert extracted bit at bit width(X)-1 of X 2225 SDValue E = DAG.getNode(MipsISD::Ext, DL, TyY, Y, 2226 DAG.getConstant(WidthY - 1, DL, MVT::i32), Const1); 2227 2228 if (WidthX > WidthY) 2229 E = DAG.getNode(ISD::ZERO_EXTEND, DL, TyX, E); 2230 else if (WidthY > WidthX) 2231 E = DAG.getNode(ISD::TRUNCATE, DL, TyX, E); 2232 2233 SDValue I = DAG.getNode(MipsISD::Ins, DL, TyX, E, 2234 DAG.getConstant(WidthX - 1, DL, MVT::i32), Const1, 2235 X); 2236 return DAG.getNode(ISD::BITCAST, DL, Op.getOperand(0).getValueType(), I); 2237 } 2238 2239 // (d)sll SllX, X, 1 2240 // (d)srl SrlX, SllX, 1 2241 // (d)srl SrlY, Y, width(Y)-1 2242 // (d)sll SllY, SrlX, width(Y)-1 2243 // or Or, SrlX, SllY 2244 SDValue SllX = DAG.getNode(ISD::SHL, DL, TyX, X, Const1); 2245 SDValue SrlX = DAG.getNode(ISD::SRL, DL, TyX, SllX, Const1); 2246 SDValue SrlY = DAG.getNode(ISD::SRL, DL, TyY, Y, 2247 DAG.getConstant(WidthY - 1, DL, MVT::i32)); 2248 2249 if (WidthX > WidthY) 2250 SrlY = DAG.getNode(ISD::ZERO_EXTEND, DL, TyX, SrlY); 2251 else if (WidthY > WidthX) 2252 SrlY = DAG.getNode(ISD::TRUNCATE, DL, TyX, SrlY); 2253 2254 SDValue SllY = DAG.getNode(ISD::SHL, DL, TyX, SrlY, 2255 DAG.getConstant(WidthX - 1, DL, MVT::i32)); 2256 SDValue Or = DAG.getNode(ISD::OR, DL, TyX, SrlX, SllY); 2257 return DAG.getNode(ISD::BITCAST, DL, Op.getOperand(0).getValueType(), Or); 2258 } 2259 2260 SDValue 2261 MipsTargetLowering::lowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const { 2262 if (Subtarget.isGP64bit()) 2263 return lowerFCOPYSIGN64(Op, DAG, Subtarget.hasExtractInsert()); 2264 2265 return lowerFCOPYSIGN32(Op, DAG, Subtarget.hasExtractInsert()); 2266 } 2267 2268 SDValue MipsTargetLowering:: 2269 lowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const { 2270 // check the depth 2271 assert((cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue() == 0) && 2272 "Frame address can only be determined for current frame."); 2273 2274 MachineFrameInfo &MFI = DAG.getMachineFunction().getFrameInfo(); 2275 MFI.setFrameAddressIsTaken(true); 2276 EVT VT = Op.getValueType(); 2277 SDLoc DL(Op); 2278 SDValue FrameAddr = DAG.getCopyFromReg( 2279 DAG.getEntryNode(), DL, ABI.IsN64() ? Mips::FP_64 : Mips::FP, VT); 2280 return FrameAddr; 2281 } 2282 2283 SDValue MipsTargetLowering::lowerRETURNADDR(SDValue Op, 2284 SelectionDAG &DAG) const { 2285 if (verifyReturnAddressArgumentIsConstant(Op, DAG)) 2286 return SDValue(); 2287 2288 // check the depth 2289 assert((cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue() == 0) && 2290 "Return address can be determined only for current frame."); 2291 2292 MachineFunction &MF = DAG.getMachineFunction(); 2293 MachineFrameInfo &MFI = MF.getFrameInfo(); 2294 MVT VT = Op.getSimpleValueType(); 2295 unsigned RA = ABI.IsN64() ? Mips::RA_64 : Mips::RA; 2296 MFI.setReturnAddressIsTaken(true); 2297 2298 // Return RA, which contains the return address. Mark it an implicit live-in. 2299 unsigned Reg = MF.addLiveIn(RA, getRegClassFor(VT)); 2300 return DAG.getCopyFromReg(DAG.getEntryNode(), SDLoc(Op), Reg, VT); 2301 } 2302 2303 // An EH_RETURN is the result of lowering llvm.eh.return which in turn is 2304 // generated from __builtin_eh_return (offset, handler) 2305 // The effect of this is to adjust the stack pointer by "offset" 2306 // and then branch to "handler". 2307 SDValue MipsTargetLowering::lowerEH_RETURN(SDValue Op, SelectionDAG &DAG) 2308 const { 2309 MachineFunction &MF = DAG.getMachineFunction(); 2310 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>(); 2311 2312 MipsFI->setCallsEhReturn(); 2313 SDValue Chain = Op.getOperand(0); 2314 SDValue Offset = Op.getOperand(1); 2315 SDValue Handler = Op.getOperand(2); 2316 SDLoc DL(Op); 2317 EVT Ty = ABI.IsN64() ? MVT::i64 : MVT::i32; 2318 2319 // Store stack offset in V1, store jump target in V0. Glue CopyToReg and 2320 // EH_RETURN nodes, so that instructions are emitted back-to-back. 2321 unsigned OffsetReg = ABI.IsN64() ? Mips::V1_64 : Mips::V1; 2322 unsigned AddrReg = ABI.IsN64() ? Mips::V0_64 : Mips::V0; 2323 Chain = DAG.getCopyToReg(Chain, DL, OffsetReg, Offset, SDValue()); 2324 Chain = DAG.getCopyToReg(Chain, DL, AddrReg, Handler, Chain.getValue(1)); 2325 return DAG.getNode(MipsISD::EH_RETURN, DL, MVT::Other, Chain, 2326 DAG.getRegister(OffsetReg, Ty), 2327 DAG.getRegister(AddrReg, getPointerTy(MF.getDataLayout())), 2328 Chain.getValue(1)); 2329 } 2330 2331 SDValue MipsTargetLowering::lowerATOMIC_FENCE(SDValue Op, 2332 SelectionDAG &DAG) const { 2333 // FIXME: Need pseudo-fence for 'singlethread' fences 2334 // FIXME: Set SType for weaker fences where supported/appropriate. 2335 unsigned SType = 0; 2336 SDLoc DL(Op); 2337 return DAG.getNode(MipsISD::Sync, DL, MVT::Other, Op.getOperand(0), 2338 DAG.getConstant(SType, DL, MVT::i32)); 2339 } 2340 2341 SDValue MipsTargetLowering::lowerShiftLeftParts(SDValue Op, 2342 SelectionDAG &DAG) const { 2343 SDLoc DL(Op); 2344 MVT VT = Subtarget.isGP64bit() ? MVT::i64 : MVT::i32; 2345 2346 SDValue Lo = Op.getOperand(0), Hi = Op.getOperand(1); 2347 SDValue Shamt = Op.getOperand(2); 2348 // if shamt < (VT.bits): 2349 // lo = (shl lo, shamt) 2350 // hi = (or (shl hi, shamt) (srl (srl lo, 1), ~shamt)) 2351 // else: 2352 // lo = 0 2353 // hi = (shl lo, shamt[4:0]) 2354 SDValue Not = DAG.getNode(ISD::XOR, DL, MVT::i32, Shamt, 2355 DAG.getConstant(-1, DL, MVT::i32)); 2356 SDValue ShiftRight1Lo = DAG.getNode(ISD::SRL, DL, VT, Lo, 2357 DAG.getConstant(1, DL, VT)); 2358 SDValue ShiftRightLo = DAG.getNode(ISD::SRL, DL, VT, ShiftRight1Lo, Not); 2359 SDValue ShiftLeftHi = DAG.getNode(ISD::SHL, DL, VT, Hi, Shamt); 2360 SDValue Or = DAG.getNode(ISD::OR, DL, VT, ShiftLeftHi, ShiftRightLo); 2361 SDValue ShiftLeftLo = DAG.getNode(ISD::SHL, DL, VT, Lo, Shamt); 2362 SDValue Cond = DAG.getNode(ISD::AND, DL, MVT::i32, Shamt, 2363 DAG.getConstant(VT.getSizeInBits(), DL, MVT::i32)); 2364 Lo = DAG.getNode(ISD::SELECT, DL, VT, Cond, 2365 DAG.getConstant(0, DL, VT), ShiftLeftLo); 2366 Hi = DAG.getNode(ISD::SELECT, DL, VT, Cond, ShiftLeftLo, Or); 2367 2368 SDValue Ops[2] = {Lo, Hi}; 2369 return DAG.getMergeValues(Ops, DL); 2370 } 2371 2372 SDValue MipsTargetLowering::lowerShiftRightParts(SDValue Op, SelectionDAG &DAG, 2373 bool IsSRA) const { 2374 SDLoc DL(Op); 2375 SDValue Lo = Op.getOperand(0), Hi = Op.getOperand(1); 2376 SDValue Shamt = Op.getOperand(2); 2377 MVT VT = Subtarget.isGP64bit() ? MVT::i64 : MVT::i32; 2378 2379 // if shamt < (VT.bits): 2380 // lo = (or (shl (shl hi, 1), ~shamt) (srl lo, shamt)) 2381 // if isSRA: 2382 // hi = (sra hi, shamt) 2383 // else: 2384 // hi = (srl hi, shamt) 2385 // else: 2386 // if isSRA: 2387 // lo = (sra hi, shamt[4:0]) 2388 // hi = (sra hi, 31) 2389 // else: 2390 // lo = (srl hi, shamt[4:0]) 2391 // hi = 0 2392 SDValue Not = DAG.getNode(ISD::XOR, DL, MVT::i32, Shamt, 2393 DAG.getConstant(-1, DL, MVT::i32)); 2394 SDValue ShiftLeft1Hi = DAG.getNode(ISD::SHL, DL, VT, Hi, 2395 DAG.getConstant(1, DL, VT)); 2396 SDValue ShiftLeftHi = DAG.getNode(ISD::SHL, DL, VT, ShiftLeft1Hi, Not); 2397 SDValue ShiftRightLo = DAG.getNode(ISD::SRL, DL, VT, Lo, Shamt); 2398 SDValue Or = DAG.getNode(ISD::OR, DL, VT, ShiftLeftHi, ShiftRightLo); 2399 SDValue ShiftRightHi = DAG.getNode(IsSRA ? ISD::SRA : ISD::SRL, 2400 DL, VT, Hi, Shamt); 2401 SDValue Cond = DAG.getNode(ISD::AND, DL, MVT::i32, Shamt, 2402 DAG.getConstant(VT.getSizeInBits(), DL, MVT::i32)); 2403 SDValue Ext = DAG.getNode(ISD::SRA, DL, VT, Hi, 2404 DAG.getConstant(VT.getSizeInBits() - 1, DL, VT)); 2405 Lo = DAG.getNode(ISD::SELECT, DL, VT, Cond, ShiftRightHi, Or); 2406 Hi = DAG.getNode(ISD::SELECT, DL, VT, Cond, 2407 IsSRA ? Ext : DAG.getConstant(0, DL, VT), ShiftRightHi); 2408 2409 SDValue Ops[2] = {Lo, Hi}; 2410 return DAG.getMergeValues(Ops, DL); 2411 } 2412 2413 static SDValue createLoadLR(unsigned Opc, SelectionDAG &DAG, LoadSDNode *LD, 2414 SDValue Chain, SDValue Src, unsigned Offset) { 2415 SDValue Ptr = LD->getBasePtr(); 2416 EVT VT = LD->getValueType(0), MemVT = LD->getMemoryVT(); 2417 EVT BasePtrVT = Ptr.getValueType(); 2418 SDLoc DL(LD); 2419 SDVTList VTList = DAG.getVTList(VT, MVT::Other); 2420 2421 if (Offset) 2422 Ptr = DAG.getNode(ISD::ADD, DL, BasePtrVT, Ptr, 2423 DAG.getConstant(Offset, DL, BasePtrVT)); 2424 2425 SDValue Ops[] = { Chain, Ptr, Src }; 2426 return DAG.getMemIntrinsicNode(Opc, DL, VTList, Ops, MemVT, 2427 LD->getMemOperand()); 2428 } 2429 2430 // Expand an unaligned 32 or 64-bit integer load node. 2431 SDValue MipsTargetLowering::lowerLOAD(SDValue Op, SelectionDAG &DAG) const { 2432 LoadSDNode *LD = cast<LoadSDNode>(Op); 2433 EVT MemVT = LD->getMemoryVT(); 2434 2435 if (Subtarget.systemSupportsUnalignedAccess()) 2436 return Op; 2437 2438 // Return if load is aligned or if MemVT is neither i32 nor i64. 2439 if ((LD->getAlignment() >= MemVT.getSizeInBits() / 8) || 2440 ((MemVT != MVT::i32) && (MemVT != MVT::i64))) 2441 return SDValue(); 2442 2443 bool IsLittle = Subtarget.isLittle(); 2444 EVT VT = Op.getValueType(); 2445 ISD::LoadExtType ExtType = LD->getExtensionType(); 2446 SDValue Chain = LD->getChain(), Undef = DAG.getUNDEF(VT); 2447 2448 assert((VT == MVT::i32) || (VT == MVT::i64)); 2449 2450 // Expand 2451 // (set dst, (i64 (load baseptr))) 2452 // to 2453 // (set tmp, (ldl (add baseptr, 7), undef)) 2454 // (set dst, (ldr baseptr, tmp)) 2455 if ((VT == MVT::i64) && (ExtType == ISD::NON_EXTLOAD)) { 2456 SDValue LDL = createLoadLR(MipsISD::LDL, DAG, LD, Chain, Undef, 2457 IsLittle ? 7 : 0); 2458 return createLoadLR(MipsISD::LDR, DAG, LD, LDL.getValue(1), LDL, 2459 IsLittle ? 0 : 7); 2460 } 2461 2462 SDValue LWL = createLoadLR(MipsISD::LWL, DAG, LD, Chain, Undef, 2463 IsLittle ? 3 : 0); 2464 SDValue LWR = createLoadLR(MipsISD::LWR, DAG, LD, LWL.getValue(1), LWL, 2465 IsLittle ? 0 : 3); 2466 2467 // Expand 2468 // (set dst, (i32 (load baseptr))) or 2469 // (set dst, (i64 (sextload baseptr))) or 2470 // (set dst, (i64 (extload baseptr))) 2471 // to 2472 // (set tmp, (lwl (add baseptr, 3), undef)) 2473 // (set dst, (lwr baseptr, tmp)) 2474 if ((VT == MVT::i32) || (ExtType == ISD::SEXTLOAD) || 2475 (ExtType == ISD::EXTLOAD)) 2476 return LWR; 2477 2478 assert((VT == MVT::i64) && (ExtType == ISD::ZEXTLOAD)); 2479 2480 // Expand 2481 // (set dst, (i64 (zextload baseptr))) 2482 // to 2483 // (set tmp0, (lwl (add baseptr, 3), undef)) 2484 // (set tmp1, (lwr baseptr, tmp0)) 2485 // (set tmp2, (shl tmp1, 32)) 2486 // (set dst, (srl tmp2, 32)) 2487 SDLoc DL(LD); 2488 SDValue Const32 = DAG.getConstant(32, DL, MVT::i32); 2489 SDValue SLL = DAG.getNode(ISD::SHL, DL, MVT::i64, LWR, Const32); 2490 SDValue SRL = DAG.getNode(ISD::SRL, DL, MVT::i64, SLL, Const32); 2491 SDValue Ops[] = { SRL, LWR.getValue(1) }; 2492 return DAG.getMergeValues(Ops, DL); 2493 } 2494 2495 static SDValue createStoreLR(unsigned Opc, SelectionDAG &DAG, StoreSDNode *SD, 2496 SDValue Chain, unsigned Offset) { 2497 SDValue Ptr = SD->getBasePtr(), Value = SD->getValue(); 2498 EVT MemVT = SD->getMemoryVT(), BasePtrVT = Ptr.getValueType(); 2499 SDLoc DL(SD); 2500 SDVTList VTList = DAG.getVTList(MVT::Other); 2501 2502 if (Offset) 2503 Ptr = DAG.getNode(ISD::ADD, DL, BasePtrVT, Ptr, 2504 DAG.getConstant(Offset, DL, BasePtrVT)); 2505 2506 SDValue Ops[] = { Chain, Value, Ptr }; 2507 return DAG.getMemIntrinsicNode(Opc, DL, VTList, Ops, MemVT, 2508 SD->getMemOperand()); 2509 } 2510 2511 // Expand an unaligned 32 or 64-bit integer store node. 2512 static SDValue lowerUnalignedIntStore(StoreSDNode *SD, SelectionDAG &DAG, 2513 bool IsLittle) { 2514 SDValue Value = SD->getValue(), Chain = SD->getChain(); 2515 EVT VT = Value.getValueType(); 2516 2517 // Expand 2518 // (store val, baseptr) or 2519 // (truncstore val, baseptr) 2520 // to 2521 // (swl val, (add baseptr, 3)) 2522 // (swr val, baseptr) 2523 if ((VT == MVT::i32) || SD->isTruncatingStore()) { 2524 SDValue SWL = createStoreLR(MipsISD::SWL, DAG, SD, Chain, 2525 IsLittle ? 3 : 0); 2526 return createStoreLR(MipsISD::SWR, DAG, SD, SWL, IsLittle ? 0 : 3); 2527 } 2528 2529 assert(VT == MVT::i64); 2530 2531 // Expand 2532 // (store val, baseptr) 2533 // to 2534 // (sdl val, (add baseptr, 7)) 2535 // (sdr val, baseptr) 2536 SDValue SDL = createStoreLR(MipsISD::SDL, DAG, SD, Chain, IsLittle ? 7 : 0); 2537 return createStoreLR(MipsISD::SDR, DAG, SD, SDL, IsLittle ? 0 : 7); 2538 } 2539 2540 // Lower (store (fp_to_sint $fp) $ptr) to (store (TruncIntFP $fp), $ptr). 2541 static SDValue lowerFP_TO_SINT_STORE(StoreSDNode *SD, SelectionDAG &DAG) { 2542 SDValue Val = SD->getValue(); 2543 2544 if (Val.getOpcode() != ISD::FP_TO_SINT) 2545 return SDValue(); 2546 2547 EVT FPTy = EVT::getFloatingPointVT(Val.getValueSizeInBits()); 2548 SDValue Tr = DAG.getNode(MipsISD::TruncIntFP, SDLoc(Val), FPTy, 2549 Val.getOperand(0)); 2550 return DAG.getStore(SD->getChain(), SDLoc(SD), Tr, SD->getBasePtr(), 2551 SD->getPointerInfo(), SD->getAlignment(), 2552 SD->getMemOperand()->getFlags()); 2553 } 2554 2555 SDValue MipsTargetLowering::lowerSTORE(SDValue Op, SelectionDAG &DAG) const { 2556 StoreSDNode *SD = cast<StoreSDNode>(Op); 2557 EVT MemVT = SD->getMemoryVT(); 2558 2559 // Lower unaligned integer stores. 2560 if (!Subtarget.systemSupportsUnalignedAccess() && 2561 (SD->getAlignment() < MemVT.getSizeInBits() / 8) && 2562 ((MemVT == MVT::i32) || (MemVT == MVT::i64))) 2563 return lowerUnalignedIntStore(SD, DAG, Subtarget.isLittle()); 2564 2565 return lowerFP_TO_SINT_STORE(SD, DAG); 2566 } 2567 2568 SDValue MipsTargetLowering::lowerEH_DWARF_CFA(SDValue Op, 2569 SelectionDAG &DAG) const { 2570 2571 // Return a fixed StackObject with offset 0 which points to the old stack 2572 // pointer. 2573 MachineFrameInfo &MFI = DAG.getMachineFunction().getFrameInfo(); 2574 EVT ValTy = Op->getValueType(0); 2575 int FI = MFI.CreateFixedObject(Op.getValueSizeInBits() / 8, 0, false); 2576 return DAG.getFrameIndex(FI, ValTy); 2577 } 2578 2579 SDValue MipsTargetLowering::lowerFP_TO_SINT(SDValue Op, 2580 SelectionDAG &DAG) const { 2581 EVT FPTy = EVT::getFloatingPointVT(Op.getValueSizeInBits()); 2582 SDValue Trunc = DAG.getNode(MipsISD::TruncIntFP, SDLoc(Op), FPTy, 2583 Op.getOperand(0)); 2584 return DAG.getNode(ISD::BITCAST, SDLoc(Op), Op.getValueType(), Trunc); 2585 } 2586 2587 //===----------------------------------------------------------------------===// 2588 // Calling Convention Implementation 2589 //===----------------------------------------------------------------------===// 2590 2591 //===----------------------------------------------------------------------===// 2592 // TODO: Implement a generic logic using tblgen that can support this. 2593 // Mips O32 ABI rules: 2594 // --- 2595 // i32 - Passed in A0, A1, A2, A3 and stack 2596 // f32 - Only passed in f32 registers if no int reg has been used yet to hold 2597 // an argument. Otherwise, passed in A1, A2, A3 and stack. 2598 // f64 - Only passed in two aliased f32 registers if no int reg has been used 2599 // yet to hold an argument. Otherwise, use A2, A3 and stack. If A1 is 2600 // not used, it must be shadowed. If only A3 is available, shadow it and 2601 // go to stack. 2602 // vXiX - Received as scalarized i32s, passed in A0 - A3 and the stack. 2603 // vXf32 - Passed in either a pair of registers {A0, A1}, {A2, A3} or {A0 - A3} 2604 // with the remainder spilled to the stack. 2605 // vXf64 - Passed in either {A0, A1, A2, A3} or {A2, A3} and in both cases 2606 // spilling the remainder to the stack. 2607 // 2608 // For vararg functions, all arguments are passed in A0, A1, A2, A3 and stack. 2609 //===----------------------------------------------------------------------===// 2610 2611 static bool CC_MipsO32(unsigned ValNo, MVT ValVT, MVT LocVT, 2612 CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, 2613 CCState &State, ArrayRef<MCPhysReg> F64Regs) { 2614 const MipsSubtarget &Subtarget = static_cast<const MipsSubtarget &>( 2615 State.getMachineFunction().getSubtarget()); 2616 2617 static const MCPhysReg IntRegs[] = { Mips::A0, Mips::A1, Mips::A2, Mips::A3 }; 2618 2619 const MipsCCState * MipsState = static_cast<MipsCCState *>(&State); 2620 2621 static const MCPhysReg F32Regs[] = { Mips::F12, Mips::F14 }; 2622 2623 static const MCPhysReg FloatVectorIntRegs[] = { Mips::A0, Mips::A2 }; 2624 2625 // Do not process byval args here. 2626 if (ArgFlags.isByVal()) 2627 return true; 2628 2629 // Promote i8 and i16 2630 if (ArgFlags.isInReg() && !Subtarget.isLittle()) { 2631 if (LocVT == MVT::i8 || LocVT == MVT::i16 || LocVT == MVT::i32) { 2632 LocVT = MVT::i32; 2633 if (ArgFlags.isSExt()) 2634 LocInfo = CCValAssign::SExtUpper; 2635 else if (ArgFlags.isZExt()) 2636 LocInfo = CCValAssign::ZExtUpper; 2637 else 2638 LocInfo = CCValAssign::AExtUpper; 2639 } 2640 } 2641 2642 // Promote i8 and i16 2643 if (LocVT == MVT::i8 || LocVT == MVT::i16) { 2644 LocVT = MVT::i32; 2645 if (ArgFlags.isSExt()) 2646 LocInfo = CCValAssign::SExt; 2647 else if (ArgFlags.isZExt()) 2648 LocInfo = CCValAssign::ZExt; 2649 else 2650 LocInfo = CCValAssign::AExt; 2651 } 2652 2653 unsigned Reg; 2654 2655 // f32 and f64 are allocated in A0, A1, A2, A3 when either of the following 2656 // is true: function is vararg, argument is 3rd or higher, there is previous 2657 // argument which is not f32 or f64. 2658 bool AllocateFloatsInIntReg = State.isVarArg() || ValNo > 1 || 2659 State.getFirstUnallocated(F32Regs) != ValNo; 2660 unsigned OrigAlign = ArgFlags.getOrigAlign(); 2661 bool isI64 = (ValVT == MVT::i32 && OrigAlign == 8); 2662 bool isVectorFloat = MipsState->WasOriginalArgVectorFloat(ValNo); 2663 2664 // The MIPS vector ABI for floats passes them in a pair of registers 2665 if (ValVT == MVT::i32 && isVectorFloat) { 2666 // This is the start of an vector that was scalarized into an unknown number 2667 // of components. It doesn't matter how many there are. Allocate one of the 2668 // notional 8 byte aligned registers which map onto the argument stack, and 2669 // shadow the register lost to alignment requirements. 2670 if (ArgFlags.isSplit()) { 2671 Reg = State.AllocateReg(FloatVectorIntRegs); 2672 if (Reg == Mips::A2) 2673 State.AllocateReg(Mips::A1); 2674 else if (Reg == 0) 2675 State.AllocateReg(Mips::A3); 2676 } else { 2677 // If we're an intermediate component of the split, we can just attempt to 2678 // allocate a register directly. 2679 Reg = State.AllocateReg(IntRegs); 2680 } 2681 } else if (ValVT == MVT::i32 || (ValVT == MVT::f32 && AllocateFloatsInIntReg)) { 2682 Reg = State.AllocateReg(IntRegs); 2683 // If this is the first part of an i64 arg, 2684 // the allocated register must be either A0 or A2. 2685 if (isI64 && (Reg == Mips::A1 || Reg == Mips::A3)) 2686 Reg = State.AllocateReg(IntRegs); 2687 LocVT = MVT::i32; 2688 } else if (ValVT == MVT::f64 && AllocateFloatsInIntReg) { 2689 // Allocate int register and shadow next int register. If first 2690 // available register is Mips::A1 or Mips::A3, shadow it too. 2691 Reg = State.AllocateReg(IntRegs); 2692 if (Reg == Mips::A1 || Reg == Mips::A3) 2693 Reg = State.AllocateReg(IntRegs); 2694 State.AllocateReg(IntRegs); 2695 LocVT = MVT::i32; 2696 } else if (ValVT.isFloatingPoint() && !AllocateFloatsInIntReg) { 2697 // we are guaranteed to find an available float register 2698 if (ValVT == MVT::f32) { 2699 Reg = State.AllocateReg(F32Regs); 2700 // Shadow int register 2701 State.AllocateReg(IntRegs); 2702 } else { 2703 Reg = State.AllocateReg(F64Regs); 2704 // Shadow int registers 2705 unsigned Reg2 = State.AllocateReg(IntRegs); 2706 if (Reg2 == Mips::A1 || Reg2 == Mips::A3) 2707 State.AllocateReg(IntRegs); 2708 State.AllocateReg(IntRegs); 2709 } 2710 } else 2711 llvm_unreachable("Cannot handle this ValVT."); 2712 2713 if (!Reg) { 2714 unsigned Offset = State.AllocateStack(ValVT.getSizeInBits() >> 3, 2715 OrigAlign); 2716 State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo)); 2717 } else 2718 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); 2719 2720 return false; 2721 } 2722 2723 static bool CC_MipsO32_FP32(unsigned ValNo, MVT ValVT, 2724 MVT LocVT, CCValAssign::LocInfo LocInfo, 2725 ISD::ArgFlagsTy ArgFlags, CCState &State) { 2726 static const MCPhysReg F64Regs[] = { Mips::D6, Mips::D7 }; 2727 2728 return CC_MipsO32(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State, F64Regs); 2729 } 2730 2731 static bool CC_MipsO32_FP64(unsigned ValNo, MVT ValVT, 2732 MVT LocVT, CCValAssign::LocInfo LocInfo, 2733 ISD::ArgFlagsTy ArgFlags, CCState &State) { 2734 static const MCPhysReg F64Regs[] = { Mips::D12_64, Mips::D14_64 }; 2735 2736 return CC_MipsO32(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State, F64Regs); 2737 } 2738 2739 static bool CC_MipsO32(unsigned ValNo, MVT ValVT, MVT LocVT, 2740 CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, 2741 CCState &State) LLVM_ATTRIBUTE_UNUSED; 2742 2743 #include "MipsGenCallingConv.inc" 2744 2745 //===----------------------------------------------------------------------===// 2746 // Call Calling Convention Implementation 2747 //===----------------------------------------------------------------------===// 2748 2749 // Return next O32 integer argument register. 2750 static unsigned getNextIntArgReg(unsigned Reg) { 2751 assert((Reg == Mips::A0) || (Reg == Mips::A2)); 2752 return (Reg == Mips::A0) ? Mips::A1 : Mips::A3; 2753 } 2754 2755 SDValue MipsTargetLowering::passArgOnStack(SDValue StackPtr, unsigned Offset, 2756 SDValue Chain, SDValue Arg, 2757 const SDLoc &DL, bool IsTailCall, 2758 SelectionDAG &DAG) const { 2759 if (!IsTailCall) { 2760 SDValue PtrOff = 2761 DAG.getNode(ISD::ADD, DL, getPointerTy(DAG.getDataLayout()), StackPtr, 2762 DAG.getIntPtrConstant(Offset, DL)); 2763 return DAG.getStore(Chain, DL, Arg, PtrOff, MachinePointerInfo()); 2764 } 2765 2766 MachineFrameInfo &MFI = DAG.getMachineFunction().getFrameInfo(); 2767 int FI = MFI.CreateFixedObject(Arg.getValueSizeInBits() / 8, Offset, false); 2768 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy(DAG.getDataLayout())); 2769 return DAG.getStore(Chain, DL, Arg, FIN, MachinePointerInfo(), 2770 /* Alignment = */ 0, MachineMemOperand::MOVolatile); 2771 } 2772 2773 void MipsTargetLowering:: 2774 getOpndList(SmallVectorImpl<SDValue> &Ops, 2775 std::deque< std::pair<unsigned, SDValue> > &RegsToPass, 2776 bool IsPICCall, bool GlobalOrExternal, bool InternalLinkage, 2777 bool IsCallReloc, CallLoweringInfo &CLI, SDValue Callee, 2778 SDValue Chain) const { 2779 // Insert node "GP copy globalreg" before call to function. 2780 // 2781 // R_MIPS_CALL* operators (emitted when non-internal functions are called 2782 // in PIC mode) allow symbols to be resolved via lazy binding. 2783 // The lazy binding stub requires GP to point to the GOT. 2784 // Note that we don't need GP to point to the GOT for indirect calls 2785 // (when R_MIPS_CALL* is not used for the call) because Mips linker generates 2786 // lazy binding stub for a function only when R_MIPS_CALL* are the only relocs 2787 // used for the function (that is, Mips linker doesn't generate lazy binding 2788 // stub for a function whose address is taken in the program). 2789 if (IsPICCall && !InternalLinkage && IsCallReloc) { 2790 unsigned GPReg = ABI.IsN64() ? Mips::GP_64 : Mips::GP; 2791 EVT Ty = ABI.IsN64() ? MVT::i64 : MVT::i32; 2792 RegsToPass.push_back(std::make_pair(GPReg, getGlobalReg(CLI.DAG, Ty))); 2793 } 2794 2795 // Build a sequence of copy-to-reg nodes chained together with token 2796 // chain and flag operands which copy the outgoing args into registers. 2797 // The InFlag in necessary since all emitted instructions must be 2798 // stuck together. 2799 SDValue InFlag; 2800 2801 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) { 2802 Chain = CLI.DAG.getCopyToReg(Chain, CLI.DL, RegsToPass[i].first, 2803 RegsToPass[i].second, InFlag); 2804 InFlag = Chain.getValue(1); 2805 } 2806 2807 // Add argument registers to the end of the list so that they are 2808 // known live into the call. 2809 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) 2810 Ops.push_back(CLI.DAG.getRegister(RegsToPass[i].first, 2811 RegsToPass[i].second.getValueType())); 2812 2813 // Add a register mask operand representing the call-preserved registers. 2814 const TargetRegisterInfo *TRI = Subtarget.getRegisterInfo(); 2815 const uint32_t *Mask = 2816 TRI->getCallPreservedMask(CLI.DAG.getMachineFunction(), CLI.CallConv); 2817 assert(Mask && "Missing call preserved mask for calling convention"); 2818 if (Subtarget.inMips16HardFloat()) { 2819 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(CLI.Callee)) { 2820 llvm::StringRef Sym = G->getGlobal()->getName(); 2821 Function *F = G->getGlobal()->getParent()->getFunction(Sym); 2822 if (F && F->hasFnAttribute("__Mips16RetHelper")) { 2823 Mask = MipsRegisterInfo::getMips16RetHelperMask(); 2824 } 2825 } 2826 } 2827 Ops.push_back(CLI.DAG.getRegisterMask(Mask)); 2828 2829 if (InFlag.getNode()) 2830 Ops.push_back(InFlag); 2831 } 2832 2833 /// LowerCall - functions arguments are copied from virtual regs to 2834 /// (physical regs)/(stack frame), CALLSEQ_START and CALLSEQ_END are emitted. 2835 SDValue 2836 MipsTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI, 2837 SmallVectorImpl<SDValue> &InVals) const { 2838 SelectionDAG &DAG = CLI.DAG; 2839 SDLoc DL = CLI.DL; 2840 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs; 2841 SmallVectorImpl<SDValue> &OutVals = CLI.OutVals; 2842 SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins; 2843 SDValue Chain = CLI.Chain; 2844 SDValue Callee = CLI.Callee; 2845 bool &IsTailCall = CLI.IsTailCall; 2846 CallingConv::ID CallConv = CLI.CallConv; 2847 bool IsVarArg = CLI.IsVarArg; 2848 2849 MachineFunction &MF = DAG.getMachineFunction(); 2850 MachineFrameInfo &MFI = MF.getFrameInfo(); 2851 const TargetFrameLowering *TFL = Subtarget.getFrameLowering(); 2852 MipsFunctionInfo *FuncInfo = MF.getInfo<MipsFunctionInfo>(); 2853 bool IsPIC = isPositionIndependent(); 2854 2855 // Analyze operands of the call, assigning locations to each operand. 2856 SmallVector<CCValAssign, 16> ArgLocs; 2857 MipsCCState CCInfo( 2858 CallConv, IsVarArg, DAG.getMachineFunction(), ArgLocs, *DAG.getContext(), 2859 MipsCCState::getSpecialCallingConvForCallee(Callee.getNode(), Subtarget)); 2860 2861 // Allocate the reserved argument area. It seems strange to do this from the 2862 // caller side but removing it breaks the frame size calculation. 2863 CCInfo.AllocateStack(ABI.GetCalleeAllocdArgSizeInBytes(CallConv), 1); 2864 2865 const ExternalSymbolSDNode *ES = 2866 dyn_cast_or_null<const ExternalSymbolSDNode>(Callee.getNode()); 2867 CCInfo.AnalyzeCallOperands(Outs, CC_Mips, CLI.getArgs(), 2868 ES ? ES->getSymbol() : nullptr); 2869 2870 // Get a count of how many bytes are to be pushed on the stack. 2871 unsigned NextStackOffset = CCInfo.getNextStackOffset(); 2872 2873 // Check if it's really possible to do a tail call. Restrict it to functions 2874 // that are part of this compilation unit. 2875 bool InternalLinkage = false; 2876 if (IsTailCall) { 2877 IsTailCall = isEligibleForTailCallOptimization( 2878 CCInfo, NextStackOffset, *MF.getInfo<MipsFunctionInfo>()); 2879 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) { 2880 InternalLinkage = G->getGlobal()->hasInternalLinkage(); 2881 IsTailCall &= (InternalLinkage || G->getGlobal()->hasLocalLinkage() || 2882 G->getGlobal()->hasPrivateLinkage() || 2883 G->getGlobal()->hasHiddenVisibility() || 2884 G->getGlobal()->hasProtectedVisibility()); 2885 } 2886 } 2887 if (!IsTailCall && CLI.CS && CLI.CS->isMustTailCall()) 2888 report_fatal_error("failed to perform tail call elimination on a call " 2889 "site marked musttail"); 2890 2891 if (IsTailCall) 2892 ++NumTailCalls; 2893 2894 // Chain is the output chain of the last Load/Store or CopyToReg node. 2895 // ByValChain is the output chain of the last Memcpy node created for copying 2896 // byval arguments to the stack. 2897 unsigned StackAlignment = TFL->getStackAlignment(); 2898 NextStackOffset = alignTo(NextStackOffset, StackAlignment); 2899 SDValue NextStackOffsetVal = DAG.getIntPtrConstant(NextStackOffset, DL, true); 2900 2901 if (!IsTailCall) 2902 Chain = DAG.getCALLSEQ_START(Chain, NextStackOffset, 0, DL); 2903 2904 SDValue StackPtr = 2905 DAG.getCopyFromReg(Chain, DL, ABI.IsN64() ? Mips::SP_64 : Mips::SP, 2906 getPointerTy(DAG.getDataLayout())); 2907 2908 std::deque< std::pair<unsigned, SDValue> > RegsToPass; 2909 SmallVector<SDValue, 8> MemOpChains; 2910 2911 CCInfo.rewindByValRegsInfo(); 2912 2913 // Walk the register/memloc assignments, inserting copies/loads. 2914 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { 2915 SDValue Arg = OutVals[i]; 2916 CCValAssign &VA = ArgLocs[i]; 2917 MVT ValVT = VA.getValVT(), LocVT = VA.getLocVT(); 2918 ISD::ArgFlagsTy Flags = Outs[i].Flags; 2919 bool UseUpperBits = false; 2920 2921 // ByVal Arg. 2922 if (Flags.isByVal()) { 2923 unsigned FirstByValReg, LastByValReg; 2924 unsigned ByValIdx = CCInfo.getInRegsParamsProcessed(); 2925 CCInfo.getInRegsParamInfo(ByValIdx, FirstByValReg, LastByValReg); 2926 2927 assert(Flags.getByValSize() && 2928 "ByVal args of size 0 should have been ignored by front-end."); 2929 assert(ByValIdx < CCInfo.getInRegsParamsCount()); 2930 assert(!IsTailCall && 2931 "Do not tail-call optimize if there is a byval argument."); 2932 passByValArg(Chain, DL, RegsToPass, MemOpChains, StackPtr, MFI, DAG, Arg, 2933 FirstByValReg, LastByValReg, Flags, Subtarget.isLittle(), 2934 VA); 2935 CCInfo.nextInRegsParam(); 2936 continue; 2937 } 2938 2939 // Promote the value if needed. 2940 switch (VA.getLocInfo()) { 2941 default: 2942 llvm_unreachable("Unknown loc info!"); 2943 case CCValAssign::Full: 2944 if (VA.isRegLoc()) { 2945 if ((ValVT == MVT::f32 && LocVT == MVT::i32) || 2946 (ValVT == MVT::f64 && LocVT == MVT::i64) || 2947 (ValVT == MVT::i64 && LocVT == MVT::f64)) 2948 Arg = DAG.getNode(ISD::BITCAST, DL, LocVT, Arg); 2949 else if (ValVT == MVT::f64 && LocVT == MVT::i32) { 2950 SDValue Lo = DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32, 2951 Arg, DAG.getConstant(0, DL, MVT::i32)); 2952 SDValue Hi = DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32, 2953 Arg, DAG.getConstant(1, DL, MVT::i32)); 2954 if (!Subtarget.isLittle()) 2955 std::swap(Lo, Hi); 2956 unsigned LocRegLo = VA.getLocReg(); 2957 unsigned LocRegHigh = getNextIntArgReg(LocRegLo); 2958 RegsToPass.push_back(std::make_pair(LocRegLo, Lo)); 2959 RegsToPass.push_back(std::make_pair(LocRegHigh, Hi)); 2960 continue; 2961 } 2962 } 2963 break; 2964 case CCValAssign::BCvt: 2965 Arg = DAG.getNode(ISD::BITCAST, DL, LocVT, Arg); 2966 break; 2967 case CCValAssign::SExtUpper: 2968 UseUpperBits = true; 2969 LLVM_FALLTHROUGH; 2970 case CCValAssign::SExt: 2971 Arg = DAG.getNode(ISD::SIGN_EXTEND, DL, LocVT, Arg); 2972 break; 2973 case CCValAssign::ZExtUpper: 2974 UseUpperBits = true; 2975 LLVM_FALLTHROUGH; 2976 case CCValAssign::ZExt: 2977 Arg = DAG.getNode(ISD::ZERO_EXTEND, DL, LocVT, Arg); 2978 break; 2979 case CCValAssign::AExtUpper: 2980 UseUpperBits = true; 2981 LLVM_FALLTHROUGH; 2982 case CCValAssign::AExt: 2983 Arg = DAG.getNode(ISD::ANY_EXTEND, DL, LocVT, Arg); 2984 break; 2985 } 2986 2987 if (UseUpperBits) { 2988 unsigned ValSizeInBits = Outs[i].ArgVT.getSizeInBits(); 2989 unsigned LocSizeInBits = VA.getLocVT().getSizeInBits(); 2990 Arg = DAG.getNode( 2991 ISD::SHL, DL, VA.getLocVT(), Arg, 2992 DAG.getConstant(LocSizeInBits - ValSizeInBits, DL, VA.getLocVT())); 2993 } 2994 2995 // Arguments that can be passed on register must be kept at 2996 // RegsToPass vector 2997 if (VA.isRegLoc()) { 2998 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg)); 2999 continue; 3000 } 3001 3002 // Register can't get to this point... 3003 assert(VA.isMemLoc()); 3004 3005 // emit ISD::STORE whichs stores the 3006 // parameter value to a stack Location 3007 MemOpChains.push_back(passArgOnStack(StackPtr, VA.getLocMemOffset(), 3008 Chain, Arg, DL, IsTailCall, DAG)); 3009 } 3010 3011 // Transform all store nodes into one single node because all store 3012 // nodes are independent of each other. 3013 if (!MemOpChains.empty()) 3014 Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, MemOpChains); 3015 3016 // If the callee is a GlobalAddress/ExternalSymbol node (quite common, every 3017 // direct call is) turn it into a TargetGlobalAddress/TargetExternalSymbol 3018 // node so that legalize doesn't hack it. 3019 3020 SDValue CalleeLo; 3021 EVT Ty = Callee.getValueType(); 3022 bool GlobalOrExternal = false, IsCallReloc = false; 3023 3024 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) { 3025 if (IsPIC) { 3026 const GlobalValue *Val = G->getGlobal(); 3027 InternalLinkage = Val->hasInternalLinkage(); 3028 3029 if (InternalLinkage) 3030 Callee = getAddrLocal(G, DL, Ty, DAG, ABI.IsN32() || ABI.IsN64()); 3031 else if (LargeGOT) { 3032 Callee = getAddrGlobalLargeGOT(G, DL, Ty, DAG, MipsII::MO_CALL_HI16, 3033 MipsII::MO_CALL_LO16, Chain, 3034 FuncInfo->callPtrInfo(Val)); 3035 IsCallReloc = true; 3036 } else { 3037 Callee = getAddrGlobal(G, DL, Ty, DAG, MipsII::MO_GOT_CALL, Chain, 3038 FuncInfo->callPtrInfo(Val)); 3039 IsCallReloc = true; 3040 } 3041 } else 3042 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), DL, 3043 getPointerTy(DAG.getDataLayout()), 0, 3044 MipsII::MO_NO_FLAG); 3045 GlobalOrExternal = true; 3046 } 3047 else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) { 3048 const char *Sym = S->getSymbol(); 3049 3050 if (!IsPIC) // static 3051 Callee = DAG.getTargetExternalSymbol( 3052 Sym, getPointerTy(DAG.getDataLayout()), MipsII::MO_NO_FLAG); 3053 else if (LargeGOT) { 3054 Callee = getAddrGlobalLargeGOT(S, DL, Ty, DAG, MipsII::MO_CALL_HI16, 3055 MipsII::MO_CALL_LO16, Chain, 3056 FuncInfo->callPtrInfo(Sym)); 3057 IsCallReloc = true; 3058 } else { // PIC 3059 Callee = getAddrGlobal(S, DL, Ty, DAG, MipsII::MO_GOT_CALL, Chain, 3060 FuncInfo->callPtrInfo(Sym)); 3061 IsCallReloc = true; 3062 } 3063 3064 GlobalOrExternal = true; 3065 } 3066 3067 SmallVector<SDValue, 8> Ops(1, Chain); 3068 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue); 3069 3070 getOpndList(Ops, RegsToPass, IsPIC, GlobalOrExternal, InternalLinkage, 3071 IsCallReloc, CLI, Callee, Chain); 3072 3073 if (IsTailCall) { 3074 MF.getFrameInfo().setHasTailCall(); 3075 return DAG.getNode(MipsISD::TailCall, DL, MVT::Other, Ops); 3076 } 3077 3078 Chain = DAG.getNode(MipsISD::JmpLink, DL, NodeTys, Ops); 3079 SDValue InFlag = Chain.getValue(1); 3080 3081 // Create the CALLSEQ_END node. 3082 Chain = DAG.getCALLSEQ_END(Chain, NextStackOffsetVal, 3083 DAG.getIntPtrConstant(0, DL, true), InFlag, DL); 3084 InFlag = Chain.getValue(1); 3085 3086 // Handle result values, copying them out of physregs into vregs that we 3087 // return. 3088 return LowerCallResult(Chain, InFlag, CallConv, IsVarArg, Ins, DL, DAG, 3089 InVals, CLI); 3090 } 3091 3092 /// LowerCallResult - Lower the result values of a call into the 3093 /// appropriate copies out of appropriate physical registers. 3094 SDValue MipsTargetLowering::LowerCallResult( 3095 SDValue Chain, SDValue InFlag, CallingConv::ID CallConv, bool IsVarArg, 3096 const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &DL, 3097 SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals, 3098 TargetLowering::CallLoweringInfo &CLI) const { 3099 // Assign locations to each value returned by this call. 3100 SmallVector<CCValAssign, 16> RVLocs; 3101 MipsCCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), RVLocs, 3102 *DAG.getContext()); 3103 3104 const ExternalSymbolSDNode *ES = 3105 dyn_cast_or_null<const ExternalSymbolSDNode>(CLI.Callee.getNode()); 3106 CCInfo.AnalyzeCallResult(Ins, RetCC_Mips, CLI.RetTy, 3107 ES ? ES->getSymbol() : nullptr); 3108 3109 // Copy all of the result registers out of their specified physreg. 3110 for (unsigned i = 0; i != RVLocs.size(); ++i) { 3111 CCValAssign &VA = RVLocs[i]; 3112 assert(VA.isRegLoc() && "Can only return in registers!"); 3113 3114 SDValue Val = DAG.getCopyFromReg(Chain, DL, RVLocs[i].getLocReg(), 3115 RVLocs[i].getLocVT(), InFlag); 3116 Chain = Val.getValue(1); 3117 InFlag = Val.getValue(2); 3118 3119 if (VA.isUpperBitsInLoc()) { 3120 unsigned ValSizeInBits = Ins[i].ArgVT.getSizeInBits(); 3121 unsigned LocSizeInBits = VA.getLocVT().getSizeInBits(); 3122 unsigned Shift = 3123 VA.getLocInfo() == CCValAssign::ZExtUpper ? ISD::SRL : ISD::SRA; 3124 Val = DAG.getNode( 3125 Shift, DL, VA.getLocVT(), Val, 3126 DAG.getConstant(LocSizeInBits - ValSizeInBits, DL, VA.getLocVT())); 3127 } 3128 3129 switch (VA.getLocInfo()) { 3130 default: 3131 llvm_unreachable("Unknown loc info!"); 3132 case CCValAssign::Full: 3133 break; 3134 case CCValAssign::BCvt: 3135 Val = DAG.getNode(ISD::BITCAST, DL, VA.getValVT(), Val); 3136 break; 3137 case CCValAssign::AExt: 3138 case CCValAssign::AExtUpper: 3139 Val = DAG.getNode(ISD::TRUNCATE, DL, VA.getValVT(), Val); 3140 break; 3141 case CCValAssign::ZExt: 3142 case CCValAssign::ZExtUpper: 3143 Val = DAG.getNode(ISD::AssertZext, DL, VA.getLocVT(), Val, 3144 DAG.getValueType(VA.getValVT())); 3145 Val = DAG.getNode(ISD::TRUNCATE, DL, VA.getValVT(), Val); 3146 break; 3147 case CCValAssign::SExt: 3148 case CCValAssign::SExtUpper: 3149 Val = DAG.getNode(ISD::AssertSext, DL, VA.getLocVT(), Val, 3150 DAG.getValueType(VA.getValVT())); 3151 Val = DAG.getNode(ISD::TRUNCATE, DL, VA.getValVT(), Val); 3152 break; 3153 } 3154 3155 InVals.push_back(Val); 3156 } 3157 3158 return Chain; 3159 } 3160 3161 static SDValue UnpackFromArgumentSlot(SDValue Val, const CCValAssign &VA, 3162 EVT ArgVT, const SDLoc &DL, 3163 SelectionDAG &DAG) { 3164 MVT LocVT = VA.getLocVT(); 3165 EVT ValVT = VA.getValVT(); 3166 3167 // Shift into the upper bits if necessary. 3168 switch (VA.getLocInfo()) { 3169 default: 3170 break; 3171 case CCValAssign::AExtUpper: 3172 case CCValAssign::SExtUpper: 3173 case CCValAssign::ZExtUpper: { 3174 unsigned ValSizeInBits = ArgVT.getSizeInBits(); 3175 unsigned LocSizeInBits = VA.getLocVT().getSizeInBits(); 3176 unsigned Opcode = 3177 VA.getLocInfo() == CCValAssign::ZExtUpper ? ISD::SRL : ISD::SRA; 3178 Val = DAG.getNode( 3179 Opcode, DL, VA.getLocVT(), Val, 3180 DAG.getConstant(LocSizeInBits - ValSizeInBits, DL, VA.getLocVT())); 3181 break; 3182 } 3183 } 3184 3185 // If this is an value smaller than the argument slot size (32-bit for O32, 3186 // 64-bit for N32/N64), it has been promoted in some way to the argument slot 3187 // size. Extract the value and insert any appropriate assertions regarding 3188 // sign/zero extension. 3189 switch (VA.getLocInfo()) { 3190 default: 3191 llvm_unreachable("Unknown loc info!"); 3192 case CCValAssign::Full: 3193 break; 3194 case CCValAssign::AExtUpper: 3195 case CCValAssign::AExt: 3196 Val = DAG.getNode(ISD::TRUNCATE, DL, ValVT, Val); 3197 break; 3198 case CCValAssign::SExtUpper: 3199 case CCValAssign::SExt: 3200 Val = DAG.getNode(ISD::AssertSext, DL, LocVT, Val, DAG.getValueType(ValVT)); 3201 Val = DAG.getNode(ISD::TRUNCATE, DL, ValVT, Val); 3202 break; 3203 case CCValAssign::ZExtUpper: 3204 case CCValAssign::ZExt: 3205 Val = DAG.getNode(ISD::AssertZext, DL, LocVT, Val, DAG.getValueType(ValVT)); 3206 Val = DAG.getNode(ISD::TRUNCATE, DL, ValVT, Val); 3207 break; 3208 case CCValAssign::BCvt: 3209 Val = DAG.getNode(ISD::BITCAST, DL, ValVT, Val); 3210 break; 3211 } 3212 3213 return Val; 3214 } 3215 3216 //===----------------------------------------------------------------------===// 3217 // Formal Arguments Calling Convention Implementation 3218 //===----------------------------------------------------------------------===// 3219 /// LowerFormalArguments - transform physical registers into virtual registers 3220 /// and generate load operations for arguments places on the stack. 3221 SDValue MipsTargetLowering::LowerFormalArguments( 3222 SDValue Chain, CallingConv::ID CallConv, bool IsVarArg, 3223 const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &DL, 3224 SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const { 3225 MachineFunction &MF = DAG.getMachineFunction(); 3226 MachineFrameInfo &MFI = MF.getFrameInfo(); 3227 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>(); 3228 3229 MipsFI->setVarArgsFrameIndex(0); 3230 3231 // Used with vargs to acumulate store chains. 3232 std::vector<SDValue> OutChains; 3233 3234 // Assign locations to all of the incoming arguments. 3235 SmallVector<CCValAssign, 16> ArgLocs; 3236 MipsCCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), ArgLocs, 3237 *DAG.getContext()); 3238 CCInfo.AllocateStack(ABI.GetCalleeAllocdArgSizeInBytes(CallConv), 1); 3239 const Function *Func = DAG.getMachineFunction().getFunction(); 3240 Function::const_arg_iterator FuncArg = Func->arg_begin(); 3241 3242 if (Func->hasFnAttribute("interrupt") && !Func->arg_empty()) 3243 report_fatal_error( 3244 "Functions with the interrupt attribute cannot have arguments!"); 3245 3246 CCInfo.AnalyzeFormalArguments(Ins, CC_Mips_FixedArg); 3247 MipsFI->setFormalArgInfo(CCInfo.getNextStackOffset(), 3248 CCInfo.getInRegsParamsCount() > 0); 3249 3250 unsigned CurArgIdx = 0; 3251 CCInfo.rewindByValRegsInfo(); 3252 3253 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { 3254 CCValAssign &VA = ArgLocs[i]; 3255 if (Ins[i].isOrigArg()) { 3256 std::advance(FuncArg, Ins[i].getOrigArgIndex() - CurArgIdx); 3257 CurArgIdx = Ins[i].getOrigArgIndex(); 3258 } 3259 EVT ValVT = VA.getValVT(); 3260 ISD::ArgFlagsTy Flags = Ins[i].Flags; 3261 bool IsRegLoc = VA.isRegLoc(); 3262 3263 if (Flags.isByVal()) { 3264 assert(Ins[i].isOrigArg() && "Byval arguments cannot be implicit"); 3265 unsigned FirstByValReg, LastByValReg; 3266 unsigned ByValIdx = CCInfo.getInRegsParamsProcessed(); 3267 CCInfo.getInRegsParamInfo(ByValIdx, FirstByValReg, LastByValReg); 3268 3269 assert(Flags.getByValSize() && 3270 "ByVal args of size 0 should have been ignored by front-end."); 3271 assert(ByValIdx < CCInfo.getInRegsParamsCount()); 3272 copyByValRegs(Chain, DL, OutChains, DAG, Flags, InVals, &*FuncArg, 3273 FirstByValReg, LastByValReg, VA, CCInfo); 3274 CCInfo.nextInRegsParam(); 3275 continue; 3276 } 3277 3278 // Arguments stored on registers 3279 if (IsRegLoc) { 3280 MVT RegVT = VA.getLocVT(); 3281 unsigned ArgReg = VA.getLocReg(); 3282 const TargetRegisterClass *RC = getRegClassFor(RegVT); 3283 3284 // Transform the arguments stored on 3285 // physical registers into virtual ones 3286 unsigned Reg = addLiveIn(DAG.getMachineFunction(), ArgReg, RC); 3287 SDValue ArgValue = DAG.getCopyFromReg(Chain, DL, Reg, RegVT); 3288 3289 ArgValue = UnpackFromArgumentSlot(ArgValue, VA, Ins[i].ArgVT, DL, DAG); 3290 3291 // Handle floating point arguments passed in integer registers and 3292 // long double arguments passed in floating point registers. 3293 if ((RegVT == MVT::i32 && ValVT == MVT::f32) || 3294 (RegVT == MVT::i64 && ValVT == MVT::f64) || 3295 (RegVT == MVT::f64 && ValVT == MVT::i64)) 3296 ArgValue = DAG.getNode(ISD::BITCAST, DL, ValVT, ArgValue); 3297 else if (ABI.IsO32() && RegVT == MVT::i32 && 3298 ValVT == MVT::f64) { 3299 unsigned Reg2 = addLiveIn(DAG.getMachineFunction(), 3300 getNextIntArgReg(ArgReg), RC); 3301 SDValue ArgValue2 = DAG.getCopyFromReg(Chain, DL, Reg2, RegVT); 3302 if (!Subtarget.isLittle()) 3303 std::swap(ArgValue, ArgValue2); 3304 ArgValue = DAG.getNode(MipsISD::BuildPairF64, DL, MVT::f64, 3305 ArgValue, ArgValue2); 3306 } 3307 3308 InVals.push_back(ArgValue); 3309 } else { // VA.isRegLoc() 3310 MVT LocVT = VA.getLocVT(); 3311 3312 if (ABI.IsO32()) { 3313 // We ought to be able to use LocVT directly but O32 sets it to i32 3314 // when allocating floating point values to integer registers. 3315 // This shouldn't influence how we load the value into registers unless 3316 // we are targeting softfloat. 3317 if (VA.getValVT().isFloatingPoint() && !Subtarget.useSoftFloat()) 3318 LocVT = VA.getValVT(); 3319 } 3320 3321 // sanity check 3322 assert(VA.isMemLoc()); 3323 3324 // The stack pointer offset is relative to the caller stack frame. 3325 int FI = MFI.CreateFixedObject(LocVT.getSizeInBits() / 8, 3326 VA.getLocMemOffset(), true); 3327 3328 // Create load nodes to retrieve arguments from the stack 3329 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy(DAG.getDataLayout())); 3330 SDValue ArgValue = DAG.getLoad( 3331 LocVT, DL, Chain, FIN, 3332 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), FI)); 3333 OutChains.push_back(ArgValue.getValue(1)); 3334 3335 ArgValue = UnpackFromArgumentSlot(ArgValue, VA, Ins[i].ArgVT, DL, DAG); 3336 3337 InVals.push_back(ArgValue); 3338 } 3339 } 3340 3341 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { 3342 // The mips ABIs for returning structs by value requires that we copy 3343 // the sret argument into $v0 for the return. Save the argument into 3344 // a virtual register so that we can access it from the return points. 3345 if (Ins[i].Flags.isSRet()) { 3346 unsigned Reg = MipsFI->getSRetReturnReg(); 3347 if (!Reg) { 3348 Reg = MF.getRegInfo().createVirtualRegister( 3349 getRegClassFor(ABI.IsN64() ? MVT::i64 : MVT::i32)); 3350 MipsFI->setSRetReturnReg(Reg); 3351 } 3352 SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), DL, Reg, InVals[i]); 3353 Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, Copy, Chain); 3354 break; 3355 } 3356 } 3357 3358 if (IsVarArg) 3359 writeVarArgRegs(OutChains, Chain, DL, DAG, CCInfo); 3360 3361 // All stores are grouped in one node to allow the matching between 3362 // the size of Ins and InVals. This only happens when on varg functions 3363 if (!OutChains.empty()) { 3364 OutChains.push_back(Chain); 3365 Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, OutChains); 3366 } 3367 3368 return Chain; 3369 } 3370 3371 //===----------------------------------------------------------------------===// 3372 // Return Value Calling Convention Implementation 3373 //===----------------------------------------------------------------------===// 3374 3375 bool 3376 MipsTargetLowering::CanLowerReturn(CallingConv::ID CallConv, 3377 MachineFunction &MF, bool IsVarArg, 3378 const SmallVectorImpl<ISD::OutputArg> &Outs, 3379 LLVMContext &Context) const { 3380 SmallVector<CCValAssign, 16> RVLocs; 3381 MipsCCState CCInfo(CallConv, IsVarArg, MF, RVLocs, Context); 3382 return CCInfo.CheckReturn(Outs, RetCC_Mips); 3383 } 3384 3385 bool 3386 MipsTargetLowering::shouldSignExtendTypeInLibCall(EVT Type, bool IsSigned) const { 3387 if (Subtarget.hasMips3() && Subtarget.useSoftFloat()) { 3388 if (Type == MVT::i32) 3389 return true; 3390 } 3391 return IsSigned; 3392 } 3393 3394 SDValue 3395 MipsTargetLowering::LowerInterruptReturn(SmallVectorImpl<SDValue> &RetOps, 3396 const SDLoc &DL, 3397 SelectionDAG &DAG) const { 3398 3399 MachineFunction &MF = DAG.getMachineFunction(); 3400 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>(); 3401 3402 MipsFI->setISR(); 3403 3404 return DAG.getNode(MipsISD::ERet, DL, MVT::Other, RetOps); 3405 } 3406 3407 SDValue 3408 MipsTargetLowering::LowerReturn(SDValue Chain, CallingConv::ID CallConv, 3409 bool IsVarArg, 3410 const SmallVectorImpl<ISD::OutputArg> &Outs, 3411 const SmallVectorImpl<SDValue> &OutVals, 3412 const SDLoc &DL, SelectionDAG &DAG) const { 3413 // CCValAssign - represent the assignment of 3414 // the return value to a location 3415 SmallVector<CCValAssign, 16> RVLocs; 3416 MachineFunction &MF = DAG.getMachineFunction(); 3417 3418 // CCState - Info about the registers and stack slot. 3419 MipsCCState CCInfo(CallConv, IsVarArg, MF, RVLocs, *DAG.getContext()); 3420 3421 // Analyze return values. 3422 CCInfo.AnalyzeReturn(Outs, RetCC_Mips); 3423 3424 SDValue Flag; 3425 SmallVector<SDValue, 4> RetOps(1, Chain); 3426 3427 // Copy the result values into the output registers. 3428 for (unsigned i = 0; i != RVLocs.size(); ++i) { 3429 SDValue Val = OutVals[i]; 3430 CCValAssign &VA = RVLocs[i]; 3431 assert(VA.isRegLoc() && "Can only return in registers!"); 3432 bool UseUpperBits = false; 3433 3434 switch (VA.getLocInfo()) { 3435 default: 3436 llvm_unreachable("Unknown loc info!"); 3437 case CCValAssign::Full: 3438 break; 3439 case CCValAssign::BCvt: 3440 Val = DAG.getNode(ISD::BITCAST, DL, VA.getLocVT(), Val); 3441 break; 3442 case CCValAssign::AExtUpper: 3443 UseUpperBits = true; 3444 LLVM_FALLTHROUGH; 3445 case CCValAssign::AExt: 3446 Val = DAG.getNode(ISD::ANY_EXTEND, DL, VA.getLocVT(), Val); 3447 break; 3448 case CCValAssign::ZExtUpper: 3449 UseUpperBits = true; 3450 LLVM_FALLTHROUGH; 3451 case CCValAssign::ZExt: 3452 Val = DAG.getNode(ISD::ZERO_EXTEND, DL, VA.getLocVT(), Val); 3453 break; 3454 case CCValAssign::SExtUpper: 3455 UseUpperBits = true; 3456 LLVM_FALLTHROUGH; 3457 case CCValAssign::SExt: 3458 Val = DAG.getNode(ISD::SIGN_EXTEND, DL, VA.getLocVT(), Val); 3459 break; 3460 } 3461 3462 if (UseUpperBits) { 3463 unsigned ValSizeInBits = Outs[i].ArgVT.getSizeInBits(); 3464 unsigned LocSizeInBits = VA.getLocVT().getSizeInBits(); 3465 Val = DAG.getNode( 3466 ISD::SHL, DL, VA.getLocVT(), Val, 3467 DAG.getConstant(LocSizeInBits - ValSizeInBits, DL, VA.getLocVT())); 3468 } 3469 3470 Chain = DAG.getCopyToReg(Chain, DL, VA.getLocReg(), Val, Flag); 3471 3472 // Guarantee that all emitted copies are stuck together with flags. 3473 Flag = Chain.getValue(1); 3474 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT())); 3475 } 3476 3477 // The mips ABIs for returning structs by value requires that we copy 3478 // the sret argument into $v0 for the return. We saved the argument into 3479 // a virtual register in the entry block, so now we copy the value out 3480 // and into $v0. 3481 if (MF.getFunction()->hasStructRetAttr()) { 3482 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>(); 3483 unsigned Reg = MipsFI->getSRetReturnReg(); 3484 3485 if (!Reg) 3486 llvm_unreachable("sret virtual register not created in the entry block"); 3487 SDValue Val = 3488 DAG.getCopyFromReg(Chain, DL, Reg, getPointerTy(DAG.getDataLayout())); 3489 unsigned V0 = ABI.IsN64() ? Mips::V0_64 : Mips::V0; 3490 3491 Chain = DAG.getCopyToReg(Chain, DL, V0, Val, Flag); 3492 Flag = Chain.getValue(1); 3493 RetOps.push_back(DAG.getRegister(V0, getPointerTy(DAG.getDataLayout()))); 3494 } 3495 3496 RetOps[0] = Chain; // Update chain. 3497 3498 // Add the flag if we have it. 3499 if (Flag.getNode()) 3500 RetOps.push_back(Flag); 3501 3502 // ISRs must use "eret". 3503 if (DAG.getMachineFunction().getFunction()->hasFnAttribute("interrupt")) 3504 return LowerInterruptReturn(RetOps, DL, DAG); 3505 3506 // Standard return on Mips is a "jr $ra" 3507 return DAG.getNode(MipsISD::Ret, DL, MVT::Other, RetOps); 3508 } 3509 3510 //===----------------------------------------------------------------------===// 3511 // Mips Inline Assembly Support 3512 //===----------------------------------------------------------------------===// 3513 3514 /// getConstraintType - Given a constraint letter, return the type of 3515 /// constraint it is for this target. 3516 MipsTargetLowering::ConstraintType 3517 MipsTargetLowering::getConstraintType(StringRef Constraint) const { 3518 // Mips specific constraints 3519 // GCC config/mips/constraints.md 3520 // 3521 // 'd' : An address register. Equivalent to r 3522 // unless generating MIPS16 code. 3523 // 'y' : Equivalent to r; retained for 3524 // backwards compatibility. 3525 // 'c' : A register suitable for use in an indirect 3526 // jump. This will always be $25 for -mabicalls. 3527 // 'l' : The lo register. 1 word storage. 3528 // 'x' : The hilo register pair. Double word storage. 3529 if (Constraint.size() == 1) { 3530 switch (Constraint[0]) { 3531 default : break; 3532 case 'd': 3533 case 'y': 3534 case 'f': 3535 case 'c': 3536 case 'l': 3537 case 'x': 3538 return C_RegisterClass; 3539 case 'R': 3540 return C_Memory; 3541 } 3542 } 3543 3544 if (Constraint == "ZC") 3545 return C_Memory; 3546 3547 return TargetLowering::getConstraintType(Constraint); 3548 } 3549 3550 /// Examine constraint type and operand type and determine a weight value. 3551 /// This object must already have been set up with the operand type 3552 /// and the current alternative constraint selected. 3553 TargetLowering::ConstraintWeight 3554 MipsTargetLowering::getSingleConstraintMatchWeight( 3555 AsmOperandInfo &info, const char *constraint) const { 3556 ConstraintWeight weight = CW_Invalid; 3557 Value *CallOperandVal = info.CallOperandVal; 3558 // If we don't have a value, we can't do a match, 3559 // but allow it at the lowest weight. 3560 if (!CallOperandVal) 3561 return CW_Default; 3562 Type *type = CallOperandVal->getType(); 3563 // Look at the constraint type. 3564 switch (*constraint) { 3565 default: 3566 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint); 3567 break; 3568 case 'd': 3569 case 'y': 3570 if (type->isIntegerTy()) 3571 weight = CW_Register; 3572 break; 3573 case 'f': // FPU or MSA register 3574 if (Subtarget.hasMSA() && type->isVectorTy() && 3575 cast<VectorType>(type)->getBitWidth() == 128) 3576 weight = CW_Register; 3577 else if (type->isFloatTy()) 3578 weight = CW_Register; 3579 break; 3580 case 'c': // $25 for indirect jumps 3581 case 'l': // lo register 3582 case 'x': // hilo register pair 3583 if (type->isIntegerTy()) 3584 weight = CW_SpecificReg; 3585 break; 3586 case 'I': // signed 16 bit immediate 3587 case 'J': // integer zero 3588 case 'K': // unsigned 16 bit immediate 3589 case 'L': // signed 32 bit immediate where lower 16 bits are 0 3590 case 'N': // immediate in the range of -65535 to -1 (inclusive) 3591 case 'O': // signed 15 bit immediate (+- 16383) 3592 case 'P': // immediate in the range of 65535 to 1 (inclusive) 3593 if (isa<ConstantInt>(CallOperandVal)) 3594 weight = CW_Constant; 3595 break; 3596 case 'R': 3597 weight = CW_Memory; 3598 break; 3599 } 3600 return weight; 3601 } 3602 3603 /// This is a helper function to parse a physical register string and split it 3604 /// into non-numeric and numeric parts (Prefix and Reg). The first boolean flag 3605 /// that is returned indicates whether parsing was successful. The second flag 3606 /// is true if the numeric part exists. 3607 static std::pair<bool, bool> parsePhysicalReg(StringRef C, StringRef &Prefix, 3608 unsigned long long &Reg) { 3609 if (C.front() != '{' || C.back() != '}') 3610 return std::make_pair(false, false); 3611 3612 // Search for the first numeric character. 3613 StringRef::const_iterator I, B = C.begin() + 1, E = C.end() - 1; 3614 I = std::find_if(B, E, isdigit); 3615 3616 Prefix = StringRef(B, I - B); 3617 3618 // The second flag is set to false if no numeric characters were found. 3619 if (I == E) 3620 return std::make_pair(true, false); 3621 3622 // Parse the numeric characters. 3623 return std::make_pair(!getAsUnsignedInteger(StringRef(I, E - I), 10, Reg), 3624 true); 3625 } 3626 3627 std::pair<unsigned, const TargetRegisterClass *> MipsTargetLowering:: 3628 parseRegForInlineAsmConstraint(StringRef C, MVT VT) const { 3629 const TargetRegisterInfo *TRI = 3630 Subtarget.getRegisterInfo(); 3631 const TargetRegisterClass *RC; 3632 StringRef Prefix; 3633 unsigned long long Reg; 3634 3635 std::pair<bool, bool> R = parsePhysicalReg(C, Prefix, Reg); 3636 3637 if (!R.first) 3638 return std::make_pair(0U, nullptr); 3639 3640 if ((Prefix == "hi" || Prefix == "lo")) { // Parse hi/lo. 3641 // No numeric characters follow "hi" or "lo". 3642 if (R.second) 3643 return std::make_pair(0U, nullptr); 3644 3645 RC = TRI->getRegClass(Prefix == "hi" ? 3646 Mips::HI32RegClassID : Mips::LO32RegClassID); 3647 return std::make_pair(*(RC->begin()), RC); 3648 } else if (Prefix.startswith("$msa")) { 3649 // Parse $msa(ir|csr|access|save|modify|request|map|unmap) 3650 3651 // No numeric characters follow the name. 3652 if (R.second) 3653 return std::make_pair(0U, nullptr); 3654 3655 Reg = StringSwitch<unsigned long long>(Prefix) 3656 .Case("$msair", Mips::MSAIR) 3657 .Case("$msacsr", Mips::MSACSR) 3658 .Case("$msaaccess", Mips::MSAAccess) 3659 .Case("$msasave", Mips::MSASave) 3660 .Case("$msamodify", Mips::MSAModify) 3661 .Case("$msarequest", Mips::MSARequest) 3662 .Case("$msamap", Mips::MSAMap) 3663 .Case("$msaunmap", Mips::MSAUnmap) 3664 .Default(0); 3665 3666 if (!Reg) 3667 return std::make_pair(0U, nullptr); 3668 3669 RC = TRI->getRegClass(Mips::MSACtrlRegClassID); 3670 return std::make_pair(Reg, RC); 3671 } 3672 3673 if (!R.second) 3674 return std::make_pair(0U, nullptr); 3675 3676 if (Prefix == "$f") { // Parse $f0-$f31. 3677 // If the size of FP registers is 64-bit or Reg is an even number, select 3678 // the 64-bit register class. Otherwise, select the 32-bit register class. 3679 if (VT == MVT::Other) 3680 VT = (Subtarget.isFP64bit() || !(Reg % 2)) ? MVT::f64 : MVT::f32; 3681 3682 RC = getRegClassFor(VT); 3683 3684 if (RC == &Mips::AFGR64RegClass) { 3685 assert(Reg % 2 == 0); 3686 Reg >>= 1; 3687 } 3688 } else if (Prefix == "$fcc") // Parse $fcc0-$fcc7. 3689 RC = TRI->getRegClass(Mips::FCCRegClassID); 3690 else if (Prefix == "$w") { // Parse $w0-$w31. 3691 RC = getRegClassFor((VT == MVT::Other) ? MVT::v16i8 : VT); 3692 } else { // Parse $0-$31. 3693 assert(Prefix == "$"); 3694 RC = getRegClassFor((VT == MVT::Other) ? MVT::i32 : VT); 3695 } 3696 3697 assert(Reg < RC->getNumRegs()); 3698 return std::make_pair(*(RC->begin() + Reg), RC); 3699 } 3700 3701 /// Given a register class constraint, like 'r', if this corresponds directly 3702 /// to an LLVM register class, return a register of 0 and the register class 3703 /// pointer. 3704 std::pair<unsigned, const TargetRegisterClass *> 3705 MipsTargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, 3706 StringRef Constraint, 3707 MVT VT) const { 3708 if (Constraint.size() == 1) { 3709 switch (Constraint[0]) { 3710 case 'd': // Address register. Same as 'r' unless generating MIPS16 code. 3711 case 'y': // Same as 'r'. Exists for compatibility. 3712 case 'r': 3713 if (VT == MVT::i32 || VT == MVT::i16 || VT == MVT::i8) { 3714 if (Subtarget.inMips16Mode()) 3715 return std::make_pair(0U, &Mips::CPU16RegsRegClass); 3716 return std::make_pair(0U, &Mips::GPR32RegClass); 3717 } 3718 if (VT == MVT::i64 && !Subtarget.isGP64bit()) 3719 return std::make_pair(0U, &Mips::GPR32RegClass); 3720 if (VT == MVT::i64 && Subtarget.isGP64bit()) 3721 return std::make_pair(0U, &Mips::GPR64RegClass); 3722 // This will generate an error message 3723 return std::make_pair(0U, nullptr); 3724 case 'f': // FPU or MSA register 3725 if (VT == MVT::v16i8) 3726 return std::make_pair(0U, &Mips::MSA128BRegClass); 3727 else if (VT == MVT::v8i16 || VT == MVT::v8f16) 3728 return std::make_pair(0U, &Mips::MSA128HRegClass); 3729 else if (VT == MVT::v4i32 || VT == MVT::v4f32) 3730 return std::make_pair(0U, &Mips::MSA128WRegClass); 3731 else if (VT == MVT::v2i64 || VT == MVT::v2f64) 3732 return std::make_pair(0U, &Mips::MSA128DRegClass); 3733 else if (VT == MVT::f32) 3734 return std::make_pair(0U, &Mips::FGR32RegClass); 3735 else if ((VT == MVT::f64) && (!Subtarget.isSingleFloat())) { 3736 if (Subtarget.isFP64bit()) 3737 return std::make_pair(0U, &Mips::FGR64RegClass); 3738 return std::make_pair(0U, &Mips::AFGR64RegClass); 3739 } 3740 break; 3741 case 'c': // register suitable for indirect jump 3742 if (VT == MVT::i32) 3743 return std::make_pair((unsigned)Mips::T9, &Mips::GPR32RegClass); 3744 assert(VT == MVT::i64 && "Unexpected type."); 3745 return std::make_pair((unsigned)Mips::T9_64, &Mips::GPR64RegClass); 3746 case 'l': // register suitable for indirect jump 3747 if (VT == MVT::i32) 3748 return std::make_pair((unsigned)Mips::LO0, &Mips::LO32RegClass); 3749 return std::make_pair((unsigned)Mips::LO0_64, &Mips::LO64RegClass); 3750 case 'x': // register suitable for indirect jump 3751 // Fixme: Not triggering the use of both hi and low 3752 // This will generate an error message 3753 return std::make_pair(0U, nullptr); 3754 } 3755 } 3756 3757 std::pair<unsigned, const TargetRegisterClass *> R; 3758 R = parseRegForInlineAsmConstraint(Constraint, VT); 3759 3760 if (R.second) 3761 return R; 3762 3763 return TargetLowering::getRegForInlineAsmConstraint(TRI, Constraint, VT); 3764 } 3765 3766 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops 3767 /// vector. If it is invalid, don't add anything to Ops. 3768 void MipsTargetLowering::LowerAsmOperandForConstraint(SDValue Op, 3769 std::string &Constraint, 3770 std::vector<SDValue>&Ops, 3771 SelectionDAG &DAG) const { 3772 SDLoc DL(Op); 3773 SDValue Result; 3774 3775 // Only support length 1 constraints for now. 3776 if (Constraint.length() > 1) return; 3777 3778 char ConstraintLetter = Constraint[0]; 3779 switch (ConstraintLetter) { 3780 default: break; // This will fall through to the generic implementation 3781 case 'I': // Signed 16 bit constant 3782 // If this fails, the parent routine will give an error 3783 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 3784 EVT Type = Op.getValueType(); 3785 int64_t Val = C->getSExtValue(); 3786 if (isInt<16>(Val)) { 3787 Result = DAG.getTargetConstant(Val, DL, Type); 3788 break; 3789 } 3790 } 3791 return; 3792 case 'J': // integer zero 3793 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 3794 EVT Type = Op.getValueType(); 3795 int64_t Val = C->getZExtValue(); 3796 if (Val == 0) { 3797 Result = DAG.getTargetConstant(0, DL, Type); 3798 break; 3799 } 3800 } 3801 return; 3802 case 'K': // unsigned 16 bit immediate 3803 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 3804 EVT Type = Op.getValueType(); 3805 uint64_t Val = (uint64_t)C->getZExtValue(); 3806 if (isUInt<16>(Val)) { 3807 Result = DAG.getTargetConstant(Val, DL, Type); 3808 break; 3809 } 3810 } 3811 return; 3812 case 'L': // signed 32 bit immediate where lower 16 bits are 0 3813 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 3814 EVT Type = Op.getValueType(); 3815 int64_t Val = C->getSExtValue(); 3816 if ((isInt<32>(Val)) && ((Val & 0xffff) == 0)){ 3817 Result = DAG.getTargetConstant(Val, DL, Type); 3818 break; 3819 } 3820 } 3821 return; 3822 case 'N': // immediate in the range of -65535 to -1 (inclusive) 3823 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 3824 EVT Type = Op.getValueType(); 3825 int64_t Val = C->getSExtValue(); 3826 if ((Val >= -65535) && (Val <= -1)) { 3827 Result = DAG.getTargetConstant(Val, DL, Type); 3828 break; 3829 } 3830 } 3831 return; 3832 case 'O': // signed 15 bit immediate 3833 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 3834 EVT Type = Op.getValueType(); 3835 int64_t Val = C->getSExtValue(); 3836 if ((isInt<15>(Val))) { 3837 Result = DAG.getTargetConstant(Val, DL, Type); 3838 break; 3839 } 3840 } 3841 return; 3842 case 'P': // immediate in the range of 1 to 65535 (inclusive) 3843 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 3844 EVT Type = Op.getValueType(); 3845 int64_t Val = C->getSExtValue(); 3846 if ((Val <= 65535) && (Val >= 1)) { 3847 Result = DAG.getTargetConstant(Val, DL, Type); 3848 break; 3849 } 3850 } 3851 return; 3852 } 3853 3854 if (Result.getNode()) { 3855 Ops.push_back(Result); 3856 return; 3857 } 3858 3859 TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG); 3860 } 3861 3862 bool MipsTargetLowering::isLegalAddressingMode(const DataLayout &DL, 3863 const AddrMode &AM, Type *Ty, 3864 unsigned AS) const { 3865 // No global is ever allowed as a base. 3866 if (AM.BaseGV) 3867 return false; 3868 3869 switch (AM.Scale) { 3870 case 0: // "r+i" or just "i", depending on HasBaseReg. 3871 break; 3872 case 1: 3873 if (!AM.HasBaseReg) // allow "r+i". 3874 break; 3875 return false; // disallow "r+r" or "r+r+i". 3876 default: 3877 return false; 3878 } 3879 3880 return true; 3881 } 3882 3883 bool 3884 MipsTargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const { 3885 // The Mips target isn't yet aware of offsets. 3886 return false; 3887 } 3888 3889 EVT MipsTargetLowering::getOptimalMemOpType(uint64_t Size, unsigned DstAlign, 3890 unsigned SrcAlign, 3891 bool IsMemset, bool ZeroMemset, 3892 bool MemcpyStrSrc, 3893 MachineFunction &MF) const { 3894 if (Subtarget.hasMips64()) 3895 return MVT::i64; 3896 3897 return MVT::i32; 3898 } 3899 3900 bool MipsTargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const { 3901 if (VT != MVT::f32 && VT != MVT::f64) 3902 return false; 3903 if (Imm.isNegZero()) 3904 return false; 3905 return Imm.isZero(); 3906 } 3907 3908 unsigned MipsTargetLowering::getJumpTableEncoding() const { 3909 3910 // FIXME: For space reasons this should be: EK_GPRel32BlockAddress. 3911 if (ABI.IsN64() && isPositionIndependent()) 3912 return MachineJumpTableInfo::EK_GPRel64BlockAddress; 3913 3914 return TargetLowering::getJumpTableEncoding(); 3915 } 3916 3917 bool MipsTargetLowering::useSoftFloat() const { 3918 return Subtarget.useSoftFloat(); 3919 } 3920 3921 void MipsTargetLowering::copyByValRegs( 3922 SDValue Chain, const SDLoc &DL, std::vector<SDValue> &OutChains, 3923 SelectionDAG &DAG, const ISD::ArgFlagsTy &Flags, 3924 SmallVectorImpl<SDValue> &InVals, const Argument *FuncArg, 3925 unsigned FirstReg, unsigned LastReg, const CCValAssign &VA, 3926 MipsCCState &State) const { 3927 MachineFunction &MF = DAG.getMachineFunction(); 3928 MachineFrameInfo &MFI = MF.getFrameInfo(); 3929 unsigned GPRSizeInBytes = Subtarget.getGPRSizeInBytes(); 3930 unsigned NumRegs = LastReg - FirstReg; 3931 unsigned RegAreaSize = NumRegs * GPRSizeInBytes; 3932 unsigned FrameObjSize = std::max(Flags.getByValSize(), RegAreaSize); 3933 int FrameObjOffset; 3934 ArrayRef<MCPhysReg> ByValArgRegs = ABI.GetByValArgRegs(); 3935 3936 if (RegAreaSize) 3937 FrameObjOffset = 3938 (int)ABI.GetCalleeAllocdArgSizeInBytes(State.getCallingConv()) - 3939 (int)((ByValArgRegs.size() - FirstReg) * GPRSizeInBytes); 3940 else 3941 FrameObjOffset = VA.getLocMemOffset(); 3942 3943 // Create frame object. 3944 EVT PtrTy = getPointerTy(DAG.getDataLayout()); 3945 int FI = MFI.CreateFixedObject(FrameObjSize, FrameObjOffset, true); 3946 SDValue FIN = DAG.getFrameIndex(FI, PtrTy); 3947 InVals.push_back(FIN); 3948 3949 if (!NumRegs) 3950 return; 3951 3952 // Copy arg registers. 3953 MVT RegTy = MVT::getIntegerVT(GPRSizeInBytes * 8); 3954 const TargetRegisterClass *RC = getRegClassFor(RegTy); 3955 3956 for (unsigned I = 0; I < NumRegs; ++I) { 3957 unsigned ArgReg = ByValArgRegs[FirstReg + I]; 3958 unsigned VReg = addLiveIn(MF, ArgReg, RC); 3959 unsigned Offset = I * GPRSizeInBytes; 3960 SDValue StorePtr = DAG.getNode(ISD::ADD, DL, PtrTy, FIN, 3961 DAG.getConstant(Offset, DL, PtrTy)); 3962 SDValue Store = DAG.getStore(Chain, DL, DAG.getRegister(VReg, RegTy), 3963 StorePtr, MachinePointerInfo(FuncArg, Offset)); 3964 OutChains.push_back(Store); 3965 } 3966 } 3967 3968 // Copy byVal arg to registers and stack. 3969 void MipsTargetLowering::passByValArg( 3970 SDValue Chain, const SDLoc &DL, 3971 std::deque<std::pair<unsigned, SDValue>> &RegsToPass, 3972 SmallVectorImpl<SDValue> &MemOpChains, SDValue StackPtr, 3973 MachineFrameInfo &MFI, SelectionDAG &DAG, SDValue Arg, unsigned FirstReg, 3974 unsigned LastReg, const ISD::ArgFlagsTy &Flags, bool isLittle, 3975 const CCValAssign &VA) const { 3976 unsigned ByValSizeInBytes = Flags.getByValSize(); 3977 unsigned OffsetInBytes = 0; // From beginning of struct 3978 unsigned RegSizeInBytes = Subtarget.getGPRSizeInBytes(); 3979 unsigned Alignment = std::min(Flags.getByValAlign(), RegSizeInBytes); 3980 EVT PtrTy = getPointerTy(DAG.getDataLayout()), 3981 RegTy = MVT::getIntegerVT(RegSizeInBytes * 8); 3982 unsigned NumRegs = LastReg - FirstReg; 3983 3984 if (NumRegs) { 3985 ArrayRef<MCPhysReg> ArgRegs = ABI.GetByValArgRegs(); 3986 bool LeftoverBytes = (NumRegs * RegSizeInBytes > ByValSizeInBytes); 3987 unsigned I = 0; 3988 3989 // Copy words to registers. 3990 for (; I < NumRegs - LeftoverBytes; ++I, OffsetInBytes += RegSizeInBytes) { 3991 SDValue LoadPtr = DAG.getNode(ISD::ADD, DL, PtrTy, Arg, 3992 DAG.getConstant(OffsetInBytes, DL, PtrTy)); 3993 SDValue LoadVal = DAG.getLoad(RegTy, DL, Chain, LoadPtr, 3994 MachinePointerInfo(), Alignment); 3995 MemOpChains.push_back(LoadVal.getValue(1)); 3996 unsigned ArgReg = ArgRegs[FirstReg + I]; 3997 RegsToPass.push_back(std::make_pair(ArgReg, LoadVal)); 3998 } 3999 4000 // Return if the struct has been fully copied. 4001 if (ByValSizeInBytes == OffsetInBytes) 4002 return; 4003 4004 // Copy the remainder of the byval argument with sub-word loads and shifts. 4005 if (LeftoverBytes) { 4006 SDValue Val; 4007 4008 for (unsigned LoadSizeInBytes = RegSizeInBytes / 2, TotalBytesLoaded = 0; 4009 OffsetInBytes < ByValSizeInBytes; LoadSizeInBytes /= 2) { 4010 unsigned RemainingSizeInBytes = ByValSizeInBytes - OffsetInBytes; 4011 4012 if (RemainingSizeInBytes < LoadSizeInBytes) 4013 continue; 4014 4015 // Load subword. 4016 SDValue LoadPtr = DAG.getNode(ISD::ADD, DL, PtrTy, Arg, 4017 DAG.getConstant(OffsetInBytes, DL, 4018 PtrTy)); 4019 SDValue LoadVal = DAG.getExtLoad( 4020 ISD::ZEXTLOAD, DL, RegTy, Chain, LoadPtr, MachinePointerInfo(), 4021 MVT::getIntegerVT(LoadSizeInBytes * 8), Alignment); 4022 MemOpChains.push_back(LoadVal.getValue(1)); 4023 4024 // Shift the loaded value. 4025 unsigned Shamt; 4026 4027 if (isLittle) 4028 Shamt = TotalBytesLoaded * 8; 4029 else 4030 Shamt = (RegSizeInBytes - (TotalBytesLoaded + LoadSizeInBytes)) * 8; 4031 4032 SDValue Shift = DAG.getNode(ISD::SHL, DL, RegTy, LoadVal, 4033 DAG.getConstant(Shamt, DL, MVT::i32)); 4034 4035 if (Val.getNode()) 4036 Val = DAG.getNode(ISD::OR, DL, RegTy, Val, Shift); 4037 else 4038 Val = Shift; 4039 4040 OffsetInBytes += LoadSizeInBytes; 4041 TotalBytesLoaded += LoadSizeInBytes; 4042 Alignment = std::min(Alignment, LoadSizeInBytes); 4043 } 4044 4045 unsigned ArgReg = ArgRegs[FirstReg + I]; 4046 RegsToPass.push_back(std::make_pair(ArgReg, Val)); 4047 return; 4048 } 4049 } 4050 4051 // Copy remainder of byval arg to it with memcpy. 4052 unsigned MemCpySize = ByValSizeInBytes - OffsetInBytes; 4053 SDValue Src = DAG.getNode(ISD::ADD, DL, PtrTy, Arg, 4054 DAG.getConstant(OffsetInBytes, DL, PtrTy)); 4055 SDValue Dst = DAG.getNode(ISD::ADD, DL, PtrTy, StackPtr, 4056 DAG.getIntPtrConstant(VA.getLocMemOffset(), DL)); 4057 Chain = DAG.getMemcpy(Chain, DL, Dst, Src, 4058 DAG.getConstant(MemCpySize, DL, PtrTy), 4059 Alignment, /*isVolatile=*/false, /*AlwaysInline=*/false, 4060 /*isTailCall=*/false, 4061 MachinePointerInfo(), MachinePointerInfo()); 4062 MemOpChains.push_back(Chain); 4063 } 4064 4065 void MipsTargetLowering::writeVarArgRegs(std::vector<SDValue> &OutChains, 4066 SDValue Chain, const SDLoc &DL, 4067 SelectionDAG &DAG, 4068 CCState &State) const { 4069 ArrayRef<MCPhysReg> ArgRegs = ABI.GetVarArgRegs(); 4070 unsigned Idx = State.getFirstUnallocated(ArgRegs); 4071 unsigned RegSizeInBytes = Subtarget.getGPRSizeInBytes(); 4072 MVT RegTy = MVT::getIntegerVT(RegSizeInBytes * 8); 4073 const TargetRegisterClass *RC = getRegClassFor(RegTy); 4074 MachineFunction &MF = DAG.getMachineFunction(); 4075 MachineFrameInfo &MFI = MF.getFrameInfo(); 4076 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>(); 4077 4078 // Offset of the first variable argument from stack pointer. 4079 int VaArgOffset; 4080 4081 if (ArgRegs.size() == Idx) 4082 VaArgOffset = alignTo(State.getNextStackOffset(), RegSizeInBytes); 4083 else { 4084 VaArgOffset = 4085 (int)ABI.GetCalleeAllocdArgSizeInBytes(State.getCallingConv()) - 4086 (int)(RegSizeInBytes * (ArgRegs.size() - Idx)); 4087 } 4088 4089 // Record the frame index of the first variable argument 4090 // which is a value necessary to VASTART. 4091 int FI = MFI.CreateFixedObject(RegSizeInBytes, VaArgOffset, true); 4092 MipsFI->setVarArgsFrameIndex(FI); 4093 4094 // Copy the integer registers that have not been used for argument passing 4095 // to the argument register save area. For O32, the save area is allocated 4096 // in the caller's stack frame, while for N32/64, it is allocated in the 4097 // callee's stack frame. 4098 for (unsigned I = Idx; I < ArgRegs.size(); 4099 ++I, VaArgOffset += RegSizeInBytes) { 4100 unsigned Reg = addLiveIn(MF, ArgRegs[I], RC); 4101 SDValue ArgValue = DAG.getCopyFromReg(Chain, DL, Reg, RegTy); 4102 FI = MFI.CreateFixedObject(RegSizeInBytes, VaArgOffset, true); 4103 SDValue PtrOff = DAG.getFrameIndex(FI, getPointerTy(DAG.getDataLayout())); 4104 SDValue Store = 4105 DAG.getStore(Chain, DL, ArgValue, PtrOff, MachinePointerInfo()); 4106 cast<StoreSDNode>(Store.getNode())->getMemOperand()->setValue( 4107 (Value *)nullptr); 4108 OutChains.push_back(Store); 4109 } 4110 } 4111 4112 void MipsTargetLowering::HandleByVal(CCState *State, unsigned &Size, 4113 unsigned Align) const { 4114 const TargetFrameLowering *TFL = Subtarget.getFrameLowering(); 4115 4116 assert(Size && "Byval argument's size shouldn't be 0."); 4117 4118 Align = std::min(Align, TFL->getStackAlignment()); 4119 4120 unsigned FirstReg = 0; 4121 unsigned NumRegs = 0; 4122 4123 if (State->getCallingConv() != CallingConv::Fast) { 4124 unsigned RegSizeInBytes = Subtarget.getGPRSizeInBytes(); 4125 ArrayRef<MCPhysReg> IntArgRegs = ABI.GetByValArgRegs(); 4126 // FIXME: The O32 case actually describes no shadow registers. 4127 const MCPhysReg *ShadowRegs = 4128 ABI.IsO32() ? IntArgRegs.data() : Mips64DPRegs; 4129 4130 // We used to check the size as well but we can't do that anymore since 4131 // CCState::HandleByVal() rounds up the size after calling this function. 4132 assert(!(Align % RegSizeInBytes) && 4133 "Byval argument's alignment should be a multiple of" 4134 "RegSizeInBytes."); 4135 4136 FirstReg = State->getFirstUnallocated(IntArgRegs); 4137 4138 // If Align > RegSizeInBytes, the first arg register must be even. 4139 // FIXME: This condition happens to do the right thing but it's not the 4140 // right way to test it. We want to check that the stack frame offset 4141 // of the register is aligned. 4142 if ((Align > RegSizeInBytes) && (FirstReg % 2)) { 4143 State->AllocateReg(IntArgRegs[FirstReg], ShadowRegs[FirstReg]); 4144 ++FirstReg; 4145 } 4146 4147 // Mark the registers allocated. 4148 Size = alignTo(Size, RegSizeInBytes); 4149 for (unsigned I = FirstReg; Size > 0 && (I < IntArgRegs.size()); 4150 Size -= RegSizeInBytes, ++I, ++NumRegs) 4151 State->AllocateReg(IntArgRegs[I], ShadowRegs[I]); 4152 } 4153 4154 State->addInRegsParamInfo(FirstReg, FirstReg + NumRegs); 4155 } 4156 4157 MachineBasicBlock *MipsTargetLowering::emitPseudoSELECT(MachineInstr &MI, 4158 MachineBasicBlock *BB, 4159 bool isFPCmp, 4160 unsigned Opc) const { 4161 assert(!(Subtarget.hasMips4() || Subtarget.hasMips32()) && 4162 "Subtarget already supports SELECT nodes with the use of" 4163 "conditional-move instructions."); 4164 4165 const TargetInstrInfo *TII = 4166 Subtarget.getInstrInfo(); 4167 DebugLoc DL = MI.getDebugLoc(); 4168 4169 // To "insert" a SELECT instruction, we actually have to insert the 4170 // diamond control-flow pattern. The incoming instruction knows the 4171 // destination vreg to set, the condition code register to branch on, the 4172 // true/false values to select between, and a branch opcode to use. 4173 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 4174 MachineFunction::iterator It = ++BB->getIterator(); 4175 4176 // thisMBB: 4177 // ... 4178 // TrueVal = ... 4179 // setcc r1, r2, r3 4180 // bNE r1, r0, copy1MBB 4181 // fallthrough --> copy0MBB 4182 MachineBasicBlock *thisMBB = BB; 4183 MachineFunction *F = BB->getParent(); 4184 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB); 4185 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB); 4186 F->insert(It, copy0MBB); 4187 F->insert(It, sinkMBB); 4188 4189 // Transfer the remainder of BB and its successor edges to sinkMBB. 4190 sinkMBB->splice(sinkMBB->begin(), BB, 4191 std::next(MachineBasicBlock::iterator(MI)), BB->end()); 4192 sinkMBB->transferSuccessorsAndUpdatePHIs(BB); 4193 4194 // Next, add the true and fallthrough blocks as its successors. 4195 BB->addSuccessor(copy0MBB); 4196 BB->addSuccessor(sinkMBB); 4197 4198 if (isFPCmp) { 4199 // bc1[tf] cc, sinkMBB 4200 BuildMI(BB, DL, TII->get(Opc)) 4201 .addReg(MI.getOperand(1).getReg()) 4202 .addMBB(sinkMBB); 4203 } else { 4204 // bne rs, $0, sinkMBB 4205 BuildMI(BB, DL, TII->get(Opc)) 4206 .addReg(MI.getOperand(1).getReg()) 4207 .addReg(Mips::ZERO) 4208 .addMBB(sinkMBB); 4209 } 4210 4211 // copy0MBB: 4212 // %FalseValue = ... 4213 // # fallthrough to sinkMBB 4214 BB = copy0MBB; 4215 4216 // Update machine-CFG edges 4217 BB->addSuccessor(sinkMBB); 4218 4219 // sinkMBB: 4220 // %Result = phi [ %TrueValue, thisMBB ], [ %FalseValue, copy0MBB ] 4221 // ... 4222 BB = sinkMBB; 4223 4224 BuildMI(*BB, BB->begin(), DL, TII->get(Mips::PHI), MI.getOperand(0).getReg()) 4225 .addReg(MI.getOperand(2).getReg()) 4226 .addMBB(thisMBB) 4227 .addReg(MI.getOperand(3).getReg()) 4228 .addMBB(copy0MBB); 4229 4230 MI.eraseFromParent(); // The pseudo instruction is gone now. 4231 4232 return BB; 4233 } 4234 4235 // FIXME? Maybe this could be a TableGen attribute on some registers and 4236 // this table could be generated automatically from RegInfo. 4237 unsigned MipsTargetLowering::getRegisterByName(const char* RegName, EVT VT, 4238 SelectionDAG &DAG) const { 4239 // Named registers is expected to be fairly rare. For now, just support $28 4240 // since the linux kernel uses it. 4241 if (Subtarget.isGP64bit()) { 4242 unsigned Reg = StringSwitch<unsigned>(RegName) 4243 .Case("$28", Mips::GP_64) 4244 .Default(0); 4245 if (Reg) 4246 return Reg; 4247 } else { 4248 unsigned Reg = StringSwitch<unsigned>(RegName) 4249 .Case("$28", Mips::GP) 4250 .Default(0); 4251 if (Reg) 4252 return Reg; 4253 } 4254 report_fatal_error("Invalid register name global variable"); 4255 } 4256