1 //===- MipsISelLowering.cpp - Mips DAG Lowering Implementation ------------===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // This file defines the interfaces that Mips uses to lower LLVM code into a 10 // selection DAG. 11 // 12 //===----------------------------------------------------------------------===// 13 14 #include "MipsISelLowering.h" 15 #include "MCTargetDesc/MipsBaseInfo.h" 16 #include "MCTargetDesc/MipsInstPrinter.h" 17 #include "MCTargetDesc/MipsMCTargetDesc.h" 18 #include "MipsCCState.h" 19 #include "MipsInstrInfo.h" 20 #include "MipsMachineFunction.h" 21 #include "MipsRegisterInfo.h" 22 #include "MipsSubtarget.h" 23 #include "MipsTargetMachine.h" 24 #include "MipsTargetObjectFile.h" 25 #include "llvm/ADT/APFloat.h" 26 #include "llvm/ADT/ArrayRef.h" 27 #include "llvm/ADT/SmallVector.h" 28 #include "llvm/ADT/Statistic.h" 29 #include "llvm/ADT/StringRef.h" 30 #include "llvm/ADT/StringSwitch.h" 31 #include "llvm/CodeGen/CallingConvLower.h" 32 #include "llvm/CodeGen/FunctionLoweringInfo.h" 33 #include "llvm/CodeGen/ISDOpcodes.h" 34 #include "llvm/CodeGen/MachineBasicBlock.h" 35 #include "llvm/CodeGen/MachineFrameInfo.h" 36 #include "llvm/CodeGen/MachineFunction.h" 37 #include "llvm/CodeGen/MachineInstr.h" 38 #include "llvm/CodeGen/MachineInstrBuilder.h" 39 #include "llvm/CodeGen/MachineJumpTableInfo.h" 40 #include "llvm/CodeGen/MachineMemOperand.h" 41 #include "llvm/CodeGen/MachineOperand.h" 42 #include "llvm/CodeGen/MachineRegisterInfo.h" 43 #include "llvm/CodeGen/RuntimeLibcalls.h" 44 #include "llvm/CodeGen/SelectionDAG.h" 45 #include "llvm/CodeGen/SelectionDAGNodes.h" 46 #include "llvm/CodeGen/TargetFrameLowering.h" 47 #include "llvm/CodeGen/TargetInstrInfo.h" 48 #include "llvm/CodeGen/TargetRegisterInfo.h" 49 #include "llvm/CodeGen/ValueTypes.h" 50 #include "llvm/IR/CallingConv.h" 51 #include "llvm/IR/Constants.h" 52 #include "llvm/IR/DataLayout.h" 53 #include "llvm/IR/DebugLoc.h" 54 #include "llvm/IR/DerivedTypes.h" 55 #include "llvm/IR/Function.h" 56 #include "llvm/IR/GlobalValue.h" 57 #include "llvm/IR/Type.h" 58 #include "llvm/IR/Value.h" 59 #include "llvm/MC/MCContext.h" 60 #include "llvm/MC/MCRegisterInfo.h" 61 #include "llvm/Support/Casting.h" 62 #include "llvm/Support/CodeGen.h" 63 #include "llvm/Support/CommandLine.h" 64 #include "llvm/Support/Compiler.h" 65 #include "llvm/Support/ErrorHandling.h" 66 #include "llvm/Support/MachineValueType.h" 67 #include "llvm/Support/MathExtras.h" 68 #include "llvm/Target/TargetMachine.h" 69 #include "llvm/Target/TargetOptions.h" 70 #include <algorithm> 71 #include <cassert> 72 #include <cctype> 73 #include <cstdint> 74 #include <deque> 75 #include <iterator> 76 #include <utility> 77 #include <vector> 78 79 using namespace llvm; 80 81 #define DEBUG_TYPE "mips-lower" 82 83 STATISTIC(NumTailCalls, "Number of tail calls"); 84 85 static cl::opt<bool> 86 NoZeroDivCheck("mno-check-zero-division", cl::Hidden, 87 cl::desc("MIPS: Don't trap on integer division by zero."), 88 cl::init(false)); 89 90 extern cl::opt<bool> EmitJalrReloc; 91 92 static const MCPhysReg Mips64DPRegs[8] = { 93 Mips::D12_64, Mips::D13_64, Mips::D14_64, Mips::D15_64, 94 Mips::D16_64, Mips::D17_64, Mips::D18_64, Mips::D19_64 95 }; 96 97 // The MIPS MSA ABI passes vector arguments in the integer register set. 98 // The number of integer registers used is dependant on the ABI used. 99 MVT MipsTargetLowering::getRegisterTypeForCallingConv(LLVMContext &Context, 100 CallingConv::ID CC, 101 EVT VT) const { 102 if (!VT.isVector()) 103 return getRegisterType(Context, VT); 104 105 return Subtarget.isABI_O32() || VT.getSizeInBits() == 32 ? MVT::i32 106 : MVT::i64; 107 } 108 109 unsigned MipsTargetLowering::getNumRegistersForCallingConv(LLVMContext &Context, 110 CallingConv::ID CC, 111 EVT VT) const { 112 if (VT.isVector()) 113 return divideCeil(VT.getSizeInBits(), Subtarget.isABI_O32() ? 32 : 64); 114 return MipsTargetLowering::getNumRegisters(Context, VT); 115 } 116 117 unsigned MipsTargetLowering::getVectorTypeBreakdownForCallingConv( 118 LLVMContext &Context, CallingConv::ID CC, EVT VT, EVT &IntermediateVT, 119 unsigned &NumIntermediates, MVT &RegisterVT) const { 120 // Break down vector types to either 2 i64s or 4 i32s. 121 RegisterVT = getRegisterTypeForCallingConv(Context, CC, VT); 122 IntermediateVT = RegisterVT; 123 NumIntermediates = 124 VT.getFixedSizeInBits() < RegisterVT.getFixedSizeInBits() 125 ? VT.getVectorNumElements() 126 : divideCeil(VT.getSizeInBits(), RegisterVT.getSizeInBits()); 127 return NumIntermediates; 128 } 129 130 SDValue MipsTargetLowering::getGlobalReg(SelectionDAG &DAG, EVT Ty) const { 131 MachineFunction &MF = DAG.getMachineFunction(); 132 MipsFunctionInfo *FI = MF.getInfo<MipsFunctionInfo>(); 133 return DAG.getRegister(FI->getGlobalBaseReg(MF), Ty); 134 } 135 136 SDValue MipsTargetLowering::getTargetNode(GlobalAddressSDNode *N, EVT Ty, 137 SelectionDAG &DAG, 138 unsigned Flag) const { 139 return DAG.getTargetGlobalAddress(N->getGlobal(), SDLoc(N), Ty, 0, Flag); 140 } 141 142 SDValue MipsTargetLowering::getTargetNode(ExternalSymbolSDNode *N, EVT Ty, 143 SelectionDAG &DAG, 144 unsigned Flag) const { 145 return DAG.getTargetExternalSymbol(N->getSymbol(), Ty, Flag); 146 } 147 148 SDValue MipsTargetLowering::getTargetNode(BlockAddressSDNode *N, EVT Ty, 149 SelectionDAG &DAG, 150 unsigned Flag) const { 151 return DAG.getTargetBlockAddress(N->getBlockAddress(), Ty, 0, Flag); 152 } 153 154 SDValue MipsTargetLowering::getTargetNode(JumpTableSDNode *N, EVT Ty, 155 SelectionDAG &DAG, 156 unsigned Flag) const { 157 return DAG.getTargetJumpTable(N->getIndex(), Ty, Flag); 158 } 159 160 SDValue MipsTargetLowering::getTargetNode(ConstantPoolSDNode *N, EVT Ty, 161 SelectionDAG &DAG, 162 unsigned Flag) const { 163 return DAG.getTargetConstantPool(N->getConstVal(), Ty, N->getAlign(), 164 N->getOffset(), Flag); 165 } 166 167 const char *MipsTargetLowering::getTargetNodeName(unsigned Opcode) const { 168 switch ((MipsISD::NodeType)Opcode) { 169 case MipsISD::FIRST_NUMBER: break; 170 case MipsISD::JmpLink: return "MipsISD::JmpLink"; 171 case MipsISD::TailCall: return "MipsISD::TailCall"; 172 case MipsISD::Highest: return "MipsISD::Highest"; 173 case MipsISD::Higher: return "MipsISD::Higher"; 174 case MipsISD::Hi: return "MipsISD::Hi"; 175 case MipsISD::Lo: return "MipsISD::Lo"; 176 case MipsISD::GotHi: return "MipsISD::GotHi"; 177 case MipsISD::TlsHi: return "MipsISD::TlsHi"; 178 case MipsISD::GPRel: return "MipsISD::GPRel"; 179 case MipsISD::ThreadPointer: return "MipsISD::ThreadPointer"; 180 case MipsISD::Ret: return "MipsISD::Ret"; 181 case MipsISD::ERet: return "MipsISD::ERet"; 182 case MipsISD::EH_RETURN: return "MipsISD::EH_RETURN"; 183 case MipsISD::FMS: return "MipsISD::FMS"; 184 case MipsISD::FPBrcond: return "MipsISD::FPBrcond"; 185 case MipsISD::FPCmp: return "MipsISD::FPCmp"; 186 case MipsISD::FSELECT: return "MipsISD::FSELECT"; 187 case MipsISD::MTC1_D64: return "MipsISD::MTC1_D64"; 188 case MipsISD::CMovFP_T: return "MipsISD::CMovFP_T"; 189 case MipsISD::CMovFP_F: return "MipsISD::CMovFP_F"; 190 case MipsISD::TruncIntFP: return "MipsISD::TruncIntFP"; 191 case MipsISD::MFHI: return "MipsISD::MFHI"; 192 case MipsISD::MFLO: return "MipsISD::MFLO"; 193 case MipsISD::MTLOHI: return "MipsISD::MTLOHI"; 194 case MipsISD::Mult: return "MipsISD::Mult"; 195 case MipsISD::Multu: return "MipsISD::Multu"; 196 case MipsISD::MAdd: return "MipsISD::MAdd"; 197 case MipsISD::MAddu: return "MipsISD::MAddu"; 198 case MipsISD::MSub: return "MipsISD::MSub"; 199 case MipsISD::MSubu: return "MipsISD::MSubu"; 200 case MipsISD::DivRem: return "MipsISD::DivRem"; 201 case MipsISD::DivRemU: return "MipsISD::DivRemU"; 202 case MipsISD::DivRem16: return "MipsISD::DivRem16"; 203 case MipsISD::DivRemU16: return "MipsISD::DivRemU16"; 204 case MipsISD::BuildPairF64: return "MipsISD::BuildPairF64"; 205 case MipsISD::ExtractElementF64: return "MipsISD::ExtractElementF64"; 206 case MipsISD::Wrapper: return "MipsISD::Wrapper"; 207 case MipsISD::DynAlloc: return "MipsISD::DynAlloc"; 208 case MipsISD::Sync: return "MipsISD::Sync"; 209 case MipsISD::Ext: return "MipsISD::Ext"; 210 case MipsISD::Ins: return "MipsISD::Ins"; 211 case MipsISD::CIns: return "MipsISD::CIns"; 212 case MipsISD::LWL: return "MipsISD::LWL"; 213 case MipsISD::LWR: return "MipsISD::LWR"; 214 case MipsISD::SWL: return "MipsISD::SWL"; 215 case MipsISD::SWR: return "MipsISD::SWR"; 216 case MipsISD::LDL: return "MipsISD::LDL"; 217 case MipsISD::LDR: return "MipsISD::LDR"; 218 case MipsISD::SDL: return "MipsISD::SDL"; 219 case MipsISD::SDR: return "MipsISD::SDR"; 220 case MipsISD::EXTP: return "MipsISD::EXTP"; 221 case MipsISD::EXTPDP: return "MipsISD::EXTPDP"; 222 case MipsISD::EXTR_S_H: return "MipsISD::EXTR_S_H"; 223 case MipsISD::EXTR_W: return "MipsISD::EXTR_W"; 224 case MipsISD::EXTR_R_W: return "MipsISD::EXTR_R_W"; 225 case MipsISD::EXTR_RS_W: return "MipsISD::EXTR_RS_W"; 226 case MipsISD::SHILO: return "MipsISD::SHILO"; 227 case MipsISD::MTHLIP: return "MipsISD::MTHLIP"; 228 case MipsISD::MULSAQ_S_W_PH: return "MipsISD::MULSAQ_S_W_PH"; 229 case MipsISD::MAQ_S_W_PHL: return "MipsISD::MAQ_S_W_PHL"; 230 case MipsISD::MAQ_S_W_PHR: return "MipsISD::MAQ_S_W_PHR"; 231 case MipsISD::MAQ_SA_W_PHL: return "MipsISD::MAQ_SA_W_PHL"; 232 case MipsISD::MAQ_SA_W_PHR: return "MipsISD::MAQ_SA_W_PHR"; 233 case MipsISD::DPAU_H_QBL: return "MipsISD::DPAU_H_QBL"; 234 case MipsISD::DPAU_H_QBR: return "MipsISD::DPAU_H_QBR"; 235 case MipsISD::DPSU_H_QBL: return "MipsISD::DPSU_H_QBL"; 236 case MipsISD::DPSU_H_QBR: return "MipsISD::DPSU_H_QBR"; 237 case MipsISD::DPAQ_S_W_PH: return "MipsISD::DPAQ_S_W_PH"; 238 case MipsISD::DPSQ_S_W_PH: return "MipsISD::DPSQ_S_W_PH"; 239 case MipsISD::DPAQ_SA_L_W: return "MipsISD::DPAQ_SA_L_W"; 240 case MipsISD::DPSQ_SA_L_W: return "MipsISD::DPSQ_SA_L_W"; 241 case MipsISD::DPA_W_PH: return "MipsISD::DPA_W_PH"; 242 case MipsISD::DPS_W_PH: return "MipsISD::DPS_W_PH"; 243 case MipsISD::DPAQX_S_W_PH: return "MipsISD::DPAQX_S_W_PH"; 244 case MipsISD::DPAQX_SA_W_PH: return "MipsISD::DPAQX_SA_W_PH"; 245 case MipsISD::DPAX_W_PH: return "MipsISD::DPAX_W_PH"; 246 case MipsISD::DPSX_W_PH: return "MipsISD::DPSX_W_PH"; 247 case MipsISD::DPSQX_S_W_PH: return "MipsISD::DPSQX_S_W_PH"; 248 case MipsISD::DPSQX_SA_W_PH: return "MipsISD::DPSQX_SA_W_PH"; 249 case MipsISD::MULSA_W_PH: return "MipsISD::MULSA_W_PH"; 250 case MipsISD::MULT: return "MipsISD::MULT"; 251 case MipsISD::MULTU: return "MipsISD::MULTU"; 252 case MipsISD::MADD_DSP: return "MipsISD::MADD_DSP"; 253 case MipsISD::MADDU_DSP: return "MipsISD::MADDU_DSP"; 254 case MipsISD::MSUB_DSP: return "MipsISD::MSUB_DSP"; 255 case MipsISD::MSUBU_DSP: return "MipsISD::MSUBU_DSP"; 256 case MipsISD::SHLL_DSP: return "MipsISD::SHLL_DSP"; 257 case MipsISD::SHRA_DSP: return "MipsISD::SHRA_DSP"; 258 case MipsISD::SHRL_DSP: return "MipsISD::SHRL_DSP"; 259 case MipsISD::SETCC_DSP: return "MipsISD::SETCC_DSP"; 260 case MipsISD::SELECT_CC_DSP: return "MipsISD::SELECT_CC_DSP"; 261 case MipsISD::VALL_ZERO: return "MipsISD::VALL_ZERO"; 262 case MipsISD::VANY_ZERO: return "MipsISD::VANY_ZERO"; 263 case MipsISD::VALL_NONZERO: return "MipsISD::VALL_NONZERO"; 264 case MipsISD::VANY_NONZERO: return "MipsISD::VANY_NONZERO"; 265 case MipsISD::VCEQ: return "MipsISD::VCEQ"; 266 case MipsISD::VCLE_S: return "MipsISD::VCLE_S"; 267 case MipsISD::VCLE_U: return "MipsISD::VCLE_U"; 268 case MipsISD::VCLT_S: return "MipsISD::VCLT_S"; 269 case MipsISD::VCLT_U: return "MipsISD::VCLT_U"; 270 case MipsISD::VEXTRACT_SEXT_ELT: return "MipsISD::VEXTRACT_SEXT_ELT"; 271 case MipsISD::VEXTRACT_ZEXT_ELT: return "MipsISD::VEXTRACT_ZEXT_ELT"; 272 case MipsISD::VNOR: return "MipsISD::VNOR"; 273 case MipsISD::VSHF: return "MipsISD::VSHF"; 274 case MipsISD::SHF: return "MipsISD::SHF"; 275 case MipsISD::ILVEV: return "MipsISD::ILVEV"; 276 case MipsISD::ILVOD: return "MipsISD::ILVOD"; 277 case MipsISD::ILVL: return "MipsISD::ILVL"; 278 case MipsISD::ILVR: return "MipsISD::ILVR"; 279 case MipsISD::PCKEV: return "MipsISD::PCKEV"; 280 case MipsISD::PCKOD: return "MipsISD::PCKOD"; 281 case MipsISD::INSVE: return "MipsISD::INSVE"; 282 } 283 return nullptr; 284 } 285 286 MipsTargetLowering::MipsTargetLowering(const MipsTargetMachine &TM, 287 const MipsSubtarget &STI) 288 : TargetLowering(TM), Subtarget(STI), ABI(TM.getABI()) { 289 // Mips does not have i1 type, so use i32 for 290 // setcc operations results (slt, sgt, ...). 291 setBooleanContents(ZeroOrOneBooleanContent); 292 setBooleanVectorContents(ZeroOrNegativeOneBooleanContent); 293 // The cmp.cond.fmt instruction in MIPS32r6/MIPS64r6 uses 0 and -1 like MSA 294 // does. Integer booleans still use 0 and 1. 295 if (Subtarget.hasMips32r6()) 296 setBooleanContents(ZeroOrOneBooleanContent, 297 ZeroOrNegativeOneBooleanContent); 298 299 // Load extented operations for i1 types must be promoted 300 for (MVT VT : MVT::integer_valuetypes()) { 301 setLoadExtAction(ISD::EXTLOAD, VT, MVT::i1, Promote); 302 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i1, Promote); 303 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i1, Promote); 304 } 305 306 // MIPS doesn't have extending float->double load/store. Set LoadExtAction 307 // for f32, f16 308 for (MVT VT : MVT::fp_valuetypes()) { 309 setLoadExtAction(ISD::EXTLOAD, VT, MVT::f32, Expand); 310 setLoadExtAction(ISD::EXTLOAD, VT, MVT::f16, Expand); 311 } 312 313 // Set LoadExtAction for f16 vectors to Expand 314 for (MVT VT : MVT::fp_fixedlen_vector_valuetypes()) { 315 MVT F16VT = MVT::getVectorVT(MVT::f16, VT.getVectorNumElements()); 316 if (F16VT.isValid()) 317 setLoadExtAction(ISD::EXTLOAD, VT, F16VT, Expand); 318 } 319 320 setTruncStoreAction(MVT::f32, MVT::f16, Expand); 321 setTruncStoreAction(MVT::f64, MVT::f16, Expand); 322 323 setTruncStoreAction(MVT::f64, MVT::f32, Expand); 324 325 // Used by legalize types to correctly generate the setcc result. 326 // Without this, every float setcc comes with a AND/OR with the result, 327 // we don't want this, since the fpcmp result goes to a flag register, 328 // which is used implicitly by brcond and select operations. 329 AddPromotedToType(ISD::SETCC, MVT::i1, MVT::i32); 330 331 // Mips Custom Operations 332 setOperationAction(ISD::BR_JT, MVT::Other, Expand); 333 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom); 334 setOperationAction(ISD::BlockAddress, MVT::i32, Custom); 335 setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom); 336 setOperationAction(ISD::JumpTable, MVT::i32, Custom); 337 setOperationAction(ISD::ConstantPool, MVT::i32, Custom); 338 setOperationAction(ISD::SELECT, MVT::f32, Custom); 339 setOperationAction(ISD::SELECT, MVT::f64, Custom); 340 setOperationAction(ISD::SELECT, MVT::i32, Custom); 341 setOperationAction(ISD::SETCC, MVT::f32, Custom); 342 setOperationAction(ISD::SETCC, MVT::f64, Custom); 343 setOperationAction(ISD::BRCOND, MVT::Other, Custom); 344 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom); 345 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom); 346 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom); 347 348 if (!(TM.Options.NoNaNsFPMath || Subtarget.inAbs2008Mode())) { 349 setOperationAction(ISD::FABS, MVT::f32, Custom); 350 setOperationAction(ISD::FABS, MVT::f64, Custom); 351 } 352 353 if (Subtarget.isGP64bit()) { 354 setOperationAction(ISD::GlobalAddress, MVT::i64, Custom); 355 setOperationAction(ISD::BlockAddress, MVT::i64, Custom); 356 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom); 357 setOperationAction(ISD::JumpTable, MVT::i64, Custom); 358 setOperationAction(ISD::ConstantPool, MVT::i64, Custom); 359 setOperationAction(ISD::SELECT, MVT::i64, Custom); 360 setOperationAction(ISD::LOAD, MVT::i64, Custom); 361 setOperationAction(ISD::STORE, MVT::i64, Custom); 362 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom); 363 setOperationAction(ISD::SHL_PARTS, MVT::i64, Custom); 364 setOperationAction(ISD::SRA_PARTS, MVT::i64, Custom); 365 setOperationAction(ISD::SRL_PARTS, MVT::i64, Custom); 366 } 367 368 if (!Subtarget.isGP64bit()) { 369 setOperationAction(ISD::SHL_PARTS, MVT::i32, Custom); 370 setOperationAction(ISD::SRA_PARTS, MVT::i32, Custom); 371 setOperationAction(ISD::SRL_PARTS, MVT::i32, Custom); 372 } 373 374 setOperationAction(ISD::EH_DWARF_CFA, MVT::i32, Custom); 375 if (Subtarget.isGP64bit()) 376 setOperationAction(ISD::EH_DWARF_CFA, MVT::i64, Custom); 377 378 setOperationAction(ISD::SDIV, MVT::i32, Expand); 379 setOperationAction(ISD::SREM, MVT::i32, Expand); 380 setOperationAction(ISD::UDIV, MVT::i32, Expand); 381 setOperationAction(ISD::UREM, MVT::i32, Expand); 382 setOperationAction(ISD::SDIV, MVT::i64, Expand); 383 setOperationAction(ISD::SREM, MVT::i64, Expand); 384 setOperationAction(ISD::UDIV, MVT::i64, Expand); 385 setOperationAction(ISD::UREM, MVT::i64, Expand); 386 387 // Operations not directly supported by Mips. 388 setOperationAction(ISD::BR_CC, MVT::f32, Expand); 389 setOperationAction(ISD::BR_CC, MVT::f64, Expand); 390 setOperationAction(ISD::BR_CC, MVT::i32, Expand); 391 setOperationAction(ISD::BR_CC, MVT::i64, Expand); 392 setOperationAction(ISD::SELECT_CC, MVT::i32, Expand); 393 setOperationAction(ISD::SELECT_CC, MVT::i64, Expand); 394 setOperationAction(ISD::SELECT_CC, MVT::f32, Expand); 395 setOperationAction(ISD::SELECT_CC, MVT::f64, Expand); 396 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand); 397 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Expand); 398 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand); 399 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Expand); 400 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand); 401 if (Subtarget.hasCnMips()) { 402 setOperationAction(ISD::CTPOP, MVT::i32, Legal); 403 setOperationAction(ISD::CTPOP, MVT::i64, Legal); 404 } else { 405 setOperationAction(ISD::CTPOP, MVT::i32, Expand); 406 setOperationAction(ISD::CTPOP, MVT::i64, Expand); 407 } 408 setOperationAction(ISD::CTTZ, MVT::i32, Expand); 409 setOperationAction(ISD::CTTZ, MVT::i64, Expand); 410 setOperationAction(ISD::ROTL, MVT::i32, Expand); 411 setOperationAction(ISD::ROTL, MVT::i64, Expand); 412 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Expand); 413 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64, Expand); 414 415 if (!Subtarget.hasMips32r2()) 416 setOperationAction(ISD::ROTR, MVT::i32, Expand); 417 418 if (!Subtarget.hasMips64r2()) 419 setOperationAction(ISD::ROTR, MVT::i64, Expand); 420 421 setOperationAction(ISD::FSIN, MVT::f32, Expand); 422 setOperationAction(ISD::FSIN, MVT::f64, Expand); 423 setOperationAction(ISD::FCOS, MVT::f32, Expand); 424 setOperationAction(ISD::FCOS, MVT::f64, Expand); 425 setOperationAction(ISD::FSINCOS, MVT::f32, Expand); 426 setOperationAction(ISD::FSINCOS, MVT::f64, Expand); 427 setOperationAction(ISD::FPOW, MVT::f32, Expand); 428 setOperationAction(ISD::FPOW, MVT::f64, Expand); 429 setOperationAction(ISD::FLOG, MVT::f32, Expand); 430 setOperationAction(ISD::FLOG2, MVT::f32, Expand); 431 setOperationAction(ISD::FLOG10, MVT::f32, Expand); 432 setOperationAction(ISD::FEXP, MVT::f32, Expand); 433 setOperationAction(ISD::FMA, MVT::f32, Expand); 434 setOperationAction(ISD::FMA, MVT::f64, Expand); 435 setOperationAction(ISD::FREM, MVT::f32, Expand); 436 setOperationAction(ISD::FREM, MVT::f64, Expand); 437 438 // Lower f16 conversion operations into library calls 439 setOperationAction(ISD::FP16_TO_FP, MVT::f32, Expand); 440 setOperationAction(ISD::FP_TO_FP16, MVT::f32, Expand); 441 setOperationAction(ISD::FP16_TO_FP, MVT::f64, Expand); 442 setOperationAction(ISD::FP_TO_FP16, MVT::f64, Expand); 443 444 setOperationAction(ISD::EH_RETURN, MVT::Other, Custom); 445 446 setOperationAction(ISD::VASTART, MVT::Other, Custom); 447 setOperationAction(ISD::VAARG, MVT::Other, Custom); 448 setOperationAction(ISD::VACOPY, MVT::Other, Expand); 449 setOperationAction(ISD::VAEND, MVT::Other, Expand); 450 451 // Use the default for now 452 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand); 453 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand); 454 455 if (!Subtarget.isGP64bit()) { 456 setOperationAction(ISD::ATOMIC_LOAD, MVT::i64, Expand); 457 setOperationAction(ISD::ATOMIC_STORE, MVT::i64, Expand); 458 } 459 460 if (!Subtarget.hasMips32r2()) { 461 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8, Expand); 462 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand); 463 } 464 465 // MIPS16 lacks MIPS32's clz and clo instructions. 466 if (!Subtarget.hasMips32() || Subtarget.inMips16Mode()) 467 setOperationAction(ISD::CTLZ, MVT::i32, Expand); 468 if (!Subtarget.hasMips64()) 469 setOperationAction(ISD::CTLZ, MVT::i64, Expand); 470 471 if (!Subtarget.hasMips32r2()) 472 setOperationAction(ISD::BSWAP, MVT::i32, Expand); 473 if (!Subtarget.hasMips64r2()) 474 setOperationAction(ISD::BSWAP, MVT::i64, Expand); 475 476 if (Subtarget.isGP64bit()) { 477 setLoadExtAction(ISD::SEXTLOAD, MVT::i64, MVT::i32, Custom); 478 setLoadExtAction(ISD::ZEXTLOAD, MVT::i64, MVT::i32, Custom); 479 setLoadExtAction(ISD::EXTLOAD, MVT::i64, MVT::i32, Custom); 480 setTruncStoreAction(MVT::i64, MVT::i32, Custom); 481 } 482 483 setOperationAction(ISD::TRAP, MVT::Other, Legal); 484 485 setTargetDAGCombine({ISD::SDIVREM, ISD::UDIVREM, ISD::SELECT, ISD::AND, 486 ISD::OR, ISD::ADD, ISD::SUB, ISD::AssertZext, ISD::SHL}); 487 488 if (ABI.IsO32()) { 489 // These libcalls are not available in 32-bit. 490 setLibcallName(RTLIB::SHL_I128, nullptr); 491 setLibcallName(RTLIB::SRL_I128, nullptr); 492 setLibcallName(RTLIB::SRA_I128, nullptr); 493 setLibcallName(RTLIB::MUL_I128, nullptr); 494 setLibcallName(RTLIB::MULO_I64, nullptr); 495 setLibcallName(RTLIB::MULO_I128, nullptr); 496 } 497 498 setMinFunctionAlignment(Subtarget.isGP64bit() ? Align(8) : Align(4)); 499 500 // The arguments on the stack are defined in terms of 4-byte slots on O32 501 // and 8-byte slots on N32/N64. 502 setMinStackArgumentAlignment((ABI.IsN32() || ABI.IsN64()) ? Align(8) 503 : Align(4)); 504 505 setStackPointerRegisterToSaveRestore(ABI.IsN64() ? Mips::SP_64 : Mips::SP); 506 507 MaxStoresPerMemcpy = 16; 508 509 isMicroMips = Subtarget.inMicroMipsMode(); 510 } 511 512 const MipsTargetLowering * 513 MipsTargetLowering::create(const MipsTargetMachine &TM, 514 const MipsSubtarget &STI) { 515 if (STI.inMips16Mode()) 516 return createMips16TargetLowering(TM, STI); 517 518 return createMipsSETargetLowering(TM, STI); 519 } 520 521 // Create a fast isel object. 522 FastISel * 523 MipsTargetLowering::createFastISel(FunctionLoweringInfo &funcInfo, 524 const TargetLibraryInfo *libInfo) const { 525 const MipsTargetMachine &TM = 526 static_cast<const MipsTargetMachine &>(funcInfo.MF->getTarget()); 527 528 // We support only the standard encoding [MIPS32,MIPS32R5] ISAs. 529 bool UseFastISel = TM.Options.EnableFastISel && Subtarget.hasMips32() && 530 !Subtarget.hasMips32r6() && !Subtarget.inMips16Mode() && 531 !Subtarget.inMicroMipsMode(); 532 533 // Disable if either of the following is true: 534 // We do not generate PIC, the ABI is not O32, XGOT is being used. 535 if (!TM.isPositionIndependent() || !TM.getABI().IsO32() || 536 Subtarget.useXGOT()) 537 UseFastISel = false; 538 539 return UseFastISel ? Mips::createFastISel(funcInfo, libInfo) : nullptr; 540 } 541 542 EVT MipsTargetLowering::getSetCCResultType(const DataLayout &, LLVMContext &, 543 EVT VT) const { 544 if (!VT.isVector()) 545 return MVT::i32; 546 return VT.changeVectorElementTypeToInteger(); 547 } 548 549 static SDValue performDivRemCombine(SDNode *N, SelectionDAG &DAG, 550 TargetLowering::DAGCombinerInfo &DCI, 551 const MipsSubtarget &Subtarget) { 552 if (DCI.isBeforeLegalizeOps()) 553 return SDValue(); 554 555 EVT Ty = N->getValueType(0); 556 unsigned LO = (Ty == MVT::i32) ? Mips::LO0 : Mips::LO0_64; 557 unsigned HI = (Ty == MVT::i32) ? Mips::HI0 : Mips::HI0_64; 558 unsigned Opc = N->getOpcode() == ISD::SDIVREM ? MipsISD::DivRem16 : 559 MipsISD::DivRemU16; 560 SDLoc DL(N); 561 562 SDValue DivRem = DAG.getNode(Opc, DL, MVT::Glue, 563 N->getOperand(0), N->getOperand(1)); 564 SDValue InChain = DAG.getEntryNode(); 565 SDValue InGlue = DivRem; 566 567 // insert MFLO 568 if (N->hasAnyUseOfValue(0)) { 569 SDValue CopyFromLo = DAG.getCopyFromReg(InChain, DL, LO, Ty, 570 InGlue); 571 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), CopyFromLo); 572 InChain = CopyFromLo.getValue(1); 573 InGlue = CopyFromLo.getValue(2); 574 } 575 576 // insert MFHI 577 if (N->hasAnyUseOfValue(1)) { 578 SDValue CopyFromHi = DAG.getCopyFromReg(InChain, DL, 579 HI, Ty, InGlue); 580 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), CopyFromHi); 581 } 582 583 return SDValue(); 584 } 585 586 static Mips::CondCode condCodeToFCC(ISD::CondCode CC) { 587 switch (CC) { 588 default: llvm_unreachable("Unknown fp condition code!"); 589 case ISD::SETEQ: 590 case ISD::SETOEQ: return Mips::FCOND_OEQ; 591 case ISD::SETUNE: return Mips::FCOND_UNE; 592 case ISD::SETLT: 593 case ISD::SETOLT: return Mips::FCOND_OLT; 594 case ISD::SETGT: 595 case ISD::SETOGT: return Mips::FCOND_OGT; 596 case ISD::SETLE: 597 case ISD::SETOLE: return Mips::FCOND_OLE; 598 case ISD::SETGE: 599 case ISD::SETOGE: return Mips::FCOND_OGE; 600 case ISD::SETULT: return Mips::FCOND_ULT; 601 case ISD::SETULE: return Mips::FCOND_ULE; 602 case ISD::SETUGT: return Mips::FCOND_UGT; 603 case ISD::SETUGE: return Mips::FCOND_UGE; 604 case ISD::SETUO: return Mips::FCOND_UN; 605 case ISD::SETO: return Mips::FCOND_OR; 606 case ISD::SETNE: 607 case ISD::SETONE: return Mips::FCOND_ONE; 608 case ISD::SETUEQ: return Mips::FCOND_UEQ; 609 } 610 } 611 612 /// This function returns true if the floating point conditional branches and 613 /// conditional moves which use condition code CC should be inverted. 614 static bool invertFPCondCodeUser(Mips::CondCode CC) { 615 if (CC >= Mips::FCOND_F && CC <= Mips::FCOND_NGT) 616 return false; 617 618 assert((CC >= Mips::FCOND_T && CC <= Mips::FCOND_GT) && 619 "Illegal Condition Code"); 620 621 return true; 622 } 623 624 // Creates and returns an FPCmp node from a setcc node. 625 // Returns Op if setcc is not a floating point comparison. 626 static SDValue createFPCmp(SelectionDAG &DAG, const SDValue &Op) { 627 // must be a SETCC node 628 if (Op.getOpcode() != ISD::SETCC) 629 return Op; 630 631 SDValue LHS = Op.getOperand(0); 632 633 if (!LHS.getValueType().isFloatingPoint()) 634 return Op; 635 636 SDValue RHS = Op.getOperand(1); 637 SDLoc DL(Op); 638 639 // Assume the 3rd operand is a CondCodeSDNode. Add code to check the type of 640 // node if necessary. 641 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get(); 642 643 return DAG.getNode(MipsISD::FPCmp, DL, MVT::Glue, LHS, RHS, 644 DAG.getConstant(condCodeToFCC(CC), DL, MVT::i32)); 645 } 646 647 // Creates and returns a CMovFPT/F node. 648 static SDValue createCMovFP(SelectionDAG &DAG, SDValue Cond, SDValue True, 649 SDValue False, const SDLoc &DL) { 650 ConstantSDNode *CC = cast<ConstantSDNode>(Cond.getOperand(2)); 651 bool invert = invertFPCondCodeUser((Mips::CondCode)CC->getSExtValue()); 652 SDValue FCC0 = DAG.getRegister(Mips::FCC0, MVT::i32); 653 654 return DAG.getNode((invert ? MipsISD::CMovFP_F : MipsISD::CMovFP_T), DL, 655 True.getValueType(), True, FCC0, False, Cond); 656 } 657 658 static SDValue performSELECTCombine(SDNode *N, SelectionDAG &DAG, 659 TargetLowering::DAGCombinerInfo &DCI, 660 const MipsSubtarget &Subtarget) { 661 if (DCI.isBeforeLegalizeOps()) 662 return SDValue(); 663 664 SDValue SetCC = N->getOperand(0); 665 666 if ((SetCC.getOpcode() != ISD::SETCC) || 667 !SetCC.getOperand(0).getValueType().isInteger()) 668 return SDValue(); 669 670 SDValue False = N->getOperand(2); 671 EVT FalseTy = False.getValueType(); 672 673 if (!FalseTy.isInteger()) 674 return SDValue(); 675 676 ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(False); 677 678 // If the RHS (False) is 0, we swap the order of the operands 679 // of ISD::SELECT (obviously also inverting the condition) so that we can 680 // take advantage of conditional moves using the $0 register. 681 // Example: 682 // return (a != 0) ? x : 0; 683 // load $reg, x 684 // movz $reg, $0, a 685 if (!FalseC) 686 return SDValue(); 687 688 const SDLoc DL(N); 689 690 if (!FalseC->getZExtValue()) { 691 ISD::CondCode CC = cast<CondCodeSDNode>(SetCC.getOperand(2))->get(); 692 SDValue True = N->getOperand(1); 693 694 SetCC = DAG.getSetCC(DL, SetCC.getValueType(), SetCC.getOperand(0), 695 SetCC.getOperand(1), 696 ISD::getSetCCInverse(CC, SetCC.getValueType())); 697 698 return DAG.getNode(ISD::SELECT, DL, FalseTy, SetCC, False, True); 699 } 700 701 // If both operands are integer constants there's a possibility that we 702 // can do some interesting optimizations. 703 SDValue True = N->getOperand(1); 704 ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(True); 705 706 if (!TrueC || !True.getValueType().isInteger()) 707 return SDValue(); 708 709 // We'll also ignore MVT::i64 operands as this optimizations proves 710 // to be ineffective because of the required sign extensions as the result 711 // of a SETCC operator is always MVT::i32 for non-vector types. 712 if (True.getValueType() == MVT::i64) 713 return SDValue(); 714 715 int64_t Diff = TrueC->getSExtValue() - FalseC->getSExtValue(); 716 717 // 1) (a < x) ? y : y-1 718 // slti $reg1, a, x 719 // addiu $reg2, $reg1, y-1 720 if (Diff == 1) 721 return DAG.getNode(ISD::ADD, DL, SetCC.getValueType(), SetCC, False); 722 723 // 2) (a < x) ? y-1 : y 724 // slti $reg1, a, x 725 // xor $reg1, $reg1, 1 726 // addiu $reg2, $reg1, y-1 727 if (Diff == -1) { 728 ISD::CondCode CC = cast<CondCodeSDNode>(SetCC.getOperand(2))->get(); 729 SetCC = DAG.getSetCC(DL, SetCC.getValueType(), SetCC.getOperand(0), 730 SetCC.getOperand(1), 731 ISD::getSetCCInverse(CC, SetCC.getValueType())); 732 return DAG.getNode(ISD::ADD, DL, SetCC.getValueType(), SetCC, True); 733 } 734 735 // Could not optimize. 736 return SDValue(); 737 } 738 739 static SDValue performCMovFPCombine(SDNode *N, SelectionDAG &DAG, 740 TargetLowering::DAGCombinerInfo &DCI, 741 const MipsSubtarget &Subtarget) { 742 if (DCI.isBeforeLegalizeOps()) 743 return SDValue(); 744 745 SDValue ValueIfTrue = N->getOperand(0), ValueIfFalse = N->getOperand(2); 746 747 ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(ValueIfFalse); 748 if (!FalseC || FalseC->getZExtValue()) 749 return SDValue(); 750 751 // Since RHS (False) is 0, we swap the order of the True/False operands 752 // (obviously also inverting the condition) so that we can 753 // take advantage of conditional moves using the $0 register. 754 // Example: 755 // return (a != 0) ? x : 0; 756 // load $reg, x 757 // movz $reg, $0, a 758 unsigned Opc = (N->getOpcode() == MipsISD::CMovFP_T) ? MipsISD::CMovFP_F : 759 MipsISD::CMovFP_T; 760 761 SDValue FCC = N->getOperand(1), Glue = N->getOperand(3); 762 return DAG.getNode(Opc, SDLoc(N), ValueIfFalse.getValueType(), 763 ValueIfFalse, FCC, ValueIfTrue, Glue); 764 } 765 766 static SDValue performANDCombine(SDNode *N, SelectionDAG &DAG, 767 TargetLowering::DAGCombinerInfo &DCI, 768 const MipsSubtarget &Subtarget) { 769 if (DCI.isBeforeLegalizeOps() || !Subtarget.hasExtractInsert()) 770 return SDValue(); 771 772 SDValue FirstOperand = N->getOperand(0); 773 unsigned FirstOperandOpc = FirstOperand.getOpcode(); 774 SDValue Mask = N->getOperand(1); 775 EVT ValTy = N->getValueType(0); 776 SDLoc DL(N); 777 778 uint64_t Pos = 0; 779 unsigned SMPos, SMSize; 780 ConstantSDNode *CN; 781 SDValue NewOperand; 782 unsigned Opc; 783 784 // Op's second operand must be a shifted mask. 785 if (!(CN = dyn_cast<ConstantSDNode>(Mask)) || 786 !isShiftedMask_64(CN->getZExtValue(), SMPos, SMSize)) 787 return SDValue(); 788 789 if (FirstOperandOpc == ISD::SRA || FirstOperandOpc == ISD::SRL) { 790 // Pattern match EXT. 791 // $dst = and ((sra or srl) $src , pos), (2**size - 1) 792 // => ext $dst, $src, pos, size 793 794 // The second operand of the shift must be an immediate. 795 if (!(CN = dyn_cast<ConstantSDNode>(FirstOperand.getOperand(1)))) 796 return SDValue(); 797 798 Pos = CN->getZExtValue(); 799 800 // Return if the shifted mask does not start at bit 0 or the sum of its size 801 // and Pos exceeds the word's size. 802 if (SMPos != 0 || Pos + SMSize > ValTy.getSizeInBits()) 803 return SDValue(); 804 805 Opc = MipsISD::Ext; 806 NewOperand = FirstOperand.getOperand(0); 807 } else if (FirstOperandOpc == ISD::SHL && Subtarget.hasCnMips()) { 808 // Pattern match CINS. 809 // $dst = and (shl $src , pos), mask 810 // => cins $dst, $src, pos, size 811 // mask is a shifted mask with consecutive 1's, pos = shift amount, 812 // size = population count. 813 814 // The second operand of the shift must be an immediate. 815 if (!(CN = dyn_cast<ConstantSDNode>(FirstOperand.getOperand(1)))) 816 return SDValue(); 817 818 Pos = CN->getZExtValue(); 819 820 if (SMPos != Pos || Pos >= ValTy.getSizeInBits() || SMSize >= 32 || 821 Pos + SMSize > ValTy.getSizeInBits()) 822 return SDValue(); 823 824 NewOperand = FirstOperand.getOperand(0); 825 // SMSize is 'location' (position) in this case, not size. 826 SMSize--; 827 Opc = MipsISD::CIns; 828 } else { 829 // Pattern match EXT. 830 // $dst = and $src, (2**size - 1) , if size > 16 831 // => ext $dst, $src, pos, size , pos = 0 832 833 // If the mask is <= 0xffff, andi can be used instead. 834 if (CN->getZExtValue() <= 0xffff) 835 return SDValue(); 836 837 // Return if the mask doesn't start at position 0. 838 if (SMPos) 839 return SDValue(); 840 841 Opc = MipsISD::Ext; 842 NewOperand = FirstOperand; 843 } 844 return DAG.getNode(Opc, DL, ValTy, NewOperand, 845 DAG.getConstant(Pos, DL, MVT::i32), 846 DAG.getConstant(SMSize, DL, MVT::i32)); 847 } 848 849 static SDValue performORCombine(SDNode *N, SelectionDAG &DAG, 850 TargetLowering::DAGCombinerInfo &DCI, 851 const MipsSubtarget &Subtarget) { 852 // Pattern match INS. 853 // $dst = or (and $src1 , mask0), (and (shl $src, pos), mask1), 854 // where mask1 = (2**size - 1) << pos, mask0 = ~mask1 855 // => ins $dst, $src, size, pos, $src1 856 if (DCI.isBeforeLegalizeOps() || !Subtarget.hasExtractInsert()) 857 return SDValue(); 858 859 SDValue And0 = N->getOperand(0), And1 = N->getOperand(1); 860 unsigned SMPos0, SMSize0, SMPos1, SMSize1; 861 ConstantSDNode *CN, *CN1; 862 863 // See if Op's first operand matches (and $src1 , mask0). 864 if (And0.getOpcode() != ISD::AND) 865 return SDValue(); 866 867 if (!(CN = dyn_cast<ConstantSDNode>(And0.getOperand(1))) || 868 !isShiftedMask_64(~CN->getSExtValue(), SMPos0, SMSize0)) 869 return SDValue(); 870 871 // See if Op's second operand matches (and (shl $src, pos), mask1). 872 if (And1.getOpcode() == ISD::AND && 873 And1.getOperand(0).getOpcode() == ISD::SHL) { 874 875 if (!(CN = dyn_cast<ConstantSDNode>(And1.getOperand(1))) || 876 !isShiftedMask_64(CN->getZExtValue(), SMPos1, SMSize1)) 877 return SDValue(); 878 879 // The shift masks must have the same position and size. 880 if (SMPos0 != SMPos1 || SMSize0 != SMSize1) 881 return SDValue(); 882 883 SDValue Shl = And1.getOperand(0); 884 885 if (!(CN = dyn_cast<ConstantSDNode>(Shl.getOperand(1)))) 886 return SDValue(); 887 888 unsigned Shamt = CN->getZExtValue(); 889 890 // Return if the shift amount and the first bit position of mask are not the 891 // same. 892 EVT ValTy = N->getValueType(0); 893 if ((Shamt != SMPos0) || (SMPos0 + SMSize0 > ValTy.getSizeInBits())) 894 return SDValue(); 895 896 SDLoc DL(N); 897 return DAG.getNode(MipsISD::Ins, DL, ValTy, Shl.getOperand(0), 898 DAG.getConstant(SMPos0, DL, MVT::i32), 899 DAG.getConstant(SMSize0, DL, MVT::i32), 900 And0.getOperand(0)); 901 } else { 902 // Pattern match DINS. 903 // $dst = or (and $src, mask0), mask1 904 // where mask0 = ((1 << SMSize0) -1) << SMPos0 905 // => dins $dst, $src, pos, size 906 if (~CN->getSExtValue() == ((((int64_t)1 << SMSize0) - 1) << SMPos0) && 907 ((SMSize0 + SMPos0 <= 64 && Subtarget.hasMips64r2()) || 908 (SMSize0 + SMPos0 <= 32))) { 909 // Check if AND instruction has constant as argument 910 bool isConstCase = And1.getOpcode() != ISD::AND; 911 if (And1.getOpcode() == ISD::AND) { 912 if (!(CN1 = dyn_cast<ConstantSDNode>(And1->getOperand(1)))) 913 return SDValue(); 914 } else { 915 if (!(CN1 = dyn_cast<ConstantSDNode>(N->getOperand(1)))) 916 return SDValue(); 917 } 918 // Don't generate INS if constant OR operand doesn't fit into bits 919 // cleared by constant AND operand. 920 if (CN->getSExtValue() & CN1->getSExtValue()) 921 return SDValue(); 922 923 SDLoc DL(N); 924 EVT ValTy = N->getOperand(0)->getValueType(0); 925 SDValue Const1; 926 SDValue SrlX; 927 if (!isConstCase) { 928 Const1 = DAG.getConstant(SMPos0, DL, MVT::i32); 929 SrlX = DAG.getNode(ISD::SRL, DL, And1->getValueType(0), And1, Const1); 930 } 931 return DAG.getNode( 932 MipsISD::Ins, DL, N->getValueType(0), 933 isConstCase 934 ? DAG.getConstant(CN1->getSExtValue() >> SMPos0, DL, ValTy) 935 : SrlX, 936 DAG.getConstant(SMPos0, DL, MVT::i32), 937 DAG.getConstant(ValTy.getSizeInBits() / 8 < 8 ? SMSize0 & 31 938 : SMSize0, 939 DL, MVT::i32), 940 And0->getOperand(0)); 941 942 } 943 return SDValue(); 944 } 945 } 946 947 static SDValue performMADD_MSUBCombine(SDNode *ROOTNode, SelectionDAG &CurDAG, 948 const MipsSubtarget &Subtarget) { 949 // ROOTNode must have a multiplication as an operand for the match to be 950 // successful. 951 if (ROOTNode->getOperand(0).getOpcode() != ISD::MUL && 952 ROOTNode->getOperand(1).getOpcode() != ISD::MUL) 953 return SDValue(); 954 955 // We don't handle vector types here. 956 if (ROOTNode->getValueType(0).isVector()) 957 return SDValue(); 958 959 // For MIPS64, madd / msub instructions are inefficent to use with 64 bit 960 // arithmetic. E.g. 961 // (add (mul a b) c) => 962 // let res = (madd (mthi (drotr c 32))x(mtlo c) a b) in 963 // MIPS64: (or (dsll (mfhi res) 32) (dsrl (dsll (mflo res) 32) 32) 964 // or 965 // MIPS64R2: (dins (mflo res) (mfhi res) 32 32) 966 // 967 // The overhead of setting up the Hi/Lo registers and reassembling the 968 // result makes this a dubious optimzation for MIPS64. The core of the 969 // problem is that Hi/Lo contain the upper and lower 32 bits of the 970 // operand and result. 971 // 972 // It requires a chain of 4 add/mul for MIPS64R2 to get better code 973 // density than doing it naively, 5 for MIPS64. Additionally, using 974 // madd/msub on MIPS64 requires the operands actually be 32 bit sign 975 // extended operands, not true 64 bit values. 976 // 977 // FIXME: For the moment, disable this completely for MIPS64. 978 if (Subtarget.hasMips64()) 979 return SDValue(); 980 981 SDValue Mult = ROOTNode->getOperand(0).getOpcode() == ISD::MUL 982 ? ROOTNode->getOperand(0) 983 : ROOTNode->getOperand(1); 984 985 SDValue AddOperand = ROOTNode->getOperand(0).getOpcode() == ISD::MUL 986 ? ROOTNode->getOperand(1) 987 : ROOTNode->getOperand(0); 988 989 // Transform this to a MADD only if the user of this node is the add. 990 // If there are other users of the mul, this function returns here. 991 if (!Mult.hasOneUse()) 992 return SDValue(); 993 994 // maddu and madd are unusual instructions in that on MIPS64 bits 63..31 995 // must be in canonical form, i.e. sign extended. For MIPS32, the operands 996 // of the multiply must have 32 or more sign bits, otherwise we cannot 997 // perform this optimization. We have to check this here as we're performing 998 // this optimization pre-legalization. 999 SDValue MultLHS = Mult->getOperand(0); 1000 SDValue MultRHS = Mult->getOperand(1); 1001 1002 bool IsSigned = MultLHS->getOpcode() == ISD::SIGN_EXTEND && 1003 MultRHS->getOpcode() == ISD::SIGN_EXTEND; 1004 bool IsUnsigned = MultLHS->getOpcode() == ISD::ZERO_EXTEND && 1005 MultRHS->getOpcode() == ISD::ZERO_EXTEND; 1006 1007 if (!IsSigned && !IsUnsigned) 1008 return SDValue(); 1009 1010 // Initialize accumulator. 1011 SDLoc DL(ROOTNode); 1012 SDValue TopHalf; 1013 SDValue BottomHalf; 1014 BottomHalf = CurDAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32, AddOperand, 1015 CurDAG.getIntPtrConstant(0, DL)); 1016 1017 TopHalf = CurDAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32, AddOperand, 1018 CurDAG.getIntPtrConstant(1, DL)); 1019 SDValue ACCIn = CurDAG.getNode(MipsISD::MTLOHI, DL, MVT::Untyped, 1020 BottomHalf, 1021 TopHalf); 1022 1023 // Create MipsMAdd(u) / MipsMSub(u) node. 1024 bool IsAdd = ROOTNode->getOpcode() == ISD::ADD; 1025 unsigned Opcode = IsAdd ? (IsUnsigned ? MipsISD::MAddu : MipsISD::MAdd) 1026 : (IsUnsigned ? MipsISD::MSubu : MipsISD::MSub); 1027 SDValue MAddOps[3] = { 1028 CurDAG.getNode(ISD::TRUNCATE, DL, MVT::i32, Mult->getOperand(0)), 1029 CurDAG.getNode(ISD::TRUNCATE, DL, MVT::i32, Mult->getOperand(1)), ACCIn}; 1030 EVT VTs[2] = {MVT::i32, MVT::i32}; 1031 SDValue MAdd = CurDAG.getNode(Opcode, DL, VTs, MAddOps); 1032 1033 SDValue ResLo = CurDAG.getNode(MipsISD::MFLO, DL, MVT::i32, MAdd); 1034 SDValue ResHi = CurDAG.getNode(MipsISD::MFHI, DL, MVT::i32, MAdd); 1035 SDValue Combined = 1036 CurDAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, ResLo, ResHi); 1037 return Combined; 1038 } 1039 1040 static SDValue performSUBCombine(SDNode *N, SelectionDAG &DAG, 1041 TargetLowering::DAGCombinerInfo &DCI, 1042 const MipsSubtarget &Subtarget) { 1043 // (sub v0 (mul v1, v2)) => (msub v1, v2, v0) 1044 if (DCI.isBeforeLegalizeOps()) { 1045 if (Subtarget.hasMips32() && !Subtarget.hasMips32r6() && 1046 !Subtarget.inMips16Mode() && N->getValueType(0) == MVT::i64) 1047 return performMADD_MSUBCombine(N, DAG, Subtarget); 1048 1049 return SDValue(); 1050 } 1051 1052 return SDValue(); 1053 } 1054 1055 static SDValue performADDCombine(SDNode *N, SelectionDAG &DAG, 1056 TargetLowering::DAGCombinerInfo &DCI, 1057 const MipsSubtarget &Subtarget) { 1058 // (add v0 (mul v1, v2)) => (madd v1, v2, v0) 1059 if (DCI.isBeforeLegalizeOps()) { 1060 if (Subtarget.hasMips32() && !Subtarget.hasMips32r6() && 1061 !Subtarget.inMips16Mode() && N->getValueType(0) == MVT::i64) 1062 return performMADD_MSUBCombine(N, DAG, Subtarget); 1063 1064 return SDValue(); 1065 } 1066 1067 // (add v0, (add v1, abs_lo(tjt))) => (add (add v0, v1), abs_lo(tjt)) 1068 SDValue Add = N->getOperand(1); 1069 1070 if (Add.getOpcode() != ISD::ADD) 1071 return SDValue(); 1072 1073 SDValue Lo = Add.getOperand(1); 1074 1075 if ((Lo.getOpcode() != MipsISD::Lo) || 1076 (Lo.getOperand(0).getOpcode() != ISD::TargetJumpTable)) 1077 return SDValue(); 1078 1079 EVT ValTy = N->getValueType(0); 1080 SDLoc DL(N); 1081 1082 SDValue Add1 = DAG.getNode(ISD::ADD, DL, ValTy, N->getOperand(0), 1083 Add.getOperand(0)); 1084 return DAG.getNode(ISD::ADD, DL, ValTy, Add1, Lo); 1085 } 1086 1087 static SDValue performSHLCombine(SDNode *N, SelectionDAG &DAG, 1088 TargetLowering::DAGCombinerInfo &DCI, 1089 const MipsSubtarget &Subtarget) { 1090 // Pattern match CINS. 1091 // $dst = shl (and $src , imm), pos 1092 // => cins $dst, $src, pos, size 1093 1094 if (DCI.isBeforeLegalizeOps() || !Subtarget.hasCnMips()) 1095 return SDValue(); 1096 1097 SDValue FirstOperand = N->getOperand(0); 1098 unsigned FirstOperandOpc = FirstOperand.getOpcode(); 1099 SDValue SecondOperand = N->getOperand(1); 1100 EVT ValTy = N->getValueType(0); 1101 SDLoc DL(N); 1102 1103 uint64_t Pos = 0; 1104 unsigned SMPos, SMSize; 1105 ConstantSDNode *CN; 1106 SDValue NewOperand; 1107 1108 // The second operand of the shift must be an immediate. 1109 if (!(CN = dyn_cast<ConstantSDNode>(SecondOperand))) 1110 return SDValue(); 1111 1112 Pos = CN->getZExtValue(); 1113 1114 if (Pos >= ValTy.getSizeInBits()) 1115 return SDValue(); 1116 1117 if (FirstOperandOpc != ISD::AND) 1118 return SDValue(); 1119 1120 // AND's second operand must be a shifted mask. 1121 if (!(CN = dyn_cast<ConstantSDNode>(FirstOperand.getOperand(1))) || 1122 !isShiftedMask_64(CN->getZExtValue(), SMPos, SMSize)) 1123 return SDValue(); 1124 1125 // Return if the shifted mask does not start at bit 0 or the sum of its size 1126 // and Pos exceeds the word's size. 1127 if (SMPos != 0 || SMSize > 32 || Pos + SMSize > ValTy.getSizeInBits()) 1128 return SDValue(); 1129 1130 NewOperand = FirstOperand.getOperand(0); 1131 // SMSize is 'location' (position) in this case, not size. 1132 SMSize--; 1133 1134 return DAG.getNode(MipsISD::CIns, DL, ValTy, NewOperand, 1135 DAG.getConstant(Pos, DL, MVT::i32), 1136 DAG.getConstant(SMSize, DL, MVT::i32)); 1137 } 1138 1139 SDValue MipsTargetLowering::PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) 1140 const { 1141 SelectionDAG &DAG = DCI.DAG; 1142 unsigned Opc = N->getOpcode(); 1143 1144 switch (Opc) { 1145 default: break; 1146 case ISD::SDIVREM: 1147 case ISD::UDIVREM: 1148 return performDivRemCombine(N, DAG, DCI, Subtarget); 1149 case ISD::SELECT: 1150 return performSELECTCombine(N, DAG, DCI, Subtarget); 1151 case MipsISD::CMovFP_F: 1152 case MipsISD::CMovFP_T: 1153 return performCMovFPCombine(N, DAG, DCI, Subtarget); 1154 case ISD::AND: 1155 return performANDCombine(N, DAG, DCI, Subtarget); 1156 case ISD::OR: 1157 return performORCombine(N, DAG, DCI, Subtarget); 1158 case ISD::ADD: 1159 return performADDCombine(N, DAG, DCI, Subtarget); 1160 case ISD::SHL: 1161 return performSHLCombine(N, DAG, DCI, Subtarget); 1162 case ISD::SUB: 1163 return performSUBCombine(N, DAG, DCI, Subtarget); 1164 } 1165 1166 return SDValue(); 1167 } 1168 1169 bool MipsTargetLowering::isCheapToSpeculateCttz() const { 1170 return Subtarget.hasMips32(); 1171 } 1172 1173 bool MipsTargetLowering::isCheapToSpeculateCtlz() const { 1174 return Subtarget.hasMips32(); 1175 } 1176 1177 bool MipsTargetLowering::shouldFoldConstantShiftPairToMask( 1178 const SDNode *N, CombineLevel Level) const { 1179 if (N->getOperand(0).getValueType().isVector()) 1180 return false; 1181 return true; 1182 } 1183 1184 void 1185 MipsTargetLowering::ReplaceNodeResults(SDNode *N, 1186 SmallVectorImpl<SDValue> &Results, 1187 SelectionDAG &DAG) const { 1188 return LowerOperationWrapper(N, Results, DAG); 1189 } 1190 1191 SDValue MipsTargetLowering:: 1192 LowerOperation(SDValue Op, SelectionDAG &DAG) const 1193 { 1194 switch (Op.getOpcode()) 1195 { 1196 case ISD::BRCOND: return lowerBRCOND(Op, DAG); 1197 case ISD::ConstantPool: return lowerConstantPool(Op, DAG); 1198 case ISD::GlobalAddress: return lowerGlobalAddress(Op, DAG); 1199 case ISD::BlockAddress: return lowerBlockAddress(Op, DAG); 1200 case ISD::GlobalTLSAddress: return lowerGlobalTLSAddress(Op, DAG); 1201 case ISD::JumpTable: return lowerJumpTable(Op, DAG); 1202 case ISD::SELECT: return lowerSELECT(Op, DAG); 1203 case ISD::SETCC: return lowerSETCC(Op, DAG); 1204 case ISD::VASTART: return lowerVASTART(Op, DAG); 1205 case ISD::VAARG: return lowerVAARG(Op, DAG); 1206 case ISD::FCOPYSIGN: return lowerFCOPYSIGN(Op, DAG); 1207 case ISD::FABS: return lowerFABS(Op, DAG); 1208 case ISD::FRAMEADDR: return lowerFRAMEADDR(Op, DAG); 1209 case ISD::RETURNADDR: return lowerRETURNADDR(Op, DAG); 1210 case ISD::EH_RETURN: return lowerEH_RETURN(Op, DAG); 1211 case ISD::ATOMIC_FENCE: return lowerATOMIC_FENCE(Op, DAG); 1212 case ISD::SHL_PARTS: return lowerShiftLeftParts(Op, DAG); 1213 case ISD::SRA_PARTS: return lowerShiftRightParts(Op, DAG, true); 1214 case ISD::SRL_PARTS: return lowerShiftRightParts(Op, DAG, false); 1215 case ISD::LOAD: return lowerLOAD(Op, DAG); 1216 case ISD::STORE: return lowerSTORE(Op, DAG); 1217 case ISD::EH_DWARF_CFA: return lowerEH_DWARF_CFA(Op, DAG); 1218 case ISD::FP_TO_SINT: return lowerFP_TO_SINT(Op, DAG); 1219 } 1220 return SDValue(); 1221 } 1222 1223 //===----------------------------------------------------------------------===// 1224 // Lower helper functions 1225 //===----------------------------------------------------------------------===// 1226 1227 // addLiveIn - This helper function adds the specified physical register to the 1228 // MachineFunction as a live in value. It also creates a corresponding 1229 // virtual register for it. 1230 static unsigned 1231 addLiveIn(MachineFunction &MF, unsigned PReg, const TargetRegisterClass *RC) 1232 { 1233 Register VReg = MF.getRegInfo().createVirtualRegister(RC); 1234 MF.getRegInfo().addLiveIn(PReg, VReg); 1235 return VReg; 1236 } 1237 1238 static MachineBasicBlock *insertDivByZeroTrap(MachineInstr &MI, 1239 MachineBasicBlock &MBB, 1240 const TargetInstrInfo &TII, 1241 bool Is64Bit, bool IsMicroMips) { 1242 if (NoZeroDivCheck) 1243 return &MBB; 1244 1245 // Insert instruction "teq $divisor_reg, $zero, 7". 1246 MachineBasicBlock::iterator I(MI); 1247 MachineInstrBuilder MIB; 1248 MachineOperand &Divisor = MI.getOperand(2); 1249 MIB = BuildMI(MBB, std::next(I), MI.getDebugLoc(), 1250 TII.get(IsMicroMips ? Mips::TEQ_MM : Mips::TEQ)) 1251 .addReg(Divisor.getReg(), getKillRegState(Divisor.isKill())) 1252 .addReg(Mips::ZERO) 1253 .addImm(7); 1254 1255 // Use the 32-bit sub-register if this is a 64-bit division. 1256 if (Is64Bit) 1257 MIB->getOperand(0).setSubReg(Mips::sub_32); 1258 1259 // Clear Divisor's kill flag. 1260 Divisor.setIsKill(false); 1261 1262 // We would normally delete the original instruction here but in this case 1263 // we only needed to inject an additional instruction rather than replace it. 1264 1265 return &MBB; 1266 } 1267 1268 MachineBasicBlock * 1269 MipsTargetLowering::EmitInstrWithCustomInserter(MachineInstr &MI, 1270 MachineBasicBlock *BB) const { 1271 switch (MI.getOpcode()) { 1272 default: 1273 llvm_unreachable("Unexpected instr type to insert"); 1274 case Mips::ATOMIC_LOAD_ADD_I8: 1275 return emitAtomicBinaryPartword(MI, BB, 1); 1276 case Mips::ATOMIC_LOAD_ADD_I16: 1277 return emitAtomicBinaryPartword(MI, BB, 2); 1278 case Mips::ATOMIC_LOAD_ADD_I32: 1279 return emitAtomicBinary(MI, BB); 1280 case Mips::ATOMIC_LOAD_ADD_I64: 1281 return emitAtomicBinary(MI, BB); 1282 1283 case Mips::ATOMIC_LOAD_AND_I8: 1284 return emitAtomicBinaryPartword(MI, BB, 1); 1285 case Mips::ATOMIC_LOAD_AND_I16: 1286 return emitAtomicBinaryPartword(MI, BB, 2); 1287 case Mips::ATOMIC_LOAD_AND_I32: 1288 return emitAtomicBinary(MI, BB); 1289 case Mips::ATOMIC_LOAD_AND_I64: 1290 return emitAtomicBinary(MI, BB); 1291 1292 case Mips::ATOMIC_LOAD_OR_I8: 1293 return emitAtomicBinaryPartword(MI, BB, 1); 1294 case Mips::ATOMIC_LOAD_OR_I16: 1295 return emitAtomicBinaryPartword(MI, BB, 2); 1296 case Mips::ATOMIC_LOAD_OR_I32: 1297 return emitAtomicBinary(MI, BB); 1298 case Mips::ATOMIC_LOAD_OR_I64: 1299 return emitAtomicBinary(MI, BB); 1300 1301 case Mips::ATOMIC_LOAD_XOR_I8: 1302 return emitAtomicBinaryPartword(MI, BB, 1); 1303 case Mips::ATOMIC_LOAD_XOR_I16: 1304 return emitAtomicBinaryPartword(MI, BB, 2); 1305 case Mips::ATOMIC_LOAD_XOR_I32: 1306 return emitAtomicBinary(MI, BB); 1307 case Mips::ATOMIC_LOAD_XOR_I64: 1308 return emitAtomicBinary(MI, BB); 1309 1310 case Mips::ATOMIC_LOAD_NAND_I8: 1311 return emitAtomicBinaryPartword(MI, BB, 1); 1312 case Mips::ATOMIC_LOAD_NAND_I16: 1313 return emitAtomicBinaryPartword(MI, BB, 2); 1314 case Mips::ATOMIC_LOAD_NAND_I32: 1315 return emitAtomicBinary(MI, BB); 1316 case Mips::ATOMIC_LOAD_NAND_I64: 1317 return emitAtomicBinary(MI, BB); 1318 1319 case Mips::ATOMIC_LOAD_SUB_I8: 1320 return emitAtomicBinaryPartword(MI, BB, 1); 1321 case Mips::ATOMIC_LOAD_SUB_I16: 1322 return emitAtomicBinaryPartword(MI, BB, 2); 1323 case Mips::ATOMIC_LOAD_SUB_I32: 1324 return emitAtomicBinary(MI, BB); 1325 case Mips::ATOMIC_LOAD_SUB_I64: 1326 return emitAtomicBinary(MI, BB); 1327 1328 case Mips::ATOMIC_SWAP_I8: 1329 return emitAtomicBinaryPartword(MI, BB, 1); 1330 case Mips::ATOMIC_SWAP_I16: 1331 return emitAtomicBinaryPartword(MI, BB, 2); 1332 case Mips::ATOMIC_SWAP_I32: 1333 return emitAtomicBinary(MI, BB); 1334 case Mips::ATOMIC_SWAP_I64: 1335 return emitAtomicBinary(MI, BB); 1336 1337 case Mips::ATOMIC_CMP_SWAP_I8: 1338 return emitAtomicCmpSwapPartword(MI, BB, 1); 1339 case Mips::ATOMIC_CMP_SWAP_I16: 1340 return emitAtomicCmpSwapPartword(MI, BB, 2); 1341 case Mips::ATOMIC_CMP_SWAP_I32: 1342 return emitAtomicCmpSwap(MI, BB); 1343 case Mips::ATOMIC_CMP_SWAP_I64: 1344 return emitAtomicCmpSwap(MI, BB); 1345 1346 case Mips::ATOMIC_LOAD_MIN_I8: 1347 return emitAtomicBinaryPartword(MI, BB, 1); 1348 case Mips::ATOMIC_LOAD_MIN_I16: 1349 return emitAtomicBinaryPartword(MI, BB, 2); 1350 case Mips::ATOMIC_LOAD_MIN_I32: 1351 return emitAtomicBinary(MI, BB); 1352 case Mips::ATOMIC_LOAD_MIN_I64: 1353 return emitAtomicBinary(MI, BB); 1354 1355 case Mips::ATOMIC_LOAD_MAX_I8: 1356 return emitAtomicBinaryPartword(MI, BB, 1); 1357 case Mips::ATOMIC_LOAD_MAX_I16: 1358 return emitAtomicBinaryPartword(MI, BB, 2); 1359 case Mips::ATOMIC_LOAD_MAX_I32: 1360 return emitAtomicBinary(MI, BB); 1361 case Mips::ATOMIC_LOAD_MAX_I64: 1362 return emitAtomicBinary(MI, BB); 1363 1364 case Mips::ATOMIC_LOAD_UMIN_I8: 1365 return emitAtomicBinaryPartword(MI, BB, 1); 1366 case Mips::ATOMIC_LOAD_UMIN_I16: 1367 return emitAtomicBinaryPartword(MI, BB, 2); 1368 case Mips::ATOMIC_LOAD_UMIN_I32: 1369 return emitAtomicBinary(MI, BB); 1370 case Mips::ATOMIC_LOAD_UMIN_I64: 1371 return emitAtomicBinary(MI, BB); 1372 1373 case Mips::ATOMIC_LOAD_UMAX_I8: 1374 return emitAtomicBinaryPartword(MI, BB, 1); 1375 case Mips::ATOMIC_LOAD_UMAX_I16: 1376 return emitAtomicBinaryPartword(MI, BB, 2); 1377 case Mips::ATOMIC_LOAD_UMAX_I32: 1378 return emitAtomicBinary(MI, BB); 1379 case Mips::ATOMIC_LOAD_UMAX_I64: 1380 return emitAtomicBinary(MI, BB); 1381 1382 case Mips::PseudoSDIV: 1383 case Mips::PseudoUDIV: 1384 case Mips::DIV: 1385 case Mips::DIVU: 1386 case Mips::MOD: 1387 case Mips::MODU: 1388 return insertDivByZeroTrap(MI, *BB, *Subtarget.getInstrInfo(), false, 1389 false); 1390 case Mips::SDIV_MM_Pseudo: 1391 case Mips::UDIV_MM_Pseudo: 1392 case Mips::SDIV_MM: 1393 case Mips::UDIV_MM: 1394 case Mips::DIV_MMR6: 1395 case Mips::DIVU_MMR6: 1396 case Mips::MOD_MMR6: 1397 case Mips::MODU_MMR6: 1398 return insertDivByZeroTrap(MI, *BB, *Subtarget.getInstrInfo(), false, true); 1399 case Mips::PseudoDSDIV: 1400 case Mips::PseudoDUDIV: 1401 case Mips::DDIV: 1402 case Mips::DDIVU: 1403 case Mips::DMOD: 1404 case Mips::DMODU: 1405 return insertDivByZeroTrap(MI, *BB, *Subtarget.getInstrInfo(), true, false); 1406 1407 case Mips::PseudoSELECT_I: 1408 case Mips::PseudoSELECT_I64: 1409 case Mips::PseudoSELECT_S: 1410 case Mips::PseudoSELECT_D32: 1411 case Mips::PseudoSELECT_D64: 1412 return emitPseudoSELECT(MI, BB, false, Mips::BNE); 1413 case Mips::PseudoSELECTFP_F_I: 1414 case Mips::PseudoSELECTFP_F_I64: 1415 case Mips::PseudoSELECTFP_F_S: 1416 case Mips::PseudoSELECTFP_F_D32: 1417 case Mips::PseudoSELECTFP_F_D64: 1418 return emitPseudoSELECT(MI, BB, true, Mips::BC1F); 1419 case Mips::PseudoSELECTFP_T_I: 1420 case Mips::PseudoSELECTFP_T_I64: 1421 case Mips::PseudoSELECTFP_T_S: 1422 case Mips::PseudoSELECTFP_T_D32: 1423 case Mips::PseudoSELECTFP_T_D64: 1424 return emitPseudoSELECT(MI, BB, true, Mips::BC1T); 1425 case Mips::PseudoD_SELECT_I: 1426 case Mips::PseudoD_SELECT_I64: 1427 return emitPseudoD_SELECT(MI, BB); 1428 case Mips::LDR_W: 1429 return emitLDR_W(MI, BB); 1430 case Mips::LDR_D: 1431 return emitLDR_D(MI, BB); 1432 case Mips::STR_W: 1433 return emitSTR_W(MI, BB); 1434 case Mips::STR_D: 1435 return emitSTR_D(MI, BB); 1436 } 1437 } 1438 1439 // This function also handles Mips::ATOMIC_SWAP_I32 (when BinOpcode == 0), and 1440 // Mips::ATOMIC_LOAD_NAND_I32 (when Nand == true) 1441 MachineBasicBlock * 1442 MipsTargetLowering::emitAtomicBinary(MachineInstr &MI, 1443 MachineBasicBlock *BB) const { 1444 1445 MachineFunction *MF = BB->getParent(); 1446 MachineRegisterInfo &RegInfo = MF->getRegInfo(); 1447 const TargetInstrInfo *TII = Subtarget.getInstrInfo(); 1448 DebugLoc DL = MI.getDebugLoc(); 1449 1450 unsigned AtomicOp; 1451 bool NeedsAdditionalReg = false; 1452 switch (MI.getOpcode()) { 1453 case Mips::ATOMIC_LOAD_ADD_I32: 1454 AtomicOp = Mips::ATOMIC_LOAD_ADD_I32_POSTRA; 1455 break; 1456 case Mips::ATOMIC_LOAD_SUB_I32: 1457 AtomicOp = Mips::ATOMIC_LOAD_SUB_I32_POSTRA; 1458 break; 1459 case Mips::ATOMIC_LOAD_AND_I32: 1460 AtomicOp = Mips::ATOMIC_LOAD_AND_I32_POSTRA; 1461 break; 1462 case Mips::ATOMIC_LOAD_OR_I32: 1463 AtomicOp = Mips::ATOMIC_LOAD_OR_I32_POSTRA; 1464 break; 1465 case Mips::ATOMIC_LOAD_XOR_I32: 1466 AtomicOp = Mips::ATOMIC_LOAD_XOR_I32_POSTRA; 1467 break; 1468 case Mips::ATOMIC_LOAD_NAND_I32: 1469 AtomicOp = Mips::ATOMIC_LOAD_NAND_I32_POSTRA; 1470 break; 1471 case Mips::ATOMIC_SWAP_I32: 1472 AtomicOp = Mips::ATOMIC_SWAP_I32_POSTRA; 1473 break; 1474 case Mips::ATOMIC_LOAD_ADD_I64: 1475 AtomicOp = Mips::ATOMIC_LOAD_ADD_I64_POSTRA; 1476 break; 1477 case Mips::ATOMIC_LOAD_SUB_I64: 1478 AtomicOp = Mips::ATOMIC_LOAD_SUB_I64_POSTRA; 1479 break; 1480 case Mips::ATOMIC_LOAD_AND_I64: 1481 AtomicOp = Mips::ATOMIC_LOAD_AND_I64_POSTRA; 1482 break; 1483 case Mips::ATOMIC_LOAD_OR_I64: 1484 AtomicOp = Mips::ATOMIC_LOAD_OR_I64_POSTRA; 1485 break; 1486 case Mips::ATOMIC_LOAD_XOR_I64: 1487 AtomicOp = Mips::ATOMIC_LOAD_XOR_I64_POSTRA; 1488 break; 1489 case Mips::ATOMIC_LOAD_NAND_I64: 1490 AtomicOp = Mips::ATOMIC_LOAD_NAND_I64_POSTRA; 1491 break; 1492 case Mips::ATOMIC_SWAP_I64: 1493 AtomicOp = Mips::ATOMIC_SWAP_I64_POSTRA; 1494 break; 1495 case Mips::ATOMIC_LOAD_MIN_I32: 1496 AtomicOp = Mips::ATOMIC_LOAD_MIN_I32_POSTRA; 1497 NeedsAdditionalReg = true; 1498 break; 1499 case Mips::ATOMIC_LOAD_MAX_I32: 1500 AtomicOp = Mips::ATOMIC_LOAD_MAX_I32_POSTRA; 1501 NeedsAdditionalReg = true; 1502 break; 1503 case Mips::ATOMIC_LOAD_UMIN_I32: 1504 AtomicOp = Mips::ATOMIC_LOAD_UMIN_I32_POSTRA; 1505 NeedsAdditionalReg = true; 1506 break; 1507 case Mips::ATOMIC_LOAD_UMAX_I32: 1508 AtomicOp = Mips::ATOMIC_LOAD_UMAX_I32_POSTRA; 1509 NeedsAdditionalReg = true; 1510 break; 1511 case Mips::ATOMIC_LOAD_MIN_I64: 1512 AtomicOp = Mips::ATOMIC_LOAD_MIN_I64_POSTRA; 1513 NeedsAdditionalReg = true; 1514 break; 1515 case Mips::ATOMIC_LOAD_MAX_I64: 1516 AtomicOp = Mips::ATOMIC_LOAD_MAX_I64_POSTRA; 1517 NeedsAdditionalReg = true; 1518 break; 1519 case Mips::ATOMIC_LOAD_UMIN_I64: 1520 AtomicOp = Mips::ATOMIC_LOAD_UMIN_I64_POSTRA; 1521 NeedsAdditionalReg = true; 1522 break; 1523 case Mips::ATOMIC_LOAD_UMAX_I64: 1524 AtomicOp = Mips::ATOMIC_LOAD_UMAX_I64_POSTRA; 1525 NeedsAdditionalReg = true; 1526 break; 1527 default: 1528 llvm_unreachable("Unknown pseudo atomic for replacement!"); 1529 } 1530 1531 Register OldVal = MI.getOperand(0).getReg(); 1532 Register Ptr = MI.getOperand(1).getReg(); 1533 Register Incr = MI.getOperand(2).getReg(); 1534 Register Scratch = RegInfo.createVirtualRegister(RegInfo.getRegClass(OldVal)); 1535 1536 MachineBasicBlock::iterator II(MI); 1537 1538 // The scratch registers here with the EarlyClobber | Define | Implicit 1539 // flags is used to persuade the register allocator and the machine 1540 // verifier to accept the usage of this register. This has to be a real 1541 // register which has an UNDEF value but is dead after the instruction which 1542 // is unique among the registers chosen for the instruction. 1543 1544 // The EarlyClobber flag has the semantic properties that the operand it is 1545 // attached to is clobbered before the rest of the inputs are read. Hence it 1546 // must be unique among the operands to the instruction. 1547 // The Define flag is needed to coerce the machine verifier that an Undef 1548 // value isn't a problem. 1549 // The Dead flag is needed as the value in scratch isn't used by any other 1550 // instruction. Kill isn't used as Dead is more precise. 1551 // The implicit flag is here due to the interaction between the other flags 1552 // and the machine verifier. 1553 1554 // For correctness purpose, a new pseudo is introduced here. We need this 1555 // new pseudo, so that FastRegisterAllocator does not see an ll/sc sequence 1556 // that is spread over >1 basic blocks. A register allocator which 1557 // introduces (or any codegen infact) a store, can violate the expectations 1558 // of the hardware. 1559 // 1560 // An atomic read-modify-write sequence starts with a linked load 1561 // instruction and ends with a store conditional instruction. The atomic 1562 // read-modify-write sequence fails if any of the following conditions 1563 // occur between the execution of ll and sc: 1564 // * A coherent store is completed by another process or coherent I/O 1565 // module into the block of synchronizable physical memory containing 1566 // the word. The size and alignment of the block is 1567 // implementation-dependent. 1568 // * A coherent store is executed between an LL and SC sequence on the 1569 // same processor to the block of synchornizable physical memory 1570 // containing the word. 1571 // 1572 1573 Register PtrCopy = RegInfo.createVirtualRegister(RegInfo.getRegClass(Ptr)); 1574 Register IncrCopy = RegInfo.createVirtualRegister(RegInfo.getRegClass(Incr)); 1575 1576 BuildMI(*BB, II, DL, TII->get(Mips::COPY), IncrCopy).addReg(Incr); 1577 BuildMI(*BB, II, DL, TII->get(Mips::COPY), PtrCopy).addReg(Ptr); 1578 1579 MachineInstrBuilder MIB = 1580 BuildMI(*BB, II, DL, TII->get(AtomicOp)) 1581 .addReg(OldVal, RegState::Define | RegState::EarlyClobber) 1582 .addReg(PtrCopy) 1583 .addReg(IncrCopy) 1584 .addReg(Scratch, RegState::Define | RegState::EarlyClobber | 1585 RegState::Implicit | RegState::Dead); 1586 if (NeedsAdditionalReg) { 1587 Register Scratch2 = 1588 RegInfo.createVirtualRegister(RegInfo.getRegClass(OldVal)); 1589 MIB.addReg(Scratch2, RegState::Define | RegState::EarlyClobber | 1590 RegState::Implicit | RegState::Dead); 1591 } 1592 1593 MI.eraseFromParent(); 1594 1595 return BB; 1596 } 1597 1598 MachineBasicBlock *MipsTargetLowering::emitSignExtendToI32InReg( 1599 MachineInstr &MI, MachineBasicBlock *BB, unsigned Size, unsigned DstReg, 1600 unsigned SrcReg) const { 1601 const TargetInstrInfo *TII = Subtarget.getInstrInfo(); 1602 const DebugLoc &DL = MI.getDebugLoc(); 1603 1604 if (Subtarget.hasMips32r2() && Size == 1) { 1605 BuildMI(BB, DL, TII->get(Mips::SEB), DstReg).addReg(SrcReg); 1606 return BB; 1607 } 1608 1609 if (Subtarget.hasMips32r2() && Size == 2) { 1610 BuildMI(BB, DL, TII->get(Mips::SEH), DstReg).addReg(SrcReg); 1611 return BB; 1612 } 1613 1614 MachineFunction *MF = BB->getParent(); 1615 MachineRegisterInfo &RegInfo = MF->getRegInfo(); 1616 const TargetRegisterClass *RC = getRegClassFor(MVT::i32); 1617 Register ScrReg = RegInfo.createVirtualRegister(RC); 1618 1619 assert(Size < 32); 1620 int64_t ShiftImm = 32 - (Size * 8); 1621 1622 BuildMI(BB, DL, TII->get(Mips::SLL), ScrReg).addReg(SrcReg).addImm(ShiftImm); 1623 BuildMI(BB, DL, TII->get(Mips::SRA), DstReg).addReg(ScrReg).addImm(ShiftImm); 1624 1625 return BB; 1626 } 1627 1628 MachineBasicBlock *MipsTargetLowering::emitAtomicBinaryPartword( 1629 MachineInstr &MI, MachineBasicBlock *BB, unsigned Size) const { 1630 assert((Size == 1 || Size == 2) && 1631 "Unsupported size for EmitAtomicBinaryPartial."); 1632 1633 MachineFunction *MF = BB->getParent(); 1634 MachineRegisterInfo &RegInfo = MF->getRegInfo(); 1635 const TargetRegisterClass *RC = getRegClassFor(MVT::i32); 1636 const bool ArePtrs64bit = ABI.ArePtrs64bit(); 1637 const TargetRegisterClass *RCp = 1638 getRegClassFor(ArePtrs64bit ? MVT::i64 : MVT::i32); 1639 const TargetInstrInfo *TII = Subtarget.getInstrInfo(); 1640 DebugLoc DL = MI.getDebugLoc(); 1641 1642 Register Dest = MI.getOperand(0).getReg(); 1643 Register Ptr = MI.getOperand(1).getReg(); 1644 Register Incr = MI.getOperand(2).getReg(); 1645 1646 Register AlignedAddr = RegInfo.createVirtualRegister(RCp); 1647 Register ShiftAmt = RegInfo.createVirtualRegister(RC); 1648 Register Mask = RegInfo.createVirtualRegister(RC); 1649 Register Mask2 = RegInfo.createVirtualRegister(RC); 1650 Register Incr2 = RegInfo.createVirtualRegister(RC); 1651 Register MaskLSB2 = RegInfo.createVirtualRegister(RCp); 1652 Register PtrLSB2 = RegInfo.createVirtualRegister(RC); 1653 Register MaskUpper = RegInfo.createVirtualRegister(RC); 1654 Register Scratch = RegInfo.createVirtualRegister(RC); 1655 Register Scratch2 = RegInfo.createVirtualRegister(RC); 1656 Register Scratch3 = RegInfo.createVirtualRegister(RC); 1657 1658 unsigned AtomicOp = 0; 1659 bool NeedsAdditionalReg = false; 1660 switch (MI.getOpcode()) { 1661 case Mips::ATOMIC_LOAD_NAND_I8: 1662 AtomicOp = Mips::ATOMIC_LOAD_NAND_I8_POSTRA; 1663 break; 1664 case Mips::ATOMIC_LOAD_NAND_I16: 1665 AtomicOp = Mips::ATOMIC_LOAD_NAND_I16_POSTRA; 1666 break; 1667 case Mips::ATOMIC_SWAP_I8: 1668 AtomicOp = Mips::ATOMIC_SWAP_I8_POSTRA; 1669 break; 1670 case Mips::ATOMIC_SWAP_I16: 1671 AtomicOp = Mips::ATOMIC_SWAP_I16_POSTRA; 1672 break; 1673 case Mips::ATOMIC_LOAD_ADD_I8: 1674 AtomicOp = Mips::ATOMIC_LOAD_ADD_I8_POSTRA; 1675 break; 1676 case Mips::ATOMIC_LOAD_ADD_I16: 1677 AtomicOp = Mips::ATOMIC_LOAD_ADD_I16_POSTRA; 1678 break; 1679 case Mips::ATOMIC_LOAD_SUB_I8: 1680 AtomicOp = Mips::ATOMIC_LOAD_SUB_I8_POSTRA; 1681 break; 1682 case Mips::ATOMIC_LOAD_SUB_I16: 1683 AtomicOp = Mips::ATOMIC_LOAD_SUB_I16_POSTRA; 1684 break; 1685 case Mips::ATOMIC_LOAD_AND_I8: 1686 AtomicOp = Mips::ATOMIC_LOAD_AND_I8_POSTRA; 1687 break; 1688 case Mips::ATOMIC_LOAD_AND_I16: 1689 AtomicOp = Mips::ATOMIC_LOAD_AND_I16_POSTRA; 1690 break; 1691 case Mips::ATOMIC_LOAD_OR_I8: 1692 AtomicOp = Mips::ATOMIC_LOAD_OR_I8_POSTRA; 1693 break; 1694 case Mips::ATOMIC_LOAD_OR_I16: 1695 AtomicOp = Mips::ATOMIC_LOAD_OR_I16_POSTRA; 1696 break; 1697 case Mips::ATOMIC_LOAD_XOR_I8: 1698 AtomicOp = Mips::ATOMIC_LOAD_XOR_I8_POSTRA; 1699 break; 1700 case Mips::ATOMIC_LOAD_XOR_I16: 1701 AtomicOp = Mips::ATOMIC_LOAD_XOR_I16_POSTRA; 1702 break; 1703 case Mips::ATOMIC_LOAD_MIN_I8: 1704 AtomicOp = Mips::ATOMIC_LOAD_MIN_I8_POSTRA; 1705 NeedsAdditionalReg = true; 1706 break; 1707 case Mips::ATOMIC_LOAD_MIN_I16: 1708 AtomicOp = Mips::ATOMIC_LOAD_MIN_I16_POSTRA; 1709 NeedsAdditionalReg = true; 1710 break; 1711 case Mips::ATOMIC_LOAD_MAX_I8: 1712 AtomicOp = Mips::ATOMIC_LOAD_MAX_I8_POSTRA; 1713 NeedsAdditionalReg = true; 1714 break; 1715 case Mips::ATOMIC_LOAD_MAX_I16: 1716 AtomicOp = Mips::ATOMIC_LOAD_MAX_I16_POSTRA; 1717 NeedsAdditionalReg = true; 1718 break; 1719 case Mips::ATOMIC_LOAD_UMIN_I8: 1720 AtomicOp = Mips::ATOMIC_LOAD_UMIN_I8_POSTRA; 1721 NeedsAdditionalReg = true; 1722 break; 1723 case Mips::ATOMIC_LOAD_UMIN_I16: 1724 AtomicOp = Mips::ATOMIC_LOAD_UMIN_I16_POSTRA; 1725 NeedsAdditionalReg = true; 1726 break; 1727 case Mips::ATOMIC_LOAD_UMAX_I8: 1728 AtomicOp = Mips::ATOMIC_LOAD_UMAX_I8_POSTRA; 1729 NeedsAdditionalReg = true; 1730 break; 1731 case Mips::ATOMIC_LOAD_UMAX_I16: 1732 AtomicOp = Mips::ATOMIC_LOAD_UMAX_I16_POSTRA; 1733 NeedsAdditionalReg = true; 1734 break; 1735 default: 1736 llvm_unreachable("Unknown subword atomic pseudo for expansion!"); 1737 } 1738 1739 // insert new blocks after the current block 1740 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 1741 MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB); 1742 MachineFunction::iterator It = ++BB->getIterator(); 1743 MF->insert(It, exitMBB); 1744 1745 // Transfer the remainder of BB and its successor edges to exitMBB. 1746 exitMBB->splice(exitMBB->begin(), BB, 1747 std::next(MachineBasicBlock::iterator(MI)), BB->end()); 1748 exitMBB->transferSuccessorsAndUpdatePHIs(BB); 1749 1750 BB->addSuccessor(exitMBB, BranchProbability::getOne()); 1751 1752 // thisMBB: 1753 // addiu masklsb2,$0,-4 # 0xfffffffc 1754 // and alignedaddr,ptr,masklsb2 1755 // andi ptrlsb2,ptr,3 1756 // sll shiftamt,ptrlsb2,3 1757 // ori maskupper,$0,255 # 0xff 1758 // sll mask,maskupper,shiftamt 1759 // nor mask2,$0,mask 1760 // sll incr2,incr,shiftamt 1761 1762 int64_t MaskImm = (Size == 1) ? 255 : 65535; 1763 BuildMI(BB, DL, TII->get(ABI.GetPtrAddiuOp()), MaskLSB2) 1764 .addReg(ABI.GetNullPtr()).addImm(-4); 1765 BuildMI(BB, DL, TII->get(ABI.GetPtrAndOp()), AlignedAddr) 1766 .addReg(Ptr).addReg(MaskLSB2); 1767 BuildMI(BB, DL, TII->get(Mips::ANDi), PtrLSB2) 1768 .addReg(Ptr, 0, ArePtrs64bit ? Mips::sub_32 : 0).addImm(3); 1769 if (Subtarget.isLittle()) { 1770 BuildMI(BB, DL, TII->get(Mips::SLL), ShiftAmt).addReg(PtrLSB2).addImm(3); 1771 } else { 1772 Register Off = RegInfo.createVirtualRegister(RC); 1773 BuildMI(BB, DL, TII->get(Mips::XORi), Off) 1774 .addReg(PtrLSB2).addImm((Size == 1) ? 3 : 2); 1775 BuildMI(BB, DL, TII->get(Mips::SLL), ShiftAmt).addReg(Off).addImm(3); 1776 } 1777 BuildMI(BB, DL, TII->get(Mips::ORi), MaskUpper) 1778 .addReg(Mips::ZERO).addImm(MaskImm); 1779 BuildMI(BB, DL, TII->get(Mips::SLLV), Mask) 1780 .addReg(MaskUpper).addReg(ShiftAmt); 1781 BuildMI(BB, DL, TII->get(Mips::NOR), Mask2).addReg(Mips::ZERO).addReg(Mask); 1782 BuildMI(BB, DL, TII->get(Mips::SLLV), Incr2).addReg(Incr).addReg(ShiftAmt); 1783 1784 1785 // The purposes of the flags on the scratch registers is explained in 1786 // emitAtomicBinary. In summary, we need a scratch register which is going to 1787 // be undef, that is unique among registers chosen for the instruction. 1788 1789 MachineInstrBuilder MIB = 1790 BuildMI(BB, DL, TII->get(AtomicOp)) 1791 .addReg(Dest, RegState::Define | RegState::EarlyClobber) 1792 .addReg(AlignedAddr) 1793 .addReg(Incr2) 1794 .addReg(Mask) 1795 .addReg(Mask2) 1796 .addReg(ShiftAmt) 1797 .addReg(Scratch, RegState::EarlyClobber | RegState::Define | 1798 RegState::Dead | RegState::Implicit) 1799 .addReg(Scratch2, RegState::EarlyClobber | RegState::Define | 1800 RegState::Dead | RegState::Implicit) 1801 .addReg(Scratch3, RegState::EarlyClobber | RegState::Define | 1802 RegState::Dead | RegState::Implicit); 1803 if (NeedsAdditionalReg) { 1804 Register Scratch4 = RegInfo.createVirtualRegister(RC); 1805 MIB.addReg(Scratch4, RegState::EarlyClobber | RegState::Define | 1806 RegState::Dead | RegState::Implicit); 1807 } 1808 1809 MI.eraseFromParent(); // The instruction is gone now. 1810 1811 return exitMBB; 1812 } 1813 1814 // Lower atomic compare and swap to a pseudo instruction, taking care to 1815 // define a scratch register for the pseudo instruction's expansion. The 1816 // instruction is expanded after the register allocator as to prevent 1817 // the insertion of stores between the linked load and the store conditional. 1818 1819 MachineBasicBlock * 1820 MipsTargetLowering::emitAtomicCmpSwap(MachineInstr &MI, 1821 MachineBasicBlock *BB) const { 1822 1823 assert((MI.getOpcode() == Mips::ATOMIC_CMP_SWAP_I32 || 1824 MI.getOpcode() == Mips::ATOMIC_CMP_SWAP_I64) && 1825 "Unsupported atomic pseudo for EmitAtomicCmpSwap."); 1826 1827 const unsigned Size = MI.getOpcode() == Mips::ATOMIC_CMP_SWAP_I32 ? 4 : 8; 1828 1829 MachineFunction *MF = BB->getParent(); 1830 MachineRegisterInfo &MRI = MF->getRegInfo(); 1831 const TargetRegisterClass *RC = getRegClassFor(MVT::getIntegerVT(Size * 8)); 1832 const TargetInstrInfo *TII = Subtarget.getInstrInfo(); 1833 DebugLoc DL = MI.getDebugLoc(); 1834 1835 unsigned AtomicOp = MI.getOpcode() == Mips::ATOMIC_CMP_SWAP_I32 1836 ? Mips::ATOMIC_CMP_SWAP_I32_POSTRA 1837 : Mips::ATOMIC_CMP_SWAP_I64_POSTRA; 1838 Register Dest = MI.getOperand(0).getReg(); 1839 Register Ptr = MI.getOperand(1).getReg(); 1840 Register OldVal = MI.getOperand(2).getReg(); 1841 Register NewVal = MI.getOperand(3).getReg(); 1842 1843 Register Scratch = MRI.createVirtualRegister(RC); 1844 MachineBasicBlock::iterator II(MI); 1845 1846 // We need to create copies of the various registers and kill them at the 1847 // atomic pseudo. If the copies are not made, when the atomic is expanded 1848 // after fast register allocation, the spills will end up outside of the 1849 // blocks that their values are defined in, causing livein errors. 1850 1851 Register PtrCopy = MRI.createVirtualRegister(MRI.getRegClass(Ptr)); 1852 Register OldValCopy = MRI.createVirtualRegister(MRI.getRegClass(OldVal)); 1853 Register NewValCopy = MRI.createVirtualRegister(MRI.getRegClass(NewVal)); 1854 1855 BuildMI(*BB, II, DL, TII->get(Mips::COPY), PtrCopy).addReg(Ptr); 1856 BuildMI(*BB, II, DL, TII->get(Mips::COPY), OldValCopy).addReg(OldVal); 1857 BuildMI(*BB, II, DL, TII->get(Mips::COPY), NewValCopy).addReg(NewVal); 1858 1859 // The purposes of the flags on the scratch registers is explained in 1860 // emitAtomicBinary. In summary, we need a scratch register which is going to 1861 // be undef, that is unique among registers chosen for the instruction. 1862 1863 BuildMI(*BB, II, DL, TII->get(AtomicOp)) 1864 .addReg(Dest, RegState::Define | RegState::EarlyClobber) 1865 .addReg(PtrCopy, RegState::Kill) 1866 .addReg(OldValCopy, RegState::Kill) 1867 .addReg(NewValCopy, RegState::Kill) 1868 .addReg(Scratch, RegState::EarlyClobber | RegState::Define | 1869 RegState::Dead | RegState::Implicit); 1870 1871 MI.eraseFromParent(); // The instruction is gone now. 1872 1873 return BB; 1874 } 1875 1876 MachineBasicBlock *MipsTargetLowering::emitAtomicCmpSwapPartword( 1877 MachineInstr &MI, MachineBasicBlock *BB, unsigned Size) const { 1878 assert((Size == 1 || Size == 2) && 1879 "Unsupported size for EmitAtomicCmpSwapPartial."); 1880 1881 MachineFunction *MF = BB->getParent(); 1882 MachineRegisterInfo &RegInfo = MF->getRegInfo(); 1883 const TargetRegisterClass *RC = getRegClassFor(MVT::i32); 1884 const bool ArePtrs64bit = ABI.ArePtrs64bit(); 1885 const TargetRegisterClass *RCp = 1886 getRegClassFor(ArePtrs64bit ? MVT::i64 : MVT::i32); 1887 const TargetInstrInfo *TII = Subtarget.getInstrInfo(); 1888 DebugLoc DL = MI.getDebugLoc(); 1889 1890 Register Dest = MI.getOperand(0).getReg(); 1891 Register Ptr = MI.getOperand(1).getReg(); 1892 Register CmpVal = MI.getOperand(2).getReg(); 1893 Register NewVal = MI.getOperand(3).getReg(); 1894 1895 Register AlignedAddr = RegInfo.createVirtualRegister(RCp); 1896 Register ShiftAmt = RegInfo.createVirtualRegister(RC); 1897 Register Mask = RegInfo.createVirtualRegister(RC); 1898 Register Mask2 = RegInfo.createVirtualRegister(RC); 1899 Register ShiftedCmpVal = RegInfo.createVirtualRegister(RC); 1900 Register ShiftedNewVal = RegInfo.createVirtualRegister(RC); 1901 Register MaskLSB2 = RegInfo.createVirtualRegister(RCp); 1902 Register PtrLSB2 = RegInfo.createVirtualRegister(RC); 1903 Register MaskUpper = RegInfo.createVirtualRegister(RC); 1904 Register MaskedCmpVal = RegInfo.createVirtualRegister(RC); 1905 Register MaskedNewVal = RegInfo.createVirtualRegister(RC); 1906 unsigned AtomicOp = MI.getOpcode() == Mips::ATOMIC_CMP_SWAP_I8 1907 ? Mips::ATOMIC_CMP_SWAP_I8_POSTRA 1908 : Mips::ATOMIC_CMP_SWAP_I16_POSTRA; 1909 1910 // The scratch registers here with the EarlyClobber | Define | Dead | Implicit 1911 // flags are used to coerce the register allocator and the machine verifier to 1912 // accept the usage of these registers. 1913 // The EarlyClobber flag has the semantic properties that the operand it is 1914 // attached to is clobbered before the rest of the inputs are read. Hence it 1915 // must be unique among the operands to the instruction. 1916 // The Define flag is needed to coerce the machine verifier that an Undef 1917 // value isn't a problem. 1918 // The Dead flag is needed as the value in scratch isn't used by any other 1919 // instruction. Kill isn't used as Dead is more precise. 1920 Register Scratch = RegInfo.createVirtualRegister(RC); 1921 Register Scratch2 = RegInfo.createVirtualRegister(RC); 1922 1923 // insert new blocks after the current block 1924 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 1925 MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB); 1926 MachineFunction::iterator It = ++BB->getIterator(); 1927 MF->insert(It, exitMBB); 1928 1929 // Transfer the remainder of BB and its successor edges to exitMBB. 1930 exitMBB->splice(exitMBB->begin(), BB, 1931 std::next(MachineBasicBlock::iterator(MI)), BB->end()); 1932 exitMBB->transferSuccessorsAndUpdatePHIs(BB); 1933 1934 BB->addSuccessor(exitMBB, BranchProbability::getOne()); 1935 1936 // thisMBB: 1937 // addiu masklsb2,$0,-4 # 0xfffffffc 1938 // and alignedaddr,ptr,masklsb2 1939 // andi ptrlsb2,ptr,3 1940 // xori ptrlsb2,ptrlsb2,3 # Only for BE 1941 // sll shiftamt,ptrlsb2,3 1942 // ori maskupper,$0,255 # 0xff 1943 // sll mask,maskupper,shiftamt 1944 // nor mask2,$0,mask 1945 // andi maskedcmpval,cmpval,255 1946 // sll shiftedcmpval,maskedcmpval,shiftamt 1947 // andi maskednewval,newval,255 1948 // sll shiftednewval,maskednewval,shiftamt 1949 int64_t MaskImm = (Size == 1) ? 255 : 65535; 1950 BuildMI(BB, DL, TII->get(ArePtrs64bit ? Mips::DADDiu : Mips::ADDiu), MaskLSB2) 1951 .addReg(ABI.GetNullPtr()).addImm(-4); 1952 BuildMI(BB, DL, TII->get(ArePtrs64bit ? Mips::AND64 : Mips::AND), AlignedAddr) 1953 .addReg(Ptr).addReg(MaskLSB2); 1954 BuildMI(BB, DL, TII->get(Mips::ANDi), PtrLSB2) 1955 .addReg(Ptr, 0, ArePtrs64bit ? Mips::sub_32 : 0).addImm(3); 1956 if (Subtarget.isLittle()) { 1957 BuildMI(BB, DL, TII->get(Mips::SLL), ShiftAmt).addReg(PtrLSB2).addImm(3); 1958 } else { 1959 Register Off = RegInfo.createVirtualRegister(RC); 1960 BuildMI(BB, DL, TII->get(Mips::XORi), Off) 1961 .addReg(PtrLSB2).addImm((Size == 1) ? 3 : 2); 1962 BuildMI(BB, DL, TII->get(Mips::SLL), ShiftAmt).addReg(Off).addImm(3); 1963 } 1964 BuildMI(BB, DL, TII->get(Mips::ORi), MaskUpper) 1965 .addReg(Mips::ZERO).addImm(MaskImm); 1966 BuildMI(BB, DL, TII->get(Mips::SLLV), Mask) 1967 .addReg(MaskUpper).addReg(ShiftAmt); 1968 BuildMI(BB, DL, TII->get(Mips::NOR), Mask2).addReg(Mips::ZERO).addReg(Mask); 1969 BuildMI(BB, DL, TII->get(Mips::ANDi), MaskedCmpVal) 1970 .addReg(CmpVal).addImm(MaskImm); 1971 BuildMI(BB, DL, TII->get(Mips::SLLV), ShiftedCmpVal) 1972 .addReg(MaskedCmpVal).addReg(ShiftAmt); 1973 BuildMI(BB, DL, TII->get(Mips::ANDi), MaskedNewVal) 1974 .addReg(NewVal).addImm(MaskImm); 1975 BuildMI(BB, DL, TII->get(Mips::SLLV), ShiftedNewVal) 1976 .addReg(MaskedNewVal).addReg(ShiftAmt); 1977 1978 // The purposes of the flags on the scratch registers are explained in 1979 // emitAtomicBinary. In summary, we need a scratch register which is going to 1980 // be undef, that is unique among the register chosen for the instruction. 1981 1982 BuildMI(BB, DL, TII->get(AtomicOp)) 1983 .addReg(Dest, RegState::Define | RegState::EarlyClobber) 1984 .addReg(AlignedAddr) 1985 .addReg(Mask) 1986 .addReg(ShiftedCmpVal) 1987 .addReg(Mask2) 1988 .addReg(ShiftedNewVal) 1989 .addReg(ShiftAmt) 1990 .addReg(Scratch, RegState::EarlyClobber | RegState::Define | 1991 RegState::Dead | RegState::Implicit) 1992 .addReg(Scratch2, RegState::EarlyClobber | RegState::Define | 1993 RegState::Dead | RegState::Implicit); 1994 1995 MI.eraseFromParent(); // The instruction is gone now. 1996 1997 return exitMBB; 1998 } 1999 2000 SDValue MipsTargetLowering::lowerBRCOND(SDValue Op, SelectionDAG &DAG) const { 2001 // The first operand is the chain, the second is the condition, the third is 2002 // the block to branch to if the condition is true. 2003 SDValue Chain = Op.getOperand(0); 2004 SDValue Dest = Op.getOperand(2); 2005 SDLoc DL(Op); 2006 2007 assert(!Subtarget.hasMips32r6() && !Subtarget.hasMips64r6()); 2008 SDValue CondRes = createFPCmp(DAG, Op.getOperand(1)); 2009 2010 // Return if flag is not set by a floating point comparison. 2011 if (CondRes.getOpcode() != MipsISD::FPCmp) 2012 return Op; 2013 2014 SDValue CCNode = CondRes.getOperand(2); 2015 Mips::CondCode CC = 2016 (Mips::CondCode)cast<ConstantSDNode>(CCNode)->getZExtValue(); 2017 unsigned Opc = invertFPCondCodeUser(CC) ? Mips::BRANCH_F : Mips::BRANCH_T; 2018 SDValue BrCode = DAG.getConstant(Opc, DL, MVT::i32); 2019 SDValue FCC0 = DAG.getRegister(Mips::FCC0, MVT::i32); 2020 return DAG.getNode(MipsISD::FPBrcond, DL, Op.getValueType(), Chain, BrCode, 2021 FCC0, Dest, CondRes); 2022 } 2023 2024 SDValue MipsTargetLowering:: 2025 lowerSELECT(SDValue Op, SelectionDAG &DAG) const 2026 { 2027 assert(!Subtarget.hasMips32r6() && !Subtarget.hasMips64r6()); 2028 SDValue Cond = createFPCmp(DAG, Op.getOperand(0)); 2029 2030 // Return if flag is not set by a floating point comparison. 2031 if (Cond.getOpcode() != MipsISD::FPCmp) 2032 return Op; 2033 2034 return createCMovFP(DAG, Cond, Op.getOperand(1), Op.getOperand(2), 2035 SDLoc(Op)); 2036 } 2037 2038 SDValue MipsTargetLowering::lowerSETCC(SDValue Op, SelectionDAG &DAG) const { 2039 assert(!Subtarget.hasMips32r6() && !Subtarget.hasMips64r6()); 2040 SDValue Cond = createFPCmp(DAG, Op); 2041 2042 assert(Cond.getOpcode() == MipsISD::FPCmp && 2043 "Floating point operand expected."); 2044 2045 SDLoc DL(Op); 2046 SDValue True = DAG.getConstant(1, DL, MVT::i32); 2047 SDValue False = DAG.getConstant(0, DL, MVT::i32); 2048 2049 return createCMovFP(DAG, Cond, True, False, DL); 2050 } 2051 2052 SDValue MipsTargetLowering::lowerGlobalAddress(SDValue Op, 2053 SelectionDAG &DAG) const { 2054 EVT Ty = Op.getValueType(); 2055 GlobalAddressSDNode *N = cast<GlobalAddressSDNode>(Op); 2056 const GlobalValue *GV = N->getGlobal(); 2057 2058 if (!isPositionIndependent()) { 2059 const MipsTargetObjectFile *TLOF = 2060 static_cast<const MipsTargetObjectFile *>( 2061 getTargetMachine().getObjFileLowering()); 2062 const GlobalObject *GO = GV->getAliaseeObject(); 2063 if (GO && TLOF->IsGlobalInSmallSection(GO, getTargetMachine())) 2064 // %gp_rel relocation 2065 return getAddrGPRel(N, SDLoc(N), Ty, DAG, ABI.IsN64()); 2066 2067 // %hi/%lo relocation 2068 return Subtarget.hasSym32() ? getAddrNonPIC(N, SDLoc(N), Ty, DAG) 2069 // %highest/%higher/%hi/%lo relocation 2070 : getAddrNonPICSym64(N, SDLoc(N), Ty, DAG); 2071 } 2072 2073 // Every other architecture would use shouldAssumeDSOLocal in here, but 2074 // mips is special. 2075 // * In PIC code mips requires got loads even for local statics! 2076 // * To save on got entries, for local statics the got entry contains the 2077 // page and an additional add instruction takes care of the low bits. 2078 // * It is legal to access a hidden symbol with a non hidden undefined, 2079 // so one cannot guarantee that all access to a hidden symbol will know 2080 // it is hidden. 2081 // * Mips linkers don't support creating a page and a full got entry for 2082 // the same symbol. 2083 // * Given all that, we have to use a full got entry for hidden symbols :-( 2084 if (GV->hasLocalLinkage()) 2085 return getAddrLocal(N, SDLoc(N), Ty, DAG, ABI.IsN32() || ABI.IsN64()); 2086 2087 if (Subtarget.useXGOT()) 2088 return getAddrGlobalLargeGOT( 2089 N, SDLoc(N), Ty, DAG, MipsII::MO_GOT_HI16, MipsII::MO_GOT_LO16, 2090 DAG.getEntryNode(), 2091 MachinePointerInfo::getGOT(DAG.getMachineFunction())); 2092 2093 return getAddrGlobal( 2094 N, SDLoc(N), Ty, DAG, 2095 (ABI.IsN32() || ABI.IsN64()) ? MipsII::MO_GOT_DISP : MipsII::MO_GOT, 2096 DAG.getEntryNode(), MachinePointerInfo::getGOT(DAG.getMachineFunction())); 2097 } 2098 2099 SDValue MipsTargetLowering::lowerBlockAddress(SDValue Op, 2100 SelectionDAG &DAG) const { 2101 BlockAddressSDNode *N = cast<BlockAddressSDNode>(Op); 2102 EVT Ty = Op.getValueType(); 2103 2104 if (!isPositionIndependent()) 2105 return Subtarget.hasSym32() ? getAddrNonPIC(N, SDLoc(N), Ty, DAG) 2106 : getAddrNonPICSym64(N, SDLoc(N), Ty, DAG); 2107 2108 return getAddrLocal(N, SDLoc(N), Ty, DAG, ABI.IsN32() || ABI.IsN64()); 2109 } 2110 2111 SDValue MipsTargetLowering:: 2112 lowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const 2113 { 2114 // If the relocation model is PIC, use the General Dynamic TLS Model or 2115 // Local Dynamic TLS model, otherwise use the Initial Exec or 2116 // Local Exec TLS Model. 2117 2118 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op); 2119 if (DAG.getTarget().useEmulatedTLS()) 2120 return LowerToTLSEmulatedModel(GA, DAG); 2121 2122 SDLoc DL(GA); 2123 const GlobalValue *GV = GA->getGlobal(); 2124 EVT PtrVT = getPointerTy(DAG.getDataLayout()); 2125 2126 TLSModel::Model model = getTargetMachine().getTLSModel(GV); 2127 2128 if (model == TLSModel::GeneralDynamic || model == TLSModel::LocalDynamic) { 2129 // General Dynamic and Local Dynamic TLS Model. 2130 unsigned Flag = (model == TLSModel::LocalDynamic) ? MipsII::MO_TLSLDM 2131 : MipsII::MO_TLSGD; 2132 2133 SDValue TGA = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, Flag); 2134 SDValue Argument = DAG.getNode(MipsISD::Wrapper, DL, PtrVT, 2135 getGlobalReg(DAG, PtrVT), TGA); 2136 unsigned PtrSize = PtrVT.getSizeInBits(); 2137 IntegerType *PtrTy = Type::getIntNTy(*DAG.getContext(), PtrSize); 2138 2139 SDValue TlsGetAddr = DAG.getExternalSymbol("__tls_get_addr", PtrVT); 2140 2141 ArgListTy Args; 2142 ArgListEntry Entry; 2143 Entry.Node = Argument; 2144 Entry.Ty = PtrTy; 2145 Args.push_back(Entry); 2146 2147 TargetLowering::CallLoweringInfo CLI(DAG); 2148 CLI.setDebugLoc(DL) 2149 .setChain(DAG.getEntryNode()) 2150 .setLibCallee(CallingConv::C, PtrTy, TlsGetAddr, std::move(Args)); 2151 std::pair<SDValue, SDValue> CallResult = LowerCallTo(CLI); 2152 2153 SDValue Ret = CallResult.first; 2154 2155 if (model != TLSModel::LocalDynamic) 2156 return Ret; 2157 2158 SDValue TGAHi = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, 2159 MipsII::MO_DTPREL_HI); 2160 SDValue Hi = DAG.getNode(MipsISD::TlsHi, DL, PtrVT, TGAHi); 2161 SDValue TGALo = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, 2162 MipsII::MO_DTPREL_LO); 2163 SDValue Lo = DAG.getNode(MipsISD::Lo, DL, PtrVT, TGALo); 2164 SDValue Add = DAG.getNode(ISD::ADD, DL, PtrVT, Hi, Ret); 2165 return DAG.getNode(ISD::ADD, DL, PtrVT, Add, Lo); 2166 } 2167 2168 SDValue Offset; 2169 if (model == TLSModel::InitialExec) { 2170 // Initial Exec TLS Model 2171 SDValue TGA = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, 2172 MipsII::MO_GOTTPREL); 2173 TGA = DAG.getNode(MipsISD::Wrapper, DL, PtrVT, getGlobalReg(DAG, PtrVT), 2174 TGA); 2175 Offset = 2176 DAG.getLoad(PtrVT, DL, DAG.getEntryNode(), TGA, MachinePointerInfo()); 2177 } else { 2178 // Local Exec TLS Model 2179 assert(model == TLSModel::LocalExec); 2180 SDValue TGAHi = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, 2181 MipsII::MO_TPREL_HI); 2182 SDValue TGALo = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, 2183 MipsII::MO_TPREL_LO); 2184 SDValue Hi = DAG.getNode(MipsISD::TlsHi, DL, PtrVT, TGAHi); 2185 SDValue Lo = DAG.getNode(MipsISD::Lo, DL, PtrVT, TGALo); 2186 Offset = DAG.getNode(ISD::ADD, DL, PtrVT, Hi, Lo); 2187 } 2188 2189 SDValue ThreadPointer = DAG.getNode(MipsISD::ThreadPointer, DL, PtrVT); 2190 return DAG.getNode(ISD::ADD, DL, PtrVT, ThreadPointer, Offset); 2191 } 2192 2193 SDValue MipsTargetLowering:: 2194 lowerJumpTable(SDValue Op, SelectionDAG &DAG) const 2195 { 2196 JumpTableSDNode *N = cast<JumpTableSDNode>(Op); 2197 EVT Ty = Op.getValueType(); 2198 2199 if (!isPositionIndependent()) 2200 return Subtarget.hasSym32() ? getAddrNonPIC(N, SDLoc(N), Ty, DAG) 2201 : getAddrNonPICSym64(N, SDLoc(N), Ty, DAG); 2202 2203 return getAddrLocal(N, SDLoc(N), Ty, DAG, ABI.IsN32() || ABI.IsN64()); 2204 } 2205 2206 SDValue MipsTargetLowering:: 2207 lowerConstantPool(SDValue Op, SelectionDAG &DAG) const 2208 { 2209 ConstantPoolSDNode *N = cast<ConstantPoolSDNode>(Op); 2210 EVT Ty = Op.getValueType(); 2211 2212 if (!isPositionIndependent()) { 2213 const MipsTargetObjectFile *TLOF = 2214 static_cast<const MipsTargetObjectFile *>( 2215 getTargetMachine().getObjFileLowering()); 2216 2217 if (TLOF->IsConstantInSmallSection(DAG.getDataLayout(), N->getConstVal(), 2218 getTargetMachine())) 2219 // %gp_rel relocation 2220 return getAddrGPRel(N, SDLoc(N), Ty, DAG, ABI.IsN64()); 2221 2222 return Subtarget.hasSym32() ? getAddrNonPIC(N, SDLoc(N), Ty, DAG) 2223 : getAddrNonPICSym64(N, SDLoc(N), Ty, DAG); 2224 } 2225 2226 return getAddrLocal(N, SDLoc(N), Ty, DAG, ABI.IsN32() || ABI.IsN64()); 2227 } 2228 2229 SDValue MipsTargetLowering::lowerVASTART(SDValue Op, SelectionDAG &DAG) const { 2230 MachineFunction &MF = DAG.getMachineFunction(); 2231 MipsFunctionInfo *FuncInfo = MF.getInfo<MipsFunctionInfo>(); 2232 2233 SDLoc DL(Op); 2234 SDValue FI = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), 2235 getPointerTy(MF.getDataLayout())); 2236 2237 // vastart just stores the address of the VarArgsFrameIndex slot into the 2238 // memory location argument. 2239 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue(); 2240 return DAG.getStore(Op.getOperand(0), DL, FI, Op.getOperand(1), 2241 MachinePointerInfo(SV)); 2242 } 2243 2244 SDValue MipsTargetLowering::lowerVAARG(SDValue Op, SelectionDAG &DAG) const { 2245 SDNode *Node = Op.getNode(); 2246 EVT VT = Node->getValueType(0); 2247 SDValue Chain = Node->getOperand(0); 2248 SDValue VAListPtr = Node->getOperand(1); 2249 const Align Align = 2250 llvm::MaybeAlign(Node->getConstantOperandVal(3)).valueOrOne(); 2251 const Value *SV = cast<SrcValueSDNode>(Node->getOperand(2))->getValue(); 2252 SDLoc DL(Node); 2253 unsigned ArgSlotSizeInBytes = (ABI.IsN32() || ABI.IsN64()) ? 8 : 4; 2254 2255 SDValue VAListLoad = DAG.getLoad(getPointerTy(DAG.getDataLayout()), DL, Chain, 2256 VAListPtr, MachinePointerInfo(SV)); 2257 SDValue VAList = VAListLoad; 2258 2259 // Re-align the pointer if necessary. 2260 // It should only ever be necessary for 64-bit types on O32 since the minimum 2261 // argument alignment is the same as the maximum type alignment for N32/N64. 2262 // 2263 // FIXME: We currently align too often. The code generator doesn't notice 2264 // when the pointer is still aligned from the last va_arg (or pair of 2265 // va_args for the i64 on O32 case). 2266 if (Align > getMinStackArgumentAlignment()) { 2267 VAList = DAG.getNode( 2268 ISD::ADD, DL, VAList.getValueType(), VAList, 2269 DAG.getConstant(Align.value() - 1, DL, VAList.getValueType())); 2270 2271 VAList = DAG.getNode( 2272 ISD::AND, DL, VAList.getValueType(), VAList, 2273 DAG.getConstant(-(int64_t)Align.value(), DL, VAList.getValueType())); 2274 } 2275 2276 // Increment the pointer, VAList, to the next vaarg. 2277 auto &TD = DAG.getDataLayout(); 2278 unsigned ArgSizeInBytes = 2279 TD.getTypeAllocSize(VT.getTypeForEVT(*DAG.getContext())); 2280 SDValue Tmp3 = 2281 DAG.getNode(ISD::ADD, DL, VAList.getValueType(), VAList, 2282 DAG.getConstant(alignTo(ArgSizeInBytes, ArgSlotSizeInBytes), 2283 DL, VAList.getValueType())); 2284 // Store the incremented VAList to the legalized pointer 2285 Chain = DAG.getStore(VAListLoad.getValue(1), DL, Tmp3, VAListPtr, 2286 MachinePointerInfo(SV)); 2287 2288 // In big-endian mode we must adjust the pointer when the load size is smaller 2289 // than the argument slot size. We must also reduce the known alignment to 2290 // match. For example in the N64 ABI, we must add 4 bytes to the offset to get 2291 // the correct half of the slot, and reduce the alignment from 8 (slot 2292 // alignment) down to 4 (type alignment). 2293 if (!Subtarget.isLittle() && ArgSizeInBytes < ArgSlotSizeInBytes) { 2294 unsigned Adjustment = ArgSlotSizeInBytes - ArgSizeInBytes; 2295 VAList = DAG.getNode(ISD::ADD, DL, VAListPtr.getValueType(), VAList, 2296 DAG.getIntPtrConstant(Adjustment, DL)); 2297 } 2298 // Load the actual argument out of the pointer VAList 2299 return DAG.getLoad(VT, DL, Chain, VAList, MachinePointerInfo()); 2300 } 2301 2302 static SDValue lowerFCOPYSIGN32(SDValue Op, SelectionDAG &DAG, 2303 bool HasExtractInsert) { 2304 EVT TyX = Op.getOperand(0).getValueType(); 2305 EVT TyY = Op.getOperand(1).getValueType(); 2306 SDLoc DL(Op); 2307 SDValue Const1 = DAG.getConstant(1, DL, MVT::i32); 2308 SDValue Const31 = DAG.getConstant(31, DL, MVT::i32); 2309 SDValue Res; 2310 2311 // If operand is of type f64, extract the upper 32-bit. Otherwise, bitcast it 2312 // to i32. 2313 SDValue X = (TyX == MVT::f32) ? 2314 DAG.getNode(ISD::BITCAST, DL, MVT::i32, Op.getOperand(0)) : 2315 DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32, Op.getOperand(0), 2316 Const1); 2317 SDValue Y = (TyY == MVT::f32) ? 2318 DAG.getNode(ISD::BITCAST, DL, MVT::i32, Op.getOperand(1)) : 2319 DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32, Op.getOperand(1), 2320 Const1); 2321 2322 if (HasExtractInsert) { 2323 // ext E, Y, 31, 1 ; extract bit31 of Y 2324 // ins X, E, 31, 1 ; insert extracted bit at bit31 of X 2325 SDValue E = DAG.getNode(MipsISD::Ext, DL, MVT::i32, Y, Const31, Const1); 2326 Res = DAG.getNode(MipsISD::Ins, DL, MVT::i32, E, Const31, Const1, X); 2327 } else { 2328 // sll SllX, X, 1 2329 // srl SrlX, SllX, 1 2330 // srl SrlY, Y, 31 2331 // sll SllY, SrlX, 31 2332 // or Or, SrlX, SllY 2333 SDValue SllX = DAG.getNode(ISD::SHL, DL, MVT::i32, X, Const1); 2334 SDValue SrlX = DAG.getNode(ISD::SRL, DL, MVT::i32, SllX, Const1); 2335 SDValue SrlY = DAG.getNode(ISD::SRL, DL, MVT::i32, Y, Const31); 2336 SDValue SllY = DAG.getNode(ISD::SHL, DL, MVT::i32, SrlY, Const31); 2337 Res = DAG.getNode(ISD::OR, DL, MVT::i32, SrlX, SllY); 2338 } 2339 2340 if (TyX == MVT::f32) 2341 return DAG.getNode(ISD::BITCAST, DL, Op.getOperand(0).getValueType(), Res); 2342 2343 SDValue LowX = DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32, 2344 Op.getOperand(0), 2345 DAG.getConstant(0, DL, MVT::i32)); 2346 return DAG.getNode(MipsISD::BuildPairF64, DL, MVT::f64, LowX, Res); 2347 } 2348 2349 static SDValue lowerFCOPYSIGN64(SDValue Op, SelectionDAG &DAG, 2350 bool HasExtractInsert) { 2351 unsigned WidthX = Op.getOperand(0).getValueSizeInBits(); 2352 unsigned WidthY = Op.getOperand(1).getValueSizeInBits(); 2353 EVT TyX = MVT::getIntegerVT(WidthX), TyY = MVT::getIntegerVT(WidthY); 2354 SDLoc DL(Op); 2355 SDValue Const1 = DAG.getConstant(1, DL, MVT::i32); 2356 2357 // Bitcast to integer nodes. 2358 SDValue X = DAG.getNode(ISD::BITCAST, DL, TyX, Op.getOperand(0)); 2359 SDValue Y = DAG.getNode(ISD::BITCAST, DL, TyY, Op.getOperand(1)); 2360 2361 if (HasExtractInsert) { 2362 // ext E, Y, width(Y) - 1, 1 ; extract bit width(Y)-1 of Y 2363 // ins X, E, width(X) - 1, 1 ; insert extracted bit at bit width(X)-1 of X 2364 SDValue E = DAG.getNode(MipsISD::Ext, DL, TyY, Y, 2365 DAG.getConstant(WidthY - 1, DL, MVT::i32), Const1); 2366 2367 if (WidthX > WidthY) 2368 E = DAG.getNode(ISD::ZERO_EXTEND, DL, TyX, E); 2369 else if (WidthY > WidthX) 2370 E = DAG.getNode(ISD::TRUNCATE, DL, TyX, E); 2371 2372 SDValue I = DAG.getNode(MipsISD::Ins, DL, TyX, E, 2373 DAG.getConstant(WidthX - 1, DL, MVT::i32), Const1, 2374 X); 2375 return DAG.getNode(ISD::BITCAST, DL, Op.getOperand(0).getValueType(), I); 2376 } 2377 2378 // (d)sll SllX, X, 1 2379 // (d)srl SrlX, SllX, 1 2380 // (d)srl SrlY, Y, width(Y)-1 2381 // (d)sll SllY, SrlX, width(Y)-1 2382 // or Or, SrlX, SllY 2383 SDValue SllX = DAG.getNode(ISD::SHL, DL, TyX, X, Const1); 2384 SDValue SrlX = DAG.getNode(ISD::SRL, DL, TyX, SllX, Const1); 2385 SDValue SrlY = DAG.getNode(ISD::SRL, DL, TyY, Y, 2386 DAG.getConstant(WidthY - 1, DL, MVT::i32)); 2387 2388 if (WidthX > WidthY) 2389 SrlY = DAG.getNode(ISD::ZERO_EXTEND, DL, TyX, SrlY); 2390 else if (WidthY > WidthX) 2391 SrlY = DAG.getNode(ISD::TRUNCATE, DL, TyX, SrlY); 2392 2393 SDValue SllY = DAG.getNode(ISD::SHL, DL, TyX, SrlY, 2394 DAG.getConstant(WidthX - 1, DL, MVT::i32)); 2395 SDValue Or = DAG.getNode(ISD::OR, DL, TyX, SrlX, SllY); 2396 return DAG.getNode(ISD::BITCAST, DL, Op.getOperand(0).getValueType(), Or); 2397 } 2398 2399 SDValue 2400 MipsTargetLowering::lowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const { 2401 if (Subtarget.isGP64bit()) 2402 return lowerFCOPYSIGN64(Op, DAG, Subtarget.hasExtractInsert()); 2403 2404 return lowerFCOPYSIGN32(Op, DAG, Subtarget.hasExtractInsert()); 2405 } 2406 2407 static SDValue lowerFABS32(SDValue Op, SelectionDAG &DAG, 2408 bool HasExtractInsert) { 2409 SDLoc DL(Op); 2410 SDValue Res, Const1 = DAG.getConstant(1, DL, MVT::i32); 2411 2412 // If operand is of type f64, extract the upper 32-bit. Otherwise, bitcast it 2413 // to i32. 2414 SDValue X = (Op.getValueType() == MVT::f32) 2415 ? DAG.getNode(ISD::BITCAST, DL, MVT::i32, Op.getOperand(0)) 2416 : DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32, 2417 Op.getOperand(0), Const1); 2418 2419 // Clear MSB. 2420 if (HasExtractInsert) 2421 Res = DAG.getNode(MipsISD::Ins, DL, MVT::i32, 2422 DAG.getRegister(Mips::ZERO, MVT::i32), 2423 DAG.getConstant(31, DL, MVT::i32), Const1, X); 2424 else { 2425 // TODO: Provide DAG patterns which transform (and x, cst) 2426 // back to a (shl (srl x (clz cst)) (clz cst)) sequence. 2427 SDValue SllX = DAG.getNode(ISD::SHL, DL, MVT::i32, X, Const1); 2428 Res = DAG.getNode(ISD::SRL, DL, MVT::i32, SllX, Const1); 2429 } 2430 2431 if (Op.getValueType() == MVT::f32) 2432 return DAG.getNode(ISD::BITCAST, DL, MVT::f32, Res); 2433 2434 // FIXME: For mips32r2, the sequence of (BuildPairF64 (ins (ExtractElementF64 2435 // Op 1), $zero, 31 1) (ExtractElementF64 Op 0)) and the Op has one use, we 2436 // should be able to drop the usage of mfc1/mtc1 and rewrite the register in 2437 // place. 2438 SDValue LowX = 2439 DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32, Op.getOperand(0), 2440 DAG.getConstant(0, DL, MVT::i32)); 2441 return DAG.getNode(MipsISD::BuildPairF64, DL, MVT::f64, LowX, Res); 2442 } 2443 2444 static SDValue lowerFABS64(SDValue Op, SelectionDAG &DAG, 2445 bool HasExtractInsert) { 2446 SDLoc DL(Op); 2447 SDValue Res, Const1 = DAG.getConstant(1, DL, MVT::i32); 2448 2449 // Bitcast to integer node. 2450 SDValue X = DAG.getNode(ISD::BITCAST, DL, MVT::i64, Op.getOperand(0)); 2451 2452 // Clear MSB. 2453 if (HasExtractInsert) 2454 Res = DAG.getNode(MipsISD::Ins, DL, MVT::i64, 2455 DAG.getRegister(Mips::ZERO_64, MVT::i64), 2456 DAG.getConstant(63, DL, MVT::i32), Const1, X); 2457 else { 2458 SDValue SllX = DAG.getNode(ISD::SHL, DL, MVT::i64, X, Const1); 2459 Res = DAG.getNode(ISD::SRL, DL, MVT::i64, SllX, Const1); 2460 } 2461 2462 return DAG.getNode(ISD::BITCAST, DL, MVT::f64, Res); 2463 } 2464 2465 SDValue MipsTargetLowering::lowerFABS(SDValue Op, SelectionDAG &DAG) const { 2466 if ((ABI.IsN32() || ABI.IsN64()) && (Op.getValueType() == MVT::f64)) 2467 return lowerFABS64(Op, DAG, Subtarget.hasExtractInsert()); 2468 2469 return lowerFABS32(Op, DAG, Subtarget.hasExtractInsert()); 2470 } 2471 2472 SDValue MipsTargetLowering:: 2473 lowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const { 2474 // check the depth 2475 if (cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue() != 0) { 2476 DAG.getContext()->emitError( 2477 "return address can be determined only for current frame"); 2478 return SDValue(); 2479 } 2480 2481 MachineFrameInfo &MFI = DAG.getMachineFunction().getFrameInfo(); 2482 MFI.setFrameAddressIsTaken(true); 2483 EVT VT = Op.getValueType(); 2484 SDLoc DL(Op); 2485 SDValue FrameAddr = DAG.getCopyFromReg( 2486 DAG.getEntryNode(), DL, ABI.IsN64() ? Mips::FP_64 : Mips::FP, VT); 2487 return FrameAddr; 2488 } 2489 2490 SDValue MipsTargetLowering::lowerRETURNADDR(SDValue Op, 2491 SelectionDAG &DAG) const { 2492 if (verifyReturnAddressArgumentIsConstant(Op, DAG)) 2493 return SDValue(); 2494 2495 // check the depth 2496 if (cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue() != 0) { 2497 DAG.getContext()->emitError( 2498 "return address can be determined only for current frame"); 2499 return SDValue(); 2500 } 2501 2502 MachineFunction &MF = DAG.getMachineFunction(); 2503 MachineFrameInfo &MFI = MF.getFrameInfo(); 2504 MVT VT = Op.getSimpleValueType(); 2505 unsigned RA = ABI.IsN64() ? Mips::RA_64 : Mips::RA; 2506 MFI.setReturnAddressIsTaken(true); 2507 2508 // Return RA, which contains the return address. Mark it an implicit live-in. 2509 Register Reg = MF.addLiveIn(RA, getRegClassFor(VT)); 2510 return DAG.getCopyFromReg(DAG.getEntryNode(), SDLoc(Op), Reg, VT); 2511 } 2512 2513 // An EH_RETURN is the result of lowering llvm.eh.return which in turn is 2514 // generated from __builtin_eh_return (offset, handler) 2515 // The effect of this is to adjust the stack pointer by "offset" 2516 // and then branch to "handler". 2517 SDValue MipsTargetLowering::lowerEH_RETURN(SDValue Op, SelectionDAG &DAG) 2518 const { 2519 MachineFunction &MF = DAG.getMachineFunction(); 2520 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>(); 2521 2522 MipsFI->setCallsEhReturn(); 2523 SDValue Chain = Op.getOperand(0); 2524 SDValue Offset = Op.getOperand(1); 2525 SDValue Handler = Op.getOperand(2); 2526 SDLoc DL(Op); 2527 EVT Ty = ABI.IsN64() ? MVT::i64 : MVT::i32; 2528 2529 // Store stack offset in V1, store jump target in V0. Glue CopyToReg and 2530 // EH_RETURN nodes, so that instructions are emitted back-to-back. 2531 unsigned OffsetReg = ABI.IsN64() ? Mips::V1_64 : Mips::V1; 2532 unsigned AddrReg = ABI.IsN64() ? Mips::V0_64 : Mips::V0; 2533 Chain = DAG.getCopyToReg(Chain, DL, OffsetReg, Offset, SDValue()); 2534 Chain = DAG.getCopyToReg(Chain, DL, AddrReg, Handler, Chain.getValue(1)); 2535 return DAG.getNode(MipsISD::EH_RETURN, DL, MVT::Other, Chain, 2536 DAG.getRegister(OffsetReg, Ty), 2537 DAG.getRegister(AddrReg, getPointerTy(MF.getDataLayout())), 2538 Chain.getValue(1)); 2539 } 2540 2541 SDValue MipsTargetLowering::lowerATOMIC_FENCE(SDValue Op, 2542 SelectionDAG &DAG) const { 2543 // FIXME: Need pseudo-fence for 'singlethread' fences 2544 // FIXME: Set SType for weaker fences where supported/appropriate. 2545 unsigned SType = 0; 2546 SDLoc DL(Op); 2547 return DAG.getNode(MipsISD::Sync, DL, MVT::Other, Op.getOperand(0), 2548 DAG.getConstant(SType, DL, MVT::i32)); 2549 } 2550 2551 SDValue MipsTargetLowering::lowerShiftLeftParts(SDValue Op, 2552 SelectionDAG &DAG) const { 2553 SDLoc DL(Op); 2554 MVT VT = Subtarget.isGP64bit() ? MVT::i64 : MVT::i32; 2555 2556 SDValue Lo = Op.getOperand(0), Hi = Op.getOperand(1); 2557 SDValue Shamt = Op.getOperand(2); 2558 // if shamt < (VT.bits): 2559 // lo = (shl lo, shamt) 2560 // hi = (or (shl hi, shamt) (srl (srl lo, 1), ~shamt)) 2561 // else: 2562 // lo = 0 2563 // hi = (shl lo, shamt[4:0]) 2564 SDValue Not = DAG.getNode(ISD::XOR, DL, MVT::i32, Shamt, 2565 DAG.getConstant(-1, DL, MVT::i32)); 2566 SDValue ShiftRight1Lo = DAG.getNode(ISD::SRL, DL, VT, Lo, 2567 DAG.getConstant(1, DL, VT)); 2568 SDValue ShiftRightLo = DAG.getNode(ISD::SRL, DL, VT, ShiftRight1Lo, Not); 2569 SDValue ShiftLeftHi = DAG.getNode(ISD::SHL, DL, VT, Hi, Shamt); 2570 SDValue Or = DAG.getNode(ISD::OR, DL, VT, ShiftLeftHi, ShiftRightLo); 2571 SDValue ShiftLeftLo = DAG.getNode(ISD::SHL, DL, VT, Lo, Shamt); 2572 SDValue Cond = DAG.getNode(ISD::AND, DL, MVT::i32, Shamt, 2573 DAG.getConstant(VT.getSizeInBits(), DL, MVT::i32)); 2574 Lo = DAG.getNode(ISD::SELECT, DL, VT, Cond, 2575 DAG.getConstant(0, DL, VT), ShiftLeftLo); 2576 Hi = DAG.getNode(ISD::SELECT, DL, VT, Cond, ShiftLeftLo, Or); 2577 2578 SDValue Ops[2] = {Lo, Hi}; 2579 return DAG.getMergeValues(Ops, DL); 2580 } 2581 2582 SDValue MipsTargetLowering::lowerShiftRightParts(SDValue Op, SelectionDAG &DAG, 2583 bool IsSRA) const { 2584 SDLoc DL(Op); 2585 SDValue Lo = Op.getOperand(0), Hi = Op.getOperand(1); 2586 SDValue Shamt = Op.getOperand(2); 2587 MVT VT = Subtarget.isGP64bit() ? MVT::i64 : MVT::i32; 2588 2589 // if shamt < (VT.bits): 2590 // lo = (or (shl (shl hi, 1), ~shamt) (srl lo, shamt)) 2591 // if isSRA: 2592 // hi = (sra hi, shamt) 2593 // else: 2594 // hi = (srl hi, shamt) 2595 // else: 2596 // if isSRA: 2597 // lo = (sra hi, shamt[4:0]) 2598 // hi = (sra hi, 31) 2599 // else: 2600 // lo = (srl hi, shamt[4:0]) 2601 // hi = 0 2602 SDValue Not = DAG.getNode(ISD::XOR, DL, MVT::i32, Shamt, 2603 DAG.getConstant(-1, DL, MVT::i32)); 2604 SDValue ShiftLeft1Hi = DAG.getNode(ISD::SHL, DL, VT, Hi, 2605 DAG.getConstant(1, DL, VT)); 2606 SDValue ShiftLeftHi = DAG.getNode(ISD::SHL, DL, VT, ShiftLeft1Hi, Not); 2607 SDValue ShiftRightLo = DAG.getNode(ISD::SRL, DL, VT, Lo, Shamt); 2608 SDValue Or = DAG.getNode(ISD::OR, DL, VT, ShiftLeftHi, ShiftRightLo); 2609 SDValue ShiftRightHi = DAG.getNode(IsSRA ? ISD::SRA : ISD::SRL, 2610 DL, VT, Hi, Shamt); 2611 SDValue Cond = DAG.getNode(ISD::AND, DL, MVT::i32, Shamt, 2612 DAG.getConstant(VT.getSizeInBits(), DL, MVT::i32)); 2613 SDValue Ext = DAG.getNode(ISD::SRA, DL, VT, Hi, 2614 DAG.getConstant(VT.getSizeInBits() - 1, DL, VT)); 2615 2616 if (!(Subtarget.hasMips4() || Subtarget.hasMips32())) { 2617 SDVTList VTList = DAG.getVTList(VT, VT); 2618 return DAG.getNode(Subtarget.isGP64bit() ? Mips::PseudoD_SELECT_I64 2619 : Mips::PseudoD_SELECT_I, 2620 DL, VTList, Cond, ShiftRightHi, 2621 IsSRA ? Ext : DAG.getConstant(0, DL, VT), Or, 2622 ShiftRightHi); 2623 } 2624 2625 Lo = DAG.getNode(ISD::SELECT, DL, VT, Cond, ShiftRightHi, Or); 2626 Hi = DAG.getNode(ISD::SELECT, DL, VT, Cond, 2627 IsSRA ? Ext : DAG.getConstant(0, DL, VT), ShiftRightHi); 2628 2629 SDValue Ops[2] = {Lo, Hi}; 2630 return DAG.getMergeValues(Ops, DL); 2631 } 2632 2633 static SDValue createLoadLR(unsigned Opc, SelectionDAG &DAG, LoadSDNode *LD, 2634 SDValue Chain, SDValue Src, unsigned Offset) { 2635 SDValue Ptr = LD->getBasePtr(); 2636 EVT VT = LD->getValueType(0), MemVT = LD->getMemoryVT(); 2637 EVT BasePtrVT = Ptr.getValueType(); 2638 SDLoc DL(LD); 2639 SDVTList VTList = DAG.getVTList(VT, MVT::Other); 2640 2641 if (Offset) 2642 Ptr = DAG.getNode(ISD::ADD, DL, BasePtrVT, Ptr, 2643 DAG.getConstant(Offset, DL, BasePtrVT)); 2644 2645 SDValue Ops[] = { Chain, Ptr, Src }; 2646 return DAG.getMemIntrinsicNode(Opc, DL, VTList, Ops, MemVT, 2647 LD->getMemOperand()); 2648 } 2649 2650 // Expand an unaligned 32 or 64-bit integer load node. 2651 SDValue MipsTargetLowering::lowerLOAD(SDValue Op, SelectionDAG &DAG) const { 2652 LoadSDNode *LD = cast<LoadSDNode>(Op); 2653 EVT MemVT = LD->getMemoryVT(); 2654 2655 if (Subtarget.systemSupportsUnalignedAccess()) 2656 return Op; 2657 2658 // Return if load is aligned or if MemVT is neither i32 nor i64. 2659 if ((LD->getAlignment() >= MemVT.getSizeInBits() / 8) || 2660 ((MemVT != MVT::i32) && (MemVT != MVT::i64))) 2661 return SDValue(); 2662 2663 bool IsLittle = Subtarget.isLittle(); 2664 EVT VT = Op.getValueType(); 2665 ISD::LoadExtType ExtType = LD->getExtensionType(); 2666 SDValue Chain = LD->getChain(), Undef = DAG.getUNDEF(VT); 2667 2668 assert((VT == MVT::i32) || (VT == MVT::i64)); 2669 2670 // Expand 2671 // (set dst, (i64 (load baseptr))) 2672 // to 2673 // (set tmp, (ldl (add baseptr, 7), undef)) 2674 // (set dst, (ldr baseptr, tmp)) 2675 if ((VT == MVT::i64) && (ExtType == ISD::NON_EXTLOAD)) { 2676 SDValue LDL = createLoadLR(MipsISD::LDL, DAG, LD, Chain, Undef, 2677 IsLittle ? 7 : 0); 2678 return createLoadLR(MipsISD::LDR, DAG, LD, LDL.getValue(1), LDL, 2679 IsLittle ? 0 : 7); 2680 } 2681 2682 SDValue LWL = createLoadLR(MipsISD::LWL, DAG, LD, Chain, Undef, 2683 IsLittle ? 3 : 0); 2684 SDValue LWR = createLoadLR(MipsISD::LWR, DAG, LD, LWL.getValue(1), LWL, 2685 IsLittle ? 0 : 3); 2686 2687 // Expand 2688 // (set dst, (i32 (load baseptr))) or 2689 // (set dst, (i64 (sextload baseptr))) or 2690 // (set dst, (i64 (extload baseptr))) 2691 // to 2692 // (set tmp, (lwl (add baseptr, 3), undef)) 2693 // (set dst, (lwr baseptr, tmp)) 2694 if ((VT == MVT::i32) || (ExtType == ISD::SEXTLOAD) || 2695 (ExtType == ISD::EXTLOAD)) 2696 return LWR; 2697 2698 assert((VT == MVT::i64) && (ExtType == ISD::ZEXTLOAD)); 2699 2700 // Expand 2701 // (set dst, (i64 (zextload baseptr))) 2702 // to 2703 // (set tmp0, (lwl (add baseptr, 3), undef)) 2704 // (set tmp1, (lwr baseptr, tmp0)) 2705 // (set tmp2, (shl tmp1, 32)) 2706 // (set dst, (srl tmp2, 32)) 2707 SDLoc DL(LD); 2708 SDValue Const32 = DAG.getConstant(32, DL, MVT::i32); 2709 SDValue SLL = DAG.getNode(ISD::SHL, DL, MVT::i64, LWR, Const32); 2710 SDValue SRL = DAG.getNode(ISD::SRL, DL, MVT::i64, SLL, Const32); 2711 SDValue Ops[] = { SRL, LWR.getValue(1) }; 2712 return DAG.getMergeValues(Ops, DL); 2713 } 2714 2715 static SDValue createStoreLR(unsigned Opc, SelectionDAG &DAG, StoreSDNode *SD, 2716 SDValue Chain, unsigned Offset) { 2717 SDValue Ptr = SD->getBasePtr(), Value = SD->getValue(); 2718 EVT MemVT = SD->getMemoryVT(), BasePtrVT = Ptr.getValueType(); 2719 SDLoc DL(SD); 2720 SDVTList VTList = DAG.getVTList(MVT::Other); 2721 2722 if (Offset) 2723 Ptr = DAG.getNode(ISD::ADD, DL, BasePtrVT, Ptr, 2724 DAG.getConstant(Offset, DL, BasePtrVT)); 2725 2726 SDValue Ops[] = { Chain, Value, Ptr }; 2727 return DAG.getMemIntrinsicNode(Opc, DL, VTList, Ops, MemVT, 2728 SD->getMemOperand()); 2729 } 2730 2731 // Expand an unaligned 32 or 64-bit integer store node. 2732 static SDValue lowerUnalignedIntStore(StoreSDNode *SD, SelectionDAG &DAG, 2733 bool IsLittle) { 2734 SDValue Value = SD->getValue(), Chain = SD->getChain(); 2735 EVT VT = Value.getValueType(); 2736 2737 // Expand 2738 // (store val, baseptr) or 2739 // (truncstore val, baseptr) 2740 // to 2741 // (swl val, (add baseptr, 3)) 2742 // (swr val, baseptr) 2743 if ((VT == MVT::i32) || SD->isTruncatingStore()) { 2744 SDValue SWL = createStoreLR(MipsISD::SWL, DAG, SD, Chain, 2745 IsLittle ? 3 : 0); 2746 return createStoreLR(MipsISD::SWR, DAG, SD, SWL, IsLittle ? 0 : 3); 2747 } 2748 2749 assert(VT == MVT::i64); 2750 2751 // Expand 2752 // (store val, baseptr) 2753 // to 2754 // (sdl val, (add baseptr, 7)) 2755 // (sdr val, baseptr) 2756 SDValue SDL = createStoreLR(MipsISD::SDL, DAG, SD, Chain, IsLittle ? 7 : 0); 2757 return createStoreLR(MipsISD::SDR, DAG, SD, SDL, IsLittle ? 0 : 7); 2758 } 2759 2760 // Lower (store (fp_to_sint $fp) $ptr) to (store (TruncIntFP $fp), $ptr). 2761 static SDValue lowerFP_TO_SINT_STORE(StoreSDNode *SD, SelectionDAG &DAG, 2762 bool SingleFloat) { 2763 SDValue Val = SD->getValue(); 2764 2765 if (Val.getOpcode() != ISD::FP_TO_SINT || 2766 (Val.getValueSizeInBits() > 32 && SingleFloat)) 2767 return SDValue(); 2768 2769 EVT FPTy = EVT::getFloatingPointVT(Val.getValueSizeInBits()); 2770 SDValue Tr = DAG.getNode(MipsISD::TruncIntFP, SDLoc(Val), FPTy, 2771 Val.getOperand(0)); 2772 return DAG.getStore(SD->getChain(), SDLoc(SD), Tr, SD->getBasePtr(), 2773 SD->getPointerInfo(), SD->getAlignment(), 2774 SD->getMemOperand()->getFlags()); 2775 } 2776 2777 SDValue MipsTargetLowering::lowerSTORE(SDValue Op, SelectionDAG &DAG) const { 2778 StoreSDNode *SD = cast<StoreSDNode>(Op); 2779 EVT MemVT = SD->getMemoryVT(); 2780 2781 // Lower unaligned integer stores. 2782 if (!Subtarget.systemSupportsUnalignedAccess() && 2783 (SD->getAlignment() < MemVT.getSizeInBits() / 8) && 2784 ((MemVT == MVT::i32) || (MemVT == MVT::i64))) 2785 return lowerUnalignedIntStore(SD, DAG, Subtarget.isLittle()); 2786 2787 return lowerFP_TO_SINT_STORE(SD, DAG, Subtarget.isSingleFloat()); 2788 } 2789 2790 SDValue MipsTargetLowering::lowerEH_DWARF_CFA(SDValue Op, 2791 SelectionDAG &DAG) const { 2792 2793 // Return a fixed StackObject with offset 0 which points to the old stack 2794 // pointer. 2795 MachineFrameInfo &MFI = DAG.getMachineFunction().getFrameInfo(); 2796 EVT ValTy = Op->getValueType(0); 2797 int FI = MFI.CreateFixedObject(Op.getValueSizeInBits() / 8, 0, false); 2798 return DAG.getFrameIndex(FI, ValTy); 2799 } 2800 2801 SDValue MipsTargetLowering::lowerFP_TO_SINT(SDValue Op, 2802 SelectionDAG &DAG) const { 2803 if (Op.getValueSizeInBits() > 32 && Subtarget.isSingleFloat()) 2804 return SDValue(); 2805 2806 EVT FPTy = EVT::getFloatingPointVT(Op.getValueSizeInBits()); 2807 SDValue Trunc = DAG.getNode(MipsISD::TruncIntFP, SDLoc(Op), FPTy, 2808 Op.getOperand(0)); 2809 return DAG.getNode(ISD::BITCAST, SDLoc(Op), Op.getValueType(), Trunc); 2810 } 2811 2812 //===----------------------------------------------------------------------===// 2813 // Calling Convention Implementation 2814 //===----------------------------------------------------------------------===// 2815 2816 //===----------------------------------------------------------------------===// 2817 // TODO: Implement a generic logic using tblgen that can support this. 2818 // Mips O32 ABI rules: 2819 // --- 2820 // i32 - Passed in A0, A1, A2, A3 and stack 2821 // f32 - Only passed in f32 registers if no int reg has been used yet to hold 2822 // an argument. Otherwise, passed in A1, A2, A3 and stack. 2823 // f64 - Only passed in two aliased f32 registers if no int reg has been used 2824 // yet to hold an argument. Otherwise, use A2, A3 and stack. If A1 is 2825 // not used, it must be shadowed. If only A3 is available, shadow it and 2826 // go to stack. 2827 // vXiX - Received as scalarized i32s, passed in A0 - A3 and the stack. 2828 // vXf32 - Passed in either a pair of registers {A0, A1}, {A2, A3} or {A0 - A3} 2829 // with the remainder spilled to the stack. 2830 // vXf64 - Passed in either {A0, A1, A2, A3} or {A2, A3} and in both cases 2831 // spilling the remainder to the stack. 2832 // 2833 // For vararg functions, all arguments are passed in A0, A1, A2, A3 and stack. 2834 //===----------------------------------------------------------------------===// 2835 2836 static bool CC_MipsO32(unsigned ValNo, MVT ValVT, MVT LocVT, 2837 CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, 2838 CCState &State, ArrayRef<MCPhysReg> F64Regs) { 2839 const MipsSubtarget &Subtarget = static_cast<const MipsSubtarget &>( 2840 State.getMachineFunction().getSubtarget()); 2841 2842 static const MCPhysReg IntRegs[] = { Mips::A0, Mips::A1, Mips::A2, Mips::A3 }; 2843 2844 const MipsCCState * MipsState = static_cast<MipsCCState *>(&State); 2845 2846 static const MCPhysReg F32Regs[] = { Mips::F12, Mips::F14 }; 2847 2848 static const MCPhysReg FloatVectorIntRegs[] = { Mips::A0, Mips::A2 }; 2849 2850 // Do not process byval args here. 2851 if (ArgFlags.isByVal()) 2852 return true; 2853 2854 // Promote i8 and i16 2855 if (ArgFlags.isInReg() && !Subtarget.isLittle()) { 2856 if (LocVT == MVT::i8 || LocVT == MVT::i16 || LocVT == MVT::i32) { 2857 LocVT = MVT::i32; 2858 if (ArgFlags.isSExt()) 2859 LocInfo = CCValAssign::SExtUpper; 2860 else if (ArgFlags.isZExt()) 2861 LocInfo = CCValAssign::ZExtUpper; 2862 else 2863 LocInfo = CCValAssign::AExtUpper; 2864 } 2865 } 2866 2867 // Promote i8 and i16 2868 if (LocVT == MVT::i8 || LocVT == MVT::i16) { 2869 LocVT = MVT::i32; 2870 if (ArgFlags.isSExt()) 2871 LocInfo = CCValAssign::SExt; 2872 else if (ArgFlags.isZExt()) 2873 LocInfo = CCValAssign::ZExt; 2874 else 2875 LocInfo = CCValAssign::AExt; 2876 } 2877 2878 unsigned Reg; 2879 2880 // f32 and f64 are allocated in A0, A1, A2, A3 when either of the following 2881 // is true: function is vararg, argument is 3rd or higher, there is previous 2882 // argument which is not f32 or f64. 2883 bool AllocateFloatsInIntReg = State.isVarArg() || ValNo > 1 || 2884 State.getFirstUnallocated(F32Regs) != ValNo; 2885 Align OrigAlign = ArgFlags.getNonZeroOrigAlign(); 2886 bool isI64 = (ValVT == MVT::i32 && OrigAlign == Align(8)); 2887 bool isVectorFloat = MipsState->WasOriginalArgVectorFloat(ValNo); 2888 2889 // The MIPS vector ABI for floats passes them in a pair of registers 2890 if (ValVT == MVT::i32 && isVectorFloat) { 2891 // This is the start of an vector that was scalarized into an unknown number 2892 // of components. It doesn't matter how many there are. Allocate one of the 2893 // notional 8 byte aligned registers which map onto the argument stack, and 2894 // shadow the register lost to alignment requirements. 2895 if (ArgFlags.isSplit()) { 2896 Reg = State.AllocateReg(FloatVectorIntRegs); 2897 if (Reg == Mips::A2) 2898 State.AllocateReg(Mips::A1); 2899 else if (Reg == 0) 2900 State.AllocateReg(Mips::A3); 2901 } else { 2902 // If we're an intermediate component of the split, we can just attempt to 2903 // allocate a register directly. 2904 Reg = State.AllocateReg(IntRegs); 2905 } 2906 } else if (ValVT == MVT::i32 || 2907 (ValVT == MVT::f32 && AllocateFloatsInIntReg)) { 2908 Reg = State.AllocateReg(IntRegs); 2909 // If this is the first part of an i64 arg, 2910 // the allocated register must be either A0 or A2. 2911 if (isI64 && (Reg == Mips::A1 || Reg == Mips::A3)) 2912 Reg = State.AllocateReg(IntRegs); 2913 LocVT = MVT::i32; 2914 } else if (ValVT == MVT::f64 && AllocateFloatsInIntReg) { 2915 LocVT = MVT::i32; 2916 2917 // Allocate int register and shadow next int register. If first 2918 // available register is Mips::A1 or Mips::A3, shadow it too. 2919 Reg = State.AllocateReg(IntRegs); 2920 if (Reg == Mips::A1 || Reg == Mips::A3) 2921 Reg = State.AllocateReg(IntRegs); 2922 2923 if (Reg) { 2924 State.addLoc( 2925 CCValAssign::getCustomReg(ValNo, ValVT, Reg, LocVT, LocInfo)); 2926 MCRegister HiReg = State.AllocateReg(IntRegs); 2927 assert(HiReg); 2928 State.addLoc( 2929 CCValAssign::getCustomReg(ValNo, ValVT, HiReg, LocVT, LocInfo)); 2930 return false; 2931 } 2932 } else if (ValVT.isFloatingPoint() && !AllocateFloatsInIntReg) { 2933 // we are guaranteed to find an available float register 2934 if (ValVT == MVT::f32) { 2935 Reg = State.AllocateReg(F32Regs); 2936 // Shadow int register 2937 State.AllocateReg(IntRegs); 2938 } else { 2939 Reg = State.AllocateReg(F64Regs); 2940 // Shadow int registers 2941 unsigned Reg2 = State.AllocateReg(IntRegs); 2942 if (Reg2 == Mips::A1 || Reg2 == Mips::A3) 2943 State.AllocateReg(IntRegs); 2944 State.AllocateReg(IntRegs); 2945 } 2946 } else 2947 llvm_unreachable("Cannot handle this ValVT."); 2948 2949 if (!Reg) { 2950 unsigned Offset = State.AllocateStack(ValVT.getStoreSize(), OrigAlign); 2951 State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo)); 2952 } else 2953 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); 2954 2955 return false; 2956 } 2957 2958 static bool CC_MipsO32_FP32(unsigned ValNo, MVT ValVT, 2959 MVT LocVT, CCValAssign::LocInfo LocInfo, 2960 ISD::ArgFlagsTy ArgFlags, CCState &State) { 2961 static const MCPhysReg F64Regs[] = { Mips::D6, Mips::D7 }; 2962 2963 return CC_MipsO32(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State, F64Regs); 2964 } 2965 2966 static bool CC_MipsO32_FP64(unsigned ValNo, MVT ValVT, 2967 MVT LocVT, CCValAssign::LocInfo LocInfo, 2968 ISD::ArgFlagsTy ArgFlags, CCState &State) { 2969 static const MCPhysReg F64Regs[] = { Mips::D12_64, Mips::D14_64 }; 2970 2971 return CC_MipsO32(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State, F64Regs); 2972 } 2973 2974 static bool CC_MipsO32(unsigned ValNo, MVT ValVT, MVT LocVT, 2975 CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, 2976 CCState &State) LLVM_ATTRIBUTE_UNUSED; 2977 2978 #include "MipsGenCallingConv.inc" 2979 2980 CCAssignFn *MipsTargetLowering::CCAssignFnForCall() const{ 2981 return CC_Mips_FixedArg; 2982 } 2983 2984 CCAssignFn *MipsTargetLowering::CCAssignFnForReturn() const{ 2985 return RetCC_Mips; 2986 } 2987 //===----------------------------------------------------------------------===// 2988 // Call Calling Convention Implementation 2989 //===----------------------------------------------------------------------===// 2990 2991 SDValue MipsTargetLowering::passArgOnStack(SDValue StackPtr, unsigned Offset, 2992 SDValue Chain, SDValue Arg, 2993 const SDLoc &DL, bool IsTailCall, 2994 SelectionDAG &DAG) const { 2995 if (!IsTailCall) { 2996 SDValue PtrOff = 2997 DAG.getNode(ISD::ADD, DL, getPointerTy(DAG.getDataLayout()), StackPtr, 2998 DAG.getIntPtrConstant(Offset, DL)); 2999 return DAG.getStore(Chain, DL, Arg, PtrOff, MachinePointerInfo()); 3000 } 3001 3002 MachineFrameInfo &MFI = DAG.getMachineFunction().getFrameInfo(); 3003 int FI = MFI.CreateFixedObject(Arg.getValueSizeInBits() / 8, Offset, false); 3004 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy(DAG.getDataLayout())); 3005 return DAG.getStore(Chain, DL, Arg, FIN, MachinePointerInfo(), MaybeAlign(), 3006 MachineMemOperand::MOVolatile); 3007 } 3008 3009 void MipsTargetLowering:: 3010 getOpndList(SmallVectorImpl<SDValue> &Ops, 3011 std::deque<std::pair<unsigned, SDValue>> &RegsToPass, 3012 bool IsPICCall, bool GlobalOrExternal, bool InternalLinkage, 3013 bool IsCallReloc, CallLoweringInfo &CLI, SDValue Callee, 3014 SDValue Chain) const { 3015 // Insert node "GP copy globalreg" before call to function. 3016 // 3017 // R_MIPS_CALL* operators (emitted when non-internal functions are called 3018 // in PIC mode) allow symbols to be resolved via lazy binding. 3019 // The lazy binding stub requires GP to point to the GOT. 3020 // Note that we don't need GP to point to the GOT for indirect calls 3021 // (when R_MIPS_CALL* is not used for the call) because Mips linker generates 3022 // lazy binding stub for a function only when R_MIPS_CALL* are the only relocs 3023 // used for the function (that is, Mips linker doesn't generate lazy binding 3024 // stub for a function whose address is taken in the program). 3025 if (IsPICCall && !InternalLinkage && IsCallReloc) { 3026 unsigned GPReg = ABI.IsN64() ? Mips::GP_64 : Mips::GP; 3027 EVT Ty = ABI.IsN64() ? MVT::i64 : MVT::i32; 3028 RegsToPass.push_back(std::make_pair(GPReg, getGlobalReg(CLI.DAG, Ty))); 3029 } 3030 3031 // Build a sequence of copy-to-reg nodes chained together with token 3032 // chain and flag operands which copy the outgoing args into registers. 3033 // The InFlag in necessary since all emitted instructions must be 3034 // stuck together. 3035 SDValue InFlag; 3036 3037 for (auto &R : RegsToPass) { 3038 Chain = CLI.DAG.getCopyToReg(Chain, CLI.DL, R.first, R.second, InFlag); 3039 InFlag = Chain.getValue(1); 3040 } 3041 3042 // Add argument registers to the end of the list so that they are 3043 // known live into the call. 3044 for (auto &R : RegsToPass) 3045 Ops.push_back(CLI.DAG.getRegister(R.first, R.second.getValueType())); 3046 3047 // Add a register mask operand representing the call-preserved registers. 3048 const TargetRegisterInfo *TRI = Subtarget.getRegisterInfo(); 3049 const uint32_t *Mask = 3050 TRI->getCallPreservedMask(CLI.DAG.getMachineFunction(), CLI.CallConv); 3051 assert(Mask && "Missing call preserved mask for calling convention"); 3052 if (Subtarget.inMips16HardFloat()) { 3053 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(CLI.Callee)) { 3054 StringRef Sym = G->getGlobal()->getName(); 3055 Function *F = G->getGlobal()->getParent()->getFunction(Sym); 3056 if (F && F->hasFnAttribute("__Mips16RetHelper")) { 3057 Mask = MipsRegisterInfo::getMips16RetHelperMask(); 3058 } 3059 } 3060 } 3061 Ops.push_back(CLI.DAG.getRegisterMask(Mask)); 3062 3063 if (InFlag.getNode()) 3064 Ops.push_back(InFlag); 3065 } 3066 3067 void MipsTargetLowering::AdjustInstrPostInstrSelection(MachineInstr &MI, 3068 SDNode *Node) const { 3069 switch (MI.getOpcode()) { 3070 default: 3071 return; 3072 case Mips::JALR: 3073 case Mips::JALRPseudo: 3074 case Mips::JALR64: 3075 case Mips::JALR64Pseudo: 3076 case Mips::JALR16_MM: 3077 case Mips::JALRC16_MMR6: 3078 case Mips::TAILCALLREG: 3079 case Mips::TAILCALLREG64: 3080 case Mips::TAILCALLR6REG: 3081 case Mips::TAILCALL64R6REG: 3082 case Mips::TAILCALLREG_MM: 3083 case Mips::TAILCALLREG_MMR6: { 3084 if (!EmitJalrReloc || 3085 Subtarget.inMips16Mode() || 3086 !isPositionIndependent() || 3087 Node->getNumOperands() < 1 || 3088 Node->getOperand(0).getNumOperands() < 2) { 3089 return; 3090 } 3091 // We are after the callee address, set by LowerCall(). 3092 // If added to MI, asm printer will emit .reloc R_MIPS_JALR for the 3093 // symbol. 3094 const SDValue TargetAddr = Node->getOperand(0).getOperand(1); 3095 StringRef Sym; 3096 if (const GlobalAddressSDNode *G = 3097 dyn_cast_or_null<const GlobalAddressSDNode>(TargetAddr)) { 3098 // We must not emit the R_MIPS_JALR relocation against data symbols 3099 // since this will cause run-time crashes if the linker replaces the 3100 // call instruction with a relative branch to the data symbol. 3101 if (!isa<Function>(G->getGlobal())) { 3102 LLVM_DEBUG(dbgs() << "Not adding R_MIPS_JALR against data symbol " 3103 << G->getGlobal()->getName() << "\n"); 3104 return; 3105 } 3106 Sym = G->getGlobal()->getName(); 3107 } 3108 else if (const ExternalSymbolSDNode *ES = 3109 dyn_cast_or_null<const ExternalSymbolSDNode>(TargetAddr)) { 3110 Sym = ES->getSymbol(); 3111 } 3112 3113 if (Sym.empty()) 3114 return; 3115 3116 MachineFunction *MF = MI.getParent()->getParent(); 3117 MCSymbol *S = MF->getContext().getOrCreateSymbol(Sym); 3118 LLVM_DEBUG(dbgs() << "Adding R_MIPS_JALR against " << Sym << "\n"); 3119 MI.addOperand(MachineOperand::CreateMCSymbol(S, MipsII::MO_JALR)); 3120 } 3121 } 3122 } 3123 3124 /// LowerCall - functions arguments are copied from virtual regs to 3125 /// (physical regs)/(stack frame), CALLSEQ_START and CALLSEQ_END are emitted. 3126 SDValue 3127 MipsTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI, 3128 SmallVectorImpl<SDValue> &InVals) const { 3129 SelectionDAG &DAG = CLI.DAG; 3130 SDLoc DL = CLI.DL; 3131 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs; 3132 SmallVectorImpl<SDValue> &OutVals = CLI.OutVals; 3133 SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins; 3134 SDValue Chain = CLI.Chain; 3135 SDValue Callee = CLI.Callee; 3136 bool &IsTailCall = CLI.IsTailCall; 3137 CallingConv::ID CallConv = CLI.CallConv; 3138 bool IsVarArg = CLI.IsVarArg; 3139 3140 MachineFunction &MF = DAG.getMachineFunction(); 3141 MachineFrameInfo &MFI = MF.getFrameInfo(); 3142 const TargetFrameLowering *TFL = Subtarget.getFrameLowering(); 3143 MipsFunctionInfo *FuncInfo = MF.getInfo<MipsFunctionInfo>(); 3144 bool IsPIC = isPositionIndependent(); 3145 3146 // Analyze operands of the call, assigning locations to each operand. 3147 SmallVector<CCValAssign, 16> ArgLocs; 3148 MipsCCState CCInfo( 3149 CallConv, IsVarArg, DAG.getMachineFunction(), ArgLocs, *DAG.getContext(), 3150 MipsCCState::getSpecialCallingConvForCallee(Callee.getNode(), Subtarget)); 3151 3152 const ExternalSymbolSDNode *ES = 3153 dyn_cast_or_null<const ExternalSymbolSDNode>(Callee.getNode()); 3154 3155 // There is one case where CALLSEQ_START..CALLSEQ_END can be nested, which 3156 // is during the lowering of a call with a byval argument which produces 3157 // a call to memcpy. For the O32 case, this causes the caller to allocate 3158 // stack space for the reserved argument area for the callee, then recursively 3159 // again for the memcpy call. In the NEWABI case, this doesn't occur as those 3160 // ABIs mandate that the callee allocates the reserved argument area. We do 3161 // still produce nested CALLSEQ_START..CALLSEQ_END with zero space though. 3162 // 3163 // If the callee has a byval argument and memcpy is used, we are mandated 3164 // to already have produced a reserved argument area for the callee for O32. 3165 // Therefore, the reserved argument area can be reused for both calls. 3166 // 3167 // Other cases of calling memcpy cannot have a chain with a CALLSEQ_START 3168 // present, as we have yet to hook that node onto the chain. 3169 // 3170 // Hence, the CALLSEQ_START and CALLSEQ_END nodes can be eliminated in this 3171 // case. GCC does a similar trick, in that wherever possible, it calculates 3172 // the maximum out going argument area (including the reserved area), and 3173 // preallocates the stack space on entrance to the caller. 3174 // 3175 // FIXME: We should do the same for efficiency and space. 3176 3177 // Note: The check on the calling convention below must match 3178 // MipsABIInfo::GetCalleeAllocdArgSizeInBytes(). 3179 bool MemcpyInByVal = ES && 3180 StringRef(ES->getSymbol()) == StringRef("memcpy") && 3181 CallConv != CallingConv::Fast && 3182 Chain.getOpcode() == ISD::CALLSEQ_START; 3183 3184 // Allocate the reserved argument area. It seems strange to do this from the 3185 // caller side but removing it breaks the frame size calculation. 3186 unsigned ReservedArgArea = 3187 MemcpyInByVal ? 0 : ABI.GetCalleeAllocdArgSizeInBytes(CallConv); 3188 CCInfo.AllocateStack(ReservedArgArea, Align(1)); 3189 3190 CCInfo.AnalyzeCallOperands(Outs, CC_Mips, CLI.getArgs(), 3191 ES ? ES->getSymbol() : nullptr); 3192 3193 // Get a count of how many bytes are to be pushed on the stack. 3194 unsigned NextStackOffset = CCInfo.getNextStackOffset(); 3195 3196 // Call site info for function parameters tracking. 3197 MachineFunction::CallSiteInfo CSInfo; 3198 3199 // Check if it's really possible to do a tail call. Restrict it to functions 3200 // that are part of this compilation unit. 3201 bool InternalLinkage = false; 3202 if (IsTailCall) { 3203 IsTailCall = isEligibleForTailCallOptimization( 3204 CCInfo, NextStackOffset, *MF.getInfo<MipsFunctionInfo>()); 3205 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) { 3206 InternalLinkage = G->getGlobal()->hasInternalLinkage(); 3207 IsTailCall &= (InternalLinkage || G->getGlobal()->hasLocalLinkage() || 3208 G->getGlobal()->hasPrivateLinkage() || 3209 G->getGlobal()->hasHiddenVisibility() || 3210 G->getGlobal()->hasProtectedVisibility()); 3211 } 3212 } 3213 if (!IsTailCall && CLI.CB && CLI.CB->isMustTailCall()) 3214 report_fatal_error("failed to perform tail call elimination on a call " 3215 "site marked musttail"); 3216 3217 if (IsTailCall) 3218 ++NumTailCalls; 3219 3220 // Chain is the output chain of the last Load/Store or CopyToReg node. 3221 // ByValChain is the output chain of the last Memcpy node created for copying 3222 // byval arguments to the stack. 3223 unsigned StackAlignment = TFL->getStackAlignment(); 3224 NextStackOffset = alignTo(NextStackOffset, StackAlignment); 3225 SDValue NextStackOffsetVal = DAG.getIntPtrConstant(NextStackOffset, DL, true); 3226 3227 if (!(IsTailCall || MemcpyInByVal)) 3228 Chain = DAG.getCALLSEQ_START(Chain, NextStackOffset, 0, DL); 3229 3230 SDValue StackPtr = 3231 DAG.getCopyFromReg(Chain, DL, ABI.IsN64() ? Mips::SP_64 : Mips::SP, 3232 getPointerTy(DAG.getDataLayout())); 3233 3234 std::deque<std::pair<unsigned, SDValue>> RegsToPass; 3235 SmallVector<SDValue, 8> MemOpChains; 3236 3237 CCInfo.rewindByValRegsInfo(); 3238 3239 // Walk the register/memloc assignments, inserting copies/loads. 3240 for (unsigned i = 0, e = ArgLocs.size(), OutIdx = 0; i != e; ++i, ++OutIdx) { 3241 SDValue Arg = OutVals[OutIdx]; 3242 CCValAssign &VA = ArgLocs[i]; 3243 MVT ValVT = VA.getValVT(), LocVT = VA.getLocVT(); 3244 ISD::ArgFlagsTy Flags = Outs[OutIdx].Flags; 3245 bool UseUpperBits = false; 3246 3247 // ByVal Arg. 3248 if (Flags.isByVal()) { 3249 unsigned FirstByValReg, LastByValReg; 3250 unsigned ByValIdx = CCInfo.getInRegsParamsProcessed(); 3251 CCInfo.getInRegsParamInfo(ByValIdx, FirstByValReg, LastByValReg); 3252 3253 assert(Flags.getByValSize() && 3254 "ByVal args of size 0 should have been ignored by front-end."); 3255 assert(ByValIdx < CCInfo.getInRegsParamsCount()); 3256 assert(!IsTailCall && 3257 "Do not tail-call optimize if there is a byval argument."); 3258 passByValArg(Chain, DL, RegsToPass, MemOpChains, StackPtr, MFI, DAG, Arg, 3259 FirstByValReg, LastByValReg, Flags, Subtarget.isLittle(), 3260 VA); 3261 CCInfo.nextInRegsParam(); 3262 continue; 3263 } 3264 3265 // Promote the value if needed. 3266 switch (VA.getLocInfo()) { 3267 default: 3268 llvm_unreachable("Unknown loc info!"); 3269 case CCValAssign::Full: 3270 if (VA.isRegLoc()) { 3271 if ((ValVT == MVT::f32 && LocVT == MVT::i32) || 3272 (ValVT == MVT::f64 && LocVT == MVT::i64) || 3273 (ValVT == MVT::i64 && LocVT == MVT::f64)) 3274 Arg = DAG.getNode(ISD::BITCAST, DL, LocVT, Arg); 3275 else if (ValVT == MVT::f64 && LocVT == MVT::i32) { 3276 SDValue Lo = DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32, 3277 Arg, DAG.getConstant(0, DL, MVT::i32)); 3278 SDValue Hi = DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32, 3279 Arg, DAG.getConstant(1, DL, MVT::i32)); 3280 if (!Subtarget.isLittle()) 3281 std::swap(Lo, Hi); 3282 3283 assert(VA.needsCustom()); 3284 3285 Register LocRegLo = VA.getLocReg(); 3286 Register LocRegHigh = ArgLocs[++i].getLocReg(); 3287 RegsToPass.push_back(std::make_pair(LocRegLo, Lo)); 3288 RegsToPass.push_back(std::make_pair(LocRegHigh, Hi)); 3289 continue; 3290 } 3291 } 3292 break; 3293 case CCValAssign::BCvt: 3294 Arg = DAG.getNode(ISD::BITCAST, DL, LocVT, Arg); 3295 break; 3296 case CCValAssign::SExtUpper: 3297 UseUpperBits = true; 3298 LLVM_FALLTHROUGH; 3299 case CCValAssign::SExt: 3300 Arg = DAG.getNode(ISD::SIGN_EXTEND, DL, LocVT, Arg); 3301 break; 3302 case CCValAssign::ZExtUpper: 3303 UseUpperBits = true; 3304 LLVM_FALLTHROUGH; 3305 case CCValAssign::ZExt: 3306 Arg = DAG.getNode(ISD::ZERO_EXTEND, DL, LocVT, Arg); 3307 break; 3308 case CCValAssign::AExtUpper: 3309 UseUpperBits = true; 3310 LLVM_FALLTHROUGH; 3311 case CCValAssign::AExt: 3312 Arg = DAG.getNode(ISD::ANY_EXTEND, DL, LocVT, Arg); 3313 break; 3314 } 3315 3316 if (UseUpperBits) { 3317 unsigned ValSizeInBits = Outs[OutIdx].ArgVT.getSizeInBits(); 3318 unsigned LocSizeInBits = VA.getLocVT().getSizeInBits(); 3319 Arg = DAG.getNode( 3320 ISD::SHL, DL, VA.getLocVT(), Arg, 3321 DAG.getConstant(LocSizeInBits - ValSizeInBits, DL, VA.getLocVT())); 3322 } 3323 3324 // Arguments that can be passed on register must be kept at 3325 // RegsToPass vector 3326 if (VA.isRegLoc()) { 3327 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg)); 3328 3329 // If the parameter is passed through reg $D, which splits into 3330 // two physical registers, avoid creating call site info. 3331 if (Mips::AFGR64RegClass.contains(VA.getLocReg())) 3332 continue; 3333 3334 // Collect CSInfo about which register passes which parameter. 3335 const TargetOptions &Options = DAG.getTarget().Options; 3336 if (Options.SupportsDebugEntryValues) 3337 CSInfo.emplace_back(VA.getLocReg(), i); 3338 3339 continue; 3340 } 3341 3342 // Register can't get to this point... 3343 assert(VA.isMemLoc()); 3344 3345 // emit ISD::STORE whichs stores the 3346 // parameter value to a stack Location 3347 MemOpChains.push_back(passArgOnStack(StackPtr, VA.getLocMemOffset(), 3348 Chain, Arg, DL, IsTailCall, DAG)); 3349 } 3350 3351 // Transform all store nodes into one single node because all store 3352 // nodes are independent of each other. 3353 if (!MemOpChains.empty()) 3354 Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, MemOpChains); 3355 3356 // If the callee is a GlobalAddress/ExternalSymbol node (quite common, every 3357 // direct call is) turn it into a TargetGlobalAddress/TargetExternalSymbol 3358 // node so that legalize doesn't hack it. 3359 3360 EVT Ty = Callee.getValueType(); 3361 bool GlobalOrExternal = false, IsCallReloc = false; 3362 3363 // The long-calls feature is ignored in case of PIC. 3364 // While we do not support -mshared / -mno-shared properly, 3365 // ignore long-calls in case of -mabicalls too. 3366 if (!Subtarget.isABICalls() && !IsPIC) { 3367 // If the function should be called using "long call", 3368 // get its address into a register to prevent using 3369 // of the `jal` instruction for the direct call. 3370 if (auto *N = dyn_cast<ExternalSymbolSDNode>(Callee)) { 3371 if (Subtarget.useLongCalls()) 3372 Callee = Subtarget.hasSym32() 3373 ? getAddrNonPIC(N, SDLoc(N), Ty, DAG) 3374 : getAddrNonPICSym64(N, SDLoc(N), Ty, DAG); 3375 } else if (auto *N = dyn_cast<GlobalAddressSDNode>(Callee)) { 3376 bool UseLongCalls = Subtarget.useLongCalls(); 3377 // If the function has long-call/far/near attribute 3378 // it overrides command line switch pased to the backend. 3379 if (auto *F = dyn_cast<Function>(N->getGlobal())) { 3380 if (F->hasFnAttribute("long-call")) 3381 UseLongCalls = true; 3382 else if (F->hasFnAttribute("short-call")) 3383 UseLongCalls = false; 3384 } 3385 if (UseLongCalls) 3386 Callee = Subtarget.hasSym32() 3387 ? getAddrNonPIC(N, SDLoc(N), Ty, DAG) 3388 : getAddrNonPICSym64(N, SDLoc(N), Ty, DAG); 3389 } 3390 } 3391 3392 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) { 3393 if (IsPIC) { 3394 const GlobalValue *Val = G->getGlobal(); 3395 InternalLinkage = Val->hasInternalLinkage(); 3396 3397 if (InternalLinkage) 3398 Callee = getAddrLocal(G, DL, Ty, DAG, ABI.IsN32() || ABI.IsN64()); 3399 else if (Subtarget.useXGOT()) { 3400 Callee = getAddrGlobalLargeGOT(G, DL, Ty, DAG, MipsII::MO_CALL_HI16, 3401 MipsII::MO_CALL_LO16, Chain, 3402 FuncInfo->callPtrInfo(MF, Val)); 3403 IsCallReloc = true; 3404 } else { 3405 Callee = getAddrGlobal(G, DL, Ty, DAG, MipsII::MO_GOT_CALL, Chain, 3406 FuncInfo->callPtrInfo(MF, Val)); 3407 IsCallReloc = true; 3408 } 3409 } else 3410 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), DL, 3411 getPointerTy(DAG.getDataLayout()), 0, 3412 MipsII::MO_NO_FLAG); 3413 GlobalOrExternal = true; 3414 } 3415 else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) { 3416 const char *Sym = S->getSymbol(); 3417 3418 if (!IsPIC) // static 3419 Callee = DAG.getTargetExternalSymbol( 3420 Sym, getPointerTy(DAG.getDataLayout()), MipsII::MO_NO_FLAG); 3421 else if (Subtarget.useXGOT()) { 3422 Callee = getAddrGlobalLargeGOT(S, DL, Ty, DAG, MipsII::MO_CALL_HI16, 3423 MipsII::MO_CALL_LO16, Chain, 3424 FuncInfo->callPtrInfo(MF, Sym)); 3425 IsCallReloc = true; 3426 } else { // PIC 3427 Callee = getAddrGlobal(S, DL, Ty, DAG, MipsII::MO_GOT_CALL, Chain, 3428 FuncInfo->callPtrInfo(MF, Sym)); 3429 IsCallReloc = true; 3430 } 3431 3432 GlobalOrExternal = true; 3433 } 3434 3435 SmallVector<SDValue, 8> Ops(1, Chain); 3436 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue); 3437 3438 getOpndList(Ops, RegsToPass, IsPIC, GlobalOrExternal, InternalLinkage, 3439 IsCallReloc, CLI, Callee, Chain); 3440 3441 if (IsTailCall) { 3442 MF.getFrameInfo().setHasTailCall(); 3443 SDValue Ret = DAG.getNode(MipsISD::TailCall, DL, MVT::Other, Ops); 3444 DAG.addCallSiteInfo(Ret.getNode(), std::move(CSInfo)); 3445 return Ret; 3446 } 3447 3448 Chain = DAG.getNode(MipsISD::JmpLink, DL, NodeTys, Ops); 3449 SDValue InFlag = Chain.getValue(1); 3450 3451 DAG.addCallSiteInfo(Chain.getNode(), std::move(CSInfo)); 3452 3453 // Create the CALLSEQ_END node in the case of where it is not a call to 3454 // memcpy. 3455 if (!(MemcpyInByVal)) { 3456 Chain = DAG.getCALLSEQ_END(Chain, NextStackOffsetVal, 3457 DAG.getIntPtrConstant(0, DL, true), InFlag, DL); 3458 InFlag = Chain.getValue(1); 3459 } 3460 3461 // Handle result values, copying them out of physregs into vregs that we 3462 // return. 3463 return LowerCallResult(Chain, InFlag, CallConv, IsVarArg, Ins, DL, DAG, 3464 InVals, CLI); 3465 } 3466 3467 /// LowerCallResult - Lower the result values of a call into the 3468 /// appropriate copies out of appropriate physical registers. 3469 SDValue MipsTargetLowering::LowerCallResult( 3470 SDValue Chain, SDValue InFlag, CallingConv::ID CallConv, bool IsVarArg, 3471 const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &DL, 3472 SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals, 3473 TargetLowering::CallLoweringInfo &CLI) const { 3474 // Assign locations to each value returned by this call. 3475 SmallVector<CCValAssign, 16> RVLocs; 3476 MipsCCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), RVLocs, 3477 *DAG.getContext()); 3478 3479 const ExternalSymbolSDNode *ES = 3480 dyn_cast_or_null<const ExternalSymbolSDNode>(CLI.Callee.getNode()); 3481 CCInfo.AnalyzeCallResult(Ins, RetCC_Mips, CLI.RetTy, 3482 ES ? ES->getSymbol() : nullptr); 3483 3484 // Copy all of the result registers out of their specified physreg. 3485 for (unsigned i = 0; i != RVLocs.size(); ++i) { 3486 CCValAssign &VA = RVLocs[i]; 3487 assert(VA.isRegLoc() && "Can only return in registers!"); 3488 3489 SDValue Val = DAG.getCopyFromReg(Chain, DL, RVLocs[i].getLocReg(), 3490 RVLocs[i].getLocVT(), InFlag); 3491 Chain = Val.getValue(1); 3492 InFlag = Val.getValue(2); 3493 3494 if (VA.isUpperBitsInLoc()) { 3495 unsigned ValSizeInBits = Ins[i].ArgVT.getSizeInBits(); 3496 unsigned LocSizeInBits = VA.getLocVT().getSizeInBits(); 3497 unsigned Shift = 3498 VA.getLocInfo() == CCValAssign::ZExtUpper ? ISD::SRL : ISD::SRA; 3499 Val = DAG.getNode( 3500 Shift, DL, VA.getLocVT(), Val, 3501 DAG.getConstant(LocSizeInBits - ValSizeInBits, DL, VA.getLocVT())); 3502 } 3503 3504 switch (VA.getLocInfo()) { 3505 default: 3506 llvm_unreachable("Unknown loc info!"); 3507 case CCValAssign::Full: 3508 break; 3509 case CCValAssign::BCvt: 3510 Val = DAG.getNode(ISD::BITCAST, DL, VA.getValVT(), Val); 3511 break; 3512 case CCValAssign::AExt: 3513 case CCValAssign::AExtUpper: 3514 Val = DAG.getNode(ISD::TRUNCATE, DL, VA.getValVT(), Val); 3515 break; 3516 case CCValAssign::ZExt: 3517 case CCValAssign::ZExtUpper: 3518 Val = DAG.getNode(ISD::AssertZext, DL, VA.getLocVT(), Val, 3519 DAG.getValueType(VA.getValVT())); 3520 Val = DAG.getNode(ISD::TRUNCATE, DL, VA.getValVT(), Val); 3521 break; 3522 case CCValAssign::SExt: 3523 case CCValAssign::SExtUpper: 3524 Val = DAG.getNode(ISD::AssertSext, DL, VA.getLocVT(), Val, 3525 DAG.getValueType(VA.getValVT())); 3526 Val = DAG.getNode(ISD::TRUNCATE, DL, VA.getValVT(), Val); 3527 break; 3528 } 3529 3530 InVals.push_back(Val); 3531 } 3532 3533 return Chain; 3534 } 3535 3536 static SDValue UnpackFromArgumentSlot(SDValue Val, const CCValAssign &VA, 3537 EVT ArgVT, const SDLoc &DL, 3538 SelectionDAG &DAG) { 3539 MVT LocVT = VA.getLocVT(); 3540 EVT ValVT = VA.getValVT(); 3541 3542 // Shift into the upper bits if necessary. 3543 switch (VA.getLocInfo()) { 3544 default: 3545 break; 3546 case CCValAssign::AExtUpper: 3547 case CCValAssign::SExtUpper: 3548 case CCValAssign::ZExtUpper: { 3549 unsigned ValSizeInBits = ArgVT.getSizeInBits(); 3550 unsigned LocSizeInBits = VA.getLocVT().getSizeInBits(); 3551 unsigned Opcode = 3552 VA.getLocInfo() == CCValAssign::ZExtUpper ? ISD::SRL : ISD::SRA; 3553 Val = DAG.getNode( 3554 Opcode, DL, VA.getLocVT(), Val, 3555 DAG.getConstant(LocSizeInBits - ValSizeInBits, DL, VA.getLocVT())); 3556 break; 3557 } 3558 } 3559 3560 // If this is an value smaller than the argument slot size (32-bit for O32, 3561 // 64-bit for N32/N64), it has been promoted in some way to the argument slot 3562 // size. Extract the value and insert any appropriate assertions regarding 3563 // sign/zero extension. 3564 switch (VA.getLocInfo()) { 3565 default: 3566 llvm_unreachable("Unknown loc info!"); 3567 case CCValAssign::Full: 3568 break; 3569 case CCValAssign::AExtUpper: 3570 case CCValAssign::AExt: 3571 Val = DAG.getNode(ISD::TRUNCATE, DL, ValVT, Val); 3572 break; 3573 case CCValAssign::SExtUpper: 3574 case CCValAssign::SExt: 3575 Val = DAG.getNode(ISD::AssertSext, DL, LocVT, Val, DAG.getValueType(ValVT)); 3576 Val = DAG.getNode(ISD::TRUNCATE, DL, ValVT, Val); 3577 break; 3578 case CCValAssign::ZExtUpper: 3579 case CCValAssign::ZExt: 3580 Val = DAG.getNode(ISD::AssertZext, DL, LocVT, Val, DAG.getValueType(ValVT)); 3581 Val = DAG.getNode(ISD::TRUNCATE, DL, ValVT, Val); 3582 break; 3583 case CCValAssign::BCvt: 3584 Val = DAG.getNode(ISD::BITCAST, DL, ValVT, Val); 3585 break; 3586 } 3587 3588 return Val; 3589 } 3590 3591 //===----------------------------------------------------------------------===// 3592 // Formal Arguments Calling Convention Implementation 3593 //===----------------------------------------------------------------------===// 3594 /// LowerFormalArguments - transform physical registers into virtual registers 3595 /// and generate load operations for arguments places on the stack. 3596 SDValue MipsTargetLowering::LowerFormalArguments( 3597 SDValue Chain, CallingConv::ID CallConv, bool IsVarArg, 3598 const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &DL, 3599 SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const { 3600 MachineFunction &MF = DAG.getMachineFunction(); 3601 MachineFrameInfo &MFI = MF.getFrameInfo(); 3602 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>(); 3603 3604 MipsFI->setVarArgsFrameIndex(0); 3605 3606 // Used with vargs to acumulate store chains. 3607 std::vector<SDValue> OutChains; 3608 3609 // Assign locations to all of the incoming arguments. 3610 SmallVector<CCValAssign, 16> ArgLocs; 3611 MipsCCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), ArgLocs, 3612 *DAG.getContext()); 3613 CCInfo.AllocateStack(ABI.GetCalleeAllocdArgSizeInBytes(CallConv), Align(1)); 3614 const Function &Func = DAG.getMachineFunction().getFunction(); 3615 Function::const_arg_iterator FuncArg = Func.arg_begin(); 3616 3617 if (Func.hasFnAttribute("interrupt") && !Func.arg_empty()) 3618 report_fatal_error( 3619 "Functions with the interrupt attribute cannot have arguments!"); 3620 3621 CCInfo.AnalyzeFormalArguments(Ins, CC_Mips_FixedArg); 3622 MipsFI->setFormalArgInfo(CCInfo.getNextStackOffset(), 3623 CCInfo.getInRegsParamsCount() > 0); 3624 3625 unsigned CurArgIdx = 0; 3626 CCInfo.rewindByValRegsInfo(); 3627 3628 for (unsigned i = 0, e = ArgLocs.size(), InsIdx = 0; i != e; ++i, ++InsIdx) { 3629 CCValAssign &VA = ArgLocs[i]; 3630 if (Ins[InsIdx].isOrigArg()) { 3631 std::advance(FuncArg, Ins[InsIdx].getOrigArgIndex() - CurArgIdx); 3632 CurArgIdx = Ins[InsIdx].getOrigArgIndex(); 3633 } 3634 EVT ValVT = VA.getValVT(); 3635 ISD::ArgFlagsTy Flags = Ins[InsIdx].Flags; 3636 bool IsRegLoc = VA.isRegLoc(); 3637 3638 if (Flags.isByVal()) { 3639 assert(Ins[InsIdx].isOrigArg() && "Byval arguments cannot be implicit"); 3640 unsigned FirstByValReg, LastByValReg; 3641 unsigned ByValIdx = CCInfo.getInRegsParamsProcessed(); 3642 CCInfo.getInRegsParamInfo(ByValIdx, FirstByValReg, LastByValReg); 3643 3644 assert(Flags.getByValSize() && 3645 "ByVal args of size 0 should have been ignored by front-end."); 3646 assert(ByValIdx < CCInfo.getInRegsParamsCount()); 3647 copyByValRegs(Chain, DL, OutChains, DAG, Flags, InVals, &*FuncArg, 3648 FirstByValReg, LastByValReg, VA, CCInfo); 3649 CCInfo.nextInRegsParam(); 3650 continue; 3651 } 3652 3653 // Arguments stored on registers 3654 if (IsRegLoc) { 3655 MVT RegVT = VA.getLocVT(); 3656 Register ArgReg = VA.getLocReg(); 3657 const TargetRegisterClass *RC = getRegClassFor(RegVT); 3658 3659 // Transform the arguments stored on 3660 // physical registers into virtual ones 3661 unsigned Reg = addLiveIn(DAG.getMachineFunction(), ArgReg, RC); 3662 SDValue ArgValue = DAG.getCopyFromReg(Chain, DL, Reg, RegVT); 3663 3664 ArgValue = 3665 UnpackFromArgumentSlot(ArgValue, VA, Ins[InsIdx].ArgVT, DL, DAG); 3666 3667 // Handle floating point arguments passed in integer registers and 3668 // long double arguments passed in floating point registers. 3669 if ((RegVT == MVT::i32 && ValVT == MVT::f32) || 3670 (RegVT == MVT::i64 && ValVT == MVT::f64) || 3671 (RegVT == MVT::f64 && ValVT == MVT::i64)) 3672 ArgValue = DAG.getNode(ISD::BITCAST, DL, ValVT, ArgValue); 3673 else if (ABI.IsO32() && RegVT == MVT::i32 && 3674 ValVT == MVT::f64) { 3675 assert(VA.needsCustom() && "Expected custom argument for f64 split"); 3676 CCValAssign &NextVA = ArgLocs[++i]; 3677 unsigned Reg2 = 3678 addLiveIn(DAG.getMachineFunction(), NextVA.getLocReg(), RC); 3679 SDValue ArgValue2 = DAG.getCopyFromReg(Chain, DL, Reg2, RegVT); 3680 if (!Subtarget.isLittle()) 3681 std::swap(ArgValue, ArgValue2); 3682 ArgValue = DAG.getNode(MipsISD::BuildPairF64, DL, MVT::f64, 3683 ArgValue, ArgValue2); 3684 } 3685 3686 InVals.push_back(ArgValue); 3687 } else { // VA.isRegLoc() 3688 MVT LocVT = VA.getLocVT(); 3689 3690 assert(!VA.needsCustom() && "unexpected custom memory argument"); 3691 3692 if (ABI.IsO32()) { 3693 // We ought to be able to use LocVT directly but O32 sets it to i32 3694 // when allocating floating point values to integer registers. 3695 // This shouldn't influence how we load the value into registers unless 3696 // we are targeting softfloat. 3697 if (VA.getValVT().isFloatingPoint() && !Subtarget.useSoftFloat()) 3698 LocVT = VA.getValVT(); 3699 } 3700 3701 // Only arguments pased on the stack should make it here. 3702 assert(VA.isMemLoc()); 3703 3704 // The stack pointer offset is relative to the caller stack frame. 3705 int FI = MFI.CreateFixedObject(LocVT.getSizeInBits() / 8, 3706 VA.getLocMemOffset(), true); 3707 3708 // Create load nodes to retrieve arguments from the stack 3709 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy(DAG.getDataLayout())); 3710 SDValue ArgValue = DAG.getLoad( 3711 LocVT, DL, Chain, FIN, 3712 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), FI)); 3713 OutChains.push_back(ArgValue.getValue(1)); 3714 3715 ArgValue = 3716 UnpackFromArgumentSlot(ArgValue, VA, Ins[InsIdx].ArgVT, DL, DAG); 3717 3718 InVals.push_back(ArgValue); 3719 } 3720 } 3721 3722 for (unsigned i = 0, e = ArgLocs.size(), InsIdx = 0; i != e; ++i, ++InsIdx) { 3723 3724 if (ArgLocs[i].needsCustom()) { 3725 ++i; 3726 continue; 3727 } 3728 3729 // The mips ABIs for returning structs by value requires that we copy 3730 // the sret argument into $v0 for the return. Save the argument into 3731 // a virtual register so that we can access it from the return points. 3732 if (Ins[InsIdx].Flags.isSRet()) { 3733 unsigned Reg = MipsFI->getSRetReturnReg(); 3734 if (!Reg) { 3735 Reg = MF.getRegInfo().createVirtualRegister( 3736 getRegClassFor(ABI.IsN64() ? MVT::i64 : MVT::i32)); 3737 MipsFI->setSRetReturnReg(Reg); 3738 } 3739 SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), DL, Reg, InVals[i]); 3740 Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, Copy, Chain); 3741 break; 3742 } 3743 } 3744 3745 if (IsVarArg) 3746 writeVarArgRegs(OutChains, Chain, DL, DAG, CCInfo); 3747 3748 // All stores are grouped in one node to allow the matching between 3749 // the size of Ins and InVals. This only happens when on varg functions 3750 if (!OutChains.empty()) { 3751 OutChains.push_back(Chain); 3752 Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, OutChains); 3753 } 3754 3755 return Chain; 3756 } 3757 3758 //===----------------------------------------------------------------------===// 3759 // Return Value Calling Convention Implementation 3760 //===----------------------------------------------------------------------===// 3761 3762 bool 3763 MipsTargetLowering::CanLowerReturn(CallingConv::ID CallConv, 3764 MachineFunction &MF, bool IsVarArg, 3765 const SmallVectorImpl<ISD::OutputArg> &Outs, 3766 LLVMContext &Context) const { 3767 SmallVector<CCValAssign, 16> RVLocs; 3768 MipsCCState CCInfo(CallConv, IsVarArg, MF, RVLocs, Context); 3769 return CCInfo.CheckReturn(Outs, RetCC_Mips); 3770 } 3771 3772 bool MipsTargetLowering::shouldSignExtendTypeInLibCall(EVT Type, 3773 bool IsSigned) const { 3774 if ((ABI.IsN32() || ABI.IsN64()) && Type == MVT::i32) 3775 return true; 3776 3777 return IsSigned; 3778 } 3779 3780 SDValue 3781 MipsTargetLowering::LowerInterruptReturn(SmallVectorImpl<SDValue> &RetOps, 3782 const SDLoc &DL, 3783 SelectionDAG &DAG) const { 3784 MachineFunction &MF = DAG.getMachineFunction(); 3785 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>(); 3786 3787 MipsFI->setISR(); 3788 3789 return DAG.getNode(MipsISD::ERet, DL, MVT::Other, RetOps); 3790 } 3791 3792 SDValue 3793 MipsTargetLowering::LowerReturn(SDValue Chain, CallingConv::ID CallConv, 3794 bool IsVarArg, 3795 const SmallVectorImpl<ISD::OutputArg> &Outs, 3796 const SmallVectorImpl<SDValue> &OutVals, 3797 const SDLoc &DL, SelectionDAG &DAG) const { 3798 // CCValAssign - represent the assignment of 3799 // the return value to a location 3800 SmallVector<CCValAssign, 16> RVLocs; 3801 MachineFunction &MF = DAG.getMachineFunction(); 3802 3803 // CCState - Info about the registers and stack slot. 3804 MipsCCState CCInfo(CallConv, IsVarArg, MF, RVLocs, *DAG.getContext()); 3805 3806 // Analyze return values. 3807 CCInfo.AnalyzeReturn(Outs, RetCC_Mips); 3808 3809 SDValue Flag; 3810 SmallVector<SDValue, 4> RetOps(1, Chain); 3811 3812 // Copy the result values into the output registers. 3813 for (unsigned i = 0; i != RVLocs.size(); ++i) { 3814 SDValue Val = OutVals[i]; 3815 CCValAssign &VA = RVLocs[i]; 3816 assert(VA.isRegLoc() && "Can only return in registers!"); 3817 bool UseUpperBits = false; 3818 3819 switch (VA.getLocInfo()) { 3820 default: 3821 llvm_unreachable("Unknown loc info!"); 3822 case CCValAssign::Full: 3823 break; 3824 case CCValAssign::BCvt: 3825 Val = DAG.getNode(ISD::BITCAST, DL, VA.getLocVT(), Val); 3826 break; 3827 case CCValAssign::AExtUpper: 3828 UseUpperBits = true; 3829 LLVM_FALLTHROUGH; 3830 case CCValAssign::AExt: 3831 Val = DAG.getNode(ISD::ANY_EXTEND, DL, VA.getLocVT(), Val); 3832 break; 3833 case CCValAssign::ZExtUpper: 3834 UseUpperBits = true; 3835 LLVM_FALLTHROUGH; 3836 case CCValAssign::ZExt: 3837 Val = DAG.getNode(ISD::ZERO_EXTEND, DL, VA.getLocVT(), Val); 3838 break; 3839 case CCValAssign::SExtUpper: 3840 UseUpperBits = true; 3841 LLVM_FALLTHROUGH; 3842 case CCValAssign::SExt: 3843 Val = DAG.getNode(ISD::SIGN_EXTEND, DL, VA.getLocVT(), Val); 3844 break; 3845 } 3846 3847 if (UseUpperBits) { 3848 unsigned ValSizeInBits = Outs[i].ArgVT.getSizeInBits(); 3849 unsigned LocSizeInBits = VA.getLocVT().getSizeInBits(); 3850 Val = DAG.getNode( 3851 ISD::SHL, DL, VA.getLocVT(), Val, 3852 DAG.getConstant(LocSizeInBits - ValSizeInBits, DL, VA.getLocVT())); 3853 } 3854 3855 Chain = DAG.getCopyToReg(Chain, DL, VA.getLocReg(), Val, Flag); 3856 3857 // Guarantee that all emitted copies are stuck together with flags. 3858 Flag = Chain.getValue(1); 3859 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT())); 3860 } 3861 3862 // The mips ABIs for returning structs by value requires that we copy 3863 // the sret argument into $v0 for the return. We saved the argument into 3864 // a virtual register in the entry block, so now we copy the value out 3865 // and into $v0. 3866 if (MF.getFunction().hasStructRetAttr()) { 3867 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>(); 3868 unsigned Reg = MipsFI->getSRetReturnReg(); 3869 3870 if (!Reg) 3871 llvm_unreachable("sret virtual register not created in the entry block"); 3872 SDValue Val = 3873 DAG.getCopyFromReg(Chain, DL, Reg, getPointerTy(DAG.getDataLayout())); 3874 unsigned V0 = ABI.IsN64() ? Mips::V0_64 : Mips::V0; 3875 3876 Chain = DAG.getCopyToReg(Chain, DL, V0, Val, Flag); 3877 Flag = Chain.getValue(1); 3878 RetOps.push_back(DAG.getRegister(V0, getPointerTy(DAG.getDataLayout()))); 3879 } 3880 3881 RetOps[0] = Chain; // Update chain. 3882 3883 // Add the flag if we have it. 3884 if (Flag.getNode()) 3885 RetOps.push_back(Flag); 3886 3887 // ISRs must use "eret". 3888 if (DAG.getMachineFunction().getFunction().hasFnAttribute("interrupt")) 3889 return LowerInterruptReturn(RetOps, DL, DAG); 3890 3891 // Standard return on Mips is a "jr $ra" 3892 return DAG.getNode(MipsISD::Ret, DL, MVT::Other, RetOps); 3893 } 3894 3895 //===----------------------------------------------------------------------===// 3896 // Mips Inline Assembly Support 3897 //===----------------------------------------------------------------------===// 3898 3899 /// getConstraintType - Given a constraint letter, return the type of 3900 /// constraint it is for this target. 3901 MipsTargetLowering::ConstraintType 3902 MipsTargetLowering::getConstraintType(StringRef Constraint) const { 3903 // Mips specific constraints 3904 // GCC config/mips/constraints.md 3905 // 3906 // 'd' : An address register. Equivalent to r 3907 // unless generating MIPS16 code. 3908 // 'y' : Equivalent to r; retained for 3909 // backwards compatibility. 3910 // 'c' : A register suitable for use in an indirect 3911 // jump. This will always be $25 for -mabicalls. 3912 // 'l' : The lo register. 1 word storage. 3913 // 'x' : The hilo register pair. Double word storage. 3914 if (Constraint.size() == 1) { 3915 switch (Constraint[0]) { 3916 default : break; 3917 case 'd': 3918 case 'y': 3919 case 'f': 3920 case 'c': 3921 case 'l': 3922 case 'x': 3923 return C_RegisterClass; 3924 case 'R': 3925 return C_Memory; 3926 } 3927 } 3928 3929 if (Constraint == "ZC") 3930 return C_Memory; 3931 3932 return TargetLowering::getConstraintType(Constraint); 3933 } 3934 3935 /// Examine constraint type and operand type and determine a weight value. 3936 /// This object must already have been set up with the operand type 3937 /// and the current alternative constraint selected. 3938 TargetLowering::ConstraintWeight 3939 MipsTargetLowering::getSingleConstraintMatchWeight( 3940 AsmOperandInfo &info, const char *constraint) const { 3941 ConstraintWeight weight = CW_Invalid; 3942 Value *CallOperandVal = info.CallOperandVal; 3943 // If we don't have a value, we can't do a match, 3944 // but allow it at the lowest weight. 3945 if (!CallOperandVal) 3946 return CW_Default; 3947 Type *type = CallOperandVal->getType(); 3948 // Look at the constraint type. 3949 switch (*constraint) { 3950 default: 3951 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint); 3952 break; 3953 case 'd': 3954 case 'y': 3955 if (type->isIntegerTy()) 3956 weight = CW_Register; 3957 break; 3958 case 'f': // FPU or MSA register 3959 if (Subtarget.hasMSA() && type->isVectorTy() && 3960 type->getPrimitiveSizeInBits().getFixedSize() == 128) 3961 weight = CW_Register; 3962 else if (type->isFloatTy()) 3963 weight = CW_Register; 3964 break; 3965 case 'c': // $25 for indirect jumps 3966 case 'l': // lo register 3967 case 'x': // hilo register pair 3968 if (type->isIntegerTy()) 3969 weight = CW_SpecificReg; 3970 break; 3971 case 'I': // signed 16 bit immediate 3972 case 'J': // integer zero 3973 case 'K': // unsigned 16 bit immediate 3974 case 'L': // signed 32 bit immediate where lower 16 bits are 0 3975 case 'N': // immediate in the range of -65535 to -1 (inclusive) 3976 case 'O': // signed 15 bit immediate (+- 16383) 3977 case 'P': // immediate in the range of 65535 to 1 (inclusive) 3978 if (isa<ConstantInt>(CallOperandVal)) 3979 weight = CW_Constant; 3980 break; 3981 case 'R': 3982 weight = CW_Memory; 3983 break; 3984 } 3985 return weight; 3986 } 3987 3988 /// This is a helper function to parse a physical register string and split it 3989 /// into non-numeric and numeric parts (Prefix and Reg). The first boolean flag 3990 /// that is returned indicates whether parsing was successful. The second flag 3991 /// is true if the numeric part exists. 3992 static std::pair<bool, bool> parsePhysicalReg(StringRef C, StringRef &Prefix, 3993 unsigned long long &Reg) { 3994 if (C.front() != '{' || C.back() != '}') 3995 return std::make_pair(false, false); 3996 3997 // Search for the first numeric character. 3998 StringRef::const_iterator I, B = C.begin() + 1, E = C.end() - 1; 3999 I = std::find_if(B, E, isdigit); 4000 4001 Prefix = StringRef(B, I - B); 4002 4003 // The second flag is set to false if no numeric characters were found. 4004 if (I == E) 4005 return std::make_pair(true, false); 4006 4007 // Parse the numeric characters. 4008 return std::make_pair(!getAsUnsignedInteger(StringRef(I, E - I), 10, Reg), 4009 true); 4010 } 4011 4012 EVT MipsTargetLowering::getTypeForExtReturn(LLVMContext &Context, EVT VT, 4013 ISD::NodeType) const { 4014 bool Cond = !Subtarget.isABI_O32() && VT.getSizeInBits() == 32; 4015 EVT MinVT = getRegisterType(Context, Cond ? MVT::i64 : MVT::i32); 4016 return VT.bitsLT(MinVT) ? MinVT : VT; 4017 } 4018 4019 std::pair<unsigned, const TargetRegisterClass *> MipsTargetLowering:: 4020 parseRegForInlineAsmConstraint(StringRef C, MVT VT) const { 4021 const TargetRegisterInfo *TRI = 4022 Subtarget.getRegisterInfo(); 4023 const TargetRegisterClass *RC; 4024 StringRef Prefix; 4025 unsigned long long Reg; 4026 4027 std::pair<bool, bool> R = parsePhysicalReg(C, Prefix, Reg); 4028 4029 if (!R.first) 4030 return std::make_pair(0U, nullptr); 4031 4032 if ((Prefix == "hi" || Prefix == "lo")) { // Parse hi/lo. 4033 // No numeric characters follow "hi" or "lo". 4034 if (R.second) 4035 return std::make_pair(0U, nullptr); 4036 4037 RC = TRI->getRegClass(Prefix == "hi" ? 4038 Mips::HI32RegClassID : Mips::LO32RegClassID); 4039 return std::make_pair(*(RC->begin()), RC); 4040 } else if (Prefix.startswith("$msa")) { 4041 // Parse $msa(ir|csr|access|save|modify|request|map|unmap) 4042 4043 // No numeric characters follow the name. 4044 if (R.second) 4045 return std::make_pair(0U, nullptr); 4046 4047 Reg = StringSwitch<unsigned long long>(Prefix) 4048 .Case("$msair", Mips::MSAIR) 4049 .Case("$msacsr", Mips::MSACSR) 4050 .Case("$msaaccess", Mips::MSAAccess) 4051 .Case("$msasave", Mips::MSASave) 4052 .Case("$msamodify", Mips::MSAModify) 4053 .Case("$msarequest", Mips::MSARequest) 4054 .Case("$msamap", Mips::MSAMap) 4055 .Case("$msaunmap", Mips::MSAUnmap) 4056 .Default(0); 4057 4058 if (!Reg) 4059 return std::make_pair(0U, nullptr); 4060 4061 RC = TRI->getRegClass(Mips::MSACtrlRegClassID); 4062 return std::make_pair(Reg, RC); 4063 } 4064 4065 if (!R.second) 4066 return std::make_pair(0U, nullptr); 4067 4068 if (Prefix == "$f") { // Parse $f0-$f31. 4069 // If the size of FP registers is 64-bit or Reg is an even number, select 4070 // the 64-bit register class. Otherwise, select the 32-bit register class. 4071 if (VT == MVT::Other) 4072 VT = (Subtarget.isFP64bit() || !(Reg % 2)) ? MVT::f64 : MVT::f32; 4073 4074 RC = getRegClassFor(VT); 4075 4076 if (RC == &Mips::AFGR64RegClass) { 4077 assert(Reg % 2 == 0); 4078 Reg >>= 1; 4079 } 4080 } else if (Prefix == "$fcc") // Parse $fcc0-$fcc7. 4081 RC = TRI->getRegClass(Mips::FCCRegClassID); 4082 else if (Prefix == "$w") { // Parse $w0-$w31. 4083 RC = getRegClassFor((VT == MVT::Other) ? MVT::v16i8 : VT); 4084 } else { // Parse $0-$31. 4085 assert(Prefix == "$"); 4086 RC = getRegClassFor((VT == MVT::Other) ? MVT::i32 : VT); 4087 } 4088 4089 assert(Reg < RC->getNumRegs()); 4090 return std::make_pair(*(RC->begin() + Reg), RC); 4091 } 4092 4093 /// Given a register class constraint, like 'r', if this corresponds directly 4094 /// to an LLVM register class, return a register of 0 and the register class 4095 /// pointer. 4096 std::pair<unsigned, const TargetRegisterClass *> 4097 MipsTargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, 4098 StringRef Constraint, 4099 MVT VT) const { 4100 if (Constraint.size() == 1) { 4101 switch (Constraint[0]) { 4102 case 'd': // Address register. Same as 'r' unless generating MIPS16 code. 4103 case 'y': // Same as 'r'. Exists for compatibility. 4104 case 'r': 4105 if (VT == MVT::i32 || VT == MVT::i16 || VT == MVT::i8 || VT == MVT::i1) { 4106 if (Subtarget.inMips16Mode()) 4107 return std::make_pair(0U, &Mips::CPU16RegsRegClass); 4108 return std::make_pair(0U, &Mips::GPR32RegClass); 4109 } 4110 if (VT == MVT::i64 && !Subtarget.isGP64bit()) 4111 return std::make_pair(0U, &Mips::GPR32RegClass); 4112 if (VT == MVT::i64 && Subtarget.isGP64bit()) 4113 return std::make_pair(0U, &Mips::GPR64RegClass); 4114 // This will generate an error message 4115 return std::make_pair(0U, nullptr); 4116 case 'f': // FPU or MSA register 4117 if (VT == MVT::v16i8) 4118 return std::make_pair(0U, &Mips::MSA128BRegClass); 4119 else if (VT == MVT::v8i16 || VT == MVT::v8f16) 4120 return std::make_pair(0U, &Mips::MSA128HRegClass); 4121 else if (VT == MVT::v4i32 || VT == MVT::v4f32) 4122 return std::make_pair(0U, &Mips::MSA128WRegClass); 4123 else if (VT == MVT::v2i64 || VT == MVT::v2f64) 4124 return std::make_pair(0U, &Mips::MSA128DRegClass); 4125 else if (VT == MVT::f32) 4126 return std::make_pair(0U, &Mips::FGR32RegClass); 4127 else if ((VT == MVT::f64) && (!Subtarget.isSingleFloat())) { 4128 if (Subtarget.isFP64bit()) 4129 return std::make_pair(0U, &Mips::FGR64RegClass); 4130 return std::make_pair(0U, &Mips::AFGR64RegClass); 4131 } 4132 break; 4133 case 'c': // register suitable for indirect jump 4134 if (VT == MVT::i32) 4135 return std::make_pair((unsigned)Mips::T9, &Mips::GPR32RegClass); 4136 if (VT == MVT::i64) 4137 return std::make_pair((unsigned)Mips::T9_64, &Mips::GPR64RegClass); 4138 // This will generate an error message 4139 return std::make_pair(0U, nullptr); 4140 case 'l': // use the `lo` register to store values 4141 // that are no bigger than a word 4142 if (VT == MVT::i32 || VT == MVT::i16 || VT == MVT::i8) 4143 return std::make_pair((unsigned)Mips::LO0, &Mips::LO32RegClass); 4144 return std::make_pair((unsigned)Mips::LO0_64, &Mips::LO64RegClass); 4145 case 'x': // use the concatenated `hi` and `lo` registers 4146 // to store doubleword values 4147 // Fixme: Not triggering the use of both hi and low 4148 // This will generate an error message 4149 return std::make_pair(0U, nullptr); 4150 } 4151 } 4152 4153 if (!Constraint.empty()) { 4154 std::pair<unsigned, const TargetRegisterClass *> R; 4155 R = parseRegForInlineAsmConstraint(Constraint, VT); 4156 4157 if (R.second) 4158 return R; 4159 } 4160 4161 return TargetLowering::getRegForInlineAsmConstraint(TRI, Constraint, VT); 4162 } 4163 4164 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops 4165 /// vector. If it is invalid, don't add anything to Ops. 4166 void MipsTargetLowering::LowerAsmOperandForConstraint(SDValue Op, 4167 std::string &Constraint, 4168 std::vector<SDValue>&Ops, 4169 SelectionDAG &DAG) const { 4170 SDLoc DL(Op); 4171 SDValue Result; 4172 4173 // Only support length 1 constraints for now. 4174 if (Constraint.length() > 1) return; 4175 4176 char ConstraintLetter = Constraint[0]; 4177 switch (ConstraintLetter) { 4178 default: break; // This will fall through to the generic implementation 4179 case 'I': // Signed 16 bit constant 4180 // If this fails, the parent routine will give an error 4181 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 4182 EVT Type = Op.getValueType(); 4183 int64_t Val = C->getSExtValue(); 4184 if (isInt<16>(Val)) { 4185 Result = DAG.getTargetConstant(Val, DL, Type); 4186 break; 4187 } 4188 } 4189 return; 4190 case 'J': // integer zero 4191 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 4192 EVT Type = Op.getValueType(); 4193 int64_t Val = C->getZExtValue(); 4194 if (Val == 0) { 4195 Result = DAG.getTargetConstant(0, DL, Type); 4196 break; 4197 } 4198 } 4199 return; 4200 case 'K': // unsigned 16 bit immediate 4201 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 4202 EVT Type = Op.getValueType(); 4203 uint64_t Val = (uint64_t)C->getZExtValue(); 4204 if (isUInt<16>(Val)) { 4205 Result = DAG.getTargetConstant(Val, DL, Type); 4206 break; 4207 } 4208 } 4209 return; 4210 case 'L': // signed 32 bit immediate where lower 16 bits are 0 4211 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 4212 EVT Type = Op.getValueType(); 4213 int64_t Val = C->getSExtValue(); 4214 if ((isInt<32>(Val)) && ((Val & 0xffff) == 0)){ 4215 Result = DAG.getTargetConstant(Val, DL, Type); 4216 break; 4217 } 4218 } 4219 return; 4220 case 'N': // immediate in the range of -65535 to -1 (inclusive) 4221 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 4222 EVT Type = Op.getValueType(); 4223 int64_t Val = C->getSExtValue(); 4224 if ((Val >= -65535) && (Val <= -1)) { 4225 Result = DAG.getTargetConstant(Val, DL, Type); 4226 break; 4227 } 4228 } 4229 return; 4230 case 'O': // signed 15 bit immediate 4231 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 4232 EVT Type = Op.getValueType(); 4233 int64_t Val = C->getSExtValue(); 4234 if ((isInt<15>(Val))) { 4235 Result = DAG.getTargetConstant(Val, DL, Type); 4236 break; 4237 } 4238 } 4239 return; 4240 case 'P': // immediate in the range of 1 to 65535 (inclusive) 4241 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 4242 EVT Type = Op.getValueType(); 4243 int64_t Val = C->getSExtValue(); 4244 if ((Val <= 65535) && (Val >= 1)) { 4245 Result = DAG.getTargetConstant(Val, DL, Type); 4246 break; 4247 } 4248 } 4249 return; 4250 } 4251 4252 if (Result.getNode()) { 4253 Ops.push_back(Result); 4254 return; 4255 } 4256 4257 TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG); 4258 } 4259 4260 bool MipsTargetLowering::isLegalAddressingMode(const DataLayout &DL, 4261 const AddrMode &AM, Type *Ty, 4262 unsigned AS, 4263 Instruction *I) const { 4264 // No global is ever allowed as a base. 4265 if (AM.BaseGV) 4266 return false; 4267 4268 switch (AM.Scale) { 4269 case 0: // "r+i" or just "i", depending on HasBaseReg. 4270 break; 4271 case 1: 4272 if (!AM.HasBaseReg) // allow "r+i". 4273 break; 4274 return false; // disallow "r+r" or "r+r+i". 4275 default: 4276 return false; 4277 } 4278 4279 return true; 4280 } 4281 4282 bool 4283 MipsTargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const { 4284 // The Mips target isn't yet aware of offsets. 4285 return false; 4286 } 4287 4288 EVT MipsTargetLowering::getOptimalMemOpType( 4289 const MemOp &Op, const AttributeList &FuncAttributes) const { 4290 if (Subtarget.hasMips64()) 4291 return MVT::i64; 4292 4293 return MVT::i32; 4294 } 4295 4296 bool MipsTargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT, 4297 bool ForCodeSize) const { 4298 if (VT != MVT::f32 && VT != MVT::f64) 4299 return false; 4300 if (Imm.isNegZero()) 4301 return false; 4302 return Imm.isZero(); 4303 } 4304 4305 unsigned MipsTargetLowering::getJumpTableEncoding() const { 4306 4307 // FIXME: For space reasons this should be: EK_GPRel32BlockAddress. 4308 if (ABI.IsN64() && isPositionIndependent()) 4309 return MachineJumpTableInfo::EK_GPRel64BlockAddress; 4310 4311 return TargetLowering::getJumpTableEncoding(); 4312 } 4313 4314 bool MipsTargetLowering::useSoftFloat() const { 4315 return Subtarget.useSoftFloat(); 4316 } 4317 4318 void MipsTargetLowering::copyByValRegs( 4319 SDValue Chain, const SDLoc &DL, std::vector<SDValue> &OutChains, 4320 SelectionDAG &DAG, const ISD::ArgFlagsTy &Flags, 4321 SmallVectorImpl<SDValue> &InVals, const Argument *FuncArg, 4322 unsigned FirstReg, unsigned LastReg, const CCValAssign &VA, 4323 MipsCCState &State) const { 4324 MachineFunction &MF = DAG.getMachineFunction(); 4325 MachineFrameInfo &MFI = MF.getFrameInfo(); 4326 unsigned GPRSizeInBytes = Subtarget.getGPRSizeInBytes(); 4327 unsigned NumRegs = LastReg - FirstReg; 4328 unsigned RegAreaSize = NumRegs * GPRSizeInBytes; 4329 unsigned FrameObjSize = std::max(Flags.getByValSize(), RegAreaSize); 4330 int FrameObjOffset; 4331 ArrayRef<MCPhysReg> ByValArgRegs = ABI.GetByValArgRegs(); 4332 4333 if (RegAreaSize) 4334 FrameObjOffset = 4335 (int)ABI.GetCalleeAllocdArgSizeInBytes(State.getCallingConv()) - 4336 (int)((ByValArgRegs.size() - FirstReg) * GPRSizeInBytes); 4337 else 4338 FrameObjOffset = VA.getLocMemOffset(); 4339 4340 // Create frame object. 4341 EVT PtrTy = getPointerTy(DAG.getDataLayout()); 4342 // Make the fixed object stored to mutable so that the load instructions 4343 // referencing it have their memory dependencies added. 4344 // Set the frame object as isAliased which clears the underlying objects 4345 // vector in ScheduleDAGInstrs::buildSchedGraph() resulting in addition of all 4346 // stores as dependencies for loads referencing this fixed object. 4347 int FI = MFI.CreateFixedObject(FrameObjSize, FrameObjOffset, false, true); 4348 SDValue FIN = DAG.getFrameIndex(FI, PtrTy); 4349 InVals.push_back(FIN); 4350 4351 if (!NumRegs) 4352 return; 4353 4354 // Copy arg registers. 4355 MVT RegTy = MVT::getIntegerVT(GPRSizeInBytes * 8); 4356 const TargetRegisterClass *RC = getRegClassFor(RegTy); 4357 4358 for (unsigned I = 0; I < NumRegs; ++I) { 4359 unsigned ArgReg = ByValArgRegs[FirstReg + I]; 4360 unsigned VReg = addLiveIn(MF, ArgReg, RC); 4361 unsigned Offset = I * GPRSizeInBytes; 4362 SDValue StorePtr = DAG.getNode(ISD::ADD, DL, PtrTy, FIN, 4363 DAG.getConstant(Offset, DL, PtrTy)); 4364 SDValue Store = DAG.getStore(Chain, DL, DAG.getRegister(VReg, RegTy), 4365 StorePtr, MachinePointerInfo(FuncArg, Offset)); 4366 OutChains.push_back(Store); 4367 } 4368 } 4369 4370 // Copy byVal arg to registers and stack. 4371 void MipsTargetLowering::passByValArg( 4372 SDValue Chain, const SDLoc &DL, 4373 std::deque<std::pair<unsigned, SDValue>> &RegsToPass, 4374 SmallVectorImpl<SDValue> &MemOpChains, SDValue StackPtr, 4375 MachineFrameInfo &MFI, SelectionDAG &DAG, SDValue Arg, unsigned FirstReg, 4376 unsigned LastReg, const ISD::ArgFlagsTy &Flags, bool isLittle, 4377 const CCValAssign &VA) const { 4378 unsigned ByValSizeInBytes = Flags.getByValSize(); 4379 unsigned OffsetInBytes = 0; // From beginning of struct 4380 unsigned RegSizeInBytes = Subtarget.getGPRSizeInBytes(); 4381 Align Alignment = 4382 std::min(Flags.getNonZeroByValAlign(), Align(RegSizeInBytes)); 4383 EVT PtrTy = getPointerTy(DAG.getDataLayout()), 4384 RegTy = MVT::getIntegerVT(RegSizeInBytes * 8); 4385 unsigned NumRegs = LastReg - FirstReg; 4386 4387 if (NumRegs) { 4388 ArrayRef<MCPhysReg> ArgRegs = ABI.GetByValArgRegs(); 4389 bool LeftoverBytes = (NumRegs * RegSizeInBytes > ByValSizeInBytes); 4390 unsigned I = 0; 4391 4392 // Copy words to registers. 4393 for (; I < NumRegs - LeftoverBytes; ++I, OffsetInBytes += RegSizeInBytes) { 4394 SDValue LoadPtr = DAG.getNode(ISD::ADD, DL, PtrTy, Arg, 4395 DAG.getConstant(OffsetInBytes, DL, PtrTy)); 4396 SDValue LoadVal = DAG.getLoad(RegTy, DL, Chain, LoadPtr, 4397 MachinePointerInfo(), Alignment); 4398 MemOpChains.push_back(LoadVal.getValue(1)); 4399 unsigned ArgReg = ArgRegs[FirstReg + I]; 4400 RegsToPass.push_back(std::make_pair(ArgReg, LoadVal)); 4401 } 4402 4403 // Return if the struct has been fully copied. 4404 if (ByValSizeInBytes == OffsetInBytes) 4405 return; 4406 4407 // Copy the remainder of the byval argument with sub-word loads and shifts. 4408 if (LeftoverBytes) { 4409 SDValue Val; 4410 4411 for (unsigned LoadSizeInBytes = RegSizeInBytes / 2, TotalBytesLoaded = 0; 4412 OffsetInBytes < ByValSizeInBytes; LoadSizeInBytes /= 2) { 4413 unsigned RemainingSizeInBytes = ByValSizeInBytes - OffsetInBytes; 4414 4415 if (RemainingSizeInBytes < LoadSizeInBytes) 4416 continue; 4417 4418 // Load subword. 4419 SDValue LoadPtr = DAG.getNode(ISD::ADD, DL, PtrTy, Arg, 4420 DAG.getConstant(OffsetInBytes, DL, 4421 PtrTy)); 4422 SDValue LoadVal = DAG.getExtLoad( 4423 ISD::ZEXTLOAD, DL, RegTy, Chain, LoadPtr, MachinePointerInfo(), 4424 MVT::getIntegerVT(LoadSizeInBytes * 8), Alignment); 4425 MemOpChains.push_back(LoadVal.getValue(1)); 4426 4427 // Shift the loaded value. 4428 unsigned Shamt; 4429 4430 if (isLittle) 4431 Shamt = TotalBytesLoaded * 8; 4432 else 4433 Shamt = (RegSizeInBytes - (TotalBytesLoaded + LoadSizeInBytes)) * 8; 4434 4435 SDValue Shift = DAG.getNode(ISD::SHL, DL, RegTy, LoadVal, 4436 DAG.getConstant(Shamt, DL, MVT::i32)); 4437 4438 if (Val.getNode()) 4439 Val = DAG.getNode(ISD::OR, DL, RegTy, Val, Shift); 4440 else 4441 Val = Shift; 4442 4443 OffsetInBytes += LoadSizeInBytes; 4444 TotalBytesLoaded += LoadSizeInBytes; 4445 Alignment = std::min(Alignment, Align(LoadSizeInBytes)); 4446 } 4447 4448 unsigned ArgReg = ArgRegs[FirstReg + I]; 4449 RegsToPass.push_back(std::make_pair(ArgReg, Val)); 4450 return; 4451 } 4452 } 4453 4454 // Copy remainder of byval arg to it with memcpy. 4455 unsigned MemCpySize = ByValSizeInBytes - OffsetInBytes; 4456 SDValue Src = DAG.getNode(ISD::ADD, DL, PtrTy, Arg, 4457 DAG.getConstant(OffsetInBytes, DL, PtrTy)); 4458 SDValue Dst = DAG.getNode(ISD::ADD, DL, PtrTy, StackPtr, 4459 DAG.getIntPtrConstant(VA.getLocMemOffset(), DL)); 4460 Chain = DAG.getMemcpy( 4461 Chain, DL, Dst, Src, DAG.getConstant(MemCpySize, DL, PtrTy), 4462 Align(Alignment), /*isVolatile=*/false, /*AlwaysInline=*/false, 4463 /*isTailCall=*/false, MachinePointerInfo(), MachinePointerInfo()); 4464 MemOpChains.push_back(Chain); 4465 } 4466 4467 void MipsTargetLowering::writeVarArgRegs(std::vector<SDValue> &OutChains, 4468 SDValue Chain, const SDLoc &DL, 4469 SelectionDAG &DAG, 4470 CCState &State) const { 4471 ArrayRef<MCPhysReg> ArgRegs = ABI.GetVarArgRegs(); 4472 unsigned Idx = State.getFirstUnallocated(ArgRegs); 4473 unsigned RegSizeInBytes = Subtarget.getGPRSizeInBytes(); 4474 MVT RegTy = MVT::getIntegerVT(RegSizeInBytes * 8); 4475 const TargetRegisterClass *RC = getRegClassFor(RegTy); 4476 MachineFunction &MF = DAG.getMachineFunction(); 4477 MachineFrameInfo &MFI = MF.getFrameInfo(); 4478 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>(); 4479 4480 // Offset of the first variable argument from stack pointer. 4481 int VaArgOffset; 4482 4483 if (ArgRegs.size() == Idx) 4484 VaArgOffset = alignTo(State.getNextStackOffset(), RegSizeInBytes); 4485 else { 4486 VaArgOffset = 4487 (int)ABI.GetCalleeAllocdArgSizeInBytes(State.getCallingConv()) - 4488 (int)(RegSizeInBytes * (ArgRegs.size() - Idx)); 4489 } 4490 4491 // Record the frame index of the first variable argument 4492 // which is a value necessary to VASTART. 4493 int FI = MFI.CreateFixedObject(RegSizeInBytes, VaArgOffset, true); 4494 MipsFI->setVarArgsFrameIndex(FI); 4495 4496 // Copy the integer registers that have not been used for argument passing 4497 // to the argument register save area. For O32, the save area is allocated 4498 // in the caller's stack frame, while for N32/64, it is allocated in the 4499 // callee's stack frame. 4500 for (unsigned I = Idx; I < ArgRegs.size(); 4501 ++I, VaArgOffset += RegSizeInBytes) { 4502 unsigned Reg = addLiveIn(MF, ArgRegs[I], RC); 4503 SDValue ArgValue = DAG.getCopyFromReg(Chain, DL, Reg, RegTy); 4504 FI = MFI.CreateFixedObject(RegSizeInBytes, VaArgOffset, true); 4505 SDValue PtrOff = DAG.getFrameIndex(FI, getPointerTy(DAG.getDataLayout())); 4506 SDValue Store = 4507 DAG.getStore(Chain, DL, ArgValue, PtrOff, MachinePointerInfo()); 4508 cast<StoreSDNode>(Store.getNode())->getMemOperand()->setValue( 4509 (Value *)nullptr); 4510 OutChains.push_back(Store); 4511 } 4512 } 4513 4514 void MipsTargetLowering::HandleByVal(CCState *State, unsigned &Size, 4515 Align Alignment) const { 4516 const TargetFrameLowering *TFL = Subtarget.getFrameLowering(); 4517 4518 assert(Size && "Byval argument's size shouldn't be 0."); 4519 4520 Alignment = std::min(Alignment, TFL->getStackAlign()); 4521 4522 unsigned FirstReg = 0; 4523 unsigned NumRegs = 0; 4524 4525 if (State->getCallingConv() != CallingConv::Fast) { 4526 unsigned RegSizeInBytes = Subtarget.getGPRSizeInBytes(); 4527 ArrayRef<MCPhysReg> IntArgRegs = ABI.GetByValArgRegs(); 4528 // FIXME: The O32 case actually describes no shadow registers. 4529 const MCPhysReg *ShadowRegs = 4530 ABI.IsO32() ? IntArgRegs.data() : Mips64DPRegs; 4531 4532 // We used to check the size as well but we can't do that anymore since 4533 // CCState::HandleByVal() rounds up the size after calling this function. 4534 assert( 4535 Alignment >= Align(RegSizeInBytes) && 4536 "Byval argument's alignment should be a multiple of RegSizeInBytes."); 4537 4538 FirstReg = State->getFirstUnallocated(IntArgRegs); 4539 4540 // If Alignment > RegSizeInBytes, the first arg register must be even. 4541 // FIXME: This condition happens to do the right thing but it's not the 4542 // right way to test it. We want to check that the stack frame offset 4543 // of the register is aligned. 4544 if ((Alignment > RegSizeInBytes) && (FirstReg % 2)) { 4545 State->AllocateReg(IntArgRegs[FirstReg], ShadowRegs[FirstReg]); 4546 ++FirstReg; 4547 } 4548 4549 // Mark the registers allocated. 4550 Size = alignTo(Size, RegSizeInBytes); 4551 for (unsigned I = FirstReg; Size > 0 && (I < IntArgRegs.size()); 4552 Size -= RegSizeInBytes, ++I, ++NumRegs) 4553 State->AllocateReg(IntArgRegs[I], ShadowRegs[I]); 4554 } 4555 4556 State->addInRegsParamInfo(FirstReg, FirstReg + NumRegs); 4557 } 4558 4559 MachineBasicBlock *MipsTargetLowering::emitPseudoSELECT(MachineInstr &MI, 4560 MachineBasicBlock *BB, 4561 bool isFPCmp, 4562 unsigned Opc) const { 4563 assert(!(Subtarget.hasMips4() || Subtarget.hasMips32()) && 4564 "Subtarget already supports SELECT nodes with the use of" 4565 "conditional-move instructions."); 4566 4567 const TargetInstrInfo *TII = 4568 Subtarget.getInstrInfo(); 4569 DebugLoc DL = MI.getDebugLoc(); 4570 4571 // To "insert" a SELECT instruction, we actually have to insert the 4572 // diamond control-flow pattern. The incoming instruction knows the 4573 // destination vreg to set, the condition code register to branch on, the 4574 // true/false values to select between, and a branch opcode to use. 4575 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 4576 MachineFunction::iterator It = ++BB->getIterator(); 4577 4578 // thisMBB: 4579 // ... 4580 // TrueVal = ... 4581 // setcc r1, r2, r3 4582 // bNE r1, r0, copy1MBB 4583 // fallthrough --> copy0MBB 4584 MachineBasicBlock *thisMBB = BB; 4585 MachineFunction *F = BB->getParent(); 4586 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB); 4587 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB); 4588 F->insert(It, copy0MBB); 4589 F->insert(It, sinkMBB); 4590 4591 // Transfer the remainder of BB and its successor edges to sinkMBB. 4592 sinkMBB->splice(sinkMBB->begin(), BB, 4593 std::next(MachineBasicBlock::iterator(MI)), BB->end()); 4594 sinkMBB->transferSuccessorsAndUpdatePHIs(BB); 4595 4596 // Next, add the true and fallthrough blocks as its successors. 4597 BB->addSuccessor(copy0MBB); 4598 BB->addSuccessor(sinkMBB); 4599 4600 if (isFPCmp) { 4601 // bc1[tf] cc, sinkMBB 4602 BuildMI(BB, DL, TII->get(Opc)) 4603 .addReg(MI.getOperand(1).getReg()) 4604 .addMBB(sinkMBB); 4605 } else { 4606 // bne rs, $0, sinkMBB 4607 BuildMI(BB, DL, TII->get(Opc)) 4608 .addReg(MI.getOperand(1).getReg()) 4609 .addReg(Mips::ZERO) 4610 .addMBB(sinkMBB); 4611 } 4612 4613 // copy0MBB: 4614 // %FalseValue = ... 4615 // # fallthrough to sinkMBB 4616 BB = copy0MBB; 4617 4618 // Update machine-CFG edges 4619 BB->addSuccessor(sinkMBB); 4620 4621 // sinkMBB: 4622 // %Result = phi [ %TrueValue, thisMBB ], [ %FalseValue, copy0MBB ] 4623 // ... 4624 BB = sinkMBB; 4625 4626 BuildMI(*BB, BB->begin(), DL, TII->get(Mips::PHI), MI.getOperand(0).getReg()) 4627 .addReg(MI.getOperand(2).getReg()) 4628 .addMBB(thisMBB) 4629 .addReg(MI.getOperand(3).getReg()) 4630 .addMBB(copy0MBB); 4631 4632 MI.eraseFromParent(); // The pseudo instruction is gone now. 4633 4634 return BB; 4635 } 4636 4637 MachineBasicBlock * 4638 MipsTargetLowering::emitPseudoD_SELECT(MachineInstr &MI, 4639 MachineBasicBlock *BB) const { 4640 assert(!(Subtarget.hasMips4() || Subtarget.hasMips32()) && 4641 "Subtarget already supports SELECT nodes with the use of" 4642 "conditional-move instructions."); 4643 4644 const TargetInstrInfo *TII = Subtarget.getInstrInfo(); 4645 DebugLoc DL = MI.getDebugLoc(); 4646 4647 // D_SELECT substitutes two SELECT nodes that goes one after another and 4648 // have the same condition operand. On machines which don't have 4649 // conditional-move instruction, it reduces unnecessary branch instructions 4650 // which are result of using two diamond patterns that are result of two 4651 // SELECT pseudo instructions. 4652 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 4653 MachineFunction::iterator It = ++BB->getIterator(); 4654 4655 // thisMBB: 4656 // ... 4657 // TrueVal = ... 4658 // setcc r1, r2, r3 4659 // bNE r1, r0, copy1MBB 4660 // fallthrough --> copy0MBB 4661 MachineBasicBlock *thisMBB = BB; 4662 MachineFunction *F = BB->getParent(); 4663 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB); 4664 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB); 4665 F->insert(It, copy0MBB); 4666 F->insert(It, sinkMBB); 4667 4668 // Transfer the remainder of BB and its successor edges to sinkMBB. 4669 sinkMBB->splice(sinkMBB->begin(), BB, 4670 std::next(MachineBasicBlock::iterator(MI)), BB->end()); 4671 sinkMBB->transferSuccessorsAndUpdatePHIs(BB); 4672 4673 // Next, add the true and fallthrough blocks as its successors. 4674 BB->addSuccessor(copy0MBB); 4675 BB->addSuccessor(sinkMBB); 4676 4677 // bne rs, $0, sinkMBB 4678 BuildMI(BB, DL, TII->get(Mips::BNE)) 4679 .addReg(MI.getOperand(2).getReg()) 4680 .addReg(Mips::ZERO) 4681 .addMBB(sinkMBB); 4682 4683 // copy0MBB: 4684 // %FalseValue = ... 4685 // # fallthrough to sinkMBB 4686 BB = copy0MBB; 4687 4688 // Update machine-CFG edges 4689 BB->addSuccessor(sinkMBB); 4690 4691 // sinkMBB: 4692 // %Result = phi [ %TrueValue, thisMBB ], [ %FalseValue, copy0MBB ] 4693 // ... 4694 BB = sinkMBB; 4695 4696 // Use two PHI nodes to select two reults 4697 BuildMI(*BB, BB->begin(), DL, TII->get(Mips::PHI), MI.getOperand(0).getReg()) 4698 .addReg(MI.getOperand(3).getReg()) 4699 .addMBB(thisMBB) 4700 .addReg(MI.getOperand(5).getReg()) 4701 .addMBB(copy0MBB); 4702 BuildMI(*BB, BB->begin(), DL, TII->get(Mips::PHI), MI.getOperand(1).getReg()) 4703 .addReg(MI.getOperand(4).getReg()) 4704 .addMBB(thisMBB) 4705 .addReg(MI.getOperand(6).getReg()) 4706 .addMBB(copy0MBB); 4707 4708 MI.eraseFromParent(); // The pseudo instruction is gone now. 4709 4710 return BB; 4711 } 4712 4713 // FIXME? Maybe this could be a TableGen attribute on some registers and 4714 // this table could be generated automatically from RegInfo. 4715 Register 4716 MipsTargetLowering::getRegisterByName(const char *RegName, LLT VT, 4717 const MachineFunction &MF) const { 4718 // The Linux kernel uses $28 and sp. 4719 if (Subtarget.isGP64bit()) { 4720 Register Reg = StringSwitch<Register>(RegName) 4721 .Case("$28", Mips::GP_64) 4722 .Case("sp", Mips::SP_64) 4723 .Default(Register()); 4724 if (Reg) 4725 return Reg; 4726 } else { 4727 Register Reg = StringSwitch<Register>(RegName) 4728 .Case("$28", Mips::GP) 4729 .Case("sp", Mips::SP) 4730 .Default(Register()); 4731 if (Reg) 4732 return Reg; 4733 } 4734 report_fatal_error("Invalid register name global variable"); 4735 } 4736 4737 MachineBasicBlock *MipsTargetLowering::emitLDR_W(MachineInstr &MI, 4738 MachineBasicBlock *BB) const { 4739 MachineFunction *MF = BB->getParent(); 4740 MachineRegisterInfo &MRI = MF->getRegInfo(); 4741 const TargetInstrInfo *TII = Subtarget.getInstrInfo(); 4742 const bool IsLittle = Subtarget.isLittle(); 4743 DebugLoc DL = MI.getDebugLoc(); 4744 4745 Register Dest = MI.getOperand(0).getReg(); 4746 Register Address = MI.getOperand(1).getReg(); 4747 unsigned Imm = MI.getOperand(2).getImm(); 4748 4749 MachineBasicBlock::iterator I(MI); 4750 4751 if (Subtarget.hasMips32r6() || Subtarget.hasMips64r6()) { 4752 // Mips release 6 can load from adress that is not naturally-aligned. 4753 Register Temp = MRI.createVirtualRegister(&Mips::GPR32RegClass); 4754 BuildMI(*BB, I, DL, TII->get(Mips::LW)) 4755 .addDef(Temp) 4756 .addUse(Address) 4757 .addImm(Imm); 4758 BuildMI(*BB, I, DL, TII->get(Mips::FILL_W)).addDef(Dest).addUse(Temp); 4759 } else { 4760 // Mips release 5 needs to use instructions that can load from an unaligned 4761 // memory address. 4762 Register LoadHalf = MRI.createVirtualRegister(&Mips::GPR32RegClass); 4763 Register LoadFull = MRI.createVirtualRegister(&Mips::GPR32RegClass); 4764 Register Undef = MRI.createVirtualRegister(&Mips::GPR32RegClass); 4765 BuildMI(*BB, I, DL, TII->get(Mips::IMPLICIT_DEF)).addDef(Undef); 4766 BuildMI(*BB, I, DL, TII->get(Mips::LWR)) 4767 .addDef(LoadHalf) 4768 .addUse(Address) 4769 .addImm(Imm + (IsLittle ? 0 : 3)) 4770 .addUse(Undef); 4771 BuildMI(*BB, I, DL, TII->get(Mips::LWL)) 4772 .addDef(LoadFull) 4773 .addUse(Address) 4774 .addImm(Imm + (IsLittle ? 3 : 0)) 4775 .addUse(LoadHalf); 4776 BuildMI(*BB, I, DL, TII->get(Mips::FILL_W)).addDef(Dest).addUse(LoadFull); 4777 } 4778 4779 MI.eraseFromParent(); 4780 return BB; 4781 } 4782 4783 MachineBasicBlock *MipsTargetLowering::emitLDR_D(MachineInstr &MI, 4784 MachineBasicBlock *BB) const { 4785 MachineFunction *MF = BB->getParent(); 4786 MachineRegisterInfo &MRI = MF->getRegInfo(); 4787 const TargetInstrInfo *TII = Subtarget.getInstrInfo(); 4788 const bool IsLittle = Subtarget.isLittle(); 4789 DebugLoc DL = MI.getDebugLoc(); 4790 4791 Register Dest = MI.getOperand(0).getReg(); 4792 Register Address = MI.getOperand(1).getReg(); 4793 unsigned Imm = MI.getOperand(2).getImm(); 4794 4795 MachineBasicBlock::iterator I(MI); 4796 4797 if (Subtarget.hasMips32r6() || Subtarget.hasMips64r6()) { 4798 // Mips release 6 can load from adress that is not naturally-aligned. 4799 if (Subtarget.isGP64bit()) { 4800 Register Temp = MRI.createVirtualRegister(&Mips::GPR64RegClass); 4801 BuildMI(*BB, I, DL, TII->get(Mips::LD)) 4802 .addDef(Temp) 4803 .addUse(Address) 4804 .addImm(Imm); 4805 BuildMI(*BB, I, DL, TII->get(Mips::FILL_D)).addDef(Dest).addUse(Temp); 4806 } else { 4807 Register Wtemp = MRI.createVirtualRegister(&Mips::MSA128WRegClass); 4808 Register Lo = MRI.createVirtualRegister(&Mips::GPR32RegClass); 4809 Register Hi = MRI.createVirtualRegister(&Mips::GPR32RegClass); 4810 BuildMI(*BB, I, DL, TII->get(Mips::LW)) 4811 .addDef(Lo) 4812 .addUse(Address) 4813 .addImm(Imm + (IsLittle ? 0 : 4)); 4814 BuildMI(*BB, I, DL, TII->get(Mips::LW)) 4815 .addDef(Hi) 4816 .addUse(Address) 4817 .addImm(Imm + (IsLittle ? 4 : 0)); 4818 BuildMI(*BB, I, DL, TII->get(Mips::FILL_W)).addDef(Wtemp).addUse(Lo); 4819 BuildMI(*BB, I, DL, TII->get(Mips::INSERT_W), Dest) 4820 .addUse(Wtemp) 4821 .addUse(Hi) 4822 .addImm(1); 4823 } 4824 } else { 4825 // Mips release 5 needs to use instructions that can load from an unaligned 4826 // memory address. 4827 Register LoHalf = MRI.createVirtualRegister(&Mips::GPR32RegClass); 4828 Register LoFull = MRI.createVirtualRegister(&Mips::GPR32RegClass); 4829 Register LoUndef = MRI.createVirtualRegister(&Mips::GPR32RegClass); 4830 Register HiHalf = MRI.createVirtualRegister(&Mips::GPR32RegClass); 4831 Register HiFull = MRI.createVirtualRegister(&Mips::GPR32RegClass); 4832 Register HiUndef = MRI.createVirtualRegister(&Mips::GPR32RegClass); 4833 Register Wtemp = MRI.createVirtualRegister(&Mips::MSA128WRegClass); 4834 BuildMI(*BB, I, DL, TII->get(Mips::IMPLICIT_DEF)).addDef(LoUndef); 4835 BuildMI(*BB, I, DL, TII->get(Mips::LWR)) 4836 .addDef(LoHalf) 4837 .addUse(Address) 4838 .addImm(Imm + (IsLittle ? 0 : 7)) 4839 .addUse(LoUndef); 4840 BuildMI(*BB, I, DL, TII->get(Mips::LWL)) 4841 .addDef(LoFull) 4842 .addUse(Address) 4843 .addImm(Imm + (IsLittle ? 3 : 4)) 4844 .addUse(LoHalf); 4845 BuildMI(*BB, I, DL, TII->get(Mips::IMPLICIT_DEF)).addDef(HiUndef); 4846 BuildMI(*BB, I, DL, TII->get(Mips::LWR)) 4847 .addDef(HiHalf) 4848 .addUse(Address) 4849 .addImm(Imm + (IsLittle ? 4 : 3)) 4850 .addUse(HiUndef); 4851 BuildMI(*BB, I, DL, TII->get(Mips::LWL)) 4852 .addDef(HiFull) 4853 .addUse(Address) 4854 .addImm(Imm + (IsLittle ? 7 : 0)) 4855 .addUse(HiHalf); 4856 BuildMI(*BB, I, DL, TII->get(Mips::FILL_W)).addDef(Wtemp).addUse(LoFull); 4857 BuildMI(*BB, I, DL, TII->get(Mips::INSERT_W), Dest) 4858 .addUse(Wtemp) 4859 .addUse(HiFull) 4860 .addImm(1); 4861 } 4862 4863 MI.eraseFromParent(); 4864 return BB; 4865 } 4866 4867 MachineBasicBlock *MipsTargetLowering::emitSTR_W(MachineInstr &MI, 4868 MachineBasicBlock *BB) const { 4869 MachineFunction *MF = BB->getParent(); 4870 MachineRegisterInfo &MRI = MF->getRegInfo(); 4871 const TargetInstrInfo *TII = Subtarget.getInstrInfo(); 4872 const bool IsLittle = Subtarget.isLittle(); 4873 DebugLoc DL = MI.getDebugLoc(); 4874 4875 Register StoreVal = MI.getOperand(0).getReg(); 4876 Register Address = MI.getOperand(1).getReg(); 4877 unsigned Imm = MI.getOperand(2).getImm(); 4878 4879 MachineBasicBlock::iterator I(MI); 4880 4881 if (Subtarget.hasMips32r6() || Subtarget.hasMips64r6()) { 4882 // Mips release 6 can store to adress that is not naturally-aligned. 4883 Register BitcastW = MRI.createVirtualRegister(&Mips::MSA128WRegClass); 4884 Register Tmp = MRI.createVirtualRegister(&Mips::GPR32RegClass); 4885 BuildMI(*BB, I, DL, TII->get(Mips::COPY)).addDef(BitcastW).addUse(StoreVal); 4886 BuildMI(*BB, I, DL, TII->get(Mips::COPY_S_W)) 4887 .addDef(Tmp) 4888 .addUse(BitcastW) 4889 .addImm(0); 4890 BuildMI(*BB, I, DL, TII->get(Mips::SW)) 4891 .addUse(Tmp) 4892 .addUse(Address) 4893 .addImm(Imm); 4894 } else { 4895 // Mips release 5 needs to use instructions that can store to an unaligned 4896 // memory address. 4897 Register Tmp = MRI.createVirtualRegister(&Mips::GPR32RegClass); 4898 BuildMI(*BB, I, DL, TII->get(Mips::COPY_S_W)) 4899 .addDef(Tmp) 4900 .addUse(StoreVal) 4901 .addImm(0); 4902 BuildMI(*BB, I, DL, TII->get(Mips::SWR)) 4903 .addUse(Tmp) 4904 .addUse(Address) 4905 .addImm(Imm + (IsLittle ? 0 : 3)); 4906 BuildMI(*BB, I, DL, TII->get(Mips::SWL)) 4907 .addUse(Tmp) 4908 .addUse(Address) 4909 .addImm(Imm + (IsLittle ? 3 : 0)); 4910 } 4911 4912 MI.eraseFromParent(); 4913 4914 return BB; 4915 } 4916 4917 MachineBasicBlock *MipsTargetLowering::emitSTR_D(MachineInstr &MI, 4918 MachineBasicBlock *BB) const { 4919 MachineFunction *MF = BB->getParent(); 4920 MachineRegisterInfo &MRI = MF->getRegInfo(); 4921 const TargetInstrInfo *TII = Subtarget.getInstrInfo(); 4922 const bool IsLittle = Subtarget.isLittle(); 4923 DebugLoc DL = MI.getDebugLoc(); 4924 4925 Register StoreVal = MI.getOperand(0).getReg(); 4926 Register Address = MI.getOperand(1).getReg(); 4927 unsigned Imm = MI.getOperand(2).getImm(); 4928 4929 MachineBasicBlock::iterator I(MI); 4930 4931 if (Subtarget.hasMips32r6() || Subtarget.hasMips64r6()) { 4932 // Mips release 6 can store to adress that is not naturally-aligned. 4933 if (Subtarget.isGP64bit()) { 4934 Register BitcastD = MRI.createVirtualRegister(&Mips::MSA128DRegClass); 4935 Register Lo = MRI.createVirtualRegister(&Mips::GPR64RegClass); 4936 BuildMI(*BB, I, DL, TII->get(Mips::COPY)) 4937 .addDef(BitcastD) 4938 .addUse(StoreVal); 4939 BuildMI(*BB, I, DL, TII->get(Mips::COPY_S_D)) 4940 .addDef(Lo) 4941 .addUse(BitcastD) 4942 .addImm(0); 4943 BuildMI(*BB, I, DL, TII->get(Mips::SD)) 4944 .addUse(Lo) 4945 .addUse(Address) 4946 .addImm(Imm); 4947 } else { 4948 Register BitcastW = MRI.createVirtualRegister(&Mips::MSA128WRegClass); 4949 Register Lo = MRI.createVirtualRegister(&Mips::GPR32RegClass); 4950 Register Hi = MRI.createVirtualRegister(&Mips::GPR32RegClass); 4951 BuildMI(*BB, I, DL, TII->get(Mips::COPY)) 4952 .addDef(BitcastW) 4953 .addUse(StoreVal); 4954 BuildMI(*BB, I, DL, TII->get(Mips::COPY_S_W)) 4955 .addDef(Lo) 4956 .addUse(BitcastW) 4957 .addImm(0); 4958 BuildMI(*BB, I, DL, TII->get(Mips::COPY_S_W)) 4959 .addDef(Hi) 4960 .addUse(BitcastW) 4961 .addImm(1); 4962 BuildMI(*BB, I, DL, TII->get(Mips::SW)) 4963 .addUse(Lo) 4964 .addUse(Address) 4965 .addImm(Imm + (IsLittle ? 0 : 4)); 4966 BuildMI(*BB, I, DL, TII->get(Mips::SW)) 4967 .addUse(Hi) 4968 .addUse(Address) 4969 .addImm(Imm + (IsLittle ? 4 : 0)); 4970 } 4971 } else { 4972 // Mips release 5 needs to use instructions that can store to an unaligned 4973 // memory address. 4974 Register Bitcast = MRI.createVirtualRegister(&Mips::MSA128WRegClass); 4975 Register Lo = MRI.createVirtualRegister(&Mips::GPR32RegClass); 4976 Register Hi = MRI.createVirtualRegister(&Mips::GPR32RegClass); 4977 BuildMI(*BB, I, DL, TII->get(Mips::COPY)).addDef(Bitcast).addUse(StoreVal); 4978 BuildMI(*BB, I, DL, TII->get(Mips::COPY_S_W)) 4979 .addDef(Lo) 4980 .addUse(Bitcast) 4981 .addImm(0); 4982 BuildMI(*BB, I, DL, TII->get(Mips::COPY_S_W)) 4983 .addDef(Hi) 4984 .addUse(Bitcast) 4985 .addImm(1); 4986 BuildMI(*BB, I, DL, TII->get(Mips::SWR)) 4987 .addUse(Lo) 4988 .addUse(Address) 4989 .addImm(Imm + (IsLittle ? 0 : 3)); 4990 BuildMI(*BB, I, DL, TII->get(Mips::SWL)) 4991 .addUse(Lo) 4992 .addUse(Address) 4993 .addImm(Imm + (IsLittle ? 3 : 0)); 4994 BuildMI(*BB, I, DL, TII->get(Mips::SWR)) 4995 .addUse(Hi) 4996 .addUse(Address) 4997 .addImm(Imm + (IsLittle ? 4 : 7)); 4998 BuildMI(*BB, I, DL, TII->get(Mips::SWL)) 4999 .addUse(Hi) 5000 .addUse(Address) 5001 .addImm(Imm + (IsLittle ? 7 : 4)); 5002 } 5003 5004 MI.eraseFromParent(); 5005 return BB; 5006 } 5007