1 //===- MipsISelLowering.cpp - Mips DAG Lowering Implementation ------------===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // This file defines the interfaces that Mips uses to lower LLVM code into a 10 // selection DAG. 11 // 12 //===----------------------------------------------------------------------===// 13 14 #include "MipsISelLowering.h" 15 #include "MCTargetDesc/MipsBaseInfo.h" 16 #include "MCTargetDesc/MipsInstPrinter.h" 17 #include "MCTargetDesc/MipsMCTargetDesc.h" 18 #include "MipsCCState.h" 19 #include "MipsInstrInfo.h" 20 #include "MipsMachineFunction.h" 21 #include "MipsRegisterInfo.h" 22 #include "MipsSubtarget.h" 23 #include "MipsTargetMachine.h" 24 #include "MipsTargetObjectFile.h" 25 #include "llvm/ADT/APFloat.h" 26 #include "llvm/ADT/ArrayRef.h" 27 #include "llvm/ADT/SmallVector.h" 28 #include "llvm/ADT/Statistic.h" 29 #include "llvm/ADT/StringRef.h" 30 #include "llvm/ADT/StringSwitch.h" 31 #include "llvm/CodeGen/CallingConvLower.h" 32 #include "llvm/CodeGen/FunctionLoweringInfo.h" 33 #include "llvm/CodeGen/ISDOpcodes.h" 34 #include "llvm/CodeGen/MachineBasicBlock.h" 35 #include "llvm/CodeGen/MachineFrameInfo.h" 36 #include "llvm/CodeGen/MachineFunction.h" 37 #include "llvm/CodeGen/MachineInstr.h" 38 #include "llvm/CodeGen/MachineInstrBuilder.h" 39 #include "llvm/CodeGen/MachineJumpTableInfo.h" 40 #include "llvm/CodeGen/MachineMemOperand.h" 41 #include "llvm/CodeGen/MachineOperand.h" 42 #include "llvm/CodeGen/MachineRegisterInfo.h" 43 #include "llvm/CodeGen/RuntimeLibcalls.h" 44 #include "llvm/CodeGen/SelectionDAG.h" 45 #include "llvm/CodeGen/SelectionDAGNodes.h" 46 #include "llvm/CodeGen/TargetFrameLowering.h" 47 #include "llvm/CodeGen/TargetInstrInfo.h" 48 #include "llvm/CodeGen/TargetRegisterInfo.h" 49 #include "llvm/CodeGen/ValueTypes.h" 50 #include "llvm/IR/CallingConv.h" 51 #include "llvm/IR/Constants.h" 52 #include "llvm/IR/DataLayout.h" 53 #include "llvm/IR/DebugLoc.h" 54 #include "llvm/IR/DerivedTypes.h" 55 #include "llvm/IR/Function.h" 56 #include "llvm/IR/GlobalValue.h" 57 #include "llvm/IR/Type.h" 58 #include "llvm/IR/Value.h" 59 #include "llvm/MC/MCContext.h" 60 #include "llvm/MC/MCRegisterInfo.h" 61 #include "llvm/Support/Casting.h" 62 #include "llvm/Support/CodeGen.h" 63 #include "llvm/Support/CommandLine.h" 64 #include "llvm/Support/Compiler.h" 65 #include "llvm/Support/ErrorHandling.h" 66 #include "llvm/Support/MachineValueType.h" 67 #include "llvm/Support/MathExtras.h" 68 #include "llvm/Target/TargetMachine.h" 69 #include "llvm/Target/TargetOptions.h" 70 #include <algorithm> 71 #include <cassert> 72 #include <cctype> 73 #include <cstdint> 74 #include <deque> 75 #include <iterator> 76 #include <utility> 77 #include <vector> 78 79 using namespace llvm; 80 81 #define DEBUG_TYPE "mips-lower" 82 83 STATISTIC(NumTailCalls, "Number of tail calls"); 84 85 static cl::opt<bool> 86 NoZeroDivCheck("mno-check-zero-division", cl::Hidden, 87 cl::desc("MIPS: Don't trap on integer division by zero."), 88 cl::init(false)); 89 90 extern cl::opt<bool> EmitJalrReloc; 91 92 static const MCPhysReg Mips64DPRegs[8] = { 93 Mips::D12_64, Mips::D13_64, Mips::D14_64, Mips::D15_64, 94 Mips::D16_64, Mips::D17_64, Mips::D18_64, Mips::D19_64 95 }; 96 97 // The MIPS MSA ABI passes vector arguments in the integer register set. 98 // The number of integer registers used is dependant on the ABI used. 99 MVT MipsTargetLowering::getRegisterTypeForCallingConv(LLVMContext &Context, 100 CallingConv::ID CC, 101 EVT VT) const { 102 if (!VT.isVector()) 103 return getRegisterType(Context, VT); 104 105 return Subtarget.isABI_O32() || VT.getSizeInBits() == 32 ? MVT::i32 106 : MVT::i64; 107 } 108 109 unsigned MipsTargetLowering::getNumRegistersForCallingConv(LLVMContext &Context, 110 CallingConv::ID CC, 111 EVT VT) const { 112 if (VT.isVector()) 113 return divideCeil(VT.getSizeInBits(), Subtarget.isABI_O32() ? 32 : 64); 114 return MipsTargetLowering::getNumRegisters(Context, VT); 115 } 116 117 unsigned MipsTargetLowering::getVectorTypeBreakdownForCallingConv( 118 LLVMContext &Context, CallingConv::ID CC, EVT VT, EVT &IntermediateVT, 119 unsigned &NumIntermediates, MVT &RegisterVT) const { 120 // Break down vector types to either 2 i64s or 4 i32s. 121 RegisterVT = getRegisterTypeForCallingConv(Context, CC, VT); 122 IntermediateVT = RegisterVT; 123 NumIntermediates = 124 VT.getFixedSizeInBits() < RegisterVT.getFixedSizeInBits() 125 ? VT.getVectorNumElements() 126 : divideCeil(VT.getSizeInBits(), RegisterVT.getSizeInBits()); 127 return NumIntermediates; 128 } 129 130 SDValue MipsTargetLowering::getGlobalReg(SelectionDAG &DAG, EVT Ty) const { 131 MachineFunction &MF = DAG.getMachineFunction(); 132 MipsFunctionInfo *FI = MF.getInfo<MipsFunctionInfo>(); 133 return DAG.getRegister(FI->getGlobalBaseReg(MF), Ty); 134 } 135 136 SDValue MipsTargetLowering::getTargetNode(GlobalAddressSDNode *N, EVT Ty, 137 SelectionDAG &DAG, 138 unsigned Flag) const { 139 return DAG.getTargetGlobalAddress(N->getGlobal(), SDLoc(N), Ty, 0, Flag); 140 } 141 142 SDValue MipsTargetLowering::getTargetNode(ExternalSymbolSDNode *N, EVT Ty, 143 SelectionDAG &DAG, 144 unsigned Flag) const { 145 return DAG.getTargetExternalSymbol(N->getSymbol(), Ty, Flag); 146 } 147 148 SDValue MipsTargetLowering::getTargetNode(BlockAddressSDNode *N, EVT Ty, 149 SelectionDAG &DAG, 150 unsigned Flag) const { 151 return DAG.getTargetBlockAddress(N->getBlockAddress(), Ty, 0, Flag); 152 } 153 154 SDValue MipsTargetLowering::getTargetNode(JumpTableSDNode *N, EVT Ty, 155 SelectionDAG &DAG, 156 unsigned Flag) const { 157 return DAG.getTargetJumpTable(N->getIndex(), Ty, Flag); 158 } 159 160 SDValue MipsTargetLowering::getTargetNode(ConstantPoolSDNode *N, EVT Ty, 161 SelectionDAG &DAG, 162 unsigned Flag) const { 163 return DAG.getTargetConstantPool(N->getConstVal(), Ty, N->getAlign(), 164 N->getOffset(), Flag); 165 } 166 167 const char *MipsTargetLowering::getTargetNodeName(unsigned Opcode) const { 168 switch ((MipsISD::NodeType)Opcode) { 169 case MipsISD::FIRST_NUMBER: break; 170 case MipsISD::JmpLink: return "MipsISD::JmpLink"; 171 case MipsISD::TailCall: return "MipsISD::TailCall"; 172 case MipsISD::Highest: return "MipsISD::Highest"; 173 case MipsISD::Higher: return "MipsISD::Higher"; 174 case MipsISD::Hi: return "MipsISD::Hi"; 175 case MipsISD::Lo: return "MipsISD::Lo"; 176 case MipsISD::GotHi: return "MipsISD::GotHi"; 177 case MipsISD::TlsHi: return "MipsISD::TlsHi"; 178 case MipsISD::GPRel: return "MipsISD::GPRel"; 179 case MipsISD::ThreadPointer: return "MipsISD::ThreadPointer"; 180 case MipsISD::Ret: return "MipsISD::Ret"; 181 case MipsISD::ERet: return "MipsISD::ERet"; 182 case MipsISD::EH_RETURN: return "MipsISD::EH_RETURN"; 183 case MipsISD::FMS: return "MipsISD::FMS"; 184 case MipsISD::FPBrcond: return "MipsISD::FPBrcond"; 185 case MipsISD::FPCmp: return "MipsISD::FPCmp"; 186 case MipsISD::FSELECT: return "MipsISD::FSELECT"; 187 case MipsISD::MTC1_D64: return "MipsISD::MTC1_D64"; 188 case MipsISD::CMovFP_T: return "MipsISD::CMovFP_T"; 189 case MipsISD::CMovFP_F: return "MipsISD::CMovFP_F"; 190 case MipsISD::TruncIntFP: return "MipsISD::TruncIntFP"; 191 case MipsISD::MFHI: return "MipsISD::MFHI"; 192 case MipsISD::MFLO: return "MipsISD::MFLO"; 193 case MipsISD::MTLOHI: return "MipsISD::MTLOHI"; 194 case MipsISD::Mult: return "MipsISD::Mult"; 195 case MipsISD::Multu: return "MipsISD::Multu"; 196 case MipsISD::MAdd: return "MipsISD::MAdd"; 197 case MipsISD::MAddu: return "MipsISD::MAddu"; 198 case MipsISD::MSub: return "MipsISD::MSub"; 199 case MipsISD::MSubu: return "MipsISD::MSubu"; 200 case MipsISD::DivRem: return "MipsISD::DivRem"; 201 case MipsISD::DivRemU: return "MipsISD::DivRemU"; 202 case MipsISD::DivRem16: return "MipsISD::DivRem16"; 203 case MipsISD::DivRemU16: return "MipsISD::DivRemU16"; 204 case MipsISD::BuildPairF64: return "MipsISD::BuildPairF64"; 205 case MipsISD::ExtractElementF64: return "MipsISD::ExtractElementF64"; 206 case MipsISD::Wrapper: return "MipsISD::Wrapper"; 207 case MipsISD::DynAlloc: return "MipsISD::DynAlloc"; 208 case MipsISD::Sync: return "MipsISD::Sync"; 209 case MipsISD::Ext: return "MipsISD::Ext"; 210 case MipsISD::Ins: return "MipsISD::Ins"; 211 case MipsISD::CIns: return "MipsISD::CIns"; 212 case MipsISD::LWL: return "MipsISD::LWL"; 213 case MipsISD::LWR: return "MipsISD::LWR"; 214 case MipsISD::SWL: return "MipsISD::SWL"; 215 case MipsISD::SWR: return "MipsISD::SWR"; 216 case MipsISD::LDL: return "MipsISD::LDL"; 217 case MipsISD::LDR: return "MipsISD::LDR"; 218 case MipsISD::SDL: return "MipsISD::SDL"; 219 case MipsISD::SDR: return "MipsISD::SDR"; 220 case MipsISD::EXTP: return "MipsISD::EXTP"; 221 case MipsISD::EXTPDP: return "MipsISD::EXTPDP"; 222 case MipsISD::EXTR_S_H: return "MipsISD::EXTR_S_H"; 223 case MipsISD::EXTR_W: return "MipsISD::EXTR_W"; 224 case MipsISD::EXTR_R_W: return "MipsISD::EXTR_R_W"; 225 case MipsISD::EXTR_RS_W: return "MipsISD::EXTR_RS_W"; 226 case MipsISD::SHILO: return "MipsISD::SHILO"; 227 case MipsISD::MTHLIP: return "MipsISD::MTHLIP"; 228 case MipsISD::MULSAQ_S_W_PH: return "MipsISD::MULSAQ_S_W_PH"; 229 case MipsISD::MAQ_S_W_PHL: return "MipsISD::MAQ_S_W_PHL"; 230 case MipsISD::MAQ_S_W_PHR: return "MipsISD::MAQ_S_W_PHR"; 231 case MipsISD::MAQ_SA_W_PHL: return "MipsISD::MAQ_SA_W_PHL"; 232 case MipsISD::MAQ_SA_W_PHR: return "MipsISD::MAQ_SA_W_PHR"; 233 case MipsISD::DPAU_H_QBL: return "MipsISD::DPAU_H_QBL"; 234 case MipsISD::DPAU_H_QBR: return "MipsISD::DPAU_H_QBR"; 235 case MipsISD::DPSU_H_QBL: return "MipsISD::DPSU_H_QBL"; 236 case MipsISD::DPSU_H_QBR: return "MipsISD::DPSU_H_QBR"; 237 case MipsISD::DPAQ_S_W_PH: return "MipsISD::DPAQ_S_W_PH"; 238 case MipsISD::DPSQ_S_W_PH: return "MipsISD::DPSQ_S_W_PH"; 239 case MipsISD::DPAQ_SA_L_W: return "MipsISD::DPAQ_SA_L_W"; 240 case MipsISD::DPSQ_SA_L_W: return "MipsISD::DPSQ_SA_L_W"; 241 case MipsISD::DPA_W_PH: return "MipsISD::DPA_W_PH"; 242 case MipsISD::DPS_W_PH: return "MipsISD::DPS_W_PH"; 243 case MipsISD::DPAQX_S_W_PH: return "MipsISD::DPAQX_S_W_PH"; 244 case MipsISD::DPAQX_SA_W_PH: return "MipsISD::DPAQX_SA_W_PH"; 245 case MipsISD::DPAX_W_PH: return "MipsISD::DPAX_W_PH"; 246 case MipsISD::DPSX_W_PH: return "MipsISD::DPSX_W_PH"; 247 case MipsISD::DPSQX_S_W_PH: return "MipsISD::DPSQX_S_W_PH"; 248 case MipsISD::DPSQX_SA_W_PH: return "MipsISD::DPSQX_SA_W_PH"; 249 case MipsISD::MULSA_W_PH: return "MipsISD::MULSA_W_PH"; 250 case MipsISD::MULT: return "MipsISD::MULT"; 251 case MipsISD::MULTU: return "MipsISD::MULTU"; 252 case MipsISD::MADD_DSP: return "MipsISD::MADD_DSP"; 253 case MipsISD::MADDU_DSP: return "MipsISD::MADDU_DSP"; 254 case MipsISD::MSUB_DSP: return "MipsISD::MSUB_DSP"; 255 case MipsISD::MSUBU_DSP: return "MipsISD::MSUBU_DSP"; 256 case MipsISD::SHLL_DSP: return "MipsISD::SHLL_DSP"; 257 case MipsISD::SHRA_DSP: return "MipsISD::SHRA_DSP"; 258 case MipsISD::SHRL_DSP: return "MipsISD::SHRL_DSP"; 259 case MipsISD::SETCC_DSP: return "MipsISD::SETCC_DSP"; 260 case MipsISD::SELECT_CC_DSP: return "MipsISD::SELECT_CC_DSP"; 261 case MipsISD::VALL_ZERO: return "MipsISD::VALL_ZERO"; 262 case MipsISD::VANY_ZERO: return "MipsISD::VANY_ZERO"; 263 case MipsISD::VALL_NONZERO: return "MipsISD::VALL_NONZERO"; 264 case MipsISD::VANY_NONZERO: return "MipsISD::VANY_NONZERO"; 265 case MipsISD::VCEQ: return "MipsISD::VCEQ"; 266 case MipsISD::VCLE_S: return "MipsISD::VCLE_S"; 267 case MipsISD::VCLE_U: return "MipsISD::VCLE_U"; 268 case MipsISD::VCLT_S: return "MipsISD::VCLT_S"; 269 case MipsISD::VCLT_U: return "MipsISD::VCLT_U"; 270 case MipsISD::VEXTRACT_SEXT_ELT: return "MipsISD::VEXTRACT_SEXT_ELT"; 271 case MipsISD::VEXTRACT_ZEXT_ELT: return "MipsISD::VEXTRACT_ZEXT_ELT"; 272 case MipsISD::VNOR: return "MipsISD::VNOR"; 273 case MipsISD::VSHF: return "MipsISD::VSHF"; 274 case MipsISD::SHF: return "MipsISD::SHF"; 275 case MipsISD::ILVEV: return "MipsISD::ILVEV"; 276 case MipsISD::ILVOD: return "MipsISD::ILVOD"; 277 case MipsISD::ILVL: return "MipsISD::ILVL"; 278 case MipsISD::ILVR: return "MipsISD::ILVR"; 279 case MipsISD::PCKEV: return "MipsISD::PCKEV"; 280 case MipsISD::PCKOD: return "MipsISD::PCKOD"; 281 case MipsISD::INSVE: return "MipsISD::INSVE"; 282 } 283 return nullptr; 284 } 285 286 MipsTargetLowering::MipsTargetLowering(const MipsTargetMachine &TM, 287 const MipsSubtarget &STI) 288 : TargetLowering(TM), Subtarget(STI), ABI(TM.getABI()) { 289 // Mips does not have i1 type, so use i32 for 290 // setcc operations results (slt, sgt, ...). 291 setBooleanContents(ZeroOrOneBooleanContent); 292 setBooleanVectorContents(ZeroOrNegativeOneBooleanContent); 293 // The cmp.cond.fmt instruction in MIPS32r6/MIPS64r6 uses 0 and -1 like MSA 294 // does. Integer booleans still use 0 and 1. 295 if (Subtarget.hasMips32r6()) 296 setBooleanContents(ZeroOrOneBooleanContent, 297 ZeroOrNegativeOneBooleanContent); 298 299 // Load extented operations for i1 types must be promoted 300 for (MVT VT : MVT::integer_valuetypes()) { 301 setLoadExtAction(ISD::EXTLOAD, VT, MVT::i1, Promote); 302 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i1, Promote); 303 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i1, Promote); 304 } 305 306 // MIPS doesn't have extending float->double load/store. Set LoadExtAction 307 // for f32, f16 308 for (MVT VT : MVT::fp_valuetypes()) { 309 setLoadExtAction(ISD::EXTLOAD, VT, MVT::f32, Expand); 310 setLoadExtAction(ISD::EXTLOAD, VT, MVT::f16, Expand); 311 } 312 313 // Set LoadExtAction for f16 vectors to Expand 314 for (MVT VT : MVT::fp_fixedlen_vector_valuetypes()) { 315 MVT F16VT = MVT::getVectorVT(MVT::f16, VT.getVectorNumElements()); 316 if (F16VT.isValid()) 317 setLoadExtAction(ISD::EXTLOAD, VT, F16VT, Expand); 318 } 319 320 setTruncStoreAction(MVT::f32, MVT::f16, Expand); 321 setTruncStoreAction(MVT::f64, MVT::f16, Expand); 322 323 setTruncStoreAction(MVT::f64, MVT::f32, Expand); 324 325 // Used by legalize types to correctly generate the setcc result. 326 // Without this, every float setcc comes with a AND/OR with the result, 327 // we don't want this, since the fpcmp result goes to a flag register, 328 // which is used implicitly by brcond and select operations. 329 AddPromotedToType(ISD::SETCC, MVT::i1, MVT::i32); 330 331 // Mips Custom Operations 332 setOperationAction(ISD::BR_JT, MVT::Other, Expand); 333 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom); 334 setOperationAction(ISD::BlockAddress, MVT::i32, Custom); 335 setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom); 336 setOperationAction(ISD::JumpTable, MVT::i32, Custom); 337 setOperationAction(ISD::ConstantPool, MVT::i32, Custom); 338 setOperationAction(ISD::SELECT, MVT::f32, Custom); 339 setOperationAction(ISD::SELECT, MVT::f64, Custom); 340 setOperationAction(ISD::SELECT, MVT::i32, Custom); 341 setOperationAction(ISD::SETCC, MVT::f32, Custom); 342 setOperationAction(ISD::SETCC, MVT::f64, Custom); 343 setOperationAction(ISD::BRCOND, MVT::Other, Custom); 344 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom); 345 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom); 346 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom); 347 348 if (!(TM.Options.NoNaNsFPMath || Subtarget.inAbs2008Mode())) { 349 setOperationAction(ISD::FABS, MVT::f32, Custom); 350 setOperationAction(ISD::FABS, MVT::f64, Custom); 351 } 352 353 if (Subtarget.isGP64bit()) { 354 setOperationAction(ISD::GlobalAddress, MVT::i64, Custom); 355 setOperationAction(ISD::BlockAddress, MVT::i64, Custom); 356 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom); 357 setOperationAction(ISD::JumpTable, MVT::i64, Custom); 358 setOperationAction(ISD::ConstantPool, MVT::i64, Custom); 359 setOperationAction(ISD::SELECT, MVT::i64, Custom); 360 setOperationAction(ISD::LOAD, MVT::i64, Custom); 361 setOperationAction(ISD::STORE, MVT::i64, Custom); 362 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom); 363 setOperationAction(ISD::SHL_PARTS, MVT::i64, Custom); 364 setOperationAction(ISD::SRA_PARTS, MVT::i64, Custom); 365 setOperationAction(ISD::SRL_PARTS, MVT::i64, Custom); 366 } 367 368 if (!Subtarget.isGP64bit()) { 369 setOperationAction(ISD::SHL_PARTS, MVT::i32, Custom); 370 setOperationAction(ISD::SRA_PARTS, MVT::i32, Custom); 371 setOperationAction(ISD::SRL_PARTS, MVT::i32, Custom); 372 } 373 374 setOperationAction(ISD::EH_DWARF_CFA, MVT::i32, Custom); 375 if (Subtarget.isGP64bit()) 376 setOperationAction(ISD::EH_DWARF_CFA, MVT::i64, Custom); 377 378 setOperationAction(ISD::SDIV, MVT::i32, Expand); 379 setOperationAction(ISD::SREM, MVT::i32, Expand); 380 setOperationAction(ISD::UDIV, MVT::i32, Expand); 381 setOperationAction(ISD::UREM, MVT::i32, Expand); 382 setOperationAction(ISD::SDIV, MVT::i64, Expand); 383 setOperationAction(ISD::SREM, MVT::i64, Expand); 384 setOperationAction(ISD::UDIV, MVT::i64, Expand); 385 setOperationAction(ISD::UREM, MVT::i64, Expand); 386 387 // Operations not directly supported by Mips. 388 setOperationAction(ISD::BR_CC, MVT::f32, Expand); 389 setOperationAction(ISD::BR_CC, MVT::f64, Expand); 390 setOperationAction(ISD::BR_CC, MVT::i32, Expand); 391 setOperationAction(ISD::BR_CC, MVT::i64, Expand); 392 setOperationAction(ISD::SELECT_CC, MVT::i32, Expand); 393 setOperationAction(ISD::SELECT_CC, MVT::i64, Expand); 394 setOperationAction(ISD::SELECT_CC, MVT::f32, Expand); 395 setOperationAction(ISD::SELECT_CC, MVT::f64, Expand); 396 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand); 397 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Expand); 398 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand); 399 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Expand); 400 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand); 401 if (Subtarget.hasCnMips()) { 402 setOperationAction(ISD::CTPOP, MVT::i32, Legal); 403 setOperationAction(ISD::CTPOP, MVT::i64, Legal); 404 } else { 405 setOperationAction(ISD::CTPOP, MVT::i32, Expand); 406 setOperationAction(ISD::CTPOP, MVT::i64, Expand); 407 } 408 setOperationAction(ISD::CTTZ, MVT::i32, Expand); 409 setOperationAction(ISD::CTTZ, MVT::i64, Expand); 410 setOperationAction(ISD::ROTL, MVT::i32, Expand); 411 setOperationAction(ISD::ROTL, MVT::i64, Expand); 412 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Expand); 413 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64, Expand); 414 415 if (!Subtarget.hasMips32r2()) 416 setOperationAction(ISD::ROTR, MVT::i32, Expand); 417 418 if (!Subtarget.hasMips64r2()) 419 setOperationAction(ISD::ROTR, MVT::i64, Expand); 420 421 setOperationAction(ISD::FSIN, MVT::f32, Expand); 422 setOperationAction(ISD::FSIN, MVT::f64, Expand); 423 setOperationAction(ISD::FCOS, MVT::f32, Expand); 424 setOperationAction(ISD::FCOS, MVT::f64, Expand); 425 setOperationAction(ISD::FSINCOS, MVT::f32, Expand); 426 setOperationAction(ISD::FSINCOS, MVT::f64, Expand); 427 setOperationAction(ISD::FPOW, MVT::f32, Expand); 428 setOperationAction(ISD::FPOW, MVT::f64, Expand); 429 setOperationAction(ISD::FLOG, MVT::f32, Expand); 430 setOperationAction(ISD::FLOG2, MVT::f32, Expand); 431 setOperationAction(ISD::FLOG10, MVT::f32, Expand); 432 setOperationAction(ISD::FEXP, MVT::f32, Expand); 433 setOperationAction(ISD::FMA, MVT::f32, Expand); 434 setOperationAction(ISD::FMA, MVT::f64, Expand); 435 setOperationAction(ISD::FREM, MVT::f32, Expand); 436 setOperationAction(ISD::FREM, MVT::f64, Expand); 437 438 // Lower f16 conversion operations into library calls 439 setOperationAction(ISD::FP16_TO_FP, MVT::f32, Expand); 440 setOperationAction(ISD::FP_TO_FP16, MVT::f32, Expand); 441 setOperationAction(ISD::FP16_TO_FP, MVT::f64, Expand); 442 setOperationAction(ISD::FP_TO_FP16, MVT::f64, Expand); 443 444 setOperationAction(ISD::EH_RETURN, MVT::Other, Custom); 445 446 setOperationAction(ISD::VASTART, MVT::Other, Custom); 447 setOperationAction(ISD::VAARG, MVT::Other, Custom); 448 setOperationAction(ISD::VACOPY, MVT::Other, Expand); 449 setOperationAction(ISD::VAEND, MVT::Other, Expand); 450 451 // Use the default for now 452 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand); 453 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand); 454 455 if (!Subtarget.isGP64bit()) { 456 setOperationAction(ISD::ATOMIC_LOAD, MVT::i64, Expand); 457 setOperationAction(ISD::ATOMIC_STORE, MVT::i64, Expand); 458 } 459 460 if (!Subtarget.hasMips32r2()) { 461 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8, Expand); 462 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand); 463 } 464 465 // MIPS16 lacks MIPS32's clz and clo instructions. 466 if (!Subtarget.hasMips32() || Subtarget.inMips16Mode()) 467 setOperationAction(ISD::CTLZ, MVT::i32, Expand); 468 if (!Subtarget.hasMips64()) 469 setOperationAction(ISD::CTLZ, MVT::i64, Expand); 470 471 if (!Subtarget.hasMips32r2()) 472 setOperationAction(ISD::BSWAP, MVT::i32, Expand); 473 if (!Subtarget.hasMips64r2()) 474 setOperationAction(ISD::BSWAP, MVT::i64, Expand); 475 476 if (Subtarget.isGP64bit()) { 477 setLoadExtAction(ISD::SEXTLOAD, MVT::i64, MVT::i32, Custom); 478 setLoadExtAction(ISD::ZEXTLOAD, MVT::i64, MVT::i32, Custom); 479 setLoadExtAction(ISD::EXTLOAD, MVT::i64, MVT::i32, Custom); 480 setTruncStoreAction(MVT::i64, MVT::i32, Custom); 481 } 482 483 setOperationAction(ISD::TRAP, MVT::Other, Legal); 484 485 setTargetDAGCombine({ISD::SDIVREM, ISD::UDIVREM, ISD::SELECT, ISD::AND, 486 ISD::OR, ISD::ADD, ISD::SUB, ISD::AssertZext, ISD::SHL}); 487 488 if (ABI.IsO32()) { 489 // These libcalls are not available in 32-bit. 490 setLibcallName(RTLIB::SHL_I128, nullptr); 491 setLibcallName(RTLIB::SRL_I128, nullptr); 492 setLibcallName(RTLIB::SRA_I128, nullptr); 493 setLibcallName(RTLIB::MUL_I128, nullptr); 494 setLibcallName(RTLIB::MULO_I64, nullptr); 495 setLibcallName(RTLIB::MULO_I128, nullptr); 496 } 497 498 setMinFunctionAlignment(Subtarget.isGP64bit() ? Align(8) : Align(4)); 499 500 // The arguments on the stack are defined in terms of 4-byte slots on O32 501 // and 8-byte slots on N32/N64. 502 setMinStackArgumentAlignment((ABI.IsN32() || ABI.IsN64()) ? Align(8) 503 : Align(4)); 504 505 setStackPointerRegisterToSaveRestore(ABI.IsN64() ? Mips::SP_64 : Mips::SP); 506 507 MaxStoresPerMemcpy = 16; 508 509 isMicroMips = Subtarget.inMicroMipsMode(); 510 } 511 512 const MipsTargetLowering * 513 MipsTargetLowering::create(const MipsTargetMachine &TM, 514 const MipsSubtarget &STI) { 515 if (STI.inMips16Mode()) 516 return createMips16TargetLowering(TM, STI); 517 518 return createMipsSETargetLowering(TM, STI); 519 } 520 521 // Create a fast isel object. 522 FastISel * 523 MipsTargetLowering::createFastISel(FunctionLoweringInfo &funcInfo, 524 const TargetLibraryInfo *libInfo) const { 525 const MipsTargetMachine &TM = 526 static_cast<const MipsTargetMachine &>(funcInfo.MF->getTarget()); 527 528 // We support only the standard encoding [MIPS32,MIPS32R5] ISAs. 529 bool UseFastISel = TM.Options.EnableFastISel && Subtarget.hasMips32() && 530 !Subtarget.hasMips32r6() && !Subtarget.inMips16Mode() && 531 !Subtarget.inMicroMipsMode(); 532 533 // Disable if either of the following is true: 534 // We do not generate PIC, the ABI is not O32, XGOT is being used. 535 if (!TM.isPositionIndependent() || !TM.getABI().IsO32() || 536 Subtarget.useXGOT()) 537 UseFastISel = false; 538 539 return UseFastISel ? Mips::createFastISel(funcInfo, libInfo) : nullptr; 540 } 541 542 EVT MipsTargetLowering::getSetCCResultType(const DataLayout &, LLVMContext &, 543 EVT VT) const { 544 if (!VT.isVector()) 545 return MVT::i32; 546 return VT.changeVectorElementTypeToInteger(); 547 } 548 549 static SDValue performDivRemCombine(SDNode *N, SelectionDAG &DAG, 550 TargetLowering::DAGCombinerInfo &DCI, 551 const MipsSubtarget &Subtarget) { 552 if (DCI.isBeforeLegalizeOps()) 553 return SDValue(); 554 555 EVT Ty = N->getValueType(0); 556 unsigned LO = (Ty == MVT::i32) ? Mips::LO0 : Mips::LO0_64; 557 unsigned HI = (Ty == MVT::i32) ? Mips::HI0 : Mips::HI0_64; 558 unsigned Opc = N->getOpcode() == ISD::SDIVREM ? MipsISD::DivRem16 : 559 MipsISD::DivRemU16; 560 SDLoc DL(N); 561 562 SDValue DivRem = DAG.getNode(Opc, DL, MVT::Glue, 563 N->getOperand(0), N->getOperand(1)); 564 SDValue InChain = DAG.getEntryNode(); 565 SDValue InGlue = DivRem; 566 567 // insert MFLO 568 if (N->hasAnyUseOfValue(0)) { 569 SDValue CopyFromLo = DAG.getCopyFromReg(InChain, DL, LO, Ty, 570 InGlue); 571 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), CopyFromLo); 572 InChain = CopyFromLo.getValue(1); 573 InGlue = CopyFromLo.getValue(2); 574 } 575 576 // insert MFHI 577 if (N->hasAnyUseOfValue(1)) { 578 SDValue CopyFromHi = DAG.getCopyFromReg(InChain, DL, 579 HI, Ty, InGlue); 580 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), CopyFromHi); 581 } 582 583 return SDValue(); 584 } 585 586 static Mips::CondCode condCodeToFCC(ISD::CondCode CC) { 587 switch (CC) { 588 default: llvm_unreachable("Unknown fp condition code!"); 589 case ISD::SETEQ: 590 case ISD::SETOEQ: return Mips::FCOND_OEQ; 591 case ISD::SETUNE: return Mips::FCOND_UNE; 592 case ISD::SETLT: 593 case ISD::SETOLT: return Mips::FCOND_OLT; 594 case ISD::SETGT: 595 case ISD::SETOGT: return Mips::FCOND_OGT; 596 case ISD::SETLE: 597 case ISD::SETOLE: return Mips::FCOND_OLE; 598 case ISD::SETGE: 599 case ISD::SETOGE: return Mips::FCOND_OGE; 600 case ISD::SETULT: return Mips::FCOND_ULT; 601 case ISD::SETULE: return Mips::FCOND_ULE; 602 case ISD::SETUGT: return Mips::FCOND_UGT; 603 case ISD::SETUGE: return Mips::FCOND_UGE; 604 case ISD::SETUO: return Mips::FCOND_UN; 605 case ISD::SETO: return Mips::FCOND_OR; 606 case ISD::SETNE: 607 case ISD::SETONE: return Mips::FCOND_ONE; 608 case ISD::SETUEQ: return Mips::FCOND_UEQ; 609 } 610 } 611 612 /// This function returns true if the floating point conditional branches and 613 /// conditional moves which use condition code CC should be inverted. 614 static bool invertFPCondCodeUser(Mips::CondCode CC) { 615 if (CC >= Mips::FCOND_F && CC <= Mips::FCOND_NGT) 616 return false; 617 618 assert((CC >= Mips::FCOND_T && CC <= Mips::FCOND_GT) && 619 "Illegal Condition Code"); 620 621 return true; 622 } 623 624 // Creates and returns an FPCmp node from a setcc node. 625 // Returns Op if setcc is not a floating point comparison. 626 static SDValue createFPCmp(SelectionDAG &DAG, const SDValue &Op) { 627 // must be a SETCC node 628 if (Op.getOpcode() != ISD::SETCC) 629 return Op; 630 631 SDValue LHS = Op.getOperand(0); 632 633 if (!LHS.getValueType().isFloatingPoint()) 634 return Op; 635 636 SDValue RHS = Op.getOperand(1); 637 SDLoc DL(Op); 638 639 // Assume the 3rd operand is a CondCodeSDNode. Add code to check the type of 640 // node if necessary. 641 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get(); 642 643 return DAG.getNode(MipsISD::FPCmp, DL, MVT::Glue, LHS, RHS, 644 DAG.getConstant(condCodeToFCC(CC), DL, MVT::i32)); 645 } 646 647 // Creates and returns a CMovFPT/F node. 648 static SDValue createCMovFP(SelectionDAG &DAG, SDValue Cond, SDValue True, 649 SDValue False, const SDLoc &DL) { 650 ConstantSDNode *CC = cast<ConstantSDNode>(Cond.getOperand(2)); 651 bool invert = invertFPCondCodeUser((Mips::CondCode)CC->getSExtValue()); 652 SDValue FCC0 = DAG.getRegister(Mips::FCC0, MVT::i32); 653 654 return DAG.getNode((invert ? MipsISD::CMovFP_F : MipsISD::CMovFP_T), DL, 655 True.getValueType(), True, FCC0, False, Cond); 656 } 657 658 static SDValue performSELECTCombine(SDNode *N, SelectionDAG &DAG, 659 TargetLowering::DAGCombinerInfo &DCI, 660 const MipsSubtarget &Subtarget) { 661 if (DCI.isBeforeLegalizeOps()) 662 return SDValue(); 663 664 SDValue SetCC = N->getOperand(0); 665 666 if ((SetCC.getOpcode() != ISD::SETCC) || 667 !SetCC.getOperand(0).getValueType().isInteger()) 668 return SDValue(); 669 670 SDValue False = N->getOperand(2); 671 EVT FalseTy = False.getValueType(); 672 673 if (!FalseTy.isInteger()) 674 return SDValue(); 675 676 ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(False); 677 678 // If the RHS (False) is 0, we swap the order of the operands 679 // of ISD::SELECT (obviously also inverting the condition) so that we can 680 // take advantage of conditional moves using the $0 register. 681 // Example: 682 // return (a != 0) ? x : 0; 683 // load $reg, x 684 // movz $reg, $0, a 685 if (!FalseC) 686 return SDValue(); 687 688 const SDLoc DL(N); 689 690 if (!FalseC->getZExtValue()) { 691 ISD::CondCode CC = cast<CondCodeSDNode>(SetCC.getOperand(2))->get(); 692 SDValue True = N->getOperand(1); 693 694 SetCC = DAG.getSetCC(DL, SetCC.getValueType(), SetCC.getOperand(0), 695 SetCC.getOperand(1), 696 ISD::getSetCCInverse(CC, SetCC.getValueType())); 697 698 return DAG.getNode(ISD::SELECT, DL, FalseTy, SetCC, False, True); 699 } 700 701 // If both operands are integer constants there's a possibility that we 702 // can do some interesting optimizations. 703 SDValue True = N->getOperand(1); 704 ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(True); 705 706 if (!TrueC || !True.getValueType().isInteger()) 707 return SDValue(); 708 709 // We'll also ignore MVT::i64 operands as this optimizations proves 710 // to be ineffective because of the required sign extensions as the result 711 // of a SETCC operator is always MVT::i32 for non-vector types. 712 if (True.getValueType() == MVT::i64) 713 return SDValue(); 714 715 int64_t Diff = TrueC->getSExtValue() - FalseC->getSExtValue(); 716 717 // 1) (a < x) ? y : y-1 718 // slti $reg1, a, x 719 // addiu $reg2, $reg1, y-1 720 if (Diff == 1) 721 return DAG.getNode(ISD::ADD, DL, SetCC.getValueType(), SetCC, False); 722 723 // 2) (a < x) ? y-1 : y 724 // slti $reg1, a, x 725 // xor $reg1, $reg1, 1 726 // addiu $reg2, $reg1, y-1 727 if (Diff == -1) { 728 ISD::CondCode CC = cast<CondCodeSDNode>(SetCC.getOperand(2))->get(); 729 SetCC = DAG.getSetCC(DL, SetCC.getValueType(), SetCC.getOperand(0), 730 SetCC.getOperand(1), 731 ISD::getSetCCInverse(CC, SetCC.getValueType())); 732 return DAG.getNode(ISD::ADD, DL, SetCC.getValueType(), SetCC, True); 733 } 734 735 // Could not optimize. 736 return SDValue(); 737 } 738 739 static SDValue performCMovFPCombine(SDNode *N, SelectionDAG &DAG, 740 TargetLowering::DAGCombinerInfo &DCI, 741 const MipsSubtarget &Subtarget) { 742 if (DCI.isBeforeLegalizeOps()) 743 return SDValue(); 744 745 SDValue ValueIfTrue = N->getOperand(0), ValueIfFalse = N->getOperand(2); 746 747 ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(ValueIfFalse); 748 if (!FalseC || FalseC->getZExtValue()) 749 return SDValue(); 750 751 // Since RHS (False) is 0, we swap the order of the True/False operands 752 // (obviously also inverting the condition) so that we can 753 // take advantage of conditional moves using the $0 register. 754 // Example: 755 // return (a != 0) ? x : 0; 756 // load $reg, x 757 // movz $reg, $0, a 758 unsigned Opc = (N->getOpcode() == MipsISD::CMovFP_T) ? MipsISD::CMovFP_F : 759 MipsISD::CMovFP_T; 760 761 SDValue FCC = N->getOperand(1), Glue = N->getOperand(3); 762 return DAG.getNode(Opc, SDLoc(N), ValueIfFalse.getValueType(), 763 ValueIfFalse, FCC, ValueIfTrue, Glue); 764 } 765 766 static SDValue performANDCombine(SDNode *N, SelectionDAG &DAG, 767 TargetLowering::DAGCombinerInfo &DCI, 768 const MipsSubtarget &Subtarget) { 769 if (DCI.isBeforeLegalizeOps() || !Subtarget.hasExtractInsert()) 770 return SDValue(); 771 772 SDValue FirstOperand = N->getOperand(0); 773 unsigned FirstOperandOpc = FirstOperand.getOpcode(); 774 SDValue Mask = N->getOperand(1); 775 EVT ValTy = N->getValueType(0); 776 SDLoc DL(N); 777 778 uint64_t Pos = 0; 779 unsigned SMPos, SMSize; 780 ConstantSDNode *CN; 781 SDValue NewOperand; 782 unsigned Opc; 783 784 // Op's second operand must be a shifted mask. 785 if (!(CN = dyn_cast<ConstantSDNode>(Mask)) || 786 !isShiftedMask_64(CN->getZExtValue(), SMPos, SMSize)) 787 return SDValue(); 788 789 if (FirstOperandOpc == ISD::SRA || FirstOperandOpc == ISD::SRL) { 790 // Pattern match EXT. 791 // $dst = and ((sra or srl) $src , pos), (2**size - 1) 792 // => ext $dst, $src, pos, size 793 794 // The second operand of the shift must be an immediate. 795 if (!(CN = dyn_cast<ConstantSDNode>(FirstOperand.getOperand(1)))) 796 return SDValue(); 797 798 Pos = CN->getZExtValue(); 799 800 // Return if the shifted mask does not start at bit 0 or the sum of its size 801 // and Pos exceeds the word's size. 802 if (SMPos != 0 || Pos + SMSize > ValTy.getSizeInBits()) 803 return SDValue(); 804 805 Opc = MipsISD::Ext; 806 NewOperand = FirstOperand.getOperand(0); 807 } else if (FirstOperandOpc == ISD::SHL && Subtarget.hasCnMips()) { 808 // Pattern match CINS. 809 // $dst = and (shl $src , pos), mask 810 // => cins $dst, $src, pos, size 811 // mask is a shifted mask with consecutive 1's, pos = shift amount, 812 // size = population count. 813 814 // The second operand of the shift must be an immediate. 815 if (!(CN = dyn_cast<ConstantSDNode>(FirstOperand.getOperand(1)))) 816 return SDValue(); 817 818 Pos = CN->getZExtValue(); 819 820 if (SMPos != Pos || Pos >= ValTy.getSizeInBits() || SMSize >= 32 || 821 Pos + SMSize > ValTy.getSizeInBits()) 822 return SDValue(); 823 824 NewOperand = FirstOperand.getOperand(0); 825 // SMSize is 'location' (position) in this case, not size. 826 SMSize--; 827 Opc = MipsISD::CIns; 828 } else { 829 // Pattern match EXT. 830 // $dst = and $src, (2**size - 1) , if size > 16 831 // => ext $dst, $src, pos, size , pos = 0 832 833 // If the mask is <= 0xffff, andi can be used instead. 834 if (CN->getZExtValue() <= 0xffff) 835 return SDValue(); 836 837 // Return if the mask doesn't start at position 0. 838 if (SMPos) 839 return SDValue(); 840 841 Opc = MipsISD::Ext; 842 NewOperand = FirstOperand; 843 } 844 return DAG.getNode(Opc, DL, ValTy, NewOperand, 845 DAG.getConstant(Pos, DL, MVT::i32), 846 DAG.getConstant(SMSize, DL, MVT::i32)); 847 } 848 849 static SDValue performORCombine(SDNode *N, SelectionDAG &DAG, 850 TargetLowering::DAGCombinerInfo &DCI, 851 const MipsSubtarget &Subtarget) { 852 // Pattern match INS. 853 // $dst = or (and $src1 , mask0), (and (shl $src, pos), mask1), 854 // where mask1 = (2**size - 1) << pos, mask0 = ~mask1 855 // => ins $dst, $src, size, pos, $src1 856 if (DCI.isBeforeLegalizeOps() || !Subtarget.hasExtractInsert()) 857 return SDValue(); 858 859 SDValue And0 = N->getOperand(0), And1 = N->getOperand(1); 860 unsigned SMPos0, SMSize0, SMPos1, SMSize1; 861 ConstantSDNode *CN, *CN1; 862 863 // See if Op's first operand matches (and $src1 , mask0). 864 if (And0.getOpcode() != ISD::AND) 865 return SDValue(); 866 867 if (!(CN = dyn_cast<ConstantSDNode>(And0.getOperand(1))) || 868 !isShiftedMask_64(~CN->getSExtValue(), SMPos0, SMSize0)) 869 return SDValue(); 870 871 // See if Op's second operand matches (and (shl $src, pos), mask1). 872 if (And1.getOpcode() == ISD::AND && 873 And1.getOperand(0).getOpcode() == ISD::SHL) { 874 875 if (!(CN = dyn_cast<ConstantSDNode>(And1.getOperand(1))) || 876 !isShiftedMask_64(CN->getZExtValue(), SMPos1, SMSize1)) 877 return SDValue(); 878 879 // The shift masks must have the same position and size. 880 if (SMPos0 != SMPos1 || SMSize0 != SMSize1) 881 return SDValue(); 882 883 SDValue Shl = And1.getOperand(0); 884 885 if (!(CN = dyn_cast<ConstantSDNode>(Shl.getOperand(1)))) 886 return SDValue(); 887 888 unsigned Shamt = CN->getZExtValue(); 889 890 // Return if the shift amount and the first bit position of mask are not the 891 // same. 892 EVT ValTy = N->getValueType(0); 893 if ((Shamt != SMPos0) || (SMPos0 + SMSize0 > ValTy.getSizeInBits())) 894 return SDValue(); 895 896 SDLoc DL(N); 897 return DAG.getNode(MipsISD::Ins, DL, ValTy, Shl.getOperand(0), 898 DAG.getConstant(SMPos0, DL, MVT::i32), 899 DAG.getConstant(SMSize0, DL, MVT::i32), 900 And0.getOperand(0)); 901 } else { 902 // Pattern match DINS. 903 // $dst = or (and $src, mask0), mask1 904 // where mask0 = ((1 << SMSize0) -1) << SMPos0 905 // => dins $dst, $src, pos, size 906 if (~CN->getSExtValue() == ((((int64_t)1 << SMSize0) - 1) << SMPos0) && 907 ((SMSize0 + SMPos0 <= 64 && Subtarget.hasMips64r2()) || 908 (SMSize0 + SMPos0 <= 32))) { 909 // Check if AND instruction has constant as argument 910 bool isConstCase = And1.getOpcode() != ISD::AND; 911 if (And1.getOpcode() == ISD::AND) { 912 if (!(CN1 = dyn_cast<ConstantSDNode>(And1->getOperand(1)))) 913 return SDValue(); 914 } else { 915 if (!(CN1 = dyn_cast<ConstantSDNode>(N->getOperand(1)))) 916 return SDValue(); 917 } 918 // Don't generate INS if constant OR operand doesn't fit into bits 919 // cleared by constant AND operand. 920 if (CN->getSExtValue() & CN1->getSExtValue()) 921 return SDValue(); 922 923 SDLoc DL(N); 924 EVT ValTy = N->getOperand(0)->getValueType(0); 925 SDValue Const1; 926 SDValue SrlX; 927 if (!isConstCase) { 928 Const1 = DAG.getConstant(SMPos0, DL, MVT::i32); 929 SrlX = DAG.getNode(ISD::SRL, DL, And1->getValueType(0), And1, Const1); 930 } 931 return DAG.getNode( 932 MipsISD::Ins, DL, N->getValueType(0), 933 isConstCase 934 ? DAG.getConstant(CN1->getSExtValue() >> SMPos0, DL, ValTy) 935 : SrlX, 936 DAG.getConstant(SMPos0, DL, MVT::i32), 937 DAG.getConstant(ValTy.getSizeInBits() / 8 < 8 ? SMSize0 & 31 938 : SMSize0, 939 DL, MVT::i32), 940 And0->getOperand(0)); 941 942 } 943 return SDValue(); 944 } 945 } 946 947 static SDValue performMADD_MSUBCombine(SDNode *ROOTNode, SelectionDAG &CurDAG, 948 const MipsSubtarget &Subtarget) { 949 // ROOTNode must have a multiplication as an operand for the match to be 950 // successful. 951 if (ROOTNode->getOperand(0).getOpcode() != ISD::MUL && 952 ROOTNode->getOperand(1).getOpcode() != ISD::MUL) 953 return SDValue(); 954 955 // We don't handle vector types here. 956 if (ROOTNode->getValueType(0).isVector()) 957 return SDValue(); 958 959 // For MIPS64, madd / msub instructions are inefficent to use with 64 bit 960 // arithmetic. E.g. 961 // (add (mul a b) c) => 962 // let res = (madd (mthi (drotr c 32))x(mtlo c) a b) in 963 // MIPS64: (or (dsll (mfhi res) 32) (dsrl (dsll (mflo res) 32) 32) 964 // or 965 // MIPS64R2: (dins (mflo res) (mfhi res) 32 32) 966 // 967 // The overhead of setting up the Hi/Lo registers and reassembling the 968 // result makes this a dubious optimzation for MIPS64. The core of the 969 // problem is that Hi/Lo contain the upper and lower 32 bits of the 970 // operand and result. 971 // 972 // It requires a chain of 4 add/mul for MIPS64R2 to get better code 973 // density than doing it naively, 5 for MIPS64. Additionally, using 974 // madd/msub on MIPS64 requires the operands actually be 32 bit sign 975 // extended operands, not true 64 bit values. 976 // 977 // FIXME: For the moment, disable this completely for MIPS64. 978 if (Subtarget.hasMips64()) 979 return SDValue(); 980 981 SDValue Mult = ROOTNode->getOperand(0).getOpcode() == ISD::MUL 982 ? ROOTNode->getOperand(0) 983 : ROOTNode->getOperand(1); 984 985 SDValue AddOperand = ROOTNode->getOperand(0).getOpcode() == ISD::MUL 986 ? ROOTNode->getOperand(1) 987 : ROOTNode->getOperand(0); 988 989 // Transform this to a MADD only if the user of this node is the add. 990 // If there are other users of the mul, this function returns here. 991 if (!Mult.hasOneUse()) 992 return SDValue(); 993 994 // maddu and madd are unusual instructions in that on MIPS64 bits 63..31 995 // must be in canonical form, i.e. sign extended. For MIPS32, the operands 996 // of the multiply must have 32 or more sign bits, otherwise we cannot 997 // perform this optimization. We have to check this here as we're performing 998 // this optimization pre-legalization. 999 SDValue MultLHS = Mult->getOperand(0); 1000 SDValue MultRHS = Mult->getOperand(1); 1001 1002 bool IsSigned = MultLHS->getOpcode() == ISD::SIGN_EXTEND && 1003 MultRHS->getOpcode() == ISD::SIGN_EXTEND; 1004 bool IsUnsigned = MultLHS->getOpcode() == ISD::ZERO_EXTEND && 1005 MultRHS->getOpcode() == ISD::ZERO_EXTEND; 1006 1007 if (!IsSigned && !IsUnsigned) 1008 return SDValue(); 1009 1010 // Initialize accumulator. 1011 SDLoc DL(ROOTNode); 1012 SDValue TopHalf; 1013 SDValue BottomHalf; 1014 BottomHalf = CurDAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32, AddOperand, 1015 CurDAG.getIntPtrConstant(0, DL)); 1016 1017 TopHalf = CurDAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32, AddOperand, 1018 CurDAG.getIntPtrConstant(1, DL)); 1019 SDValue ACCIn = CurDAG.getNode(MipsISD::MTLOHI, DL, MVT::Untyped, 1020 BottomHalf, 1021 TopHalf); 1022 1023 // Create MipsMAdd(u) / MipsMSub(u) node. 1024 bool IsAdd = ROOTNode->getOpcode() == ISD::ADD; 1025 unsigned Opcode = IsAdd ? (IsUnsigned ? MipsISD::MAddu : MipsISD::MAdd) 1026 : (IsUnsigned ? MipsISD::MSubu : MipsISD::MSub); 1027 SDValue MAddOps[3] = { 1028 CurDAG.getNode(ISD::TRUNCATE, DL, MVT::i32, Mult->getOperand(0)), 1029 CurDAG.getNode(ISD::TRUNCATE, DL, MVT::i32, Mult->getOperand(1)), ACCIn}; 1030 EVT VTs[2] = {MVT::i32, MVT::i32}; 1031 SDValue MAdd = CurDAG.getNode(Opcode, DL, VTs, MAddOps); 1032 1033 SDValue ResLo = CurDAG.getNode(MipsISD::MFLO, DL, MVT::i32, MAdd); 1034 SDValue ResHi = CurDAG.getNode(MipsISD::MFHI, DL, MVT::i32, MAdd); 1035 SDValue Combined = 1036 CurDAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, ResLo, ResHi); 1037 return Combined; 1038 } 1039 1040 static SDValue performSUBCombine(SDNode *N, SelectionDAG &DAG, 1041 TargetLowering::DAGCombinerInfo &DCI, 1042 const MipsSubtarget &Subtarget) { 1043 // (sub v0 (mul v1, v2)) => (msub v1, v2, v0) 1044 if (DCI.isBeforeLegalizeOps()) { 1045 if (Subtarget.hasMips32() && !Subtarget.hasMips32r6() && 1046 !Subtarget.inMips16Mode() && N->getValueType(0) == MVT::i64) 1047 return performMADD_MSUBCombine(N, DAG, Subtarget); 1048 1049 return SDValue(); 1050 } 1051 1052 return SDValue(); 1053 } 1054 1055 static SDValue performADDCombine(SDNode *N, SelectionDAG &DAG, 1056 TargetLowering::DAGCombinerInfo &DCI, 1057 const MipsSubtarget &Subtarget) { 1058 // (add v0 (mul v1, v2)) => (madd v1, v2, v0) 1059 if (DCI.isBeforeLegalizeOps()) { 1060 if (Subtarget.hasMips32() && !Subtarget.hasMips32r6() && 1061 !Subtarget.inMips16Mode() && N->getValueType(0) == MVT::i64) 1062 return performMADD_MSUBCombine(N, DAG, Subtarget); 1063 1064 return SDValue(); 1065 } 1066 1067 // (add v0, (add v1, abs_lo(tjt))) => (add (add v0, v1), abs_lo(tjt)) 1068 SDValue Add = N->getOperand(1); 1069 1070 if (Add.getOpcode() != ISD::ADD) 1071 return SDValue(); 1072 1073 SDValue Lo = Add.getOperand(1); 1074 1075 if ((Lo.getOpcode() != MipsISD::Lo) || 1076 (Lo.getOperand(0).getOpcode() != ISD::TargetJumpTable)) 1077 return SDValue(); 1078 1079 EVT ValTy = N->getValueType(0); 1080 SDLoc DL(N); 1081 1082 SDValue Add1 = DAG.getNode(ISD::ADD, DL, ValTy, N->getOperand(0), 1083 Add.getOperand(0)); 1084 return DAG.getNode(ISD::ADD, DL, ValTy, Add1, Lo); 1085 } 1086 1087 static SDValue performSHLCombine(SDNode *N, SelectionDAG &DAG, 1088 TargetLowering::DAGCombinerInfo &DCI, 1089 const MipsSubtarget &Subtarget) { 1090 // Pattern match CINS. 1091 // $dst = shl (and $src , imm), pos 1092 // => cins $dst, $src, pos, size 1093 1094 if (DCI.isBeforeLegalizeOps() || !Subtarget.hasCnMips()) 1095 return SDValue(); 1096 1097 SDValue FirstOperand = N->getOperand(0); 1098 unsigned FirstOperandOpc = FirstOperand.getOpcode(); 1099 SDValue SecondOperand = N->getOperand(1); 1100 EVT ValTy = N->getValueType(0); 1101 SDLoc DL(N); 1102 1103 uint64_t Pos = 0; 1104 unsigned SMPos, SMSize; 1105 ConstantSDNode *CN; 1106 SDValue NewOperand; 1107 1108 // The second operand of the shift must be an immediate. 1109 if (!(CN = dyn_cast<ConstantSDNode>(SecondOperand))) 1110 return SDValue(); 1111 1112 Pos = CN->getZExtValue(); 1113 1114 if (Pos >= ValTy.getSizeInBits()) 1115 return SDValue(); 1116 1117 if (FirstOperandOpc != ISD::AND) 1118 return SDValue(); 1119 1120 // AND's second operand must be a shifted mask. 1121 if (!(CN = dyn_cast<ConstantSDNode>(FirstOperand.getOperand(1))) || 1122 !isShiftedMask_64(CN->getZExtValue(), SMPos, SMSize)) 1123 return SDValue(); 1124 1125 // Return if the shifted mask does not start at bit 0 or the sum of its size 1126 // and Pos exceeds the word's size. 1127 if (SMPos != 0 || SMSize > 32 || Pos + SMSize > ValTy.getSizeInBits()) 1128 return SDValue(); 1129 1130 NewOperand = FirstOperand.getOperand(0); 1131 // SMSize is 'location' (position) in this case, not size. 1132 SMSize--; 1133 1134 return DAG.getNode(MipsISD::CIns, DL, ValTy, NewOperand, 1135 DAG.getConstant(Pos, DL, MVT::i32), 1136 DAG.getConstant(SMSize, DL, MVT::i32)); 1137 } 1138 1139 SDValue MipsTargetLowering::PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) 1140 const { 1141 SelectionDAG &DAG = DCI.DAG; 1142 unsigned Opc = N->getOpcode(); 1143 1144 switch (Opc) { 1145 default: break; 1146 case ISD::SDIVREM: 1147 case ISD::UDIVREM: 1148 return performDivRemCombine(N, DAG, DCI, Subtarget); 1149 case ISD::SELECT: 1150 return performSELECTCombine(N, DAG, DCI, Subtarget); 1151 case MipsISD::CMovFP_F: 1152 case MipsISD::CMovFP_T: 1153 return performCMovFPCombine(N, DAG, DCI, Subtarget); 1154 case ISD::AND: 1155 return performANDCombine(N, DAG, DCI, Subtarget); 1156 case ISD::OR: 1157 return performORCombine(N, DAG, DCI, Subtarget); 1158 case ISD::ADD: 1159 return performADDCombine(N, DAG, DCI, Subtarget); 1160 case ISD::SHL: 1161 return performSHLCombine(N, DAG, DCI, Subtarget); 1162 case ISD::SUB: 1163 return performSUBCombine(N, DAG, DCI, Subtarget); 1164 } 1165 1166 return SDValue(); 1167 } 1168 1169 bool MipsTargetLowering::isCheapToSpeculateCttz() const { 1170 return Subtarget.hasMips32(); 1171 } 1172 1173 bool MipsTargetLowering::isCheapToSpeculateCtlz() const { 1174 return Subtarget.hasMips32(); 1175 } 1176 1177 bool MipsTargetLowering::hasBitTest(SDValue X, SDValue Y) const { 1178 // We can use ANDI+SLTIU as a bit test. Y contains the bit position. 1179 // For MIPSR2 or later, we may be able to use the `ext` instruction or its' 1180 // double-word variants. 1181 if (auto *C = dyn_cast<ConstantSDNode>(Y)) 1182 return C->getAPIntValue().ule(15); 1183 1184 return false; 1185 } 1186 1187 bool MipsTargetLowering::shouldFoldConstantShiftPairToMask( 1188 const SDNode *N, CombineLevel Level) const { 1189 if (N->getOperand(0).getValueType().isVector()) 1190 return false; 1191 return true; 1192 } 1193 1194 void 1195 MipsTargetLowering::ReplaceNodeResults(SDNode *N, 1196 SmallVectorImpl<SDValue> &Results, 1197 SelectionDAG &DAG) const { 1198 return LowerOperationWrapper(N, Results, DAG); 1199 } 1200 1201 SDValue MipsTargetLowering:: 1202 LowerOperation(SDValue Op, SelectionDAG &DAG) const 1203 { 1204 switch (Op.getOpcode()) 1205 { 1206 case ISD::BRCOND: return lowerBRCOND(Op, DAG); 1207 case ISD::ConstantPool: return lowerConstantPool(Op, DAG); 1208 case ISD::GlobalAddress: return lowerGlobalAddress(Op, DAG); 1209 case ISD::BlockAddress: return lowerBlockAddress(Op, DAG); 1210 case ISD::GlobalTLSAddress: return lowerGlobalTLSAddress(Op, DAG); 1211 case ISD::JumpTable: return lowerJumpTable(Op, DAG); 1212 case ISD::SELECT: return lowerSELECT(Op, DAG); 1213 case ISD::SETCC: return lowerSETCC(Op, DAG); 1214 case ISD::VASTART: return lowerVASTART(Op, DAG); 1215 case ISD::VAARG: return lowerVAARG(Op, DAG); 1216 case ISD::FCOPYSIGN: return lowerFCOPYSIGN(Op, DAG); 1217 case ISD::FABS: return lowerFABS(Op, DAG); 1218 case ISD::FRAMEADDR: return lowerFRAMEADDR(Op, DAG); 1219 case ISD::RETURNADDR: return lowerRETURNADDR(Op, DAG); 1220 case ISD::EH_RETURN: return lowerEH_RETURN(Op, DAG); 1221 case ISD::ATOMIC_FENCE: return lowerATOMIC_FENCE(Op, DAG); 1222 case ISD::SHL_PARTS: return lowerShiftLeftParts(Op, DAG); 1223 case ISD::SRA_PARTS: return lowerShiftRightParts(Op, DAG, true); 1224 case ISD::SRL_PARTS: return lowerShiftRightParts(Op, DAG, false); 1225 case ISD::LOAD: return lowerLOAD(Op, DAG); 1226 case ISD::STORE: return lowerSTORE(Op, DAG); 1227 case ISD::EH_DWARF_CFA: return lowerEH_DWARF_CFA(Op, DAG); 1228 case ISD::FP_TO_SINT: return lowerFP_TO_SINT(Op, DAG); 1229 } 1230 return SDValue(); 1231 } 1232 1233 //===----------------------------------------------------------------------===// 1234 // Lower helper functions 1235 //===----------------------------------------------------------------------===// 1236 1237 // addLiveIn - This helper function adds the specified physical register to the 1238 // MachineFunction as a live in value. It also creates a corresponding 1239 // virtual register for it. 1240 static unsigned 1241 addLiveIn(MachineFunction &MF, unsigned PReg, const TargetRegisterClass *RC) 1242 { 1243 Register VReg = MF.getRegInfo().createVirtualRegister(RC); 1244 MF.getRegInfo().addLiveIn(PReg, VReg); 1245 return VReg; 1246 } 1247 1248 static MachineBasicBlock *insertDivByZeroTrap(MachineInstr &MI, 1249 MachineBasicBlock &MBB, 1250 const TargetInstrInfo &TII, 1251 bool Is64Bit, bool IsMicroMips) { 1252 if (NoZeroDivCheck) 1253 return &MBB; 1254 1255 // Insert instruction "teq $divisor_reg, $zero, 7". 1256 MachineBasicBlock::iterator I(MI); 1257 MachineInstrBuilder MIB; 1258 MachineOperand &Divisor = MI.getOperand(2); 1259 MIB = BuildMI(MBB, std::next(I), MI.getDebugLoc(), 1260 TII.get(IsMicroMips ? Mips::TEQ_MM : Mips::TEQ)) 1261 .addReg(Divisor.getReg(), getKillRegState(Divisor.isKill())) 1262 .addReg(Mips::ZERO) 1263 .addImm(7); 1264 1265 // Use the 32-bit sub-register if this is a 64-bit division. 1266 if (Is64Bit) 1267 MIB->getOperand(0).setSubReg(Mips::sub_32); 1268 1269 // Clear Divisor's kill flag. 1270 Divisor.setIsKill(false); 1271 1272 // We would normally delete the original instruction here but in this case 1273 // we only needed to inject an additional instruction rather than replace it. 1274 1275 return &MBB; 1276 } 1277 1278 MachineBasicBlock * 1279 MipsTargetLowering::EmitInstrWithCustomInserter(MachineInstr &MI, 1280 MachineBasicBlock *BB) const { 1281 switch (MI.getOpcode()) { 1282 default: 1283 llvm_unreachable("Unexpected instr type to insert"); 1284 case Mips::ATOMIC_LOAD_ADD_I8: 1285 return emitAtomicBinaryPartword(MI, BB, 1); 1286 case Mips::ATOMIC_LOAD_ADD_I16: 1287 return emitAtomicBinaryPartword(MI, BB, 2); 1288 case Mips::ATOMIC_LOAD_ADD_I32: 1289 return emitAtomicBinary(MI, BB); 1290 case Mips::ATOMIC_LOAD_ADD_I64: 1291 return emitAtomicBinary(MI, BB); 1292 1293 case Mips::ATOMIC_LOAD_AND_I8: 1294 return emitAtomicBinaryPartword(MI, BB, 1); 1295 case Mips::ATOMIC_LOAD_AND_I16: 1296 return emitAtomicBinaryPartword(MI, BB, 2); 1297 case Mips::ATOMIC_LOAD_AND_I32: 1298 return emitAtomicBinary(MI, BB); 1299 case Mips::ATOMIC_LOAD_AND_I64: 1300 return emitAtomicBinary(MI, BB); 1301 1302 case Mips::ATOMIC_LOAD_OR_I8: 1303 return emitAtomicBinaryPartword(MI, BB, 1); 1304 case Mips::ATOMIC_LOAD_OR_I16: 1305 return emitAtomicBinaryPartword(MI, BB, 2); 1306 case Mips::ATOMIC_LOAD_OR_I32: 1307 return emitAtomicBinary(MI, BB); 1308 case Mips::ATOMIC_LOAD_OR_I64: 1309 return emitAtomicBinary(MI, BB); 1310 1311 case Mips::ATOMIC_LOAD_XOR_I8: 1312 return emitAtomicBinaryPartword(MI, BB, 1); 1313 case Mips::ATOMIC_LOAD_XOR_I16: 1314 return emitAtomicBinaryPartword(MI, BB, 2); 1315 case Mips::ATOMIC_LOAD_XOR_I32: 1316 return emitAtomicBinary(MI, BB); 1317 case Mips::ATOMIC_LOAD_XOR_I64: 1318 return emitAtomicBinary(MI, BB); 1319 1320 case Mips::ATOMIC_LOAD_NAND_I8: 1321 return emitAtomicBinaryPartword(MI, BB, 1); 1322 case Mips::ATOMIC_LOAD_NAND_I16: 1323 return emitAtomicBinaryPartword(MI, BB, 2); 1324 case Mips::ATOMIC_LOAD_NAND_I32: 1325 return emitAtomicBinary(MI, BB); 1326 case Mips::ATOMIC_LOAD_NAND_I64: 1327 return emitAtomicBinary(MI, BB); 1328 1329 case Mips::ATOMIC_LOAD_SUB_I8: 1330 return emitAtomicBinaryPartword(MI, BB, 1); 1331 case Mips::ATOMIC_LOAD_SUB_I16: 1332 return emitAtomicBinaryPartword(MI, BB, 2); 1333 case Mips::ATOMIC_LOAD_SUB_I32: 1334 return emitAtomicBinary(MI, BB); 1335 case Mips::ATOMIC_LOAD_SUB_I64: 1336 return emitAtomicBinary(MI, BB); 1337 1338 case Mips::ATOMIC_SWAP_I8: 1339 return emitAtomicBinaryPartword(MI, BB, 1); 1340 case Mips::ATOMIC_SWAP_I16: 1341 return emitAtomicBinaryPartword(MI, BB, 2); 1342 case Mips::ATOMIC_SWAP_I32: 1343 return emitAtomicBinary(MI, BB); 1344 case Mips::ATOMIC_SWAP_I64: 1345 return emitAtomicBinary(MI, BB); 1346 1347 case Mips::ATOMIC_CMP_SWAP_I8: 1348 return emitAtomicCmpSwapPartword(MI, BB, 1); 1349 case Mips::ATOMIC_CMP_SWAP_I16: 1350 return emitAtomicCmpSwapPartword(MI, BB, 2); 1351 case Mips::ATOMIC_CMP_SWAP_I32: 1352 return emitAtomicCmpSwap(MI, BB); 1353 case Mips::ATOMIC_CMP_SWAP_I64: 1354 return emitAtomicCmpSwap(MI, BB); 1355 1356 case Mips::ATOMIC_LOAD_MIN_I8: 1357 return emitAtomicBinaryPartword(MI, BB, 1); 1358 case Mips::ATOMIC_LOAD_MIN_I16: 1359 return emitAtomicBinaryPartword(MI, BB, 2); 1360 case Mips::ATOMIC_LOAD_MIN_I32: 1361 return emitAtomicBinary(MI, BB); 1362 case Mips::ATOMIC_LOAD_MIN_I64: 1363 return emitAtomicBinary(MI, BB); 1364 1365 case Mips::ATOMIC_LOAD_MAX_I8: 1366 return emitAtomicBinaryPartword(MI, BB, 1); 1367 case Mips::ATOMIC_LOAD_MAX_I16: 1368 return emitAtomicBinaryPartword(MI, BB, 2); 1369 case Mips::ATOMIC_LOAD_MAX_I32: 1370 return emitAtomicBinary(MI, BB); 1371 case Mips::ATOMIC_LOAD_MAX_I64: 1372 return emitAtomicBinary(MI, BB); 1373 1374 case Mips::ATOMIC_LOAD_UMIN_I8: 1375 return emitAtomicBinaryPartword(MI, BB, 1); 1376 case Mips::ATOMIC_LOAD_UMIN_I16: 1377 return emitAtomicBinaryPartword(MI, BB, 2); 1378 case Mips::ATOMIC_LOAD_UMIN_I32: 1379 return emitAtomicBinary(MI, BB); 1380 case Mips::ATOMIC_LOAD_UMIN_I64: 1381 return emitAtomicBinary(MI, BB); 1382 1383 case Mips::ATOMIC_LOAD_UMAX_I8: 1384 return emitAtomicBinaryPartword(MI, BB, 1); 1385 case Mips::ATOMIC_LOAD_UMAX_I16: 1386 return emitAtomicBinaryPartword(MI, BB, 2); 1387 case Mips::ATOMIC_LOAD_UMAX_I32: 1388 return emitAtomicBinary(MI, BB); 1389 case Mips::ATOMIC_LOAD_UMAX_I64: 1390 return emitAtomicBinary(MI, BB); 1391 1392 case Mips::PseudoSDIV: 1393 case Mips::PseudoUDIV: 1394 case Mips::DIV: 1395 case Mips::DIVU: 1396 case Mips::MOD: 1397 case Mips::MODU: 1398 return insertDivByZeroTrap(MI, *BB, *Subtarget.getInstrInfo(), false, 1399 false); 1400 case Mips::SDIV_MM_Pseudo: 1401 case Mips::UDIV_MM_Pseudo: 1402 case Mips::SDIV_MM: 1403 case Mips::UDIV_MM: 1404 case Mips::DIV_MMR6: 1405 case Mips::DIVU_MMR6: 1406 case Mips::MOD_MMR6: 1407 case Mips::MODU_MMR6: 1408 return insertDivByZeroTrap(MI, *BB, *Subtarget.getInstrInfo(), false, true); 1409 case Mips::PseudoDSDIV: 1410 case Mips::PseudoDUDIV: 1411 case Mips::DDIV: 1412 case Mips::DDIVU: 1413 case Mips::DMOD: 1414 case Mips::DMODU: 1415 return insertDivByZeroTrap(MI, *BB, *Subtarget.getInstrInfo(), true, false); 1416 1417 case Mips::PseudoSELECT_I: 1418 case Mips::PseudoSELECT_I64: 1419 case Mips::PseudoSELECT_S: 1420 case Mips::PseudoSELECT_D32: 1421 case Mips::PseudoSELECT_D64: 1422 return emitPseudoSELECT(MI, BB, false, Mips::BNE); 1423 case Mips::PseudoSELECTFP_F_I: 1424 case Mips::PseudoSELECTFP_F_I64: 1425 case Mips::PseudoSELECTFP_F_S: 1426 case Mips::PseudoSELECTFP_F_D32: 1427 case Mips::PseudoSELECTFP_F_D64: 1428 return emitPseudoSELECT(MI, BB, true, Mips::BC1F); 1429 case Mips::PseudoSELECTFP_T_I: 1430 case Mips::PseudoSELECTFP_T_I64: 1431 case Mips::PseudoSELECTFP_T_S: 1432 case Mips::PseudoSELECTFP_T_D32: 1433 case Mips::PseudoSELECTFP_T_D64: 1434 return emitPseudoSELECT(MI, BB, true, Mips::BC1T); 1435 case Mips::PseudoD_SELECT_I: 1436 case Mips::PseudoD_SELECT_I64: 1437 return emitPseudoD_SELECT(MI, BB); 1438 case Mips::LDR_W: 1439 return emitLDR_W(MI, BB); 1440 case Mips::LDR_D: 1441 return emitLDR_D(MI, BB); 1442 case Mips::STR_W: 1443 return emitSTR_W(MI, BB); 1444 case Mips::STR_D: 1445 return emitSTR_D(MI, BB); 1446 } 1447 } 1448 1449 // This function also handles Mips::ATOMIC_SWAP_I32 (when BinOpcode == 0), and 1450 // Mips::ATOMIC_LOAD_NAND_I32 (when Nand == true) 1451 MachineBasicBlock * 1452 MipsTargetLowering::emitAtomicBinary(MachineInstr &MI, 1453 MachineBasicBlock *BB) const { 1454 1455 MachineFunction *MF = BB->getParent(); 1456 MachineRegisterInfo &RegInfo = MF->getRegInfo(); 1457 const TargetInstrInfo *TII = Subtarget.getInstrInfo(); 1458 DebugLoc DL = MI.getDebugLoc(); 1459 1460 unsigned AtomicOp; 1461 bool NeedsAdditionalReg = false; 1462 switch (MI.getOpcode()) { 1463 case Mips::ATOMIC_LOAD_ADD_I32: 1464 AtomicOp = Mips::ATOMIC_LOAD_ADD_I32_POSTRA; 1465 break; 1466 case Mips::ATOMIC_LOAD_SUB_I32: 1467 AtomicOp = Mips::ATOMIC_LOAD_SUB_I32_POSTRA; 1468 break; 1469 case Mips::ATOMIC_LOAD_AND_I32: 1470 AtomicOp = Mips::ATOMIC_LOAD_AND_I32_POSTRA; 1471 break; 1472 case Mips::ATOMIC_LOAD_OR_I32: 1473 AtomicOp = Mips::ATOMIC_LOAD_OR_I32_POSTRA; 1474 break; 1475 case Mips::ATOMIC_LOAD_XOR_I32: 1476 AtomicOp = Mips::ATOMIC_LOAD_XOR_I32_POSTRA; 1477 break; 1478 case Mips::ATOMIC_LOAD_NAND_I32: 1479 AtomicOp = Mips::ATOMIC_LOAD_NAND_I32_POSTRA; 1480 break; 1481 case Mips::ATOMIC_SWAP_I32: 1482 AtomicOp = Mips::ATOMIC_SWAP_I32_POSTRA; 1483 break; 1484 case Mips::ATOMIC_LOAD_ADD_I64: 1485 AtomicOp = Mips::ATOMIC_LOAD_ADD_I64_POSTRA; 1486 break; 1487 case Mips::ATOMIC_LOAD_SUB_I64: 1488 AtomicOp = Mips::ATOMIC_LOAD_SUB_I64_POSTRA; 1489 break; 1490 case Mips::ATOMIC_LOAD_AND_I64: 1491 AtomicOp = Mips::ATOMIC_LOAD_AND_I64_POSTRA; 1492 break; 1493 case Mips::ATOMIC_LOAD_OR_I64: 1494 AtomicOp = Mips::ATOMIC_LOAD_OR_I64_POSTRA; 1495 break; 1496 case Mips::ATOMIC_LOAD_XOR_I64: 1497 AtomicOp = Mips::ATOMIC_LOAD_XOR_I64_POSTRA; 1498 break; 1499 case Mips::ATOMIC_LOAD_NAND_I64: 1500 AtomicOp = Mips::ATOMIC_LOAD_NAND_I64_POSTRA; 1501 break; 1502 case Mips::ATOMIC_SWAP_I64: 1503 AtomicOp = Mips::ATOMIC_SWAP_I64_POSTRA; 1504 break; 1505 case Mips::ATOMIC_LOAD_MIN_I32: 1506 AtomicOp = Mips::ATOMIC_LOAD_MIN_I32_POSTRA; 1507 NeedsAdditionalReg = true; 1508 break; 1509 case Mips::ATOMIC_LOAD_MAX_I32: 1510 AtomicOp = Mips::ATOMIC_LOAD_MAX_I32_POSTRA; 1511 NeedsAdditionalReg = true; 1512 break; 1513 case Mips::ATOMIC_LOAD_UMIN_I32: 1514 AtomicOp = Mips::ATOMIC_LOAD_UMIN_I32_POSTRA; 1515 NeedsAdditionalReg = true; 1516 break; 1517 case Mips::ATOMIC_LOAD_UMAX_I32: 1518 AtomicOp = Mips::ATOMIC_LOAD_UMAX_I32_POSTRA; 1519 NeedsAdditionalReg = true; 1520 break; 1521 case Mips::ATOMIC_LOAD_MIN_I64: 1522 AtomicOp = Mips::ATOMIC_LOAD_MIN_I64_POSTRA; 1523 NeedsAdditionalReg = true; 1524 break; 1525 case Mips::ATOMIC_LOAD_MAX_I64: 1526 AtomicOp = Mips::ATOMIC_LOAD_MAX_I64_POSTRA; 1527 NeedsAdditionalReg = true; 1528 break; 1529 case Mips::ATOMIC_LOAD_UMIN_I64: 1530 AtomicOp = Mips::ATOMIC_LOAD_UMIN_I64_POSTRA; 1531 NeedsAdditionalReg = true; 1532 break; 1533 case Mips::ATOMIC_LOAD_UMAX_I64: 1534 AtomicOp = Mips::ATOMIC_LOAD_UMAX_I64_POSTRA; 1535 NeedsAdditionalReg = true; 1536 break; 1537 default: 1538 llvm_unreachable("Unknown pseudo atomic for replacement!"); 1539 } 1540 1541 Register OldVal = MI.getOperand(0).getReg(); 1542 Register Ptr = MI.getOperand(1).getReg(); 1543 Register Incr = MI.getOperand(2).getReg(); 1544 Register Scratch = RegInfo.createVirtualRegister(RegInfo.getRegClass(OldVal)); 1545 1546 MachineBasicBlock::iterator II(MI); 1547 1548 // The scratch registers here with the EarlyClobber | Define | Implicit 1549 // flags is used to persuade the register allocator and the machine 1550 // verifier to accept the usage of this register. This has to be a real 1551 // register which has an UNDEF value but is dead after the instruction which 1552 // is unique among the registers chosen for the instruction. 1553 1554 // The EarlyClobber flag has the semantic properties that the operand it is 1555 // attached to is clobbered before the rest of the inputs are read. Hence it 1556 // must be unique among the operands to the instruction. 1557 // The Define flag is needed to coerce the machine verifier that an Undef 1558 // value isn't a problem. 1559 // The Dead flag is needed as the value in scratch isn't used by any other 1560 // instruction. Kill isn't used as Dead is more precise. 1561 // The implicit flag is here due to the interaction between the other flags 1562 // and the machine verifier. 1563 1564 // For correctness purpose, a new pseudo is introduced here. We need this 1565 // new pseudo, so that FastRegisterAllocator does not see an ll/sc sequence 1566 // that is spread over >1 basic blocks. A register allocator which 1567 // introduces (or any codegen infact) a store, can violate the expectations 1568 // of the hardware. 1569 // 1570 // An atomic read-modify-write sequence starts with a linked load 1571 // instruction and ends with a store conditional instruction. The atomic 1572 // read-modify-write sequence fails if any of the following conditions 1573 // occur between the execution of ll and sc: 1574 // * A coherent store is completed by another process or coherent I/O 1575 // module into the block of synchronizable physical memory containing 1576 // the word. The size and alignment of the block is 1577 // implementation-dependent. 1578 // * A coherent store is executed between an LL and SC sequence on the 1579 // same processor to the block of synchornizable physical memory 1580 // containing the word. 1581 // 1582 1583 Register PtrCopy = RegInfo.createVirtualRegister(RegInfo.getRegClass(Ptr)); 1584 Register IncrCopy = RegInfo.createVirtualRegister(RegInfo.getRegClass(Incr)); 1585 1586 BuildMI(*BB, II, DL, TII->get(Mips::COPY), IncrCopy).addReg(Incr); 1587 BuildMI(*BB, II, DL, TII->get(Mips::COPY), PtrCopy).addReg(Ptr); 1588 1589 MachineInstrBuilder MIB = 1590 BuildMI(*BB, II, DL, TII->get(AtomicOp)) 1591 .addReg(OldVal, RegState::Define | RegState::EarlyClobber) 1592 .addReg(PtrCopy) 1593 .addReg(IncrCopy) 1594 .addReg(Scratch, RegState::Define | RegState::EarlyClobber | 1595 RegState::Implicit | RegState::Dead); 1596 if (NeedsAdditionalReg) { 1597 Register Scratch2 = 1598 RegInfo.createVirtualRegister(RegInfo.getRegClass(OldVal)); 1599 MIB.addReg(Scratch2, RegState::Define | RegState::EarlyClobber | 1600 RegState::Implicit | RegState::Dead); 1601 } 1602 1603 MI.eraseFromParent(); 1604 1605 return BB; 1606 } 1607 1608 MachineBasicBlock *MipsTargetLowering::emitSignExtendToI32InReg( 1609 MachineInstr &MI, MachineBasicBlock *BB, unsigned Size, unsigned DstReg, 1610 unsigned SrcReg) const { 1611 const TargetInstrInfo *TII = Subtarget.getInstrInfo(); 1612 const DebugLoc &DL = MI.getDebugLoc(); 1613 1614 if (Subtarget.hasMips32r2() && Size == 1) { 1615 BuildMI(BB, DL, TII->get(Mips::SEB), DstReg).addReg(SrcReg); 1616 return BB; 1617 } 1618 1619 if (Subtarget.hasMips32r2() && Size == 2) { 1620 BuildMI(BB, DL, TII->get(Mips::SEH), DstReg).addReg(SrcReg); 1621 return BB; 1622 } 1623 1624 MachineFunction *MF = BB->getParent(); 1625 MachineRegisterInfo &RegInfo = MF->getRegInfo(); 1626 const TargetRegisterClass *RC = getRegClassFor(MVT::i32); 1627 Register ScrReg = RegInfo.createVirtualRegister(RC); 1628 1629 assert(Size < 32); 1630 int64_t ShiftImm = 32 - (Size * 8); 1631 1632 BuildMI(BB, DL, TII->get(Mips::SLL), ScrReg).addReg(SrcReg).addImm(ShiftImm); 1633 BuildMI(BB, DL, TII->get(Mips::SRA), DstReg).addReg(ScrReg).addImm(ShiftImm); 1634 1635 return BB; 1636 } 1637 1638 MachineBasicBlock *MipsTargetLowering::emitAtomicBinaryPartword( 1639 MachineInstr &MI, MachineBasicBlock *BB, unsigned Size) const { 1640 assert((Size == 1 || Size == 2) && 1641 "Unsupported size for EmitAtomicBinaryPartial."); 1642 1643 MachineFunction *MF = BB->getParent(); 1644 MachineRegisterInfo &RegInfo = MF->getRegInfo(); 1645 const TargetRegisterClass *RC = getRegClassFor(MVT::i32); 1646 const bool ArePtrs64bit = ABI.ArePtrs64bit(); 1647 const TargetRegisterClass *RCp = 1648 getRegClassFor(ArePtrs64bit ? MVT::i64 : MVT::i32); 1649 const TargetInstrInfo *TII = Subtarget.getInstrInfo(); 1650 DebugLoc DL = MI.getDebugLoc(); 1651 1652 Register Dest = MI.getOperand(0).getReg(); 1653 Register Ptr = MI.getOperand(1).getReg(); 1654 Register Incr = MI.getOperand(2).getReg(); 1655 1656 Register AlignedAddr = RegInfo.createVirtualRegister(RCp); 1657 Register ShiftAmt = RegInfo.createVirtualRegister(RC); 1658 Register Mask = RegInfo.createVirtualRegister(RC); 1659 Register Mask2 = RegInfo.createVirtualRegister(RC); 1660 Register Incr2 = RegInfo.createVirtualRegister(RC); 1661 Register MaskLSB2 = RegInfo.createVirtualRegister(RCp); 1662 Register PtrLSB2 = RegInfo.createVirtualRegister(RC); 1663 Register MaskUpper = RegInfo.createVirtualRegister(RC); 1664 Register Scratch = RegInfo.createVirtualRegister(RC); 1665 Register Scratch2 = RegInfo.createVirtualRegister(RC); 1666 Register Scratch3 = RegInfo.createVirtualRegister(RC); 1667 1668 unsigned AtomicOp = 0; 1669 bool NeedsAdditionalReg = false; 1670 switch (MI.getOpcode()) { 1671 case Mips::ATOMIC_LOAD_NAND_I8: 1672 AtomicOp = Mips::ATOMIC_LOAD_NAND_I8_POSTRA; 1673 break; 1674 case Mips::ATOMIC_LOAD_NAND_I16: 1675 AtomicOp = Mips::ATOMIC_LOAD_NAND_I16_POSTRA; 1676 break; 1677 case Mips::ATOMIC_SWAP_I8: 1678 AtomicOp = Mips::ATOMIC_SWAP_I8_POSTRA; 1679 break; 1680 case Mips::ATOMIC_SWAP_I16: 1681 AtomicOp = Mips::ATOMIC_SWAP_I16_POSTRA; 1682 break; 1683 case Mips::ATOMIC_LOAD_ADD_I8: 1684 AtomicOp = Mips::ATOMIC_LOAD_ADD_I8_POSTRA; 1685 break; 1686 case Mips::ATOMIC_LOAD_ADD_I16: 1687 AtomicOp = Mips::ATOMIC_LOAD_ADD_I16_POSTRA; 1688 break; 1689 case Mips::ATOMIC_LOAD_SUB_I8: 1690 AtomicOp = Mips::ATOMIC_LOAD_SUB_I8_POSTRA; 1691 break; 1692 case Mips::ATOMIC_LOAD_SUB_I16: 1693 AtomicOp = Mips::ATOMIC_LOAD_SUB_I16_POSTRA; 1694 break; 1695 case Mips::ATOMIC_LOAD_AND_I8: 1696 AtomicOp = Mips::ATOMIC_LOAD_AND_I8_POSTRA; 1697 break; 1698 case Mips::ATOMIC_LOAD_AND_I16: 1699 AtomicOp = Mips::ATOMIC_LOAD_AND_I16_POSTRA; 1700 break; 1701 case Mips::ATOMIC_LOAD_OR_I8: 1702 AtomicOp = Mips::ATOMIC_LOAD_OR_I8_POSTRA; 1703 break; 1704 case Mips::ATOMIC_LOAD_OR_I16: 1705 AtomicOp = Mips::ATOMIC_LOAD_OR_I16_POSTRA; 1706 break; 1707 case Mips::ATOMIC_LOAD_XOR_I8: 1708 AtomicOp = Mips::ATOMIC_LOAD_XOR_I8_POSTRA; 1709 break; 1710 case Mips::ATOMIC_LOAD_XOR_I16: 1711 AtomicOp = Mips::ATOMIC_LOAD_XOR_I16_POSTRA; 1712 break; 1713 case Mips::ATOMIC_LOAD_MIN_I8: 1714 AtomicOp = Mips::ATOMIC_LOAD_MIN_I8_POSTRA; 1715 NeedsAdditionalReg = true; 1716 break; 1717 case Mips::ATOMIC_LOAD_MIN_I16: 1718 AtomicOp = Mips::ATOMIC_LOAD_MIN_I16_POSTRA; 1719 NeedsAdditionalReg = true; 1720 break; 1721 case Mips::ATOMIC_LOAD_MAX_I8: 1722 AtomicOp = Mips::ATOMIC_LOAD_MAX_I8_POSTRA; 1723 NeedsAdditionalReg = true; 1724 break; 1725 case Mips::ATOMIC_LOAD_MAX_I16: 1726 AtomicOp = Mips::ATOMIC_LOAD_MAX_I16_POSTRA; 1727 NeedsAdditionalReg = true; 1728 break; 1729 case Mips::ATOMIC_LOAD_UMIN_I8: 1730 AtomicOp = Mips::ATOMIC_LOAD_UMIN_I8_POSTRA; 1731 NeedsAdditionalReg = true; 1732 break; 1733 case Mips::ATOMIC_LOAD_UMIN_I16: 1734 AtomicOp = Mips::ATOMIC_LOAD_UMIN_I16_POSTRA; 1735 NeedsAdditionalReg = true; 1736 break; 1737 case Mips::ATOMIC_LOAD_UMAX_I8: 1738 AtomicOp = Mips::ATOMIC_LOAD_UMAX_I8_POSTRA; 1739 NeedsAdditionalReg = true; 1740 break; 1741 case Mips::ATOMIC_LOAD_UMAX_I16: 1742 AtomicOp = Mips::ATOMIC_LOAD_UMAX_I16_POSTRA; 1743 NeedsAdditionalReg = true; 1744 break; 1745 default: 1746 llvm_unreachable("Unknown subword atomic pseudo for expansion!"); 1747 } 1748 1749 // insert new blocks after the current block 1750 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 1751 MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB); 1752 MachineFunction::iterator It = ++BB->getIterator(); 1753 MF->insert(It, exitMBB); 1754 1755 // Transfer the remainder of BB and its successor edges to exitMBB. 1756 exitMBB->splice(exitMBB->begin(), BB, 1757 std::next(MachineBasicBlock::iterator(MI)), BB->end()); 1758 exitMBB->transferSuccessorsAndUpdatePHIs(BB); 1759 1760 BB->addSuccessor(exitMBB, BranchProbability::getOne()); 1761 1762 // thisMBB: 1763 // addiu masklsb2,$0,-4 # 0xfffffffc 1764 // and alignedaddr,ptr,masklsb2 1765 // andi ptrlsb2,ptr,3 1766 // sll shiftamt,ptrlsb2,3 1767 // ori maskupper,$0,255 # 0xff 1768 // sll mask,maskupper,shiftamt 1769 // nor mask2,$0,mask 1770 // sll incr2,incr,shiftamt 1771 1772 int64_t MaskImm = (Size == 1) ? 255 : 65535; 1773 BuildMI(BB, DL, TII->get(ABI.GetPtrAddiuOp()), MaskLSB2) 1774 .addReg(ABI.GetNullPtr()).addImm(-4); 1775 BuildMI(BB, DL, TII->get(ABI.GetPtrAndOp()), AlignedAddr) 1776 .addReg(Ptr).addReg(MaskLSB2); 1777 BuildMI(BB, DL, TII->get(Mips::ANDi), PtrLSB2) 1778 .addReg(Ptr, 0, ArePtrs64bit ? Mips::sub_32 : 0).addImm(3); 1779 if (Subtarget.isLittle()) { 1780 BuildMI(BB, DL, TII->get(Mips::SLL), ShiftAmt).addReg(PtrLSB2).addImm(3); 1781 } else { 1782 Register Off = RegInfo.createVirtualRegister(RC); 1783 BuildMI(BB, DL, TII->get(Mips::XORi), Off) 1784 .addReg(PtrLSB2).addImm((Size == 1) ? 3 : 2); 1785 BuildMI(BB, DL, TII->get(Mips::SLL), ShiftAmt).addReg(Off).addImm(3); 1786 } 1787 BuildMI(BB, DL, TII->get(Mips::ORi), MaskUpper) 1788 .addReg(Mips::ZERO).addImm(MaskImm); 1789 BuildMI(BB, DL, TII->get(Mips::SLLV), Mask) 1790 .addReg(MaskUpper).addReg(ShiftAmt); 1791 BuildMI(BB, DL, TII->get(Mips::NOR), Mask2).addReg(Mips::ZERO).addReg(Mask); 1792 BuildMI(BB, DL, TII->get(Mips::SLLV), Incr2).addReg(Incr).addReg(ShiftAmt); 1793 1794 1795 // The purposes of the flags on the scratch registers is explained in 1796 // emitAtomicBinary. In summary, we need a scratch register which is going to 1797 // be undef, that is unique among registers chosen for the instruction. 1798 1799 MachineInstrBuilder MIB = 1800 BuildMI(BB, DL, TII->get(AtomicOp)) 1801 .addReg(Dest, RegState::Define | RegState::EarlyClobber) 1802 .addReg(AlignedAddr) 1803 .addReg(Incr2) 1804 .addReg(Mask) 1805 .addReg(Mask2) 1806 .addReg(ShiftAmt) 1807 .addReg(Scratch, RegState::EarlyClobber | RegState::Define | 1808 RegState::Dead | RegState::Implicit) 1809 .addReg(Scratch2, RegState::EarlyClobber | RegState::Define | 1810 RegState::Dead | RegState::Implicit) 1811 .addReg(Scratch3, RegState::EarlyClobber | RegState::Define | 1812 RegState::Dead | RegState::Implicit); 1813 if (NeedsAdditionalReg) { 1814 Register Scratch4 = RegInfo.createVirtualRegister(RC); 1815 MIB.addReg(Scratch4, RegState::EarlyClobber | RegState::Define | 1816 RegState::Dead | RegState::Implicit); 1817 } 1818 1819 MI.eraseFromParent(); // The instruction is gone now. 1820 1821 return exitMBB; 1822 } 1823 1824 // Lower atomic compare and swap to a pseudo instruction, taking care to 1825 // define a scratch register for the pseudo instruction's expansion. The 1826 // instruction is expanded after the register allocator as to prevent 1827 // the insertion of stores between the linked load and the store conditional. 1828 1829 MachineBasicBlock * 1830 MipsTargetLowering::emitAtomicCmpSwap(MachineInstr &MI, 1831 MachineBasicBlock *BB) const { 1832 1833 assert((MI.getOpcode() == Mips::ATOMIC_CMP_SWAP_I32 || 1834 MI.getOpcode() == Mips::ATOMIC_CMP_SWAP_I64) && 1835 "Unsupported atomic pseudo for EmitAtomicCmpSwap."); 1836 1837 const unsigned Size = MI.getOpcode() == Mips::ATOMIC_CMP_SWAP_I32 ? 4 : 8; 1838 1839 MachineFunction *MF = BB->getParent(); 1840 MachineRegisterInfo &MRI = MF->getRegInfo(); 1841 const TargetRegisterClass *RC = getRegClassFor(MVT::getIntegerVT(Size * 8)); 1842 const TargetInstrInfo *TII = Subtarget.getInstrInfo(); 1843 DebugLoc DL = MI.getDebugLoc(); 1844 1845 unsigned AtomicOp = MI.getOpcode() == Mips::ATOMIC_CMP_SWAP_I32 1846 ? Mips::ATOMIC_CMP_SWAP_I32_POSTRA 1847 : Mips::ATOMIC_CMP_SWAP_I64_POSTRA; 1848 Register Dest = MI.getOperand(0).getReg(); 1849 Register Ptr = MI.getOperand(1).getReg(); 1850 Register OldVal = MI.getOperand(2).getReg(); 1851 Register NewVal = MI.getOperand(3).getReg(); 1852 1853 Register Scratch = MRI.createVirtualRegister(RC); 1854 MachineBasicBlock::iterator II(MI); 1855 1856 // We need to create copies of the various registers and kill them at the 1857 // atomic pseudo. If the copies are not made, when the atomic is expanded 1858 // after fast register allocation, the spills will end up outside of the 1859 // blocks that their values are defined in, causing livein errors. 1860 1861 Register PtrCopy = MRI.createVirtualRegister(MRI.getRegClass(Ptr)); 1862 Register OldValCopy = MRI.createVirtualRegister(MRI.getRegClass(OldVal)); 1863 Register NewValCopy = MRI.createVirtualRegister(MRI.getRegClass(NewVal)); 1864 1865 BuildMI(*BB, II, DL, TII->get(Mips::COPY), PtrCopy).addReg(Ptr); 1866 BuildMI(*BB, II, DL, TII->get(Mips::COPY), OldValCopy).addReg(OldVal); 1867 BuildMI(*BB, II, DL, TII->get(Mips::COPY), NewValCopy).addReg(NewVal); 1868 1869 // The purposes of the flags on the scratch registers is explained in 1870 // emitAtomicBinary. In summary, we need a scratch register which is going to 1871 // be undef, that is unique among registers chosen for the instruction. 1872 1873 BuildMI(*BB, II, DL, TII->get(AtomicOp)) 1874 .addReg(Dest, RegState::Define | RegState::EarlyClobber) 1875 .addReg(PtrCopy, RegState::Kill) 1876 .addReg(OldValCopy, RegState::Kill) 1877 .addReg(NewValCopy, RegState::Kill) 1878 .addReg(Scratch, RegState::EarlyClobber | RegState::Define | 1879 RegState::Dead | RegState::Implicit); 1880 1881 MI.eraseFromParent(); // The instruction is gone now. 1882 1883 return BB; 1884 } 1885 1886 MachineBasicBlock *MipsTargetLowering::emitAtomicCmpSwapPartword( 1887 MachineInstr &MI, MachineBasicBlock *BB, unsigned Size) const { 1888 assert((Size == 1 || Size == 2) && 1889 "Unsupported size for EmitAtomicCmpSwapPartial."); 1890 1891 MachineFunction *MF = BB->getParent(); 1892 MachineRegisterInfo &RegInfo = MF->getRegInfo(); 1893 const TargetRegisterClass *RC = getRegClassFor(MVT::i32); 1894 const bool ArePtrs64bit = ABI.ArePtrs64bit(); 1895 const TargetRegisterClass *RCp = 1896 getRegClassFor(ArePtrs64bit ? MVT::i64 : MVT::i32); 1897 const TargetInstrInfo *TII = Subtarget.getInstrInfo(); 1898 DebugLoc DL = MI.getDebugLoc(); 1899 1900 Register Dest = MI.getOperand(0).getReg(); 1901 Register Ptr = MI.getOperand(1).getReg(); 1902 Register CmpVal = MI.getOperand(2).getReg(); 1903 Register NewVal = MI.getOperand(3).getReg(); 1904 1905 Register AlignedAddr = RegInfo.createVirtualRegister(RCp); 1906 Register ShiftAmt = RegInfo.createVirtualRegister(RC); 1907 Register Mask = RegInfo.createVirtualRegister(RC); 1908 Register Mask2 = RegInfo.createVirtualRegister(RC); 1909 Register ShiftedCmpVal = RegInfo.createVirtualRegister(RC); 1910 Register ShiftedNewVal = RegInfo.createVirtualRegister(RC); 1911 Register MaskLSB2 = RegInfo.createVirtualRegister(RCp); 1912 Register PtrLSB2 = RegInfo.createVirtualRegister(RC); 1913 Register MaskUpper = RegInfo.createVirtualRegister(RC); 1914 Register MaskedCmpVal = RegInfo.createVirtualRegister(RC); 1915 Register MaskedNewVal = RegInfo.createVirtualRegister(RC); 1916 unsigned AtomicOp = MI.getOpcode() == Mips::ATOMIC_CMP_SWAP_I8 1917 ? Mips::ATOMIC_CMP_SWAP_I8_POSTRA 1918 : Mips::ATOMIC_CMP_SWAP_I16_POSTRA; 1919 1920 // The scratch registers here with the EarlyClobber | Define | Dead | Implicit 1921 // flags are used to coerce the register allocator and the machine verifier to 1922 // accept the usage of these registers. 1923 // The EarlyClobber flag has the semantic properties that the operand it is 1924 // attached to is clobbered before the rest of the inputs are read. Hence it 1925 // must be unique among the operands to the instruction. 1926 // The Define flag is needed to coerce the machine verifier that an Undef 1927 // value isn't a problem. 1928 // The Dead flag is needed as the value in scratch isn't used by any other 1929 // instruction. Kill isn't used as Dead is more precise. 1930 Register Scratch = RegInfo.createVirtualRegister(RC); 1931 Register Scratch2 = RegInfo.createVirtualRegister(RC); 1932 1933 // insert new blocks after the current block 1934 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 1935 MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB); 1936 MachineFunction::iterator It = ++BB->getIterator(); 1937 MF->insert(It, exitMBB); 1938 1939 // Transfer the remainder of BB and its successor edges to exitMBB. 1940 exitMBB->splice(exitMBB->begin(), BB, 1941 std::next(MachineBasicBlock::iterator(MI)), BB->end()); 1942 exitMBB->transferSuccessorsAndUpdatePHIs(BB); 1943 1944 BB->addSuccessor(exitMBB, BranchProbability::getOne()); 1945 1946 // thisMBB: 1947 // addiu masklsb2,$0,-4 # 0xfffffffc 1948 // and alignedaddr,ptr,masklsb2 1949 // andi ptrlsb2,ptr,3 1950 // xori ptrlsb2,ptrlsb2,3 # Only for BE 1951 // sll shiftamt,ptrlsb2,3 1952 // ori maskupper,$0,255 # 0xff 1953 // sll mask,maskupper,shiftamt 1954 // nor mask2,$0,mask 1955 // andi maskedcmpval,cmpval,255 1956 // sll shiftedcmpval,maskedcmpval,shiftamt 1957 // andi maskednewval,newval,255 1958 // sll shiftednewval,maskednewval,shiftamt 1959 int64_t MaskImm = (Size == 1) ? 255 : 65535; 1960 BuildMI(BB, DL, TII->get(ArePtrs64bit ? Mips::DADDiu : Mips::ADDiu), MaskLSB2) 1961 .addReg(ABI.GetNullPtr()).addImm(-4); 1962 BuildMI(BB, DL, TII->get(ArePtrs64bit ? Mips::AND64 : Mips::AND), AlignedAddr) 1963 .addReg(Ptr).addReg(MaskLSB2); 1964 BuildMI(BB, DL, TII->get(Mips::ANDi), PtrLSB2) 1965 .addReg(Ptr, 0, ArePtrs64bit ? Mips::sub_32 : 0).addImm(3); 1966 if (Subtarget.isLittle()) { 1967 BuildMI(BB, DL, TII->get(Mips::SLL), ShiftAmt).addReg(PtrLSB2).addImm(3); 1968 } else { 1969 Register Off = RegInfo.createVirtualRegister(RC); 1970 BuildMI(BB, DL, TII->get(Mips::XORi), Off) 1971 .addReg(PtrLSB2).addImm((Size == 1) ? 3 : 2); 1972 BuildMI(BB, DL, TII->get(Mips::SLL), ShiftAmt).addReg(Off).addImm(3); 1973 } 1974 BuildMI(BB, DL, TII->get(Mips::ORi), MaskUpper) 1975 .addReg(Mips::ZERO).addImm(MaskImm); 1976 BuildMI(BB, DL, TII->get(Mips::SLLV), Mask) 1977 .addReg(MaskUpper).addReg(ShiftAmt); 1978 BuildMI(BB, DL, TII->get(Mips::NOR), Mask2).addReg(Mips::ZERO).addReg(Mask); 1979 BuildMI(BB, DL, TII->get(Mips::ANDi), MaskedCmpVal) 1980 .addReg(CmpVal).addImm(MaskImm); 1981 BuildMI(BB, DL, TII->get(Mips::SLLV), ShiftedCmpVal) 1982 .addReg(MaskedCmpVal).addReg(ShiftAmt); 1983 BuildMI(BB, DL, TII->get(Mips::ANDi), MaskedNewVal) 1984 .addReg(NewVal).addImm(MaskImm); 1985 BuildMI(BB, DL, TII->get(Mips::SLLV), ShiftedNewVal) 1986 .addReg(MaskedNewVal).addReg(ShiftAmt); 1987 1988 // The purposes of the flags on the scratch registers are explained in 1989 // emitAtomicBinary. In summary, we need a scratch register which is going to 1990 // be undef, that is unique among the register chosen for the instruction. 1991 1992 BuildMI(BB, DL, TII->get(AtomicOp)) 1993 .addReg(Dest, RegState::Define | RegState::EarlyClobber) 1994 .addReg(AlignedAddr) 1995 .addReg(Mask) 1996 .addReg(ShiftedCmpVal) 1997 .addReg(Mask2) 1998 .addReg(ShiftedNewVal) 1999 .addReg(ShiftAmt) 2000 .addReg(Scratch, RegState::EarlyClobber | RegState::Define | 2001 RegState::Dead | RegState::Implicit) 2002 .addReg(Scratch2, RegState::EarlyClobber | RegState::Define | 2003 RegState::Dead | RegState::Implicit); 2004 2005 MI.eraseFromParent(); // The instruction is gone now. 2006 2007 return exitMBB; 2008 } 2009 2010 SDValue MipsTargetLowering::lowerBRCOND(SDValue Op, SelectionDAG &DAG) const { 2011 // The first operand is the chain, the second is the condition, the third is 2012 // the block to branch to if the condition is true. 2013 SDValue Chain = Op.getOperand(0); 2014 SDValue Dest = Op.getOperand(2); 2015 SDLoc DL(Op); 2016 2017 assert(!Subtarget.hasMips32r6() && !Subtarget.hasMips64r6()); 2018 SDValue CondRes = createFPCmp(DAG, Op.getOperand(1)); 2019 2020 // Return if flag is not set by a floating point comparison. 2021 if (CondRes.getOpcode() != MipsISD::FPCmp) 2022 return Op; 2023 2024 SDValue CCNode = CondRes.getOperand(2); 2025 Mips::CondCode CC = 2026 (Mips::CondCode)cast<ConstantSDNode>(CCNode)->getZExtValue(); 2027 unsigned Opc = invertFPCondCodeUser(CC) ? Mips::BRANCH_F : Mips::BRANCH_T; 2028 SDValue BrCode = DAG.getConstant(Opc, DL, MVT::i32); 2029 SDValue FCC0 = DAG.getRegister(Mips::FCC0, MVT::i32); 2030 return DAG.getNode(MipsISD::FPBrcond, DL, Op.getValueType(), Chain, BrCode, 2031 FCC0, Dest, CondRes); 2032 } 2033 2034 SDValue MipsTargetLowering:: 2035 lowerSELECT(SDValue Op, SelectionDAG &DAG) const 2036 { 2037 assert(!Subtarget.hasMips32r6() && !Subtarget.hasMips64r6()); 2038 SDValue Cond = createFPCmp(DAG, Op.getOperand(0)); 2039 2040 // Return if flag is not set by a floating point comparison. 2041 if (Cond.getOpcode() != MipsISD::FPCmp) 2042 return Op; 2043 2044 return createCMovFP(DAG, Cond, Op.getOperand(1), Op.getOperand(2), 2045 SDLoc(Op)); 2046 } 2047 2048 SDValue MipsTargetLowering::lowerSETCC(SDValue Op, SelectionDAG &DAG) const { 2049 assert(!Subtarget.hasMips32r6() && !Subtarget.hasMips64r6()); 2050 SDValue Cond = createFPCmp(DAG, Op); 2051 2052 assert(Cond.getOpcode() == MipsISD::FPCmp && 2053 "Floating point operand expected."); 2054 2055 SDLoc DL(Op); 2056 SDValue True = DAG.getConstant(1, DL, MVT::i32); 2057 SDValue False = DAG.getConstant(0, DL, MVT::i32); 2058 2059 return createCMovFP(DAG, Cond, True, False, DL); 2060 } 2061 2062 SDValue MipsTargetLowering::lowerGlobalAddress(SDValue Op, 2063 SelectionDAG &DAG) const { 2064 EVT Ty = Op.getValueType(); 2065 GlobalAddressSDNode *N = cast<GlobalAddressSDNode>(Op); 2066 const GlobalValue *GV = N->getGlobal(); 2067 2068 if (!isPositionIndependent()) { 2069 const MipsTargetObjectFile *TLOF = 2070 static_cast<const MipsTargetObjectFile *>( 2071 getTargetMachine().getObjFileLowering()); 2072 const GlobalObject *GO = GV->getAliaseeObject(); 2073 if (GO && TLOF->IsGlobalInSmallSection(GO, getTargetMachine())) 2074 // %gp_rel relocation 2075 return getAddrGPRel(N, SDLoc(N), Ty, DAG, ABI.IsN64()); 2076 2077 // %hi/%lo relocation 2078 return Subtarget.hasSym32() ? getAddrNonPIC(N, SDLoc(N), Ty, DAG) 2079 // %highest/%higher/%hi/%lo relocation 2080 : getAddrNonPICSym64(N, SDLoc(N), Ty, DAG); 2081 } 2082 2083 // Every other architecture would use shouldAssumeDSOLocal in here, but 2084 // mips is special. 2085 // * In PIC code mips requires got loads even for local statics! 2086 // * To save on got entries, for local statics the got entry contains the 2087 // page and an additional add instruction takes care of the low bits. 2088 // * It is legal to access a hidden symbol with a non hidden undefined, 2089 // so one cannot guarantee that all access to a hidden symbol will know 2090 // it is hidden. 2091 // * Mips linkers don't support creating a page and a full got entry for 2092 // the same symbol. 2093 // * Given all that, we have to use a full got entry for hidden symbols :-( 2094 if (GV->hasLocalLinkage()) 2095 return getAddrLocal(N, SDLoc(N), Ty, DAG, ABI.IsN32() || ABI.IsN64()); 2096 2097 if (Subtarget.useXGOT()) 2098 return getAddrGlobalLargeGOT( 2099 N, SDLoc(N), Ty, DAG, MipsII::MO_GOT_HI16, MipsII::MO_GOT_LO16, 2100 DAG.getEntryNode(), 2101 MachinePointerInfo::getGOT(DAG.getMachineFunction())); 2102 2103 return getAddrGlobal( 2104 N, SDLoc(N), Ty, DAG, 2105 (ABI.IsN32() || ABI.IsN64()) ? MipsII::MO_GOT_DISP : MipsII::MO_GOT, 2106 DAG.getEntryNode(), MachinePointerInfo::getGOT(DAG.getMachineFunction())); 2107 } 2108 2109 SDValue MipsTargetLowering::lowerBlockAddress(SDValue Op, 2110 SelectionDAG &DAG) const { 2111 BlockAddressSDNode *N = cast<BlockAddressSDNode>(Op); 2112 EVT Ty = Op.getValueType(); 2113 2114 if (!isPositionIndependent()) 2115 return Subtarget.hasSym32() ? getAddrNonPIC(N, SDLoc(N), Ty, DAG) 2116 : getAddrNonPICSym64(N, SDLoc(N), Ty, DAG); 2117 2118 return getAddrLocal(N, SDLoc(N), Ty, DAG, ABI.IsN32() || ABI.IsN64()); 2119 } 2120 2121 SDValue MipsTargetLowering:: 2122 lowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const 2123 { 2124 // If the relocation model is PIC, use the General Dynamic TLS Model or 2125 // Local Dynamic TLS model, otherwise use the Initial Exec or 2126 // Local Exec TLS Model. 2127 2128 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op); 2129 if (DAG.getTarget().useEmulatedTLS()) 2130 return LowerToTLSEmulatedModel(GA, DAG); 2131 2132 SDLoc DL(GA); 2133 const GlobalValue *GV = GA->getGlobal(); 2134 EVT PtrVT = getPointerTy(DAG.getDataLayout()); 2135 2136 TLSModel::Model model = getTargetMachine().getTLSModel(GV); 2137 2138 if (model == TLSModel::GeneralDynamic || model == TLSModel::LocalDynamic) { 2139 // General Dynamic and Local Dynamic TLS Model. 2140 unsigned Flag = (model == TLSModel::LocalDynamic) ? MipsII::MO_TLSLDM 2141 : MipsII::MO_TLSGD; 2142 2143 SDValue TGA = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, Flag); 2144 SDValue Argument = DAG.getNode(MipsISD::Wrapper, DL, PtrVT, 2145 getGlobalReg(DAG, PtrVT), TGA); 2146 unsigned PtrSize = PtrVT.getSizeInBits(); 2147 IntegerType *PtrTy = Type::getIntNTy(*DAG.getContext(), PtrSize); 2148 2149 SDValue TlsGetAddr = DAG.getExternalSymbol("__tls_get_addr", PtrVT); 2150 2151 ArgListTy Args; 2152 ArgListEntry Entry; 2153 Entry.Node = Argument; 2154 Entry.Ty = PtrTy; 2155 Args.push_back(Entry); 2156 2157 TargetLowering::CallLoweringInfo CLI(DAG); 2158 CLI.setDebugLoc(DL) 2159 .setChain(DAG.getEntryNode()) 2160 .setLibCallee(CallingConv::C, PtrTy, TlsGetAddr, std::move(Args)); 2161 std::pair<SDValue, SDValue> CallResult = LowerCallTo(CLI); 2162 2163 SDValue Ret = CallResult.first; 2164 2165 if (model != TLSModel::LocalDynamic) 2166 return Ret; 2167 2168 SDValue TGAHi = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, 2169 MipsII::MO_DTPREL_HI); 2170 SDValue Hi = DAG.getNode(MipsISD::TlsHi, DL, PtrVT, TGAHi); 2171 SDValue TGALo = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, 2172 MipsII::MO_DTPREL_LO); 2173 SDValue Lo = DAG.getNode(MipsISD::Lo, DL, PtrVT, TGALo); 2174 SDValue Add = DAG.getNode(ISD::ADD, DL, PtrVT, Hi, Ret); 2175 return DAG.getNode(ISD::ADD, DL, PtrVT, Add, Lo); 2176 } 2177 2178 SDValue Offset; 2179 if (model == TLSModel::InitialExec) { 2180 // Initial Exec TLS Model 2181 SDValue TGA = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, 2182 MipsII::MO_GOTTPREL); 2183 TGA = DAG.getNode(MipsISD::Wrapper, DL, PtrVT, getGlobalReg(DAG, PtrVT), 2184 TGA); 2185 Offset = 2186 DAG.getLoad(PtrVT, DL, DAG.getEntryNode(), TGA, MachinePointerInfo()); 2187 } else { 2188 // Local Exec TLS Model 2189 assert(model == TLSModel::LocalExec); 2190 SDValue TGAHi = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, 2191 MipsII::MO_TPREL_HI); 2192 SDValue TGALo = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, 2193 MipsII::MO_TPREL_LO); 2194 SDValue Hi = DAG.getNode(MipsISD::TlsHi, DL, PtrVT, TGAHi); 2195 SDValue Lo = DAG.getNode(MipsISD::Lo, DL, PtrVT, TGALo); 2196 Offset = DAG.getNode(ISD::ADD, DL, PtrVT, Hi, Lo); 2197 } 2198 2199 SDValue ThreadPointer = DAG.getNode(MipsISD::ThreadPointer, DL, PtrVT); 2200 return DAG.getNode(ISD::ADD, DL, PtrVT, ThreadPointer, Offset); 2201 } 2202 2203 SDValue MipsTargetLowering:: 2204 lowerJumpTable(SDValue Op, SelectionDAG &DAG) const 2205 { 2206 JumpTableSDNode *N = cast<JumpTableSDNode>(Op); 2207 EVT Ty = Op.getValueType(); 2208 2209 if (!isPositionIndependent()) 2210 return Subtarget.hasSym32() ? getAddrNonPIC(N, SDLoc(N), Ty, DAG) 2211 : getAddrNonPICSym64(N, SDLoc(N), Ty, DAG); 2212 2213 return getAddrLocal(N, SDLoc(N), Ty, DAG, ABI.IsN32() || ABI.IsN64()); 2214 } 2215 2216 SDValue MipsTargetLowering:: 2217 lowerConstantPool(SDValue Op, SelectionDAG &DAG) const 2218 { 2219 ConstantPoolSDNode *N = cast<ConstantPoolSDNode>(Op); 2220 EVT Ty = Op.getValueType(); 2221 2222 if (!isPositionIndependent()) { 2223 const MipsTargetObjectFile *TLOF = 2224 static_cast<const MipsTargetObjectFile *>( 2225 getTargetMachine().getObjFileLowering()); 2226 2227 if (TLOF->IsConstantInSmallSection(DAG.getDataLayout(), N->getConstVal(), 2228 getTargetMachine())) 2229 // %gp_rel relocation 2230 return getAddrGPRel(N, SDLoc(N), Ty, DAG, ABI.IsN64()); 2231 2232 return Subtarget.hasSym32() ? getAddrNonPIC(N, SDLoc(N), Ty, DAG) 2233 : getAddrNonPICSym64(N, SDLoc(N), Ty, DAG); 2234 } 2235 2236 return getAddrLocal(N, SDLoc(N), Ty, DAG, ABI.IsN32() || ABI.IsN64()); 2237 } 2238 2239 SDValue MipsTargetLowering::lowerVASTART(SDValue Op, SelectionDAG &DAG) const { 2240 MachineFunction &MF = DAG.getMachineFunction(); 2241 MipsFunctionInfo *FuncInfo = MF.getInfo<MipsFunctionInfo>(); 2242 2243 SDLoc DL(Op); 2244 SDValue FI = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), 2245 getPointerTy(MF.getDataLayout())); 2246 2247 // vastart just stores the address of the VarArgsFrameIndex slot into the 2248 // memory location argument. 2249 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue(); 2250 return DAG.getStore(Op.getOperand(0), DL, FI, Op.getOperand(1), 2251 MachinePointerInfo(SV)); 2252 } 2253 2254 SDValue MipsTargetLowering::lowerVAARG(SDValue Op, SelectionDAG &DAG) const { 2255 SDNode *Node = Op.getNode(); 2256 EVT VT = Node->getValueType(0); 2257 SDValue Chain = Node->getOperand(0); 2258 SDValue VAListPtr = Node->getOperand(1); 2259 const Align Align = 2260 llvm::MaybeAlign(Node->getConstantOperandVal(3)).valueOrOne(); 2261 const Value *SV = cast<SrcValueSDNode>(Node->getOperand(2))->getValue(); 2262 SDLoc DL(Node); 2263 unsigned ArgSlotSizeInBytes = (ABI.IsN32() || ABI.IsN64()) ? 8 : 4; 2264 2265 SDValue VAListLoad = DAG.getLoad(getPointerTy(DAG.getDataLayout()), DL, Chain, 2266 VAListPtr, MachinePointerInfo(SV)); 2267 SDValue VAList = VAListLoad; 2268 2269 // Re-align the pointer if necessary. 2270 // It should only ever be necessary for 64-bit types on O32 since the minimum 2271 // argument alignment is the same as the maximum type alignment for N32/N64. 2272 // 2273 // FIXME: We currently align too often. The code generator doesn't notice 2274 // when the pointer is still aligned from the last va_arg (or pair of 2275 // va_args for the i64 on O32 case). 2276 if (Align > getMinStackArgumentAlignment()) { 2277 VAList = DAG.getNode( 2278 ISD::ADD, DL, VAList.getValueType(), VAList, 2279 DAG.getConstant(Align.value() - 1, DL, VAList.getValueType())); 2280 2281 VAList = DAG.getNode( 2282 ISD::AND, DL, VAList.getValueType(), VAList, 2283 DAG.getConstant(-(int64_t)Align.value(), DL, VAList.getValueType())); 2284 } 2285 2286 // Increment the pointer, VAList, to the next vaarg. 2287 auto &TD = DAG.getDataLayout(); 2288 unsigned ArgSizeInBytes = 2289 TD.getTypeAllocSize(VT.getTypeForEVT(*DAG.getContext())); 2290 SDValue Tmp3 = 2291 DAG.getNode(ISD::ADD, DL, VAList.getValueType(), VAList, 2292 DAG.getConstant(alignTo(ArgSizeInBytes, ArgSlotSizeInBytes), 2293 DL, VAList.getValueType())); 2294 // Store the incremented VAList to the legalized pointer 2295 Chain = DAG.getStore(VAListLoad.getValue(1), DL, Tmp3, VAListPtr, 2296 MachinePointerInfo(SV)); 2297 2298 // In big-endian mode we must adjust the pointer when the load size is smaller 2299 // than the argument slot size. We must also reduce the known alignment to 2300 // match. For example in the N64 ABI, we must add 4 bytes to the offset to get 2301 // the correct half of the slot, and reduce the alignment from 8 (slot 2302 // alignment) down to 4 (type alignment). 2303 if (!Subtarget.isLittle() && ArgSizeInBytes < ArgSlotSizeInBytes) { 2304 unsigned Adjustment = ArgSlotSizeInBytes - ArgSizeInBytes; 2305 VAList = DAG.getNode(ISD::ADD, DL, VAListPtr.getValueType(), VAList, 2306 DAG.getIntPtrConstant(Adjustment, DL)); 2307 } 2308 // Load the actual argument out of the pointer VAList 2309 return DAG.getLoad(VT, DL, Chain, VAList, MachinePointerInfo()); 2310 } 2311 2312 static SDValue lowerFCOPYSIGN32(SDValue Op, SelectionDAG &DAG, 2313 bool HasExtractInsert) { 2314 EVT TyX = Op.getOperand(0).getValueType(); 2315 EVT TyY = Op.getOperand(1).getValueType(); 2316 SDLoc DL(Op); 2317 SDValue Const1 = DAG.getConstant(1, DL, MVT::i32); 2318 SDValue Const31 = DAG.getConstant(31, DL, MVT::i32); 2319 SDValue Res; 2320 2321 // If operand is of type f64, extract the upper 32-bit. Otherwise, bitcast it 2322 // to i32. 2323 SDValue X = (TyX == MVT::f32) ? 2324 DAG.getNode(ISD::BITCAST, DL, MVT::i32, Op.getOperand(0)) : 2325 DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32, Op.getOperand(0), 2326 Const1); 2327 SDValue Y = (TyY == MVT::f32) ? 2328 DAG.getNode(ISD::BITCAST, DL, MVT::i32, Op.getOperand(1)) : 2329 DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32, Op.getOperand(1), 2330 Const1); 2331 2332 if (HasExtractInsert) { 2333 // ext E, Y, 31, 1 ; extract bit31 of Y 2334 // ins X, E, 31, 1 ; insert extracted bit at bit31 of X 2335 SDValue E = DAG.getNode(MipsISD::Ext, DL, MVT::i32, Y, Const31, Const1); 2336 Res = DAG.getNode(MipsISD::Ins, DL, MVT::i32, E, Const31, Const1, X); 2337 } else { 2338 // sll SllX, X, 1 2339 // srl SrlX, SllX, 1 2340 // srl SrlY, Y, 31 2341 // sll SllY, SrlX, 31 2342 // or Or, SrlX, SllY 2343 SDValue SllX = DAG.getNode(ISD::SHL, DL, MVT::i32, X, Const1); 2344 SDValue SrlX = DAG.getNode(ISD::SRL, DL, MVT::i32, SllX, Const1); 2345 SDValue SrlY = DAG.getNode(ISD::SRL, DL, MVT::i32, Y, Const31); 2346 SDValue SllY = DAG.getNode(ISD::SHL, DL, MVT::i32, SrlY, Const31); 2347 Res = DAG.getNode(ISD::OR, DL, MVT::i32, SrlX, SllY); 2348 } 2349 2350 if (TyX == MVT::f32) 2351 return DAG.getNode(ISD::BITCAST, DL, Op.getOperand(0).getValueType(), Res); 2352 2353 SDValue LowX = DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32, 2354 Op.getOperand(0), 2355 DAG.getConstant(0, DL, MVT::i32)); 2356 return DAG.getNode(MipsISD::BuildPairF64, DL, MVT::f64, LowX, Res); 2357 } 2358 2359 static SDValue lowerFCOPYSIGN64(SDValue Op, SelectionDAG &DAG, 2360 bool HasExtractInsert) { 2361 unsigned WidthX = Op.getOperand(0).getValueSizeInBits(); 2362 unsigned WidthY = Op.getOperand(1).getValueSizeInBits(); 2363 EVT TyX = MVT::getIntegerVT(WidthX), TyY = MVT::getIntegerVT(WidthY); 2364 SDLoc DL(Op); 2365 SDValue Const1 = DAG.getConstant(1, DL, MVT::i32); 2366 2367 // Bitcast to integer nodes. 2368 SDValue X = DAG.getNode(ISD::BITCAST, DL, TyX, Op.getOperand(0)); 2369 SDValue Y = DAG.getNode(ISD::BITCAST, DL, TyY, Op.getOperand(1)); 2370 2371 if (HasExtractInsert) { 2372 // ext E, Y, width(Y) - 1, 1 ; extract bit width(Y)-1 of Y 2373 // ins X, E, width(X) - 1, 1 ; insert extracted bit at bit width(X)-1 of X 2374 SDValue E = DAG.getNode(MipsISD::Ext, DL, TyY, Y, 2375 DAG.getConstant(WidthY - 1, DL, MVT::i32), Const1); 2376 2377 if (WidthX > WidthY) 2378 E = DAG.getNode(ISD::ZERO_EXTEND, DL, TyX, E); 2379 else if (WidthY > WidthX) 2380 E = DAG.getNode(ISD::TRUNCATE, DL, TyX, E); 2381 2382 SDValue I = DAG.getNode(MipsISD::Ins, DL, TyX, E, 2383 DAG.getConstant(WidthX - 1, DL, MVT::i32), Const1, 2384 X); 2385 return DAG.getNode(ISD::BITCAST, DL, Op.getOperand(0).getValueType(), I); 2386 } 2387 2388 // (d)sll SllX, X, 1 2389 // (d)srl SrlX, SllX, 1 2390 // (d)srl SrlY, Y, width(Y)-1 2391 // (d)sll SllY, SrlX, width(Y)-1 2392 // or Or, SrlX, SllY 2393 SDValue SllX = DAG.getNode(ISD::SHL, DL, TyX, X, Const1); 2394 SDValue SrlX = DAG.getNode(ISD::SRL, DL, TyX, SllX, Const1); 2395 SDValue SrlY = DAG.getNode(ISD::SRL, DL, TyY, Y, 2396 DAG.getConstant(WidthY - 1, DL, MVT::i32)); 2397 2398 if (WidthX > WidthY) 2399 SrlY = DAG.getNode(ISD::ZERO_EXTEND, DL, TyX, SrlY); 2400 else if (WidthY > WidthX) 2401 SrlY = DAG.getNode(ISD::TRUNCATE, DL, TyX, SrlY); 2402 2403 SDValue SllY = DAG.getNode(ISD::SHL, DL, TyX, SrlY, 2404 DAG.getConstant(WidthX - 1, DL, MVT::i32)); 2405 SDValue Or = DAG.getNode(ISD::OR, DL, TyX, SrlX, SllY); 2406 return DAG.getNode(ISD::BITCAST, DL, Op.getOperand(0).getValueType(), Or); 2407 } 2408 2409 SDValue 2410 MipsTargetLowering::lowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const { 2411 if (Subtarget.isGP64bit()) 2412 return lowerFCOPYSIGN64(Op, DAG, Subtarget.hasExtractInsert()); 2413 2414 return lowerFCOPYSIGN32(Op, DAG, Subtarget.hasExtractInsert()); 2415 } 2416 2417 static SDValue lowerFABS32(SDValue Op, SelectionDAG &DAG, 2418 bool HasExtractInsert) { 2419 SDLoc DL(Op); 2420 SDValue Res, Const1 = DAG.getConstant(1, DL, MVT::i32); 2421 2422 // If operand is of type f64, extract the upper 32-bit. Otherwise, bitcast it 2423 // to i32. 2424 SDValue X = (Op.getValueType() == MVT::f32) 2425 ? DAG.getNode(ISD::BITCAST, DL, MVT::i32, Op.getOperand(0)) 2426 : DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32, 2427 Op.getOperand(0), Const1); 2428 2429 // Clear MSB. 2430 if (HasExtractInsert) 2431 Res = DAG.getNode(MipsISD::Ins, DL, MVT::i32, 2432 DAG.getRegister(Mips::ZERO, MVT::i32), 2433 DAG.getConstant(31, DL, MVT::i32), Const1, X); 2434 else { 2435 // TODO: Provide DAG patterns which transform (and x, cst) 2436 // back to a (shl (srl x (clz cst)) (clz cst)) sequence. 2437 SDValue SllX = DAG.getNode(ISD::SHL, DL, MVT::i32, X, Const1); 2438 Res = DAG.getNode(ISD::SRL, DL, MVT::i32, SllX, Const1); 2439 } 2440 2441 if (Op.getValueType() == MVT::f32) 2442 return DAG.getNode(ISD::BITCAST, DL, MVT::f32, Res); 2443 2444 // FIXME: For mips32r2, the sequence of (BuildPairF64 (ins (ExtractElementF64 2445 // Op 1), $zero, 31 1) (ExtractElementF64 Op 0)) and the Op has one use, we 2446 // should be able to drop the usage of mfc1/mtc1 and rewrite the register in 2447 // place. 2448 SDValue LowX = 2449 DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32, Op.getOperand(0), 2450 DAG.getConstant(0, DL, MVT::i32)); 2451 return DAG.getNode(MipsISD::BuildPairF64, DL, MVT::f64, LowX, Res); 2452 } 2453 2454 static SDValue lowerFABS64(SDValue Op, SelectionDAG &DAG, 2455 bool HasExtractInsert) { 2456 SDLoc DL(Op); 2457 SDValue Res, Const1 = DAG.getConstant(1, DL, MVT::i32); 2458 2459 // Bitcast to integer node. 2460 SDValue X = DAG.getNode(ISD::BITCAST, DL, MVT::i64, Op.getOperand(0)); 2461 2462 // Clear MSB. 2463 if (HasExtractInsert) 2464 Res = DAG.getNode(MipsISD::Ins, DL, MVT::i64, 2465 DAG.getRegister(Mips::ZERO_64, MVT::i64), 2466 DAG.getConstant(63, DL, MVT::i32), Const1, X); 2467 else { 2468 SDValue SllX = DAG.getNode(ISD::SHL, DL, MVT::i64, X, Const1); 2469 Res = DAG.getNode(ISD::SRL, DL, MVT::i64, SllX, Const1); 2470 } 2471 2472 return DAG.getNode(ISD::BITCAST, DL, MVT::f64, Res); 2473 } 2474 2475 SDValue MipsTargetLowering::lowerFABS(SDValue Op, SelectionDAG &DAG) const { 2476 if ((ABI.IsN32() || ABI.IsN64()) && (Op.getValueType() == MVT::f64)) 2477 return lowerFABS64(Op, DAG, Subtarget.hasExtractInsert()); 2478 2479 return lowerFABS32(Op, DAG, Subtarget.hasExtractInsert()); 2480 } 2481 2482 SDValue MipsTargetLowering:: 2483 lowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const { 2484 // check the depth 2485 if (cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue() != 0) { 2486 DAG.getContext()->emitError( 2487 "return address can be determined only for current frame"); 2488 return SDValue(); 2489 } 2490 2491 MachineFrameInfo &MFI = DAG.getMachineFunction().getFrameInfo(); 2492 MFI.setFrameAddressIsTaken(true); 2493 EVT VT = Op.getValueType(); 2494 SDLoc DL(Op); 2495 SDValue FrameAddr = DAG.getCopyFromReg( 2496 DAG.getEntryNode(), DL, ABI.IsN64() ? Mips::FP_64 : Mips::FP, VT); 2497 return FrameAddr; 2498 } 2499 2500 SDValue MipsTargetLowering::lowerRETURNADDR(SDValue Op, 2501 SelectionDAG &DAG) const { 2502 if (verifyReturnAddressArgumentIsConstant(Op, DAG)) 2503 return SDValue(); 2504 2505 // check the depth 2506 if (cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue() != 0) { 2507 DAG.getContext()->emitError( 2508 "return address can be determined only for current frame"); 2509 return SDValue(); 2510 } 2511 2512 MachineFunction &MF = DAG.getMachineFunction(); 2513 MachineFrameInfo &MFI = MF.getFrameInfo(); 2514 MVT VT = Op.getSimpleValueType(); 2515 unsigned RA = ABI.IsN64() ? Mips::RA_64 : Mips::RA; 2516 MFI.setReturnAddressIsTaken(true); 2517 2518 // Return RA, which contains the return address. Mark it an implicit live-in. 2519 Register Reg = MF.addLiveIn(RA, getRegClassFor(VT)); 2520 return DAG.getCopyFromReg(DAG.getEntryNode(), SDLoc(Op), Reg, VT); 2521 } 2522 2523 // An EH_RETURN is the result of lowering llvm.eh.return which in turn is 2524 // generated from __builtin_eh_return (offset, handler) 2525 // The effect of this is to adjust the stack pointer by "offset" 2526 // and then branch to "handler". 2527 SDValue MipsTargetLowering::lowerEH_RETURN(SDValue Op, SelectionDAG &DAG) 2528 const { 2529 MachineFunction &MF = DAG.getMachineFunction(); 2530 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>(); 2531 2532 MipsFI->setCallsEhReturn(); 2533 SDValue Chain = Op.getOperand(0); 2534 SDValue Offset = Op.getOperand(1); 2535 SDValue Handler = Op.getOperand(2); 2536 SDLoc DL(Op); 2537 EVT Ty = ABI.IsN64() ? MVT::i64 : MVT::i32; 2538 2539 // Store stack offset in V1, store jump target in V0. Glue CopyToReg and 2540 // EH_RETURN nodes, so that instructions are emitted back-to-back. 2541 unsigned OffsetReg = ABI.IsN64() ? Mips::V1_64 : Mips::V1; 2542 unsigned AddrReg = ABI.IsN64() ? Mips::V0_64 : Mips::V0; 2543 Chain = DAG.getCopyToReg(Chain, DL, OffsetReg, Offset, SDValue()); 2544 Chain = DAG.getCopyToReg(Chain, DL, AddrReg, Handler, Chain.getValue(1)); 2545 return DAG.getNode(MipsISD::EH_RETURN, DL, MVT::Other, Chain, 2546 DAG.getRegister(OffsetReg, Ty), 2547 DAG.getRegister(AddrReg, getPointerTy(MF.getDataLayout())), 2548 Chain.getValue(1)); 2549 } 2550 2551 SDValue MipsTargetLowering::lowerATOMIC_FENCE(SDValue Op, 2552 SelectionDAG &DAG) const { 2553 // FIXME: Need pseudo-fence for 'singlethread' fences 2554 // FIXME: Set SType for weaker fences where supported/appropriate. 2555 unsigned SType = 0; 2556 SDLoc DL(Op); 2557 return DAG.getNode(MipsISD::Sync, DL, MVT::Other, Op.getOperand(0), 2558 DAG.getConstant(SType, DL, MVT::i32)); 2559 } 2560 2561 SDValue MipsTargetLowering::lowerShiftLeftParts(SDValue Op, 2562 SelectionDAG &DAG) const { 2563 SDLoc DL(Op); 2564 MVT VT = Subtarget.isGP64bit() ? MVT::i64 : MVT::i32; 2565 2566 SDValue Lo = Op.getOperand(0), Hi = Op.getOperand(1); 2567 SDValue Shamt = Op.getOperand(2); 2568 // if shamt < (VT.bits): 2569 // lo = (shl lo, shamt) 2570 // hi = (or (shl hi, shamt) (srl (srl lo, 1), ~shamt)) 2571 // else: 2572 // lo = 0 2573 // hi = (shl lo, shamt[4:0]) 2574 SDValue Not = DAG.getNode(ISD::XOR, DL, MVT::i32, Shamt, 2575 DAG.getConstant(-1, DL, MVT::i32)); 2576 SDValue ShiftRight1Lo = DAG.getNode(ISD::SRL, DL, VT, Lo, 2577 DAG.getConstant(1, DL, VT)); 2578 SDValue ShiftRightLo = DAG.getNode(ISD::SRL, DL, VT, ShiftRight1Lo, Not); 2579 SDValue ShiftLeftHi = DAG.getNode(ISD::SHL, DL, VT, Hi, Shamt); 2580 SDValue Or = DAG.getNode(ISD::OR, DL, VT, ShiftLeftHi, ShiftRightLo); 2581 SDValue ShiftLeftLo = DAG.getNode(ISD::SHL, DL, VT, Lo, Shamt); 2582 SDValue Cond = DAG.getNode(ISD::AND, DL, MVT::i32, Shamt, 2583 DAG.getConstant(VT.getSizeInBits(), DL, MVT::i32)); 2584 Lo = DAG.getNode(ISD::SELECT, DL, VT, Cond, 2585 DAG.getConstant(0, DL, VT), ShiftLeftLo); 2586 Hi = DAG.getNode(ISD::SELECT, DL, VT, Cond, ShiftLeftLo, Or); 2587 2588 SDValue Ops[2] = {Lo, Hi}; 2589 return DAG.getMergeValues(Ops, DL); 2590 } 2591 2592 SDValue MipsTargetLowering::lowerShiftRightParts(SDValue Op, SelectionDAG &DAG, 2593 bool IsSRA) const { 2594 SDLoc DL(Op); 2595 SDValue Lo = Op.getOperand(0), Hi = Op.getOperand(1); 2596 SDValue Shamt = Op.getOperand(2); 2597 MVT VT = Subtarget.isGP64bit() ? MVT::i64 : MVT::i32; 2598 2599 // if shamt < (VT.bits): 2600 // lo = (or (shl (shl hi, 1), ~shamt) (srl lo, shamt)) 2601 // if isSRA: 2602 // hi = (sra hi, shamt) 2603 // else: 2604 // hi = (srl hi, shamt) 2605 // else: 2606 // if isSRA: 2607 // lo = (sra hi, shamt[4:0]) 2608 // hi = (sra hi, 31) 2609 // else: 2610 // lo = (srl hi, shamt[4:0]) 2611 // hi = 0 2612 SDValue Not = DAG.getNode(ISD::XOR, DL, MVT::i32, Shamt, 2613 DAG.getConstant(-1, DL, MVT::i32)); 2614 SDValue ShiftLeft1Hi = DAG.getNode(ISD::SHL, DL, VT, Hi, 2615 DAG.getConstant(1, DL, VT)); 2616 SDValue ShiftLeftHi = DAG.getNode(ISD::SHL, DL, VT, ShiftLeft1Hi, Not); 2617 SDValue ShiftRightLo = DAG.getNode(ISD::SRL, DL, VT, Lo, Shamt); 2618 SDValue Or = DAG.getNode(ISD::OR, DL, VT, ShiftLeftHi, ShiftRightLo); 2619 SDValue ShiftRightHi = DAG.getNode(IsSRA ? ISD::SRA : ISD::SRL, 2620 DL, VT, Hi, Shamt); 2621 SDValue Cond = DAG.getNode(ISD::AND, DL, MVT::i32, Shamt, 2622 DAG.getConstant(VT.getSizeInBits(), DL, MVT::i32)); 2623 SDValue Ext = DAG.getNode(ISD::SRA, DL, VT, Hi, 2624 DAG.getConstant(VT.getSizeInBits() - 1, DL, VT)); 2625 2626 if (!(Subtarget.hasMips4() || Subtarget.hasMips32())) { 2627 SDVTList VTList = DAG.getVTList(VT, VT); 2628 return DAG.getNode(Subtarget.isGP64bit() ? Mips::PseudoD_SELECT_I64 2629 : Mips::PseudoD_SELECT_I, 2630 DL, VTList, Cond, ShiftRightHi, 2631 IsSRA ? Ext : DAG.getConstant(0, DL, VT), Or, 2632 ShiftRightHi); 2633 } 2634 2635 Lo = DAG.getNode(ISD::SELECT, DL, VT, Cond, ShiftRightHi, Or); 2636 Hi = DAG.getNode(ISD::SELECT, DL, VT, Cond, 2637 IsSRA ? Ext : DAG.getConstant(0, DL, VT), ShiftRightHi); 2638 2639 SDValue Ops[2] = {Lo, Hi}; 2640 return DAG.getMergeValues(Ops, DL); 2641 } 2642 2643 static SDValue createLoadLR(unsigned Opc, SelectionDAG &DAG, LoadSDNode *LD, 2644 SDValue Chain, SDValue Src, unsigned Offset) { 2645 SDValue Ptr = LD->getBasePtr(); 2646 EVT VT = LD->getValueType(0), MemVT = LD->getMemoryVT(); 2647 EVT BasePtrVT = Ptr.getValueType(); 2648 SDLoc DL(LD); 2649 SDVTList VTList = DAG.getVTList(VT, MVT::Other); 2650 2651 if (Offset) 2652 Ptr = DAG.getNode(ISD::ADD, DL, BasePtrVT, Ptr, 2653 DAG.getConstant(Offset, DL, BasePtrVT)); 2654 2655 SDValue Ops[] = { Chain, Ptr, Src }; 2656 return DAG.getMemIntrinsicNode(Opc, DL, VTList, Ops, MemVT, 2657 LD->getMemOperand()); 2658 } 2659 2660 // Expand an unaligned 32 or 64-bit integer load node. 2661 SDValue MipsTargetLowering::lowerLOAD(SDValue Op, SelectionDAG &DAG) const { 2662 LoadSDNode *LD = cast<LoadSDNode>(Op); 2663 EVT MemVT = LD->getMemoryVT(); 2664 2665 if (Subtarget.systemSupportsUnalignedAccess()) 2666 return Op; 2667 2668 // Return if load is aligned or if MemVT is neither i32 nor i64. 2669 if ((LD->getAlignment() >= MemVT.getSizeInBits() / 8) || 2670 ((MemVT != MVT::i32) && (MemVT != MVT::i64))) 2671 return SDValue(); 2672 2673 bool IsLittle = Subtarget.isLittle(); 2674 EVT VT = Op.getValueType(); 2675 ISD::LoadExtType ExtType = LD->getExtensionType(); 2676 SDValue Chain = LD->getChain(), Undef = DAG.getUNDEF(VT); 2677 2678 assert((VT == MVT::i32) || (VT == MVT::i64)); 2679 2680 // Expand 2681 // (set dst, (i64 (load baseptr))) 2682 // to 2683 // (set tmp, (ldl (add baseptr, 7), undef)) 2684 // (set dst, (ldr baseptr, tmp)) 2685 if ((VT == MVT::i64) && (ExtType == ISD::NON_EXTLOAD)) { 2686 SDValue LDL = createLoadLR(MipsISD::LDL, DAG, LD, Chain, Undef, 2687 IsLittle ? 7 : 0); 2688 return createLoadLR(MipsISD::LDR, DAG, LD, LDL.getValue(1), LDL, 2689 IsLittle ? 0 : 7); 2690 } 2691 2692 SDValue LWL = createLoadLR(MipsISD::LWL, DAG, LD, Chain, Undef, 2693 IsLittle ? 3 : 0); 2694 SDValue LWR = createLoadLR(MipsISD::LWR, DAG, LD, LWL.getValue(1), LWL, 2695 IsLittle ? 0 : 3); 2696 2697 // Expand 2698 // (set dst, (i32 (load baseptr))) or 2699 // (set dst, (i64 (sextload baseptr))) or 2700 // (set dst, (i64 (extload baseptr))) 2701 // to 2702 // (set tmp, (lwl (add baseptr, 3), undef)) 2703 // (set dst, (lwr baseptr, tmp)) 2704 if ((VT == MVT::i32) || (ExtType == ISD::SEXTLOAD) || 2705 (ExtType == ISD::EXTLOAD)) 2706 return LWR; 2707 2708 assert((VT == MVT::i64) && (ExtType == ISD::ZEXTLOAD)); 2709 2710 // Expand 2711 // (set dst, (i64 (zextload baseptr))) 2712 // to 2713 // (set tmp0, (lwl (add baseptr, 3), undef)) 2714 // (set tmp1, (lwr baseptr, tmp0)) 2715 // (set tmp2, (shl tmp1, 32)) 2716 // (set dst, (srl tmp2, 32)) 2717 SDLoc DL(LD); 2718 SDValue Const32 = DAG.getConstant(32, DL, MVT::i32); 2719 SDValue SLL = DAG.getNode(ISD::SHL, DL, MVT::i64, LWR, Const32); 2720 SDValue SRL = DAG.getNode(ISD::SRL, DL, MVT::i64, SLL, Const32); 2721 SDValue Ops[] = { SRL, LWR.getValue(1) }; 2722 return DAG.getMergeValues(Ops, DL); 2723 } 2724 2725 static SDValue createStoreLR(unsigned Opc, SelectionDAG &DAG, StoreSDNode *SD, 2726 SDValue Chain, unsigned Offset) { 2727 SDValue Ptr = SD->getBasePtr(), Value = SD->getValue(); 2728 EVT MemVT = SD->getMemoryVT(), BasePtrVT = Ptr.getValueType(); 2729 SDLoc DL(SD); 2730 SDVTList VTList = DAG.getVTList(MVT::Other); 2731 2732 if (Offset) 2733 Ptr = DAG.getNode(ISD::ADD, DL, BasePtrVT, Ptr, 2734 DAG.getConstant(Offset, DL, BasePtrVT)); 2735 2736 SDValue Ops[] = { Chain, Value, Ptr }; 2737 return DAG.getMemIntrinsicNode(Opc, DL, VTList, Ops, MemVT, 2738 SD->getMemOperand()); 2739 } 2740 2741 // Expand an unaligned 32 or 64-bit integer store node. 2742 static SDValue lowerUnalignedIntStore(StoreSDNode *SD, SelectionDAG &DAG, 2743 bool IsLittle) { 2744 SDValue Value = SD->getValue(), Chain = SD->getChain(); 2745 EVT VT = Value.getValueType(); 2746 2747 // Expand 2748 // (store val, baseptr) or 2749 // (truncstore val, baseptr) 2750 // to 2751 // (swl val, (add baseptr, 3)) 2752 // (swr val, baseptr) 2753 if ((VT == MVT::i32) || SD->isTruncatingStore()) { 2754 SDValue SWL = createStoreLR(MipsISD::SWL, DAG, SD, Chain, 2755 IsLittle ? 3 : 0); 2756 return createStoreLR(MipsISD::SWR, DAG, SD, SWL, IsLittle ? 0 : 3); 2757 } 2758 2759 assert(VT == MVT::i64); 2760 2761 // Expand 2762 // (store val, baseptr) 2763 // to 2764 // (sdl val, (add baseptr, 7)) 2765 // (sdr val, baseptr) 2766 SDValue SDL = createStoreLR(MipsISD::SDL, DAG, SD, Chain, IsLittle ? 7 : 0); 2767 return createStoreLR(MipsISD::SDR, DAG, SD, SDL, IsLittle ? 0 : 7); 2768 } 2769 2770 // Lower (store (fp_to_sint $fp) $ptr) to (store (TruncIntFP $fp), $ptr). 2771 static SDValue lowerFP_TO_SINT_STORE(StoreSDNode *SD, SelectionDAG &DAG, 2772 bool SingleFloat) { 2773 SDValue Val = SD->getValue(); 2774 2775 if (Val.getOpcode() != ISD::FP_TO_SINT || 2776 (Val.getValueSizeInBits() > 32 && SingleFloat)) 2777 return SDValue(); 2778 2779 EVT FPTy = EVT::getFloatingPointVT(Val.getValueSizeInBits()); 2780 SDValue Tr = DAG.getNode(MipsISD::TruncIntFP, SDLoc(Val), FPTy, 2781 Val.getOperand(0)); 2782 return DAG.getStore(SD->getChain(), SDLoc(SD), Tr, SD->getBasePtr(), 2783 SD->getPointerInfo(), SD->getAlignment(), 2784 SD->getMemOperand()->getFlags()); 2785 } 2786 2787 SDValue MipsTargetLowering::lowerSTORE(SDValue Op, SelectionDAG &DAG) const { 2788 StoreSDNode *SD = cast<StoreSDNode>(Op); 2789 EVT MemVT = SD->getMemoryVT(); 2790 2791 // Lower unaligned integer stores. 2792 if (!Subtarget.systemSupportsUnalignedAccess() && 2793 (SD->getAlignment() < MemVT.getSizeInBits() / 8) && 2794 ((MemVT == MVT::i32) || (MemVT == MVT::i64))) 2795 return lowerUnalignedIntStore(SD, DAG, Subtarget.isLittle()); 2796 2797 return lowerFP_TO_SINT_STORE(SD, DAG, Subtarget.isSingleFloat()); 2798 } 2799 2800 SDValue MipsTargetLowering::lowerEH_DWARF_CFA(SDValue Op, 2801 SelectionDAG &DAG) const { 2802 2803 // Return a fixed StackObject with offset 0 which points to the old stack 2804 // pointer. 2805 MachineFrameInfo &MFI = DAG.getMachineFunction().getFrameInfo(); 2806 EVT ValTy = Op->getValueType(0); 2807 int FI = MFI.CreateFixedObject(Op.getValueSizeInBits() / 8, 0, false); 2808 return DAG.getFrameIndex(FI, ValTy); 2809 } 2810 2811 SDValue MipsTargetLowering::lowerFP_TO_SINT(SDValue Op, 2812 SelectionDAG &DAG) const { 2813 if (Op.getValueSizeInBits() > 32 && Subtarget.isSingleFloat()) 2814 return SDValue(); 2815 2816 EVT FPTy = EVT::getFloatingPointVT(Op.getValueSizeInBits()); 2817 SDValue Trunc = DAG.getNode(MipsISD::TruncIntFP, SDLoc(Op), FPTy, 2818 Op.getOperand(0)); 2819 return DAG.getNode(ISD::BITCAST, SDLoc(Op), Op.getValueType(), Trunc); 2820 } 2821 2822 //===----------------------------------------------------------------------===// 2823 // Calling Convention Implementation 2824 //===----------------------------------------------------------------------===// 2825 2826 //===----------------------------------------------------------------------===// 2827 // TODO: Implement a generic logic using tblgen that can support this. 2828 // Mips O32 ABI rules: 2829 // --- 2830 // i32 - Passed in A0, A1, A2, A3 and stack 2831 // f32 - Only passed in f32 registers if no int reg has been used yet to hold 2832 // an argument. Otherwise, passed in A1, A2, A3 and stack. 2833 // f64 - Only passed in two aliased f32 registers if no int reg has been used 2834 // yet to hold an argument. Otherwise, use A2, A3 and stack. If A1 is 2835 // not used, it must be shadowed. If only A3 is available, shadow it and 2836 // go to stack. 2837 // vXiX - Received as scalarized i32s, passed in A0 - A3 and the stack. 2838 // vXf32 - Passed in either a pair of registers {A0, A1}, {A2, A3} or {A0 - A3} 2839 // with the remainder spilled to the stack. 2840 // vXf64 - Passed in either {A0, A1, A2, A3} or {A2, A3} and in both cases 2841 // spilling the remainder to the stack. 2842 // 2843 // For vararg functions, all arguments are passed in A0, A1, A2, A3 and stack. 2844 //===----------------------------------------------------------------------===// 2845 2846 static bool CC_MipsO32(unsigned ValNo, MVT ValVT, MVT LocVT, 2847 CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, 2848 CCState &State, ArrayRef<MCPhysReg> F64Regs) { 2849 const MipsSubtarget &Subtarget = static_cast<const MipsSubtarget &>( 2850 State.getMachineFunction().getSubtarget()); 2851 2852 static const MCPhysReg IntRegs[] = { Mips::A0, Mips::A1, Mips::A2, Mips::A3 }; 2853 2854 const MipsCCState * MipsState = static_cast<MipsCCState *>(&State); 2855 2856 static const MCPhysReg F32Regs[] = { Mips::F12, Mips::F14 }; 2857 2858 static const MCPhysReg FloatVectorIntRegs[] = { Mips::A0, Mips::A2 }; 2859 2860 // Do not process byval args here. 2861 if (ArgFlags.isByVal()) 2862 return true; 2863 2864 // Promote i8 and i16 2865 if (ArgFlags.isInReg() && !Subtarget.isLittle()) { 2866 if (LocVT == MVT::i8 || LocVT == MVT::i16 || LocVT == MVT::i32) { 2867 LocVT = MVT::i32; 2868 if (ArgFlags.isSExt()) 2869 LocInfo = CCValAssign::SExtUpper; 2870 else if (ArgFlags.isZExt()) 2871 LocInfo = CCValAssign::ZExtUpper; 2872 else 2873 LocInfo = CCValAssign::AExtUpper; 2874 } 2875 } 2876 2877 // Promote i8 and i16 2878 if (LocVT == MVT::i8 || LocVT == MVT::i16) { 2879 LocVT = MVT::i32; 2880 if (ArgFlags.isSExt()) 2881 LocInfo = CCValAssign::SExt; 2882 else if (ArgFlags.isZExt()) 2883 LocInfo = CCValAssign::ZExt; 2884 else 2885 LocInfo = CCValAssign::AExt; 2886 } 2887 2888 unsigned Reg; 2889 2890 // f32 and f64 are allocated in A0, A1, A2, A3 when either of the following 2891 // is true: function is vararg, argument is 3rd or higher, there is previous 2892 // argument which is not f32 or f64. 2893 bool AllocateFloatsInIntReg = State.isVarArg() || ValNo > 1 || 2894 State.getFirstUnallocated(F32Regs) != ValNo; 2895 Align OrigAlign = ArgFlags.getNonZeroOrigAlign(); 2896 bool isI64 = (ValVT == MVT::i32 && OrigAlign == Align(8)); 2897 bool isVectorFloat = MipsState->WasOriginalArgVectorFloat(ValNo); 2898 2899 // The MIPS vector ABI for floats passes them in a pair of registers 2900 if (ValVT == MVT::i32 && isVectorFloat) { 2901 // This is the start of an vector that was scalarized into an unknown number 2902 // of components. It doesn't matter how many there are. Allocate one of the 2903 // notional 8 byte aligned registers which map onto the argument stack, and 2904 // shadow the register lost to alignment requirements. 2905 if (ArgFlags.isSplit()) { 2906 Reg = State.AllocateReg(FloatVectorIntRegs); 2907 if (Reg == Mips::A2) 2908 State.AllocateReg(Mips::A1); 2909 else if (Reg == 0) 2910 State.AllocateReg(Mips::A3); 2911 } else { 2912 // If we're an intermediate component of the split, we can just attempt to 2913 // allocate a register directly. 2914 Reg = State.AllocateReg(IntRegs); 2915 } 2916 } else if (ValVT == MVT::i32 || 2917 (ValVT == MVT::f32 && AllocateFloatsInIntReg)) { 2918 Reg = State.AllocateReg(IntRegs); 2919 // If this is the first part of an i64 arg, 2920 // the allocated register must be either A0 or A2. 2921 if (isI64 && (Reg == Mips::A1 || Reg == Mips::A3)) 2922 Reg = State.AllocateReg(IntRegs); 2923 LocVT = MVT::i32; 2924 } else if (ValVT == MVT::f64 && AllocateFloatsInIntReg) { 2925 LocVT = MVT::i32; 2926 2927 // Allocate int register and shadow next int register. If first 2928 // available register is Mips::A1 or Mips::A3, shadow it too. 2929 Reg = State.AllocateReg(IntRegs); 2930 if (Reg == Mips::A1 || Reg == Mips::A3) 2931 Reg = State.AllocateReg(IntRegs); 2932 2933 if (Reg) { 2934 State.addLoc( 2935 CCValAssign::getCustomReg(ValNo, ValVT, Reg, LocVT, LocInfo)); 2936 MCRegister HiReg = State.AllocateReg(IntRegs); 2937 assert(HiReg); 2938 State.addLoc( 2939 CCValAssign::getCustomReg(ValNo, ValVT, HiReg, LocVT, LocInfo)); 2940 return false; 2941 } 2942 } else if (ValVT.isFloatingPoint() && !AllocateFloatsInIntReg) { 2943 // we are guaranteed to find an available float register 2944 if (ValVT == MVT::f32) { 2945 Reg = State.AllocateReg(F32Regs); 2946 // Shadow int register 2947 State.AllocateReg(IntRegs); 2948 } else { 2949 Reg = State.AllocateReg(F64Regs); 2950 // Shadow int registers 2951 unsigned Reg2 = State.AllocateReg(IntRegs); 2952 if (Reg2 == Mips::A1 || Reg2 == Mips::A3) 2953 State.AllocateReg(IntRegs); 2954 State.AllocateReg(IntRegs); 2955 } 2956 } else 2957 llvm_unreachable("Cannot handle this ValVT."); 2958 2959 if (!Reg) { 2960 unsigned Offset = State.AllocateStack(ValVT.getStoreSize(), OrigAlign); 2961 State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo)); 2962 } else 2963 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); 2964 2965 return false; 2966 } 2967 2968 static bool CC_MipsO32_FP32(unsigned ValNo, MVT ValVT, 2969 MVT LocVT, CCValAssign::LocInfo LocInfo, 2970 ISD::ArgFlagsTy ArgFlags, CCState &State) { 2971 static const MCPhysReg F64Regs[] = { Mips::D6, Mips::D7 }; 2972 2973 return CC_MipsO32(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State, F64Regs); 2974 } 2975 2976 static bool CC_MipsO32_FP64(unsigned ValNo, MVT ValVT, 2977 MVT LocVT, CCValAssign::LocInfo LocInfo, 2978 ISD::ArgFlagsTy ArgFlags, CCState &State) { 2979 static const MCPhysReg F64Regs[] = { Mips::D12_64, Mips::D14_64 }; 2980 2981 return CC_MipsO32(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State, F64Regs); 2982 } 2983 2984 static bool CC_MipsO32(unsigned ValNo, MVT ValVT, MVT LocVT, 2985 CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, 2986 CCState &State) LLVM_ATTRIBUTE_UNUSED; 2987 2988 #include "MipsGenCallingConv.inc" 2989 2990 CCAssignFn *MipsTargetLowering::CCAssignFnForCall() const{ 2991 return CC_Mips_FixedArg; 2992 } 2993 2994 CCAssignFn *MipsTargetLowering::CCAssignFnForReturn() const{ 2995 return RetCC_Mips; 2996 } 2997 //===----------------------------------------------------------------------===// 2998 // Call Calling Convention Implementation 2999 //===----------------------------------------------------------------------===// 3000 3001 SDValue MipsTargetLowering::passArgOnStack(SDValue StackPtr, unsigned Offset, 3002 SDValue Chain, SDValue Arg, 3003 const SDLoc &DL, bool IsTailCall, 3004 SelectionDAG &DAG) const { 3005 if (!IsTailCall) { 3006 SDValue PtrOff = 3007 DAG.getNode(ISD::ADD, DL, getPointerTy(DAG.getDataLayout()), StackPtr, 3008 DAG.getIntPtrConstant(Offset, DL)); 3009 return DAG.getStore(Chain, DL, Arg, PtrOff, MachinePointerInfo()); 3010 } 3011 3012 MachineFrameInfo &MFI = DAG.getMachineFunction().getFrameInfo(); 3013 int FI = MFI.CreateFixedObject(Arg.getValueSizeInBits() / 8, Offset, false); 3014 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy(DAG.getDataLayout())); 3015 return DAG.getStore(Chain, DL, Arg, FIN, MachinePointerInfo(), MaybeAlign(), 3016 MachineMemOperand::MOVolatile); 3017 } 3018 3019 void MipsTargetLowering:: 3020 getOpndList(SmallVectorImpl<SDValue> &Ops, 3021 std::deque<std::pair<unsigned, SDValue>> &RegsToPass, 3022 bool IsPICCall, bool GlobalOrExternal, bool InternalLinkage, 3023 bool IsCallReloc, CallLoweringInfo &CLI, SDValue Callee, 3024 SDValue Chain) const { 3025 // Insert node "GP copy globalreg" before call to function. 3026 // 3027 // R_MIPS_CALL* operators (emitted when non-internal functions are called 3028 // in PIC mode) allow symbols to be resolved via lazy binding. 3029 // The lazy binding stub requires GP to point to the GOT. 3030 // Note that we don't need GP to point to the GOT for indirect calls 3031 // (when R_MIPS_CALL* is not used for the call) because Mips linker generates 3032 // lazy binding stub for a function only when R_MIPS_CALL* are the only relocs 3033 // used for the function (that is, Mips linker doesn't generate lazy binding 3034 // stub for a function whose address is taken in the program). 3035 if (IsPICCall && !InternalLinkage && IsCallReloc) { 3036 unsigned GPReg = ABI.IsN64() ? Mips::GP_64 : Mips::GP; 3037 EVT Ty = ABI.IsN64() ? MVT::i64 : MVT::i32; 3038 RegsToPass.push_back(std::make_pair(GPReg, getGlobalReg(CLI.DAG, Ty))); 3039 } 3040 3041 // Build a sequence of copy-to-reg nodes chained together with token 3042 // chain and flag operands which copy the outgoing args into registers. 3043 // The InFlag in necessary since all emitted instructions must be 3044 // stuck together. 3045 SDValue InFlag; 3046 3047 for (auto &R : RegsToPass) { 3048 Chain = CLI.DAG.getCopyToReg(Chain, CLI.DL, R.first, R.second, InFlag); 3049 InFlag = Chain.getValue(1); 3050 } 3051 3052 // Add argument registers to the end of the list so that they are 3053 // known live into the call. 3054 for (auto &R : RegsToPass) 3055 Ops.push_back(CLI.DAG.getRegister(R.first, R.second.getValueType())); 3056 3057 // Add a register mask operand representing the call-preserved registers. 3058 const TargetRegisterInfo *TRI = Subtarget.getRegisterInfo(); 3059 const uint32_t *Mask = 3060 TRI->getCallPreservedMask(CLI.DAG.getMachineFunction(), CLI.CallConv); 3061 assert(Mask && "Missing call preserved mask for calling convention"); 3062 if (Subtarget.inMips16HardFloat()) { 3063 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(CLI.Callee)) { 3064 StringRef Sym = G->getGlobal()->getName(); 3065 Function *F = G->getGlobal()->getParent()->getFunction(Sym); 3066 if (F && F->hasFnAttribute("__Mips16RetHelper")) { 3067 Mask = MipsRegisterInfo::getMips16RetHelperMask(); 3068 } 3069 } 3070 } 3071 Ops.push_back(CLI.DAG.getRegisterMask(Mask)); 3072 3073 if (InFlag.getNode()) 3074 Ops.push_back(InFlag); 3075 } 3076 3077 void MipsTargetLowering::AdjustInstrPostInstrSelection(MachineInstr &MI, 3078 SDNode *Node) const { 3079 switch (MI.getOpcode()) { 3080 default: 3081 return; 3082 case Mips::JALR: 3083 case Mips::JALRPseudo: 3084 case Mips::JALR64: 3085 case Mips::JALR64Pseudo: 3086 case Mips::JALR16_MM: 3087 case Mips::JALRC16_MMR6: 3088 case Mips::TAILCALLREG: 3089 case Mips::TAILCALLREG64: 3090 case Mips::TAILCALLR6REG: 3091 case Mips::TAILCALL64R6REG: 3092 case Mips::TAILCALLREG_MM: 3093 case Mips::TAILCALLREG_MMR6: { 3094 if (!EmitJalrReloc || 3095 Subtarget.inMips16Mode() || 3096 !isPositionIndependent() || 3097 Node->getNumOperands() < 1 || 3098 Node->getOperand(0).getNumOperands() < 2) { 3099 return; 3100 } 3101 // We are after the callee address, set by LowerCall(). 3102 // If added to MI, asm printer will emit .reloc R_MIPS_JALR for the 3103 // symbol. 3104 const SDValue TargetAddr = Node->getOperand(0).getOperand(1); 3105 StringRef Sym; 3106 if (const GlobalAddressSDNode *G = 3107 dyn_cast_or_null<const GlobalAddressSDNode>(TargetAddr)) { 3108 // We must not emit the R_MIPS_JALR relocation against data symbols 3109 // since this will cause run-time crashes if the linker replaces the 3110 // call instruction with a relative branch to the data symbol. 3111 if (!isa<Function>(G->getGlobal())) { 3112 LLVM_DEBUG(dbgs() << "Not adding R_MIPS_JALR against data symbol " 3113 << G->getGlobal()->getName() << "\n"); 3114 return; 3115 } 3116 Sym = G->getGlobal()->getName(); 3117 } 3118 else if (const ExternalSymbolSDNode *ES = 3119 dyn_cast_or_null<const ExternalSymbolSDNode>(TargetAddr)) { 3120 Sym = ES->getSymbol(); 3121 } 3122 3123 if (Sym.empty()) 3124 return; 3125 3126 MachineFunction *MF = MI.getParent()->getParent(); 3127 MCSymbol *S = MF->getContext().getOrCreateSymbol(Sym); 3128 LLVM_DEBUG(dbgs() << "Adding R_MIPS_JALR against " << Sym << "\n"); 3129 MI.addOperand(MachineOperand::CreateMCSymbol(S, MipsII::MO_JALR)); 3130 } 3131 } 3132 } 3133 3134 /// LowerCall - functions arguments are copied from virtual regs to 3135 /// (physical regs)/(stack frame), CALLSEQ_START and CALLSEQ_END are emitted. 3136 SDValue 3137 MipsTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI, 3138 SmallVectorImpl<SDValue> &InVals) const { 3139 SelectionDAG &DAG = CLI.DAG; 3140 SDLoc DL = CLI.DL; 3141 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs; 3142 SmallVectorImpl<SDValue> &OutVals = CLI.OutVals; 3143 SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins; 3144 SDValue Chain = CLI.Chain; 3145 SDValue Callee = CLI.Callee; 3146 bool &IsTailCall = CLI.IsTailCall; 3147 CallingConv::ID CallConv = CLI.CallConv; 3148 bool IsVarArg = CLI.IsVarArg; 3149 3150 MachineFunction &MF = DAG.getMachineFunction(); 3151 MachineFrameInfo &MFI = MF.getFrameInfo(); 3152 const TargetFrameLowering *TFL = Subtarget.getFrameLowering(); 3153 MipsFunctionInfo *FuncInfo = MF.getInfo<MipsFunctionInfo>(); 3154 bool IsPIC = isPositionIndependent(); 3155 3156 // Analyze operands of the call, assigning locations to each operand. 3157 SmallVector<CCValAssign, 16> ArgLocs; 3158 MipsCCState CCInfo( 3159 CallConv, IsVarArg, DAG.getMachineFunction(), ArgLocs, *DAG.getContext(), 3160 MipsCCState::getSpecialCallingConvForCallee(Callee.getNode(), Subtarget)); 3161 3162 const ExternalSymbolSDNode *ES = 3163 dyn_cast_or_null<const ExternalSymbolSDNode>(Callee.getNode()); 3164 3165 // There is one case where CALLSEQ_START..CALLSEQ_END can be nested, which 3166 // is during the lowering of a call with a byval argument which produces 3167 // a call to memcpy. For the O32 case, this causes the caller to allocate 3168 // stack space for the reserved argument area for the callee, then recursively 3169 // again for the memcpy call. In the NEWABI case, this doesn't occur as those 3170 // ABIs mandate that the callee allocates the reserved argument area. We do 3171 // still produce nested CALLSEQ_START..CALLSEQ_END with zero space though. 3172 // 3173 // If the callee has a byval argument and memcpy is used, we are mandated 3174 // to already have produced a reserved argument area for the callee for O32. 3175 // Therefore, the reserved argument area can be reused for both calls. 3176 // 3177 // Other cases of calling memcpy cannot have a chain with a CALLSEQ_START 3178 // present, as we have yet to hook that node onto the chain. 3179 // 3180 // Hence, the CALLSEQ_START and CALLSEQ_END nodes can be eliminated in this 3181 // case. GCC does a similar trick, in that wherever possible, it calculates 3182 // the maximum out going argument area (including the reserved area), and 3183 // preallocates the stack space on entrance to the caller. 3184 // 3185 // FIXME: We should do the same for efficiency and space. 3186 3187 // Note: The check on the calling convention below must match 3188 // MipsABIInfo::GetCalleeAllocdArgSizeInBytes(). 3189 bool MemcpyInByVal = ES && 3190 StringRef(ES->getSymbol()) == StringRef("memcpy") && 3191 CallConv != CallingConv::Fast && 3192 Chain.getOpcode() == ISD::CALLSEQ_START; 3193 3194 // Allocate the reserved argument area. It seems strange to do this from the 3195 // caller side but removing it breaks the frame size calculation. 3196 unsigned ReservedArgArea = 3197 MemcpyInByVal ? 0 : ABI.GetCalleeAllocdArgSizeInBytes(CallConv); 3198 CCInfo.AllocateStack(ReservedArgArea, Align(1)); 3199 3200 CCInfo.AnalyzeCallOperands(Outs, CC_Mips, CLI.getArgs(), 3201 ES ? ES->getSymbol() : nullptr); 3202 3203 // Get a count of how many bytes are to be pushed on the stack. 3204 unsigned NextStackOffset = CCInfo.getNextStackOffset(); 3205 3206 // Call site info for function parameters tracking. 3207 MachineFunction::CallSiteInfo CSInfo; 3208 3209 // Check if it's really possible to do a tail call. Restrict it to functions 3210 // that are part of this compilation unit. 3211 bool InternalLinkage = false; 3212 if (IsTailCall) { 3213 IsTailCall = isEligibleForTailCallOptimization( 3214 CCInfo, NextStackOffset, *MF.getInfo<MipsFunctionInfo>()); 3215 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) { 3216 InternalLinkage = G->getGlobal()->hasInternalLinkage(); 3217 IsTailCall &= (InternalLinkage || G->getGlobal()->hasLocalLinkage() || 3218 G->getGlobal()->hasPrivateLinkage() || 3219 G->getGlobal()->hasHiddenVisibility() || 3220 G->getGlobal()->hasProtectedVisibility()); 3221 } 3222 } 3223 if (!IsTailCall && CLI.CB && CLI.CB->isMustTailCall()) 3224 report_fatal_error("failed to perform tail call elimination on a call " 3225 "site marked musttail"); 3226 3227 if (IsTailCall) 3228 ++NumTailCalls; 3229 3230 // Chain is the output chain of the last Load/Store or CopyToReg node. 3231 // ByValChain is the output chain of the last Memcpy node created for copying 3232 // byval arguments to the stack. 3233 unsigned StackAlignment = TFL->getStackAlignment(); 3234 NextStackOffset = alignTo(NextStackOffset, StackAlignment); 3235 SDValue NextStackOffsetVal = DAG.getIntPtrConstant(NextStackOffset, DL, true); 3236 3237 if (!(IsTailCall || MemcpyInByVal)) 3238 Chain = DAG.getCALLSEQ_START(Chain, NextStackOffset, 0, DL); 3239 3240 SDValue StackPtr = 3241 DAG.getCopyFromReg(Chain, DL, ABI.IsN64() ? Mips::SP_64 : Mips::SP, 3242 getPointerTy(DAG.getDataLayout())); 3243 3244 std::deque<std::pair<unsigned, SDValue>> RegsToPass; 3245 SmallVector<SDValue, 8> MemOpChains; 3246 3247 CCInfo.rewindByValRegsInfo(); 3248 3249 // Walk the register/memloc assignments, inserting copies/loads. 3250 for (unsigned i = 0, e = ArgLocs.size(), OutIdx = 0; i != e; ++i, ++OutIdx) { 3251 SDValue Arg = OutVals[OutIdx]; 3252 CCValAssign &VA = ArgLocs[i]; 3253 MVT ValVT = VA.getValVT(), LocVT = VA.getLocVT(); 3254 ISD::ArgFlagsTy Flags = Outs[OutIdx].Flags; 3255 bool UseUpperBits = false; 3256 3257 // ByVal Arg. 3258 if (Flags.isByVal()) { 3259 unsigned FirstByValReg, LastByValReg; 3260 unsigned ByValIdx = CCInfo.getInRegsParamsProcessed(); 3261 CCInfo.getInRegsParamInfo(ByValIdx, FirstByValReg, LastByValReg); 3262 3263 assert(Flags.getByValSize() && 3264 "ByVal args of size 0 should have been ignored by front-end."); 3265 assert(ByValIdx < CCInfo.getInRegsParamsCount()); 3266 assert(!IsTailCall && 3267 "Do not tail-call optimize if there is a byval argument."); 3268 passByValArg(Chain, DL, RegsToPass, MemOpChains, StackPtr, MFI, DAG, Arg, 3269 FirstByValReg, LastByValReg, Flags, Subtarget.isLittle(), 3270 VA); 3271 CCInfo.nextInRegsParam(); 3272 continue; 3273 } 3274 3275 // Promote the value if needed. 3276 switch (VA.getLocInfo()) { 3277 default: 3278 llvm_unreachable("Unknown loc info!"); 3279 case CCValAssign::Full: 3280 if (VA.isRegLoc()) { 3281 if ((ValVT == MVT::f32 && LocVT == MVT::i32) || 3282 (ValVT == MVT::f64 && LocVT == MVT::i64) || 3283 (ValVT == MVT::i64 && LocVT == MVT::f64)) 3284 Arg = DAG.getNode(ISD::BITCAST, DL, LocVT, Arg); 3285 else if (ValVT == MVT::f64 && LocVT == MVT::i32) { 3286 SDValue Lo = DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32, 3287 Arg, DAG.getConstant(0, DL, MVT::i32)); 3288 SDValue Hi = DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32, 3289 Arg, DAG.getConstant(1, DL, MVT::i32)); 3290 if (!Subtarget.isLittle()) 3291 std::swap(Lo, Hi); 3292 3293 assert(VA.needsCustom()); 3294 3295 Register LocRegLo = VA.getLocReg(); 3296 Register LocRegHigh = ArgLocs[++i].getLocReg(); 3297 RegsToPass.push_back(std::make_pair(LocRegLo, Lo)); 3298 RegsToPass.push_back(std::make_pair(LocRegHigh, Hi)); 3299 continue; 3300 } 3301 } 3302 break; 3303 case CCValAssign::BCvt: 3304 Arg = DAG.getNode(ISD::BITCAST, DL, LocVT, Arg); 3305 break; 3306 case CCValAssign::SExtUpper: 3307 UseUpperBits = true; 3308 LLVM_FALLTHROUGH; 3309 case CCValAssign::SExt: 3310 Arg = DAG.getNode(ISD::SIGN_EXTEND, DL, LocVT, Arg); 3311 break; 3312 case CCValAssign::ZExtUpper: 3313 UseUpperBits = true; 3314 LLVM_FALLTHROUGH; 3315 case CCValAssign::ZExt: 3316 Arg = DAG.getNode(ISD::ZERO_EXTEND, DL, LocVT, Arg); 3317 break; 3318 case CCValAssign::AExtUpper: 3319 UseUpperBits = true; 3320 LLVM_FALLTHROUGH; 3321 case CCValAssign::AExt: 3322 Arg = DAG.getNode(ISD::ANY_EXTEND, DL, LocVT, Arg); 3323 break; 3324 } 3325 3326 if (UseUpperBits) { 3327 unsigned ValSizeInBits = Outs[OutIdx].ArgVT.getSizeInBits(); 3328 unsigned LocSizeInBits = VA.getLocVT().getSizeInBits(); 3329 Arg = DAG.getNode( 3330 ISD::SHL, DL, VA.getLocVT(), Arg, 3331 DAG.getConstant(LocSizeInBits - ValSizeInBits, DL, VA.getLocVT())); 3332 } 3333 3334 // Arguments that can be passed on register must be kept at 3335 // RegsToPass vector 3336 if (VA.isRegLoc()) { 3337 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg)); 3338 3339 // If the parameter is passed through reg $D, which splits into 3340 // two physical registers, avoid creating call site info. 3341 if (Mips::AFGR64RegClass.contains(VA.getLocReg())) 3342 continue; 3343 3344 // Collect CSInfo about which register passes which parameter. 3345 const TargetOptions &Options = DAG.getTarget().Options; 3346 if (Options.SupportsDebugEntryValues) 3347 CSInfo.emplace_back(VA.getLocReg(), i); 3348 3349 continue; 3350 } 3351 3352 // Register can't get to this point... 3353 assert(VA.isMemLoc()); 3354 3355 // emit ISD::STORE whichs stores the 3356 // parameter value to a stack Location 3357 MemOpChains.push_back(passArgOnStack(StackPtr, VA.getLocMemOffset(), 3358 Chain, Arg, DL, IsTailCall, DAG)); 3359 } 3360 3361 // Transform all store nodes into one single node because all store 3362 // nodes are independent of each other. 3363 if (!MemOpChains.empty()) 3364 Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, MemOpChains); 3365 3366 // If the callee is a GlobalAddress/ExternalSymbol node (quite common, every 3367 // direct call is) turn it into a TargetGlobalAddress/TargetExternalSymbol 3368 // node so that legalize doesn't hack it. 3369 3370 EVT Ty = Callee.getValueType(); 3371 bool GlobalOrExternal = false, IsCallReloc = false; 3372 3373 // The long-calls feature is ignored in case of PIC. 3374 // While we do not support -mshared / -mno-shared properly, 3375 // ignore long-calls in case of -mabicalls too. 3376 if (!Subtarget.isABICalls() && !IsPIC) { 3377 // If the function should be called using "long call", 3378 // get its address into a register to prevent using 3379 // of the `jal` instruction for the direct call. 3380 if (auto *N = dyn_cast<ExternalSymbolSDNode>(Callee)) { 3381 if (Subtarget.useLongCalls()) 3382 Callee = Subtarget.hasSym32() 3383 ? getAddrNonPIC(N, SDLoc(N), Ty, DAG) 3384 : getAddrNonPICSym64(N, SDLoc(N), Ty, DAG); 3385 } else if (auto *N = dyn_cast<GlobalAddressSDNode>(Callee)) { 3386 bool UseLongCalls = Subtarget.useLongCalls(); 3387 // If the function has long-call/far/near attribute 3388 // it overrides command line switch pased to the backend. 3389 if (auto *F = dyn_cast<Function>(N->getGlobal())) { 3390 if (F->hasFnAttribute("long-call")) 3391 UseLongCalls = true; 3392 else if (F->hasFnAttribute("short-call")) 3393 UseLongCalls = false; 3394 } 3395 if (UseLongCalls) 3396 Callee = Subtarget.hasSym32() 3397 ? getAddrNonPIC(N, SDLoc(N), Ty, DAG) 3398 : getAddrNonPICSym64(N, SDLoc(N), Ty, DAG); 3399 } 3400 } 3401 3402 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) { 3403 if (IsPIC) { 3404 const GlobalValue *Val = G->getGlobal(); 3405 InternalLinkage = Val->hasInternalLinkage(); 3406 3407 if (InternalLinkage) 3408 Callee = getAddrLocal(G, DL, Ty, DAG, ABI.IsN32() || ABI.IsN64()); 3409 else if (Subtarget.useXGOT()) { 3410 Callee = getAddrGlobalLargeGOT(G, DL, Ty, DAG, MipsII::MO_CALL_HI16, 3411 MipsII::MO_CALL_LO16, Chain, 3412 FuncInfo->callPtrInfo(MF, Val)); 3413 IsCallReloc = true; 3414 } else { 3415 Callee = getAddrGlobal(G, DL, Ty, DAG, MipsII::MO_GOT_CALL, Chain, 3416 FuncInfo->callPtrInfo(MF, Val)); 3417 IsCallReloc = true; 3418 } 3419 } else 3420 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), DL, 3421 getPointerTy(DAG.getDataLayout()), 0, 3422 MipsII::MO_NO_FLAG); 3423 GlobalOrExternal = true; 3424 } 3425 else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) { 3426 const char *Sym = S->getSymbol(); 3427 3428 if (!IsPIC) // static 3429 Callee = DAG.getTargetExternalSymbol( 3430 Sym, getPointerTy(DAG.getDataLayout()), MipsII::MO_NO_FLAG); 3431 else if (Subtarget.useXGOT()) { 3432 Callee = getAddrGlobalLargeGOT(S, DL, Ty, DAG, MipsII::MO_CALL_HI16, 3433 MipsII::MO_CALL_LO16, Chain, 3434 FuncInfo->callPtrInfo(MF, Sym)); 3435 IsCallReloc = true; 3436 } else { // PIC 3437 Callee = getAddrGlobal(S, DL, Ty, DAG, MipsII::MO_GOT_CALL, Chain, 3438 FuncInfo->callPtrInfo(MF, Sym)); 3439 IsCallReloc = true; 3440 } 3441 3442 GlobalOrExternal = true; 3443 } 3444 3445 SmallVector<SDValue, 8> Ops(1, Chain); 3446 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue); 3447 3448 getOpndList(Ops, RegsToPass, IsPIC, GlobalOrExternal, InternalLinkage, 3449 IsCallReloc, CLI, Callee, Chain); 3450 3451 if (IsTailCall) { 3452 MF.getFrameInfo().setHasTailCall(); 3453 SDValue Ret = DAG.getNode(MipsISD::TailCall, DL, MVT::Other, Ops); 3454 DAG.addCallSiteInfo(Ret.getNode(), std::move(CSInfo)); 3455 return Ret; 3456 } 3457 3458 Chain = DAG.getNode(MipsISD::JmpLink, DL, NodeTys, Ops); 3459 SDValue InFlag = Chain.getValue(1); 3460 3461 DAG.addCallSiteInfo(Chain.getNode(), std::move(CSInfo)); 3462 3463 // Create the CALLSEQ_END node in the case of where it is not a call to 3464 // memcpy. 3465 if (!(MemcpyInByVal)) { 3466 Chain = DAG.getCALLSEQ_END(Chain, NextStackOffsetVal, 3467 DAG.getIntPtrConstant(0, DL, true), InFlag, DL); 3468 InFlag = Chain.getValue(1); 3469 } 3470 3471 // Handle result values, copying them out of physregs into vregs that we 3472 // return. 3473 return LowerCallResult(Chain, InFlag, CallConv, IsVarArg, Ins, DL, DAG, 3474 InVals, CLI); 3475 } 3476 3477 /// LowerCallResult - Lower the result values of a call into the 3478 /// appropriate copies out of appropriate physical registers. 3479 SDValue MipsTargetLowering::LowerCallResult( 3480 SDValue Chain, SDValue InFlag, CallingConv::ID CallConv, bool IsVarArg, 3481 const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &DL, 3482 SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals, 3483 TargetLowering::CallLoweringInfo &CLI) const { 3484 // Assign locations to each value returned by this call. 3485 SmallVector<CCValAssign, 16> RVLocs; 3486 MipsCCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), RVLocs, 3487 *DAG.getContext()); 3488 3489 const ExternalSymbolSDNode *ES = 3490 dyn_cast_or_null<const ExternalSymbolSDNode>(CLI.Callee.getNode()); 3491 CCInfo.AnalyzeCallResult(Ins, RetCC_Mips, CLI.RetTy, 3492 ES ? ES->getSymbol() : nullptr); 3493 3494 // Copy all of the result registers out of their specified physreg. 3495 for (unsigned i = 0; i != RVLocs.size(); ++i) { 3496 CCValAssign &VA = RVLocs[i]; 3497 assert(VA.isRegLoc() && "Can only return in registers!"); 3498 3499 SDValue Val = DAG.getCopyFromReg(Chain, DL, RVLocs[i].getLocReg(), 3500 RVLocs[i].getLocVT(), InFlag); 3501 Chain = Val.getValue(1); 3502 InFlag = Val.getValue(2); 3503 3504 if (VA.isUpperBitsInLoc()) { 3505 unsigned ValSizeInBits = Ins[i].ArgVT.getSizeInBits(); 3506 unsigned LocSizeInBits = VA.getLocVT().getSizeInBits(); 3507 unsigned Shift = 3508 VA.getLocInfo() == CCValAssign::ZExtUpper ? ISD::SRL : ISD::SRA; 3509 Val = DAG.getNode( 3510 Shift, DL, VA.getLocVT(), Val, 3511 DAG.getConstant(LocSizeInBits - ValSizeInBits, DL, VA.getLocVT())); 3512 } 3513 3514 switch (VA.getLocInfo()) { 3515 default: 3516 llvm_unreachable("Unknown loc info!"); 3517 case CCValAssign::Full: 3518 break; 3519 case CCValAssign::BCvt: 3520 Val = DAG.getNode(ISD::BITCAST, DL, VA.getValVT(), Val); 3521 break; 3522 case CCValAssign::AExt: 3523 case CCValAssign::AExtUpper: 3524 Val = DAG.getNode(ISD::TRUNCATE, DL, VA.getValVT(), Val); 3525 break; 3526 case CCValAssign::ZExt: 3527 case CCValAssign::ZExtUpper: 3528 Val = DAG.getNode(ISD::AssertZext, DL, VA.getLocVT(), Val, 3529 DAG.getValueType(VA.getValVT())); 3530 Val = DAG.getNode(ISD::TRUNCATE, DL, VA.getValVT(), Val); 3531 break; 3532 case CCValAssign::SExt: 3533 case CCValAssign::SExtUpper: 3534 Val = DAG.getNode(ISD::AssertSext, DL, VA.getLocVT(), Val, 3535 DAG.getValueType(VA.getValVT())); 3536 Val = DAG.getNode(ISD::TRUNCATE, DL, VA.getValVT(), Val); 3537 break; 3538 } 3539 3540 InVals.push_back(Val); 3541 } 3542 3543 return Chain; 3544 } 3545 3546 static SDValue UnpackFromArgumentSlot(SDValue Val, const CCValAssign &VA, 3547 EVT ArgVT, const SDLoc &DL, 3548 SelectionDAG &DAG) { 3549 MVT LocVT = VA.getLocVT(); 3550 EVT ValVT = VA.getValVT(); 3551 3552 // Shift into the upper bits if necessary. 3553 switch (VA.getLocInfo()) { 3554 default: 3555 break; 3556 case CCValAssign::AExtUpper: 3557 case CCValAssign::SExtUpper: 3558 case CCValAssign::ZExtUpper: { 3559 unsigned ValSizeInBits = ArgVT.getSizeInBits(); 3560 unsigned LocSizeInBits = VA.getLocVT().getSizeInBits(); 3561 unsigned Opcode = 3562 VA.getLocInfo() == CCValAssign::ZExtUpper ? ISD::SRL : ISD::SRA; 3563 Val = DAG.getNode( 3564 Opcode, DL, VA.getLocVT(), Val, 3565 DAG.getConstant(LocSizeInBits - ValSizeInBits, DL, VA.getLocVT())); 3566 break; 3567 } 3568 } 3569 3570 // If this is an value smaller than the argument slot size (32-bit for O32, 3571 // 64-bit for N32/N64), it has been promoted in some way to the argument slot 3572 // size. Extract the value and insert any appropriate assertions regarding 3573 // sign/zero extension. 3574 switch (VA.getLocInfo()) { 3575 default: 3576 llvm_unreachable("Unknown loc info!"); 3577 case CCValAssign::Full: 3578 break; 3579 case CCValAssign::AExtUpper: 3580 case CCValAssign::AExt: 3581 Val = DAG.getNode(ISD::TRUNCATE, DL, ValVT, Val); 3582 break; 3583 case CCValAssign::SExtUpper: 3584 case CCValAssign::SExt: 3585 Val = DAG.getNode(ISD::AssertSext, DL, LocVT, Val, DAG.getValueType(ValVT)); 3586 Val = DAG.getNode(ISD::TRUNCATE, DL, ValVT, Val); 3587 break; 3588 case CCValAssign::ZExtUpper: 3589 case CCValAssign::ZExt: 3590 Val = DAG.getNode(ISD::AssertZext, DL, LocVT, Val, DAG.getValueType(ValVT)); 3591 Val = DAG.getNode(ISD::TRUNCATE, DL, ValVT, Val); 3592 break; 3593 case CCValAssign::BCvt: 3594 Val = DAG.getNode(ISD::BITCAST, DL, ValVT, Val); 3595 break; 3596 } 3597 3598 return Val; 3599 } 3600 3601 //===----------------------------------------------------------------------===// 3602 // Formal Arguments Calling Convention Implementation 3603 //===----------------------------------------------------------------------===// 3604 /// LowerFormalArguments - transform physical registers into virtual registers 3605 /// and generate load operations for arguments places on the stack. 3606 SDValue MipsTargetLowering::LowerFormalArguments( 3607 SDValue Chain, CallingConv::ID CallConv, bool IsVarArg, 3608 const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &DL, 3609 SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const { 3610 MachineFunction &MF = DAG.getMachineFunction(); 3611 MachineFrameInfo &MFI = MF.getFrameInfo(); 3612 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>(); 3613 3614 MipsFI->setVarArgsFrameIndex(0); 3615 3616 // Used with vargs to acumulate store chains. 3617 std::vector<SDValue> OutChains; 3618 3619 // Assign locations to all of the incoming arguments. 3620 SmallVector<CCValAssign, 16> ArgLocs; 3621 MipsCCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), ArgLocs, 3622 *DAG.getContext()); 3623 CCInfo.AllocateStack(ABI.GetCalleeAllocdArgSizeInBytes(CallConv), Align(1)); 3624 const Function &Func = DAG.getMachineFunction().getFunction(); 3625 Function::const_arg_iterator FuncArg = Func.arg_begin(); 3626 3627 if (Func.hasFnAttribute("interrupt") && !Func.arg_empty()) 3628 report_fatal_error( 3629 "Functions with the interrupt attribute cannot have arguments!"); 3630 3631 CCInfo.AnalyzeFormalArguments(Ins, CC_Mips_FixedArg); 3632 MipsFI->setFormalArgInfo(CCInfo.getNextStackOffset(), 3633 CCInfo.getInRegsParamsCount() > 0); 3634 3635 unsigned CurArgIdx = 0; 3636 CCInfo.rewindByValRegsInfo(); 3637 3638 for (unsigned i = 0, e = ArgLocs.size(), InsIdx = 0; i != e; ++i, ++InsIdx) { 3639 CCValAssign &VA = ArgLocs[i]; 3640 if (Ins[InsIdx].isOrigArg()) { 3641 std::advance(FuncArg, Ins[InsIdx].getOrigArgIndex() - CurArgIdx); 3642 CurArgIdx = Ins[InsIdx].getOrigArgIndex(); 3643 } 3644 EVT ValVT = VA.getValVT(); 3645 ISD::ArgFlagsTy Flags = Ins[InsIdx].Flags; 3646 bool IsRegLoc = VA.isRegLoc(); 3647 3648 if (Flags.isByVal()) { 3649 assert(Ins[InsIdx].isOrigArg() && "Byval arguments cannot be implicit"); 3650 unsigned FirstByValReg, LastByValReg; 3651 unsigned ByValIdx = CCInfo.getInRegsParamsProcessed(); 3652 CCInfo.getInRegsParamInfo(ByValIdx, FirstByValReg, LastByValReg); 3653 3654 assert(Flags.getByValSize() && 3655 "ByVal args of size 0 should have been ignored by front-end."); 3656 assert(ByValIdx < CCInfo.getInRegsParamsCount()); 3657 copyByValRegs(Chain, DL, OutChains, DAG, Flags, InVals, &*FuncArg, 3658 FirstByValReg, LastByValReg, VA, CCInfo); 3659 CCInfo.nextInRegsParam(); 3660 continue; 3661 } 3662 3663 // Arguments stored on registers 3664 if (IsRegLoc) { 3665 MVT RegVT = VA.getLocVT(); 3666 Register ArgReg = VA.getLocReg(); 3667 const TargetRegisterClass *RC = getRegClassFor(RegVT); 3668 3669 // Transform the arguments stored on 3670 // physical registers into virtual ones 3671 unsigned Reg = addLiveIn(DAG.getMachineFunction(), ArgReg, RC); 3672 SDValue ArgValue = DAG.getCopyFromReg(Chain, DL, Reg, RegVT); 3673 3674 ArgValue = 3675 UnpackFromArgumentSlot(ArgValue, VA, Ins[InsIdx].ArgVT, DL, DAG); 3676 3677 // Handle floating point arguments passed in integer registers and 3678 // long double arguments passed in floating point registers. 3679 if ((RegVT == MVT::i32 && ValVT == MVT::f32) || 3680 (RegVT == MVT::i64 && ValVT == MVT::f64) || 3681 (RegVT == MVT::f64 && ValVT == MVT::i64)) 3682 ArgValue = DAG.getNode(ISD::BITCAST, DL, ValVT, ArgValue); 3683 else if (ABI.IsO32() && RegVT == MVT::i32 && 3684 ValVT == MVT::f64) { 3685 assert(VA.needsCustom() && "Expected custom argument for f64 split"); 3686 CCValAssign &NextVA = ArgLocs[++i]; 3687 unsigned Reg2 = 3688 addLiveIn(DAG.getMachineFunction(), NextVA.getLocReg(), RC); 3689 SDValue ArgValue2 = DAG.getCopyFromReg(Chain, DL, Reg2, RegVT); 3690 if (!Subtarget.isLittle()) 3691 std::swap(ArgValue, ArgValue2); 3692 ArgValue = DAG.getNode(MipsISD::BuildPairF64, DL, MVT::f64, 3693 ArgValue, ArgValue2); 3694 } 3695 3696 InVals.push_back(ArgValue); 3697 } else { // VA.isRegLoc() 3698 MVT LocVT = VA.getLocVT(); 3699 3700 assert(!VA.needsCustom() && "unexpected custom memory argument"); 3701 3702 if (ABI.IsO32()) { 3703 // We ought to be able to use LocVT directly but O32 sets it to i32 3704 // when allocating floating point values to integer registers. 3705 // This shouldn't influence how we load the value into registers unless 3706 // we are targeting softfloat. 3707 if (VA.getValVT().isFloatingPoint() && !Subtarget.useSoftFloat()) 3708 LocVT = VA.getValVT(); 3709 } 3710 3711 // Only arguments pased on the stack should make it here. 3712 assert(VA.isMemLoc()); 3713 3714 // The stack pointer offset is relative to the caller stack frame. 3715 int FI = MFI.CreateFixedObject(LocVT.getSizeInBits() / 8, 3716 VA.getLocMemOffset(), true); 3717 3718 // Create load nodes to retrieve arguments from the stack 3719 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy(DAG.getDataLayout())); 3720 SDValue ArgValue = DAG.getLoad( 3721 LocVT, DL, Chain, FIN, 3722 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), FI)); 3723 OutChains.push_back(ArgValue.getValue(1)); 3724 3725 ArgValue = 3726 UnpackFromArgumentSlot(ArgValue, VA, Ins[InsIdx].ArgVT, DL, DAG); 3727 3728 InVals.push_back(ArgValue); 3729 } 3730 } 3731 3732 for (unsigned i = 0, e = ArgLocs.size(), InsIdx = 0; i != e; ++i, ++InsIdx) { 3733 3734 if (ArgLocs[i].needsCustom()) { 3735 ++i; 3736 continue; 3737 } 3738 3739 // The mips ABIs for returning structs by value requires that we copy 3740 // the sret argument into $v0 for the return. Save the argument into 3741 // a virtual register so that we can access it from the return points. 3742 if (Ins[InsIdx].Flags.isSRet()) { 3743 unsigned Reg = MipsFI->getSRetReturnReg(); 3744 if (!Reg) { 3745 Reg = MF.getRegInfo().createVirtualRegister( 3746 getRegClassFor(ABI.IsN64() ? MVT::i64 : MVT::i32)); 3747 MipsFI->setSRetReturnReg(Reg); 3748 } 3749 SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), DL, Reg, InVals[i]); 3750 Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, Copy, Chain); 3751 break; 3752 } 3753 } 3754 3755 if (IsVarArg) 3756 writeVarArgRegs(OutChains, Chain, DL, DAG, CCInfo); 3757 3758 // All stores are grouped in one node to allow the matching between 3759 // the size of Ins and InVals. This only happens when on varg functions 3760 if (!OutChains.empty()) { 3761 OutChains.push_back(Chain); 3762 Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, OutChains); 3763 } 3764 3765 return Chain; 3766 } 3767 3768 //===----------------------------------------------------------------------===// 3769 // Return Value Calling Convention Implementation 3770 //===----------------------------------------------------------------------===// 3771 3772 bool 3773 MipsTargetLowering::CanLowerReturn(CallingConv::ID CallConv, 3774 MachineFunction &MF, bool IsVarArg, 3775 const SmallVectorImpl<ISD::OutputArg> &Outs, 3776 LLVMContext &Context) const { 3777 SmallVector<CCValAssign, 16> RVLocs; 3778 MipsCCState CCInfo(CallConv, IsVarArg, MF, RVLocs, Context); 3779 return CCInfo.CheckReturn(Outs, RetCC_Mips); 3780 } 3781 3782 bool MipsTargetLowering::shouldSignExtendTypeInLibCall(EVT Type, 3783 bool IsSigned) const { 3784 if ((ABI.IsN32() || ABI.IsN64()) && Type == MVT::i32) 3785 return true; 3786 3787 return IsSigned; 3788 } 3789 3790 SDValue 3791 MipsTargetLowering::LowerInterruptReturn(SmallVectorImpl<SDValue> &RetOps, 3792 const SDLoc &DL, 3793 SelectionDAG &DAG) const { 3794 MachineFunction &MF = DAG.getMachineFunction(); 3795 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>(); 3796 3797 MipsFI->setISR(); 3798 3799 return DAG.getNode(MipsISD::ERet, DL, MVT::Other, RetOps); 3800 } 3801 3802 SDValue 3803 MipsTargetLowering::LowerReturn(SDValue Chain, CallingConv::ID CallConv, 3804 bool IsVarArg, 3805 const SmallVectorImpl<ISD::OutputArg> &Outs, 3806 const SmallVectorImpl<SDValue> &OutVals, 3807 const SDLoc &DL, SelectionDAG &DAG) const { 3808 // CCValAssign - represent the assignment of 3809 // the return value to a location 3810 SmallVector<CCValAssign, 16> RVLocs; 3811 MachineFunction &MF = DAG.getMachineFunction(); 3812 3813 // CCState - Info about the registers and stack slot. 3814 MipsCCState CCInfo(CallConv, IsVarArg, MF, RVLocs, *DAG.getContext()); 3815 3816 // Analyze return values. 3817 CCInfo.AnalyzeReturn(Outs, RetCC_Mips); 3818 3819 SDValue Flag; 3820 SmallVector<SDValue, 4> RetOps(1, Chain); 3821 3822 // Copy the result values into the output registers. 3823 for (unsigned i = 0; i != RVLocs.size(); ++i) { 3824 SDValue Val = OutVals[i]; 3825 CCValAssign &VA = RVLocs[i]; 3826 assert(VA.isRegLoc() && "Can only return in registers!"); 3827 bool UseUpperBits = false; 3828 3829 switch (VA.getLocInfo()) { 3830 default: 3831 llvm_unreachable("Unknown loc info!"); 3832 case CCValAssign::Full: 3833 break; 3834 case CCValAssign::BCvt: 3835 Val = DAG.getNode(ISD::BITCAST, DL, VA.getLocVT(), Val); 3836 break; 3837 case CCValAssign::AExtUpper: 3838 UseUpperBits = true; 3839 LLVM_FALLTHROUGH; 3840 case CCValAssign::AExt: 3841 Val = DAG.getNode(ISD::ANY_EXTEND, DL, VA.getLocVT(), Val); 3842 break; 3843 case CCValAssign::ZExtUpper: 3844 UseUpperBits = true; 3845 LLVM_FALLTHROUGH; 3846 case CCValAssign::ZExt: 3847 Val = DAG.getNode(ISD::ZERO_EXTEND, DL, VA.getLocVT(), Val); 3848 break; 3849 case CCValAssign::SExtUpper: 3850 UseUpperBits = true; 3851 LLVM_FALLTHROUGH; 3852 case CCValAssign::SExt: 3853 Val = DAG.getNode(ISD::SIGN_EXTEND, DL, VA.getLocVT(), Val); 3854 break; 3855 } 3856 3857 if (UseUpperBits) { 3858 unsigned ValSizeInBits = Outs[i].ArgVT.getSizeInBits(); 3859 unsigned LocSizeInBits = VA.getLocVT().getSizeInBits(); 3860 Val = DAG.getNode( 3861 ISD::SHL, DL, VA.getLocVT(), Val, 3862 DAG.getConstant(LocSizeInBits - ValSizeInBits, DL, VA.getLocVT())); 3863 } 3864 3865 Chain = DAG.getCopyToReg(Chain, DL, VA.getLocReg(), Val, Flag); 3866 3867 // Guarantee that all emitted copies are stuck together with flags. 3868 Flag = Chain.getValue(1); 3869 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT())); 3870 } 3871 3872 // The mips ABIs for returning structs by value requires that we copy 3873 // the sret argument into $v0 for the return. We saved the argument into 3874 // a virtual register in the entry block, so now we copy the value out 3875 // and into $v0. 3876 if (MF.getFunction().hasStructRetAttr()) { 3877 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>(); 3878 unsigned Reg = MipsFI->getSRetReturnReg(); 3879 3880 if (!Reg) 3881 llvm_unreachable("sret virtual register not created in the entry block"); 3882 SDValue Val = 3883 DAG.getCopyFromReg(Chain, DL, Reg, getPointerTy(DAG.getDataLayout())); 3884 unsigned V0 = ABI.IsN64() ? Mips::V0_64 : Mips::V0; 3885 3886 Chain = DAG.getCopyToReg(Chain, DL, V0, Val, Flag); 3887 Flag = Chain.getValue(1); 3888 RetOps.push_back(DAG.getRegister(V0, getPointerTy(DAG.getDataLayout()))); 3889 } 3890 3891 RetOps[0] = Chain; // Update chain. 3892 3893 // Add the flag if we have it. 3894 if (Flag.getNode()) 3895 RetOps.push_back(Flag); 3896 3897 // ISRs must use "eret". 3898 if (DAG.getMachineFunction().getFunction().hasFnAttribute("interrupt")) 3899 return LowerInterruptReturn(RetOps, DL, DAG); 3900 3901 // Standard return on Mips is a "jr $ra" 3902 return DAG.getNode(MipsISD::Ret, DL, MVT::Other, RetOps); 3903 } 3904 3905 //===----------------------------------------------------------------------===// 3906 // Mips Inline Assembly Support 3907 //===----------------------------------------------------------------------===// 3908 3909 /// getConstraintType - Given a constraint letter, return the type of 3910 /// constraint it is for this target. 3911 MipsTargetLowering::ConstraintType 3912 MipsTargetLowering::getConstraintType(StringRef Constraint) const { 3913 // Mips specific constraints 3914 // GCC config/mips/constraints.md 3915 // 3916 // 'd' : An address register. Equivalent to r 3917 // unless generating MIPS16 code. 3918 // 'y' : Equivalent to r; retained for 3919 // backwards compatibility. 3920 // 'c' : A register suitable for use in an indirect 3921 // jump. This will always be $25 for -mabicalls. 3922 // 'l' : The lo register. 1 word storage. 3923 // 'x' : The hilo register pair. Double word storage. 3924 if (Constraint.size() == 1) { 3925 switch (Constraint[0]) { 3926 default : break; 3927 case 'd': 3928 case 'y': 3929 case 'f': 3930 case 'c': 3931 case 'l': 3932 case 'x': 3933 return C_RegisterClass; 3934 case 'R': 3935 return C_Memory; 3936 } 3937 } 3938 3939 if (Constraint == "ZC") 3940 return C_Memory; 3941 3942 return TargetLowering::getConstraintType(Constraint); 3943 } 3944 3945 /// Examine constraint type and operand type and determine a weight value. 3946 /// This object must already have been set up with the operand type 3947 /// and the current alternative constraint selected. 3948 TargetLowering::ConstraintWeight 3949 MipsTargetLowering::getSingleConstraintMatchWeight( 3950 AsmOperandInfo &info, const char *constraint) const { 3951 ConstraintWeight weight = CW_Invalid; 3952 Value *CallOperandVal = info.CallOperandVal; 3953 // If we don't have a value, we can't do a match, 3954 // but allow it at the lowest weight. 3955 if (!CallOperandVal) 3956 return CW_Default; 3957 Type *type = CallOperandVal->getType(); 3958 // Look at the constraint type. 3959 switch (*constraint) { 3960 default: 3961 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint); 3962 break; 3963 case 'd': 3964 case 'y': 3965 if (type->isIntegerTy()) 3966 weight = CW_Register; 3967 break; 3968 case 'f': // FPU or MSA register 3969 if (Subtarget.hasMSA() && type->isVectorTy() && 3970 type->getPrimitiveSizeInBits().getFixedSize() == 128) 3971 weight = CW_Register; 3972 else if (type->isFloatTy()) 3973 weight = CW_Register; 3974 break; 3975 case 'c': // $25 for indirect jumps 3976 case 'l': // lo register 3977 case 'x': // hilo register pair 3978 if (type->isIntegerTy()) 3979 weight = CW_SpecificReg; 3980 break; 3981 case 'I': // signed 16 bit immediate 3982 case 'J': // integer zero 3983 case 'K': // unsigned 16 bit immediate 3984 case 'L': // signed 32 bit immediate where lower 16 bits are 0 3985 case 'N': // immediate in the range of -65535 to -1 (inclusive) 3986 case 'O': // signed 15 bit immediate (+- 16383) 3987 case 'P': // immediate in the range of 65535 to 1 (inclusive) 3988 if (isa<ConstantInt>(CallOperandVal)) 3989 weight = CW_Constant; 3990 break; 3991 case 'R': 3992 weight = CW_Memory; 3993 break; 3994 } 3995 return weight; 3996 } 3997 3998 /// This is a helper function to parse a physical register string and split it 3999 /// into non-numeric and numeric parts (Prefix and Reg). The first boolean flag 4000 /// that is returned indicates whether parsing was successful. The second flag 4001 /// is true if the numeric part exists. 4002 static std::pair<bool, bool> parsePhysicalReg(StringRef C, StringRef &Prefix, 4003 unsigned long long &Reg) { 4004 if (C.front() != '{' || C.back() != '}') 4005 return std::make_pair(false, false); 4006 4007 // Search for the first numeric character. 4008 StringRef::const_iterator I, B = C.begin() + 1, E = C.end() - 1; 4009 I = std::find_if(B, E, isdigit); 4010 4011 Prefix = StringRef(B, I - B); 4012 4013 // The second flag is set to false if no numeric characters were found. 4014 if (I == E) 4015 return std::make_pair(true, false); 4016 4017 // Parse the numeric characters. 4018 return std::make_pair(!getAsUnsignedInteger(StringRef(I, E - I), 10, Reg), 4019 true); 4020 } 4021 4022 EVT MipsTargetLowering::getTypeForExtReturn(LLVMContext &Context, EVT VT, 4023 ISD::NodeType) const { 4024 bool Cond = !Subtarget.isABI_O32() && VT.getSizeInBits() == 32; 4025 EVT MinVT = getRegisterType(Context, Cond ? MVT::i64 : MVT::i32); 4026 return VT.bitsLT(MinVT) ? MinVT : VT; 4027 } 4028 4029 std::pair<unsigned, const TargetRegisterClass *> MipsTargetLowering:: 4030 parseRegForInlineAsmConstraint(StringRef C, MVT VT) const { 4031 const TargetRegisterInfo *TRI = 4032 Subtarget.getRegisterInfo(); 4033 const TargetRegisterClass *RC; 4034 StringRef Prefix; 4035 unsigned long long Reg; 4036 4037 std::pair<bool, bool> R = parsePhysicalReg(C, Prefix, Reg); 4038 4039 if (!R.first) 4040 return std::make_pair(0U, nullptr); 4041 4042 if ((Prefix == "hi" || Prefix == "lo")) { // Parse hi/lo. 4043 // No numeric characters follow "hi" or "lo". 4044 if (R.second) 4045 return std::make_pair(0U, nullptr); 4046 4047 RC = TRI->getRegClass(Prefix == "hi" ? 4048 Mips::HI32RegClassID : Mips::LO32RegClassID); 4049 return std::make_pair(*(RC->begin()), RC); 4050 } else if (Prefix.startswith("$msa")) { 4051 // Parse $msa(ir|csr|access|save|modify|request|map|unmap) 4052 4053 // No numeric characters follow the name. 4054 if (R.second) 4055 return std::make_pair(0U, nullptr); 4056 4057 Reg = StringSwitch<unsigned long long>(Prefix) 4058 .Case("$msair", Mips::MSAIR) 4059 .Case("$msacsr", Mips::MSACSR) 4060 .Case("$msaaccess", Mips::MSAAccess) 4061 .Case("$msasave", Mips::MSASave) 4062 .Case("$msamodify", Mips::MSAModify) 4063 .Case("$msarequest", Mips::MSARequest) 4064 .Case("$msamap", Mips::MSAMap) 4065 .Case("$msaunmap", Mips::MSAUnmap) 4066 .Default(0); 4067 4068 if (!Reg) 4069 return std::make_pair(0U, nullptr); 4070 4071 RC = TRI->getRegClass(Mips::MSACtrlRegClassID); 4072 return std::make_pair(Reg, RC); 4073 } 4074 4075 if (!R.second) 4076 return std::make_pair(0U, nullptr); 4077 4078 if (Prefix == "$f") { // Parse $f0-$f31. 4079 // If the size of FP registers is 64-bit or Reg is an even number, select 4080 // the 64-bit register class. Otherwise, select the 32-bit register class. 4081 if (VT == MVT::Other) 4082 VT = (Subtarget.isFP64bit() || !(Reg % 2)) ? MVT::f64 : MVT::f32; 4083 4084 RC = getRegClassFor(VT); 4085 4086 if (RC == &Mips::AFGR64RegClass) { 4087 assert(Reg % 2 == 0); 4088 Reg >>= 1; 4089 } 4090 } else if (Prefix == "$fcc") // Parse $fcc0-$fcc7. 4091 RC = TRI->getRegClass(Mips::FCCRegClassID); 4092 else if (Prefix == "$w") { // Parse $w0-$w31. 4093 RC = getRegClassFor((VT == MVT::Other) ? MVT::v16i8 : VT); 4094 } else { // Parse $0-$31. 4095 assert(Prefix == "$"); 4096 RC = getRegClassFor((VT == MVT::Other) ? MVT::i32 : VT); 4097 } 4098 4099 assert(Reg < RC->getNumRegs()); 4100 return std::make_pair(*(RC->begin() + Reg), RC); 4101 } 4102 4103 /// Given a register class constraint, like 'r', if this corresponds directly 4104 /// to an LLVM register class, return a register of 0 and the register class 4105 /// pointer. 4106 std::pair<unsigned, const TargetRegisterClass *> 4107 MipsTargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, 4108 StringRef Constraint, 4109 MVT VT) const { 4110 if (Constraint.size() == 1) { 4111 switch (Constraint[0]) { 4112 case 'd': // Address register. Same as 'r' unless generating MIPS16 code. 4113 case 'y': // Same as 'r'. Exists for compatibility. 4114 case 'r': 4115 if (VT == MVT::i32 || VT == MVT::i16 || VT == MVT::i8 || VT == MVT::i1) { 4116 if (Subtarget.inMips16Mode()) 4117 return std::make_pair(0U, &Mips::CPU16RegsRegClass); 4118 return std::make_pair(0U, &Mips::GPR32RegClass); 4119 } 4120 if (VT == MVT::i64 && !Subtarget.isGP64bit()) 4121 return std::make_pair(0U, &Mips::GPR32RegClass); 4122 if (VT == MVT::i64 && Subtarget.isGP64bit()) 4123 return std::make_pair(0U, &Mips::GPR64RegClass); 4124 // This will generate an error message 4125 return std::make_pair(0U, nullptr); 4126 case 'f': // FPU or MSA register 4127 if (VT == MVT::v16i8) 4128 return std::make_pair(0U, &Mips::MSA128BRegClass); 4129 else if (VT == MVT::v8i16 || VT == MVT::v8f16) 4130 return std::make_pair(0U, &Mips::MSA128HRegClass); 4131 else if (VT == MVT::v4i32 || VT == MVT::v4f32) 4132 return std::make_pair(0U, &Mips::MSA128WRegClass); 4133 else if (VT == MVT::v2i64 || VT == MVT::v2f64) 4134 return std::make_pair(0U, &Mips::MSA128DRegClass); 4135 else if (VT == MVT::f32) 4136 return std::make_pair(0U, &Mips::FGR32RegClass); 4137 else if ((VT == MVT::f64) && (!Subtarget.isSingleFloat())) { 4138 if (Subtarget.isFP64bit()) 4139 return std::make_pair(0U, &Mips::FGR64RegClass); 4140 return std::make_pair(0U, &Mips::AFGR64RegClass); 4141 } 4142 break; 4143 case 'c': // register suitable for indirect jump 4144 if (VT == MVT::i32) 4145 return std::make_pair((unsigned)Mips::T9, &Mips::GPR32RegClass); 4146 if (VT == MVT::i64) 4147 return std::make_pair((unsigned)Mips::T9_64, &Mips::GPR64RegClass); 4148 // This will generate an error message 4149 return std::make_pair(0U, nullptr); 4150 case 'l': // use the `lo` register to store values 4151 // that are no bigger than a word 4152 if (VT == MVT::i32 || VT == MVT::i16 || VT == MVT::i8) 4153 return std::make_pair((unsigned)Mips::LO0, &Mips::LO32RegClass); 4154 return std::make_pair((unsigned)Mips::LO0_64, &Mips::LO64RegClass); 4155 case 'x': // use the concatenated `hi` and `lo` registers 4156 // to store doubleword values 4157 // Fixme: Not triggering the use of both hi and low 4158 // This will generate an error message 4159 return std::make_pair(0U, nullptr); 4160 } 4161 } 4162 4163 if (!Constraint.empty()) { 4164 std::pair<unsigned, const TargetRegisterClass *> R; 4165 R = parseRegForInlineAsmConstraint(Constraint, VT); 4166 4167 if (R.second) 4168 return R; 4169 } 4170 4171 return TargetLowering::getRegForInlineAsmConstraint(TRI, Constraint, VT); 4172 } 4173 4174 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops 4175 /// vector. If it is invalid, don't add anything to Ops. 4176 void MipsTargetLowering::LowerAsmOperandForConstraint(SDValue Op, 4177 std::string &Constraint, 4178 std::vector<SDValue>&Ops, 4179 SelectionDAG &DAG) const { 4180 SDLoc DL(Op); 4181 SDValue Result; 4182 4183 // Only support length 1 constraints for now. 4184 if (Constraint.length() > 1) return; 4185 4186 char ConstraintLetter = Constraint[0]; 4187 switch (ConstraintLetter) { 4188 default: break; // This will fall through to the generic implementation 4189 case 'I': // Signed 16 bit constant 4190 // If this fails, the parent routine will give an error 4191 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 4192 EVT Type = Op.getValueType(); 4193 int64_t Val = C->getSExtValue(); 4194 if (isInt<16>(Val)) { 4195 Result = DAG.getTargetConstant(Val, DL, Type); 4196 break; 4197 } 4198 } 4199 return; 4200 case 'J': // integer zero 4201 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 4202 EVT Type = Op.getValueType(); 4203 int64_t Val = C->getZExtValue(); 4204 if (Val == 0) { 4205 Result = DAG.getTargetConstant(0, DL, Type); 4206 break; 4207 } 4208 } 4209 return; 4210 case 'K': // unsigned 16 bit immediate 4211 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 4212 EVT Type = Op.getValueType(); 4213 uint64_t Val = (uint64_t)C->getZExtValue(); 4214 if (isUInt<16>(Val)) { 4215 Result = DAG.getTargetConstant(Val, DL, Type); 4216 break; 4217 } 4218 } 4219 return; 4220 case 'L': // signed 32 bit immediate where lower 16 bits are 0 4221 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 4222 EVT Type = Op.getValueType(); 4223 int64_t Val = C->getSExtValue(); 4224 if ((isInt<32>(Val)) && ((Val & 0xffff) == 0)){ 4225 Result = DAG.getTargetConstant(Val, DL, Type); 4226 break; 4227 } 4228 } 4229 return; 4230 case 'N': // immediate in the range of -65535 to -1 (inclusive) 4231 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 4232 EVT Type = Op.getValueType(); 4233 int64_t Val = C->getSExtValue(); 4234 if ((Val >= -65535) && (Val <= -1)) { 4235 Result = DAG.getTargetConstant(Val, DL, Type); 4236 break; 4237 } 4238 } 4239 return; 4240 case 'O': // signed 15 bit immediate 4241 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 4242 EVT Type = Op.getValueType(); 4243 int64_t Val = C->getSExtValue(); 4244 if ((isInt<15>(Val))) { 4245 Result = DAG.getTargetConstant(Val, DL, Type); 4246 break; 4247 } 4248 } 4249 return; 4250 case 'P': // immediate in the range of 1 to 65535 (inclusive) 4251 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 4252 EVT Type = Op.getValueType(); 4253 int64_t Val = C->getSExtValue(); 4254 if ((Val <= 65535) && (Val >= 1)) { 4255 Result = DAG.getTargetConstant(Val, DL, Type); 4256 break; 4257 } 4258 } 4259 return; 4260 } 4261 4262 if (Result.getNode()) { 4263 Ops.push_back(Result); 4264 return; 4265 } 4266 4267 TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG); 4268 } 4269 4270 bool MipsTargetLowering::isLegalAddressingMode(const DataLayout &DL, 4271 const AddrMode &AM, Type *Ty, 4272 unsigned AS, 4273 Instruction *I) const { 4274 // No global is ever allowed as a base. 4275 if (AM.BaseGV) 4276 return false; 4277 4278 switch (AM.Scale) { 4279 case 0: // "r+i" or just "i", depending on HasBaseReg. 4280 break; 4281 case 1: 4282 if (!AM.HasBaseReg) // allow "r+i". 4283 break; 4284 return false; // disallow "r+r" or "r+r+i". 4285 default: 4286 return false; 4287 } 4288 4289 return true; 4290 } 4291 4292 bool 4293 MipsTargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const { 4294 // The Mips target isn't yet aware of offsets. 4295 return false; 4296 } 4297 4298 EVT MipsTargetLowering::getOptimalMemOpType( 4299 const MemOp &Op, const AttributeList &FuncAttributes) const { 4300 if (Subtarget.hasMips64()) 4301 return MVT::i64; 4302 4303 return MVT::i32; 4304 } 4305 4306 bool MipsTargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT, 4307 bool ForCodeSize) const { 4308 if (VT != MVT::f32 && VT != MVT::f64) 4309 return false; 4310 if (Imm.isNegZero()) 4311 return false; 4312 return Imm.isZero(); 4313 } 4314 4315 unsigned MipsTargetLowering::getJumpTableEncoding() const { 4316 4317 // FIXME: For space reasons this should be: EK_GPRel32BlockAddress. 4318 if (ABI.IsN64() && isPositionIndependent()) 4319 return MachineJumpTableInfo::EK_GPRel64BlockAddress; 4320 4321 return TargetLowering::getJumpTableEncoding(); 4322 } 4323 4324 bool MipsTargetLowering::useSoftFloat() const { 4325 return Subtarget.useSoftFloat(); 4326 } 4327 4328 void MipsTargetLowering::copyByValRegs( 4329 SDValue Chain, const SDLoc &DL, std::vector<SDValue> &OutChains, 4330 SelectionDAG &DAG, const ISD::ArgFlagsTy &Flags, 4331 SmallVectorImpl<SDValue> &InVals, const Argument *FuncArg, 4332 unsigned FirstReg, unsigned LastReg, const CCValAssign &VA, 4333 MipsCCState &State) const { 4334 MachineFunction &MF = DAG.getMachineFunction(); 4335 MachineFrameInfo &MFI = MF.getFrameInfo(); 4336 unsigned GPRSizeInBytes = Subtarget.getGPRSizeInBytes(); 4337 unsigned NumRegs = LastReg - FirstReg; 4338 unsigned RegAreaSize = NumRegs * GPRSizeInBytes; 4339 unsigned FrameObjSize = std::max(Flags.getByValSize(), RegAreaSize); 4340 int FrameObjOffset; 4341 ArrayRef<MCPhysReg> ByValArgRegs = ABI.GetByValArgRegs(); 4342 4343 if (RegAreaSize) 4344 FrameObjOffset = 4345 (int)ABI.GetCalleeAllocdArgSizeInBytes(State.getCallingConv()) - 4346 (int)((ByValArgRegs.size() - FirstReg) * GPRSizeInBytes); 4347 else 4348 FrameObjOffset = VA.getLocMemOffset(); 4349 4350 // Create frame object. 4351 EVT PtrTy = getPointerTy(DAG.getDataLayout()); 4352 // Make the fixed object stored to mutable so that the load instructions 4353 // referencing it have their memory dependencies added. 4354 // Set the frame object as isAliased which clears the underlying objects 4355 // vector in ScheduleDAGInstrs::buildSchedGraph() resulting in addition of all 4356 // stores as dependencies for loads referencing this fixed object. 4357 int FI = MFI.CreateFixedObject(FrameObjSize, FrameObjOffset, false, true); 4358 SDValue FIN = DAG.getFrameIndex(FI, PtrTy); 4359 InVals.push_back(FIN); 4360 4361 if (!NumRegs) 4362 return; 4363 4364 // Copy arg registers. 4365 MVT RegTy = MVT::getIntegerVT(GPRSizeInBytes * 8); 4366 const TargetRegisterClass *RC = getRegClassFor(RegTy); 4367 4368 for (unsigned I = 0; I < NumRegs; ++I) { 4369 unsigned ArgReg = ByValArgRegs[FirstReg + I]; 4370 unsigned VReg = addLiveIn(MF, ArgReg, RC); 4371 unsigned Offset = I * GPRSizeInBytes; 4372 SDValue StorePtr = DAG.getNode(ISD::ADD, DL, PtrTy, FIN, 4373 DAG.getConstant(Offset, DL, PtrTy)); 4374 SDValue Store = DAG.getStore(Chain, DL, DAG.getRegister(VReg, RegTy), 4375 StorePtr, MachinePointerInfo(FuncArg, Offset)); 4376 OutChains.push_back(Store); 4377 } 4378 } 4379 4380 // Copy byVal arg to registers and stack. 4381 void MipsTargetLowering::passByValArg( 4382 SDValue Chain, const SDLoc &DL, 4383 std::deque<std::pair<unsigned, SDValue>> &RegsToPass, 4384 SmallVectorImpl<SDValue> &MemOpChains, SDValue StackPtr, 4385 MachineFrameInfo &MFI, SelectionDAG &DAG, SDValue Arg, unsigned FirstReg, 4386 unsigned LastReg, const ISD::ArgFlagsTy &Flags, bool isLittle, 4387 const CCValAssign &VA) const { 4388 unsigned ByValSizeInBytes = Flags.getByValSize(); 4389 unsigned OffsetInBytes = 0; // From beginning of struct 4390 unsigned RegSizeInBytes = Subtarget.getGPRSizeInBytes(); 4391 Align Alignment = 4392 std::min(Flags.getNonZeroByValAlign(), Align(RegSizeInBytes)); 4393 EVT PtrTy = getPointerTy(DAG.getDataLayout()), 4394 RegTy = MVT::getIntegerVT(RegSizeInBytes * 8); 4395 unsigned NumRegs = LastReg - FirstReg; 4396 4397 if (NumRegs) { 4398 ArrayRef<MCPhysReg> ArgRegs = ABI.GetByValArgRegs(); 4399 bool LeftoverBytes = (NumRegs * RegSizeInBytes > ByValSizeInBytes); 4400 unsigned I = 0; 4401 4402 // Copy words to registers. 4403 for (; I < NumRegs - LeftoverBytes; ++I, OffsetInBytes += RegSizeInBytes) { 4404 SDValue LoadPtr = DAG.getNode(ISD::ADD, DL, PtrTy, Arg, 4405 DAG.getConstant(OffsetInBytes, DL, PtrTy)); 4406 SDValue LoadVal = DAG.getLoad(RegTy, DL, Chain, LoadPtr, 4407 MachinePointerInfo(), Alignment); 4408 MemOpChains.push_back(LoadVal.getValue(1)); 4409 unsigned ArgReg = ArgRegs[FirstReg + I]; 4410 RegsToPass.push_back(std::make_pair(ArgReg, LoadVal)); 4411 } 4412 4413 // Return if the struct has been fully copied. 4414 if (ByValSizeInBytes == OffsetInBytes) 4415 return; 4416 4417 // Copy the remainder of the byval argument with sub-word loads and shifts. 4418 if (LeftoverBytes) { 4419 SDValue Val; 4420 4421 for (unsigned LoadSizeInBytes = RegSizeInBytes / 2, TotalBytesLoaded = 0; 4422 OffsetInBytes < ByValSizeInBytes; LoadSizeInBytes /= 2) { 4423 unsigned RemainingSizeInBytes = ByValSizeInBytes - OffsetInBytes; 4424 4425 if (RemainingSizeInBytes < LoadSizeInBytes) 4426 continue; 4427 4428 // Load subword. 4429 SDValue LoadPtr = DAG.getNode(ISD::ADD, DL, PtrTy, Arg, 4430 DAG.getConstant(OffsetInBytes, DL, 4431 PtrTy)); 4432 SDValue LoadVal = DAG.getExtLoad( 4433 ISD::ZEXTLOAD, DL, RegTy, Chain, LoadPtr, MachinePointerInfo(), 4434 MVT::getIntegerVT(LoadSizeInBytes * 8), Alignment); 4435 MemOpChains.push_back(LoadVal.getValue(1)); 4436 4437 // Shift the loaded value. 4438 unsigned Shamt; 4439 4440 if (isLittle) 4441 Shamt = TotalBytesLoaded * 8; 4442 else 4443 Shamt = (RegSizeInBytes - (TotalBytesLoaded + LoadSizeInBytes)) * 8; 4444 4445 SDValue Shift = DAG.getNode(ISD::SHL, DL, RegTy, LoadVal, 4446 DAG.getConstant(Shamt, DL, MVT::i32)); 4447 4448 if (Val.getNode()) 4449 Val = DAG.getNode(ISD::OR, DL, RegTy, Val, Shift); 4450 else 4451 Val = Shift; 4452 4453 OffsetInBytes += LoadSizeInBytes; 4454 TotalBytesLoaded += LoadSizeInBytes; 4455 Alignment = std::min(Alignment, Align(LoadSizeInBytes)); 4456 } 4457 4458 unsigned ArgReg = ArgRegs[FirstReg + I]; 4459 RegsToPass.push_back(std::make_pair(ArgReg, Val)); 4460 return; 4461 } 4462 } 4463 4464 // Copy remainder of byval arg to it with memcpy. 4465 unsigned MemCpySize = ByValSizeInBytes - OffsetInBytes; 4466 SDValue Src = DAG.getNode(ISD::ADD, DL, PtrTy, Arg, 4467 DAG.getConstant(OffsetInBytes, DL, PtrTy)); 4468 SDValue Dst = DAG.getNode(ISD::ADD, DL, PtrTy, StackPtr, 4469 DAG.getIntPtrConstant(VA.getLocMemOffset(), DL)); 4470 Chain = DAG.getMemcpy( 4471 Chain, DL, Dst, Src, DAG.getConstant(MemCpySize, DL, PtrTy), 4472 Align(Alignment), /*isVolatile=*/false, /*AlwaysInline=*/false, 4473 /*isTailCall=*/false, MachinePointerInfo(), MachinePointerInfo()); 4474 MemOpChains.push_back(Chain); 4475 } 4476 4477 void MipsTargetLowering::writeVarArgRegs(std::vector<SDValue> &OutChains, 4478 SDValue Chain, const SDLoc &DL, 4479 SelectionDAG &DAG, 4480 CCState &State) const { 4481 ArrayRef<MCPhysReg> ArgRegs = ABI.GetVarArgRegs(); 4482 unsigned Idx = State.getFirstUnallocated(ArgRegs); 4483 unsigned RegSizeInBytes = Subtarget.getGPRSizeInBytes(); 4484 MVT RegTy = MVT::getIntegerVT(RegSizeInBytes * 8); 4485 const TargetRegisterClass *RC = getRegClassFor(RegTy); 4486 MachineFunction &MF = DAG.getMachineFunction(); 4487 MachineFrameInfo &MFI = MF.getFrameInfo(); 4488 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>(); 4489 4490 // Offset of the first variable argument from stack pointer. 4491 int VaArgOffset; 4492 4493 if (ArgRegs.size() == Idx) 4494 VaArgOffset = alignTo(State.getNextStackOffset(), RegSizeInBytes); 4495 else { 4496 VaArgOffset = 4497 (int)ABI.GetCalleeAllocdArgSizeInBytes(State.getCallingConv()) - 4498 (int)(RegSizeInBytes * (ArgRegs.size() - Idx)); 4499 } 4500 4501 // Record the frame index of the first variable argument 4502 // which is a value necessary to VASTART. 4503 int FI = MFI.CreateFixedObject(RegSizeInBytes, VaArgOffset, true); 4504 MipsFI->setVarArgsFrameIndex(FI); 4505 4506 // Copy the integer registers that have not been used for argument passing 4507 // to the argument register save area. For O32, the save area is allocated 4508 // in the caller's stack frame, while for N32/64, it is allocated in the 4509 // callee's stack frame. 4510 for (unsigned I = Idx; I < ArgRegs.size(); 4511 ++I, VaArgOffset += RegSizeInBytes) { 4512 unsigned Reg = addLiveIn(MF, ArgRegs[I], RC); 4513 SDValue ArgValue = DAG.getCopyFromReg(Chain, DL, Reg, RegTy); 4514 FI = MFI.CreateFixedObject(RegSizeInBytes, VaArgOffset, true); 4515 SDValue PtrOff = DAG.getFrameIndex(FI, getPointerTy(DAG.getDataLayout())); 4516 SDValue Store = 4517 DAG.getStore(Chain, DL, ArgValue, PtrOff, MachinePointerInfo()); 4518 cast<StoreSDNode>(Store.getNode())->getMemOperand()->setValue( 4519 (Value *)nullptr); 4520 OutChains.push_back(Store); 4521 } 4522 } 4523 4524 void MipsTargetLowering::HandleByVal(CCState *State, unsigned &Size, 4525 Align Alignment) const { 4526 const TargetFrameLowering *TFL = Subtarget.getFrameLowering(); 4527 4528 assert(Size && "Byval argument's size shouldn't be 0."); 4529 4530 Alignment = std::min(Alignment, TFL->getStackAlign()); 4531 4532 unsigned FirstReg = 0; 4533 unsigned NumRegs = 0; 4534 4535 if (State->getCallingConv() != CallingConv::Fast) { 4536 unsigned RegSizeInBytes = Subtarget.getGPRSizeInBytes(); 4537 ArrayRef<MCPhysReg> IntArgRegs = ABI.GetByValArgRegs(); 4538 // FIXME: The O32 case actually describes no shadow registers. 4539 const MCPhysReg *ShadowRegs = 4540 ABI.IsO32() ? IntArgRegs.data() : Mips64DPRegs; 4541 4542 // We used to check the size as well but we can't do that anymore since 4543 // CCState::HandleByVal() rounds up the size after calling this function. 4544 assert( 4545 Alignment >= Align(RegSizeInBytes) && 4546 "Byval argument's alignment should be a multiple of RegSizeInBytes."); 4547 4548 FirstReg = State->getFirstUnallocated(IntArgRegs); 4549 4550 // If Alignment > RegSizeInBytes, the first arg register must be even. 4551 // FIXME: This condition happens to do the right thing but it's not the 4552 // right way to test it. We want to check that the stack frame offset 4553 // of the register is aligned. 4554 if ((Alignment > RegSizeInBytes) && (FirstReg % 2)) { 4555 State->AllocateReg(IntArgRegs[FirstReg], ShadowRegs[FirstReg]); 4556 ++FirstReg; 4557 } 4558 4559 // Mark the registers allocated. 4560 Size = alignTo(Size, RegSizeInBytes); 4561 for (unsigned I = FirstReg; Size > 0 && (I < IntArgRegs.size()); 4562 Size -= RegSizeInBytes, ++I, ++NumRegs) 4563 State->AllocateReg(IntArgRegs[I], ShadowRegs[I]); 4564 } 4565 4566 State->addInRegsParamInfo(FirstReg, FirstReg + NumRegs); 4567 } 4568 4569 MachineBasicBlock *MipsTargetLowering::emitPseudoSELECT(MachineInstr &MI, 4570 MachineBasicBlock *BB, 4571 bool isFPCmp, 4572 unsigned Opc) const { 4573 assert(!(Subtarget.hasMips4() || Subtarget.hasMips32()) && 4574 "Subtarget already supports SELECT nodes with the use of" 4575 "conditional-move instructions."); 4576 4577 const TargetInstrInfo *TII = 4578 Subtarget.getInstrInfo(); 4579 DebugLoc DL = MI.getDebugLoc(); 4580 4581 // To "insert" a SELECT instruction, we actually have to insert the 4582 // diamond control-flow pattern. The incoming instruction knows the 4583 // destination vreg to set, the condition code register to branch on, the 4584 // true/false values to select between, and a branch opcode to use. 4585 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 4586 MachineFunction::iterator It = ++BB->getIterator(); 4587 4588 // thisMBB: 4589 // ... 4590 // TrueVal = ... 4591 // setcc r1, r2, r3 4592 // bNE r1, r0, copy1MBB 4593 // fallthrough --> copy0MBB 4594 MachineBasicBlock *thisMBB = BB; 4595 MachineFunction *F = BB->getParent(); 4596 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB); 4597 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB); 4598 F->insert(It, copy0MBB); 4599 F->insert(It, sinkMBB); 4600 4601 // Transfer the remainder of BB and its successor edges to sinkMBB. 4602 sinkMBB->splice(sinkMBB->begin(), BB, 4603 std::next(MachineBasicBlock::iterator(MI)), BB->end()); 4604 sinkMBB->transferSuccessorsAndUpdatePHIs(BB); 4605 4606 // Next, add the true and fallthrough blocks as its successors. 4607 BB->addSuccessor(copy0MBB); 4608 BB->addSuccessor(sinkMBB); 4609 4610 if (isFPCmp) { 4611 // bc1[tf] cc, sinkMBB 4612 BuildMI(BB, DL, TII->get(Opc)) 4613 .addReg(MI.getOperand(1).getReg()) 4614 .addMBB(sinkMBB); 4615 } else { 4616 // bne rs, $0, sinkMBB 4617 BuildMI(BB, DL, TII->get(Opc)) 4618 .addReg(MI.getOperand(1).getReg()) 4619 .addReg(Mips::ZERO) 4620 .addMBB(sinkMBB); 4621 } 4622 4623 // copy0MBB: 4624 // %FalseValue = ... 4625 // # fallthrough to sinkMBB 4626 BB = copy0MBB; 4627 4628 // Update machine-CFG edges 4629 BB->addSuccessor(sinkMBB); 4630 4631 // sinkMBB: 4632 // %Result = phi [ %TrueValue, thisMBB ], [ %FalseValue, copy0MBB ] 4633 // ... 4634 BB = sinkMBB; 4635 4636 BuildMI(*BB, BB->begin(), DL, TII->get(Mips::PHI), MI.getOperand(0).getReg()) 4637 .addReg(MI.getOperand(2).getReg()) 4638 .addMBB(thisMBB) 4639 .addReg(MI.getOperand(3).getReg()) 4640 .addMBB(copy0MBB); 4641 4642 MI.eraseFromParent(); // The pseudo instruction is gone now. 4643 4644 return BB; 4645 } 4646 4647 MachineBasicBlock * 4648 MipsTargetLowering::emitPseudoD_SELECT(MachineInstr &MI, 4649 MachineBasicBlock *BB) const { 4650 assert(!(Subtarget.hasMips4() || Subtarget.hasMips32()) && 4651 "Subtarget already supports SELECT nodes with the use of" 4652 "conditional-move instructions."); 4653 4654 const TargetInstrInfo *TII = Subtarget.getInstrInfo(); 4655 DebugLoc DL = MI.getDebugLoc(); 4656 4657 // D_SELECT substitutes two SELECT nodes that goes one after another and 4658 // have the same condition operand. On machines which don't have 4659 // conditional-move instruction, it reduces unnecessary branch instructions 4660 // which are result of using two diamond patterns that are result of two 4661 // SELECT pseudo instructions. 4662 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 4663 MachineFunction::iterator It = ++BB->getIterator(); 4664 4665 // thisMBB: 4666 // ... 4667 // TrueVal = ... 4668 // setcc r1, r2, r3 4669 // bNE r1, r0, copy1MBB 4670 // fallthrough --> copy0MBB 4671 MachineBasicBlock *thisMBB = BB; 4672 MachineFunction *F = BB->getParent(); 4673 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB); 4674 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB); 4675 F->insert(It, copy0MBB); 4676 F->insert(It, sinkMBB); 4677 4678 // Transfer the remainder of BB and its successor edges to sinkMBB. 4679 sinkMBB->splice(sinkMBB->begin(), BB, 4680 std::next(MachineBasicBlock::iterator(MI)), BB->end()); 4681 sinkMBB->transferSuccessorsAndUpdatePHIs(BB); 4682 4683 // Next, add the true and fallthrough blocks as its successors. 4684 BB->addSuccessor(copy0MBB); 4685 BB->addSuccessor(sinkMBB); 4686 4687 // bne rs, $0, sinkMBB 4688 BuildMI(BB, DL, TII->get(Mips::BNE)) 4689 .addReg(MI.getOperand(2).getReg()) 4690 .addReg(Mips::ZERO) 4691 .addMBB(sinkMBB); 4692 4693 // copy0MBB: 4694 // %FalseValue = ... 4695 // # fallthrough to sinkMBB 4696 BB = copy0MBB; 4697 4698 // Update machine-CFG edges 4699 BB->addSuccessor(sinkMBB); 4700 4701 // sinkMBB: 4702 // %Result = phi [ %TrueValue, thisMBB ], [ %FalseValue, copy0MBB ] 4703 // ... 4704 BB = sinkMBB; 4705 4706 // Use two PHI nodes to select two reults 4707 BuildMI(*BB, BB->begin(), DL, TII->get(Mips::PHI), MI.getOperand(0).getReg()) 4708 .addReg(MI.getOperand(3).getReg()) 4709 .addMBB(thisMBB) 4710 .addReg(MI.getOperand(5).getReg()) 4711 .addMBB(copy0MBB); 4712 BuildMI(*BB, BB->begin(), DL, TII->get(Mips::PHI), MI.getOperand(1).getReg()) 4713 .addReg(MI.getOperand(4).getReg()) 4714 .addMBB(thisMBB) 4715 .addReg(MI.getOperand(6).getReg()) 4716 .addMBB(copy0MBB); 4717 4718 MI.eraseFromParent(); // The pseudo instruction is gone now. 4719 4720 return BB; 4721 } 4722 4723 // FIXME? Maybe this could be a TableGen attribute on some registers and 4724 // this table could be generated automatically from RegInfo. 4725 Register 4726 MipsTargetLowering::getRegisterByName(const char *RegName, LLT VT, 4727 const MachineFunction &MF) const { 4728 // The Linux kernel uses $28 and sp. 4729 if (Subtarget.isGP64bit()) { 4730 Register Reg = StringSwitch<Register>(RegName) 4731 .Case("$28", Mips::GP_64) 4732 .Case("sp", Mips::SP_64) 4733 .Default(Register()); 4734 if (Reg) 4735 return Reg; 4736 } else { 4737 Register Reg = StringSwitch<Register>(RegName) 4738 .Case("$28", Mips::GP) 4739 .Case("sp", Mips::SP) 4740 .Default(Register()); 4741 if (Reg) 4742 return Reg; 4743 } 4744 report_fatal_error("Invalid register name global variable"); 4745 } 4746 4747 MachineBasicBlock *MipsTargetLowering::emitLDR_W(MachineInstr &MI, 4748 MachineBasicBlock *BB) const { 4749 MachineFunction *MF = BB->getParent(); 4750 MachineRegisterInfo &MRI = MF->getRegInfo(); 4751 const TargetInstrInfo *TII = Subtarget.getInstrInfo(); 4752 const bool IsLittle = Subtarget.isLittle(); 4753 DebugLoc DL = MI.getDebugLoc(); 4754 4755 Register Dest = MI.getOperand(0).getReg(); 4756 Register Address = MI.getOperand(1).getReg(); 4757 unsigned Imm = MI.getOperand(2).getImm(); 4758 4759 MachineBasicBlock::iterator I(MI); 4760 4761 if (Subtarget.hasMips32r6() || Subtarget.hasMips64r6()) { 4762 // Mips release 6 can load from adress that is not naturally-aligned. 4763 Register Temp = MRI.createVirtualRegister(&Mips::GPR32RegClass); 4764 BuildMI(*BB, I, DL, TII->get(Mips::LW)) 4765 .addDef(Temp) 4766 .addUse(Address) 4767 .addImm(Imm); 4768 BuildMI(*BB, I, DL, TII->get(Mips::FILL_W)).addDef(Dest).addUse(Temp); 4769 } else { 4770 // Mips release 5 needs to use instructions that can load from an unaligned 4771 // memory address. 4772 Register LoadHalf = MRI.createVirtualRegister(&Mips::GPR32RegClass); 4773 Register LoadFull = MRI.createVirtualRegister(&Mips::GPR32RegClass); 4774 Register Undef = MRI.createVirtualRegister(&Mips::GPR32RegClass); 4775 BuildMI(*BB, I, DL, TII->get(Mips::IMPLICIT_DEF)).addDef(Undef); 4776 BuildMI(*BB, I, DL, TII->get(Mips::LWR)) 4777 .addDef(LoadHalf) 4778 .addUse(Address) 4779 .addImm(Imm + (IsLittle ? 0 : 3)) 4780 .addUse(Undef); 4781 BuildMI(*BB, I, DL, TII->get(Mips::LWL)) 4782 .addDef(LoadFull) 4783 .addUse(Address) 4784 .addImm(Imm + (IsLittle ? 3 : 0)) 4785 .addUse(LoadHalf); 4786 BuildMI(*BB, I, DL, TII->get(Mips::FILL_W)).addDef(Dest).addUse(LoadFull); 4787 } 4788 4789 MI.eraseFromParent(); 4790 return BB; 4791 } 4792 4793 MachineBasicBlock *MipsTargetLowering::emitLDR_D(MachineInstr &MI, 4794 MachineBasicBlock *BB) const { 4795 MachineFunction *MF = BB->getParent(); 4796 MachineRegisterInfo &MRI = MF->getRegInfo(); 4797 const TargetInstrInfo *TII = Subtarget.getInstrInfo(); 4798 const bool IsLittle = Subtarget.isLittle(); 4799 DebugLoc DL = MI.getDebugLoc(); 4800 4801 Register Dest = MI.getOperand(0).getReg(); 4802 Register Address = MI.getOperand(1).getReg(); 4803 unsigned Imm = MI.getOperand(2).getImm(); 4804 4805 MachineBasicBlock::iterator I(MI); 4806 4807 if (Subtarget.hasMips32r6() || Subtarget.hasMips64r6()) { 4808 // Mips release 6 can load from adress that is not naturally-aligned. 4809 if (Subtarget.isGP64bit()) { 4810 Register Temp = MRI.createVirtualRegister(&Mips::GPR64RegClass); 4811 BuildMI(*BB, I, DL, TII->get(Mips::LD)) 4812 .addDef(Temp) 4813 .addUse(Address) 4814 .addImm(Imm); 4815 BuildMI(*BB, I, DL, TII->get(Mips::FILL_D)).addDef(Dest).addUse(Temp); 4816 } else { 4817 Register Wtemp = MRI.createVirtualRegister(&Mips::MSA128WRegClass); 4818 Register Lo = MRI.createVirtualRegister(&Mips::GPR32RegClass); 4819 Register Hi = MRI.createVirtualRegister(&Mips::GPR32RegClass); 4820 BuildMI(*BB, I, DL, TII->get(Mips::LW)) 4821 .addDef(Lo) 4822 .addUse(Address) 4823 .addImm(Imm + (IsLittle ? 0 : 4)); 4824 BuildMI(*BB, I, DL, TII->get(Mips::LW)) 4825 .addDef(Hi) 4826 .addUse(Address) 4827 .addImm(Imm + (IsLittle ? 4 : 0)); 4828 BuildMI(*BB, I, DL, TII->get(Mips::FILL_W)).addDef(Wtemp).addUse(Lo); 4829 BuildMI(*BB, I, DL, TII->get(Mips::INSERT_W), Dest) 4830 .addUse(Wtemp) 4831 .addUse(Hi) 4832 .addImm(1); 4833 } 4834 } else { 4835 // Mips release 5 needs to use instructions that can load from an unaligned 4836 // memory address. 4837 Register LoHalf = MRI.createVirtualRegister(&Mips::GPR32RegClass); 4838 Register LoFull = MRI.createVirtualRegister(&Mips::GPR32RegClass); 4839 Register LoUndef = MRI.createVirtualRegister(&Mips::GPR32RegClass); 4840 Register HiHalf = MRI.createVirtualRegister(&Mips::GPR32RegClass); 4841 Register HiFull = MRI.createVirtualRegister(&Mips::GPR32RegClass); 4842 Register HiUndef = MRI.createVirtualRegister(&Mips::GPR32RegClass); 4843 Register Wtemp = MRI.createVirtualRegister(&Mips::MSA128WRegClass); 4844 BuildMI(*BB, I, DL, TII->get(Mips::IMPLICIT_DEF)).addDef(LoUndef); 4845 BuildMI(*BB, I, DL, TII->get(Mips::LWR)) 4846 .addDef(LoHalf) 4847 .addUse(Address) 4848 .addImm(Imm + (IsLittle ? 0 : 7)) 4849 .addUse(LoUndef); 4850 BuildMI(*BB, I, DL, TII->get(Mips::LWL)) 4851 .addDef(LoFull) 4852 .addUse(Address) 4853 .addImm(Imm + (IsLittle ? 3 : 4)) 4854 .addUse(LoHalf); 4855 BuildMI(*BB, I, DL, TII->get(Mips::IMPLICIT_DEF)).addDef(HiUndef); 4856 BuildMI(*BB, I, DL, TII->get(Mips::LWR)) 4857 .addDef(HiHalf) 4858 .addUse(Address) 4859 .addImm(Imm + (IsLittle ? 4 : 3)) 4860 .addUse(HiUndef); 4861 BuildMI(*BB, I, DL, TII->get(Mips::LWL)) 4862 .addDef(HiFull) 4863 .addUse(Address) 4864 .addImm(Imm + (IsLittle ? 7 : 0)) 4865 .addUse(HiHalf); 4866 BuildMI(*BB, I, DL, TII->get(Mips::FILL_W)).addDef(Wtemp).addUse(LoFull); 4867 BuildMI(*BB, I, DL, TII->get(Mips::INSERT_W), Dest) 4868 .addUse(Wtemp) 4869 .addUse(HiFull) 4870 .addImm(1); 4871 } 4872 4873 MI.eraseFromParent(); 4874 return BB; 4875 } 4876 4877 MachineBasicBlock *MipsTargetLowering::emitSTR_W(MachineInstr &MI, 4878 MachineBasicBlock *BB) const { 4879 MachineFunction *MF = BB->getParent(); 4880 MachineRegisterInfo &MRI = MF->getRegInfo(); 4881 const TargetInstrInfo *TII = Subtarget.getInstrInfo(); 4882 const bool IsLittle = Subtarget.isLittle(); 4883 DebugLoc DL = MI.getDebugLoc(); 4884 4885 Register StoreVal = MI.getOperand(0).getReg(); 4886 Register Address = MI.getOperand(1).getReg(); 4887 unsigned Imm = MI.getOperand(2).getImm(); 4888 4889 MachineBasicBlock::iterator I(MI); 4890 4891 if (Subtarget.hasMips32r6() || Subtarget.hasMips64r6()) { 4892 // Mips release 6 can store to adress that is not naturally-aligned. 4893 Register BitcastW = MRI.createVirtualRegister(&Mips::MSA128WRegClass); 4894 Register Tmp = MRI.createVirtualRegister(&Mips::GPR32RegClass); 4895 BuildMI(*BB, I, DL, TII->get(Mips::COPY)).addDef(BitcastW).addUse(StoreVal); 4896 BuildMI(*BB, I, DL, TII->get(Mips::COPY_S_W)) 4897 .addDef(Tmp) 4898 .addUse(BitcastW) 4899 .addImm(0); 4900 BuildMI(*BB, I, DL, TII->get(Mips::SW)) 4901 .addUse(Tmp) 4902 .addUse(Address) 4903 .addImm(Imm); 4904 } else { 4905 // Mips release 5 needs to use instructions that can store to an unaligned 4906 // memory address. 4907 Register Tmp = MRI.createVirtualRegister(&Mips::GPR32RegClass); 4908 BuildMI(*BB, I, DL, TII->get(Mips::COPY_S_W)) 4909 .addDef(Tmp) 4910 .addUse(StoreVal) 4911 .addImm(0); 4912 BuildMI(*BB, I, DL, TII->get(Mips::SWR)) 4913 .addUse(Tmp) 4914 .addUse(Address) 4915 .addImm(Imm + (IsLittle ? 0 : 3)); 4916 BuildMI(*BB, I, DL, TII->get(Mips::SWL)) 4917 .addUse(Tmp) 4918 .addUse(Address) 4919 .addImm(Imm + (IsLittle ? 3 : 0)); 4920 } 4921 4922 MI.eraseFromParent(); 4923 4924 return BB; 4925 } 4926 4927 MachineBasicBlock *MipsTargetLowering::emitSTR_D(MachineInstr &MI, 4928 MachineBasicBlock *BB) const { 4929 MachineFunction *MF = BB->getParent(); 4930 MachineRegisterInfo &MRI = MF->getRegInfo(); 4931 const TargetInstrInfo *TII = Subtarget.getInstrInfo(); 4932 const bool IsLittle = Subtarget.isLittle(); 4933 DebugLoc DL = MI.getDebugLoc(); 4934 4935 Register StoreVal = MI.getOperand(0).getReg(); 4936 Register Address = MI.getOperand(1).getReg(); 4937 unsigned Imm = MI.getOperand(2).getImm(); 4938 4939 MachineBasicBlock::iterator I(MI); 4940 4941 if (Subtarget.hasMips32r6() || Subtarget.hasMips64r6()) { 4942 // Mips release 6 can store to adress that is not naturally-aligned. 4943 if (Subtarget.isGP64bit()) { 4944 Register BitcastD = MRI.createVirtualRegister(&Mips::MSA128DRegClass); 4945 Register Lo = MRI.createVirtualRegister(&Mips::GPR64RegClass); 4946 BuildMI(*BB, I, DL, TII->get(Mips::COPY)) 4947 .addDef(BitcastD) 4948 .addUse(StoreVal); 4949 BuildMI(*BB, I, DL, TII->get(Mips::COPY_S_D)) 4950 .addDef(Lo) 4951 .addUse(BitcastD) 4952 .addImm(0); 4953 BuildMI(*BB, I, DL, TII->get(Mips::SD)) 4954 .addUse(Lo) 4955 .addUse(Address) 4956 .addImm(Imm); 4957 } else { 4958 Register BitcastW = MRI.createVirtualRegister(&Mips::MSA128WRegClass); 4959 Register Lo = MRI.createVirtualRegister(&Mips::GPR32RegClass); 4960 Register Hi = MRI.createVirtualRegister(&Mips::GPR32RegClass); 4961 BuildMI(*BB, I, DL, TII->get(Mips::COPY)) 4962 .addDef(BitcastW) 4963 .addUse(StoreVal); 4964 BuildMI(*BB, I, DL, TII->get(Mips::COPY_S_W)) 4965 .addDef(Lo) 4966 .addUse(BitcastW) 4967 .addImm(0); 4968 BuildMI(*BB, I, DL, TII->get(Mips::COPY_S_W)) 4969 .addDef(Hi) 4970 .addUse(BitcastW) 4971 .addImm(1); 4972 BuildMI(*BB, I, DL, TII->get(Mips::SW)) 4973 .addUse(Lo) 4974 .addUse(Address) 4975 .addImm(Imm + (IsLittle ? 0 : 4)); 4976 BuildMI(*BB, I, DL, TII->get(Mips::SW)) 4977 .addUse(Hi) 4978 .addUse(Address) 4979 .addImm(Imm + (IsLittle ? 4 : 0)); 4980 } 4981 } else { 4982 // Mips release 5 needs to use instructions that can store to an unaligned 4983 // memory address. 4984 Register Bitcast = MRI.createVirtualRegister(&Mips::MSA128WRegClass); 4985 Register Lo = MRI.createVirtualRegister(&Mips::GPR32RegClass); 4986 Register Hi = MRI.createVirtualRegister(&Mips::GPR32RegClass); 4987 BuildMI(*BB, I, DL, TII->get(Mips::COPY)).addDef(Bitcast).addUse(StoreVal); 4988 BuildMI(*BB, I, DL, TII->get(Mips::COPY_S_W)) 4989 .addDef(Lo) 4990 .addUse(Bitcast) 4991 .addImm(0); 4992 BuildMI(*BB, I, DL, TII->get(Mips::COPY_S_W)) 4993 .addDef(Hi) 4994 .addUse(Bitcast) 4995 .addImm(1); 4996 BuildMI(*BB, I, DL, TII->get(Mips::SWR)) 4997 .addUse(Lo) 4998 .addUse(Address) 4999 .addImm(Imm + (IsLittle ? 0 : 3)); 5000 BuildMI(*BB, I, DL, TII->get(Mips::SWL)) 5001 .addUse(Lo) 5002 .addUse(Address) 5003 .addImm(Imm + (IsLittle ? 3 : 0)); 5004 BuildMI(*BB, I, DL, TII->get(Mips::SWR)) 5005 .addUse(Hi) 5006 .addUse(Address) 5007 .addImm(Imm + (IsLittle ? 4 : 7)); 5008 BuildMI(*BB, I, DL, TII->get(Mips::SWL)) 5009 .addUse(Hi) 5010 .addUse(Address) 5011 .addImm(Imm + (IsLittle ? 7 : 4)); 5012 } 5013 5014 MI.eraseFromParent(); 5015 return BB; 5016 } 5017