1 //===-- MipsISelLowering.cpp - Mips DAG Lowering Implementation -----------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file defines the interfaces that Mips uses to lower LLVM code into a 11 // selection DAG. 12 // 13 //===----------------------------------------------------------------------===// 14 #define DEBUG_TYPE "mips-lower" 15 #include "MipsISelLowering.h" 16 #include "InstPrinter/MipsInstPrinter.h" 17 #include "MCTargetDesc/MipsBaseInfo.h" 18 #include "MipsMachineFunction.h" 19 #include "MipsSubtarget.h" 20 #include "MipsTargetMachine.h" 21 #include "MipsTargetObjectFile.h" 22 #include "llvm/ADT/Statistic.h" 23 #include "llvm/ADT/StringSwitch.h" 24 #include "llvm/CodeGen/CallingConvLower.h" 25 #include "llvm/CodeGen/MachineFrameInfo.h" 26 #include "llvm/CodeGen/MachineFunction.h" 27 #include "llvm/CodeGen/MachineInstrBuilder.h" 28 #include "llvm/CodeGen/MachineRegisterInfo.h" 29 #include "llvm/CodeGen/SelectionDAGISel.h" 30 #include "llvm/CodeGen/ValueTypes.h" 31 #include "llvm/IR/CallingConv.h" 32 #include "llvm/IR/DerivedTypes.h" 33 #include "llvm/IR/GlobalVariable.h" 34 #include "llvm/Support/CommandLine.h" 35 #include "llvm/Support/Debug.h" 36 #include "llvm/Support/ErrorHandling.h" 37 #include "llvm/Support/raw_ostream.h" 38 #include <cctype> 39 40 using namespace llvm; 41 42 STATISTIC(NumTailCalls, "Number of tail calls"); 43 44 static cl::opt<bool> 45 LargeGOT("mxgot", cl::Hidden, 46 cl::desc("MIPS: Enable GOT larger than 64k."), cl::init(false)); 47 48 static cl::opt<bool> 49 NoZeroDivCheck("mno-check-zero-division", cl::Hidden, 50 cl::desc("MIPS: Don't trap on integer division by zero."), 51 cl::init(false)); 52 53 static const uint16_t O32IntRegs[4] = { 54 Mips::A0, Mips::A1, Mips::A2, Mips::A3 55 }; 56 57 static const uint16_t Mips64IntRegs[8] = { 58 Mips::A0_64, Mips::A1_64, Mips::A2_64, Mips::A3_64, 59 Mips::T0_64, Mips::T1_64, Mips::T2_64, Mips::T3_64 60 }; 61 62 static const uint16_t Mips64DPRegs[8] = { 63 Mips::D12_64, Mips::D13_64, Mips::D14_64, Mips::D15_64, 64 Mips::D16_64, Mips::D17_64, Mips::D18_64, Mips::D19_64 65 }; 66 67 // If I is a shifted mask, set the size (Size) and the first bit of the 68 // mask (Pos), and return true. 69 // For example, if I is 0x003ff800, (Pos, Size) = (11, 11). 70 static bool isShiftedMask(uint64_t I, uint64_t &Pos, uint64_t &Size) { 71 if (!isShiftedMask_64(I)) 72 return false; 73 74 Size = CountPopulation_64(I); 75 Pos = countTrailingZeros(I); 76 return true; 77 } 78 79 SDValue MipsTargetLowering::getGlobalReg(SelectionDAG &DAG, EVT Ty) const { 80 MipsFunctionInfo *FI = DAG.getMachineFunction().getInfo<MipsFunctionInfo>(); 81 return DAG.getRegister(FI->getGlobalBaseReg(), Ty); 82 } 83 84 SDValue MipsTargetLowering::getTargetNode(GlobalAddressSDNode *N, EVT Ty, 85 SelectionDAG &DAG, 86 unsigned Flag) const { 87 return DAG.getTargetGlobalAddress(N->getGlobal(), SDLoc(N), Ty, 0, Flag); 88 } 89 90 SDValue MipsTargetLowering::getTargetNode(ExternalSymbolSDNode *N, EVT Ty, 91 SelectionDAG &DAG, 92 unsigned Flag) const { 93 return DAG.getTargetExternalSymbol(N->getSymbol(), Ty, Flag); 94 } 95 96 SDValue MipsTargetLowering::getTargetNode(BlockAddressSDNode *N, EVT Ty, 97 SelectionDAG &DAG, 98 unsigned Flag) const { 99 return DAG.getTargetBlockAddress(N->getBlockAddress(), Ty, 0, Flag); 100 } 101 102 SDValue MipsTargetLowering::getTargetNode(JumpTableSDNode *N, EVT Ty, 103 SelectionDAG &DAG, 104 unsigned Flag) const { 105 return DAG.getTargetJumpTable(N->getIndex(), Ty, Flag); 106 } 107 108 SDValue MipsTargetLowering::getTargetNode(ConstantPoolSDNode *N, EVT Ty, 109 SelectionDAG &DAG, 110 unsigned Flag) const { 111 return DAG.getTargetConstantPool(N->getConstVal(), Ty, N->getAlignment(), 112 N->getOffset(), Flag); 113 } 114 115 const char *MipsTargetLowering::getTargetNodeName(unsigned Opcode) const { 116 switch (Opcode) { 117 case MipsISD::JmpLink: return "MipsISD::JmpLink"; 118 case MipsISD::TailCall: return "MipsISD::TailCall"; 119 case MipsISD::Hi: return "MipsISD::Hi"; 120 case MipsISD::Lo: return "MipsISD::Lo"; 121 case MipsISD::GPRel: return "MipsISD::GPRel"; 122 case MipsISD::ThreadPointer: return "MipsISD::ThreadPointer"; 123 case MipsISD::Ret: return "MipsISD::Ret"; 124 case MipsISD::EH_RETURN: return "MipsISD::EH_RETURN"; 125 case MipsISD::FPBrcond: return "MipsISD::FPBrcond"; 126 case MipsISD::FPCmp: return "MipsISD::FPCmp"; 127 case MipsISD::CMovFP_T: return "MipsISD::CMovFP_T"; 128 case MipsISD::CMovFP_F: return "MipsISD::CMovFP_F"; 129 case MipsISD::TruncIntFP: return "MipsISD::TruncIntFP"; 130 case MipsISD::MFHI: return "MipsISD::MFHI"; 131 case MipsISD::MFLO: return "MipsISD::MFLO"; 132 case MipsISD::MTLOHI: return "MipsISD::MTLOHI"; 133 case MipsISD::Mult: return "MipsISD::Mult"; 134 case MipsISD::Multu: return "MipsISD::Multu"; 135 case MipsISD::MAdd: return "MipsISD::MAdd"; 136 case MipsISD::MAddu: return "MipsISD::MAddu"; 137 case MipsISD::MSub: return "MipsISD::MSub"; 138 case MipsISD::MSubu: return "MipsISD::MSubu"; 139 case MipsISD::DivRem: return "MipsISD::DivRem"; 140 case MipsISD::DivRemU: return "MipsISD::DivRemU"; 141 case MipsISD::DivRem16: return "MipsISD::DivRem16"; 142 case MipsISD::DivRemU16: return "MipsISD::DivRemU16"; 143 case MipsISD::BuildPairF64: return "MipsISD::BuildPairF64"; 144 case MipsISD::ExtractElementF64: return "MipsISD::ExtractElementF64"; 145 case MipsISD::Wrapper: return "MipsISD::Wrapper"; 146 case MipsISD::Sync: return "MipsISD::Sync"; 147 case MipsISD::Ext: return "MipsISD::Ext"; 148 case MipsISD::Ins: return "MipsISD::Ins"; 149 case MipsISD::LWL: return "MipsISD::LWL"; 150 case MipsISD::LWR: return "MipsISD::LWR"; 151 case MipsISD::SWL: return "MipsISD::SWL"; 152 case MipsISD::SWR: return "MipsISD::SWR"; 153 case MipsISD::LDL: return "MipsISD::LDL"; 154 case MipsISD::LDR: return "MipsISD::LDR"; 155 case MipsISD::SDL: return "MipsISD::SDL"; 156 case MipsISD::SDR: return "MipsISD::SDR"; 157 case MipsISD::EXTP: return "MipsISD::EXTP"; 158 case MipsISD::EXTPDP: return "MipsISD::EXTPDP"; 159 case MipsISD::EXTR_S_H: return "MipsISD::EXTR_S_H"; 160 case MipsISD::EXTR_W: return "MipsISD::EXTR_W"; 161 case MipsISD::EXTR_R_W: return "MipsISD::EXTR_R_W"; 162 case MipsISD::EXTR_RS_W: return "MipsISD::EXTR_RS_W"; 163 case MipsISD::SHILO: return "MipsISD::SHILO"; 164 case MipsISD::MTHLIP: return "MipsISD::MTHLIP"; 165 case MipsISD::MULT: return "MipsISD::MULT"; 166 case MipsISD::MULTU: return "MipsISD::MULTU"; 167 case MipsISD::MADD_DSP: return "MipsISD::MADD_DSP"; 168 case MipsISD::MADDU_DSP: return "MipsISD::MADDU_DSP"; 169 case MipsISD::MSUB_DSP: return "MipsISD::MSUB_DSP"; 170 case MipsISD::MSUBU_DSP: return "MipsISD::MSUBU_DSP"; 171 case MipsISD::SHLL_DSP: return "MipsISD::SHLL_DSP"; 172 case MipsISD::SHRA_DSP: return "MipsISD::SHRA_DSP"; 173 case MipsISD::SHRL_DSP: return "MipsISD::SHRL_DSP"; 174 case MipsISD::SETCC_DSP: return "MipsISD::SETCC_DSP"; 175 case MipsISD::SELECT_CC_DSP: return "MipsISD::SELECT_CC_DSP"; 176 case MipsISD::VALL_ZERO: return "MipsISD::VALL_ZERO"; 177 case MipsISD::VANY_ZERO: return "MipsISD::VANY_ZERO"; 178 case MipsISD::VALL_NONZERO: return "MipsISD::VALL_NONZERO"; 179 case MipsISD::VANY_NONZERO: return "MipsISD::VANY_NONZERO"; 180 case MipsISD::VCEQ: return "MipsISD::VCEQ"; 181 case MipsISD::VCLE_S: return "MipsISD::VCLE_S"; 182 case MipsISD::VCLE_U: return "MipsISD::VCLE_U"; 183 case MipsISD::VCLT_S: return "MipsISD::VCLT_S"; 184 case MipsISD::VCLT_U: return "MipsISD::VCLT_U"; 185 case MipsISD::VSMAX: return "MipsISD::VSMAX"; 186 case MipsISD::VSMIN: return "MipsISD::VSMIN"; 187 case MipsISD::VUMAX: return "MipsISD::VUMAX"; 188 case MipsISD::VUMIN: return "MipsISD::VUMIN"; 189 case MipsISD::VEXTRACT_SEXT_ELT: return "MipsISD::VEXTRACT_SEXT_ELT"; 190 case MipsISD::VEXTRACT_ZEXT_ELT: return "MipsISD::VEXTRACT_ZEXT_ELT"; 191 case MipsISD::VNOR: return "MipsISD::VNOR"; 192 case MipsISD::VSHF: return "MipsISD::VSHF"; 193 case MipsISD::SHF: return "MipsISD::SHF"; 194 case MipsISD::ILVEV: return "MipsISD::ILVEV"; 195 case MipsISD::ILVOD: return "MipsISD::ILVOD"; 196 case MipsISD::ILVL: return "MipsISD::ILVL"; 197 case MipsISD::ILVR: return "MipsISD::ILVR"; 198 case MipsISD::PCKEV: return "MipsISD::PCKEV"; 199 case MipsISD::PCKOD: return "MipsISD::PCKOD"; 200 default: return NULL; 201 } 202 } 203 204 MipsTargetLowering:: 205 MipsTargetLowering(MipsTargetMachine &TM) 206 : TargetLowering(TM, new MipsTargetObjectFile()), 207 Subtarget(&TM.getSubtarget<MipsSubtarget>()), 208 HasMips64(Subtarget->hasMips64()), IsN64(Subtarget->isABI_N64()), 209 IsO32(Subtarget->isABI_O32()) { 210 // Mips does not have i1 type, so use i32 for 211 // setcc operations results (slt, sgt, ...). 212 setBooleanContents(ZeroOrOneBooleanContent); 213 setBooleanVectorContents(ZeroOrNegativeOneBooleanContent); 214 215 // Load extented operations for i1 types must be promoted 216 setLoadExtAction(ISD::EXTLOAD, MVT::i1, Promote); 217 setLoadExtAction(ISD::ZEXTLOAD, MVT::i1, Promote); 218 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote); 219 220 // MIPS doesn't have extending float->double load/store 221 setLoadExtAction(ISD::EXTLOAD, MVT::f32, Expand); 222 setTruncStoreAction(MVT::f64, MVT::f32, Expand); 223 224 // Used by legalize types to correctly generate the setcc result. 225 // Without this, every float setcc comes with a AND/OR with the result, 226 // we don't want this, since the fpcmp result goes to a flag register, 227 // which is used implicitly by brcond and select operations. 228 AddPromotedToType(ISD::SETCC, MVT::i1, MVT::i32); 229 230 // Mips Custom Operations 231 setOperationAction(ISD::BR_JT, MVT::Other, Custom); 232 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom); 233 setOperationAction(ISD::BlockAddress, MVT::i32, Custom); 234 setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom); 235 setOperationAction(ISD::JumpTable, MVT::i32, Custom); 236 setOperationAction(ISD::ConstantPool, MVT::i32, Custom); 237 setOperationAction(ISD::SELECT, MVT::f32, Custom); 238 setOperationAction(ISD::SELECT, MVT::f64, Custom); 239 setOperationAction(ISD::SELECT, MVT::i32, Custom); 240 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom); 241 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom); 242 setOperationAction(ISD::SETCC, MVT::f32, Custom); 243 setOperationAction(ISD::SETCC, MVT::f64, Custom); 244 setOperationAction(ISD::BRCOND, MVT::Other, Custom); 245 setOperationAction(ISD::VASTART, MVT::Other, Custom); 246 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom); 247 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom); 248 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom); 249 250 if (!TM.Options.NoNaNsFPMath) { 251 setOperationAction(ISD::FABS, MVT::f32, Custom); 252 setOperationAction(ISD::FABS, MVT::f64, Custom); 253 } 254 255 if (HasMips64) { 256 setOperationAction(ISD::GlobalAddress, MVT::i64, Custom); 257 setOperationAction(ISD::BlockAddress, MVT::i64, Custom); 258 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom); 259 setOperationAction(ISD::JumpTable, MVT::i64, Custom); 260 setOperationAction(ISD::ConstantPool, MVT::i64, Custom); 261 setOperationAction(ISD::SELECT, MVT::i64, Custom); 262 setOperationAction(ISD::LOAD, MVT::i64, Custom); 263 setOperationAction(ISD::STORE, MVT::i64, Custom); 264 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom); 265 } 266 267 if (!HasMips64) { 268 setOperationAction(ISD::SHL_PARTS, MVT::i32, Custom); 269 setOperationAction(ISD::SRA_PARTS, MVT::i32, Custom); 270 setOperationAction(ISD::SRL_PARTS, MVT::i32, Custom); 271 } 272 273 setOperationAction(ISD::ADD, MVT::i32, Custom); 274 if (HasMips64) 275 setOperationAction(ISD::ADD, MVT::i64, Custom); 276 277 setOperationAction(ISD::SDIV, MVT::i32, Expand); 278 setOperationAction(ISD::SREM, MVT::i32, Expand); 279 setOperationAction(ISD::UDIV, MVT::i32, Expand); 280 setOperationAction(ISD::UREM, MVT::i32, Expand); 281 setOperationAction(ISD::SDIV, MVT::i64, Expand); 282 setOperationAction(ISD::SREM, MVT::i64, Expand); 283 setOperationAction(ISD::UDIV, MVT::i64, Expand); 284 setOperationAction(ISD::UREM, MVT::i64, Expand); 285 286 // Operations not directly supported by Mips. 287 setOperationAction(ISD::BR_CC, MVT::f32, Expand); 288 setOperationAction(ISD::BR_CC, MVT::f64, Expand); 289 setOperationAction(ISD::BR_CC, MVT::i32, Expand); 290 setOperationAction(ISD::BR_CC, MVT::i64, Expand); 291 setOperationAction(ISD::SELECT_CC, MVT::Other, Expand); 292 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand); 293 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Expand); 294 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand); 295 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Expand); 296 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand); 297 setOperationAction(ISD::CTPOP, MVT::i32, Expand); 298 setOperationAction(ISD::CTPOP, MVT::i64, Expand); 299 setOperationAction(ISD::CTTZ, MVT::i32, Expand); 300 setOperationAction(ISD::CTTZ, MVT::i64, Expand); 301 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32, Expand); 302 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i64, Expand); 303 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32, Expand); 304 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Expand); 305 setOperationAction(ISD::ROTL, MVT::i32, Expand); 306 setOperationAction(ISD::ROTL, MVT::i64, Expand); 307 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Expand); 308 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64, Expand); 309 310 if (!Subtarget->hasMips32r2()) 311 setOperationAction(ISD::ROTR, MVT::i32, Expand); 312 313 if (!Subtarget->hasMips64r2()) 314 setOperationAction(ISD::ROTR, MVT::i64, Expand); 315 316 setOperationAction(ISD::FSIN, MVT::f32, Expand); 317 setOperationAction(ISD::FSIN, MVT::f64, Expand); 318 setOperationAction(ISD::FCOS, MVT::f32, Expand); 319 setOperationAction(ISD::FCOS, MVT::f64, Expand); 320 setOperationAction(ISD::FSINCOS, MVT::f32, Expand); 321 setOperationAction(ISD::FSINCOS, MVT::f64, Expand); 322 setOperationAction(ISD::FPOWI, MVT::f32, Expand); 323 setOperationAction(ISD::FPOW, MVT::f32, Expand); 324 setOperationAction(ISD::FPOW, MVT::f64, Expand); 325 setOperationAction(ISD::FLOG, MVT::f32, Expand); 326 setOperationAction(ISD::FLOG2, MVT::f32, Expand); 327 setOperationAction(ISD::FLOG10, MVT::f32, Expand); 328 setOperationAction(ISD::FEXP, MVT::f32, Expand); 329 setOperationAction(ISD::FMA, MVT::f32, Expand); 330 setOperationAction(ISD::FMA, MVT::f64, Expand); 331 setOperationAction(ISD::FREM, MVT::f32, Expand); 332 setOperationAction(ISD::FREM, MVT::f64, Expand); 333 334 if (!TM.Options.NoNaNsFPMath) { 335 setOperationAction(ISD::FNEG, MVT::f32, Expand); 336 setOperationAction(ISD::FNEG, MVT::f64, Expand); 337 } 338 339 setOperationAction(ISD::EH_RETURN, MVT::Other, Custom); 340 341 setOperationAction(ISD::VAARG, MVT::Other, Expand); 342 setOperationAction(ISD::VACOPY, MVT::Other, Expand); 343 setOperationAction(ISD::VAEND, MVT::Other, Expand); 344 345 // Use the default for now 346 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand); 347 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand); 348 349 setOperationAction(ISD::ATOMIC_LOAD, MVT::i32, Expand); 350 setOperationAction(ISD::ATOMIC_LOAD, MVT::i64, Expand); 351 setOperationAction(ISD::ATOMIC_STORE, MVT::i32, Expand); 352 setOperationAction(ISD::ATOMIC_STORE, MVT::i64, Expand); 353 354 setInsertFencesForAtomic(true); 355 356 if (!Subtarget->hasSEInReg()) { 357 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8, Expand); 358 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand); 359 } 360 361 if (!Subtarget->hasBitCount()) { 362 setOperationAction(ISD::CTLZ, MVT::i32, Expand); 363 setOperationAction(ISD::CTLZ, MVT::i64, Expand); 364 } 365 366 if (!Subtarget->hasSwap()) { 367 setOperationAction(ISD::BSWAP, MVT::i32, Expand); 368 setOperationAction(ISD::BSWAP, MVT::i64, Expand); 369 } 370 371 if (HasMips64) { 372 setLoadExtAction(ISD::SEXTLOAD, MVT::i32, Custom); 373 setLoadExtAction(ISD::ZEXTLOAD, MVT::i32, Custom); 374 setLoadExtAction(ISD::EXTLOAD, MVT::i32, Custom); 375 setTruncStoreAction(MVT::i64, MVT::i32, Custom); 376 } 377 378 setOperationAction(ISD::TRAP, MVT::Other, Legal); 379 380 setTargetDAGCombine(ISD::SDIVREM); 381 setTargetDAGCombine(ISD::UDIVREM); 382 setTargetDAGCombine(ISD::SELECT); 383 setTargetDAGCombine(ISD::AND); 384 setTargetDAGCombine(ISD::OR); 385 setTargetDAGCombine(ISD::ADD); 386 387 setMinFunctionAlignment(HasMips64 ? 3 : 2); 388 389 setStackPointerRegisterToSaveRestore(IsN64 ? Mips::SP_64 : Mips::SP); 390 391 setExceptionPointerRegister(IsN64 ? Mips::A0_64 : Mips::A0); 392 setExceptionSelectorRegister(IsN64 ? Mips::A1_64 : Mips::A1); 393 394 MaxStoresPerMemcpy = 16; 395 396 isMicroMips = Subtarget->inMicroMipsMode(); 397 } 398 399 const MipsTargetLowering *MipsTargetLowering::create(MipsTargetMachine &TM) { 400 if (TM.getSubtargetImpl()->inMips16Mode()) 401 return llvm::createMips16TargetLowering(TM); 402 403 return llvm::createMipsSETargetLowering(TM); 404 } 405 406 EVT MipsTargetLowering::getSetCCResultType(LLVMContext &, EVT VT) const { 407 if (!VT.isVector()) 408 return MVT::i32; 409 return VT.changeVectorElementTypeToInteger(); 410 } 411 412 static SDValue performDivRemCombine(SDNode *N, SelectionDAG &DAG, 413 TargetLowering::DAGCombinerInfo &DCI, 414 const MipsSubtarget *Subtarget) { 415 if (DCI.isBeforeLegalizeOps()) 416 return SDValue(); 417 418 EVT Ty = N->getValueType(0); 419 unsigned LO = (Ty == MVT::i32) ? Mips::LO0 : Mips::LO0_64; 420 unsigned HI = (Ty == MVT::i32) ? Mips::HI0 : Mips::HI0_64; 421 unsigned Opc = N->getOpcode() == ISD::SDIVREM ? MipsISD::DivRem16 : 422 MipsISD::DivRemU16; 423 SDLoc DL(N); 424 425 SDValue DivRem = DAG.getNode(Opc, DL, MVT::Glue, 426 N->getOperand(0), N->getOperand(1)); 427 SDValue InChain = DAG.getEntryNode(); 428 SDValue InGlue = DivRem; 429 430 // insert MFLO 431 if (N->hasAnyUseOfValue(0)) { 432 SDValue CopyFromLo = DAG.getCopyFromReg(InChain, DL, LO, Ty, 433 InGlue); 434 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), CopyFromLo); 435 InChain = CopyFromLo.getValue(1); 436 InGlue = CopyFromLo.getValue(2); 437 } 438 439 // insert MFHI 440 if (N->hasAnyUseOfValue(1)) { 441 SDValue CopyFromHi = DAG.getCopyFromReg(InChain, DL, 442 HI, Ty, InGlue); 443 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), CopyFromHi); 444 } 445 446 return SDValue(); 447 } 448 449 static Mips::CondCode condCodeToFCC(ISD::CondCode CC) { 450 switch (CC) { 451 default: llvm_unreachable("Unknown fp condition code!"); 452 case ISD::SETEQ: 453 case ISD::SETOEQ: return Mips::FCOND_OEQ; 454 case ISD::SETUNE: return Mips::FCOND_UNE; 455 case ISD::SETLT: 456 case ISD::SETOLT: return Mips::FCOND_OLT; 457 case ISD::SETGT: 458 case ISD::SETOGT: return Mips::FCOND_OGT; 459 case ISD::SETLE: 460 case ISD::SETOLE: return Mips::FCOND_OLE; 461 case ISD::SETGE: 462 case ISD::SETOGE: return Mips::FCOND_OGE; 463 case ISD::SETULT: return Mips::FCOND_ULT; 464 case ISD::SETULE: return Mips::FCOND_ULE; 465 case ISD::SETUGT: return Mips::FCOND_UGT; 466 case ISD::SETUGE: return Mips::FCOND_UGE; 467 case ISD::SETUO: return Mips::FCOND_UN; 468 case ISD::SETO: return Mips::FCOND_OR; 469 case ISD::SETNE: 470 case ISD::SETONE: return Mips::FCOND_ONE; 471 case ISD::SETUEQ: return Mips::FCOND_UEQ; 472 } 473 } 474 475 476 /// This function returns true if the floating point conditional branches and 477 /// conditional moves which use condition code CC should be inverted. 478 static bool invertFPCondCodeUser(Mips::CondCode CC) { 479 if (CC >= Mips::FCOND_F && CC <= Mips::FCOND_NGT) 480 return false; 481 482 assert((CC >= Mips::FCOND_T && CC <= Mips::FCOND_GT) && 483 "Illegal Condition Code"); 484 485 return true; 486 } 487 488 // Creates and returns an FPCmp node from a setcc node. 489 // Returns Op if setcc is not a floating point comparison. 490 static SDValue createFPCmp(SelectionDAG &DAG, const SDValue &Op) { 491 // must be a SETCC node 492 if (Op.getOpcode() != ISD::SETCC) 493 return Op; 494 495 SDValue LHS = Op.getOperand(0); 496 497 if (!LHS.getValueType().isFloatingPoint()) 498 return Op; 499 500 SDValue RHS = Op.getOperand(1); 501 SDLoc DL(Op); 502 503 // Assume the 3rd operand is a CondCodeSDNode. Add code to check the type of 504 // node if necessary. 505 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get(); 506 507 return DAG.getNode(MipsISD::FPCmp, DL, MVT::Glue, LHS, RHS, 508 DAG.getConstant(condCodeToFCC(CC), MVT::i32)); 509 } 510 511 // Creates and returns a CMovFPT/F node. 512 static SDValue createCMovFP(SelectionDAG &DAG, SDValue Cond, SDValue True, 513 SDValue False, SDLoc DL) { 514 ConstantSDNode *CC = cast<ConstantSDNode>(Cond.getOperand(2)); 515 bool invert = invertFPCondCodeUser((Mips::CondCode)CC->getSExtValue()); 516 SDValue FCC0 = DAG.getRegister(Mips::FCC0, MVT::i32); 517 518 return DAG.getNode((invert ? MipsISD::CMovFP_F : MipsISD::CMovFP_T), DL, 519 True.getValueType(), True, FCC0, False, Cond); 520 } 521 522 static SDValue performSELECTCombine(SDNode *N, SelectionDAG &DAG, 523 TargetLowering::DAGCombinerInfo &DCI, 524 const MipsSubtarget *Subtarget) { 525 if (DCI.isBeforeLegalizeOps()) 526 return SDValue(); 527 528 SDValue SetCC = N->getOperand(0); 529 530 if ((SetCC.getOpcode() != ISD::SETCC) || 531 !SetCC.getOperand(0).getValueType().isInteger()) 532 return SDValue(); 533 534 SDValue False = N->getOperand(2); 535 EVT FalseTy = False.getValueType(); 536 537 if (!FalseTy.isInteger()) 538 return SDValue(); 539 540 ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(False); 541 542 // If the RHS (False) is 0, we swap the order of the operands 543 // of ISD::SELECT (obviously also inverting the condition) so that we can 544 // take advantage of conditional moves using the $0 register. 545 // Example: 546 // return (a != 0) ? x : 0; 547 // load $reg, x 548 // movz $reg, $0, a 549 if (!FalseC) 550 return SDValue(); 551 552 const SDLoc DL(N); 553 554 if (!FalseC->getZExtValue()) { 555 ISD::CondCode CC = cast<CondCodeSDNode>(SetCC.getOperand(2))->get(); 556 SDValue True = N->getOperand(1); 557 558 SetCC = DAG.getSetCC(DL, SetCC.getValueType(), SetCC.getOperand(0), 559 SetCC.getOperand(1), ISD::getSetCCInverse(CC, true)); 560 561 return DAG.getNode(ISD::SELECT, DL, FalseTy, SetCC, False, True); 562 } 563 564 // If both operands are integer constants there's a possibility that we 565 // can do some interesting optimizations. 566 SDValue True = N->getOperand(1); 567 ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(True); 568 569 if (!TrueC || !True.getValueType().isInteger()) 570 return SDValue(); 571 572 // We'll also ignore MVT::i64 operands as this optimizations proves 573 // to be ineffective because of the required sign extensions as the result 574 // of a SETCC operator is always MVT::i32 for non-vector types. 575 if (True.getValueType() == MVT::i64) 576 return SDValue(); 577 578 int64_t Diff = TrueC->getSExtValue() - FalseC->getSExtValue(); 579 580 // 1) (a < x) ? y : y-1 581 // slti $reg1, a, x 582 // addiu $reg2, $reg1, y-1 583 if (Diff == 1) 584 return DAG.getNode(ISD::ADD, DL, SetCC.getValueType(), SetCC, False); 585 586 // 2) (a < x) ? y-1 : y 587 // slti $reg1, a, x 588 // xor $reg1, $reg1, 1 589 // addiu $reg2, $reg1, y-1 590 if (Diff == -1) { 591 ISD::CondCode CC = cast<CondCodeSDNode>(SetCC.getOperand(2))->get(); 592 SetCC = DAG.getSetCC(DL, SetCC.getValueType(), SetCC.getOperand(0), 593 SetCC.getOperand(1), ISD::getSetCCInverse(CC, true)); 594 return DAG.getNode(ISD::ADD, DL, SetCC.getValueType(), SetCC, True); 595 } 596 597 // Couldn't optimize. 598 return SDValue(); 599 } 600 601 static SDValue performANDCombine(SDNode *N, SelectionDAG &DAG, 602 TargetLowering::DAGCombinerInfo &DCI, 603 const MipsSubtarget *Subtarget) { 604 // Pattern match EXT. 605 // $dst = and ((sra or srl) $src , pos), (2**size - 1) 606 // => ext $dst, $src, size, pos 607 if (DCI.isBeforeLegalizeOps() || !Subtarget->hasExtractInsert()) 608 return SDValue(); 609 610 SDValue ShiftRight = N->getOperand(0), Mask = N->getOperand(1); 611 unsigned ShiftRightOpc = ShiftRight.getOpcode(); 612 613 // Op's first operand must be a shift right. 614 if (ShiftRightOpc != ISD::SRA && ShiftRightOpc != ISD::SRL) 615 return SDValue(); 616 617 // The second operand of the shift must be an immediate. 618 ConstantSDNode *CN; 619 if (!(CN = dyn_cast<ConstantSDNode>(ShiftRight.getOperand(1)))) 620 return SDValue(); 621 622 uint64_t Pos = CN->getZExtValue(); 623 uint64_t SMPos, SMSize; 624 625 // Op's second operand must be a shifted mask. 626 if (!(CN = dyn_cast<ConstantSDNode>(Mask)) || 627 !isShiftedMask(CN->getZExtValue(), SMPos, SMSize)) 628 return SDValue(); 629 630 // Return if the shifted mask does not start at bit 0 or the sum of its size 631 // and Pos exceeds the word's size. 632 EVT ValTy = N->getValueType(0); 633 if (SMPos != 0 || Pos + SMSize > ValTy.getSizeInBits()) 634 return SDValue(); 635 636 return DAG.getNode(MipsISD::Ext, SDLoc(N), ValTy, 637 ShiftRight.getOperand(0), DAG.getConstant(Pos, MVT::i32), 638 DAG.getConstant(SMSize, MVT::i32)); 639 } 640 641 static SDValue performORCombine(SDNode *N, SelectionDAG &DAG, 642 TargetLowering::DAGCombinerInfo &DCI, 643 const MipsSubtarget *Subtarget) { 644 // Pattern match INS. 645 // $dst = or (and $src1 , mask0), (and (shl $src, pos), mask1), 646 // where mask1 = (2**size - 1) << pos, mask0 = ~mask1 647 // => ins $dst, $src, size, pos, $src1 648 if (DCI.isBeforeLegalizeOps() || !Subtarget->hasExtractInsert()) 649 return SDValue(); 650 651 SDValue And0 = N->getOperand(0), And1 = N->getOperand(1); 652 uint64_t SMPos0, SMSize0, SMPos1, SMSize1; 653 ConstantSDNode *CN; 654 655 // See if Op's first operand matches (and $src1 , mask0). 656 if (And0.getOpcode() != ISD::AND) 657 return SDValue(); 658 659 if (!(CN = dyn_cast<ConstantSDNode>(And0.getOperand(1))) || 660 !isShiftedMask(~CN->getSExtValue(), SMPos0, SMSize0)) 661 return SDValue(); 662 663 // See if Op's second operand matches (and (shl $src, pos), mask1). 664 if (And1.getOpcode() != ISD::AND) 665 return SDValue(); 666 667 if (!(CN = dyn_cast<ConstantSDNode>(And1.getOperand(1))) || 668 !isShiftedMask(CN->getZExtValue(), SMPos1, SMSize1)) 669 return SDValue(); 670 671 // The shift masks must have the same position and size. 672 if (SMPos0 != SMPos1 || SMSize0 != SMSize1) 673 return SDValue(); 674 675 SDValue Shl = And1.getOperand(0); 676 if (Shl.getOpcode() != ISD::SHL) 677 return SDValue(); 678 679 if (!(CN = dyn_cast<ConstantSDNode>(Shl.getOperand(1)))) 680 return SDValue(); 681 682 unsigned Shamt = CN->getZExtValue(); 683 684 // Return if the shift amount and the first bit position of mask are not the 685 // same. 686 EVT ValTy = N->getValueType(0); 687 if ((Shamt != SMPos0) || (SMPos0 + SMSize0 > ValTy.getSizeInBits())) 688 return SDValue(); 689 690 return DAG.getNode(MipsISD::Ins, SDLoc(N), ValTy, Shl.getOperand(0), 691 DAG.getConstant(SMPos0, MVT::i32), 692 DAG.getConstant(SMSize0, MVT::i32), And0.getOperand(0)); 693 } 694 695 static SDValue performADDCombine(SDNode *N, SelectionDAG &DAG, 696 TargetLowering::DAGCombinerInfo &DCI, 697 const MipsSubtarget *Subtarget) { 698 // (add v0, (add v1, abs_lo(tjt))) => (add (add v0, v1), abs_lo(tjt)) 699 700 if (DCI.isBeforeLegalizeOps()) 701 return SDValue(); 702 703 SDValue Add = N->getOperand(1); 704 705 if (Add.getOpcode() != ISD::ADD) 706 return SDValue(); 707 708 SDValue Lo = Add.getOperand(1); 709 710 if ((Lo.getOpcode() != MipsISD::Lo) || 711 (Lo.getOperand(0).getOpcode() != ISD::TargetJumpTable)) 712 return SDValue(); 713 714 EVT ValTy = N->getValueType(0); 715 SDLoc DL(N); 716 717 SDValue Add1 = DAG.getNode(ISD::ADD, DL, ValTy, N->getOperand(0), 718 Add.getOperand(0)); 719 return DAG.getNode(ISD::ADD, DL, ValTy, Add1, Lo); 720 } 721 722 SDValue MipsTargetLowering::PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) 723 const { 724 SelectionDAG &DAG = DCI.DAG; 725 unsigned Opc = N->getOpcode(); 726 727 switch (Opc) { 728 default: break; 729 case ISD::SDIVREM: 730 case ISD::UDIVREM: 731 return performDivRemCombine(N, DAG, DCI, Subtarget); 732 case ISD::SELECT: 733 return performSELECTCombine(N, DAG, DCI, Subtarget); 734 case ISD::AND: 735 return performANDCombine(N, DAG, DCI, Subtarget); 736 case ISD::OR: 737 return performORCombine(N, DAG, DCI, Subtarget); 738 case ISD::ADD: 739 return performADDCombine(N, DAG, DCI, Subtarget); 740 } 741 742 return SDValue(); 743 } 744 745 void 746 MipsTargetLowering::LowerOperationWrapper(SDNode *N, 747 SmallVectorImpl<SDValue> &Results, 748 SelectionDAG &DAG) const { 749 SDValue Res = LowerOperation(SDValue(N, 0), DAG); 750 751 for (unsigned I = 0, E = Res->getNumValues(); I != E; ++I) 752 Results.push_back(Res.getValue(I)); 753 } 754 755 void 756 MipsTargetLowering::ReplaceNodeResults(SDNode *N, 757 SmallVectorImpl<SDValue> &Results, 758 SelectionDAG &DAG) const { 759 return LowerOperationWrapper(N, Results, DAG); 760 } 761 762 SDValue MipsTargetLowering:: 763 LowerOperation(SDValue Op, SelectionDAG &DAG) const 764 { 765 switch (Op.getOpcode()) 766 { 767 case ISD::BR_JT: return lowerBR_JT(Op, DAG); 768 case ISD::BRCOND: return lowerBRCOND(Op, DAG); 769 case ISD::ConstantPool: return lowerConstantPool(Op, DAG); 770 case ISD::GlobalAddress: return lowerGlobalAddress(Op, DAG); 771 case ISD::BlockAddress: return lowerBlockAddress(Op, DAG); 772 case ISD::GlobalTLSAddress: return lowerGlobalTLSAddress(Op, DAG); 773 case ISD::JumpTable: return lowerJumpTable(Op, DAG); 774 case ISD::SELECT: return lowerSELECT(Op, DAG); 775 case ISD::SELECT_CC: return lowerSELECT_CC(Op, DAG); 776 case ISD::SETCC: return lowerSETCC(Op, DAG); 777 case ISD::VASTART: return lowerVASTART(Op, DAG); 778 case ISD::FCOPYSIGN: return lowerFCOPYSIGN(Op, DAG); 779 case ISD::FABS: return lowerFABS(Op, DAG); 780 case ISD::FRAMEADDR: return lowerFRAMEADDR(Op, DAG); 781 case ISD::RETURNADDR: return lowerRETURNADDR(Op, DAG); 782 case ISD::EH_RETURN: return lowerEH_RETURN(Op, DAG); 783 case ISD::ATOMIC_FENCE: return lowerATOMIC_FENCE(Op, DAG); 784 case ISD::SHL_PARTS: return lowerShiftLeftParts(Op, DAG); 785 case ISD::SRA_PARTS: return lowerShiftRightParts(Op, DAG, true); 786 case ISD::SRL_PARTS: return lowerShiftRightParts(Op, DAG, false); 787 case ISD::LOAD: return lowerLOAD(Op, DAG); 788 case ISD::STORE: return lowerSTORE(Op, DAG); 789 case ISD::ADD: return lowerADD(Op, DAG); 790 case ISD::FP_TO_SINT: return lowerFP_TO_SINT(Op, DAG); 791 } 792 return SDValue(); 793 } 794 795 //===----------------------------------------------------------------------===// 796 // Lower helper functions 797 //===----------------------------------------------------------------------===// 798 799 // addLiveIn - This helper function adds the specified physical register to the 800 // MachineFunction as a live in value. It also creates a corresponding 801 // virtual register for it. 802 static unsigned 803 addLiveIn(MachineFunction &MF, unsigned PReg, const TargetRegisterClass *RC) 804 { 805 unsigned VReg = MF.getRegInfo().createVirtualRegister(RC); 806 MF.getRegInfo().addLiveIn(PReg, VReg); 807 return VReg; 808 } 809 810 static MachineBasicBlock *expandPseudoDIV(MachineInstr *MI, 811 MachineBasicBlock &MBB, 812 const TargetInstrInfo &TII, 813 bool Is64Bit) { 814 if (NoZeroDivCheck) 815 return &MBB; 816 817 // Insert instruction "teq $divisor_reg, $zero, 7". 818 MachineBasicBlock::iterator I(MI); 819 MachineInstrBuilder MIB; 820 MachineOperand &Divisor = MI->getOperand(2); 821 MIB = BuildMI(MBB, llvm::next(I), MI->getDebugLoc(), TII.get(Mips::TEQ)) 822 .addReg(Divisor.getReg(), getKillRegState(Divisor.isKill())) 823 .addReg(Mips::ZERO).addImm(7); 824 825 // Use the 32-bit sub-register if this is a 64-bit division. 826 if (Is64Bit) 827 MIB->getOperand(0).setSubReg(Mips::sub_32); 828 829 // Clear Divisor's kill flag. 830 Divisor.setIsKill(false); 831 return &MBB; 832 } 833 834 MachineBasicBlock * 835 MipsTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI, 836 MachineBasicBlock *BB) const { 837 switch (MI->getOpcode()) { 838 default: 839 llvm_unreachable("Unexpected instr type to insert"); 840 case Mips::ATOMIC_LOAD_ADD_I8: 841 return emitAtomicBinaryPartword(MI, BB, 1, Mips::ADDu); 842 case Mips::ATOMIC_LOAD_ADD_I16: 843 return emitAtomicBinaryPartword(MI, BB, 2, Mips::ADDu); 844 case Mips::ATOMIC_LOAD_ADD_I32: 845 return emitAtomicBinary(MI, BB, 4, Mips::ADDu); 846 case Mips::ATOMIC_LOAD_ADD_I64: 847 return emitAtomicBinary(MI, BB, 8, Mips::DADDu); 848 849 case Mips::ATOMIC_LOAD_AND_I8: 850 return emitAtomicBinaryPartword(MI, BB, 1, Mips::AND); 851 case Mips::ATOMIC_LOAD_AND_I16: 852 return emitAtomicBinaryPartword(MI, BB, 2, Mips::AND); 853 case Mips::ATOMIC_LOAD_AND_I32: 854 return emitAtomicBinary(MI, BB, 4, Mips::AND); 855 case Mips::ATOMIC_LOAD_AND_I64: 856 return emitAtomicBinary(MI, BB, 8, Mips::AND64); 857 858 case Mips::ATOMIC_LOAD_OR_I8: 859 return emitAtomicBinaryPartword(MI, BB, 1, Mips::OR); 860 case Mips::ATOMIC_LOAD_OR_I16: 861 return emitAtomicBinaryPartword(MI, BB, 2, Mips::OR); 862 case Mips::ATOMIC_LOAD_OR_I32: 863 return emitAtomicBinary(MI, BB, 4, Mips::OR); 864 case Mips::ATOMIC_LOAD_OR_I64: 865 return emitAtomicBinary(MI, BB, 8, Mips::OR64); 866 867 case Mips::ATOMIC_LOAD_XOR_I8: 868 return emitAtomicBinaryPartword(MI, BB, 1, Mips::XOR); 869 case Mips::ATOMIC_LOAD_XOR_I16: 870 return emitAtomicBinaryPartword(MI, BB, 2, Mips::XOR); 871 case Mips::ATOMIC_LOAD_XOR_I32: 872 return emitAtomicBinary(MI, BB, 4, Mips::XOR); 873 case Mips::ATOMIC_LOAD_XOR_I64: 874 return emitAtomicBinary(MI, BB, 8, Mips::XOR64); 875 876 case Mips::ATOMIC_LOAD_NAND_I8: 877 return emitAtomicBinaryPartword(MI, BB, 1, 0, true); 878 case Mips::ATOMIC_LOAD_NAND_I16: 879 return emitAtomicBinaryPartword(MI, BB, 2, 0, true); 880 case Mips::ATOMIC_LOAD_NAND_I32: 881 return emitAtomicBinary(MI, BB, 4, 0, true); 882 case Mips::ATOMIC_LOAD_NAND_I64: 883 return emitAtomicBinary(MI, BB, 8, 0, true); 884 885 case Mips::ATOMIC_LOAD_SUB_I8: 886 return emitAtomicBinaryPartword(MI, BB, 1, Mips::SUBu); 887 case Mips::ATOMIC_LOAD_SUB_I16: 888 return emitAtomicBinaryPartword(MI, BB, 2, Mips::SUBu); 889 case Mips::ATOMIC_LOAD_SUB_I32: 890 return emitAtomicBinary(MI, BB, 4, Mips::SUBu); 891 case Mips::ATOMIC_LOAD_SUB_I64: 892 return emitAtomicBinary(MI, BB, 8, Mips::DSUBu); 893 894 case Mips::ATOMIC_SWAP_I8: 895 return emitAtomicBinaryPartword(MI, BB, 1, 0); 896 case Mips::ATOMIC_SWAP_I16: 897 return emitAtomicBinaryPartword(MI, BB, 2, 0); 898 case Mips::ATOMIC_SWAP_I32: 899 return emitAtomicBinary(MI, BB, 4, 0); 900 case Mips::ATOMIC_SWAP_I64: 901 return emitAtomicBinary(MI, BB, 8, 0); 902 903 case Mips::ATOMIC_CMP_SWAP_I8: 904 return emitAtomicCmpSwapPartword(MI, BB, 1); 905 case Mips::ATOMIC_CMP_SWAP_I16: 906 return emitAtomicCmpSwapPartword(MI, BB, 2); 907 case Mips::ATOMIC_CMP_SWAP_I32: 908 return emitAtomicCmpSwap(MI, BB, 4); 909 case Mips::ATOMIC_CMP_SWAP_I64: 910 return emitAtomicCmpSwap(MI, BB, 8); 911 case Mips::PseudoSDIV: 912 case Mips::PseudoUDIV: 913 return expandPseudoDIV(MI, *BB, *getTargetMachine().getInstrInfo(), false); 914 case Mips::PseudoDSDIV: 915 case Mips::PseudoDUDIV: 916 return expandPseudoDIV(MI, *BB, *getTargetMachine().getInstrInfo(), true); 917 } 918 } 919 920 // This function also handles Mips::ATOMIC_SWAP_I32 (when BinOpcode == 0), and 921 // Mips::ATOMIC_LOAD_NAND_I32 (when Nand == true) 922 MachineBasicBlock * 923 MipsTargetLowering::emitAtomicBinary(MachineInstr *MI, MachineBasicBlock *BB, 924 unsigned Size, unsigned BinOpcode, 925 bool Nand) const { 926 assert((Size == 4 || Size == 8) && "Unsupported size for EmitAtomicBinary."); 927 928 MachineFunction *MF = BB->getParent(); 929 MachineRegisterInfo &RegInfo = MF->getRegInfo(); 930 const TargetRegisterClass *RC = getRegClassFor(MVT::getIntegerVT(Size * 8)); 931 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 932 DebugLoc DL = MI->getDebugLoc(); 933 unsigned LL, SC, AND, NOR, ZERO, BEQ; 934 935 if (Size == 4) { 936 LL = isMicroMips ? Mips::LL_MM : Mips::LL; 937 SC = isMicroMips ? Mips::SC_MM : Mips::SC; 938 AND = Mips::AND; 939 NOR = Mips::NOR; 940 ZERO = Mips::ZERO; 941 BEQ = Mips::BEQ; 942 } 943 else { 944 LL = Mips::LLD; 945 SC = Mips::SCD; 946 AND = Mips::AND64; 947 NOR = Mips::NOR64; 948 ZERO = Mips::ZERO_64; 949 BEQ = Mips::BEQ64; 950 } 951 952 unsigned OldVal = MI->getOperand(0).getReg(); 953 unsigned Ptr = MI->getOperand(1).getReg(); 954 unsigned Incr = MI->getOperand(2).getReg(); 955 956 unsigned StoreVal = RegInfo.createVirtualRegister(RC); 957 unsigned AndRes = RegInfo.createVirtualRegister(RC); 958 unsigned Success = RegInfo.createVirtualRegister(RC); 959 960 // insert new blocks after the current block 961 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 962 MachineBasicBlock *loopMBB = MF->CreateMachineBasicBlock(LLVM_BB); 963 MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB); 964 MachineFunction::iterator It = BB; 965 ++It; 966 MF->insert(It, loopMBB); 967 MF->insert(It, exitMBB); 968 969 // Transfer the remainder of BB and its successor edges to exitMBB. 970 exitMBB->splice(exitMBB->begin(), BB, 971 llvm::next(MachineBasicBlock::iterator(MI)), BB->end()); 972 exitMBB->transferSuccessorsAndUpdatePHIs(BB); 973 974 // thisMBB: 975 // ... 976 // fallthrough --> loopMBB 977 BB->addSuccessor(loopMBB); 978 loopMBB->addSuccessor(loopMBB); 979 loopMBB->addSuccessor(exitMBB); 980 981 // loopMBB: 982 // ll oldval, 0(ptr) 983 // <binop> storeval, oldval, incr 984 // sc success, storeval, 0(ptr) 985 // beq success, $0, loopMBB 986 BB = loopMBB; 987 BuildMI(BB, DL, TII->get(LL), OldVal).addReg(Ptr).addImm(0); 988 if (Nand) { 989 // and andres, oldval, incr 990 // nor storeval, $0, andres 991 BuildMI(BB, DL, TII->get(AND), AndRes).addReg(OldVal).addReg(Incr); 992 BuildMI(BB, DL, TII->get(NOR), StoreVal).addReg(ZERO).addReg(AndRes); 993 } else if (BinOpcode) { 994 // <binop> storeval, oldval, incr 995 BuildMI(BB, DL, TII->get(BinOpcode), StoreVal).addReg(OldVal).addReg(Incr); 996 } else { 997 StoreVal = Incr; 998 } 999 BuildMI(BB, DL, TII->get(SC), Success).addReg(StoreVal).addReg(Ptr).addImm(0); 1000 BuildMI(BB, DL, TII->get(BEQ)).addReg(Success).addReg(ZERO).addMBB(loopMBB); 1001 1002 MI->eraseFromParent(); // The instruction is gone now. 1003 1004 return exitMBB; 1005 } 1006 1007 MachineBasicBlock * 1008 MipsTargetLowering::emitAtomicBinaryPartword(MachineInstr *MI, 1009 MachineBasicBlock *BB, 1010 unsigned Size, unsigned BinOpcode, 1011 bool Nand) const { 1012 assert((Size == 1 || Size == 2) && 1013 "Unsupported size for EmitAtomicBinaryPartial."); 1014 1015 MachineFunction *MF = BB->getParent(); 1016 MachineRegisterInfo &RegInfo = MF->getRegInfo(); 1017 const TargetRegisterClass *RC = getRegClassFor(MVT::i32); 1018 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 1019 DebugLoc DL = MI->getDebugLoc(); 1020 1021 unsigned Dest = MI->getOperand(0).getReg(); 1022 unsigned Ptr = MI->getOperand(1).getReg(); 1023 unsigned Incr = MI->getOperand(2).getReg(); 1024 1025 unsigned AlignedAddr = RegInfo.createVirtualRegister(RC); 1026 unsigned ShiftAmt = RegInfo.createVirtualRegister(RC); 1027 unsigned Mask = RegInfo.createVirtualRegister(RC); 1028 unsigned Mask2 = RegInfo.createVirtualRegister(RC); 1029 unsigned NewVal = RegInfo.createVirtualRegister(RC); 1030 unsigned OldVal = RegInfo.createVirtualRegister(RC); 1031 unsigned Incr2 = RegInfo.createVirtualRegister(RC); 1032 unsigned MaskLSB2 = RegInfo.createVirtualRegister(RC); 1033 unsigned PtrLSB2 = RegInfo.createVirtualRegister(RC); 1034 unsigned MaskUpper = RegInfo.createVirtualRegister(RC); 1035 unsigned AndRes = RegInfo.createVirtualRegister(RC); 1036 unsigned BinOpRes = RegInfo.createVirtualRegister(RC); 1037 unsigned MaskedOldVal0 = RegInfo.createVirtualRegister(RC); 1038 unsigned StoreVal = RegInfo.createVirtualRegister(RC); 1039 unsigned MaskedOldVal1 = RegInfo.createVirtualRegister(RC); 1040 unsigned SrlRes = RegInfo.createVirtualRegister(RC); 1041 unsigned SllRes = RegInfo.createVirtualRegister(RC); 1042 unsigned Success = RegInfo.createVirtualRegister(RC); 1043 1044 // insert new blocks after the current block 1045 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 1046 MachineBasicBlock *loopMBB = MF->CreateMachineBasicBlock(LLVM_BB); 1047 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(LLVM_BB); 1048 MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB); 1049 MachineFunction::iterator It = BB; 1050 ++It; 1051 MF->insert(It, loopMBB); 1052 MF->insert(It, sinkMBB); 1053 MF->insert(It, exitMBB); 1054 1055 // Transfer the remainder of BB and its successor edges to exitMBB. 1056 exitMBB->splice(exitMBB->begin(), BB, 1057 llvm::next(MachineBasicBlock::iterator(MI)), BB->end()); 1058 exitMBB->transferSuccessorsAndUpdatePHIs(BB); 1059 1060 BB->addSuccessor(loopMBB); 1061 loopMBB->addSuccessor(loopMBB); 1062 loopMBB->addSuccessor(sinkMBB); 1063 sinkMBB->addSuccessor(exitMBB); 1064 1065 // thisMBB: 1066 // addiu masklsb2,$0,-4 # 0xfffffffc 1067 // and alignedaddr,ptr,masklsb2 1068 // andi ptrlsb2,ptr,3 1069 // sll shiftamt,ptrlsb2,3 1070 // ori maskupper,$0,255 # 0xff 1071 // sll mask,maskupper,shiftamt 1072 // nor mask2,$0,mask 1073 // sll incr2,incr,shiftamt 1074 1075 int64_t MaskImm = (Size == 1) ? 255 : 65535; 1076 BuildMI(BB, DL, TII->get(Mips::ADDiu), MaskLSB2) 1077 .addReg(Mips::ZERO).addImm(-4); 1078 BuildMI(BB, DL, TII->get(Mips::AND), AlignedAddr) 1079 .addReg(Ptr).addReg(MaskLSB2); 1080 BuildMI(BB, DL, TII->get(Mips::ANDi), PtrLSB2).addReg(Ptr).addImm(3); 1081 if (Subtarget->isLittle()) { 1082 BuildMI(BB, DL, TII->get(Mips::SLL), ShiftAmt).addReg(PtrLSB2).addImm(3); 1083 } else { 1084 unsigned Off = RegInfo.createVirtualRegister(RC); 1085 BuildMI(BB, DL, TII->get(Mips::XORi), Off) 1086 .addReg(PtrLSB2).addImm((Size == 1) ? 3 : 2); 1087 BuildMI(BB, DL, TII->get(Mips::SLL), ShiftAmt).addReg(Off).addImm(3); 1088 } 1089 BuildMI(BB, DL, TII->get(Mips::ORi), MaskUpper) 1090 .addReg(Mips::ZERO).addImm(MaskImm); 1091 BuildMI(BB, DL, TII->get(Mips::SLLV), Mask) 1092 .addReg(MaskUpper).addReg(ShiftAmt); 1093 BuildMI(BB, DL, TII->get(Mips::NOR), Mask2).addReg(Mips::ZERO).addReg(Mask); 1094 BuildMI(BB, DL, TII->get(Mips::SLLV), Incr2).addReg(Incr).addReg(ShiftAmt); 1095 1096 // atomic.load.binop 1097 // loopMBB: 1098 // ll oldval,0(alignedaddr) 1099 // binop binopres,oldval,incr2 1100 // and newval,binopres,mask 1101 // and maskedoldval0,oldval,mask2 1102 // or storeval,maskedoldval0,newval 1103 // sc success,storeval,0(alignedaddr) 1104 // beq success,$0,loopMBB 1105 1106 // atomic.swap 1107 // loopMBB: 1108 // ll oldval,0(alignedaddr) 1109 // and newval,incr2,mask 1110 // and maskedoldval0,oldval,mask2 1111 // or storeval,maskedoldval0,newval 1112 // sc success,storeval,0(alignedaddr) 1113 // beq success,$0,loopMBB 1114 1115 BB = loopMBB; 1116 BuildMI(BB, DL, TII->get(Mips::LL), OldVal).addReg(AlignedAddr).addImm(0); 1117 if (Nand) { 1118 // and andres, oldval, incr2 1119 // nor binopres, $0, andres 1120 // and newval, binopres, mask 1121 BuildMI(BB, DL, TII->get(Mips::AND), AndRes).addReg(OldVal).addReg(Incr2); 1122 BuildMI(BB, DL, TII->get(Mips::NOR), BinOpRes) 1123 .addReg(Mips::ZERO).addReg(AndRes); 1124 BuildMI(BB, DL, TII->get(Mips::AND), NewVal).addReg(BinOpRes).addReg(Mask); 1125 } else if (BinOpcode) { 1126 // <binop> binopres, oldval, incr2 1127 // and newval, binopres, mask 1128 BuildMI(BB, DL, TII->get(BinOpcode), BinOpRes).addReg(OldVal).addReg(Incr2); 1129 BuildMI(BB, DL, TII->get(Mips::AND), NewVal).addReg(BinOpRes).addReg(Mask); 1130 } else { // atomic.swap 1131 // and newval, incr2, mask 1132 BuildMI(BB, DL, TII->get(Mips::AND), NewVal).addReg(Incr2).addReg(Mask); 1133 } 1134 1135 BuildMI(BB, DL, TII->get(Mips::AND), MaskedOldVal0) 1136 .addReg(OldVal).addReg(Mask2); 1137 BuildMI(BB, DL, TII->get(Mips::OR), StoreVal) 1138 .addReg(MaskedOldVal0).addReg(NewVal); 1139 BuildMI(BB, DL, TII->get(Mips::SC), Success) 1140 .addReg(StoreVal).addReg(AlignedAddr).addImm(0); 1141 BuildMI(BB, DL, TII->get(Mips::BEQ)) 1142 .addReg(Success).addReg(Mips::ZERO).addMBB(loopMBB); 1143 1144 // sinkMBB: 1145 // and maskedoldval1,oldval,mask 1146 // srl srlres,maskedoldval1,shiftamt 1147 // sll sllres,srlres,24 1148 // sra dest,sllres,24 1149 BB = sinkMBB; 1150 int64_t ShiftImm = (Size == 1) ? 24 : 16; 1151 1152 BuildMI(BB, DL, TII->get(Mips::AND), MaskedOldVal1) 1153 .addReg(OldVal).addReg(Mask); 1154 BuildMI(BB, DL, TII->get(Mips::SRLV), SrlRes) 1155 .addReg(MaskedOldVal1).addReg(ShiftAmt); 1156 BuildMI(BB, DL, TII->get(Mips::SLL), SllRes) 1157 .addReg(SrlRes).addImm(ShiftImm); 1158 BuildMI(BB, DL, TII->get(Mips::SRA), Dest) 1159 .addReg(SllRes).addImm(ShiftImm); 1160 1161 MI->eraseFromParent(); // The instruction is gone now. 1162 1163 return exitMBB; 1164 } 1165 1166 MachineBasicBlock * MipsTargetLowering::emitAtomicCmpSwap(MachineInstr *MI, 1167 MachineBasicBlock *BB, 1168 unsigned Size) const { 1169 assert((Size == 4 || Size == 8) && "Unsupported size for EmitAtomicCmpSwap."); 1170 1171 MachineFunction *MF = BB->getParent(); 1172 MachineRegisterInfo &RegInfo = MF->getRegInfo(); 1173 const TargetRegisterClass *RC = getRegClassFor(MVT::getIntegerVT(Size * 8)); 1174 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 1175 DebugLoc DL = MI->getDebugLoc(); 1176 unsigned LL, SC, ZERO, BNE, BEQ; 1177 1178 if (Size == 4) { 1179 LL = isMicroMips ? Mips::LL_MM : Mips::LL; 1180 SC = isMicroMips ? Mips::SC_MM : Mips::SC; 1181 ZERO = Mips::ZERO; 1182 BNE = Mips::BNE; 1183 BEQ = Mips::BEQ; 1184 } else { 1185 LL = Mips::LLD; 1186 SC = Mips::SCD; 1187 ZERO = Mips::ZERO_64; 1188 BNE = Mips::BNE64; 1189 BEQ = Mips::BEQ64; 1190 } 1191 1192 unsigned Dest = MI->getOperand(0).getReg(); 1193 unsigned Ptr = MI->getOperand(1).getReg(); 1194 unsigned OldVal = MI->getOperand(2).getReg(); 1195 unsigned NewVal = MI->getOperand(3).getReg(); 1196 1197 unsigned Success = RegInfo.createVirtualRegister(RC); 1198 1199 // insert new blocks after the current block 1200 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 1201 MachineBasicBlock *loop1MBB = MF->CreateMachineBasicBlock(LLVM_BB); 1202 MachineBasicBlock *loop2MBB = MF->CreateMachineBasicBlock(LLVM_BB); 1203 MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB); 1204 MachineFunction::iterator It = BB; 1205 ++It; 1206 MF->insert(It, loop1MBB); 1207 MF->insert(It, loop2MBB); 1208 MF->insert(It, exitMBB); 1209 1210 // Transfer the remainder of BB and its successor edges to exitMBB. 1211 exitMBB->splice(exitMBB->begin(), BB, 1212 llvm::next(MachineBasicBlock::iterator(MI)), BB->end()); 1213 exitMBB->transferSuccessorsAndUpdatePHIs(BB); 1214 1215 // thisMBB: 1216 // ... 1217 // fallthrough --> loop1MBB 1218 BB->addSuccessor(loop1MBB); 1219 loop1MBB->addSuccessor(exitMBB); 1220 loop1MBB->addSuccessor(loop2MBB); 1221 loop2MBB->addSuccessor(loop1MBB); 1222 loop2MBB->addSuccessor(exitMBB); 1223 1224 // loop1MBB: 1225 // ll dest, 0(ptr) 1226 // bne dest, oldval, exitMBB 1227 BB = loop1MBB; 1228 BuildMI(BB, DL, TII->get(LL), Dest).addReg(Ptr).addImm(0); 1229 BuildMI(BB, DL, TII->get(BNE)) 1230 .addReg(Dest).addReg(OldVal).addMBB(exitMBB); 1231 1232 // loop2MBB: 1233 // sc success, newval, 0(ptr) 1234 // beq success, $0, loop1MBB 1235 BB = loop2MBB; 1236 BuildMI(BB, DL, TII->get(SC), Success) 1237 .addReg(NewVal).addReg(Ptr).addImm(0); 1238 BuildMI(BB, DL, TII->get(BEQ)) 1239 .addReg(Success).addReg(ZERO).addMBB(loop1MBB); 1240 1241 MI->eraseFromParent(); // The instruction is gone now. 1242 1243 return exitMBB; 1244 } 1245 1246 MachineBasicBlock * 1247 MipsTargetLowering::emitAtomicCmpSwapPartword(MachineInstr *MI, 1248 MachineBasicBlock *BB, 1249 unsigned Size) const { 1250 assert((Size == 1 || Size == 2) && 1251 "Unsupported size for EmitAtomicCmpSwapPartial."); 1252 1253 MachineFunction *MF = BB->getParent(); 1254 MachineRegisterInfo &RegInfo = MF->getRegInfo(); 1255 const TargetRegisterClass *RC = getRegClassFor(MVT::i32); 1256 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 1257 DebugLoc DL = MI->getDebugLoc(); 1258 1259 unsigned Dest = MI->getOperand(0).getReg(); 1260 unsigned Ptr = MI->getOperand(1).getReg(); 1261 unsigned CmpVal = MI->getOperand(2).getReg(); 1262 unsigned NewVal = MI->getOperand(3).getReg(); 1263 1264 unsigned AlignedAddr = RegInfo.createVirtualRegister(RC); 1265 unsigned ShiftAmt = RegInfo.createVirtualRegister(RC); 1266 unsigned Mask = RegInfo.createVirtualRegister(RC); 1267 unsigned Mask2 = RegInfo.createVirtualRegister(RC); 1268 unsigned ShiftedCmpVal = RegInfo.createVirtualRegister(RC); 1269 unsigned OldVal = RegInfo.createVirtualRegister(RC); 1270 unsigned MaskedOldVal0 = RegInfo.createVirtualRegister(RC); 1271 unsigned ShiftedNewVal = RegInfo.createVirtualRegister(RC); 1272 unsigned MaskLSB2 = RegInfo.createVirtualRegister(RC); 1273 unsigned PtrLSB2 = RegInfo.createVirtualRegister(RC); 1274 unsigned MaskUpper = RegInfo.createVirtualRegister(RC); 1275 unsigned MaskedCmpVal = RegInfo.createVirtualRegister(RC); 1276 unsigned MaskedNewVal = RegInfo.createVirtualRegister(RC); 1277 unsigned MaskedOldVal1 = RegInfo.createVirtualRegister(RC); 1278 unsigned StoreVal = RegInfo.createVirtualRegister(RC); 1279 unsigned SrlRes = RegInfo.createVirtualRegister(RC); 1280 unsigned SllRes = RegInfo.createVirtualRegister(RC); 1281 unsigned Success = RegInfo.createVirtualRegister(RC); 1282 1283 // insert new blocks after the current block 1284 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 1285 MachineBasicBlock *loop1MBB = MF->CreateMachineBasicBlock(LLVM_BB); 1286 MachineBasicBlock *loop2MBB = MF->CreateMachineBasicBlock(LLVM_BB); 1287 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(LLVM_BB); 1288 MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB); 1289 MachineFunction::iterator It = BB; 1290 ++It; 1291 MF->insert(It, loop1MBB); 1292 MF->insert(It, loop2MBB); 1293 MF->insert(It, sinkMBB); 1294 MF->insert(It, exitMBB); 1295 1296 // Transfer the remainder of BB and its successor edges to exitMBB. 1297 exitMBB->splice(exitMBB->begin(), BB, 1298 llvm::next(MachineBasicBlock::iterator(MI)), BB->end()); 1299 exitMBB->transferSuccessorsAndUpdatePHIs(BB); 1300 1301 BB->addSuccessor(loop1MBB); 1302 loop1MBB->addSuccessor(sinkMBB); 1303 loop1MBB->addSuccessor(loop2MBB); 1304 loop2MBB->addSuccessor(loop1MBB); 1305 loop2MBB->addSuccessor(sinkMBB); 1306 sinkMBB->addSuccessor(exitMBB); 1307 1308 // FIXME: computation of newval2 can be moved to loop2MBB. 1309 // thisMBB: 1310 // addiu masklsb2,$0,-4 # 0xfffffffc 1311 // and alignedaddr,ptr,masklsb2 1312 // andi ptrlsb2,ptr,3 1313 // sll shiftamt,ptrlsb2,3 1314 // ori maskupper,$0,255 # 0xff 1315 // sll mask,maskupper,shiftamt 1316 // nor mask2,$0,mask 1317 // andi maskedcmpval,cmpval,255 1318 // sll shiftedcmpval,maskedcmpval,shiftamt 1319 // andi maskednewval,newval,255 1320 // sll shiftednewval,maskednewval,shiftamt 1321 int64_t MaskImm = (Size == 1) ? 255 : 65535; 1322 BuildMI(BB, DL, TII->get(Mips::ADDiu), MaskLSB2) 1323 .addReg(Mips::ZERO).addImm(-4); 1324 BuildMI(BB, DL, TII->get(Mips::AND), AlignedAddr) 1325 .addReg(Ptr).addReg(MaskLSB2); 1326 BuildMI(BB, DL, TII->get(Mips::ANDi), PtrLSB2).addReg(Ptr).addImm(3); 1327 if (Subtarget->isLittle()) { 1328 BuildMI(BB, DL, TII->get(Mips::SLL), ShiftAmt).addReg(PtrLSB2).addImm(3); 1329 } else { 1330 unsigned Off = RegInfo.createVirtualRegister(RC); 1331 BuildMI(BB, DL, TII->get(Mips::XORi), Off) 1332 .addReg(PtrLSB2).addImm((Size == 1) ? 3 : 2); 1333 BuildMI(BB, DL, TII->get(Mips::SLL), ShiftAmt).addReg(Off).addImm(3); 1334 } 1335 BuildMI(BB, DL, TII->get(Mips::ORi), MaskUpper) 1336 .addReg(Mips::ZERO).addImm(MaskImm); 1337 BuildMI(BB, DL, TII->get(Mips::SLLV), Mask) 1338 .addReg(MaskUpper).addReg(ShiftAmt); 1339 BuildMI(BB, DL, TII->get(Mips::NOR), Mask2).addReg(Mips::ZERO).addReg(Mask); 1340 BuildMI(BB, DL, TII->get(Mips::ANDi), MaskedCmpVal) 1341 .addReg(CmpVal).addImm(MaskImm); 1342 BuildMI(BB, DL, TII->get(Mips::SLLV), ShiftedCmpVal) 1343 .addReg(MaskedCmpVal).addReg(ShiftAmt); 1344 BuildMI(BB, DL, TII->get(Mips::ANDi), MaskedNewVal) 1345 .addReg(NewVal).addImm(MaskImm); 1346 BuildMI(BB, DL, TII->get(Mips::SLLV), ShiftedNewVal) 1347 .addReg(MaskedNewVal).addReg(ShiftAmt); 1348 1349 // loop1MBB: 1350 // ll oldval,0(alginedaddr) 1351 // and maskedoldval0,oldval,mask 1352 // bne maskedoldval0,shiftedcmpval,sinkMBB 1353 BB = loop1MBB; 1354 BuildMI(BB, DL, TII->get(Mips::LL), OldVal).addReg(AlignedAddr).addImm(0); 1355 BuildMI(BB, DL, TII->get(Mips::AND), MaskedOldVal0) 1356 .addReg(OldVal).addReg(Mask); 1357 BuildMI(BB, DL, TII->get(Mips::BNE)) 1358 .addReg(MaskedOldVal0).addReg(ShiftedCmpVal).addMBB(sinkMBB); 1359 1360 // loop2MBB: 1361 // and maskedoldval1,oldval,mask2 1362 // or storeval,maskedoldval1,shiftednewval 1363 // sc success,storeval,0(alignedaddr) 1364 // beq success,$0,loop1MBB 1365 BB = loop2MBB; 1366 BuildMI(BB, DL, TII->get(Mips::AND), MaskedOldVal1) 1367 .addReg(OldVal).addReg(Mask2); 1368 BuildMI(BB, DL, TII->get(Mips::OR), StoreVal) 1369 .addReg(MaskedOldVal1).addReg(ShiftedNewVal); 1370 BuildMI(BB, DL, TII->get(Mips::SC), Success) 1371 .addReg(StoreVal).addReg(AlignedAddr).addImm(0); 1372 BuildMI(BB, DL, TII->get(Mips::BEQ)) 1373 .addReg(Success).addReg(Mips::ZERO).addMBB(loop1MBB); 1374 1375 // sinkMBB: 1376 // srl srlres,maskedoldval0,shiftamt 1377 // sll sllres,srlres,24 1378 // sra dest,sllres,24 1379 BB = sinkMBB; 1380 int64_t ShiftImm = (Size == 1) ? 24 : 16; 1381 1382 BuildMI(BB, DL, TII->get(Mips::SRLV), SrlRes) 1383 .addReg(MaskedOldVal0).addReg(ShiftAmt); 1384 BuildMI(BB, DL, TII->get(Mips::SLL), SllRes) 1385 .addReg(SrlRes).addImm(ShiftImm); 1386 BuildMI(BB, DL, TII->get(Mips::SRA), Dest) 1387 .addReg(SllRes).addImm(ShiftImm); 1388 1389 MI->eraseFromParent(); // The instruction is gone now. 1390 1391 return exitMBB; 1392 } 1393 1394 //===----------------------------------------------------------------------===// 1395 // Misc Lower Operation implementation 1396 //===----------------------------------------------------------------------===// 1397 SDValue MipsTargetLowering::lowerBR_JT(SDValue Op, SelectionDAG &DAG) const { 1398 SDValue Chain = Op.getOperand(0); 1399 SDValue Table = Op.getOperand(1); 1400 SDValue Index = Op.getOperand(2); 1401 SDLoc DL(Op); 1402 EVT PTy = getPointerTy(); 1403 unsigned EntrySize = 1404 DAG.getMachineFunction().getJumpTableInfo()->getEntrySize(*getDataLayout()); 1405 1406 Index = DAG.getNode(ISD::MUL, DL, PTy, Index, 1407 DAG.getConstant(EntrySize, PTy)); 1408 SDValue Addr = DAG.getNode(ISD::ADD, DL, PTy, Index, Table); 1409 1410 EVT MemVT = EVT::getIntegerVT(*DAG.getContext(), EntrySize * 8); 1411 Addr = DAG.getExtLoad(ISD::SEXTLOAD, DL, PTy, Chain, Addr, 1412 MachinePointerInfo::getJumpTable(), MemVT, false, false, 1413 0); 1414 Chain = Addr.getValue(1); 1415 1416 if ((getTargetMachine().getRelocationModel() == Reloc::PIC_) || IsN64) { 1417 // For PIC, the sequence is: 1418 // BRIND(load(Jumptable + index) + RelocBase) 1419 // RelocBase can be JumpTable, GOT or some sort of global base. 1420 Addr = DAG.getNode(ISD::ADD, DL, PTy, Addr, 1421 getPICJumpTableRelocBase(Table, DAG)); 1422 } 1423 1424 return DAG.getNode(ISD::BRIND, DL, MVT::Other, Chain, Addr); 1425 } 1426 1427 SDValue MipsTargetLowering::lowerBRCOND(SDValue Op, SelectionDAG &DAG) const { 1428 // The first operand is the chain, the second is the condition, the third is 1429 // the block to branch to if the condition is true. 1430 SDValue Chain = Op.getOperand(0); 1431 SDValue Dest = Op.getOperand(2); 1432 SDLoc DL(Op); 1433 1434 SDValue CondRes = createFPCmp(DAG, Op.getOperand(1)); 1435 1436 // Return if flag is not set by a floating point comparison. 1437 if (CondRes.getOpcode() != MipsISD::FPCmp) 1438 return Op; 1439 1440 SDValue CCNode = CondRes.getOperand(2); 1441 Mips::CondCode CC = 1442 (Mips::CondCode)cast<ConstantSDNode>(CCNode)->getZExtValue(); 1443 unsigned Opc = invertFPCondCodeUser(CC) ? Mips::BRANCH_F : Mips::BRANCH_T; 1444 SDValue BrCode = DAG.getConstant(Opc, MVT::i32); 1445 SDValue FCC0 = DAG.getRegister(Mips::FCC0, MVT::i32); 1446 return DAG.getNode(MipsISD::FPBrcond, DL, Op.getValueType(), Chain, BrCode, 1447 FCC0, Dest, CondRes); 1448 } 1449 1450 SDValue MipsTargetLowering:: 1451 lowerSELECT(SDValue Op, SelectionDAG &DAG) const 1452 { 1453 SDValue Cond = createFPCmp(DAG, Op.getOperand(0)); 1454 1455 // Return if flag is not set by a floating point comparison. 1456 if (Cond.getOpcode() != MipsISD::FPCmp) 1457 return Op; 1458 1459 return createCMovFP(DAG, Cond, Op.getOperand(1), Op.getOperand(2), 1460 SDLoc(Op)); 1461 } 1462 1463 SDValue MipsTargetLowering:: 1464 lowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const 1465 { 1466 SDLoc DL(Op); 1467 EVT Ty = Op.getOperand(0).getValueType(); 1468 SDValue Cond = DAG.getNode(ISD::SETCC, DL, 1469 getSetCCResultType(*DAG.getContext(), Ty), 1470 Op.getOperand(0), Op.getOperand(1), 1471 Op.getOperand(4)); 1472 1473 return DAG.getNode(ISD::SELECT, DL, Op.getValueType(), Cond, Op.getOperand(2), 1474 Op.getOperand(3)); 1475 } 1476 1477 SDValue MipsTargetLowering::lowerSETCC(SDValue Op, SelectionDAG &DAG) const { 1478 SDValue Cond = createFPCmp(DAG, Op); 1479 1480 assert(Cond.getOpcode() == MipsISD::FPCmp && 1481 "Floating point operand expected."); 1482 1483 SDValue True = DAG.getConstant(1, MVT::i32); 1484 SDValue False = DAG.getConstant(0, MVT::i32); 1485 1486 return createCMovFP(DAG, Cond, True, False, SDLoc(Op)); 1487 } 1488 1489 SDValue MipsTargetLowering::lowerGlobalAddress(SDValue Op, 1490 SelectionDAG &DAG) const { 1491 // FIXME there isn't actually debug info here 1492 SDLoc DL(Op); 1493 EVT Ty = Op.getValueType(); 1494 GlobalAddressSDNode *N = cast<GlobalAddressSDNode>(Op); 1495 const GlobalValue *GV = N->getGlobal(); 1496 1497 if (getTargetMachine().getRelocationModel() != Reloc::PIC_ && !IsN64) { 1498 const MipsTargetObjectFile &TLOF = 1499 (const MipsTargetObjectFile&)getObjFileLowering(); 1500 1501 // %gp_rel relocation 1502 if (TLOF.IsGlobalInSmallSection(GV, getTargetMachine())) { 1503 SDValue GA = DAG.getTargetGlobalAddress(GV, DL, MVT::i32, 0, 1504 MipsII::MO_GPREL); 1505 SDValue GPRelNode = DAG.getNode(MipsISD::GPRel, DL, 1506 DAG.getVTList(MVT::i32), &GA, 1); 1507 SDValue GPReg = DAG.getRegister(Mips::GP, MVT::i32); 1508 return DAG.getNode(ISD::ADD, DL, MVT::i32, GPReg, GPRelNode); 1509 } 1510 1511 // %hi/%lo relocation 1512 return getAddrNonPIC(N, Ty, DAG); 1513 } 1514 1515 if (GV->hasInternalLinkage() || (GV->hasLocalLinkage() && !isa<Function>(GV))) 1516 return getAddrLocal(N, Ty, DAG, HasMips64); 1517 1518 if (LargeGOT) 1519 return getAddrGlobalLargeGOT(N, Ty, DAG, MipsII::MO_GOT_HI16, 1520 MipsII::MO_GOT_LO16, DAG.getEntryNode(), 1521 MachinePointerInfo::getGOT()); 1522 1523 return getAddrGlobal(N, Ty, DAG, 1524 HasMips64 ? MipsII::MO_GOT_DISP : MipsII::MO_GOT16, 1525 DAG.getEntryNode(), MachinePointerInfo::getGOT()); 1526 } 1527 1528 SDValue MipsTargetLowering::lowerBlockAddress(SDValue Op, 1529 SelectionDAG &DAG) const { 1530 BlockAddressSDNode *N = cast<BlockAddressSDNode>(Op); 1531 EVT Ty = Op.getValueType(); 1532 1533 if (getTargetMachine().getRelocationModel() != Reloc::PIC_ && !IsN64) 1534 return getAddrNonPIC(N, Ty, DAG); 1535 1536 return getAddrLocal(N, Ty, DAG, HasMips64); 1537 } 1538 1539 SDValue MipsTargetLowering:: 1540 lowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const 1541 { 1542 // If the relocation model is PIC, use the General Dynamic TLS Model or 1543 // Local Dynamic TLS model, otherwise use the Initial Exec or 1544 // Local Exec TLS Model. 1545 1546 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op); 1547 SDLoc DL(GA); 1548 const GlobalValue *GV = GA->getGlobal(); 1549 EVT PtrVT = getPointerTy(); 1550 1551 TLSModel::Model model = getTargetMachine().getTLSModel(GV); 1552 1553 if (model == TLSModel::GeneralDynamic || model == TLSModel::LocalDynamic) { 1554 // General Dynamic and Local Dynamic TLS Model. 1555 unsigned Flag = (model == TLSModel::LocalDynamic) ? MipsII::MO_TLSLDM 1556 : MipsII::MO_TLSGD; 1557 1558 SDValue TGA = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, Flag); 1559 SDValue Argument = DAG.getNode(MipsISD::Wrapper, DL, PtrVT, 1560 getGlobalReg(DAG, PtrVT), TGA); 1561 unsigned PtrSize = PtrVT.getSizeInBits(); 1562 IntegerType *PtrTy = Type::getIntNTy(*DAG.getContext(), PtrSize); 1563 1564 SDValue TlsGetAddr = DAG.getExternalSymbol("__tls_get_addr", PtrVT); 1565 1566 ArgListTy Args; 1567 ArgListEntry Entry; 1568 Entry.Node = Argument; 1569 Entry.Ty = PtrTy; 1570 Args.push_back(Entry); 1571 1572 TargetLowering::CallLoweringInfo CLI(DAG.getEntryNode(), PtrTy, 1573 false, false, false, false, 0, CallingConv::C, 1574 /*IsTailCall=*/false, /*doesNotRet=*/false, 1575 /*isReturnValueUsed=*/true, 1576 TlsGetAddr, Args, DAG, DL); 1577 std::pair<SDValue, SDValue> CallResult = LowerCallTo(CLI); 1578 1579 SDValue Ret = CallResult.first; 1580 1581 if (model != TLSModel::LocalDynamic) 1582 return Ret; 1583 1584 SDValue TGAHi = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, 1585 MipsII::MO_DTPREL_HI); 1586 SDValue Hi = DAG.getNode(MipsISD::Hi, DL, PtrVT, TGAHi); 1587 SDValue TGALo = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, 1588 MipsII::MO_DTPREL_LO); 1589 SDValue Lo = DAG.getNode(MipsISD::Lo, DL, PtrVT, TGALo); 1590 SDValue Add = DAG.getNode(ISD::ADD, DL, PtrVT, Hi, Ret); 1591 return DAG.getNode(ISD::ADD, DL, PtrVT, Add, Lo); 1592 } 1593 1594 SDValue Offset; 1595 if (model == TLSModel::InitialExec) { 1596 // Initial Exec TLS Model 1597 SDValue TGA = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, 1598 MipsII::MO_GOTTPREL); 1599 TGA = DAG.getNode(MipsISD::Wrapper, DL, PtrVT, getGlobalReg(DAG, PtrVT), 1600 TGA); 1601 Offset = DAG.getLoad(PtrVT, DL, 1602 DAG.getEntryNode(), TGA, MachinePointerInfo(), 1603 false, false, false, 0); 1604 } else { 1605 // Local Exec TLS Model 1606 assert(model == TLSModel::LocalExec); 1607 SDValue TGAHi = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, 1608 MipsII::MO_TPREL_HI); 1609 SDValue TGALo = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, 1610 MipsII::MO_TPREL_LO); 1611 SDValue Hi = DAG.getNode(MipsISD::Hi, DL, PtrVT, TGAHi); 1612 SDValue Lo = DAG.getNode(MipsISD::Lo, DL, PtrVT, TGALo); 1613 Offset = DAG.getNode(ISD::ADD, DL, PtrVT, Hi, Lo); 1614 } 1615 1616 SDValue ThreadPointer = DAG.getNode(MipsISD::ThreadPointer, DL, PtrVT); 1617 return DAG.getNode(ISD::ADD, DL, PtrVT, ThreadPointer, Offset); 1618 } 1619 1620 SDValue MipsTargetLowering:: 1621 lowerJumpTable(SDValue Op, SelectionDAG &DAG) const 1622 { 1623 JumpTableSDNode *N = cast<JumpTableSDNode>(Op); 1624 EVT Ty = Op.getValueType(); 1625 1626 if (getTargetMachine().getRelocationModel() != Reloc::PIC_ && !IsN64) 1627 return getAddrNonPIC(N, Ty, DAG); 1628 1629 return getAddrLocal(N, Ty, DAG, HasMips64); 1630 } 1631 1632 SDValue MipsTargetLowering:: 1633 lowerConstantPool(SDValue Op, SelectionDAG &DAG) const 1634 { 1635 // gp_rel relocation 1636 // FIXME: we should reference the constant pool using small data sections, 1637 // but the asm printer currently doesn't support this feature without 1638 // hacking it. This feature should come soon so we can uncomment the 1639 // stuff below. 1640 //if (IsInSmallSection(C->getType())) { 1641 // SDValue GPRelNode = DAG.getNode(MipsISD::GPRel, MVT::i32, CP); 1642 // SDValue GOT = DAG.getGLOBAL_OFFSET_TABLE(MVT::i32); 1643 // ResNode = DAG.getNode(ISD::ADD, MVT::i32, GOT, GPRelNode); 1644 ConstantPoolSDNode *N = cast<ConstantPoolSDNode>(Op); 1645 EVT Ty = Op.getValueType(); 1646 1647 if (getTargetMachine().getRelocationModel() != Reloc::PIC_ && !IsN64) 1648 return getAddrNonPIC(N, Ty, DAG); 1649 1650 return getAddrLocal(N, Ty, DAG, HasMips64); 1651 } 1652 1653 SDValue MipsTargetLowering::lowerVASTART(SDValue Op, SelectionDAG &DAG) const { 1654 MachineFunction &MF = DAG.getMachineFunction(); 1655 MipsFunctionInfo *FuncInfo = MF.getInfo<MipsFunctionInfo>(); 1656 1657 SDLoc DL(Op); 1658 SDValue FI = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), 1659 getPointerTy()); 1660 1661 // vastart just stores the address of the VarArgsFrameIndex slot into the 1662 // memory location argument. 1663 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue(); 1664 return DAG.getStore(Op.getOperand(0), DL, FI, Op.getOperand(1), 1665 MachinePointerInfo(SV), false, false, 0); 1666 } 1667 1668 static SDValue lowerFCOPYSIGN32(SDValue Op, SelectionDAG &DAG, 1669 bool HasExtractInsert) { 1670 EVT TyX = Op.getOperand(0).getValueType(); 1671 EVT TyY = Op.getOperand(1).getValueType(); 1672 SDValue Const1 = DAG.getConstant(1, MVT::i32); 1673 SDValue Const31 = DAG.getConstant(31, MVT::i32); 1674 SDLoc DL(Op); 1675 SDValue Res; 1676 1677 // If operand is of type f64, extract the upper 32-bit. Otherwise, bitcast it 1678 // to i32. 1679 SDValue X = (TyX == MVT::f32) ? 1680 DAG.getNode(ISD::BITCAST, DL, MVT::i32, Op.getOperand(0)) : 1681 DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32, Op.getOperand(0), 1682 Const1); 1683 SDValue Y = (TyY == MVT::f32) ? 1684 DAG.getNode(ISD::BITCAST, DL, MVT::i32, Op.getOperand(1)) : 1685 DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32, Op.getOperand(1), 1686 Const1); 1687 1688 if (HasExtractInsert) { 1689 // ext E, Y, 31, 1 ; extract bit31 of Y 1690 // ins X, E, 31, 1 ; insert extracted bit at bit31 of X 1691 SDValue E = DAG.getNode(MipsISD::Ext, DL, MVT::i32, Y, Const31, Const1); 1692 Res = DAG.getNode(MipsISD::Ins, DL, MVT::i32, E, Const31, Const1, X); 1693 } else { 1694 // sll SllX, X, 1 1695 // srl SrlX, SllX, 1 1696 // srl SrlY, Y, 31 1697 // sll SllY, SrlX, 31 1698 // or Or, SrlX, SllY 1699 SDValue SllX = DAG.getNode(ISD::SHL, DL, MVT::i32, X, Const1); 1700 SDValue SrlX = DAG.getNode(ISD::SRL, DL, MVT::i32, SllX, Const1); 1701 SDValue SrlY = DAG.getNode(ISD::SRL, DL, MVT::i32, Y, Const31); 1702 SDValue SllY = DAG.getNode(ISD::SHL, DL, MVT::i32, SrlY, Const31); 1703 Res = DAG.getNode(ISD::OR, DL, MVT::i32, SrlX, SllY); 1704 } 1705 1706 if (TyX == MVT::f32) 1707 return DAG.getNode(ISD::BITCAST, DL, Op.getOperand(0).getValueType(), Res); 1708 1709 SDValue LowX = DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32, 1710 Op.getOperand(0), DAG.getConstant(0, MVT::i32)); 1711 return DAG.getNode(MipsISD::BuildPairF64, DL, MVT::f64, LowX, Res); 1712 } 1713 1714 static SDValue lowerFCOPYSIGN64(SDValue Op, SelectionDAG &DAG, 1715 bool HasExtractInsert) { 1716 unsigned WidthX = Op.getOperand(0).getValueSizeInBits(); 1717 unsigned WidthY = Op.getOperand(1).getValueSizeInBits(); 1718 EVT TyX = MVT::getIntegerVT(WidthX), TyY = MVT::getIntegerVT(WidthY); 1719 SDValue Const1 = DAG.getConstant(1, MVT::i32); 1720 SDLoc DL(Op); 1721 1722 // Bitcast to integer nodes. 1723 SDValue X = DAG.getNode(ISD::BITCAST, DL, TyX, Op.getOperand(0)); 1724 SDValue Y = DAG.getNode(ISD::BITCAST, DL, TyY, Op.getOperand(1)); 1725 1726 if (HasExtractInsert) { 1727 // ext E, Y, width(Y) - 1, 1 ; extract bit width(Y)-1 of Y 1728 // ins X, E, width(X) - 1, 1 ; insert extracted bit at bit width(X)-1 of X 1729 SDValue E = DAG.getNode(MipsISD::Ext, DL, TyY, Y, 1730 DAG.getConstant(WidthY - 1, MVT::i32), Const1); 1731 1732 if (WidthX > WidthY) 1733 E = DAG.getNode(ISD::ZERO_EXTEND, DL, TyX, E); 1734 else if (WidthY > WidthX) 1735 E = DAG.getNode(ISD::TRUNCATE, DL, TyX, E); 1736 1737 SDValue I = DAG.getNode(MipsISD::Ins, DL, TyX, E, 1738 DAG.getConstant(WidthX - 1, MVT::i32), Const1, X); 1739 return DAG.getNode(ISD::BITCAST, DL, Op.getOperand(0).getValueType(), I); 1740 } 1741 1742 // (d)sll SllX, X, 1 1743 // (d)srl SrlX, SllX, 1 1744 // (d)srl SrlY, Y, width(Y)-1 1745 // (d)sll SllY, SrlX, width(Y)-1 1746 // or Or, SrlX, SllY 1747 SDValue SllX = DAG.getNode(ISD::SHL, DL, TyX, X, Const1); 1748 SDValue SrlX = DAG.getNode(ISD::SRL, DL, TyX, SllX, Const1); 1749 SDValue SrlY = DAG.getNode(ISD::SRL, DL, TyY, Y, 1750 DAG.getConstant(WidthY - 1, MVT::i32)); 1751 1752 if (WidthX > WidthY) 1753 SrlY = DAG.getNode(ISD::ZERO_EXTEND, DL, TyX, SrlY); 1754 else if (WidthY > WidthX) 1755 SrlY = DAG.getNode(ISD::TRUNCATE, DL, TyX, SrlY); 1756 1757 SDValue SllY = DAG.getNode(ISD::SHL, DL, TyX, SrlY, 1758 DAG.getConstant(WidthX - 1, MVT::i32)); 1759 SDValue Or = DAG.getNode(ISD::OR, DL, TyX, SrlX, SllY); 1760 return DAG.getNode(ISD::BITCAST, DL, Op.getOperand(0).getValueType(), Or); 1761 } 1762 1763 SDValue 1764 MipsTargetLowering::lowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const { 1765 if (Subtarget->hasMips64()) 1766 return lowerFCOPYSIGN64(Op, DAG, Subtarget->hasExtractInsert()); 1767 1768 return lowerFCOPYSIGN32(Op, DAG, Subtarget->hasExtractInsert()); 1769 } 1770 1771 static SDValue lowerFABS32(SDValue Op, SelectionDAG &DAG, 1772 bool HasExtractInsert) { 1773 SDValue Res, Const1 = DAG.getConstant(1, MVT::i32); 1774 SDLoc DL(Op); 1775 1776 // If operand is of type f64, extract the upper 32-bit. Otherwise, bitcast it 1777 // to i32. 1778 SDValue X = (Op.getValueType() == MVT::f32) ? 1779 DAG.getNode(ISD::BITCAST, DL, MVT::i32, Op.getOperand(0)) : 1780 DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32, Op.getOperand(0), 1781 Const1); 1782 1783 // Clear MSB. 1784 if (HasExtractInsert) 1785 Res = DAG.getNode(MipsISD::Ins, DL, MVT::i32, 1786 DAG.getRegister(Mips::ZERO, MVT::i32), 1787 DAG.getConstant(31, MVT::i32), Const1, X); 1788 else { 1789 SDValue SllX = DAG.getNode(ISD::SHL, DL, MVT::i32, X, Const1); 1790 Res = DAG.getNode(ISD::SRL, DL, MVT::i32, SllX, Const1); 1791 } 1792 1793 if (Op.getValueType() == MVT::f32) 1794 return DAG.getNode(ISD::BITCAST, DL, MVT::f32, Res); 1795 1796 SDValue LowX = DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32, 1797 Op.getOperand(0), DAG.getConstant(0, MVT::i32)); 1798 return DAG.getNode(MipsISD::BuildPairF64, DL, MVT::f64, LowX, Res); 1799 } 1800 1801 static SDValue lowerFABS64(SDValue Op, SelectionDAG &DAG, 1802 bool HasExtractInsert) { 1803 SDValue Res, Const1 = DAG.getConstant(1, MVT::i32); 1804 SDLoc DL(Op); 1805 1806 // Bitcast to integer node. 1807 SDValue X = DAG.getNode(ISD::BITCAST, DL, MVT::i64, Op.getOperand(0)); 1808 1809 // Clear MSB. 1810 if (HasExtractInsert) 1811 Res = DAG.getNode(MipsISD::Ins, DL, MVT::i64, 1812 DAG.getRegister(Mips::ZERO_64, MVT::i64), 1813 DAG.getConstant(63, MVT::i32), Const1, X); 1814 else { 1815 SDValue SllX = DAG.getNode(ISD::SHL, DL, MVT::i64, X, Const1); 1816 Res = DAG.getNode(ISD::SRL, DL, MVT::i64, SllX, Const1); 1817 } 1818 1819 return DAG.getNode(ISD::BITCAST, DL, MVT::f64, Res); 1820 } 1821 1822 SDValue 1823 MipsTargetLowering::lowerFABS(SDValue Op, SelectionDAG &DAG) const { 1824 if (Subtarget->hasMips64() && (Op.getValueType() == MVT::f64)) 1825 return lowerFABS64(Op, DAG, Subtarget->hasExtractInsert()); 1826 1827 return lowerFABS32(Op, DAG, Subtarget->hasExtractInsert()); 1828 } 1829 1830 SDValue MipsTargetLowering:: 1831 lowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const { 1832 // check the depth 1833 assert((cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue() == 0) && 1834 "Frame address can only be determined for current frame."); 1835 1836 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo(); 1837 MFI->setFrameAddressIsTaken(true); 1838 EVT VT = Op.getValueType(); 1839 SDLoc DL(Op); 1840 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), DL, 1841 IsN64 ? Mips::FP_64 : Mips::FP, VT); 1842 return FrameAddr; 1843 } 1844 1845 SDValue MipsTargetLowering::lowerRETURNADDR(SDValue Op, 1846 SelectionDAG &DAG) const { 1847 if (verifyReturnAddressArgumentIsConstant(Op, DAG)) 1848 return SDValue(); 1849 1850 // check the depth 1851 assert((cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue() == 0) && 1852 "Return address can be determined only for current frame."); 1853 1854 MachineFunction &MF = DAG.getMachineFunction(); 1855 MachineFrameInfo *MFI = MF.getFrameInfo(); 1856 MVT VT = Op.getSimpleValueType(); 1857 unsigned RA = IsN64 ? Mips::RA_64 : Mips::RA; 1858 MFI->setReturnAddressIsTaken(true); 1859 1860 // Return RA, which contains the return address. Mark it an implicit live-in. 1861 unsigned Reg = MF.addLiveIn(RA, getRegClassFor(VT)); 1862 return DAG.getCopyFromReg(DAG.getEntryNode(), SDLoc(Op), Reg, VT); 1863 } 1864 1865 // An EH_RETURN is the result of lowering llvm.eh.return which in turn is 1866 // generated from __builtin_eh_return (offset, handler) 1867 // The effect of this is to adjust the stack pointer by "offset" 1868 // and then branch to "handler". 1869 SDValue MipsTargetLowering::lowerEH_RETURN(SDValue Op, SelectionDAG &DAG) 1870 const { 1871 MachineFunction &MF = DAG.getMachineFunction(); 1872 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>(); 1873 1874 MipsFI->setCallsEhReturn(); 1875 SDValue Chain = Op.getOperand(0); 1876 SDValue Offset = Op.getOperand(1); 1877 SDValue Handler = Op.getOperand(2); 1878 SDLoc DL(Op); 1879 EVT Ty = IsN64 ? MVT::i64 : MVT::i32; 1880 1881 // Store stack offset in V1, store jump target in V0. Glue CopyToReg and 1882 // EH_RETURN nodes, so that instructions are emitted back-to-back. 1883 unsigned OffsetReg = IsN64 ? Mips::V1_64 : Mips::V1; 1884 unsigned AddrReg = IsN64 ? Mips::V0_64 : Mips::V0; 1885 Chain = DAG.getCopyToReg(Chain, DL, OffsetReg, Offset, SDValue()); 1886 Chain = DAG.getCopyToReg(Chain, DL, AddrReg, Handler, Chain.getValue(1)); 1887 return DAG.getNode(MipsISD::EH_RETURN, DL, MVT::Other, Chain, 1888 DAG.getRegister(OffsetReg, Ty), 1889 DAG.getRegister(AddrReg, getPointerTy()), 1890 Chain.getValue(1)); 1891 } 1892 1893 SDValue MipsTargetLowering::lowerATOMIC_FENCE(SDValue Op, 1894 SelectionDAG &DAG) const { 1895 // FIXME: Need pseudo-fence for 'singlethread' fences 1896 // FIXME: Set SType for weaker fences where supported/appropriate. 1897 unsigned SType = 0; 1898 SDLoc DL(Op); 1899 return DAG.getNode(MipsISD::Sync, DL, MVT::Other, Op.getOperand(0), 1900 DAG.getConstant(SType, MVT::i32)); 1901 } 1902 1903 SDValue MipsTargetLowering::lowerShiftLeftParts(SDValue Op, 1904 SelectionDAG &DAG) const { 1905 SDLoc DL(Op); 1906 SDValue Lo = Op.getOperand(0), Hi = Op.getOperand(1); 1907 SDValue Shamt = Op.getOperand(2); 1908 1909 // if shamt < 32: 1910 // lo = (shl lo, shamt) 1911 // hi = (or (shl hi, shamt) (srl (srl lo, 1), ~shamt)) 1912 // else: 1913 // lo = 0 1914 // hi = (shl lo, shamt[4:0]) 1915 SDValue Not = DAG.getNode(ISD::XOR, DL, MVT::i32, Shamt, 1916 DAG.getConstant(-1, MVT::i32)); 1917 SDValue ShiftRight1Lo = DAG.getNode(ISD::SRL, DL, MVT::i32, Lo, 1918 DAG.getConstant(1, MVT::i32)); 1919 SDValue ShiftRightLo = DAG.getNode(ISD::SRL, DL, MVT::i32, ShiftRight1Lo, 1920 Not); 1921 SDValue ShiftLeftHi = DAG.getNode(ISD::SHL, DL, MVT::i32, Hi, Shamt); 1922 SDValue Or = DAG.getNode(ISD::OR, DL, MVT::i32, ShiftLeftHi, ShiftRightLo); 1923 SDValue ShiftLeftLo = DAG.getNode(ISD::SHL, DL, MVT::i32, Lo, Shamt); 1924 SDValue Cond = DAG.getNode(ISD::AND, DL, MVT::i32, Shamt, 1925 DAG.getConstant(0x20, MVT::i32)); 1926 Lo = DAG.getNode(ISD::SELECT, DL, MVT::i32, Cond, 1927 DAG.getConstant(0, MVT::i32), ShiftLeftLo); 1928 Hi = DAG.getNode(ISD::SELECT, DL, MVT::i32, Cond, ShiftLeftLo, Or); 1929 1930 SDValue Ops[2] = {Lo, Hi}; 1931 return DAG.getMergeValues(Ops, 2, DL); 1932 } 1933 1934 SDValue MipsTargetLowering::lowerShiftRightParts(SDValue Op, SelectionDAG &DAG, 1935 bool IsSRA) const { 1936 SDLoc DL(Op); 1937 SDValue Lo = Op.getOperand(0), Hi = Op.getOperand(1); 1938 SDValue Shamt = Op.getOperand(2); 1939 1940 // if shamt < 32: 1941 // lo = (or (shl (shl hi, 1), ~shamt) (srl lo, shamt)) 1942 // if isSRA: 1943 // hi = (sra hi, shamt) 1944 // else: 1945 // hi = (srl hi, shamt) 1946 // else: 1947 // if isSRA: 1948 // lo = (sra hi, shamt[4:0]) 1949 // hi = (sra hi, 31) 1950 // else: 1951 // lo = (srl hi, shamt[4:0]) 1952 // hi = 0 1953 SDValue Not = DAG.getNode(ISD::XOR, DL, MVT::i32, Shamt, 1954 DAG.getConstant(-1, MVT::i32)); 1955 SDValue ShiftLeft1Hi = DAG.getNode(ISD::SHL, DL, MVT::i32, Hi, 1956 DAG.getConstant(1, MVT::i32)); 1957 SDValue ShiftLeftHi = DAG.getNode(ISD::SHL, DL, MVT::i32, ShiftLeft1Hi, Not); 1958 SDValue ShiftRightLo = DAG.getNode(ISD::SRL, DL, MVT::i32, Lo, Shamt); 1959 SDValue Or = DAG.getNode(ISD::OR, DL, MVT::i32, ShiftLeftHi, ShiftRightLo); 1960 SDValue ShiftRightHi = DAG.getNode(IsSRA ? ISD::SRA : ISD::SRL, DL, MVT::i32, 1961 Hi, Shamt); 1962 SDValue Cond = DAG.getNode(ISD::AND, DL, MVT::i32, Shamt, 1963 DAG.getConstant(0x20, MVT::i32)); 1964 SDValue Shift31 = DAG.getNode(ISD::SRA, DL, MVT::i32, Hi, 1965 DAG.getConstant(31, MVT::i32)); 1966 Lo = DAG.getNode(ISD::SELECT, DL, MVT::i32, Cond, ShiftRightHi, Or); 1967 Hi = DAG.getNode(ISD::SELECT, DL, MVT::i32, Cond, 1968 IsSRA ? Shift31 : DAG.getConstant(0, MVT::i32), 1969 ShiftRightHi); 1970 1971 SDValue Ops[2] = {Lo, Hi}; 1972 return DAG.getMergeValues(Ops, 2, DL); 1973 } 1974 1975 static SDValue createLoadLR(unsigned Opc, SelectionDAG &DAG, LoadSDNode *LD, 1976 SDValue Chain, SDValue Src, unsigned Offset) { 1977 SDValue Ptr = LD->getBasePtr(); 1978 EVT VT = LD->getValueType(0), MemVT = LD->getMemoryVT(); 1979 EVT BasePtrVT = Ptr.getValueType(); 1980 SDLoc DL(LD); 1981 SDVTList VTList = DAG.getVTList(VT, MVT::Other); 1982 1983 if (Offset) 1984 Ptr = DAG.getNode(ISD::ADD, DL, BasePtrVT, Ptr, 1985 DAG.getConstant(Offset, BasePtrVT)); 1986 1987 SDValue Ops[] = { Chain, Ptr, Src }; 1988 return DAG.getMemIntrinsicNode(Opc, DL, VTList, Ops, 3, MemVT, 1989 LD->getMemOperand()); 1990 } 1991 1992 // Expand an unaligned 32 or 64-bit integer load node. 1993 SDValue MipsTargetLowering::lowerLOAD(SDValue Op, SelectionDAG &DAG) const { 1994 LoadSDNode *LD = cast<LoadSDNode>(Op); 1995 EVT MemVT = LD->getMemoryVT(); 1996 1997 // Return if load is aligned or if MemVT is neither i32 nor i64. 1998 if ((LD->getAlignment() >= MemVT.getSizeInBits() / 8) || 1999 ((MemVT != MVT::i32) && (MemVT != MVT::i64))) 2000 return SDValue(); 2001 2002 bool IsLittle = Subtarget->isLittle(); 2003 EVT VT = Op.getValueType(); 2004 ISD::LoadExtType ExtType = LD->getExtensionType(); 2005 SDValue Chain = LD->getChain(), Undef = DAG.getUNDEF(VT); 2006 2007 assert((VT == MVT::i32) || (VT == MVT::i64)); 2008 2009 // Expand 2010 // (set dst, (i64 (load baseptr))) 2011 // to 2012 // (set tmp, (ldl (add baseptr, 7), undef)) 2013 // (set dst, (ldr baseptr, tmp)) 2014 if ((VT == MVT::i64) && (ExtType == ISD::NON_EXTLOAD)) { 2015 SDValue LDL = createLoadLR(MipsISD::LDL, DAG, LD, Chain, Undef, 2016 IsLittle ? 7 : 0); 2017 return createLoadLR(MipsISD::LDR, DAG, LD, LDL.getValue(1), LDL, 2018 IsLittle ? 0 : 7); 2019 } 2020 2021 SDValue LWL = createLoadLR(MipsISD::LWL, DAG, LD, Chain, Undef, 2022 IsLittle ? 3 : 0); 2023 SDValue LWR = createLoadLR(MipsISD::LWR, DAG, LD, LWL.getValue(1), LWL, 2024 IsLittle ? 0 : 3); 2025 2026 // Expand 2027 // (set dst, (i32 (load baseptr))) or 2028 // (set dst, (i64 (sextload baseptr))) or 2029 // (set dst, (i64 (extload baseptr))) 2030 // to 2031 // (set tmp, (lwl (add baseptr, 3), undef)) 2032 // (set dst, (lwr baseptr, tmp)) 2033 if ((VT == MVT::i32) || (ExtType == ISD::SEXTLOAD) || 2034 (ExtType == ISD::EXTLOAD)) 2035 return LWR; 2036 2037 assert((VT == MVT::i64) && (ExtType == ISD::ZEXTLOAD)); 2038 2039 // Expand 2040 // (set dst, (i64 (zextload baseptr))) 2041 // to 2042 // (set tmp0, (lwl (add baseptr, 3), undef)) 2043 // (set tmp1, (lwr baseptr, tmp0)) 2044 // (set tmp2, (shl tmp1, 32)) 2045 // (set dst, (srl tmp2, 32)) 2046 SDLoc DL(LD); 2047 SDValue Const32 = DAG.getConstant(32, MVT::i32); 2048 SDValue SLL = DAG.getNode(ISD::SHL, DL, MVT::i64, LWR, Const32); 2049 SDValue SRL = DAG.getNode(ISD::SRL, DL, MVT::i64, SLL, Const32); 2050 SDValue Ops[] = { SRL, LWR.getValue(1) }; 2051 return DAG.getMergeValues(Ops, 2, DL); 2052 } 2053 2054 static SDValue createStoreLR(unsigned Opc, SelectionDAG &DAG, StoreSDNode *SD, 2055 SDValue Chain, unsigned Offset) { 2056 SDValue Ptr = SD->getBasePtr(), Value = SD->getValue(); 2057 EVT MemVT = SD->getMemoryVT(), BasePtrVT = Ptr.getValueType(); 2058 SDLoc DL(SD); 2059 SDVTList VTList = DAG.getVTList(MVT::Other); 2060 2061 if (Offset) 2062 Ptr = DAG.getNode(ISD::ADD, DL, BasePtrVT, Ptr, 2063 DAG.getConstant(Offset, BasePtrVT)); 2064 2065 SDValue Ops[] = { Chain, Value, Ptr }; 2066 return DAG.getMemIntrinsicNode(Opc, DL, VTList, Ops, 3, MemVT, 2067 SD->getMemOperand()); 2068 } 2069 2070 // Expand an unaligned 32 or 64-bit integer store node. 2071 static SDValue lowerUnalignedIntStore(StoreSDNode *SD, SelectionDAG &DAG, 2072 bool IsLittle) { 2073 SDValue Value = SD->getValue(), Chain = SD->getChain(); 2074 EVT VT = Value.getValueType(); 2075 2076 // Expand 2077 // (store val, baseptr) or 2078 // (truncstore val, baseptr) 2079 // to 2080 // (swl val, (add baseptr, 3)) 2081 // (swr val, baseptr) 2082 if ((VT == MVT::i32) || SD->isTruncatingStore()) { 2083 SDValue SWL = createStoreLR(MipsISD::SWL, DAG, SD, Chain, 2084 IsLittle ? 3 : 0); 2085 return createStoreLR(MipsISD::SWR, DAG, SD, SWL, IsLittle ? 0 : 3); 2086 } 2087 2088 assert(VT == MVT::i64); 2089 2090 // Expand 2091 // (store val, baseptr) 2092 // to 2093 // (sdl val, (add baseptr, 7)) 2094 // (sdr val, baseptr) 2095 SDValue SDL = createStoreLR(MipsISD::SDL, DAG, SD, Chain, IsLittle ? 7 : 0); 2096 return createStoreLR(MipsISD::SDR, DAG, SD, SDL, IsLittle ? 0 : 7); 2097 } 2098 2099 // Lower (store (fp_to_sint $fp) $ptr) to (store (TruncIntFP $fp), $ptr). 2100 static SDValue lowerFP_TO_SINT_STORE(StoreSDNode *SD, SelectionDAG &DAG) { 2101 SDValue Val = SD->getValue(); 2102 2103 if (Val.getOpcode() != ISD::FP_TO_SINT) 2104 return SDValue(); 2105 2106 EVT FPTy = EVT::getFloatingPointVT(Val.getValueSizeInBits()); 2107 SDValue Tr = DAG.getNode(MipsISD::TruncIntFP, SDLoc(Val), FPTy, 2108 Val.getOperand(0)); 2109 2110 return DAG.getStore(SD->getChain(), SDLoc(SD), Tr, SD->getBasePtr(), 2111 SD->getPointerInfo(), SD->isVolatile(), 2112 SD->isNonTemporal(), SD->getAlignment()); 2113 } 2114 2115 SDValue MipsTargetLowering::lowerSTORE(SDValue Op, SelectionDAG &DAG) const { 2116 StoreSDNode *SD = cast<StoreSDNode>(Op); 2117 EVT MemVT = SD->getMemoryVT(); 2118 2119 // Lower unaligned integer stores. 2120 if ((SD->getAlignment() < MemVT.getSizeInBits() / 8) && 2121 ((MemVT == MVT::i32) || (MemVT == MVT::i64))) 2122 return lowerUnalignedIntStore(SD, DAG, Subtarget->isLittle()); 2123 2124 return lowerFP_TO_SINT_STORE(SD, DAG); 2125 } 2126 2127 SDValue MipsTargetLowering::lowerADD(SDValue Op, SelectionDAG &DAG) const { 2128 if (Op->getOperand(0).getOpcode() != ISD::FRAMEADDR 2129 || cast<ConstantSDNode> 2130 (Op->getOperand(0).getOperand(0))->getZExtValue() != 0 2131 || Op->getOperand(1).getOpcode() != ISD::FRAME_TO_ARGS_OFFSET) 2132 return SDValue(); 2133 2134 // The pattern 2135 // (add (frameaddr 0), (frame_to_args_offset)) 2136 // results from lowering llvm.eh.dwarf.cfa intrinsic. Transform it to 2137 // (add FrameObject, 0) 2138 // where FrameObject is a fixed StackObject with offset 0 which points to 2139 // the old stack pointer. 2140 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo(); 2141 EVT ValTy = Op->getValueType(0); 2142 int FI = MFI->CreateFixedObject(Op.getValueSizeInBits() / 8, 0, false); 2143 SDValue InArgsAddr = DAG.getFrameIndex(FI, ValTy); 2144 return DAG.getNode(ISD::ADD, SDLoc(Op), ValTy, InArgsAddr, 2145 DAG.getConstant(0, ValTy)); 2146 } 2147 2148 SDValue MipsTargetLowering::lowerFP_TO_SINT(SDValue Op, 2149 SelectionDAG &DAG) const { 2150 EVT FPTy = EVT::getFloatingPointVT(Op.getValueSizeInBits()); 2151 SDValue Trunc = DAG.getNode(MipsISD::TruncIntFP, SDLoc(Op), FPTy, 2152 Op.getOperand(0)); 2153 return DAG.getNode(ISD::BITCAST, SDLoc(Op), Op.getValueType(), Trunc); 2154 } 2155 2156 //===----------------------------------------------------------------------===// 2157 // Calling Convention Implementation 2158 //===----------------------------------------------------------------------===// 2159 2160 //===----------------------------------------------------------------------===// 2161 // TODO: Implement a generic logic using tblgen that can support this. 2162 // Mips O32 ABI rules: 2163 // --- 2164 // i32 - Passed in A0, A1, A2, A3 and stack 2165 // f32 - Only passed in f32 registers if no int reg has been used yet to hold 2166 // an argument. Otherwise, passed in A1, A2, A3 and stack. 2167 // f64 - Only passed in two aliased f32 registers if no int reg has been used 2168 // yet to hold an argument. Otherwise, use A2, A3 and stack. If A1 is 2169 // not used, it must be shadowed. If only A3 is avaiable, shadow it and 2170 // go to stack. 2171 // 2172 // For vararg functions, all arguments are passed in A0, A1, A2, A3 and stack. 2173 //===----------------------------------------------------------------------===// 2174 2175 static bool CC_MipsO32(unsigned ValNo, MVT ValVT, MVT LocVT, 2176 CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, 2177 CCState &State, const uint16_t *F64Regs) { 2178 2179 static const unsigned IntRegsSize = 4, FloatRegsSize = 2; 2180 2181 static const uint16_t IntRegs[] = { Mips::A0, Mips::A1, Mips::A2, Mips::A3 }; 2182 static const uint16_t F32Regs[] = { Mips::F12, Mips::F14 }; 2183 2184 // Do not process byval args here. 2185 if (ArgFlags.isByVal()) 2186 return true; 2187 2188 // Promote i8 and i16 2189 if (LocVT == MVT::i8 || LocVT == MVT::i16) { 2190 LocVT = MVT::i32; 2191 if (ArgFlags.isSExt()) 2192 LocInfo = CCValAssign::SExt; 2193 else if (ArgFlags.isZExt()) 2194 LocInfo = CCValAssign::ZExt; 2195 else 2196 LocInfo = CCValAssign::AExt; 2197 } 2198 2199 unsigned Reg; 2200 2201 // f32 and f64 are allocated in A0, A1, A2, A3 when either of the following 2202 // is true: function is vararg, argument is 3rd or higher, there is previous 2203 // argument which is not f32 or f64. 2204 bool AllocateFloatsInIntReg = State.isVarArg() || ValNo > 1 2205 || State.getFirstUnallocated(F32Regs, FloatRegsSize) != ValNo; 2206 unsigned OrigAlign = ArgFlags.getOrigAlign(); 2207 bool isI64 = (ValVT == MVT::i32 && OrigAlign == 8); 2208 2209 if (ValVT == MVT::i32 || (ValVT == MVT::f32 && AllocateFloatsInIntReg)) { 2210 Reg = State.AllocateReg(IntRegs, IntRegsSize); 2211 // If this is the first part of an i64 arg, 2212 // the allocated register must be either A0 or A2. 2213 if (isI64 && (Reg == Mips::A1 || Reg == Mips::A3)) 2214 Reg = State.AllocateReg(IntRegs, IntRegsSize); 2215 LocVT = MVT::i32; 2216 } else if (ValVT == MVT::f64 && AllocateFloatsInIntReg) { 2217 // Allocate int register and shadow next int register. If first 2218 // available register is Mips::A1 or Mips::A3, shadow it too. 2219 Reg = State.AllocateReg(IntRegs, IntRegsSize); 2220 if (Reg == Mips::A1 || Reg == Mips::A3) 2221 Reg = State.AllocateReg(IntRegs, IntRegsSize); 2222 State.AllocateReg(IntRegs, IntRegsSize); 2223 LocVT = MVT::i32; 2224 } else if (ValVT.isFloatingPoint() && !AllocateFloatsInIntReg) { 2225 // we are guaranteed to find an available float register 2226 if (ValVT == MVT::f32) { 2227 Reg = State.AllocateReg(F32Regs, FloatRegsSize); 2228 // Shadow int register 2229 State.AllocateReg(IntRegs, IntRegsSize); 2230 } else { 2231 Reg = State.AllocateReg(F64Regs, FloatRegsSize); 2232 // Shadow int registers 2233 unsigned Reg2 = State.AllocateReg(IntRegs, IntRegsSize); 2234 if (Reg2 == Mips::A1 || Reg2 == Mips::A3) 2235 State.AllocateReg(IntRegs, IntRegsSize); 2236 State.AllocateReg(IntRegs, IntRegsSize); 2237 } 2238 } else 2239 llvm_unreachable("Cannot handle this ValVT."); 2240 2241 if (!Reg) { 2242 unsigned Offset = State.AllocateStack(ValVT.getSizeInBits() >> 3, 2243 OrigAlign); 2244 State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo)); 2245 } else 2246 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); 2247 2248 return false; 2249 } 2250 2251 static bool CC_MipsO32_FP32(unsigned ValNo, MVT ValVT, 2252 MVT LocVT, CCValAssign::LocInfo LocInfo, 2253 ISD::ArgFlagsTy ArgFlags, CCState &State) { 2254 static const uint16_t F64Regs[] = { Mips::D6, Mips::D7 }; 2255 2256 return CC_MipsO32(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State, F64Regs); 2257 } 2258 2259 static bool CC_MipsO32_FP64(unsigned ValNo, MVT ValVT, 2260 MVT LocVT, CCValAssign::LocInfo LocInfo, 2261 ISD::ArgFlagsTy ArgFlags, CCState &State) { 2262 static const uint16_t F64Regs[] = { Mips::D12_64, Mips::D14_64 }; 2263 2264 return CC_MipsO32(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State, F64Regs); 2265 } 2266 2267 #include "MipsGenCallingConv.inc" 2268 2269 //===----------------------------------------------------------------------===// 2270 // Call Calling Convention Implementation 2271 //===----------------------------------------------------------------------===// 2272 2273 // Return next O32 integer argument register. 2274 static unsigned getNextIntArgReg(unsigned Reg) { 2275 assert((Reg == Mips::A0) || (Reg == Mips::A2)); 2276 return (Reg == Mips::A0) ? Mips::A1 : Mips::A3; 2277 } 2278 2279 SDValue 2280 MipsTargetLowering::passArgOnStack(SDValue StackPtr, unsigned Offset, 2281 SDValue Chain, SDValue Arg, SDLoc DL, 2282 bool IsTailCall, SelectionDAG &DAG) const { 2283 if (!IsTailCall) { 2284 SDValue PtrOff = DAG.getNode(ISD::ADD, DL, getPointerTy(), StackPtr, 2285 DAG.getIntPtrConstant(Offset)); 2286 return DAG.getStore(Chain, DL, Arg, PtrOff, MachinePointerInfo(), false, 2287 false, 0); 2288 } 2289 2290 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo(); 2291 int FI = MFI->CreateFixedObject(Arg.getValueSizeInBits() / 8, Offset, false); 2292 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy()); 2293 return DAG.getStore(Chain, DL, Arg, FIN, MachinePointerInfo(), 2294 /*isVolatile=*/ true, false, 0); 2295 } 2296 2297 void MipsTargetLowering:: 2298 getOpndList(SmallVectorImpl<SDValue> &Ops, 2299 std::deque< std::pair<unsigned, SDValue> > &RegsToPass, 2300 bool IsPICCall, bool GlobalOrExternal, bool InternalLinkage, 2301 CallLoweringInfo &CLI, SDValue Callee, SDValue Chain) const { 2302 // Insert node "GP copy globalreg" before call to function. 2303 // 2304 // R_MIPS_CALL* operators (emitted when non-internal functions are called 2305 // in PIC mode) allow symbols to be resolved via lazy binding. 2306 // The lazy binding stub requires GP to point to the GOT. 2307 if (IsPICCall && !InternalLinkage) { 2308 unsigned GPReg = IsN64 ? Mips::GP_64 : Mips::GP; 2309 EVT Ty = IsN64 ? MVT::i64 : MVT::i32; 2310 RegsToPass.push_back(std::make_pair(GPReg, getGlobalReg(CLI.DAG, Ty))); 2311 } 2312 2313 // Build a sequence of copy-to-reg nodes chained together with token 2314 // chain and flag operands which copy the outgoing args into registers. 2315 // The InFlag in necessary since all emitted instructions must be 2316 // stuck together. 2317 SDValue InFlag; 2318 2319 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) { 2320 Chain = CLI.DAG.getCopyToReg(Chain, CLI.DL, RegsToPass[i].first, 2321 RegsToPass[i].second, InFlag); 2322 InFlag = Chain.getValue(1); 2323 } 2324 2325 // Add argument registers to the end of the list so that they are 2326 // known live into the call. 2327 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) 2328 Ops.push_back(CLI.DAG.getRegister(RegsToPass[i].first, 2329 RegsToPass[i].second.getValueType())); 2330 2331 // Add a register mask operand representing the call-preserved registers. 2332 const TargetRegisterInfo *TRI = getTargetMachine().getRegisterInfo(); 2333 const uint32_t *Mask = TRI->getCallPreservedMask(CLI.CallConv); 2334 assert(Mask && "Missing call preserved mask for calling convention"); 2335 if (Subtarget->inMips16HardFloat()) { 2336 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(CLI.Callee)) { 2337 llvm::StringRef Sym = G->getGlobal()->getName(); 2338 Function *F = G->getGlobal()->getParent()->getFunction(Sym); 2339 if (F && F->hasFnAttribute("__Mips16RetHelper")) { 2340 Mask = MipsRegisterInfo::getMips16RetHelperMask(); 2341 } 2342 } 2343 } 2344 Ops.push_back(CLI.DAG.getRegisterMask(Mask)); 2345 2346 if (InFlag.getNode()) 2347 Ops.push_back(InFlag); 2348 } 2349 2350 /// LowerCall - functions arguments are copied from virtual regs to 2351 /// (physical regs)/(stack frame), CALLSEQ_START and CALLSEQ_END are emitted. 2352 SDValue 2353 MipsTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI, 2354 SmallVectorImpl<SDValue> &InVals) const { 2355 SelectionDAG &DAG = CLI.DAG; 2356 SDLoc DL = CLI.DL; 2357 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs; 2358 SmallVectorImpl<SDValue> &OutVals = CLI.OutVals; 2359 SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins; 2360 SDValue Chain = CLI.Chain; 2361 SDValue Callee = CLI.Callee; 2362 bool &IsTailCall = CLI.IsTailCall; 2363 CallingConv::ID CallConv = CLI.CallConv; 2364 bool IsVarArg = CLI.IsVarArg; 2365 2366 MachineFunction &MF = DAG.getMachineFunction(); 2367 MachineFrameInfo *MFI = MF.getFrameInfo(); 2368 const TargetFrameLowering *TFL = MF.getTarget().getFrameLowering(); 2369 MipsFunctionInfo *FuncInfo = MF.getInfo<MipsFunctionInfo>(); 2370 bool IsPIC = getTargetMachine().getRelocationModel() == Reloc::PIC_; 2371 2372 // Analyze operands of the call, assigning locations to each operand. 2373 SmallVector<CCValAssign, 16> ArgLocs; 2374 CCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), 2375 getTargetMachine(), ArgLocs, *DAG.getContext()); 2376 MipsCC::SpecialCallingConvType SpecialCallingConv = 2377 getSpecialCallingConv(Callee); 2378 MipsCC MipsCCInfo(CallConv, IsO32, Subtarget->isFP64bit(), CCInfo, 2379 SpecialCallingConv); 2380 2381 MipsCCInfo.analyzeCallOperands(Outs, IsVarArg, 2382 Subtarget->mipsSEUsesSoftFloat(), 2383 Callee.getNode(), CLI.Args); 2384 2385 // Get a count of how many bytes are to be pushed on the stack. 2386 unsigned NextStackOffset = CCInfo.getNextStackOffset(); 2387 2388 // Check if it's really possible to do a tail call. 2389 if (IsTailCall) 2390 IsTailCall = 2391 isEligibleForTailCallOptimization(MipsCCInfo, NextStackOffset, 2392 *MF.getInfo<MipsFunctionInfo>()); 2393 2394 if (IsTailCall) 2395 ++NumTailCalls; 2396 2397 // Chain is the output chain of the last Load/Store or CopyToReg node. 2398 // ByValChain is the output chain of the last Memcpy node created for copying 2399 // byval arguments to the stack. 2400 unsigned StackAlignment = TFL->getStackAlignment(); 2401 NextStackOffset = RoundUpToAlignment(NextStackOffset, StackAlignment); 2402 SDValue NextStackOffsetVal = DAG.getIntPtrConstant(NextStackOffset, true); 2403 2404 if (!IsTailCall) 2405 Chain = DAG.getCALLSEQ_START(Chain, NextStackOffsetVal, DL); 2406 2407 SDValue StackPtr = DAG.getCopyFromReg(Chain, DL, 2408 IsN64 ? Mips::SP_64 : Mips::SP, 2409 getPointerTy()); 2410 2411 // With EABI is it possible to have 16 args on registers. 2412 std::deque< std::pair<unsigned, SDValue> > RegsToPass; 2413 SmallVector<SDValue, 8> MemOpChains; 2414 MipsCC::byval_iterator ByValArg = MipsCCInfo.byval_begin(); 2415 2416 // Walk the register/memloc assignments, inserting copies/loads. 2417 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { 2418 SDValue Arg = OutVals[i]; 2419 CCValAssign &VA = ArgLocs[i]; 2420 MVT ValVT = VA.getValVT(), LocVT = VA.getLocVT(); 2421 ISD::ArgFlagsTy Flags = Outs[i].Flags; 2422 2423 // ByVal Arg. 2424 if (Flags.isByVal()) { 2425 assert(Flags.getByValSize() && 2426 "ByVal args of size 0 should have been ignored by front-end."); 2427 assert(ByValArg != MipsCCInfo.byval_end()); 2428 assert(!IsTailCall && 2429 "Do not tail-call optimize if there is a byval argument."); 2430 passByValArg(Chain, DL, RegsToPass, MemOpChains, StackPtr, MFI, DAG, Arg, 2431 MipsCCInfo, *ByValArg, Flags, Subtarget->isLittle()); 2432 ++ByValArg; 2433 continue; 2434 } 2435 2436 // Promote the value if needed. 2437 switch (VA.getLocInfo()) { 2438 default: llvm_unreachable("Unknown loc info!"); 2439 case CCValAssign::Full: 2440 if (VA.isRegLoc()) { 2441 if ((ValVT == MVT::f32 && LocVT == MVT::i32) || 2442 (ValVT == MVT::f64 && LocVT == MVT::i64) || 2443 (ValVT == MVT::i64 && LocVT == MVT::f64)) 2444 Arg = DAG.getNode(ISD::BITCAST, DL, LocVT, Arg); 2445 else if (ValVT == MVT::f64 && LocVT == MVT::i32) { 2446 SDValue Lo = DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32, 2447 Arg, DAG.getConstant(0, MVT::i32)); 2448 SDValue Hi = DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32, 2449 Arg, DAG.getConstant(1, MVT::i32)); 2450 if (!Subtarget->isLittle()) 2451 std::swap(Lo, Hi); 2452 unsigned LocRegLo = VA.getLocReg(); 2453 unsigned LocRegHigh = getNextIntArgReg(LocRegLo); 2454 RegsToPass.push_back(std::make_pair(LocRegLo, Lo)); 2455 RegsToPass.push_back(std::make_pair(LocRegHigh, Hi)); 2456 continue; 2457 } 2458 } 2459 break; 2460 case CCValAssign::SExt: 2461 Arg = DAG.getNode(ISD::SIGN_EXTEND, DL, LocVT, Arg); 2462 break; 2463 case CCValAssign::ZExt: 2464 Arg = DAG.getNode(ISD::ZERO_EXTEND, DL, LocVT, Arg); 2465 break; 2466 case CCValAssign::AExt: 2467 Arg = DAG.getNode(ISD::ANY_EXTEND, DL, LocVT, Arg); 2468 break; 2469 } 2470 2471 // Arguments that can be passed on register must be kept at 2472 // RegsToPass vector 2473 if (VA.isRegLoc()) { 2474 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg)); 2475 continue; 2476 } 2477 2478 // Register can't get to this point... 2479 assert(VA.isMemLoc()); 2480 2481 // emit ISD::STORE whichs stores the 2482 // parameter value to a stack Location 2483 MemOpChains.push_back(passArgOnStack(StackPtr, VA.getLocMemOffset(), 2484 Chain, Arg, DL, IsTailCall, DAG)); 2485 } 2486 2487 // Transform all store nodes into one single node because all store 2488 // nodes are independent of each other. 2489 if (!MemOpChains.empty()) 2490 Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, 2491 &MemOpChains[0], MemOpChains.size()); 2492 2493 // If the callee is a GlobalAddress/ExternalSymbol node (quite common, every 2494 // direct call is) turn it into a TargetGlobalAddress/TargetExternalSymbol 2495 // node so that legalize doesn't hack it. 2496 bool IsPICCall = (IsN64 || IsPIC); // true if calls are translated to jalr $25 2497 bool GlobalOrExternal = false, InternalLinkage = false; 2498 SDValue CalleeLo; 2499 EVT Ty = Callee.getValueType(); 2500 2501 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) { 2502 if (IsPICCall) { 2503 const GlobalValue *Val = G->getGlobal(); 2504 InternalLinkage = Val->hasInternalLinkage(); 2505 2506 if (InternalLinkage) 2507 Callee = getAddrLocal(G, Ty, DAG, HasMips64); 2508 else if (LargeGOT) 2509 Callee = getAddrGlobalLargeGOT(G, Ty, DAG, MipsII::MO_CALL_HI16, 2510 MipsII::MO_CALL_LO16, Chain, 2511 FuncInfo->callPtrInfo(Val)); 2512 else 2513 Callee = getAddrGlobal(G, Ty, DAG, MipsII::MO_GOT_CALL, Chain, 2514 FuncInfo->callPtrInfo(Val)); 2515 } else 2516 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), DL, getPointerTy(), 0, 2517 MipsII::MO_NO_FLAG); 2518 GlobalOrExternal = true; 2519 } 2520 else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) { 2521 const char *Sym = S->getSymbol(); 2522 2523 if (!IsN64 && !IsPIC) // !N64 && static 2524 Callee = DAG.getTargetExternalSymbol(Sym, getPointerTy(), 2525 MipsII::MO_NO_FLAG); 2526 else if (LargeGOT) 2527 Callee = getAddrGlobalLargeGOT(S, Ty, DAG, MipsII::MO_CALL_HI16, 2528 MipsII::MO_CALL_LO16, Chain, 2529 FuncInfo->callPtrInfo(Sym)); 2530 else // N64 || PIC 2531 Callee = getAddrGlobal(S, Ty, DAG, MipsII::MO_GOT_CALL, Chain, 2532 FuncInfo->callPtrInfo(Sym)); 2533 2534 GlobalOrExternal = true; 2535 } 2536 2537 SmallVector<SDValue, 8> Ops(1, Chain); 2538 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue); 2539 2540 getOpndList(Ops, RegsToPass, IsPICCall, GlobalOrExternal, InternalLinkage, 2541 CLI, Callee, Chain); 2542 2543 if (IsTailCall) 2544 return DAG.getNode(MipsISD::TailCall, DL, MVT::Other, &Ops[0], Ops.size()); 2545 2546 Chain = DAG.getNode(MipsISD::JmpLink, DL, NodeTys, &Ops[0], Ops.size()); 2547 SDValue InFlag = Chain.getValue(1); 2548 2549 // Create the CALLSEQ_END node. 2550 Chain = DAG.getCALLSEQ_END(Chain, NextStackOffsetVal, 2551 DAG.getIntPtrConstant(0, true), InFlag, DL); 2552 InFlag = Chain.getValue(1); 2553 2554 // Handle result values, copying them out of physregs into vregs that we 2555 // return. 2556 return LowerCallResult(Chain, InFlag, CallConv, IsVarArg, 2557 Ins, DL, DAG, InVals, CLI.Callee.getNode(), CLI.RetTy); 2558 } 2559 2560 /// LowerCallResult - Lower the result values of a call into the 2561 /// appropriate copies out of appropriate physical registers. 2562 SDValue 2563 MipsTargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag, 2564 CallingConv::ID CallConv, bool IsVarArg, 2565 const SmallVectorImpl<ISD::InputArg> &Ins, 2566 SDLoc DL, SelectionDAG &DAG, 2567 SmallVectorImpl<SDValue> &InVals, 2568 const SDNode *CallNode, 2569 const Type *RetTy) const { 2570 // Assign locations to each value returned by this call. 2571 SmallVector<CCValAssign, 16> RVLocs; 2572 CCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), 2573 getTargetMachine(), RVLocs, *DAG.getContext()); 2574 MipsCC MipsCCInfo(CallConv, IsO32, Subtarget->isFP64bit(), CCInfo); 2575 2576 MipsCCInfo.analyzeCallResult(Ins, Subtarget->mipsSEUsesSoftFloat(), 2577 CallNode, RetTy); 2578 2579 // Copy all of the result registers out of their specified physreg. 2580 for (unsigned i = 0; i != RVLocs.size(); ++i) { 2581 SDValue Val = DAG.getCopyFromReg(Chain, DL, RVLocs[i].getLocReg(), 2582 RVLocs[i].getLocVT(), InFlag); 2583 Chain = Val.getValue(1); 2584 InFlag = Val.getValue(2); 2585 2586 if (RVLocs[i].getValVT() != RVLocs[i].getLocVT()) 2587 Val = DAG.getNode(ISD::BITCAST, DL, RVLocs[i].getValVT(), Val); 2588 2589 InVals.push_back(Val); 2590 } 2591 2592 return Chain; 2593 } 2594 2595 //===----------------------------------------------------------------------===// 2596 // Formal Arguments Calling Convention Implementation 2597 //===----------------------------------------------------------------------===// 2598 /// LowerFormalArguments - transform physical registers into virtual registers 2599 /// and generate load operations for arguments places on the stack. 2600 SDValue 2601 MipsTargetLowering::LowerFormalArguments(SDValue Chain, 2602 CallingConv::ID CallConv, 2603 bool IsVarArg, 2604 const SmallVectorImpl<ISD::InputArg> &Ins, 2605 SDLoc DL, SelectionDAG &DAG, 2606 SmallVectorImpl<SDValue> &InVals) 2607 const { 2608 MachineFunction &MF = DAG.getMachineFunction(); 2609 MachineFrameInfo *MFI = MF.getFrameInfo(); 2610 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>(); 2611 2612 MipsFI->setVarArgsFrameIndex(0); 2613 2614 // Used with vargs to acumulate store chains. 2615 std::vector<SDValue> OutChains; 2616 2617 // Assign locations to all of the incoming arguments. 2618 SmallVector<CCValAssign, 16> ArgLocs; 2619 CCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), 2620 getTargetMachine(), ArgLocs, *DAG.getContext()); 2621 MipsCC MipsCCInfo(CallConv, IsO32, Subtarget->isFP64bit(), CCInfo); 2622 Function::const_arg_iterator FuncArg = 2623 DAG.getMachineFunction().getFunction()->arg_begin(); 2624 bool UseSoftFloat = Subtarget->mipsSEUsesSoftFloat(); 2625 2626 MipsCCInfo.analyzeFormalArguments(Ins, UseSoftFloat, FuncArg); 2627 MipsFI->setFormalArgInfo(CCInfo.getNextStackOffset(), 2628 MipsCCInfo.hasByValArg()); 2629 2630 unsigned CurArgIdx = 0; 2631 MipsCC::byval_iterator ByValArg = MipsCCInfo.byval_begin(); 2632 2633 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { 2634 CCValAssign &VA = ArgLocs[i]; 2635 std::advance(FuncArg, Ins[i].OrigArgIndex - CurArgIdx); 2636 CurArgIdx = Ins[i].OrigArgIndex; 2637 EVT ValVT = VA.getValVT(); 2638 ISD::ArgFlagsTy Flags = Ins[i].Flags; 2639 bool IsRegLoc = VA.isRegLoc(); 2640 2641 if (Flags.isByVal()) { 2642 assert(Flags.getByValSize() && 2643 "ByVal args of size 0 should have been ignored by front-end."); 2644 assert(ByValArg != MipsCCInfo.byval_end()); 2645 copyByValRegs(Chain, DL, OutChains, DAG, Flags, InVals, &*FuncArg, 2646 MipsCCInfo, *ByValArg); 2647 ++ByValArg; 2648 continue; 2649 } 2650 2651 // Arguments stored on registers 2652 if (IsRegLoc) { 2653 MVT RegVT = VA.getLocVT(); 2654 unsigned ArgReg = VA.getLocReg(); 2655 const TargetRegisterClass *RC = getRegClassFor(RegVT); 2656 2657 // Transform the arguments stored on 2658 // physical registers into virtual ones 2659 unsigned Reg = addLiveIn(DAG.getMachineFunction(), ArgReg, RC); 2660 SDValue ArgValue = DAG.getCopyFromReg(Chain, DL, Reg, RegVT); 2661 2662 // If this is an 8 or 16-bit value, it has been passed promoted 2663 // to 32 bits. Insert an assert[sz]ext to capture this, then 2664 // truncate to the right size. 2665 if (VA.getLocInfo() != CCValAssign::Full) { 2666 unsigned Opcode = 0; 2667 if (VA.getLocInfo() == CCValAssign::SExt) 2668 Opcode = ISD::AssertSext; 2669 else if (VA.getLocInfo() == CCValAssign::ZExt) 2670 Opcode = ISD::AssertZext; 2671 if (Opcode) 2672 ArgValue = DAG.getNode(Opcode, DL, RegVT, ArgValue, 2673 DAG.getValueType(ValVT)); 2674 ArgValue = DAG.getNode(ISD::TRUNCATE, DL, ValVT, ArgValue); 2675 } 2676 2677 // Handle floating point arguments passed in integer registers and 2678 // long double arguments passed in floating point registers. 2679 if ((RegVT == MVT::i32 && ValVT == MVT::f32) || 2680 (RegVT == MVT::i64 && ValVT == MVT::f64) || 2681 (RegVT == MVT::f64 && ValVT == MVT::i64)) 2682 ArgValue = DAG.getNode(ISD::BITCAST, DL, ValVT, ArgValue); 2683 else if (IsO32 && RegVT == MVT::i32 && ValVT == MVT::f64) { 2684 unsigned Reg2 = addLiveIn(DAG.getMachineFunction(), 2685 getNextIntArgReg(ArgReg), RC); 2686 SDValue ArgValue2 = DAG.getCopyFromReg(Chain, DL, Reg2, RegVT); 2687 if (!Subtarget->isLittle()) 2688 std::swap(ArgValue, ArgValue2); 2689 ArgValue = DAG.getNode(MipsISD::BuildPairF64, DL, MVT::f64, 2690 ArgValue, ArgValue2); 2691 } 2692 2693 InVals.push_back(ArgValue); 2694 } else { // VA.isRegLoc() 2695 2696 // sanity check 2697 assert(VA.isMemLoc()); 2698 2699 // The stack pointer offset is relative to the caller stack frame. 2700 int FI = MFI->CreateFixedObject(ValVT.getSizeInBits()/8, 2701 VA.getLocMemOffset(), true); 2702 2703 // Create load nodes to retrieve arguments from the stack 2704 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy()); 2705 SDValue Load = DAG.getLoad(ValVT, DL, Chain, FIN, 2706 MachinePointerInfo::getFixedStack(FI), 2707 false, false, false, 0); 2708 InVals.push_back(Load); 2709 OutChains.push_back(Load.getValue(1)); 2710 } 2711 } 2712 2713 // The mips ABIs for returning structs by value requires that we copy 2714 // the sret argument into $v0 for the return. Save the argument into 2715 // a virtual register so that we can access it from the return points. 2716 if (DAG.getMachineFunction().getFunction()->hasStructRetAttr()) { 2717 unsigned Reg = MipsFI->getSRetReturnReg(); 2718 if (!Reg) { 2719 Reg = MF.getRegInfo(). 2720 createVirtualRegister(getRegClassFor(IsN64 ? MVT::i64 : MVT::i32)); 2721 MipsFI->setSRetReturnReg(Reg); 2722 } 2723 SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), DL, Reg, InVals[0]); 2724 Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, Copy, Chain); 2725 } 2726 2727 if (IsVarArg) 2728 writeVarArgRegs(OutChains, MipsCCInfo, Chain, DL, DAG); 2729 2730 // All stores are grouped in one node to allow the matching between 2731 // the size of Ins and InVals. This only happens when on varg functions 2732 if (!OutChains.empty()) { 2733 OutChains.push_back(Chain); 2734 Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, 2735 &OutChains[0], OutChains.size()); 2736 } 2737 2738 return Chain; 2739 } 2740 2741 //===----------------------------------------------------------------------===// 2742 // Return Value Calling Convention Implementation 2743 //===----------------------------------------------------------------------===// 2744 2745 bool 2746 MipsTargetLowering::CanLowerReturn(CallingConv::ID CallConv, 2747 MachineFunction &MF, bool IsVarArg, 2748 const SmallVectorImpl<ISD::OutputArg> &Outs, 2749 LLVMContext &Context) const { 2750 SmallVector<CCValAssign, 16> RVLocs; 2751 CCState CCInfo(CallConv, IsVarArg, MF, getTargetMachine(), 2752 RVLocs, Context); 2753 return CCInfo.CheckReturn(Outs, RetCC_Mips); 2754 } 2755 2756 SDValue 2757 MipsTargetLowering::LowerReturn(SDValue Chain, 2758 CallingConv::ID CallConv, bool IsVarArg, 2759 const SmallVectorImpl<ISD::OutputArg> &Outs, 2760 const SmallVectorImpl<SDValue> &OutVals, 2761 SDLoc DL, SelectionDAG &DAG) const { 2762 // CCValAssign - represent the assignment of 2763 // the return value to a location 2764 SmallVector<CCValAssign, 16> RVLocs; 2765 MachineFunction &MF = DAG.getMachineFunction(); 2766 2767 // CCState - Info about the registers and stack slot. 2768 CCState CCInfo(CallConv, IsVarArg, MF, getTargetMachine(), RVLocs, 2769 *DAG.getContext()); 2770 MipsCC MipsCCInfo(CallConv, IsO32, Subtarget->isFP64bit(), CCInfo); 2771 2772 // Analyze return values. 2773 MipsCCInfo.analyzeReturn(Outs, Subtarget->mipsSEUsesSoftFloat(), 2774 MF.getFunction()->getReturnType()); 2775 2776 SDValue Flag; 2777 SmallVector<SDValue, 4> RetOps(1, Chain); 2778 2779 // Copy the result values into the output registers. 2780 for (unsigned i = 0; i != RVLocs.size(); ++i) { 2781 SDValue Val = OutVals[i]; 2782 CCValAssign &VA = RVLocs[i]; 2783 assert(VA.isRegLoc() && "Can only return in registers!"); 2784 2785 if (RVLocs[i].getValVT() != RVLocs[i].getLocVT()) 2786 Val = DAG.getNode(ISD::BITCAST, DL, RVLocs[i].getLocVT(), Val); 2787 2788 Chain = DAG.getCopyToReg(Chain, DL, VA.getLocReg(), Val, Flag); 2789 2790 // Guarantee that all emitted copies are stuck together with flags. 2791 Flag = Chain.getValue(1); 2792 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT())); 2793 } 2794 2795 // The mips ABIs for returning structs by value requires that we copy 2796 // the sret argument into $v0 for the return. We saved the argument into 2797 // a virtual register in the entry block, so now we copy the value out 2798 // and into $v0. 2799 if (MF.getFunction()->hasStructRetAttr()) { 2800 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>(); 2801 unsigned Reg = MipsFI->getSRetReturnReg(); 2802 2803 if (!Reg) 2804 llvm_unreachable("sret virtual register not created in the entry block"); 2805 SDValue Val = DAG.getCopyFromReg(Chain, DL, Reg, getPointerTy()); 2806 unsigned V0 = IsN64 ? Mips::V0_64 : Mips::V0; 2807 2808 Chain = DAG.getCopyToReg(Chain, DL, V0, Val, Flag); 2809 Flag = Chain.getValue(1); 2810 RetOps.push_back(DAG.getRegister(V0, getPointerTy())); 2811 } 2812 2813 RetOps[0] = Chain; // Update chain. 2814 2815 // Add the flag if we have it. 2816 if (Flag.getNode()) 2817 RetOps.push_back(Flag); 2818 2819 // Return on Mips is always a "jr $ra" 2820 return DAG.getNode(MipsISD::Ret, DL, MVT::Other, &RetOps[0], RetOps.size()); 2821 } 2822 2823 //===----------------------------------------------------------------------===// 2824 // Mips Inline Assembly Support 2825 //===----------------------------------------------------------------------===// 2826 2827 /// getConstraintType - Given a constraint letter, return the type of 2828 /// constraint it is for this target. 2829 MipsTargetLowering::ConstraintType MipsTargetLowering:: 2830 getConstraintType(const std::string &Constraint) const 2831 { 2832 // Mips specific constraints 2833 // GCC config/mips/constraints.md 2834 // 2835 // 'd' : An address register. Equivalent to r 2836 // unless generating MIPS16 code. 2837 // 'y' : Equivalent to r; retained for 2838 // backwards compatibility. 2839 // 'c' : A register suitable for use in an indirect 2840 // jump. This will always be $25 for -mabicalls. 2841 // 'l' : The lo register. 1 word storage. 2842 // 'x' : The hilo register pair. Double word storage. 2843 if (Constraint.size() == 1) { 2844 switch (Constraint[0]) { 2845 default : break; 2846 case 'd': 2847 case 'y': 2848 case 'f': 2849 case 'c': 2850 case 'l': 2851 case 'x': 2852 return C_RegisterClass; 2853 case 'R': 2854 return C_Memory; 2855 } 2856 } 2857 return TargetLowering::getConstraintType(Constraint); 2858 } 2859 2860 /// Examine constraint type and operand type and determine a weight value. 2861 /// This object must already have been set up with the operand type 2862 /// and the current alternative constraint selected. 2863 TargetLowering::ConstraintWeight 2864 MipsTargetLowering::getSingleConstraintMatchWeight( 2865 AsmOperandInfo &info, const char *constraint) const { 2866 ConstraintWeight weight = CW_Invalid; 2867 Value *CallOperandVal = info.CallOperandVal; 2868 // If we don't have a value, we can't do a match, 2869 // but allow it at the lowest weight. 2870 if (CallOperandVal == NULL) 2871 return CW_Default; 2872 Type *type = CallOperandVal->getType(); 2873 // Look at the constraint type. 2874 switch (*constraint) { 2875 default: 2876 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint); 2877 break; 2878 case 'd': 2879 case 'y': 2880 if (type->isIntegerTy()) 2881 weight = CW_Register; 2882 break; 2883 case 'f': // FPU or MSA register 2884 if (Subtarget->hasMSA() && type->isVectorTy() && 2885 cast<VectorType>(type)->getBitWidth() == 128) 2886 weight = CW_Register; 2887 else if (type->isFloatTy()) 2888 weight = CW_Register; 2889 break; 2890 case 'c': // $25 for indirect jumps 2891 case 'l': // lo register 2892 case 'x': // hilo register pair 2893 if (type->isIntegerTy()) 2894 weight = CW_SpecificReg; 2895 break; 2896 case 'I': // signed 16 bit immediate 2897 case 'J': // integer zero 2898 case 'K': // unsigned 16 bit immediate 2899 case 'L': // signed 32 bit immediate where lower 16 bits are 0 2900 case 'N': // immediate in the range of -65535 to -1 (inclusive) 2901 case 'O': // signed 15 bit immediate (+- 16383) 2902 case 'P': // immediate in the range of 65535 to 1 (inclusive) 2903 if (isa<ConstantInt>(CallOperandVal)) 2904 weight = CW_Constant; 2905 break; 2906 case 'R': 2907 weight = CW_Memory; 2908 break; 2909 } 2910 return weight; 2911 } 2912 2913 /// This is a helper function to parse a physical register string and split it 2914 /// into non-numeric and numeric parts (Prefix and Reg). The first boolean flag 2915 /// that is returned indicates whether parsing was successful. The second flag 2916 /// is true if the numeric part exists. 2917 static std::pair<bool, bool> 2918 parsePhysicalReg(const StringRef &C, std::string &Prefix, 2919 unsigned long long &Reg) { 2920 if (C.front() != '{' || C.back() != '}') 2921 return std::make_pair(false, false); 2922 2923 // Search for the first numeric character. 2924 StringRef::const_iterator I, B = C.begin() + 1, E = C.end() - 1; 2925 I = std::find_if(B, E, std::ptr_fun(isdigit)); 2926 2927 Prefix.assign(B, I - B); 2928 2929 // The second flag is set to false if no numeric characters were found. 2930 if (I == E) 2931 return std::make_pair(true, false); 2932 2933 // Parse the numeric characters. 2934 return std::make_pair(!getAsUnsignedInteger(StringRef(I, E - I), 10, Reg), 2935 true); 2936 } 2937 2938 std::pair<unsigned, const TargetRegisterClass *> MipsTargetLowering:: 2939 parseRegForInlineAsmConstraint(const StringRef &C, MVT VT) const { 2940 const TargetRegisterInfo *TRI = getTargetMachine().getRegisterInfo(); 2941 const TargetRegisterClass *RC; 2942 std::string Prefix; 2943 unsigned long long Reg; 2944 2945 std::pair<bool, bool> R = parsePhysicalReg(C, Prefix, Reg); 2946 2947 if (!R.first) 2948 return std::make_pair((unsigned)0, (const TargetRegisterClass*)0); 2949 2950 if ((Prefix == "hi" || Prefix == "lo")) { // Parse hi/lo. 2951 // No numeric characters follow "hi" or "lo". 2952 if (R.second) 2953 return std::make_pair((unsigned)0, (const TargetRegisterClass*)0); 2954 2955 RC = TRI->getRegClass(Prefix == "hi" ? 2956 Mips::HI32RegClassID : Mips::LO32RegClassID); 2957 return std::make_pair(*(RC->begin()), RC); 2958 } else if (Prefix.compare(0, 4, "$msa") == 0) { 2959 // Parse $msa(ir|csr|access|save|modify|request|map|unmap) 2960 2961 // No numeric characters follow the name. 2962 if (R.second) 2963 return std::make_pair((unsigned)0, (const TargetRegisterClass *)0); 2964 2965 Reg = StringSwitch<unsigned long long>(Prefix) 2966 .Case("$msair", Mips::MSAIR) 2967 .Case("$msacsr", Mips::MSACSR) 2968 .Case("$msaaccess", Mips::MSAAccess) 2969 .Case("$msasave", Mips::MSASave) 2970 .Case("$msamodify", Mips::MSAModify) 2971 .Case("$msarequest", Mips::MSARequest) 2972 .Case("$msamap", Mips::MSAMap) 2973 .Case("$msaunmap", Mips::MSAUnmap) 2974 .Default(0); 2975 2976 if (!Reg) 2977 return std::make_pair((unsigned)0, (const TargetRegisterClass *)0); 2978 2979 RC = TRI->getRegClass(Mips::MSACtrlRegClassID); 2980 return std::make_pair(Reg, RC); 2981 } 2982 2983 if (!R.second) 2984 return std::make_pair((unsigned)0, (const TargetRegisterClass*)0); 2985 2986 if (Prefix == "$f") { // Parse $f0-$f31. 2987 // If the size of FP registers is 64-bit or Reg is an even number, select 2988 // the 64-bit register class. Otherwise, select the 32-bit register class. 2989 if (VT == MVT::Other) 2990 VT = (Subtarget->isFP64bit() || !(Reg % 2)) ? MVT::f64 : MVT::f32; 2991 2992 RC = getRegClassFor(VT); 2993 2994 if (RC == &Mips::AFGR64RegClass) { 2995 assert(Reg % 2 == 0); 2996 Reg >>= 1; 2997 } 2998 } else if (Prefix == "$fcc") // Parse $fcc0-$fcc7. 2999 RC = TRI->getRegClass(Mips::FCCRegClassID); 3000 else if (Prefix == "$w") { // Parse $w0-$w31. 3001 RC = getRegClassFor((VT == MVT::Other) ? MVT::v16i8 : VT); 3002 } else { // Parse $0-$31. 3003 assert(Prefix == "$"); 3004 RC = getRegClassFor((VT == MVT::Other) ? MVT::i32 : VT); 3005 } 3006 3007 assert(Reg < RC->getNumRegs()); 3008 return std::make_pair(*(RC->begin() + Reg), RC); 3009 } 3010 3011 /// Given a register class constraint, like 'r', if this corresponds directly 3012 /// to an LLVM register class, return a register of 0 and the register class 3013 /// pointer. 3014 std::pair<unsigned, const TargetRegisterClass*> MipsTargetLowering:: 3015 getRegForInlineAsmConstraint(const std::string &Constraint, MVT VT) const 3016 { 3017 if (Constraint.size() == 1) { 3018 switch (Constraint[0]) { 3019 case 'd': // Address register. Same as 'r' unless generating MIPS16 code. 3020 case 'y': // Same as 'r'. Exists for compatibility. 3021 case 'r': 3022 if (VT == MVT::i32 || VT == MVT::i16 || VT == MVT::i8) { 3023 if (Subtarget->inMips16Mode()) 3024 return std::make_pair(0U, &Mips::CPU16RegsRegClass); 3025 return std::make_pair(0U, &Mips::GPR32RegClass); 3026 } 3027 if (VT == MVT::i64 && !HasMips64) 3028 return std::make_pair(0U, &Mips::GPR32RegClass); 3029 if (VT == MVT::i64 && HasMips64) 3030 return std::make_pair(0U, &Mips::GPR64RegClass); 3031 // This will generate an error message 3032 return std::make_pair(0u, static_cast<const TargetRegisterClass*>(0)); 3033 case 'f': // FPU or MSA register 3034 if (VT == MVT::v16i8) 3035 return std::make_pair(0U, &Mips::MSA128BRegClass); 3036 else if (VT == MVT::v8i16 || VT == MVT::v8f16) 3037 return std::make_pair(0U, &Mips::MSA128HRegClass); 3038 else if (VT == MVT::v4i32 || VT == MVT::v4f32) 3039 return std::make_pair(0U, &Mips::MSA128WRegClass); 3040 else if (VT == MVT::v2i64 || VT == MVT::v2f64) 3041 return std::make_pair(0U, &Mips::MSA128DRegClass); 3042 else if (VT == MVT::f32) 3043 return std::make_pair(0U, &Mips::FGR32RegClass); 3044 else if ((VT == MVT::f64) && (!Subtarget->isSingleFloat())) { 3045 if (Subtarget->isFP64bit()) 3046 return std::make_pair(0U, &Mips::FGR64RegClass); 3047 return std::make_pair(0U, &Mips::AFGR64RegClass); 3048 } 3049 break; 3050 case 'c': // register suitable for indirect jump 3051 if (VT == MVT::i32) 3052 return std::make_pair((unsigned)Mips::T9, &Mips::GPR32RegClass); 3053 assert(VT == MVT::i64 && "Unexpected type."); 3054 return std::make_pair((unsigned)Mips::T9_64, &Mips::GPR64RegClass); 3055 case 'l': // register suitable for indirect jump 3056 if (VT == MVT::i32) 3057 return std::make_pair((unsigned)Mips::LO0, &Mips::LO32RegClass); 3058 return std::make_pair((unsigned)Mips::LO0_64, &Mips::LO64RegClass); 3059 case 'x': // register suitable for indirect jump 3060 // Fixme: Not triggering the use of both hi and low 3061 // This will generate an error message 3062 return std::make_pair(0u, static_cast<const TargetRegisterClass*>(0)); 3063 } 3064 } 3065 3066 std::pair<unsigned, const TargetRegisterClass *> R; 3067 R = parseRegForInlineAsmConstraint(Constraint, VT); 3068 3069 if (R.second) 3070 return R; 3071 3072 return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT); 3073 } 3074 3075 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops 3076 /// vector. If it is invalid, don't add anything to Ops. 3077 void MipsTargetLowering::LowerAsmOperandForConstraint(SDValue Op, 3078 std::string &Constraint, 3079 std::vector<SDValue>&Ops, 3080 SelectionDAG &DAG) const { 3081 SDValue Result(0, 0); 3082 3083 // Only support length 1 constraints for now. 3084 if (Constraint.length() > 1) return; 3085 3086 char ConstraintLetter = Constraint[0]; 3087 switch (ConstraintLetter) { 3088 default: break; // This will fall through to the generic implementation 3089 case 'I': // Signed 16 bit constant 3090 // If this fails, the parent routine will give an error 3091 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 3092 EVT Type = Op.getValueType(); 3093 int64_t Val = C->getSExtValue(); 3094 if (isInt<16>(Val)) { 3095 Result = DAG.getTargetConstant(Val, Type); 3096 break; 3097 } 3098 } 3099 return; 3100 case 'J': // integer zero 3101 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 3102 EVT Type = Op.getValueType(); 3103 int64_t Val = C->getZExtValue(); 3104 if (Val == 0) { 3105 Result = DAG.getTargetConstant(0, Type); 3106 break; 3107 } 3108 } 3109 return; 3110 case 'K': // unsigned 16 bit immediate 3111 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 3112 EVT Type = Op.getValueType(); 3113 uint64_t Val = (uint64_t)C->getZExtValue(); 3114 if (isUInt<16>(Val)) { 3115 Result = DAG.getTargetConstant(Val, Type); 3116 break; 3117 } 3118 } 3119 return; 3120 case 'L': // signed 32 bit immediate where lower 16 bits are 0 3121 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 3122 EVT Type = Op.getValueType(); 3123 int64_t Val = C->getSExtValue(); 3124 if ((isInt<32>(Val)) && ((Val & 0xffff) == 0)){ 3125 Result = DAG.getTargetConstant(Val, Type); 3126 break; 3127 } 3128 } 3129 return; 3130 case 'N': // immediate in the range of -65535 to -1 (inclusive) 3131 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 3132 EVT Type = Op.getValueType(); 3133 int64_t Val = C->getSExtValue(); 3134 if ((Val >= -65535) && (Val <= -1)) { 3135 Result = DAG.getTargetConstant(Val, Type); 3136 break; 3137 } 3138 } 3139 return; 3140 case 'O': // signed 15 bit immediate 3141 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 3142 EVT Type = Op.getValueType(); 3143 int64_t Val = C->getSExtValue(); 3144 if ((isInt<15>(Val))) { 3145 Result = DAG.getTargetConstant(Val, Type); 3146 break; 3147 } 3148 } 3149 return; 3150 case 'P': // immediate in the range of 1 to 65535 (inclusive) 3151 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 3152 EVT Type = Op.getValueType(); 3153 int64_t Val = C->getSExtValue(); 3154 if ((Val <= 65535) && (Val >= 1)) { 3155 Result = DAG.getTargetConstant(Val, Type); 3156 break; 3157 } 3158 } 3159 return; 3160 } 3161 3162 if (Result.getNode()) { 3163 Ops.push_back(Result); 3164 return; 3165 } 3166 3167 TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG); 3168 } 3169 3170 bool MipsTargetLowering::isLegalAddressingMode(const AddrMode &AM, 3171 Type *Ty) const { 3172 // No global is ever allowed as a base. 3173 if (AM.BaseGV) 3174 return false; 3175 3176 switch (AM.Scale) { 3177 case 0: // "r+i" or just "i", depending on HasBaseReg. 3178 break; 3179 case 1: 3180 if (!AM.HasBaseReg) // allow "r+i". 3181 break; 3182 return false; // disallow "r+r" or "r+r+i". 3183 default: 3184 return false; 3185 } 3186 3187 return true; 3188 } 3189 3190 bool 3191 MipsTargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const { 3192 // The Mips target isn't yet aware of offsets. 3193 return false; 3194 } 3195 3196 EVT MipsTargetLowering::getOptimalMemOpType(uint64_t Size, unsigned DstAlign, 3197 unsigned SrcAlign, 3198 bool IsMemset, bool ZeroMemset, 3199 bool MemcpyStrSrc, 3200 MachineFunction &MF) const { 3201 if (Subtarget->hasMips64()) 3202 return MVT::i64; 3203 3204 return MVT::i32; 3205 } 3206 3207 bool MipsTargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const { 3208 if (VT != MVT::f32 && VT != MVT::f64) 3209 return false; 3210 if (Imm.isNegZero()) 3211 return false; 3212 return Imm.isZero(); 3213 } 3214 3215 unsigned MipsTargetLowering::getJumpTableEncoding() const { 3216 if (IsN64) 3217 return MachineJumpTableInfo::EK_GPRel64BlockAddress; 3218 3219 return TargetLowering::getJumpTableEncoding(); 3220 } 3221 3222 /// This function returns true if CallSym is a long double emulation routine. 3223 static bool isF128SoftLibCall(const char *CallSym) { 3224 const char *const LibCalls[] = 3225 {"__addtf3", "__divtf3", "__eqtf2", "__extenddftf2", "__extendsftf2", 3226 "__fixtfdi", "__fixtfsi", "__fixtfti", "__fixunstfdi", "__fixunstfsi", 3227 "__fixunstfti", "__floatditf", "__floatsitf", "__floattitf", 3228 "__floatunditf", "__floatunsitf", "__floatuntitf", "__getf2", "__gttf2", 3229 "__letf2", "__lttf2", "__multf3", "__netf2", "__powitf2", "__subtf3", 3230 "__trunctfdf2", "__trunctfsf2", "__unordtf2", 3231 "ceill", "copysignl", "cosl", "exp2l", "expl", "floorl", "fmal", "fmodl", 3232 "log10l", "log2l", "logl", "nearbyintl", "powl", "rintl", "sinl", "sqrtl", 3233 "truncl"}; 3234 3235 const char *const *End = LibCalls + array_lengthof(LibCalls); 3236 3237 // Check that LibCalls is sorted alphabetically. 3238 MipsTargetLowering::LTStr Comp; 3239 3240 #ifndef NDEBUG 3241 for (const char *const *I = LibCalls; I < End - 1; ++I) 3242 assert(Comp(*I, *(I + 1))); 3243 #endif 3244 3245 return std::binary_search(LibCalls, End, CallSym, Comp); 3246 } 3247 3248 /// This function returns true if Ty is fp128 or i128 which was originally a 3249 /// fp128. 3250 static bool originalTypeIsF128(const Type *Ty, const SDNode *CallNode) { 3251 if (Ty->isFP128Ty()) 3252 return true; 3253 3254 const ExternalSymbolSDNode *ES = 3255 dyn_cast_or_null<const ExternalSymbolSDNode>(CallNode); 3256 3257 // If the Ty is i128 and the function being called is a long double emulation 3258 // routine, then the original type is f128. 3259 return (ES && Ty->isIntegerTy(128) && isF128SoftLibCall(ES->getSymbol())); 3260 } 3261 3262 MipsTargetLowering::MipsCC::SpecialCallingConvType 3263 MipsTargetLowering::getSpecialCallingConv(SDValue Callee) const { 3264 MipsCC::SpecialCallingConvType SpecialCallingConv = 3265 MipsCC::NoSpecialCallingConv;; 3266 if (Subtarget->inMips16HardFloat()) { 3267 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) { 3268 llvm::StringRef Sym = G->getGlobal()->getName(); 3269 Function *F = G->getGlobal()->getParent()->getFunction(Sym); 3270 if (F && F->hasFnAttribute("__Mips16RetHelper")) { 3271 SpecialCallingConv = MipsCC::Mips16RetHelperConv; 3272 } 3273 } 3274 } 3275 return SpecialCallingConv; 3276 } 3277 3278 MipsTargetLowering::MipsCC::MipsCC( 3279 CallingConv::ID CC, bool IsO32_, bool IsFP64_, CCState &Info, 3280 MipsCC::SpecialCallingConvType SpecialCallingConv_) 3281 : CCInfo(Info), CallConv(CC), IsO32(IsO32_), IsFP64(IsFP64_), 3282 SpecialCallingConv(SpecialCallingConv_){ 3283 // Pre-allocate reserved argument area. 3284 CCInfo.AllocateStack(reservedArgArea(), 1); 3285 } 3286 3287 3288 void MipsTargetLowering::MipsCC:: 3289 analyzeCallOperands(const SmallVectorImpl<ISD::OutputArg> &Args, 3290 bool IsVarArg, bool IsSoftFloat, const SDNode *CallNode, 3291 std::vector<ArgListEntry> &FuncArgs) { 3292 assert((CallConv != CallingConv::Fast || !IsVarArg) && 3293 "CallingConv::Fast shouldn't be used for vararg functions."); 3294 3295 unsigned NumOpnds = Args.size(); 3296 llvm::CCAssignFn *FixedFn = fixedArgFn(), *VarFn = varArgFn(); 3297 3298 for (unsigned I = 0; I != NumOpnds; ++I) { 3299 MVT ArgVT = Args[I].VT; 3300 ISD::ArgFlagsTy ArgFlags = Args[I].Flags; 3301 bool R; 3302 3303 if (ArgFlags.isByVal()) { 3304 handleByValArg(I, ArgVT, ArgVT, CCValAssign::Full, ArgFlags); 3305 continue; 3306 } 3307 3308 if (IsVarArg && !Args[I].IsFixed) 3309 R = VarFn(I, ArgVT, ArgVT, CCValAssign::Full, ArgFlags, CCInfo); 3310 else { 3311 MVT RegVT = getRegVT(ArgVT, FuncArgs[Args[I].OrigArgIndex].Ty, CallNode, 3312 IsSoftFloat); 3313 R = FixedFn(I, ArgVT, RegVT, CCValAssign::Full, ArgFlags, CCInfo); 3314 } 3315 3316 if (R) { 3317 #ifndef NDEBUG 3318 dbgs() << "Call operand #" << I << " has unhandled type " 3319 << EVT(ArgVT).getEVTString(); 3320 #endif 3321 llvm_unreachable(0); 3322 } 3323 } 3324 } 3325 3326 void MipsTargetLowering::MipsCC:: 3327 analyzeFormalArguments(const SmallVectorImpl<ISD::InputArg> &Args, 3328 bool IsSoftFloat, Function::const_arg_iterator FuncArg) { 3329 unsigned NumArgs = Args.size(); 3330 llvm::CCAssignFn *FixedFn = fixedArgFn(); 3331 unsigned CurArgIdx = 0; 3332 3333 for (unsigned I = 0; I != NumArgs; ++I) { 3334 MVT ArgVT = Args[I].VT; 3335 ISD::ArgFlagsTy ArgFlags = Args[I].Flags; 3336 std::advance(FuncArg, Args[I].OrigArgIndex - CurArgIdx); 3337 CurArgIdx = Args[I].OrigArgIndex; 3338 3339 if (ArgFlags.isByVal()) { 3340 handleByValArg(I, ArgVT, ArgVT, CCValAssign::Full, ArgFlags); 3341 continue; 3342 } 3343 3344 MVT RegVT = getRegVT(ArgVT, FuncArg->getType(), 0, IsSoftFloat); 3345 3346 if (!FixedFn(I, ArgVT, RegVT, CCValAssign::Full, ArgFlags, CCInfo)) 3347 continue; 3348 3349 #ifndef NDEBUG 3350 dbgs() << "Formal Arg #" << I << " has unhandled type " 3351 << EVT(ArgVT).getEVTString(); 3352 #endif 3353 llvm_unreachable(0); 3354 } 3355 } 3356 3357 template<typename Ty> 3358 void MipsTargetLowering::MipsCC:: 3359 analyzeReturn(const SmallVectorImpl<Ty> &RetVals, bool IsSoftFloat, 3360 const SDNode *CallNode, const Type *RetTy) const { 3361 CCAssignFn *Fn; 3362 3363 if (IsSoftFloat && originalTypeIsF128(RetTy, CallNode)) 3364 Fn = RetCC_F128Soft; 3365 else 3366 Fn = RetCC_Mips; 3367 3368 for (unsigned I = 0, E = RetVals.size(); I < E; ++I) { 3369 MVT VT = RetVals[I].VT; 3370 ISD::ArgFlagsTy Flags = RetVals[I].Flags; 3371 MVT RegVT = this->getRegVT(VT, RetTy, CallNode, IsSoftFloat); 3372 3373 if (Fn(I, VT, RegVT, CCValAssign::Full, Flags, this->CCInfo)) { 3374 #ifndef NDEBUG 3375 dbgs() << "Call result #" << I << " has unhandled type " 3376 << EVT(VT).getEVTString() << '\n'; 3377 #endif 3378 llvm_unreachable(0); 3379 } 3380 } 3381 } 3382 3383 void MipsTargetLowering::MipsCC:: 3384 analyzeCallResult(const SmallVectorImpl<ISD::InputArg> &Ins, bool IsSoftFloat, 3385 const SDNode *CallNode, const Type *RetTy) const { 3386 analyzeReturn(Ins, IsSoftFloat, CallNode, RetTy); 3387 } 3388 3389 void MipsTargetLowering::MipsCC:: 3390 analyzeReturn(const SmallVectorImpl<ISD::OutputArg> &Outs, bool IsSoftFloat, 3391 const Type *RetTy) const { 3392 analyzeReturn(Outs, IsSoftFloat, 0, RetTy); 3393 } 3394 3395 void MipsTargetLowering::MipsCC::handleByValArg(unsigned ValNo, MVT ValVT, 3396 MVT LocVT, 3397 CCValAssign::LocInfo LocInfo, 3398 ISD::ArgFlagsTy ArgFlags) { 3399 assert(ArgFlags.getByValSize() && "Byval argument's size shouldn't be 0."); 3400 3401 struct ByValArgInfo ByVal; 3402 unsigned RegSize = regSize(); 3403 unsigned ByValSize = RoundUpToAlignment(ArgFlags.getByValSize(), RegSize); 3404 unsigned Align = std::min(std::max(ArgFlags.getByValAlign(), RegSize), 3405 RegSize * 2); 3406 3407 if (useRegsForByval()) 3408 allocateRegs(ByVal, ByValSize, Align); 3409 3410 // Allocate space on caller's stack. 3411 ByVal.Address = CCInfo.AllocateStack(ByValSize - RegSize * ByVal.NumRegs, 3412 Align); 3413 CCInfo.addLoc(CCValAssign::getMem(ValNo, ValVT, ByVal.Address, LocVT, 3414 LocInfo)); 3415 ByValArgs.push_back(ByVal); 3416 } 3417 3418 unsigned MipsTargetLowering::MipsCC::numIntArgRegs() const { 3419 return IsO32 ? array_lengthof(O32IntRegs) : array_lengthof(Mips64IntRegs); 3420 } 3421 3422 unsigned MipsTargetLowering::MipsCC::reservedArgArea() const { 3423 return (IsO32 && (CallConv != CallingConv::Fast)) ? 16 : 0; 3424 } 3425 3426 const uint16_t *MipsTargetLowering::MipsCC::intArgRegs() const { 3427 return IsO32 ? O32IntRegs : Mips64IntRegs; 3428 } 3429 3430 llvm::CCAssignFn *MipsTargetLowering::MipsCC::fixedArgFn() const { 3431 if (CallConv == CallingConv::Fast) 3432 return CC_Mips_FastCC; 3433 3434 if (SpecialCallingConv == Mips16RetHelperConv) 3435 return CC_Mips16RetHelper; 3436 return IsO32 ? (IsFP64 ? CC_MipsO32_FP64 : CC_MipsO32_FP32) : CC_MipsN; 3437 } 3438 3439 llvm::CCAssignFn *MipsTargetLowering::MipsCC::varArgFn() const { 3440 return IsO32 ? (IsFP64 ? CC_MipsO32_FP64 : CC_MipsO32_FP32) : CC_MipsN_VarArg; 3441 } 3442 3443 const uint16_t *MipsTargetLowering::MipsCC::shadowRegs() const { 3444 return IsO32 ? O32IntRegs : Mips64DPRegs; 3445 } 3446 3447 void MipsTargetLowering::MipsCC::allocateRegs(ByValArgInfo &ByVal, 3448 unsigned ByValSize, 3449 unsigned Align) { 3450 unsigned RegSize = regSize(), NumIntArgRegs = numIntArgRegs(); 3451 const uint16_t *IntArgRegs = intArgRegs(), *ShadowRegs = shadowRegs(); 3452 assert(!(ByValSize % RegSize) && !(Align % RegSize) && 3453 "Byval argument's size and alignment should be a multiple of" 3454 "RegSize."); 3455 3456 ByVal.FirstIdx = CCInfo.getFirstUnallocated(IntArgRegs, NumIntArgRegs); 3457 3458 // If Align > RegSize, the first arg register must be even. 3459 if ((Align > RegSize) && (ByVal.FirstIdx % 2)) { 3460 CCInfo.AllocateReg(IntArgRegs[ByVal.FirstIdx], ShadowRegs[ByVal.FirstIdx]); 3461 ++ByVal.FirstIdx; 3462 } 3463 3464 // Mark the registers allocated. 3465 for (unsigned I = ByVal.FirstIdx; ByValSize && (I < NumIntArgRegs); 3466 ByValSize -= RegSize, ++I, ++ByVal.NumRegs) 3467 CCInfo.AllocateReg(IntArgRegs[I], ShadowRegs[I]); 3468 } 3469 3470 MVT MipsTargetLowering::MipsCC::getRegVT(MVT VT, const Type *OrigTy, 3471 const SDNode *CallNode, 3472 bool IsSoftFloat) const { 3473 if (IsSoftFloat || IsO32) 3474 return VT; 3475 3476 // Check if the original type was fp128. 3477 if (originalTypeIsF128(OrigTy, CallNode)) { 3478 assert(VT == MVT::i64); 3479 return MVT::f64; 3480 } 3481 3482 return VT; 3483 } 3484 3485 void MipsTargetLowering:: 3486 copyByValRegs(SDValue Chain, SDLoc DL, std::vector<SDValue> &OutChains, 3487 SelectionDAG &DAG, const ISD::ArgFlagsTy &Flags, 3488 SmallVectorImpl<SDValue> &InVals, const Argument *FuncArg, 3489 const MipsCC &CC, const ByValArgInfo &ByVal) const { 3490 MachineFunction &MF = DAG.getMachineFunction(); 3491 MachineFrameInfo *MFI = MF.getFrameInfo(); 3492 unsigned RegAreaSize = ByVal.NumRegs * CC.regSize(); 3493 unsigned FrameObjSize = std::max(Flags.getByValSize(), RegAreaSize); 3494 int FrameObjOffset; 3495 3496 if (RegAreaSize) 3497 FrameObjOffset = (int)CC.reservedArgArea() - 3498 (int)((CC.numIntArgRegs() - ByVal.FirstIdx) * CC.regSize()); 3499 else 3500 FrameObjOffset = ByVal.Address; 3501 3502 // Create frame object. 3503 EVT PtrTy = getPointerTy(); 3504 int FI = MFI->CreateFixedObject(FrameObjSize, FrameObjOffset, true); 3505 SDValue FIN = DAG.getFrameIndex(FI, PtrTy); 3506 InVals.push_back(FIN); 3507 3508 if (!ByVal.NumRegs) 3509 return; 3510 3511 // Copy arg registers. 3512 MVT RegTy = MVT::getIntegerVT(CC.regSize() * 8); 3513 const TargetRegisterClass *RC = getRegClassFor(RegTy); 3514 3515 for (unsigned I = 0; I < ByVal.NumRegs; ++I) { 3516 unsigned ArgReg = CC.intArgRegs()[ByVal.FirstIdx + I]; 3517 unsigned VReg = addLiveIn(MF, ArgReg, RC); 3518 unsigned Offset = I * CC.regSize(); 3519 SDValue StorePtr = DAG.getNode(ISD::ADD, DL, PtrTy, FIN, 3520 DAG.getConstant(Offset, PtrTy)); 3521 SDValue Store = DAG.getStore(Chain, DL, DAG.getRegister(VReg, RegTy), 3522 StorePtr, MachinePointerInfo(FuncArg, Offset), 3523 false, false, 0); 3524 OutChains.push_back(Store); 3525 } 3526 } 3527 3528 // Copy byVal arg to registers and stack. 3529 void MipsTargetLowering:: 3530 passByValArg(SDValue Chain, SDLoc DL, 3531 std::deque< std::pair<unsigned, SDValue> > &RegsToPass, 3532 SmallVectorImpl<SDValue> &MemOpChains, SDValue StackPtr, 3533 MachineFrameInfo *MFI, SelectionDAG &DAG, SDValue Arg, 3534 const MipsCC &CC, const ByValArgInfo &ByVal, 3535 const ISD::ArgFlagsTy &Flags, bool isLittle) const { 3536 unsigned ByValSize = Flags.getByValSize(); 3537 unsigned Offset = 0; // Offset in # of bytes from the beginning of struct. 3538 unsigned RegSize = CC.regSize(); 3539 unsigned Alignment = std::min(Flags.getByValAlign(), RegSize); 3540 EVT PtrTy = getPointerTy(), RegTy = MVT::getIntegerVT(RegSize * 8); 3541 3542 if (ByVal.NumRegs) { 3543 const uint16_t *ArgRegs = CC.intArgRegs(); 3544 bool LeftoverBytes = (ByVal.NumRegs * RegSize > ByValSize); 3545 unsigned I = 0; 3546 3547 // Copy words to registers. 3548 for (; I < ByVal.NumRegs - LeftoverBytes; ++I, Offset += RegSize) { 3549 SDValue LoadPtr = DAG.getNode(ISD::ADD, DL, PtrTy, Arg, 3550 DAG.getConstant(Offset, PtrTy)); 3551 SDValue LoadVal = DAG.getLoad(RegTy, DL, Chain, LoadPtr, 3552 MachinePointerInfo(), false, false, false, 3553 Alignment); 3554 MemOpChains.push_back(LoadVal.getValue(1)); 3555 unsigned ArgReg = ArgRegs[ByVal.FirstIdx + I]; 3556 RegsToPass.push_back(std::make_pair(ArgReg, LoadVal)); 3557 } 3558 3559 // Return if the struct has been fully copied. 3560 if (ByValSize == Offset) 3561 return; 3562 3563 // Copy the remainder of the byval argument with sub-word loads and shifts. 3564 if (LeftoverBytes) { 3565 assert((ByValSize > Offset) && (ByValSize < Offset + RegSize) && 3566 "Size of the remainder should be smaller than RegSize."); 3567 SDValue Val; 3568 3569 for (unsigned LoadSize = RegSize / 2, TotalSizeLoaded = 0; 3570 Offset < ByValSize; LoadSize /= 2) { 3571 unsigned RemSize = ByValSize - Offset; 3572 3573 if (RemSize < LoadSize) 3574 continue; 3575 3576 // Load subword. 3577 SDValue LoadPtr = DAG.getNode(ISD::ADD, DL, PtrTy, Arg, 3578 DAG.getConstant(Offset, PtrTy)); 3579 SDValue LoadVal = 3580 DAG.getExtLoad(ISD::ZEXTLOAD, DL, RegTy, Chain, LoadPtr, 3581 MachinePointerInfo(), MVT::getIntegerVT(LoadSize * 8), 3582 false, false, Alignment); 3583 MemOpChains.push_back(LoadVal.getValue(1)); 3584 3585 // Shift the loaded value. 3586 unsigned Shamt; 3587 3588 if (isLittle) 3589 Shamt = TotalSizeLoaded; 3590 else 3591 Shamt = (RegSize - (TotalSizeLoaded + LoadSize)) * 8; 3592 3593 SDValue Shift = DAG.getNode(ISD::SHL, DL, RegTy, LoadVal, 3594 DAG.getConstant(Shamt, MVT::i32)); 3595 3596 if (Val.getNode()) 3597 Val = DAG.getNode(ISD::OR, DL, RegTy, Val, Shift); 3598 else 3599 Val = Shift; 3600 3601 Offset += LoadSize; 3602 TotalSizeLoaded += LoadSize; 3603 Alignment = std::min(Alignment, LoadSize); 3604 } 3605 3606 unsigned ArgReg = ArgRegs[ByVal.FirstIdx + I]; 3607 RegsToPass.push_back(std::make_pair(ArgReg, Val)); 3608 return; 3609 } 3610 } 3611 3612 // Copy remainder of byval arg to it with memcpy. 3613 unsigned MemCpySize = ByValSize - Offset; 3614 SDValue Src = DAG.getNode(ISD::ADD, DL, PtrTy, Arg, 3615 DAG.getConstant(Offset, PtrTy)); 3616 SDValue Dst = DAG.getNode(ISD::ADD, DL, PtrTy, StackPtr, 3617 DAG.getIntPtrConstant(ByVal.Address)); 3618 Chain = DAG.getMemcpy(Chain, DL, Dst, Src, DAG.getConstant(MemCpySize, PtrTy), 3619 Alignment, /*isVolatile=*/false, /*AlwaysInline=*/false, 3620 MachinePointerInfo(0), MachinePointerInfo(0)); 3621 MemOpChains.push_back(Chain); 3622 } 3623 3624 void MipsTargetLowering::writeVarArgRegs(std::vector<SDValue> &OutChains, 3625 const MipsCC &CC, SDValue Chain, 3626 SDLoc DL, SelectionDAG &DAG) const { 3627 unsigned NumRegs = CC.numIntArgRegs(); 3628 const uint16_t *ArgRegs = CC.intArgRegs(); 3629 const CCState &CCInfo = CC.getCCInfo(); 3630 unsigned Idx = CCInfo.getFirstUnallocated(ArgRegs, NumRegs); 3631 unsigned RegSize = CC.regSize(); 3632 MVT RegTy = MVT::getIntegerVT(RegSize * 8); 3633 const TargetRegisterClass *RC = getRegClassFor(RegTy); 3634 MachineFunction &MF = DAG.getMachineFunction(); 3635 MachineFrameInfo *MFI = MF.getFrameInfo(); 3636 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>(); 3637 3638 // Offset of the first variable argument from stack pointer. 3639 int VaArgOffset; 3640 3641 if (NumRegs == Idx) 3642 VaArgOffset = RoundUpToAlignment(CCInfo.getNextStackOffset(), RegSize); 3643 else 3644 VaArgOffset = (int)CC.reservedArgArea() - (int)(RegSize * (NumRegs - Idx)); 3645 3646 // Record the frame index of the first variable argument 3647 // which is a value necessary to VASTART. 3648 int FI = MFI->CreateFixedObject(RegSize, VaArgOffset, true); 3649 MipsFI->setVarArgsFrameIndex(FI); 3650 3651 // Copy the integer registers that have not been used for argument passing 3652 // to the argument register save area. For O32, the save area is allocated 3653 // in the caller's stack frame, while for N32/64, it is allocated in the 3654 // callee's stack frame. 3655 for (unsigned I = Idx; I < NumRegs; ++I, VaArgOffset += RegSize) { 3656 unsigned Reg = addLiveIn(MF, ArgRegs[I], RC); 3657 SDValue ArgValue = DAG.getCopyFromReg(Chain, DL, Reg, RegTy); 3658 FI = MFI->CreateFixedObject(RegSize, VaArgOffset, true); 3659 SDValue PtrOff = DAG.getFrameIndex(FI, getPointerTy()); 3660 SDValue Store = DAG.getStore(Chain, DL, ArgValue, PtrOff, 3661 MachinePointerInfo(), false, false, 0); 3662 cast<StoreSDNode>(Store.getNode())->getMemOperand()->setValue(0); 3663 OutChains.push_back(Store); 3664 } 3665 } 3666