1 //===- MipsISelLowering.cpp - Mips DAG Lowering Implementation ------------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file defines the interfaces that Mips uses to lower LLVM code into a 11 // selection DAG. 12 // 13 //===----------------------------------------------------------------------===// 14 15 #include "MipsISelLowering.h" 16 #include "InstPrinter/MipsInstPrinter.h" 17 #include "MCTargetDesc/MipsBaseInfo.h" 18 #include "MCTargetDesc/MipsMCTargetDesc.h" 19 #include "MipsCCState.h" 20 #include "MipsInstrInfo.h" 21 #include "MipsMachineFunction.h" 22 #include "MipsRegisterInfo.h" 23 #include "MipsSubtarget.h" 24 #include "MipsTargetMachine.h" 25 #include "MipsTargetObjectFile.h" 26 #include "llvm/ADT/APFloat.h" 27 #include "llvm/ADT/ArrayRef.h" 28 #include "llvm/ADT/SmallVector.h" 29 #include "llvm/ADT/Statistic.h" 30 #include "llvm/ADT/StringRef.h" 31 #include "llvm/ADT/StringSwitch.h" 32 #include "llvm/CodeGen/CallingConvLower.h" 33 #include "llvm/CodeGen/FunctionLoweringInfo.h" 34 #include "llvm/CodeGen/ISDOpcodes.h" 35 #include "llvm/CodeGen/MachineBasicBlock.h" 36 #include "llvm/CodeGen/MachineFrameInfo.h" 37 #include "llvm/CodeGen/MachineFunction.h" 38 #include "llvm/CodeGen/MachineInstr.h" 39 #include "llvm/CodeGen/MachineInstrBuilder.h" 40 #include "llvm/CodeGen/MachineJumpTableInfo.h" 41 #include "llvm/CodeGen/MachineMemOperand.h" 42 #include "llvm/CodeGen/MachineOperand.h" 43 #include "llvm/CodeGen/MachineRegisterInfo.h" 44 #include "llvm/CodeGen/MachineValueType.h" 45 #include "llvm/CodeGen/RuntimeLibcalls.h" 46 #include "llvm/CodeGen/SelectionDAG.h" 47 #include "llvm/CodeGen/SelectionDAGNodes.h" 48 #include "llvm/CodeGen/TargetFrameLowering.h" 49 #include "llvm/CodeGen/TargetInstrInfo.h" 50 #include "llvm/CodeGen/TargetRegisterInfo.h" 51 #include "llvm/CodeGen/ValueTypes.h" 52 #include "llvm/IR/CallingConv.h" 53 #include "llvm/IR/Constants.h" 54 #include "llvm/IR/DataLayout.h" 55 #include "llvm/IR/DebugLoc.h" 56 #include "llvm/IR/DerivedTypes.h" 57 #include "llvm/IR/Function.h" 58 #include "llvm/IR/GlobalValue.h" 59 #include "llvm/IR/Type.h" 60 #include "llvm/IR/Value.h" 61 #include "llvm/MC/MCRegisterInfo.h" 62 #include "llvm/Support/Casting.h" 63 #include "llvm/Support/CodeGen.h" 64 #include "llvm/Support/CommandLine.h" 65 #include "llvm/Support/Compiler.h" 66 #include "llvm/Support/ErrorHandling.h" 67 #include "llvm/Support/MathExtras.h" 68 #include "llvm/Target/TargetMachine.h" 69 #include "llvm/Target/TargetOptions.h" 70 #include <algorithm> 71 #include <cassert> 72 #include <cctype> 73 #include <cstdint> 74 #include <deque> 75 #include <iterator> 76 #include <utility> 77 #include <vector> 78 79 using namespace llvm; 80 81 #define DEBUG_TYPE "mips-lower" 82 83 STATISTIC(NumTailCalls, "Number of tail calls"); 84 85 static cl::opt<bool> 86 LargeGOT("mxgot", cl::Hidden, 87 cl::desc("MIPS: Enable GOT larger than 64k."), cl::init(false)); 88 89 static cl::opt<bool> 90 NoZeroDivCheck("mno-check-zero-division", cl::Hidden, 91 cl::desc("MIPS: Don't trap on integer division by zero."), 92 cl::init(false)); 93 94 static const MCPhysReg Mips64DPRegs[8] = { 95 Mips::D12_64, Mips::D13_64, Mips::D14_64, Mips::D15_64, 96 Mips::D16_64, Mips::D17_64, Mips::D18_64, Mips::D19_64 97 }; 98 99 // If I is a shifted mask, set the size (Size) and the first bit of the 100 // mask (Pos), and return true. 101 // For example, if I is 0x003ff800, (Pos, Size) = (11, 11). 102 static bool isShiftedMask(uint64_t I, uint64_t &Pos, uint64_t &Size) { 103 if (!isShiftedMask_64(I)) 104 return false; 105 106 Size = countPopulation(I); 107 Pos = countTrailingZeros(I); 108 return true; 109 } 110 111 // The MIPS MSA ABI passes vector arguments in the integer register set. 112 // The number of integer registers used is dependant on the ABI used. 113 MVT MipsTargetLowering::getRegisterTypeForCallingConv(MVT VT) const { 114 if (VT.isVector() && Subtarget.hasMSA()) 115 return Subtarget.isABI_O32() ? MVT::i32 : MVT::i64; 116 return MipsTargetLowering::getRegisterType(VT); 117 } 118 119 MVT MipsTargetLowering::getRegisterTypeForCallingConv(LLVMContext &Context, 120 EVT VT) const { 121 if (VT.isVector()) { 122 if (Subtarget.isABI_O32()) { 123 return MVT::i32; 124 } else { 125 return (VT.getSizeInBits() == 32) ? MVT::i32 : MVT::i64; 126 } 127 } 128 return MipsTargetLowering::getRegisterType(Context, VT); 129 } 130 131 unsigned MipsTargetLowering::getNumRegistersForCallingConv(LLVMContext &Context, 132 EVT VT) const { 133 if (VT.isVector()) 134 return std::max((VT.getSizeInBits() / (Subtarget.isABI_O32() ? 32 : 64)), 135 1U); 136 return MipsTargetLowering::getNumRegisters(Context, VT); 137 } 138 139 unsigned MipsTargetLowering::getVectorTypeBreakdownForCallingConv( 140 LLVMContext &Context, EVT VT, EVT &IntermediateVT, 141 unsigned &NumIntermediates, MVT &RegisterVT) const { 142 // Break down vector types to either 2 i64s or 4 i32s. 143 RegisterVT = getRegisterTypeForCallingConv(Context, VT) ; 144 IntermediateVT = RegisterVT; 145 NumIntermediates = VT.getSizeInBits() < RegisterVT.getSizeInBits() 146 ? VT.getVectorNumElements() 147 : VT.getSizeInBits() / RegisterVT.getSizeInBits(); 148 149 return NumIntermediates; 150 } 151 152 SDValue MipsTargetLowering::getGlobalReg(SelectionDAG &DAG, EVT Ty) const { 153 MipsFunctionInfo *FI = DAG.getMachineFunction().getInfo<MipsFunctionInfo>(); 154 return DAG.getRegister(FI->getGlobalBaseReg(), Ty); 155 } 156 157 SDValue MipsTargetLowering::getTargetNode(GlobalAddressSDNode *N, EVT Ty, 158 SelectionDAG &DAG, 159 unsigned Flag) const { 160 return DAG.getTargetGlobalAddress(N->getGlobal(), SDLoc(N), Ty, 0, Flag); 161 } 162 163 SDValue MipsTargetLowering::getTargetNode(ExternalSymbolSDNode *N, EVT Ty, 164 SelectionDAG &DAG, 165 unsigned Flag) const { 166 return DAG.getTargetExternalSymbol(N->getSymbol(), Ty, Flag); 167 } 168 169 SDValue MipsTargetLowering::getTargetNode(BlockAddressSDNode *N, EVT Ty, 170 SelectionDAG &DAG, 171 unsigned Flag) const { 172 return DAG.getTargetBlockAddress(N->getBlockAddress(), Ty, 0, Flag); 173 } 174 175 SDValue MipsTargetLowering::getTargetNode(JumpTableSDNode *N, EVT Ty, 176 SelectionDAG &DAG, 177 unsigned Flag) const { 178 return DAG.getTargetJumpTable(N->getIndex(), Ty, Flag); 179 } 180 181 SDValue MipsTargetLowering::getTargetNode(ConstantPoolSDNode *N, EVT Ty, 182 SelectionDAG &DAG, 183 unsigned Flag) const { 184 return DAG.getTargetConstantPool(N->getConstVal(), Ty, N->getAlignment(), 185 N->getOffset(), Flag); 186 } 187 188 const char *MipsTargetLowering::getTargetNodeName(unsigned Opcode) const { 189 switch ((MipsISD::NodeType)Opcode) { 190 case MipsISD::FIRST_NUMBER: break; 191 case MipsISD::JmpLink: return "MipsISD::JmpLink"; 192 case MipsISD::TailCall: return "MipsISD::TailCall"; 193 case MipsISD::Highest: return "MipsISD::Highest"; 194 case MipsISD::Higher: return "MipsISD::Higher"; 195 case MipsISD::Hi: return "MipsISD::Hi"; 196 case MipsISD::Lo: return "MipsISD::Lo"; 197 case MipsISD::GotHi: return "MipsISD::GotHi"; 198 case MipsISD::GPRel: return "MipsISD::GPRel"; 199 case MipsISD::ThreadPointer: return "MipsISD::ThreadPointer"; 200 case MipsISD::Ret: return "MipsISD::Ret"; 201 case MipsISD::ERet: return "MipsISD::ERet"; 202 case MipsISD::EH_RETURN: return "MipsISD::EH_RETURN"; 203 case MipsISD::FPBrcond: return "MipsISD::FPBrcond"; 204 case MipsISD::FPCmp: return "MipsISD::FPCmp"; 205 case MipsISD::FSELECT: return "MipsISD::FSELECT"; 206 case MipsISD::MTC1_D64: return "MipsISD::MTC1_D64"; 207 case MipsISD::CMovFP_T: return "MipsISD::CMovFP_T"; 208 case MipsISD::CMovFP_F: return "MipsISD::CMovFP_F"; 209 case MipsISD::TruncIntFP: return "MipsISD::TruncIntFP"; 210 case MipsISD::MFHI: return "MipsISD::MFHI"; 211 case MipsISD::MFLO: return "MipsISD::MFLO"; 212 case MipsISD::MTLOHI: return "MipsISD::MTLOHI"; 213 case MipsISD::Mult: return "MipsISD::Mult"; 214 case MipsISD::Multu: return "MipsISD::Multu"; 215 case MipsISD::MAdd: return "MipsISD::MAdd"; 216 case MipsISD::MAddu: return "MipsISD::MAddu"; 217 case MipsISD::MSub: return "MipsISD::MSub"; 218 case MipsISD::MSubu: return "MipsISD::MSubu"; 219 case MipsISD::DivRem: return "MipsISD::DivRem"; 220 case MipsISD::DivRemU: return "MipsISD::DivRemU"; 221 case MipsISD::DivRem16: return "MipsISD::DivRem16"; 222 case MipsISD::DivRemU16: return "MipsISD::DivRemU16"; 223 case MipsISD::BuildPairF64: return "MipsISD::BuildPairF64"; 224 case MipsISD::ExtractElementF64: return "MipsISD::ExtractElementF64"; 225 case MipsISD::Wrapper: return "MipsISD::Wrapper"; 226 case MipsISD::DynAlloc: return "MipsISD::DynAlloc"; 227 case MipsISD::Sync: return "MipsISD::Sync"; 228 case MipsISD::Ext: return "MipsISD::Ext"; 229 case MipsISD::Ins: return "MipsISD::Ins"; 230 case MipsISD::CIns: return "MipsISD::CIns"; 231 case MipsISD::LWL: return "MipsISD::LWL"; 232 case MipsISD::LWR: return "MipsISD::LWR"; 233 case MipsISD::SWL: return "MipsISD::SWL"; 234 case MipsISD::SWR: return "MipsISD::SWR"; 235 case MipsISD::LDL: return "MipsISD::LDL"; 236 case MipsISD::LDR: return "MipsISD::LDR"; 237 case MipsISD::SDL: return "MipsISD::SDL"; 238 case MipsISD::SDR: return "MipsISD::SDR"; 239 case MipsISD::EXTP: return "MipsISD::EXTP"; 240 case MipsISD::EXTPDP: return "MipsISD::EXTPDP"; 241 case MipsISD::EXTR_S_H: return "MipsISD::EXTR_S_H"; 242 case MipsISD::EXTR_W: return "MipsISD::EXTR_W"; 243 case MipsISD::EXTR_R_W: return "MipsISD::EXTR_R_W"; 244 case MipsISD::EXTR_RS_W: return "MipsISD::EXTR_RS_W"; 245 case MipsISD::SHILO: return "MipsISD::SHILO"; 246 case MipsISD::MTHLIP: return "MipsISD::MTHLIP"; 247 case MipsISD::MULSAQ_S_W_PH: return "MipsISD::MULSAQ_S_W_PH"; 248 case MipsISD::MAQ_S_W_PHL: return "MipsISD::MAQ_S_W_PHL"; 249 case MipsISD::MAQ_S_W_PHR: return "MipsISD::MAQ_S_W_PHR"; 250 case MipsISD::MAQ_SA_W_PHL: return "MipsISD::MAQ_SA_W_PHL"; 251 case MipsISD::MAQ_SA_W_PHR: return "MipsISD::MAQ_SA_W_PHR"; 252 case MipsISD::DPAU_H_QBL: return "MipsISD::DPAU_H_QBL"; 253 case MipsISD::DPAU_H_QBR: return "MipsISD::DPAU_H_QBR"; 254 case MipsISD::DPSU_H_QBL: return "MipsISD::DPSU_H_QBL"; 255 case MipsISD::DPSU_H_QBR: return "MipsISD::DPSU_H_QBR"; 256 case MipsISD::DPAQ_S_W_PH: return "MipsISD::DPAQ_S_W_PH"; 257 case MipsISD::DPSQ_S_W_PH: return "MipsISD::DPSQ_S_W_PH"; 258 case MipsISD::DPAQ_SA_L_W: return "MipsISD::DPAQ_SA_L_W"; 259 case MipsISD::DPSQ_SA_L_W: return "MipsISD::DPSQ_SA_L_W"; 260 case MipsISD::DPA_W_PH: return "MipsISD::DPA_W_PH"; 261 case MipsISD::DPS_W_PH: return "MipsISD::DPS_W_PH"; 262 case MipsISD::DPAQX_S_W_PH: return "MipsISD::DPAQX_S_W_PH"; 263 case MipsISD::DPAQX_SA_W_PH: return "MipsISD::DPAQX_SA_W_PH"; 264 case MipsISD::DPAX_W_PH: return "MipsISD::DPAX_W_PH"; 265 case MipsISD::DPSX_W_PH: return "MipsISD::DPSX_W_PH"; 266 case MipsISD::DPSQX_S_W_PH: return "MipsISD::DPSQX_S_W_PH"; 267 case MipsISD::DPSQX_SA_W_PH: return "MipsISD::DPSQX_SA_W_PH"; 268 case MipsISD::MULSA_W_PH: return "MipsISD::MULSA_W_PH"; 269 case MipsISD::MULT: return "MipsISD::MULT"; 270 case MipsISD::MULTU: return "MipsISD::MULTU"; 271 case MipsISD::MADD_DSP: return "MipsISD::MADD_DSP"; 272 case MipsISD::MADDU_DSP: return "MipsISD::MADDU_DSP"; 273 case MipsISD::MSUB_DSP: return "MipsISD::MSUB_DSP"; 274 case MipsISD::MSUBU_DSP: return "MipsISD::MSUBU_DSP"; 275 case MipsISD::SHLL_DSP: return "MipsISD::SHLL_DSP"; 276 case MipsISD::SHRA_DSP: return "MipsISD::SHRA_DSP"; 277 case MipsISD::SHRL_DSP: return "MipsISD::SHRL_DSP"; 278 case MipsISD::SETCC_DSP: return "MipsISD::SETCC_DSP"; 279 case MipsISD::SELECT_CC_DSP: return "MipsISD::SELECT_CC_DSP"; 280 case MipsISD::VALL_ZERO: return "MipsISD::VALL_ZERO"; 281 case MipsISD::VANY_ZERO: return "MipsISD::VANY_ZERO"; 282 case MipsISD::VALL_NONZERO: return "MipsISD::VALL_NONZERO"; 283 case MipsISD::VANY_NONZERO: return "MipsISD::VANY_NONZERO"; 284 case MipsISD::VCEQ: return "MipsISD::VCEQ"; 285 case MipsISD::VCLE_S: return "MipsISD::VCLE_S"; 286 case MipsISD::VCLE_U: return "MipsISD::VCLE_U"; 287 case MipsISD::VCLT_S: return "MipsISD::VCLT_S"; 288 case MipsISD::VCLT_U: return "MipsISD::VCLT_U"; 289 case MipsISD::VSMAX: return "MipsISD::VSMAX"; 290 case MipsISD::VSMIN: return "MipsISD::VSMIN"; 291 case MipsISD::VUMAX: return "MipsISD::VUMAX"; 292 case MipsISD::VUMIN: return "MipsISD::VUMIN"; 293 case MipsISD::VEXTRACT_SEXT_ELT: return "MipsISD::VEXTRACT_SEXT_ELT"; 294 case MipsISD::VEXTRACT_ZEXT_ELT: return "MipsISD::VEXTRACT_ZEXT_ELT"; 295 case MipsISD::VNOR: return "MipsISD::VNOR"; 296 case MipsISD::VSHF: return "MipsISD::VSHF"; 297 case MipsISD::SHF: return "MipsISD::SHF"; 298 case MipsISD::ILVEV: return "MipsISD::ILVEV"; 299 case MipsISD::ILVOD: return "MipsISD::ILVOD"; 300 case MipsISD::ILVL: return "MipsISD::ILVL"; 301 case MipsISD::ILVR: return "MipsISD::ILVR"; 302 case MipsISD::PCKEV: return "MipsISD::PCKEV"; 303 case MipsISD::PCKOD: return "MipsISD::PCKOD"; 304 case MipsISD::INSVE: return "MipsISD::INSVE"; 305 } 306 return nullptr; 307 } 308 309 MipsTargetLowering::MipsTargetLowering(const MipsTargetMachine &TM, 310 const MipsSubtarget &STI) 311 : TargetLowering(TM), Subtarget(STI), ABI(TM.getABI()) { 312 // Mips does not have i1 type, so use i32 for 313 // setcc operations results (slt, sgt, ...). 314 setBooleanContents(ZeroOrOneBooleanContent); 315 setBooleanVectorContents(ZeroOrNegativeOneBooleanContent); 316 // The cmp.cond.fmt instruction in MIPS32r6/MIPS64r6 uses 0 and -1 like MSA 317 // does. Integer booleans still use 0 and 1. 318 if (Subtarget.hasMips32r6()) 319 setBooleanContents(ZeroOrOneBooleanContent, 320 ZeroOrNegativeOneBooleanContent); 321 322 // Load extented operations for i1 types must be promoted 323 for (MVT VT : MVT::integer_valuetypes()) { 324 setLoadExtAction(ISD::EXTLOAD, VT, MVT::i1, Promote); 325 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i1, Promote); 326 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i1, Promote); 327 } 328 329 // MIPS doesn't have extending float->double load/store. Set LoadExtAction 330 // for f32, f16 331 for (MVT VT : MVT::fp_valuetypes()) { 332 setLoadExtAction(ISD::EXTLOAD, VT, MVT::f32, Expand); 333 setLoadExtAction(ISD::EXTLOAD, VT, MVT::f16, Expand); 334 } 335 336 // Set LoadExtAction for f16 vectors to Expand 337 for (MVT VT : MVT::fp_vector_valuetypes()) { 338 MVT F16VT = MVT::getVectorVT(MVT::f16, VT.getVectorNumElements()); 339 if (F16VT.isValid()) 340 setLoadExtAction(ISD::EXTLOAD, VT, F16VT, Expand); 341 } 342 343 setTruncStoreAction(MVT::f32, MVT::f16, Expand); 344 setTruncStoreAction(MVT::f64, MVT::f16, Expand); 345 346 setTruncStoreAction(MVT::f64, MVT::f32, Expand); 347 348 // Used by legalize types to correctly generate the setcc result. 349 // Without this, every float setcc comes with a AND/OR with the result, 350 // we don't want this, since the fpcmp result goes to a flag register, 351 // which is used implicitly by brcond and select operations. 352 AddPromotedToType(ISD::SETCC, MVT::i1, MVT::i32); 353 354 // Mips Custom Operations 355 setOperationAction(ISD::BR_JT, MVT::Other, Expand); 356 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom); 357 setOperationAction(ISD::BlockAddress, MVT::i32, Custom); 358 setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom); 359 setOperationAction(ISD::JumpTable, MVT::i32, Custom); 360 setOperationAction(ISD::ConstantPool, MVT::i32, Custom); 361 setOperationAction(ISD::SELECT, MVT::f32, Custom); 362 setOperationAction(ISD::SELECT, MVT::f64, Custom); 363 setOperationAction(ISD::SELECT, MVT::i32, Custom); 364 setOperationAction(ISD::SETCC, MVT::f32, Custom); 365 setOperationAction(ISD::SETCC, MVT::f64, Custom); 366 setOperationAction(ISD::BRCOND, MVT::Other, Custom); 367 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom); 368 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom); 369 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom); 370 371 if (Subtarget.isGP64bit()) { 372 setOperationAction(ISD::GlobalAddress, MVT::i64, Custom); 373 setOperationAction(ISD::BlockAddress, MVT::i64, Custom); 374 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom); 375 setOperationAction(ISD::JumpTable, MVT::i64, Custom); 376 setOperationAction(ISD::ConstantPool, MVT::i64, Custom); 377 setOperationAction(ISD::SELECT, MVT::i64, Custom); 378 setOperationAction(ISD::LOAD, MVT::i64, Custom); 379 setOperationAction(ISD::STORE, MVT::i64, Custom); 380 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom); 381 setOperationAction(ISD::SHL_PARTS, MVT::i64, Custom); 382 setOperationAction(ISD::SRA_PARTS, MVT::i64, Custom); 383 setOperationAction(ISD::SRL_PARTS, MVT::i64, Custom); 384 } 385 386 if (!Subtarget.isGP64bit()) { 387 setOperationAction(ISD::SHL_PARTS, MVT::i32, Custom); 388 setOperationAction(ISD::SRA_PARTS, MVT::i32, Custom); 389 setOperationAction(ISD::SRL_PARTS, MVT::i32, Custom); 390 } 391 392 setOperationAction(ISD::EH_DWARF_CFA, MVT::i32, Custom); 393 if (Subtarget.isGP64bit()) 394 setOperationAction(ISD::EH_DWARF_CFA, MVT::i64, Custom); 395 396 setOperationAction(ISD::SDIV, MVT::i32, Expand); 397 setOperationAction(ISD::SREM, MVT::i32, Expand); 398 setOperationAction(ISD::UDIV, MVT::i32, Expand); 399 setOperationAction(ISD::UREM, MVT::i32, Expand); 400 setOperationAction(ISD::SDIV, MVT::i64, Expand); 401 setOperationAction(ISD::SREM, MVT::i64, Expand); 402 setOperationAction(ISD::UDIV, MVT::i64, Expand); 403 setOperationAction(ISD::UREM, MVT::i64, Expand); 404 405 if (!(Subtarget.hasDSP() && Subtarget.hasMips32r2())) { 406 setOperationAction(ISD::ADDC, MVT::i32, Expand); 407 setOperationAction(ISD::ADDE, MVT::i32, Expand); 408 } 409 410 setOperationAction(ISD::ADDC, MVT::i64, Expand); 411 setOperationAction(ISD::ADDE, MVT::i64, Expand); 412 setOperationAction(ISD::SUBC, MVT::i32, Expand); 413 setOperationAction(ISD::SUBE, MVT::i32, Expand); 414 setOperationAction(ISD::SUBC, MVT::i64, Expand); 415 setOperationAction(ISD::SUBE, MVT::i64, Expand); 416 417 // Operations not directly supported by Mips. 418 setOperationAction(ISD::BR_CC, MVT::f32, Expand); 419 setOperationAction(ISD::BR_CC, MVT::f64, Expand); 420 setOperationAction(ISD::BR_CC, MVT::i32, Expand); 421 setOperationAction(ISD::BR_CC, MVT::i64, Expand); 422 setOperationAction(ISD::SELECT_CC, MVT::i32, Expand); 423 setOperationAction(ISD::SELECT_CC, MVT::i64, Expand); 424 setOperationAction(ISD::SELECT_CC, MVT::f32, Expand); 425 setOperationAction(ISD::SELECT_CC, MVT::f64, Expand); 426 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand); 427 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Expand); 428 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand); 429 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Expand); 430 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand); 431 if (Subtarget.hasCnMips()) { 432 setOperationAction(ISD::CTPOP, MVT::i32, Legal); 433 setOperationAction(ISD::CTPOP, MVT::i64, Legal); 434 } else { 435 setOperationAction(ISD::CTPOP, MVT::i32, Expand); 436 setOperationAction(ISD::CTPOP, MVT::i64, Expand); 437 } 438 setOperationAction(ISD::CTTZ, MVT::i32, Expand); 439 setOperationAction(ISD::CTTZ, MVT::i64, Expand); 440 setOperationAction(ISD::ROTL, MVT::i32, Expand); 441 setOperationAction(ISD::ROTL, MVT::i64, Expand); 442 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Expand); 443 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64, Expand); 444 445 if (!Subtarget.hasMips32r2()) 446 setOperationAction(ISD::ROTR, MVT::i32, Expand); 447 448 if (!Subtarget.hasMips64r2()) 449 setOperationAction(ISD::ROTR, MVT::i64, Expand); 450 451 setOperationAction(ISD::FSIN, MVT::f32, Expand); 452 setOperationAction(ISD::FSIN, MVT::f64, Expand); 453 setOperationAction(ISD::FCOS, MVT::f32, Expand); 454 setOperationAction(ISD::FCOS, MVT::f64, Expand); 455 setOperationAction(ISD::FSINCOS, MVT::f32, Expand); 456 setOperationAction(ISD::FSINCOS, MVT::f64, Expand); 457 setOperationAction(ISD::FPOW, MVT::f32, Expand); 458 setOperationAction(ISD::FPOW, MVT::f64, Expand); 459 setOperationAction(ISD::FLOG, MVT::f32, Expand); 460 setOperationAction(ISD::FLOG2, MVT::f32, Expand); 461 setOperationAction(ISD::FLOG10, MVT::f32, Expand); 462 setOperationAction(ISD::FEXP, MVT::f32, Expand); 463 setOperationAction(ISD::FMA, MVT::f32, Expand); 464 setOperationAction(ISD::FMA, MVT::f64, Expand); 465 setOperationAction(ISD::FREM, MVT::f32, Expand); 466 setOperationAction(ISD::FREM, MVT::f64, Expand); 467 468 // Lower f16 conversion operations into library calls 469 setOperationAction(ISD::FP16_TO_FP, MVT::f32, Expand); 470 setOperationAction(ISD::FP_TO_FP16, MVT::f32, Expand); 471 setOperationAction(ISD::FP16_TO_FP, MVT::f64, Expand); 472 setOperationAction(ISD::FP_TO_FP16, MVT::f64, Expand); 473 474 setOperationAction(ISD::EH_RETURN, MVT::Other, Custom); 475 476 setOperationAction(ISD::VASTART, MVT::Other, Custom); 477 setOperationAction(ISD::VAARG, MVT::Other, Custom); 478 setOperationAction(ISD::VACOPY, MVT::Other, Expand); 479 setOperationAction(ISD::VAEND, MVT::Other, Expand); 480 481 // Use the default for now 482 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand); 483 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand); 484 485 if (!Subtarget.isGP64bit()) { 486 setOperationAction(ISD::ATOMIC_LOAD, MVT::i64, Expand); 487 setOperationAction(ISD::ATOMIC_STORE, MVT::i64, Expand); 488 } 489 490 if (!Subtarget.hasMips32r2()) { 491 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8, Expand); 492 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand); 493 } 494 495 // MIPS16 lacks MIPS32's clz and clo instructions. 496 if (!Subtarget.hasMips32() || Subtarget.inMips16Mode()) 497 setOperationAction(ISD::CTLZ, MVT::i32, Expand); 498 if (!Subtarget.hasMips64()) 499 setOperationAction(ISD::CTLZ, MVT::i64, Expand); 500 501 if (!Subtarget.hasMips32r2()) 502 setOperationAction(ISD::BSWAP, MVT::i32, Expand); 503 if (!Subtarget.hasMips64r2()) 504 setOperationAction(ISD::BSWAP, MVT::i64, Expand); 505 506 if (Subtarget.isGP64bit()) { 507 setLoadExtAction(ISD::SEXTLOAD, MVT::i64, MVT::i32, Custom); 508 setLoadExtAction(ISD::ZEXTLOAD, MVT::i64, MVT::i32, Custom); 509 setLoadExtAction(ISD::EXTLOAD, MVT::i64, MVT::i32, Custom); 510 setTruncStoreAction(MVT::i64, MVT::i32, Custom); 511 } 512 513 setOperationAction(ISD::TRAP, MVT::Other, Legal); 514 515 setTargetDAGCombine(ISD::SDIVREM); 516 setTargetDAGCombine(ISD::UDIVREM); 517 setTargetDAGCombine(ISD::SELECT); 518 setTargetDAGCombine(ISD::AND); 519 setTargetDAGCombine(ISD::OR); 520 setTargetDAGCombine(ISD::ADD); 521 setTargetDAGCombine(ISD::SUB); 522 setTargetDAGCombine(ISD::AssertZext); 523 setTargetDAGCombine(ISD::SHL); 524 525 if (ABI.IsO32()) { 526 // These libcalls are not available in 32-bit. 527 setLibcallName(RTLIB::SHL_I128, nullptr); 528 setLibcallName(RTLIB::SRL_I128, nullptr); 529 setLibcallName(RTLIB::SRA_I128, nullptr); 530 } 531 532 setMinFunctionAlignment(Subtarget.isGP64bit() ? 3 : 2); 533 534 // The arguments on the stack are defined in terms of 4-byte slots on O32 535 // and 8-byte slots on N32/N64. 536 setMinStackArgumentAlignment((ABI.IsN32() || ABI.IsN64()) ? 8 : 4); 537 538 setStackPointerRegisterToSaveRestore(ABI.IsN64() ? Mips::SP_64 : Mips::SP); 539 540 MaxStoresPerMemcpy = 16; 541 542 isMicroMips = Subtarget.inMicroMipsMode(); 543 } 544 545 const MipsTargetLowering *MipsTargetLowering::create(const MipsTargetMachine &TM, 546 const MipsSubtarget &STI) { 547 if (STI.inMips16Mode()) 548 return createMips16TargetLowering(TM, STI); 549 550 return createMipsSETargetLowering(TM, STI); 551 } 552 553 // Create a fast isel object. 554 FastISel * 555 MipsTargetLowering::createFastISel(FunctionLoweringInfo &funcInfo, 556 const TargetLibraryInfo *libInfo) const { 557 const MipsTargetMachine &TM = 558 static_cast<const MipsTargetMachine &>(funcInfo.MF->getTarget()); 559 560 // We support only the standard encoding [MIPS32,MIPS32R5] ISAs. 561 bool UseFastISel = TM.Options.EnableFastISel && Subtarget.hasMips32() && 562 !Subtarget.hasMips32r6() && !Subtarget.inMips16Mode() && 563 !Subtarget.inMicroMipsMode(); 564 565 // Disable if either of the following is true: 566 // We do not generate PIC, the ABI is not O32, LargeGOT is being used. 567 if (!TM.isPositionIndependent() || !TM.getABI().IsO32() || LargeGOT) 568 UseFastISel = false; 569 570 return UseFastISel ? Mips::createFastISel(funcInfo, libInfo) : nullptr; 571 } 572 573 EVT MipsTargetLowering::getSetCCResultType(const DataLayout &, LLVMContext &, 574 EVT VT) const { 575 if (!VT.isVector()) 576 return MVT::i32; 577 return VT.changeVectorElementTypeToInteger(); 578 } 579 580 static SDValue performDivRemCombine(SDNode *N, SelectionDAG &DAG, 581 TargetLowering::DAGCombinerInfo &DCI, 582 const MipsSubtarget &Subtarget) { 583 if (DCI.isBeforeLegalizeOps()) 584 return SDValue(); 585 586 EVT Ty = N->getValueType(0); 587 unsigned LO = (Ty == MVT::i32) ? Mips::LO0 : Mips::LO0_64; 588 unsigned HI = (Ty == MVT::i32) ? Mips::HI0 : Mips::HI0_64; 589 unsigned Opc = N->getOpcode() == ISD::SDIVREM ? MipsISD::DivRem16 : 590 MipsISD::DivRemU16; 591 SDLoc DL(N); 592 593 SDValue DivRem = DAG.getNode(Opc, DL, MVT::Glue, 594 N->getOperand(0), N->getOperand(1)); 595 SDValue InChain = DAG.getEntryNode(); 596 SDValue InGlue = DivRem; 597 598 // insert MFLO 599 if (N->hasAnyUseOfValue(0)) { 600 SDValue CopyFromLo = DAG.getCopyFromReg(InChain, DL, LO, Ty, 601 InGlue); 602 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), CopyFromLo); 603 InChain = CopyFromLo.getValue(1); 604 InGlue = CopyFromLo.getValue(2); 605 } 606 607 // insert MFHI 608 if (N->hasAnyUseOfValue(1)) { 609 SDValue CopyFromHi = DAG.getCopyFromReg(InChain, DL, 610 HI, Ty, InGlue); 611 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), CopyFromHi); 612 } 613 614 return SDValue(); 615 } 616 617 static Mips::CondCode condCodeToFCC(ISD::CondCode CC) { 618 switch (CC) { 619 default: llvm_unreachable("Unknown fp condition code!"); 620 case ISD::SETEQ: 621 case ISD::SETOEQ: return Mips::FCOND_OEQ; 622 case ISD::SETUNE: return Mips::FCOND_UNE; 623 case ISD::SETLT: 624 case ISD::SETOLT: return Mips::FCOND_OLT; 625 case ISD::SETGT: 626 case ISD::SETOGT: return Mips::FCOND_OGT; 627 case ISD::SETLE: 628 case ISD::SETOLE: return Mips::FCOND_OLE; 629 case ISD::SETGE: 630 case ISD::SETOGE: return Mips::FCOND_OGE; 631 case ISD::SETULT: return Mips::FCOND_ULT; 632 case ISD::SETULE: return Mips::FCOND_ULE; 633 case ISD::SETUGT: return Mips::FCOND_UGT; 634 case ISD::SETUGE: return Mips::FCOND_UGE; 635 case ISD::SETUO: return Mips::FCOND_UN; 636 case ISD::SETO: return Mips::FCOND_OR; 637 case ISD::SETNE: 638 case ISD::SETONE: return Mips::FCOND_ONE; 639 case ISD::SETUEQ: return Mips::FCOND_UEQ; 640 } 641 } 642 643 /// This function returns true if the floating point conditional branches and 644 /// conditional moves which use condition code CC should be inverted. 645 static bool invertFPCondCodeUser(Mips::CondCode CC) { 646 if (CC >= Mips::FCOND_F && CC <= Mips::FCOND_NGT) 647 return false; 648 649 assert((CC >= Mips::FCOND_T && CC <= Mips::FCOND_GT) && 650 "Illegal Condition Code"); 651 652 return true; 653 } 654 655 // Creates and returns an FPCmp node from a setcc node. 656 // Returns Op if setcc is not a floating point comparison. 657 static SDValue createFPCmp(SelectionDAG &DAG, const SDValue &Op) { 658 // must be a SETCC node 659 if (Op.getOpcode() != ISD::SETCC) 660 return Op; 661 662 SDValue LHS = Op.getOperand(0); 663 664 if (!LHS.getValueType().isFloatingPoint()) 665 return Op; 666 667 SDValue RHS = Op.getOperand(1); 668 SDLoc DL(Op); 669 670 // Assume the 3rd operand is a CondCodeSDNode. Add code to check the type of 671 // node if necessary. 672 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get(); 673 674 return DAG.getNode(MipsISD::FPCmp, DL, MVT::Glue, LHS, RHS, 675 DAG.getConstant(condCodeToFCC(CC), DL, MVT::i32)); 676 } 677 678 // Creates and returns a CMovFPT/F node. 679 static SDValue createCMovFP(SelectionDAG &DAG, SDValue Cond, SDValue True, 680 SDValue False, const SDLoc &DL) { 681 ConstantSDNode *CC = cast<ConstantSDNode>(Cond.getOperand(2)); 682 bool invert = invertFPCondCodeUser((Mips::CondCode)CC->getSExtValue()); 683 SDValue FCC0 = DAG.getRegister(Mips::FCC0, MVT::i32); 684 685 return DAG.getNode((invert ? MipsISD::CMovFP_F : MipsISD::CMovFP_T), DL, 686 True.getValueType(), True, FCC0, False, Cond); 687 } 688 689 static SDValue performSELECTCombine(SDNode *N, SelectionDAG &DAG, 690 TargetLowering::DAGCombinerInfo &DCI, 691 const MipsSubtarget &Subtarget) { 692 if (DCI.isBeforeLegalizeOps()) 693 return SDValue(); 694 695 SDValue SetCC = N->getOperand(0); 696 697 if ((SetCC.getOpcode() != ISD::SETCC) || 698 !SetCC.getOperand(0).getValueType().isInteger()) 699 return SDValue(); 700 701 SDValue False = N->getOperand(2); 702 EVT FalseTy = False.getValueType(); 703 704 if (!FalseTy.isInteger()) 705 return SDValue(); 706 707 ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(False); 708 709 // If the RHS (False) is 0, we swap the order of the operands 710 // of ISD::SELECT (obviously also inverting the condition) so that we can 711 // take advantage of conditional moves using the $0 register. 712 // Example: 713 // return (a != 0) ? x : 0; 714 // load $reg, x 715 // movz $reg, $0, a 716 if (!FalseC) 717 return SDValue(); 718 719 const SDLoc DL(N); 720 721 if (!FalseC->getZExtValue()) { 722 ISD::CondCode CC = cast<CondCodeSDNode>(SetCC.getOperand(2))->get(); 723 SDValue True = N->getOperand(1); 724 725 SetCC = DAG.getSetCC(DL, SetCC.getValueType(), SetCC.getOperand(0), 726 SetCC.getOperand(1), ISD::getSetCCInverse(CC, true)); 727 728 return DAG.getNode(ISD::SELECT, DL, FalseTy, SetCC, False, True); 729 } 730 731 // If both operands are integer constants there's a possibility that we 732 // can do some interesting optimizations. 733 SDValue True = N->getOperand(1); 734 ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(True); 735 736 if (!TrueC || !True.getValueType().isInteger()) 737 return SDValue(); 738 739 // We'll also ignore MVT::i64 operands as this optimizations proves 740 // to be ineffective because of the required sign extensions as the result 741 // of a SETCC operator is always MVT::i32 for non-vector types. 742 if (True.getValueType() == MVT::i64) 743 return SDValue(); 744 745 int64_t Diff = TrueC->getSExtValue() - FalseC->getSExtValue(); 746 747 // 1) (a < x) ? y : y-1 748 // slti $reg1, a, x 749 // addiu $reg2, $reg1, y-1 750 if (Diff == 1) 751 return DAG.getNode(ISD::ADD, DL, SetCC.getValueType(), SetCC, False); 752 753 // 2) (a < x) ? y-1 : y 754 // slti $reg1, a, x 755 // xor $reg1, $reg1, 1 756 // addiu $reg2, $reg1, y-1 757 if (Diff == -1) { 758 ISD::CondCode CC = cast<CondCodeSDNode>(SetCC.getOperand(2))->get(); 759 SetCC = DAG.getSetCC(DL, SetCC.getValueType(), SetCC.getOperand(0), 760 SetCC.getOperand(1), ISD::getSetCCInverse(CC, true)); 761 return DAG.getNode(ISD::ADD, DL, SetCC.getValueType(), SetCC, True); 762 } 763 764 // Couldn't optimize. 765 return SDValue(); 766 } 767 768 static SDValue performCMovFPCombine(SDNode *N, SelectionDAG &DAG, 769 TargetLowering::DAGCombinerInfo &DCI, 770 const MipsSubtarget &Subtarget) { 771 if (DCI.isBeforeLegalizeOps()) 772 return SDValue(); 773 774 SDValue ValueIfTrue = N->getOperand(0), ValueIfFalse = N->getOperand(2); 775 776 ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(ValueIfFalse); 777 if (!FalseC || FalseC->getZExtValue()) 778 return SDValue(); 779 780 // Since RHS (False) is 0, we swap the order of the True/False operands 781 // (obviously also inverting the condition) so that we can 782 // take advantage of conditional moves using the $0 register. 783 // Example: 784 // return (a != 0) ? x : 0; 785 // load $reg, x 786 // movz $reg, $0, a 787 unsigned Opc = (N->getOpcode() == MipsISD::CMovFP_T) ? MipsISD::CMovFP_F : 788 MipsISD::CMovFP_T; 789 790 SDValue FCC = N->getOperand(1), Glue = N->getOperand(3); 791 return DAG.getNode(Opc, SDLoc(N), ValueIfFalse.getValueType(), 792 ValueIfFalse, FCC, ValueIfTrue, Glue); 793 } 794 795 static SDValue performANDCombine(SDNode *N, SelectionDAG &DAG, 796 TargetLowering::DAGCombinerInfo &DCI, 797 const MipsSubtarget &Subtarget) { 798 if (DCI.isBeforeLegalizeOps() || !Subtarget.hasExtractInsert()) 799 return SDValue(); 800 801 SDValue FirstOperand = N->getOperand(0); 802 unsigned FirstOperandOpc = FirstOperand.getOpcode(); 803 SDValue Mask = N->getOperand(1); 804 EVT ValTy = N->getValueType(0); 805 SDLoc DL(N); 806 807 uint64_t Pos = 0, SMPos, SMSize; 808 ConstantSDNode *CN; 809 SDValue NewOperand; 810 unsigned Opc; 811 812 // Op's second operand must be a shifted mask. 813 if (!(CN = dyn_cast<ConstantSDNode>(Mask)) || 814 !isShiftedMask(CN->getZExtValue(), SMPos, SMSize)) 815 return SDValue(); 816 817 if (FirstOperandOpc == ISD::SRA || FirstOperandOpc == ISD::SRL) { 818 // Pattern match EXT. 819 // $dst = and ((sra or srl) $src , pos), (2**size - 1) 820 // => ext $dst, $src, pos, size 821 822 // The second operand of the shift must be an immediate. 823 if (!(CN = dyn_cast<ConstantSDNode>(FirstOperand.getOperand(1)))) 824 return SDValue(); 825 826 Pos = CN->getZExtValue(); 827 828 // Return if the shifted mask does not start at bit 0 or the sum of its size 829 // and Pos exceeds the word's size. 830 if (SMPos != 0 || Pos + SMSize > ValTy.getSizeInBits()) 831 return SDValue(); 832 833 Opc = MipsISD::Ext; 834 NewOperand = FirstOperand.getOperand(0); 835 } else if (FirstOperandOpc == ISD::SHL && Subtarget.hasCnMips()) { 836 // Pattern match CINS. 837 // $dst = and (shl $src , pos), mask 838 // => cins $dst, $src, pos, size 839 // mask is a shifted mask with consecutive 1's, pos = shift amount, 840 // size = population count. 841 842 // The second operand of the shift must be an immediate. 843 if (!(CN = dyn_cast<ConstantSDNode>(FirstOperand.getOperand(1)))) 844 return SDValue(); 845 846 Pos = CN->getZExtValue(); 847 848 if (SMPos != Pos || Pos >= ValTy.getSizeInBits() || SMSize >= 32 || 849 Pos + SMSize > ValTy.getSizeInBits()) 850 return SDValue(); 851 852 NewOperand = FirstOperand.getOperand(0); 853 // SMSize is 'location' (position) in this case, not size. 854 SMSize--; 855 Opc = MipsISD::CIns; 856 } else { 857 // Pattern match EXT. 858 // $dst = and $src, (2**size - 1) , if size > 16 859 // => ext $dst, $src, pos, size , pos = 0 860 861 // If the mask is <= 0xffff, andi can be used instead. 862 if (CN->getZExtValue() <= 0xffff) 863 return SDValue(); 864 865 // Return if the mask doesn't start at position 0. 866 if (SMPos) 867 return SDValue(); 868 869 Opc = MipsISD::Ext; 870 NewOperand = FirstOperand; 871 } 872 return DAG.getNode(Opc, DL, ValTy, NewOperand, 873 DAG.getConstant(Pos, DL, MVT::i32), 874 DAG.getConstant(SMSize, DL, MVT::i32)); 875 } 876 877 static SDValue performORCombine(SDNode *N, SelectionDAG &DAG, 878 TargetLowering::DAGCombinerInfo &DCI, 879 const MipsSubtarget &Subtarget) { 880 // Pattern match INS. 881 // $dst = or (and $src1 , mask0), (and (shl $src, pos), mask1), 882 // where mask1 = (2**size - 1) << pos, mask0 = ~mask1 883 // => ins $dst, $src, size, pos, $src1 884 if (DCI.isBeforeLegalizeOps() || !Subtarget.hasExtractInsert()) 885 return SDValue(); 886 887 SDValue And0 = N->getOperand(0), And1 = N->getOperand(1); 888 uint64_t SMPos0, SMSize0, SMPos1, SMSize1; 889 ConstantSDNode *CN, *CN1; 890 891 // See if Op's first operand matches (and $src1 , mask0). 892 if (And0.getOpcode() != ISD::AND) 893 return SDValue(); 894 895 if (!(CN = dyn_cast<ConstantSDNode>(And0.getOperand(1))) || 896 !isShiftedMask(~CN->getSExtValue(), SMPos0, SMSize0)) 897 return SDValue(); 898 899 // See if Op's second operand matches (and (shl $src, pos), mask1). 900 if (And1.getOpcode() == ISD::AND && 901 And1.getOperand(0).getOpcode() == ISD::SHL) { 902 903 if (!(CN = dyn_cast<ConstantSDNode>(And1.getOperand(1))) || 904 !isShiftedMask(CN->getZExtValue(), SMPos1, SMSize1)) 905 return SDValue(); 906 907 // The shift masks must have the same position and size. 908 if (SMPos0 != SMPos1 || SMSize0 != SMSize1) 909 return SDValue(); 910 911 SDValue Shl = And1.getOperand(0); 912 913 if (!(CN = dyn_cast<ConstantSDNode>(Shl.getOperand(1)))) 914 return SDValue(); 915 916 unsigned Shamt = CN->getZExtValue(); 917 918 // Return if the shift amount and the first bit position of mask are not the 919 // same. 920 EVT ValTy = N->getValueType(0); 921 if ((Shamt != SMPos0) || (SMPos0 + SMSize0 > ValTy.getSizeInBits())) 922 return SDValue(); 923 924 SDLoc DL(N); 925 return DAG.getNode(MipsISD::Ins, DL, ValTy, Shl.getOperand(0), 926 DAG.getConstant(SMPos0, DL, MVT::i32), 927 DAG.getConstant(SMSize0, DL, MVT::i32), 928 And0.getOperand(0)); 929 } else { 930 // Pattern match DINS. 931 // $dst = or (and $src, mask0), mask1 932 // where mask0 = ((1 << SMSize0) -1) << SMPos0 933 // => dins $dst, $src, pos, size 934 if (~CN->getSExtValue() == ((((int64_t)1 << SMSize0) - 1) << SMPos0) && 935 ((SMSize0 + SMPos0 <= 64 && Subtarget.hasMips64r2()) || 936 (SMSize0 + SMPos0 <= 32))) { 937 // Check if AND instruction has constant as argument 938 bool isConstCase = And1.getOpcode() != ISD::AND; 939 if (And1.getOpcode() == ISD::AND) { 940 if (!(CN1 = dyn_cast<ConstantSDNode>(And1->getOperand(1)))) 941 return SDValue(); 942 } else { 943 if (!(CN1 = dyn_cast<ConstantSDNode>(N->getOperand(1)))) 944 return SDValue(); 945 } 946 // Don't generate INS if constant OR operand doesn't fit into bits 947 // cleared by constant AND operand. 948 if (CN->getSExtValue() & CN1->getSExtValue()) 949 return SDValue(); 950 951 SDLoc DL(N); 952 EVT ValTy = N->getOperand(0)->getValueType(0); 953 SDValue Const1; 954 SDValue SrlX; 955 if (!isConstCase) { 956 Const1 = DAG.getConstant(SMPos0, DL, MVT::i32); 957 SrlX = DAG.getNode(ISD::SRL, DL, And1->getValueType(0), And1, Const1); 958 } 959 return DAG.getNode( 960 MipsISD::Ins, DL, N->getValueType(0), 961 isConstCase 962 ? DAG.getConstant(CN1->getSExtValue() >> SMPos0, DL, ValTy) 963 : SrlX, 964 DAG.getConstant(SMPos0, DL, MVT::i32), 965 DAG.getConstant(ValTy.getSizeInBits() / 8 < 8 ? SMSize0 & 31 966 : SMSize0, 967 DL, MVT::i32), 968 And0->getOperand(0)); 969 970 } 971 return SDValue(); 972 } 973 } 974 975 static SDValue performMADD_MSUBCombine(SDNode *ROOTNode, SelectionDAG &CurDAG, 976 const MipsSubtarget &Subtarget) { 977 // ROOTNode must have a multiplication as an operand for the match to be 978 // successful. 979 if (ROOTNode->getOperand(0).getOpcode() != ISD::MUL && 980 ROOTNode->getOperand(1).getOpcode() != ISD::MUL) 981 return SDValue(); 982 983 // We don't handle vector types here. 984 if (ROOTNode->getValueType(0).isVector()) 985 return SDValue(); 986 987 // For MIPS64, madd / msub instructions are inefficent to use with 64 bit 988 // arithmetic. E.g. 989 // (add (mul a b) c) => 990 // let res = (madd (mthi (drotr c 32))x(mtlo c) a b) in 991 // MIPS64: (or (dsll (mfhi res) 32) (dsrl (dsll (mflo res) 32) 32) 992 // or 993 // MIPS64R2: (dins (mflo res) (mfhi res) 32 32) 994 // 995 // The overhead of setting up the Hi/Lo registers and reassembling the 996 // result makes this a dubious optimzation for MIPS64. The core of the 997 // problem is that Hi/Lo contain the upper and lower 32 bits of the 998 // operand and result. 999 // 1000 // It requires a chain of 4 add/mul for MIPS64R2 to get better code 1001 // density than doing it naively, 5 for MIPS64. Additionally, using 1002 // madd/msub on MIPS64 requires the operands actually be 32 bit sign 1003 // extended operands, not true 64 bit values. 1004 // 1005 // FIXME: For the moment, disable this completely for MIPS64. 1006 if (Subtarget.hasMips64()) 1007 return SDValue(); 1008 1009 SDValue Mult = ROOTNode->getOperand(0).getOpcode() == ISD::MUL 1010 ? ROOTNode->getOperand(0) 1011 : ROOTNode->getOperand(1); 1012 1013 SDValue AddOperand = ROOTNode->getOperand(0).getOpcode() == ISD::MUL 1014 ? ROOTNode->getOperand(1) 1015 : ROOTNode->getOperand(0); 1016 1017 // Transform this to a MADD only if the user of this node is the add. 1018 // If there are other users of the mul, this function returns here. 1019 if (!Mult.hasOneUse()) 1020 return SDValue(); 1021 1022 // maddu and madd are unusual instructions in that on MIPS64 bits 63..31 1023 // must be in canonical form, i.e. sign extended. For MIPS32, the operands 1024 // of the multiply must have 32 or more sign bits, otherwise we cannot 1025 // perform this optimization. We have to check this here as we're performing 1026 // this optimization pre-legalization. 1027 SDValue MultLHS = Mult->getOperand(0); 1028 SDValue MultRHS = Mult->getOperand(1); 1029 1030 bool IsSigned = MultLHS->getOpcode() == ISD::SIGN_EXTEND && 1031 MultRHS->getOpcode() == ISD::SIGN_EXTEND; 1032 bool IsUnsigned = MultLHS->getOpcode() == ISD::ZERO_EXTEND && 1033 MultRHS->getOpcode() == ISD::ZERO_EXTEND; 1034 1035 if (!IsSigned && !IsUnsigned) 1036 return SDValue(); 1037 1038 // Initialize accumulator. 1039 SDLoc DL(ROOTNode); 1040 SDValue TopHalf; 1041 SDValue BottomHalf; 1042 BottomHalf = CurDAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32, AddOperand, 1043 CurDAG.getIntPtrConstant(0, DL)); 1044 1045 TopHalf = CurDAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32, AddOperand, 1046 CurDAG.getIntPtrConstant(1, DL)); 1047 SDValue ACCIn = CurDAG.getNode(MipsISD::MTLOHI, DL, MVT::Untyped, 1048 BottomHalf, 1049 TopHalf); 1050 1051 // Create MipsMAdd(u) / MipsMSub(u) node. 1052 bool IsAdd = ROOTNode->getOpcode() == ISD::ADD; 1053 unsigned Opcode = IsAdd ? (IsUnsigned ? MipsISD::MAddu : MipsISD::MAdd) 1054 : (IsUnsigned ? MipsISD::MSubu : MipsISD::MSub); 1055 SDValue MAddOps[3] = { 1056 CurDAG.getNode(ISD::TRUNCATE, DL, MVT::i32, Mult->getOperand(0)), 1057 CurDAG.getNode(ISD::TRUNCATE, DL, MVT::i32, Mult->getOperand(1)), ACCIn}; 1058 EVT VTs[2] = {MVT::i32, MVT::i32}; 1059 SDValue MAdd = CurDAG.getNode(Opcode, DL, VTs, MAddOps); 1060 1061 SDValue ResLo = CurDAG.getNode(MipsISD::MFLO, DL, MVT::i32, MAdd); 1062 SDValue ResHi = CurDAG.getNode(MipsISD::MFHI, DL, MVT::i32, MAdd); 1063 SDValue Combined = 1064 CurDAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, ResLo, ResHi); 1065 return Combined; 1066 } 1067 1068 static SDValue performSUBCombine(SDNode *N, SelectionDAG &DAG, 1069 TargetLowering::DAGCombinerInfo &DCI, 1070 const MipsSubtarget &Subtarget) { 1071 // (sub v0 (mul v1, v2)) => (msub v1, v2, v0) 1072 if (DCI.isBeforeLegalizeOps()) { 1073 if (Subtarget.hasMips32() && !Subtarget.hasMips32r6() && 1074 !Subtarget.inMips16Mode() && N->getValueType(0) == MVT::i64) 1075 return performMADD_MSUBCombine(N, DAG, Subtarget); 1076 1077 return SDValue(); 1078 } 1079 1080 return SDValue(); 1081 } 1082 1083 static SDValue performADDCombine(SDNode *N, SelectionDAG &DAG, 1084 TargetLowering::DAGCombinerInfo &DCI, 1085 const MipsSubtarget &Subtarget) { 1086 // (add v0 (mul v1, v2)) => (madd v1, v2, v0) 1087 if (DCI.isBeforeLegalizeOps()) { 1088 if (Subtarget.hasMips32() && !Subtarget.hasMips32r6() && 1089 !Subtarget.inMips16Mode() && N->getValueType(0) == MVT::i64) 1090 return performMADD_MSUBCombine(N, DAG, Subtarget); 1091 1092 return SDValue(); 1093 } 1094 1095 // (add v0, (add v1, abs_lo(tjt))) => (add (add v0, v1), abs_lo(tjt)) 1096 SDValue Add = N->getOperand(1); 1097 1098 if (Add.getOpcode() != ISD::ADD) 1099 return SDValue(); 1100 1101 SDValue Lo = Add.getOperand(1); 1102 1103 if ((Lo.getOpcode() != MipsISD::Lo) || 1104 (Lo.getOperand(0).getOpcode() != ISD::TargetJumpTable)) 1105 return SDValue(); 1106 1107 EVT ValTy = N->getValueType(0); 1108 SDLoc DL(N); 1109 1110 SDValue Add1 = DAG.getNode(ISD::ADD, DL, ValTy, N->getOperand(0), 1111 Add.getOperand(0)); 1112 return DAG.getNode(ISD::ADD, DL, ValTy, Add1, Lo); 1113 } 1114 1115 static SDValue performSHLCombine(SDNode *N, SelectionDAG &DAG, 1116 TargetLowering::DAGCombinerInfo &DCI, 1117 const MipsSubtarget &Subtarget) { 1118 // Pattern match CINS. 1119 // $dst = shl (and $src , imm), pos 1120 // => cins $dst, $src, pos, size 1121 1122 if (DCI.isBeforeLegalizeOps() || !Subtarget.hasCnMips()) 1123 return SDValue(); 1124 1125 SDValue FirstOperand = N->getOperand(0); 1126 unsigned FirstOperandOpc = FirstOperand.getOpcode(); 1127 SDValue SecondOperand = N->getOperand(1); 1128 EVT ValTy = N->getValueType(0); 1129 SDLoc DL(N); 1130 1131 uint64_t Pos = 0, SMPos, SMSize; 1132 ConstantSDNode *CN; 1133 SDValue NewOperand; 1134 1135 // The second operand of the shift must be an immediate. 1136 if (!(CN = dyn_cast<ConstantSDNode>(SecondOperand))) 1137 return SDValue(); 1138 1139 Pos = CN->getZExtValue(); 1140 1141 if (Pos >= ValTy.getSizeInBits()) 1142 return SDValue(); 1143 1144 if (FirstOperandOpc != ISD::AND) 1145 return SDValue(); 1146 1147 // AND's second operand must be a shifted mask. 1148 if (!(CN = dyn_cast<ConstantSDNode>(FirstOperand.getOperand(1))) || 1149 !isShiftedMask(CN->getZExtValue(), SMPos, SMSize)) 1150 return SDValue(); 1151 1152 // Return if the shifted mask does not start at bit 0 or the sum of its size 1153 // and Pos exceeds the word's size. 1154 if (SMPos != 0 || SMSize > 32 || Pos + SMSize > ValTy.getSizeInBits()) 1155 return SDValue(); 1156 1157 NewOperand = FirstOperand.getOperand(0); 1158 // SMSize is 'location' (position) in this case, not size. 1159 SMSize--; 1160 1161 return DAG.getNode(MipsISD::CIns, DL, ValTy, NewOperand, 1162 DAG.getConstant(Pos, DL, MVT::i32), 1163 DAG.getConstant(SMSize, DL, MVT::i32)); 1164 } 1165 1166 SDValue MipsTargetLowering::PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) 1167 const { 1168 SelectionDAG &DAG = DCI.DAG; 1169 unsigned Opc = N->getOpcode(); 1170 1171 switch (Opc) { 1172 default: break; 1173 case ISD::SDIVREM: 1174 case ISD::UDIVREM: 1175 return performDivRemCombine(N, DAG, DCI, Subtarget); 1176 case ISD::SELECT: 1177 return performSELECTCombine(N, DAG, DCI, Subtarget); 1178 case MipsISD::CMovFP_F: 1179 case MipsISD::CMovFP_T: 1180 return performCMovFPCombine(N, DAG, DCI, Subtarget); 1181 case ISD::AND: 1182 return performANDCombine(N, DAG, DCI, Subtarget); 1183 case ISD::OR: 1184 return performORCombine(N, DAG, DCI, Subtarget); 1185 case ISD::ADD: 1186 return performADDCombine(N, DAG, DCI, Subtarget); 1187 case ISD::SHL: 1188 return performSHLCombine(N, DAG, DCI, Subtarget); 1189 case ISD::SUB: 1190 return performSUBCombine(N, DAG, DCI, Subtarget); 1191 } 1192 1193 return SDValue(); 1194 } 1195 1196 bool MipsTargetLowering::isCheapToSpeculateCttz() const { 1197 return Subtarget.hasMips32(); 1198 } 1199 1200 bool MipsTargetLowering::isCheapToSpeculateCtlz() const { 1201 return Subtarget.hasMips32(); 1202 } 1203 1204 void 1205 MipsTargetLowering::LowerOperationWrapper(SDNode *N, 1206 SmallVectorImpl<SDValue> &Results, 1207 SelectionDAG &DAG) const { 1208 SDValue Res = LowerOperation(SDValue(N, 0), DAG); 1209 1210 for (unsigned I = 0, E = Res->getNumValues(); I != E; ++I) 1211 Results.push_back(Res.getValue(I)); 1212 } 1213 1214 void 1215 MipsTargetLowering::ReplaceNodeResults(SDNode *N, 1216 SmallVectorImpl<SDValue> &Results, 1217 SelectionDAG &DAG) const { 1218 return LowerOperationWrapper(N, Results, DAG); 1219 } 1220 1221 SDValue MipsTargetLowering:: 1222 LowerOperation(SDValue Op, SelectionDAG &DAG) const 1223 { 1224 switch (Op.getOpcode()) 1225 { 1226 case ISD::BRCOND: return lowerBRCOND(Op, DAG); 1227 case ISD::ConstantPool: return lowerConstantPool(Op, DAG); 1228 case ISD::GlobalAddress: return lowerGlobalAddress(Op, DAG); 1229 case ISD::BlockAddress: return lowerBlockAddress(Op, DAG); 1230 case ISD::GlobalTLSAddress: return lowerGlobalTLSAddress(Op, DAG); 1231 case ISD::JumpTable: return lowerJumpTable(Op, DAG); 1232 case ISD::SELECT: return lowerSELECT(Op, DAG); 1233 case ISD::SETCC: return lowerSETCC(Op, DAG); 1234 case ISD::VASTART: return lowerVASTART(Op, DAG); 1235 case ISD::VAARG: return lowerVAARG(Op, DAG); 1236 case ISD::FCOPYSIGN: return lowerFCOPYSIGN(Op, DAG); 1237 case ISD::FRAMEADDR: return lowerFRAMEADDR(Op, DAG); 1238 case ISD::RETURNADDR: return lowerRETURNADDR(Op, DAG); 1239 case ISD::EH_RETURN: return lowerEH_RETURN(Op, DAG); 1240 case ISD::ATOMIC_FENCE: return lowerATOMIC_FENCE(Op, DAG); 1241 case ISD::SHL_PARTS: return lowerShiftLeftParts(Op, DAG); 1242 case ISD::SRA_PARTS: return lowerShiftRightParts(Op, DAG, true); 1243 case ISD::SRL_PARTS: return lowerShiftRightParts(Op, DAG, false); 1244 case ISD::LOAD: return lowerLOAD(Op, DAG); 1245 case ISD::STORE: return lowerSTORE(Op, DAG); 1246 case ISD::EH_DWARF_CFA: return lowerEH_DWARF_CFA(Op, DAG); 1247 case ISD::FP_TO_SINT: return lowerFP_TO_SINT(Op, DAG); 1248 } 1249 return SDValue(); 1250 } 1251 1252 //===----------------------------------------------------------------------===// 1253 // Lower helper functions 1254 //===----------------------------------------------------------------------===// 1255 1256 // addLiveIn - This helper function adds the specified physical register to the 1257 // MachineFunction as a live in value. It also creates a corresponding 1258 // virtual register for it. 1259 static unsigned 1260 addLiveIn(MachineFunction &MF, unsigned PReg, const TargetRegisterClass *RC) 1261 { 1262 unsigned VReg = MF.getRegInfo().createVirtualRegister(RC); 1263 MF.getRegInfo().addLiveIn(PReg, VReg); 1264 return VReg; 1265 } 1266 1267 static MachineBasicBlock *insertDivByZeroTrap(MachineInstr &MI, 1268 MachineBasicBlock &MBB, 1269 const TargetInstrInfo &TII, 1270 bool Is64Bit, bool IsMicroMips) { 1271 if (NoZeroDivCheck) 1272 return &MBB; 1273 1274 // Insert instruction "teq $divisor_reg, $zero, 7". 1275 MachineBasicBlock::iterator I(MI); 1276 MachineInstrBuilder MIB; 1277 MachineOperand &Divisor = MI.getOperand(2); 1278 MIB = BuildMI(MBB, std::next(I), MI.getDebugLoc(), 1279 TII.get(IsMicroMips ? Mips::TEQ_MM : Mips::TEQ)) 1280 .addReg(Divisor.getReg(), getKillRegState(Divisor.isKill())) 1281 .addReg(Mips::ZERO) 1282 .addImm(7); 1283 1284 // Use the 32-bit sub-register if this is a 64-bit division. 1285 if (Is64Bit) 1286 MIB->getOperand(0).setSubReg(Mips::sub_32); 1287 1288 // Clear Divisor's kill flag. 1289 Divisor.setIsKill(false); 1290 1291 // We would normally delete the original instruction here but in this case 1292 // we only needed to inject an additional instruction rather than replace it. 1293 1294 return &MBB; 1295 } 1296 1297 MachineBasicBlock * 1298 MipsTargetLowering::EmitInstrWithCustomInserter(MachineInstr &MI, 1299 MachineBasicBlock *BB) const { 1300 switch (MI.getOpcode()) { 1301 default: 1302 llvm_unreachable("Unexpected instr type to insert"); 1303 case Mips::ATOMIC_LOAD_ADD_I8: 1304 return emitAtomicBinaryPartword(MI, BB, 1, Mips::ADDu); 1305 case Mips::ATOMIC_LOAD_ADD_I16: 1306 return emitAtomicBinaryPartword(MI, BB, 2, Mips::ADDu); 1307 case Mips::ATOMIC_LOAD_ADD_I32: 1308 return emitAtomicBinary(MI, BB, 4, Mips::ADDu); 1309 case Mips::ATOMIC_LOAD_ADD_I64: 1310 return emitAtomicBinary(MI, BB, 8, Mips::DADDu); 1311 1312 case Mips::ATOMIC_LOAD_AND_I8: 1313 return emitAtomicBinaryPartword(MI, BB, 1, Mips::AND); 1314 case Mips::ATOMIC_LOAD_AND_I16: 1315 return emitAtomicBinaryPartword(MI, BB, 2, Mips::AND); 1316 case Mips::ATOMIC_LOAD_AND_I32: 1317 return emitAtomicBinary(MI, BB, 4, Mips::AND); 1318 case Mips::ATOMIC_LOAD_AND_I64: 1319 return emitAtomicBinary(MI, BB, 8, Mips::AND64); 1320 1321 case Mips::ATOMIC_LOAD_OR_I8: 1322 return emitAtomicBinaryPartword(MI, BB, 1, Mips::OR); 1323 case Mips::ATOMIC_LOAD_OR_I16: 1324 return emitAtomicBinaryPartword(MI, BB, 2, Mips::OR); 1325 case Mips::ATOMIC_LOAD_OR_I32: 1326 return emitAtomicBinary(MI, BB, 4, Mips::OR); 1327 case Mips::ATOMIC_LOAD_OR_I64: 1328 return emitAtomicBinary(MI, BB, 8, Mips::OR64); 1329 1330 case Mips::ATOMIC_LOAD_XOR_I8: 1331 return emitAtomicBinaryPartword(MI, BB, 1, Mips::XOR); 1332 case Mips::ATOMIC_LOAD_XOR_I16: 1333 return emitAtomicBinaryPartword(MI, BB, 2, Mips::XOR); 1334 case Mips::ATOMIC_LOAD_XOR_I32: 1335 return emitAtomicBinary(MI, BB, 4, Mips::XOR); 1336 case Mips::ATOMIC_LOAD_XOR_I64: 1337 return emitAtomicBinary(MI, BB, 8, Mips::XOR64); 1338 1339 case Mips::ATOMIC_LOAD_NAND_I8: 1340 return emitAtomicBinaryPartword(MI, BB, 1, 0, true); 1341 case Mips::ATOMIC_LOAD_NAND_I16: 1342 return emitAtomicBinaryPartword(MI, BB, 2, 0, true); 1343 case Mips::ATOMIC_LOAD_NAND_I32: 1344 return emitAtomicBinary(MI, BB, 4, 0, true); 1345 case Mips::ATOMIC_LOAD_NAND_I64: 1346 return emitAtomicBinary(MI, BB, 8, 0, true); 1347 1348 case Mips::ATOMIC_LOAD_SUB_I8: 1349 return emitAtomicBinaryPartword(MI, BB, 1, Mips::SUBu); 1350 case Mips::ATOMIC_LOAD_SUB_I16: 1351 return emitAtomicBinaryPartword(MI, BB, 2, Mips::SUBu); 1352 case Mips::ATOMIC_LOAD_SUB_I32: 1353 return emitAtomicBinary(MI, BB, 4, Mips::SUBu); 1354 case Mips::ATOMIC_LOAD_SUB_I64: 1355 return emitAtomicBinary(MI, BB, 8, Mips::DSUBu); 1356 1357 case Mips::ATOMIC_SWAP_I8: 1358 return emitAtomicBinaryPartword(MI, BB, 1, 0); 1359 case Mips::ATOMIC_SWAP_I16: 1360 return emitAtomicBinaryPartword(MI, BB, 2, 0); 1361 case Mips::ATOMIC_SWAP_I32: 1362 return emitAtomicBinary(MI, BB, 4, 0); 1363 case Mips::ATOMIC_SWAP_I64: 1364 return emitAtomicBinary(MI, BB, 8, 0); 1365 1366 case Mips::ATOMIC_CMP_SWAP_I8: 1367 return emitAtomicCmpSwapPartword(MI, BB, 1); 1368 case Mips::ATOMIC_CMP_SWAP_I16: 1369 return emitAtomicCmpSwapPartword(MI, BB, 2); 1370 case Mips::ATOMIC_CMP_SWAP_I32: 1371 return emitAtomicCmpSwap(MI, BB, 4); 1372 case Mips::ATOMIC_CMP_SWAP_I64: 1373 return emitAtomicCmpSwap(MI, BB, 8); 1374 case Mips::PseudoSDIV: 1375 case Mips::PseudoUDIV: 1376 case Mips::DIV: 1377 case Mips::DIVU: 1378 case Mips::MOD: 1379 case Mips::MODU: 1380 return insertDivByZeroTrap(MI, *BB, *Subtarget.getInstrInfo(), false, 1381 false); 1382 case Mips::SDIV_MM_Pseudo: 1383 case Mips::UDIV_MM_Pseudo: 1384 case Mips::SDIV_MM: 1385 case Mips::UDIV_MM: 1386 case Mips::DIV_MMR6: 1387 case Mips::DIVU_MMR6: 1388 case Mips::MOD_MMR6: 1389 case Mips::MODU_MMR6: 1390 return insertDivByZeroTrap(MI, *BB, *Subtarget.getInstrInfo(), false, true); 1391 case Mips::PseudoDSDIV: 1392 case Mips::PseudoDUDIV: 1393 case Mips::DDIV: 1394 case Mips::DDIVU: 1395 case Mips::DMOD: 1396 case Mips::DMODU: 1397 return insertDivByZeroTrap(MI, *BB, *Subtarget.getInstrInfo(), true, false); 1398 case Mips::DDIV_MM64R6: 1399 case Mips::DDIVU_MM64R6: 1400 case Mips::DMOD_MM64R6: 1401 case Mips::DMODU_MM64R6: 1402 return insertDivByZeroTrap(MI, *BB, *Subtarget.getInstrInfo(), true, true); 1403 1404 case Mips::PseudoSELECT_I: 1405 case Mips::PseudoSELECT_I64: 1406 case Mips::PseudoSELECT_S: 1407 case Mips::PseudoSELECT_D32: 1408 case Mips::PseudoSELECT_D64: 1409 return emitPseudoSELECT(MI, BB, false, Mips::BNE); 1410 case Mips::PseudoSELECTFP_F_I: 1411 case Mips::PseudoSELECTFP_F_I64: 1412 case Mips::PseudoSELECTFP_F_S: 1413 case Mips::PseudoSELECTFP_F_D32: 1414 case Mips::PseudoSELECTFP_F_D64: 1415 return emitPseudoSELECT(MI, BB, true, Mips::BC1F); 1416 case Mips::PseudoSELECTFP_T_I: 1417 case Mips::PseudoSELECTFP_T_I64: 1418 case Mips::PseudoSELECTFP_T_S: 1419 case Mips::PseudoSELECTFP_T_D32: 1420 case Mips::PseudoSELECTFP_T_D64: 1421 return emitPseudoSELECT(MI, BB, true, Mips::BC1T); 1422 } 1423 } 1424 1425 // This function also handles Mips::ATOMIC_SWAP_I32 (when BinOpcode == 0), and 1426 // Mips::ATOMIC_LOAD_NAND_I32 (when Nand == true) 1427 MachineBasicBlock *MipsTargetLowering::emitAtomicBinary(MachineInstr &MI, 1428 MachineBasicBlock *BB, 1429 unsigned Size, 1430 unsigned BinOpcode, 1431 bool Nand) const { 1432 assert((Size == 4 || Size == 8) && "Unsupported size for EmitAtomicBinary."); 1433 1434 MachineFunction *MF = BB->getParent(); 1435 MachineRegisterInfo &RegInfo = MF->getRegInfo(); 1436 const TargetRegisterClass *RC = getRegClassFor(MVT::getIntegerVT(Size * 8)); 1437 const TargetInstrInfo *TII = Subtarget.getInstrInfo(); 1438 const bool ArePtrs64bit = ABI.ArePtrs64bit(); 1439 DebugLoc DL = MI.getDebugLoc(); 1440 unsigned LL, SC, AND, NOR, ZERO, BEQ; 1441 1442 if (Size == 4) { 1443 if (isMicroMips) { 1444 LL = Mips::LL_MM; 1445 SC = Mips::SC_MM; 1446 } else { 1447 LL = Subtarget.hasMips32r6() 1448 ? (ArePtrs64bit ? Mips::LL64_R6 : Mips::LL_R6) 1449 : (ArePtrs64bit ? Mips::LL64 : Mips::LL); 1450 SC = Subtarget.hasMips32r6() 1451 ? (ArePtrs64bit ? Mips::SC64_R6 : Mips::SC_R6) 1452 : (ArePtrs64bit ? Mips::SC64 : Mips::SC); 1453 } 1454 1455 AND = Mips::AND; 1456 NOR = Mips::NOR; 1457 ZERO = Mips::ZERO; 1458 BEQ = Mips::BEQ; 1459 } else { 1460 LL = Subtarget.hasMips64r6() ? Mips::LLD_R6 : Mips::LLD; 1461 SC = Subtarget.hasMips64r6() ? Mips::SCD_R6 : Mips::SCD; 1462 AND = Mips::AND64; 1463 NOR = Mips::NOR64; 1464 ZERO = Mips::ZERO_64; 1465 BEQ = Mips::BEQ64; 1466 } 1467 1468 unsigned OldVal = MI.getOperand(0).getReg(); 1469 unsigned Ptr = MI.getOperand(1).getReg(); 1470 unsigned Incr = MI.getOperand(2).getReg(); 1471 1472 unsigned StoreVal = RegInfo.createVirtualRegister(RC); 1473 unsigned AndRes = RegInfo.createVirtualRegister(RC); 1474 unsigned Success = RegInfo.createVirtualRegister(RC); 1475 1476 // insert new blocks after the current block 1477 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 1478 MachineBasicBlock *loopMBB = MF->CreateMachineBasicBlock(LLVM_BB); 1479 MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB); 1480 MachineFunction::iterator It = ++BB->getIterator(); 1481 MF->insert(It, loopMBB); 1482 MF->insert(It, exitMBB); 1483 1484 // Transfer the remainder of BB and its successor edges to exitMBB. 1485 exitMBB->splice(exitMBB->begin(), BB, 1486 std::next(MachineBasicBlock::iterator(MI)), BB->end()); 1487 exitMBB->transferSuccessorsAndUpdatePHIs(BB); 1488 1489 // thisMBB: 1490 // ... 1491 // fallthrough --> loopMBB 1492 BB->addSuccessor(loopMBB); 1493 loopMBB->addSuccessor(loopMBB); 1494 loopMBB->addSuccessor(exitMBB); 1495 1496 // loopMBB: 1497 // ll oldval, 0(ptr) 1498 // <binop> storeval, oldval, incr 1499 // sc success, storeval, 0(ptr) 1500 // beq success, $0, loopMBB 1501 BB = loopMBB; 1502 BuildMI(BB, DL, TII->get(LL), OldVal).addReg(Ptr).addImm(0); 1503 if (Nand) { 1504 // and andres, oldval, incr 1505 // nor storeval, $0, andres 1506 BuildMI(BB, DL, TII->get(AND), AndRes).addReg(OldVal).addReg(Incr); 1507 BuildMI(BB, DL, TII->get(NOR), StoreVal).addReg(ZERO).addReg(AndRes); 1508 } else if (BinOpcode) { 1509 // <binop> storeval, oldval, incr 1510 BuildMI(BB, DL, TII->get(BinOpcode), StoreVal).addReg(OldVal).addReg(Incr); 1511 } else { 1512 StoreVal = Incr; 1513 } 1514 BuildMI(BB, DL, TII->get(SC), Success).addReg(StoreVal).addReg(Ptr).addImm(0); 1515 BuildMI(BB, DL, TII->get(BEQ)).addReg(Success).addReg(ZERO).addMBB(loopMBB); 1516 1517 MI.eraseFromParent(); // The instruction is gone now. 1518 1519 return exitMBB; 1520 } 1521 1522 MachineBasicBlock *MipsTargetLowering::emitSignExtendToI32InReg( 1523 MachineInstr &MI, MachineBasicBlock *BB, unsigned Size, unsigned DstReg, 1524 unsigned SrcReg) const { 1525 const TargetInstrInfo *TII = Subtarget.getInstrInfo(); 1526 const DebugLoc &DL = MI.getDebugLoc(); 1527 1528 if (Subtarget.hasMips32r2() && Size == 1) { 1529 BuildMI(BB, DL, TII->get(Mips::SEB), DstReg).addReg(SrcReg); 1530 return BB; 1531 } 1532 1533 if (Subtarget.hasMips32r2() && Size == 2) { 1534 BuildMI(BB, DL, TII->get(Mips::SEH), DstReg).addReg(SrcReg); 1535 return BB; 1536 } 1537 1538 MachineFunction *MF = BB->getParent(); 1539 MachineRegisterInfo &RegInfo = MF->getRegInfo(); 1540 const TargetRegisterClass *RC = getRegClassFor(MVT::i32); 1541 unsigned ScrReg = RegInfo.createVirtualRegister(RC); 1542 1543 assert(Size < 32); 1544 int64_t ShiftImm = 32 - (Size * 8); 1545 1546 BuildMI(BB, DL, TII->get(Mips::SLL), ScrReg).addReg(SrcReg).addImm(ShiftImm); 1547 BuildMI(BB, DL, TII->get(Mips::SRA), DstReg).addReg(ScrReg).addImm(ShiftImm); 1548 1549 return BB; 1550 } 1551 1552 MachineBasicBlock *MipsTargetLowering::emitAtomicBinaryPartword( 1553 MachineInstr &MI, MachineBasicBlock *BB, unsigned Size, unsigned BinOpcode, 1554 bool Nand) const { 1555 assert((Size == 1 || Size == 2) && 1556 "Unsupported size for EmitAtomicBinaryPartial."); 1557 1558 MachineFunction *MF = BB->getParent(); 1559 MachineRegisterInfo &RegInfo = MF->getRegInfo(); 1560 const TargetRegisterClass *RC = getRegClassFor(MVT::i32); 1561 const bool ArePtrs64bit = ABI.ArePtrs64bit(); 1562 const TargetRegisterClass *RCp = 1563 getRegClassFor(ArePtrs64bit ? MVT::i64 : MVT::i32); 1564 const TargetInstrInfo *TII = Subtarget.getInstrInfo(); 1565 DebugLoc DL = MI.getDebugLoc(); 1566 1567 unsigned Dest = MI.getOperand(0).getReg(); 1568 unsigned Ptr = MI.getOperand(1).getReg(); 1569 unsigned Incr = MI.getOperand(2).getReg(); 1570 1571 unsigned AlignedAddr = RegInfo.createVirtualRegister(RCp); 1572 unsigned ShiftAmt = RegInfo.createVirtualRegister(RC); 1573 unsigned Mask = RegInfo.createVirtualRegister(RC); 1574 unsigned Mask2 = RegInfo.createVirtualRegister(RC); 1575 unsigned NewVal = RegInfo.createVirtualRegister(RC); 1576 unsigned OldVal = RegInfo.createVirtualRegister(RC); 1577 unsigned Incr2 = RegInfo.createVirtualRegister(RC); 1578 unsigned MaskLSB2 = RegInfo.createVirtualRegister(RCp); 1579 unsigned PtrLSB2 = RegInfo.createVirtualRegister(RC); 1580 unsigned MaskUpper = RegInfo.createVirtualRegister(RC); 1581 unsigned AndRes = RegInfo.createVirtualRegister(RC); 1582 unsigned BinOpRes = RegInfo.createVirtualRegister(RC); 1583 unsigned MaskedOldVal0 = RegInfo.createVirtualRegister(RC); 1584 unsigned StoreVal = RegInfo.createVirtualRegister(RC); 1585 unsigned MaskedOldVal1 = RegInfo.createVirtualRegister(RC); 1586 unsigned SrlRes = RegInfo.createVirtualRegister(RC); 1587 unsigned Success = RegInfo.createVirtualRegister(RC); 1588 1589 unsigned LL, SC; 1590 if (isMicroMips) { 1591 LL = Mips::LL_MM; 1592 SC = Mips::SC_MM; 1593 } else { 1594 LL = Subtarget.hasMips32r6() ? (ArePtrs64bit ? Mips::LL64_R6 : Mips::LL_R6) 1595 : (ArePtrs64bit ? Mips::LL64 : Mips::LL); 1596 SC = Subtarget.hasMips32r6() ? (ArePtrs64bit ? Mips::SC64_R6 : Mips::SC_R6) 1597 : (ArePtrs64bit ? Mips::SC64 : Mips::SC); 1598 } 1599 1600 // insert new blocks after the current block 1601 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 1602 MachineBasicBlock *loopMBB = MF->CreateMachineBasicBlock(LLVM_BB); 1603 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(LLVM_BB); 1604 MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB); 1605 MachineFunction::iterator It = ++BB->getIterator(); 1606 MF->insert(It, loopMBB); 1607 MF->insert(It, sinkMBB); 1608 MF->insert(It, exitMBB); 1609 1610 // Transfer the remainder of BB and its successor edges to exitMBB. 1611 exitMBB->splice(exitMBB->begin(), BB, 1612 std::next(MachineBasicBlock::iterator(MI)), BB->end()); 1613 exitMBB->transferSuccessorsAndUpdatePHIs(BB); 1614 1615 BB->addSuccessor(loopMBB); 1616 loopMBB->addSuccessor(loopMBB); 1617 loopMBB->addSuccessor(sinkMBB); 1618 sinkMBB->addSuccessor(exitMBB); 1619 1620 // thisMBB: 1621 // addiu masklsb2,$0,-4 # 0xfffffffc 1622 // and alignedaddr,ptr,masklsb2 1623 // andi ptrlsb2,ptr,3 1624 // sll shiftamt,ptrlsb2,3 1625 // ori maskupper,$0,255 # 0xff 1626 // sll mask,maskupper,shiftamt 1627 // nor mask2,$0,mask 1628 // sll incr2,incr,shiftamt 1629 1630 int64_t MaskImm = (Size == 1) ? 255 : 65535; 1631 BuildMI(BB, DL, TII->get(ABI.GetPtrAddiuOp()), MaskLSB2) 1632 .addReg(ABI.GetNullPtr()).addImm(-4); 1633 BuildMI(BB, DL, TII->get(ABI.GetPtrAndOp()), AlignedAddr) 1634 .addReg(Ptr).addReg(MaskLSB2); 1635 BuildMI(BB, DL, TII->get(Mips::ANDi), PtrLSB2) 1636 .addReg(Ptr, 0, ArePtrs64bit ? Mips::sub_32 : 0).addImm(3); 1637 if (Subtarget.isLittle()) { 1638 BuildMI(BB, DL, TII->get(Mips::SLL), ShiftAmt).addReg(PtrLSB2).addImm(3); 1639 } else { 1640 unsigned Off = RegInfo.createVirtualRegister(RC); 1641 BuildMI(BB, DL, TII->get(Mips::XORi), Off) 1642 .addReg(PtrLSB2).addImm((Size == 1) ? 3 : 2); 1643 BuildMI(BB, DL, TII->get(Mips::SLL), ShiftAmt).addReg(Off).addImm(3); 1644 } 1645 BuildMI(BB, DL, TII->get(Mips::ORi), MaskUpper) 1646 .addReg(Mips::ZERO).addImm(MaskImm); 1647 BuildMI(BB, DL, TII->get(Mips::SLLV), Mask) 1648 .addReg(MaskUpper).addReg(ShiftAmt); 1649 BuildMI(BB, DL, TII->get(Mips::NOR), Mask2).addReg(Mips::ZERO).addReg(Mask); 1650 BuildMI(BB, DL, TII->get(Mips::SLLV), Incr2).addReg(Incr).addReg(ShiftAmt); 1651 1652 // atomic.load.binop 1653 // loopMBB: 1654 // ll oldval,0(alignedaddr) 1655 // binop binopres,oldval,incr2 1656 // and newval,binopres,mask 1657 // and maskedoldval0,oldval,mask2 1658 // or storeval,maskedoldval0,newval 1659 // sc success,storeval,0(alignedaddr) 1660 // beq success,$0,loopMBB 1661 1662 // atomic.swap 1663 // loopMBB: 1664 // ll oldval,0(alignedaddr) 1665 // and newval,incr2,mask 1666 // and maskedoldval0,oldval,mask2 1667 // or storeval,maskedoldval0,newval 1668 // sc success,storeval,0(alignedaddr) 1669 // beq success,$0,loopMBB 1670 1671 BB = loopMBB; 1672 BuildMI(BB, DL, TII->get(LL), OldVal).addReg(AlignedAddr).addImm(0); 1673 if (Nand) { 1674 // and andres, oldval, incr2 1675 // nor binopres, $0, andres 1676 // and newval, binopres, mask 1677 BuildMI(BB, DL, TII->get(Mips::AND), AndRes).addReg(OldVal).addReg(Incr2); 1678 BuildMI(BB, DL, TII->get(Mips::NOR), BinOpRes) 1679 .addReg(Mips::ZERO).addReg(AndRes); 1680 BuildMI(BB, DL, TII->get(Mips::AND), NewVal).addReg(BinOpRes).addReg(Mask); 1681 } else if (BinOpcode) { 1682 // <binop> binopres, oldval, incr2 1683 // and newval, binopres, mask 1684 BuildMI(BB, DL, TII->get(BinOpcode), BinOpRes).addReg(OldVal).addReg(Incr2); 1685 BuildMI(BB, DL, TII->get(Mips::AND), NewVal).addReg(BinOpRes).addReg(Mask); 1686 } else { // atomic.swap 1687 // and newval, incr2, mask 1688 BuildMI(BB, DL, TII->get(Mips::AND), NewVal).addReg(Incr2).addReg(Mask); 1689 } 1690 1691 BuildMI(BB, DL, TII->get(Mips::AND), MaskedOldVal0) 1692 .addReg(OldVal).addReg(Mask2); 1693 BuildMI(BB, DL, TII->get(Mips::OR), StoreVal) 1694 .addReg(MaskedOldVal0).addReg(NewVal); 1695 BuildMI(BB, DL, TII->get(SC), Success) 1696 .addReg(StoreVal).addReg(AlignedAddr).addImm(0); 1697 BuildMI(BB, DL, TII->get(Mips::BEQ)) 1698 .addReg(Success).addReg(Mips::ZERO).addMBB(loopMBB); 1699 1700 // sinkMBB: 1701 // and maskedoldval1,oldval,mask 1702 // srl srlres,maskedoldval1,shiftamt 1703 // sign_extend dest,srlres 1704 BB = sinkMBB; 1705 1706 BuildMI(BB, DL, TII->get(Mips::AND), MaskedOldVal1) 1707 .addReg(OldVal).addReg(Mask); 1708 BuildMI(BB, DL, TII->get(Mips::SRLV), SrlRes) 1709 .addReg(MaskedOldVal1).addReg(ShiftAmt); 1710 BB = emitSignExtendToI32InReg(MI, BB, Size, Dest, SrlRes); 1711 1712 MI.eraseFromParent(); // The instruction is gone now. 1713 1714 return exitMBB; 1715 } 1716 1717 MachineBasicBlock *MipsTargetLowering::emitAtomicCmpSwap(MachineInstr &MI, 1718 MachineBasicBlock *BB, 1719 unsigned Size) const { 1720 assert((Size == 4 || Size == 8) && "Unsupported size for EmitAtomicCmpSwap."); 1721 1722 MachineFunction *MF = BB->getParent(); 1723 MachineRegisterInfo &RegInfo = MF->getRegInfo(); 1724 const TargetRegisterClass *RC = getRegClassFor(MVT::getIntegerVT(Size * 8)); 1725 const TargetInstrInfo *TII = Subtarget.getInstrInfo(); 1726 const bool ArePtrs64bit = ABI.ArePtrs64bit(); 1727 DebugLoc DL = MI.getDebugLoc(); 1728 unsigned LL, SC, ZERO, BNE, BEQ; 1729 1730 if (Size == 4) { 1731 if (isMicroMips) { 1732 LL = Mips::LL_MM; 1733 SC = Mips::SC_MM; 1734 } else { 1735 LL = Subtarget.hasMips32r6() 1736 ? (ArePtrs64bit ? Mips::LL64_R6 : Mips::LL_R6) 1737 : (ArePtrs64bit ? Mips::LL64 : Mips::LL); 1738 SC = Subtarget.hasMips32r6() 1739 ? (ArePtrs64bit ? Mips::SC64_R6 : Mips::SC_R6) 1740 : (ArePtrs64bit ? Mips::SC64 : Mips::SC); 1741 } 1742 1743 ZERO = Mips::ZERO; 1744 BNE = Mips::BNE; 1745 BEQ = Mips::BEQ; 1746 } else { 1747 LL = Subtarget.hasMips64r6() ? Mips::LLD_R6 : Mips::LLD; 1748 SC = Subtarget.hasMips64r6() ? Mips::SCD_R6 : Mips::SCD; 1749 ZERO = Mips::ZERO_64; 1750 BNE = Mips::BNE64; 1751 BEQ = Mips::BEQ64; 1752 } 1753 1754 unsigned Dest = MI.getOperand(0).getReg(); 1755 unsigned Ptr = MI.getOperand(1).getReg(); 1756 unsigned OldVal = MI.getOperand(2).getReg(); 1757 unsigned NewVal = MI.getOperand(3).getReg(); 1758 1759 unsigned Success = RegInfo.createVirtualRegister(RC); 1760 1761 // insert new blocks after the current block 1762 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 1763 MachineBasicBlock *loop1MBB = MF->CreateMachineBasicBlock(LLVM_BB); 1764 MachineBasicBlock *loop2MBB = MF->CreateMachineBasicBlock(LLVM_BB); 1765 MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB); 1766 MachineFunction::iterator It = ++BB->getIterator(); 1767 MF->insert(It, loop1MBB); 1768 MF->insert(It, loop2MBB); 1769 MF->insert(It, exitMBB); 1770 1771 // Transfer the remainder of BB and its successor edges to exitMBB. 1772 exitMBB->splice(exitMBB->begin(), BB, 1773 std::next(MachineBasicBlock::iterator(MI)), BB->end()); 1774 exitMBB->transferSuccessorsAndUpdatePHIs(BB); 1775 1776 // thisMBB: 1777 // ... 1778 // fallthrough --> loop1MBB 1779 BB->addSuccessor(loop1MBB); 1780 loop1MBB->addSuccessor(exitMBB); 1781 loop1MBB->addSuccessor(loop2MBB); 1782 loop2MBB->addSuccessor(loop1MBB); 1783 loop2MBB->addSuccessor(exitMBB); 1784 1785 // loop1MBB: 1786 // ll dest, 0(ptr) 1787 // bne dest, oldval, exitMBB 1788 BB = loop1MBB; 1789 BuildMI(BB, DL, TII->get(LL), Dest).addReg(Ptr).addImm(0); 1790 BuildMI(BB, DL, TII->get(BNE)) 1791 .addReg(Dest).addReg(OldVal).addMBB(exitMBB); 1792 1793 // loop2MBB: 1794 // sc success, newval, 0(ptr) 1795 // beq success, $0, loop1MBB 1796 BB = loop2MBB; 1797 BuildMI(BB, DL, TII->get(SC), Success) 1798 .addReg(NewVal).addReg(Ptr).addImm(0); 1799 BuildMI(BB, DL, TII->get(BEQ)) 1800 .addReg(Success).addReg(ZERO).addMBB(loop1MBB); 1801 1802 MI.eraseFromParent(); // The instruction is gone now. 1803 1804 return exitMBB; 1805 } 1806 1807 MachineBasicBlock *MipsTargetLowering::emitAtomicCmpSwapPartword( 1808 MachineInstr &MI, MachineBasicBlock *BB, unsigned Size) const { 1809 assert((Size == 1 || Size == 2) && 1810 "Unsupported size for EmitAtomicCmpSwapPartial."); 1811 1812 MachineFunction *MF = BB->getParent(); 1813 MachineRegisterInfo &RegInfo = MF->getRegInfo(); 1814 const TargetRegisterClass *RC = getRegClassFor(MVT::i32); 1815 const bool ArePtrs64bit = ABI.ArePtrs64bit(); 1816 const TargetRegisterClass *RCp = 1817 getRegClassFor(ArePtrs64bit ? MVT::i64 : MVT::i32); 1818 const TargetInstrInfo *TII = Subtarget.getInstrInfo(); 1819 DebugLoc DL = MI.getDebugLoc(); 1820 1821 unsigned Dest = MI.getOperand(0).getReg(); 1822 unsigned Ptr = MI.getOperand(1).getReg(); 1823 unsigned CmpVal = MI.getOperand(2).getReg(); 1824 unsigned NewVal = MI.getOperand(3).getReg(); 1825 1826 unsigned AlignedAddr = RegInfo.createVirtualRegister(RCp); 1827 unsigned ShiftAmt = RegInfo.createVirtualRegister(RC); 1828 unsigned Mask = RegInfo.createVirtualRegister(RC); 1829 unsigned Mask2 = RegInfo.createVirtualRegister(RC); 1830 unsigned ShiftedCmpVal = RegInfo.createVirtualRegister(RC); 1831 unsigned OldVal = RegInfo.createVirtualRegister(RC); 1832 unsigned MaskedOldVal0 = RegInfo.createVirtualRegister(RC); 1833 unsigned ShiftedNewVal = RegInfo.createVirtualRegister(RC); 1834 unsigned MaskLSB2 = RegInfo.createVirtualRegister(RCp); 1835 unsigned PtrLSB2 = RegInfo.createVirtualRegister(RC); 1836 unsigned MaskUpper = RegInfo.createVirtualRegister(RC); 1837 unsigned MaskedCmpVal = RegInfo.createVirtualRegister(RC); 1838 unsigned MaskedNewVal = RegInfo.createVirtualRegister(RC); 1839 unsigned MaskedOldVal1 = RegInfo.createVirtualRegister(RC); 1840 unsigned StoreVal = RegInfo.createVirtualRegister(RC); 1841 unsigned SrlRes = RegInfo.createVirtualRegister(RC); 1842 unsigned Success = RegInfo.createVirtualRegister(RC); 1843 unsigned LL, SC; 1844 1845 if (isMicroMips) { 1846 LL = Mips::LL_MM; 1847 SC = Mips::SC_MM; 1848 } else { 1849 LL = Subtarget.hasMips32r6() ? (ArePtrs64bit ? Mips::LL64_R6 : Mips::LL_R6) 1850 : (ArePtrs64bit ? Mips::LL64 : Mips::LL); 1851 SC = Subtarget.hasMips32r6() ? (ArePtrs64bit ? Mips::SC64_R6 : Mips::SC_R6) 1852 : (ArePtrs64bit ? Mips::SC64 : Mips::SC); 1853 } 1854 1855 // insert new blocks after the current block 1856 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 1857 MachineBasicBlock *loop1MBB = MF->CreateMachineBasicBlock(LLVM_BB); 1858 MachineBasicBlock *loop2MBB = MF->CreateMachineBasicBlock(LLVM_BB); 1859 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(LLVM_BB); 1860 MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB); 1861 MachineFunction::iterator It = ++BB->getIterator(); 1862 MF->insert(It, loop1MBB); 1863 MF->insert(It, loop2MBB); 1864 MF->insert(It, sinkMBB); 1865 MF->insert(It, exitMBB); 1866 1867 // Transfer the remainder of BB and its successor edges to exitMBB. 1868 exitMBB->splice(exitMBB->begin(), BB, 1869 std::next(MachineBasicBlock::iterator(MI)), BB->end()); 1870 exitMBB->transferSuccessorsAndUpdatePHIs(BB); 1871 1872 BB->addSuccessor(loop1MBB); 1873 loop1MBB->addSuccessor(sinkMBB); 1874 loop1MBB->addSuccessor(loop2MBB); 1875 loop2MBB->addSuccessor(loop1MBB); 1876 loop2MBB->addSuccessor(sinkMBB); 1877 sinkMBB->addSuccessor(exitMBB); 1878 1879 // FIXME: computation of newval2 can be moved to loop2MBB. 1880 // thisMBB: 1881 // addiu masklsb2,$0,-4 # 0xfffffffc 1882 // and alignedaddr,ptr,masklsb2 1883 // andi ptrlsb2,ptr,3 1884 // xori ptrlsb2,ptrlsb2,3 # Only for BE 1885 // sll shiftamt,ptrlsb2,3 1886 // ori maskupper,$0,255 # 0xff 1887 // sll mask,maskupper,shiftamt 1888 // nor mask2,$0,mask 1889 // andi maskedcmpval,cmpval,255 1890 // sll shiftedcmpval,maskedcmpval,shiftamt 1891 // andi maskednewval,newval,255 1892 // sll shiftednewval,maskednewval,shiftamt 1893 int64_t MaskImm = (Size == 1) ? 255 : 65535; 1894 BuildMI(BB, DL, TII->get(ArePtrs64bit ? Mips::DADDiu : Mips::ADDiu), MaskLSB2) 1895 .addReg(ABI.GetNullPtr()).addImm(-4); 1896 BuildMI(BB, DL, TII->get(ArePtrs64bit ? Mips::AND64 : Mips::AND), AlignedAddr) 1897 .addReg(Ptr).addReg(MaskLSB2); 1898 BuildMI(BB, DL, TII->get(Mips::ANDi), PtrLSB2) 1899 .addReg(Ptr, 0, ArePtrs64bit ? Mips::sub_32 : 0).addImm(3); 1900 if (Subtarget.isLittle()) { 1901 BuildMI(BB, DL, TII->get(Mips::SLL), ShiftAmt).addReg(PtrLSB2).addImm(3); 1902 } else { 1903 unsigned Off = RegInfo.createVirtualRegister(RC); 1904 BuildMI(BB, DL, TII->get(Mips::XORi), Off) 1905 .addReg(PtrLSB2).addImm((Size == 1) ? 3 : 2); 1906 BuildMI(BB, DL, TII->get(Mips::SLL), ShiftAmt).addReg(Off).addImm(3); 1907 } 1908 BuildMI(BB, DL, TII->get(Mips::ORi), MaskUpper) 1909 .addReg(Mips::ZERO).addImm(MaskImm); 1910 BuildMI(BB, DL, TII->get(Mips::SLLV), Mask) 1911 .addReg(MaskUpper).addReg(ShiftAmt); 1912 BuildMI(BB, DL, TII->get(Mips::NOR), Mask2).addReg(Mips::ZERO).addReg(Mask); 1913 BuildMI(BB, DL, TII->get(Mips::ANDi), MaskedCmpVal) 1914 .addReg(CmpVal).addImm(MaskImm); 1915 BuildMI(BB, DL, TII->get(Mips::SLLV), ShiftedCmpVal) 1916 .addReg(MaskedCmpVal).addReg(ShiftAmt); 1917 BuildMI(BB, DL, TII->get(Mips::ANDi), MaskedNewVal) 1918 .addReg(NewVal).addImm(MaskImm); 1919 BuildMI(BB, DL, TII->get(Mips::SLLV), ShiftedNewVal) 1920 .addReg(MaskedNewVal).addReg(ShiftAmt); 1921 1922 // loop1MBB: 1923 // ll oldval,0(alginedaddr) 1924 // and maskedoldval0,oldval,mask 1925 // bne maskedoldval0,shiftedcmpval,sinkMBB 1926 BB = loop1MBB; 1927 BuildMI(BB, DL, TII->get(LL), OldVal).addReg(AlignedAddr).addImm(0); 1928 BuildMI(BB, DL, TII->get(Mips::AND), MaskedOldVal0) 1929 .addReg(OldVal).addReg(Mask); 1930 BuildMI(BB, DL, TII->get(Mips::BNE)) 1931 .addReg(MaskedOldVal0).addReg(ShiftedCmpVal).addMBB(sinkMBB); 1932 1933 // loop2MBB: 1934 // and maskedoldval1,oldval,mask2 1935 // or storeval,maskedoldval1,shiftednewval 1936 // sc success,storeval,0(alignedaddr) 1937 // beq success,$0,loop1MBB 1938 BB = loop2MBB; 1939 BuildMI(BB, DL, TII->get(Mips::AND), MaskedOldVal1) 1940 .addReg(OldVal).addReg(Mask2); 1941 BuildMI(BB, DL, TII->get(Mips::OR), StoreVal) 1942 .addReg(MaskedOldVal1).addReg(ShiftedNewVal); 1943 BuildMI(BB, DL, TII->get(SC), Success) 1944 .addReg(StoreVal).addReg(AlignedAddr).addImm(0); 1945 BuildMI(BB, DL, TII->get(Mips::BEQ)) 1946 .addReg(Success).addReg(Mips::ZERO).addMBB(loop1MBB); 1947 1948 // sinkMBB: 1949 // srl srlres,maskedoldval0,shiftamt 1950 // sign_extend dest,srlres 1951 BB = sinkMBB; 1952 1953 BuildMI(BB, DL, TII->get(Mips::SRLV), SrlRes) 1954 .addReg(MaskedOldVal0).addReg(ShiftAmt); 1955 BB = emitSignExtendToI32InReg(MI, BB, Size, Dest, SrlRes); 1956 1957 MI.eraseFromParent(); // The instruction is gone now. 1958 1959 return exitMBB; 1960 } 1961 1962 SDValue MipsTargetLowering::lowerBRCOND(SDValue Op, SelectionDAG &DAG) const { 1963 // The first operand is the chain, the second is the condition, the third is 1964 // the block to branch to if the condition is true. 1965 SDValue Chain = Op.getOperand(0); 1966 SDValue Dest = Op.getOperand(2); 1967 SDLoc DL(Op); 1968 1969 assert(!Subtarget.hasMips32r6() && !Subtarget.hasMips64r6()); 1970 SDValue CondRes = createFPCmp(DAG, Op.getOperand(1)); 1971 1972 // Return if flag is not set by a floating point comparison. 1973 if (CondRes.getOpcode() != MipsISD::FPCmp) 1974 return Op; 1975 1976 SDValue CCNode = CondRes.getOperand(2); 1977 Mips::CondCode CC = 1978 (Mips::CondCode)cast<ConstantSDNode>(CCNode)->getZExtValue(); 1979 unsigned Opc = invertFPCondCodeUser(CC) ? Mips::BRANCH_F : Mips::BRANCH_T; 1980 SDValue BrCode = DAG.getConstant(Opc, DL, MVT::i32); 1981 SDValue FCC0 = DAG.getRegister(Mips::FCC0, MVT::i32); 1982 return DAG.getNode(MipsISD::FPBrcond, DL, Op.getValueType(), Chain, BrCode, 1983 FCC0, Dest, CondRes); 1984 } 1985 1986 SDValue MipsTargetLowering:: 1987 lowerSELECT(SDValue Op, SelectionDAG &DAG) const 1988 { 1989 assert(!Subtarget.hasMips32r6() && !Subtarget.hasMips64r6()); 1990 SDValue Cond = createFPCmp(DAG, Op.getOperand(0)); 1991 1992 // Return if flag is not set by a floating point comparison. 1993 if (Cond.getOpcode() != MipsISD::FPCmp) 1994 return Op; 1995 1996 return createCMovFP(DAG, Cond, Op.getOperand(1), Op.getOperand(2), 1997 SDLoc(Op)); 1998 } 1999 2000 SDValue MipsTargetLowering::lowerSETCC(SDValue Op, SelectionDAG &DAG) const { 2001 assert(!Subtarget.hasMips32r6() && !Subtarget.hasMips64r6()); 2002 SDValue Cond = createFPCmp(DAG, Op); 2003 2004 assert(Cond.getOpcode() == MipsISD::FPCmp && 2005 "Floating point operand expected."); 2006 2007 SDLoc DL(Op); 2008 SDValue True = DAG.getConstant(1, DL, MVT::i32); 2009 SDValue False = DAG.getConstant(0, DL, MVT::i32); 2010 2011 return createCMovFP(DAG, Cond, True, False, DL); 2012 } 2013 2014 SDValue MipsTargetLowering::lowerGlobalAddress(SDValue Op, 2015 SelectionDAG &DAG) const { 2016 EVT Ty = Op.getValueType(); 2017 GlobalAddressSDNode *N = cast<GlobalAddressSDNode>(Op); 2018 const GlobalValue *GV = N->getGlobal(); 2019 2020 if (!isPositionIndependent()) { 2021 const MipsTargetObjectFile *TLOF = 2022 static_cast<const MipsTargetObjectFile *>( 2023 getTargetMachine().getObjFileLowering()); 2024 const GlobalObject *GO = GV->getBaseObject(); 2025 if (GO && TLOF->IsGlobalInSmallSection(GO, getTargetMachine())) 2026 // %gp_rel relocation 2027 return getAddrGPRel(N, SDLoc(N), Ty, DAG, ABI.IsN64()); 2028 2029 // %hi/%lo relocation 2030 return Subtarget.hasSym32() ? getAddrNonPIC(N, SDLoc(N), Ty, DAG) 2031 // %highest/%higher/%hi/%lo relocation 2032 : getAddrNonPICSym64(N, SDLoc(N), Ty, DAG); 2033 } 2034 2035 // Every other architecture would use shouldAssumeDSOLocal in here, but 2036 // mips is special. 2037 // * In PIC code mips requires got loads even for local statics! 2038 // * To save on got entries, for local statics the got entry contains the 2039 // page and an additional add instruction takes care of the low bits. 2040 // * It is legal to access a hidden symbol with a non hidden undefined, 2041 // so one cannot guarantee that all access to a hidden symbol will know 2042 // it is hidden. 2043 // * Mips linkers don't support creating a page and a full got entry for 2044 // the same symbol. 2045 // * Given all that, we have to use a full got entry for hidden symbols :-( 2046 if (GV->hasLocalLinkage()) 2047 return getAddrLocal(N, SDLoc(N), Ty, DAG, ABI.IsN32() || ABI.IsN64()); 2048 2049 if (LargeGOT) 2050 return getAddrGlobalLargeGOT( 2051 N, SDLoc(N), Ty, DAG, MipsII::MO_GOT_HI16, MipsII::MO_GOT_LO16, 2052 DAG.getEntryNode(), 2053 MachinePointerInfo::getGOT(DAG.getMachineFunction())); 2054 2055 return getAddrGlobal( 2056 N, SDLoc(N), Ty, DAG, 2057 (ABI.IsN32() || ABI.IsN64()) ? MipsII::MO_GOT_DISP : MipsII::MO_GOT, 2058 DAG.getEntryNode(), MachinePointerInfo::getGOT(DAG.getMachineFunction())); 2059 } 2060 2061 SDValue MipsTargetLowering::lowerBlockAddress(SDValue Op, 2062 SelectionDAG &DAG) const { 2063 BlockAddressSDNode *N = cast<BlockAddressSDNode>(Op); 2064 EVT Ty = Op.getValueType(); 2065 2066 if (!isPositionIndependent()) 2067 return Subtarget.hasSym32() ? getAddrNonPIC(N, SDLoc(N), Ty, DAG) 2068 : getAddrNonPICSym64(N, SDLoc(N), Ty, DAG); 2069 2070 return getAddrLocal(N, SDLoc(N), Ty, DAG, ABI.IsN32() || ABI.IsN64()); 2071 } 2072 2073 SDValue MipsTargetLowering:: 2074 lowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const 2075 { 2076 // If the relocation model is PIC, use the General Dynamic TLS Model or 2077 // Local Dynamic TLS model, otherwise use the Initial Exec or 2078 // Local Exec TLS Model. 2079 2080 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op); 2081 if (DAG.getTarget().Options.EmulatedTLS) 2082 return LowerToTLSEmulatedModel(GA, DAG); 2083 2084 SDLoc DL(GA); 2085 const GlobalValue *GV = GA->getGlobal(); 2086 EVT PtrVT = getPointerTy(DAG.getDataLayout()); 2087 2088 TLSModel::Model model = getTargetMachine().getTLSModel(GV); 2089 2090 if (model == TLSModel::GeneralDynamic || model == TLSModel::LocalDynamic) { 2091 // General Dynamic and Local Dynamic TLS Model. 2092 unsigned Flag = (model == TLSModel::LocalDynamic) ? MipsII::MO_TLSLDM 2093 : MipsII::MO_TLSGD; 2094 2095 SDValue TGA = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, Flag); 2096 SDValue Argument = DAG.getNode(MipsISD::Wrapper, DL, PtrVT, 2097 getGlobalReg(DAG, PtrVT), TGA); 2098 unsigned PtrSize = PtrVT.getSizeInBits(); 2099 IntegerType *PtrTy = Type::getIntNTy(*DAG.getContext(), PtrSize); 2100 2101 SDValue TlsGetAddr = DAG.getExternalSymbol("__tls_get_addr", PtrVT); 2102 2103 ArgListTy Args; 2104 ArgListEntry Entry; 2105 Entry.Node = Argument; 2106 Entry.Ty = PtrTy; 2107 Args.push_back(Entry); 2108 2109 TargetLowering::CallLoweringInfo CLI(DAG); 2110 CLI.setDebugLoc(DL) 2111 .setChain(DAG.getEntryNode()) 2112 .setLibCallee(CallingConv::C, PtrTy, TlsGetAddr, std::move(Args)); 2113 std::pair<SDValue, SDValue> CallResult = LowerCallTo(CLI); 2114 2115 SDValue Ret = CallResult.first; 2116 2117 if (model != TLSModel::LocalDynamic) 2118 return Ret; 2119 2120 SDValue TGAHi = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, 2121 MipsII::MO_DTPREL_HI); 2122 SDValue Hi = DAG.getNode(MipsISD::Hi, DL, PtrVT, TGAHi); 2123 SDValue TGALo = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, 2124 MipsII::MO_DTPREL_LO); 2125 SDValue Lo = DAG.getNode(MipsISD::Lo, DL, PtrVT, TGALo); 2126 SDValue Add = DAG.getNode(ISD::ADD, DL, PtrVT, Hi, Ret); 2127 return DAG.getNode(ISD::ADD, DL, PtrVT, Add, Lo); 2128 } 2129 2130 SDValue Offset; 2131 if (model == TLSModel::InitialExec) { 2132 // Initial Exec TLS Model 2133 SDValue TGA = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, 2134 MipsII::MO_GOTTPREL); 2135 TGA = DAG.getNode(MipsISD::Wrapper, DL, PtrVT, getGlobalReg(DAG, PtrVT), 2136 TGA); 2137 Offset = 2138 DAG.getLoad(PtrVT, DL, DAG.getEntryNode(), TGA, MachinePointerInfo()); 2139 } else { 2140 // Local Exec TLS Model 2141 assert(model == TLSModel::LocalExec); 2142 SDValue TGAHi = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, 2143 MipsII::MO_TPREL_HI); 2144 SDValue TGALo = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, 2145 MipsII::MO_TPREL_LO); 2146 SDValue Hi = DAG.getNode(MipsISD::Hi, DL, PtrVT, TGAHi); 2147 SDValue Lo = DAG.getNode(MipsISD::Lo, DL, PtrVT, TGALo); 2148 Offset = DAG.getNode(ISD::ADD, DL, PtrVT, Hi, Lo); 2149 } 2150 2151 SDValue ThreadPointer = DAG.getNode(MipsISD::ThreadPointer, DL, PtrVT); 2152 return DAG.getNode(ISD::ADD, DL, PtrVT, ThreadPointer, Offset); 2153 } 2154 2155 SDValue MipsTargetLowering:: 2156 lowerJumpTable(SDValue Op, SelectionDAG &DAG) const 2157 { 2158 JumpTableSDNode *N = cast<JumpTableSDNode>(Op); 2159 EVT Ty = Op.getValueType(); 2160 2161 if (!isPositionIndependent()) 2162 return Subtarget.hasSym32() ? getAddrNonPIC(N, SDLoc(N), Ty, DAG) 2163 : getAddrNonPICSym64(N, SDLoc(N), Ty, DAG); 2164 2165 return getAddrLocal(N, SDLoc(N), Ty, DAG, ABI.IsN32() || ABI.IsN64()); 2166 } 2167 2168 SDValue MipsTargetLowering:: 2169 lowerConstantPool(SDValue Op, SelectionDAG &DAG) const 2170 { 2171 ConstantPoolSDNode *N = cast<ConstantPoolSDNode>(Op); 2172 EVT Ty = Op.getValueType(); 2173 2174 if (!isPositionIndependent()) { 2175 const MipsTargetObjectFile *TLOF = 2176 static_cast<const MipsTargetObjectFile *>( 2177 getTargetMachine().getObjFileLowering()); 2178 2179 if (TLOF->IsConstantInSmallSection(DAG.getDataLayout(), N->getConstVal(), 2180 getTargetMachine())) 2181 // %gp_rel relocation 2182 return getAddrGPRel(N, SDLoc(N), Ty, DAG, ABI.IsN64()); 2183 2184 return Subtarget.hasSym32() ? getAddrNonPIC(N, SDLoc(N), Ty, DAG) 2185 : getAddrNonPICSym64(N, SDLoc(N), Ty, DAG); 2186 } 2187 2188 return getAddrLocal(N, SDLoc(N), Ty, DAG, ABI.IsN32() || ABI.IsN64()); 2189 } 2190 2191 SDValue MipsTargetLowering::lowerVASTART(SDValue Op, SelectionDAG &DAG) const { 2192 MachineFunction &MF = DAG.getMachineFunction(); 2193 MipsFunctionInfo *FuncInfo = MF.getInfo<MipsFunctionInfo>(); 2194 2195 SDLoc DL(Op); 2196 SDValue FI = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), 2197 getPointerTy(MF.getDataLayout())); 2198 2199 // vastart just stores the address of the VarArgsFrameIndex slot into the 2200 // memory location argument. 2201 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue(); 2202 return DAG.getStore(Op.getOperand(0), DL, FI, Op.getOperand(1), 2203 MachinePointerInfo(SV)); 2204 } 2205 2206 SDValue MipsTargetLowering::lowerVAARG(SDValue Op, SelectionDAG &DAG) const { 2207 SDNode *Node = Op.getNode(); 2208 EVT VT = Node->getValueType(0); 2209 SDValue Chain = Node->getOperand(0); 2210 SDValue VAListPtr = Node->getOperand(1); 2211 unsigned Align = Node->getConstantOperandVal(3); 2212 const Value *SV = cast<SrcValueSDNode>(Node->getOperand(2))->getValue(); 2213 SDLoc DL(Node); 2214 unsigned ArgSlotSizeInBytes = (ABI.IsN32() || ABI.IsN64()) ? 8 : 4; 2215 2216 SDValue VAListLoad = DAG.getLoad(getPointerTy(DAG.getDataLayout()), DL, Chain, 2217 VAListPtr, MachinePointerInfo(SV)); 2218 SDValue VAList = VAListLoad; 2219 2220 // Re-align the pointer if necessary. 2221 // It should only ever be necessary for 64-bit types on O32 since the minimum 2222 // argument alignment is the same as the maximum type alignment for N32/N64. 2223 // 2224 // FIXME: We currently align too often. The code generator doesn't notice 2225 // when the pointer is still aligned from the last va_arg (or pair of 2226 // va_args for the i64 on O32 case). 2227 if (Align > getMinStackArgumentAlignment()) { 2228 assert(((Align & (Align-1)) == 0) && "Expected Align to be a power of 2"); 2229 2230 VAList = DAG.getNode(ISD::ADD, DL, VAList.getValueType(), VAList, 2231 DAG.getConstant(Align - 1, DL, VAList.getValueType())); 2232 2233 VAList = DAG.getNode(ISD::AND, DL, VAList.getValueType(), VAList, 2234 DAG.getConstant(-(int64_t)Align, DL, 2235 VAList.getValueType())); 2236 } 2237 2238 // Increment the pointer, VAList, to the next vaarg. 2239 auto &TD = DAG.getDataLayout(); 2240 unsigned ArgSizeInBytes = 2241 TD.getTypeAllocSize(VT.getTypeForEVT(*DAG.getContext())); 2242 SDValue Tmp3 = 2243 DAG.getNode(ISD::ADD, DL, VAList.getValueType(), VAList, 2244 DAG.getConstant(alignTo(ArgSizeInBytes, ArgSlotSizeInBytes), 2245 DL, VAList.getValueType())); 2246 // Store the incremented VAList to the legalized pointer 2247 Chain = DAG.getStore(VAListLoad.getValue(1), DL, Tmp3, VAListPtr, 2248 MachinePointerInfo(SV)); 2249 2250 // In big-endian mode we must adjust the pointer when the load size is smaller 2251 // than the argument slot size. We must also reduce the known alignment to 2252 // match. For example in the N64 ABI, we must add 4 bytes to the offset to get 2253 // the correct half of the slot, and reduce the alignment from 8 (slot 2254 // alignment) down to 4 (type alignment). 2255 if (!Subtarget.isLittle() && ArgSizeInBytes < ArgSlotSizeInBytes) { 2256 unsigned Adjustment = ArgSlotSizeInBytes - ArgSizeInBytes; 2257 VAList = DAG.getNode(ISD::ADD, DL, VAListPtr.getValueType(), VAList, 2258 DAG.getIntPtrConstant(Adjustment, DL)); 2259 } 2260 // Load the actual argument out of the pointer VAList 2261 return DAG.getLoad(VT, DL, Chain, VAList, MachinePointerInfo()); 2262 } 2263 2264 static SDValue lowerFCOPYSIGN32(SDValue Op, SelectionDAG &DAG, 2265 bool HasExtractInsert) { 2266 EVT TyX = Op.getOperand(0).getValueType(); 2267 EVT TyY = Op.getOperand(1).getValueType(); 2268 SDLoc DL(Op); 2269 SDValue Const1 = DAG.getConstant(1, DL, MVT::i32); 2270 SDValue Const31 = DAG.getConstant(31, DL, MVT::i32); 2271 SDValue Res; 2272 2273 // If operand is of type f64, extract the upper 32-bit. Otherwise, bitcast it 2274 // to i32. 2275 SDValue X = (TyX == MVT::f32) ? 2276 DAG.getNode(ISD::BITCAST, DL, MVT::i32, Op.getOperand(0)) : 2277 DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32, Op.getOperand(0), 2278 Const1); 2279 SDValue Y = (TyY == MVT::f32) ? 2280 DAG.getNode(ISD::BITCAST, DL, MVT::i32, Op.getOperand(1)) : 2281 DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32, Op.getOperand(1), 2282 Const1); 2283 2284 if (HasExtractInsert) { 2285 // ext E, Y, 31, 1 ; extract bit31 of Y 2286 // ins X, E, 31, 1 ; insert extracted bit at bit31 of X 2287 SDValue E = DAG.getNode(MipsISD::Ext, DL, MVT::i32, Y, Const31, Const1); 2288 Res = DAG.getNode(MipsISD::Ins, DL, MVT::i32, E, Const31, Const1, X); 2289 } else { 2290 // sll SllX, X, 1 2291 // srl SrlX, SllX, 1 2292 // srl SrlY, Y, 31 2293 // sll SllY, SrlX, 31 2294 // or Or, SrlX, SllY 2295 SDValue SllX = DAG.getNode(ISD::SHL, DL, MVT::i32, X, Const1); 2296 SDValue SrlX = DAG.getNode(ISD::SRL, DL, MVT::i32, SllX, Const1); 2297 SDValue SrlY = DAG.getNode(ISD::SRL, DL, MVT::i32, Y, Const31); 2298 SDValue SllY = DAG.getNode(ISD::SHL, DL, MVT::i32, SrlY, Const31); 2299 Res = DAG.getNode(ISD::OR, DL, MVT::i32, SrlX, SllY); 2300 } 2301 2302 if (TyX == MVT::f32) 2303 return DAG.getNode(ISD::BITCAST, DL, Op.getOperand(0).getValueType(), Res); 2304 2305 SDValue LowX = DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32, 2306 Op.getOperand(0), 2307 DAG.getConstant(0, DL, MVT::i32)); 2308 return DAG.getNode(MipsISD::BuildPairF64, DL, MVT::f64, LowX, Res); 2309 } 2310 2311 static SDValue lowerFCOPYSIGN64(SDValue Op, SelectionDAG &DAG, 2312 bool HasExtractInsert) { 2313 unsigned WidthX = Op.getOperand(0).getValueSizeInBits(); 2314 unsigned WidthY = Op.getOperand(1).getValueSizeInBits(); 2315 EVT TyX = MVT::getIntegerVT(WidthX), TyY = MVT::getIntegerVT(WidthY); 2316 SDLoc DL(Op); 2317 SDValue Const1 = DAG.getConstant(1, DL, MVT::i32); 2318 2319 // Bitcast to integer nodes. 2320 SDValue X = DAG.getNode(ISD::BITCAST, DL, TyX, Op.getOperand(0)); 2321 SDValue Y = DAG.getNode(ISD::BITCAST, DL, TyY, Op.getOperand(1)); 2322 2323 if (HasExtractInsert) { 2324 // ext E, Y, width(Y) - 1, 1 ; extract bit width(Y)-1 of Y 2325 // ins X, E, width(X) - 1, 1 ; insert extracted bit at bit width(X)-1 of X 2326 SDValue E = DAG.getNode(MipsISD::Ext, DL, TyY, Y, 2327 DAG.getConstant(WidthY - 1, DL, MVT::i32), Const1); 2328 2329 if (WidthX > WidthY) 2330 E = DAG.getNode(ISD::ZERO_EXTEND, DL, TyX, E); 2331 else if (WidthY > WidthX) 2332 E = DAG.getNode(ISD::TRUNCATE, DL, TyX, E); 2333 2334 SDValue I = DAG.getNode(MipsISD::Ins, DL, TyX, E, 2335 DAG.getConstant(WidthX - 1, DL, MVT::i32), Const1, 2336 X); 2337 return DAG.getNode(ISD::BITCAST, DL, Op.getOperand(0).getValueType(), I); 2338 } 2339 2340 // (d)sll SllX, X, 1 2341 // (d)srl SrlX, SllX, 1 2342 // (d)srl SrlY, Y, width(Y)-1 2343 // (d)sll SllY, SrlX, width(Y)-1 2344 // or Or, SrlX, SllY 2345 SDValue SllX = DAG.getNode(ISD::SHL, DL, TyX, X, Const1); 2346 SDValue SrlX = DAG.getNode(ISD::SRL, DL, TyX, SllX, Const1); 2347 SDValue SrlY = DAG.getNode(ISD::SRL, DL, TyY, Y, 2348 DAG.getConstant(WidthY - 1, DL, MVT::i32)); 2349 2350 if (WidthX > WidthY) 2351 SrlY = DAG.getNode(ISD::ZERO_EXTEND, DL, TyX, SrlY); 2352 else if (WidthY > WidthX) 2353 SrlY = DAG.getNode(ISD::TRUNCATE, DL, TyX, SrlY); 2354 2355 SDValue SllY = DAG.getNode(ISD::SHL, DL, TyX, SrlY, 2356 DAG.getConstant(WidthX - 1, DL, MVT::i32)); 2357 SDValue Or = DAG.getNode(ISD::OR, DL, TyX, SrlX, SllY); 2358 return DAG.getNode(ISD::BITCAST, DL, Op.getOperand(0).getValueType(), Or); 2359 } 2360 2361 SDValue 2362 MipsTargetLowering::lowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const { 2363 if (Subtarget.isGP64bit()) 2364 return lowerFCOPYSIGN64(Op, DAG, Subtarget.hasExtractInsert()); 2365 2366 return lowerFCOPYSIGN32(Op, DAG, Subtarget.hasExtractInsert()); 2367 } 2368 2369 SDValue MipsTargetLowering:: 2370 lowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const { 2371 // check the depth 2372 assert((cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue() == 0) && 2373 "Frame address can only be determined for current frame."); 2374 2375 MachineFrameInfo &MFI = DAG.getMachineFunction().getFrameInfo(); 2376 MFI.setFrameAddressIsTaken(true); 2377 EVT VT = Op.getValueType(); 2378 SDLoc DL(Op); 2379 SDValue FrameAddr = DAG.getCopyFromReg( 2380 DAG.getEntryNode(), DL, ABI.IsN64() ? Mips::FP_64 : Mips::FP, VT); 2381 return FrameAddr; 2382 } 2383 2384 SDValue MipsTargetLowering::lowerRETURNADDR(SDValue Op, 2385 SelectionDAG &DAG) const { 2386 if (verifyReturnAddressArgumentIsConstant(Op, DAG)) 2387 return SDValue(); 2388 2389 // check the depth 2390 assert((cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue() == 0) && 2391 "Return address can be determined only for current frame."); 2392 2393 MachineFunction &MF = DAG.getMachineFunction(); 2394 MachineFrameInfo &MFI = MF.getFrameInfo(); 2395 MVT VT = Op.getSimpleValueType(); 2396 unsigned RA = ABI.IsN64() ? Mips::RA_64 : Mips::RA; 2397 MFI.setReturnAddressIsTaken(true); 2398 2399 // Return RA, which contains the return address. Mark it an implicit live-in. 2400 unsigned Reg = MF.addLiveIn(RA, getRegClassFor(VT)); 2401 return DAG.getCopyFromReg(DAG.getEntryNode(), SDLoc(Op), Reg, VT); 2402 } 2403 2404 // An EH_RETURN is the result of lowering llvm.eh.return which in turn is 2405 // generated from __builtin_eh_return (offset, handler) 2406 // The effect of this is to adjust the stack pointer by "offset" 2407 // and then branch to "handler". 2408 SDValue MipsTargetLowering::lowerEH_RETURN(SDValue Op, SelectionDAG &DAG) 2409 const { 2410 MachineFunction &MF = DAG.getMachineFunction(); 2411 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>(); 2412 2413 MipsFI->setCallsEhReturn(); 2414 SDValue Chain = Op.getOperand(0); 2415 SDValue Offset = Op.getOperand(1); 2416 SDValue Handler = Op.getOperand(2); 2417 SDLoc DL(Op); 2418 EVT Ty = ABI.IsN64() ? MVT::i64 : MVT::i32; 2419 2420 // Store stack offset in V1, store jump target in V0. Glue CopyToReg and 2421 // EH_RETURN nodes, so that instructions are emitted back-to-back. 2422 unsigned OffsetReg = ABI.IsN64() ? Mips::V1_64 : Mips::V1; 2423 unsigned AddrReg = ABI.IsN64() ? Mips::V0_64 : Mips::V0; 2424 Chain = DAG.getCopyToReg(Chain, DL, OffsetReg, Offset, SDValue()); 2425 Chain = DAG.getCopyToReg(Chain, DL, AddrReg, Handler, Chain.getValue(1)); 2426 return DAG.getNode(MipsISD::EH_RETURN, DL, MVT::Other, Chain, 2427 DAG.getRegister(OffsetReg, Ty), 2428 DAG.getRegister(AddrReg, getPointerTy(MF.getDataLayout())), 2429 Chain.getValue(1)); 2430 } 2431 2432 SDValue MipsTargetLowering::lowerATOMIC_FENCE(SDValue Op, 2433 SelectionDAG &DAG) const { 2434 // FIXME: Need pseudo-fence for 'singlethread' fences 2435 // FIXME: Set SType for weaker fences where supported/appropriate. 2436 unsigned SType = 0; 2437 SDLoc DL(Op); 2438 return DAG.getNode(MipsISD::Sync, DL, MVT::Other, Op.getOperand(0), 2439 DAG.getConstant(SType, DL, MVT::i32)); 2440 } 2441 2442 SDValue MipsTargetLowering::lowerShiftLeftParts(SDValue Op, 2443 SelectionDAG &DAG) const { 2444 SDLoc DL(Op); 2445 MVT VT = Subtarget.isGP64bit() ? MVT::i64 : MVT::i32; 2446 2447 SDValue Lo = Op.getOperand(0), Hi = Op.getOperand(1); 2448 SDValue Shamt = Op.getOperand(2); 2449 // if shamt < (VT.bits): 2450 // lo = (shl lo, shamt) 2451 // hi = (or (shl hi, shamt) (srl (srl lo, 1), ~shamt)) 2452 // else: 2453 // lo = 0 2454 // hi = (shl lo, shamt[4:0]) 2455 SDValue Not = DAG.getNode(ISD::XOR, DL, MVT::i32, Shamt, 2456 DAG.getConstant(-1, DL, MVT::i32)); 2457 SDValue ShiftRight1Lo = DAG.getNode(ISD::SRL, DL, VT, Lo, 2458 DAG.getConstant(1, DL, VT)); 2459 SDValue ShiftRightLo = DAG.getNode(ISD::SRL, DL, VT, ShiftRight1Lo, Not); 2460 SDValue ShiftLeftHi = DAG.getNode(ISD::SHL, DL, VT, Hi, Shamt); 2461 SDValue Or = DAG.getNode(ISD::OR, DL, VT, ShiftLeftHi, ShiftRightLo); 2462 SDValue ShiftLeftLo = DAG.getNode(ISD::SHL, DL, VT, Lo, Shamt); 2463 SDValue Cond = DAG.getNode(ISD::AND, DL, MVT::i32, Shamt, 2464 DAG.getConstant(VT.getSizeInBits(), DL, MVT::i32)); 2465 Lo = DAG.getNode(ISD::SELECT, DL, VT, Cond, 2466 DAG.getConstant(0, DL, VT), ShiftLeftLo); 2467 Hi = DAG.getNode(ISD::SELECT, DL, VT, Cond, ShiftLeftLo, Or); 2468 2469 SDValue Ops[2] = {Lo, Hi}; 2470 return DAG.getMergeValues(Ops, DL); 2471 } 2472 2473 SDValue MipsTargetLowering::lowerShiftRightParts(SDValue Op, SelectionDAG &DAG, 2474 bool IsSRA) const { 2475 SDLoc DL(Op); 2476 SDValue Lo = Op.getOperand(0), Hi = Op.getOperand(1); 2477 SDValue Shamt = Op.getOperand(2); 2478 MVT VT = Subtarget.isGP64bit() ? MVT::i64 : MVT::i32; 2479 2480 // if shamt < (VT.bits): 2481 // lo = (or (shl (shl hi, 1), ~shamt) (srl lo, shamt)) 2482 // if isSRA: 2483 // hi = (sra hi, shamt) 2484 // else: 2485 // hi = (srl hi, shamt) 2486 // else: 2487 // if isSRA: 2488 // lo = (sra hi, shamt[4:0]) 2489 // hi = (sra hi, 31) 2490 // else: 2491 // lo = (srl hi, shamt[4:0]) 2492 // hi = 0 2493 SDValue Not = DAG.getNode(ISD::XOR, DL, MVT::i32, Shamt, 2494 DAG.getConstant(-1, DL, MVT::i32)); 2495 SDValue ShiftLeft1Hi = DAG.getNode(ISD::SHL, DL, VT, Hi, 2496 DAG.getConstant(1, DL, VT)); 2497 SDValue ShiftLeftHi = DAG.getNode(ISD::SHL, DL, VT, ShiftLeft1Hi, Not); 2498 SDValue ShiftRightLo = DAG.getNode(ISD::SRL, DL, VT, Lo, Shamt); 2499 SDValue Or = DAG.getNode(ISD::OR, DL, VT, ShiftLeftHi, ShiftRightLo); 2500 SDValue ShiftRightHi = DAG.getNode(IsSRA ? ISD::SRA : ISD::SRL, 2501 DL, VT, Hi, Shamt); 2502 SDValue Cond = DAG.getNode(ISD::AND, DL, MVT::i32, Shamt, 2503 DAG.getConstant(VT.getSizeInBits(), DL, MVT::i32)); 2504 SDValue Ext = DAG.getNode(ISD::SRA, DL, VT, Hi, 2505 DAG.getConstant(VT.getSizeInBits() - 1, DL, VT)); 2506 Lo = DAG.getNode(ISD::SELECT, DL, VT, Cond, ShiftRightHi, Or); 2507 Hi = DAG.getNode(ISD::SELECT, DL, VT, Cond, 2508 IsSRA ? Ext : DAG.getConstant(0, DL, VT), ShiftRightHi); 2509 2510 SDValue Ops[2] = {Lo, Hi}; 2511 return DAG.getMergeValues(Ops, DL); 2512 } 2513 2514 static SDValue createLoadLR(unsigned Opc, SelectionDAG &DAG, LoadSDNode *LD, 2515 SDValue Chain, SDValue Src, unsigned Offset) { 2516 SDValue Ptr = LD->getBasePtr(); 2517 EVT VT = LD->getValueType(0), MemVT = LD->getMemoryVT(); 2518 EVT BasePtrVT = Ptr.getValueType(); 2519 SDLoc DL(LD); 2520 SDVTList VTList = DAG.getVTList(VT, MVT::Other); 2521 2522 if (Offset) 2523 Ptr = DAG.getNode(ISD::ADD, DL, BasePtrVT, Ptr, 2524 DAG.getConstant(Offset, DL, BasePtrVT)); 2525 2526 SDValue Ops[] = { Chain, Ptr, Src }; 2527 return DAG.getMemIntrinsicNode(Opc, DL, VTList, Ops, MemVT, 2528 LD->getMemOperand()); 2529 } 2530 2531 // Expand an unaligned 32 or 64-bit integer load node. 2532 SDValue MipsTargetLowering::lowerLOAD(SDValue Op, SelectionDAG &DAG) const { 2533 LoadSDNode *LD = cast<LoadSDNode>(Op); 2534 EVT MemVT = LD->getMemoryVT(); 2535 2536 if (Subtarget.systemSupportsUnalignedAccess()) 2537 return Op; 2538 2539 // Return if load is aligned or if MemVT is neither i32 nor i64. 2540 if ((LD->getAlignment() >= MemVT.getSizeInBits() / 8) || 2541 ((MemVT != MVT::i32) && (MemVT != MVT::i64))) 2542 return SDValue(); 2543 2544 bool IsLittle = Subtarget.isLittle(); 2545 EVT VT = Op.getValueType(); 2546 ISD::LoadExtType ExtType = LD->getExtensionType(); 2547 SDValue Chain = LD->getChain(), Undef = DAG.getUNDEF(VT); 2548 2549 assert((VT == MVT::i32) || (VT == MVT::i64)); 2550 2551 // Expand 2552 // (set dst, (i64 (load baseptr))) 2553 // to 2554 // (set tmp, (ldl (add baseptr, 7), undef)) 2555 // (set dst, (ldr baseptr, tmp)) 2556 if ((VT == MVT::i64) && (ExtType == ISD::NON_EXTLOAD)) { 2557 SDValue LDL = createLoadLR(MipsISD::LDL, DAG, LD, Chain, Undef, 2558 IsLittle ? 7 : 0); 2559 return createLoadLR(MipsISD::LDR, DAG, LD, LDL.getValue(1), LDL, 2560 IsLittle ? 0 : 7); 2561 } 2562 2563 SDValue LWL = createLoadLR(MipsISD::LWL, DAG, LD, Chain, Undef, 2564 IsLittle ? 3 : 0); 2565 SDValue LWR = createLoadLR(MipsISD::LWR, DAG, LD, LWL.getValue(1), LWL, 2566 IsLittle ? 0 : 3); 2567 2568 // Expand 2569 // (set dst, (i32 (load baseptr))) or 2570 // (set dst, (i64 (sextload baseptr))) or 2571 // (set dst, (i64 (extload baseptr))) 2572 // to 2573 // (set tmp, (lwl (add baseptr, 3), undef)) 2574 // (set dst, (lwr baseptr, tmp)) 2575 if ((VT == MVT::i32) || (ExtType == ISD::SEXTLOAD) || 2576 (ExtType == ISD::EXTLOAD)) 2577 return LWR; 2578 2579 assert((VT == MVT::i64) && (ExtType == ISD::ZEXTLOAD)); 2580 2581 // Expand 2582 // (set dst, (i64 (zextload baseptr))) 2583 // to 2584 // (set tmp0, (lwl (add baseptr, 3), undef)) 2585 // (set tmp1, (lwr baseptr, tmp0)) 2586 // (set tmp2, (shl tmp1, 32)) 2587 // (set dst, (srl tmp2, 32)) 2588 SDLoc DL(LD); 2589 SDValue Const32 = DAG.getConstant(32, DL, MVT::i32); 2590 SDValue SLL = DAG.getNode(ISD::SHL, DL, MVT::i64, LWR, Const32); 2591 SDValue SRL = DAG.getNode(ISD::SRL, DL, MVT::i64, SLL, Const32); 2592 SDValue Ops[] = { SRL, LWR.getValue(1) }; 2593 return DAG.getMergeValues(Ops, DL); 2594 } 2595 2596 static SDValue createStoreLR(unsigned Opc, SelectionDAG &DAG, StoreSDNode *SD, 2597 SDValue Chain, unsigned Offset) { 2598 SDValue Ptr = SD->getBasePtr(), Value = SD->getValue(); 2599 EVT MemVT = SD->getMemoryVT(), BasePtrVT = Ptr.getValueType(); 2600 SDLoc DL(SD); 2601 SDVTList VTList = DAG.getVTList(MVT::Other); 2602 2603 if (Offset) 2604 Ptr = DAG.getNode(ISD::ADD, DL, BasePtrVT, Ptr, 2605 DAG.getConstant(Offset, DL, BasePtrVT)); 2606 2607 SDValue Ops[] = { Chain, Value, Ptr }; 2608 return DAG.getMemIntrinsicNode(Opc, DL, VTList, Ops, MemVT, 2609 SD->getMemOperand()); 2610 } 2611 2612 // Expand an unaligned 32 or 64-bit integer store node. 2613 static SDValue lowerUnalignedIntStore(StoreSDNode *SD, SelectionDAG &DAG, 2614 bool IsLittle) { 2615 SDValue Value = SD->getValue(), Chain = SD->getChain(); 2616 EVT VT = Value.getValueType(); 2617 2618 // Expand 2619 // (store val, baseptr) or 2620 // (truncstore val, baseptr) 2621 // to 2622 // (swl val, (add baseptr, 3)) 2623 // (swr val, baseptr) 2624 if ((VT == MVT::i32) || SD->isTruncatingStore()) { 2625 SDValue SWL = createStoreLR(MipsISD::SWL, DAG, SD, Chain, 2626 IsLittle ? 3 : 0); 2627 return createStoreLR(MipsISD::SWR, DAG, SD, SWL, IsLittle ? 0 : 3); 2628 } 2629 2630 assert(VT == MVT::i64); 2631 2632 // Expand 2633 // (store val, baseptr) 2634 // to 2635 // (sdl val, (add baseptr, 7)) 2636 // (sdr val, baseptr) 2637 SDValue SDL = createStoreLR(MipsISD::SDL, DAG, SD, Chain, IsLittle ? 7 : 0); 2638 return createStoreLR(MipsISD::SDR, DAG, SD, SDL, IsLittle ? 0 : 7); 2639 } 2640 2641 // Lower (store (fp_to_sint $fp) $ptr) to (store (TruncIntFP $fp), $ptr). 2642 static SDValue lowerFP_TO_SINT_STORE(StoreSDNode *SD, SelectionDAG &DAG) { 2643 SDValue Val = SD->getValue(); 2644 2645 if (Val.getOpcode() != ISD::FP_TO_SINT) 2646 return SDValue(); 2647 2648 EVT FPTy = EVT::getFloatingPointVT(Val.getValueSizeInBits()); 2649 SDValue Tr = DAG.getNode(MipsISD::TruncIntFP, SDLoc(Val), FPTy, 2650 Val.getOperand(0)); 2651 return DAG.getStore(SD->getChain(), SDLoc(SD), Tr, SD->getBasePtr(), 2652 SD->getPointerInfo(), SD->getAlignment(), 2653 SD->getMemOperand()->getFlags()); 2654 } 2655 2656 SDValue MipsTargetLowering::lowerSTORE(SDValue Op, SelectionDAG &DAG) const { 2657 StoreSDNode *SD = cast<StoreSDNode>(Op); 2658 EVT MemVT = SD->getMemoryVT(); 2659 2660 // Lower unaligned integer stores. 2661 if (!Subtarget.systemSupportsUnalignedAccess() && 2662 (SD->getAlignment() < MemVT.getSizeInBits() / 8) && 2663 ((MemVT == MVT::i32) || (MemVT == MVT::i64))) 2664 return lowerUnalignedIntStore(SD, DAG, Subtarget.isLittle()); 2665 2666 return lowerFP_TO_SINT_STORE(SD, DAG); 2667 } 2668 2669 SDValue MipsTargetLowering::lowerEH_DWARF_CFA(SDValue Op, 2670 SelectionDAG &DAG) const { 2671 2672 // Return a fixed StackObject with offset 0 which points to the old stack 2673 // pointer. 2674 MachineFrameInfo &MFI = DAG.getMachineFunction().getFrameInfo(); 2675 EVT ValTy = Op->getValueType(0); 2676 int FI = MFI.CreateFixedObject(Op.getValueSizeInBits() / 8, 0, false); 2677 return DAG.getFrameIndex(FI, ValTy); 2678 } 2679 2680 SDValue MipsTargetLowering::lowerFP_TO_SINT(SDValue Op, 2681 SelectionDAG &DAG) const { 2682 EVT FPTy = EVT::getFloatingPointVT(Op.getValueSizeInBits()); 2683 SDValue Trunc = DAG.getNode(MipsISD::TruncIntFP, SDLoc(Op), FPTy, 2684 Op.getOperand(0)); 2685 return DAG.getNode(ISD::BITCAST, SDLoc(Op), Op.getValueType(), Trunc); 2686 } 2687 2688 //===----------------------------------------------------------------------===// 2689 // Calling Convention Implementation 2690 //===----------------------------------------------------------------------===// 2691 2692 //===----------------------------------------------------------------------===// 2693 // TODO: Implement a generic logic using tblgen that can support this. 2694 // Mips O32 ABI rules: 2695 // --- 2696 // i32 - Passed in A0, A1, A2, A3 and stack 2697 // f32 - Only passed in f32 registers if no int reg has been used yet to hold 2698 // an argument. Otherwise, passed in A1, A2, A3 and stack. 2699 // f64 - Only passed in two aliased f32 registers if no int reg has been used 2700 // yet to hold an argument. Otherwise, use A2, A3 and stack. If A1 is 2701 // not used, it must be shadowed. If only A3 is available, shadow it and 2702 // go to stack. 2703 // vXiX - Received as scalarized i32s, passed in A0 - A3 and the stack. 2704 // vXf32 - Passed in either a pair of registers {A0, A1}, {A2, A3} or {A0 - A3} 2705 // with the remainder spilled to the stack. 2706 // vXf64 - Passed in either {A0, A1, A2, A3} or {A2, A3} and in both cases 2707 // spilling the remainder to the stack. 2708 // 2709 // For vararg functions, all arguments are passed in A0, A1, A2, A3 and stack. 2710 //===----------------------------------------------------------------------===// 2711 2712 static bool CC_MipsO32(unsigned ValNo, MVT ValVT, MVT LocVT, 2713 CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, 2714 CCState &State, ArrayRef<MCPhysReg> F64Regs) { 2715 const MipsSubtarget &Subtarget = static_cast<const MipsSubtarget &>( 2716 State.getMachineFunction().getSubtarget()); 2717 2718 static const MCPhysReg IntRegs[] = { Mips::A0, Mips::A1, Mips::A2, Mips::A3 }; 2719 2720 const MipsCCState * MipsState = static_cast<MipsCCState *>(&State); 2721 2722 static const MCPhysReg F32Regs[] = { Mips::F12, Mips::F14 }; 2723 2724 static const MCPhysReg FloatVectorIntRegs[] = { Mips::A0, Mips::A2 }; 2725 2726 // Do not process byval args here. 2727 if (ArgFlags.isByVal()) 2728 return true; 2729 2730 // Promote i8 and i16 2731 if (ArgFlags.isInReg() && !Subtarget.isLittle()) { 2732 if (LocVT == MVT::i8 || LocVT == MVT::i16 || LocVT == MVT::i32) { 2733 LocVT = MVT::i32; 2734 if (ArgFlags.isSExt()) 2735 LocInfo = CCValAssign::SExtUpper; 2736 else if (ArgFlags.isZExt()) 2737 LocInfo = CCValAssign::ZExtUpper; 2738 else 2739 LocInfo = CCValAssign::AExtUpper; 2740 } 2741 } 2742 2743 // Promote i8 and i16 2744 if (LocVT == MVT::i8 || LocVT == MVT::i16) { 2745 LocVT = MVT::i32; 2746 if (ArgFlags.isSExt()) 2747 LocInfo = CCValAssign::SExt; 2748 else if (ArgFlags.isZExt()) 2749 LocInfo = CCValAssign::ZExt; 2750 else 2751 LocInfo = CCValAssign::AExt; 2752 } 2753 2754 unsigned Reg; 2755 2756 // f32 and f64 are allocated in A0, A1, A2, A3 when either of the following 2757 // is true: function is vararg, argument is 3rd or higher, there is previous 2758 // argument which is not f32 or f64. 2759 bool AllocateFloatsInIntReg = State.isVarArg() || ValNo > 1 || 2760 State.getFirstUnallocated(F32Regs) != ValNo; 2761 unsigned OrigAlign = ArgFlags.getOrigAlign(); 2762 bool isI64 = (ValVT == MVT::i32 && OrigAlign == 8); 2763 bool isVectorFloat = MipsState->WasOriginalArgVectorFloat(ValNo); 2764 2765 // The MIPS vector ABI for floats passes them in a pair of registers 2766 if (ValVT == MVT::i32 && isVectorFloat) { 2767 // This is the start of an vector that was scalarized into an unknown number 2768 // of components. It doesn't matter how many there are. Allocate one of the 2769 // notional 8 byte aligned registers which map onto the argument stack, and 2770 // shadow the register lost to alignment requirements. 2771 if (ArgFlags.isSplit()) { 2772 Reg = State.AllocateReg(FloatVectorIntRegs); 2773 if (Reg == Mips::A2) 2774 State.AllocateReg(Mips::A1); 2775 else if (Reg == 0) 2776 State.AllocateReg(Mips::A3); 2777 } else { 2778 // If we're an intermediate component of the split, we can just attempt to 2779 // allocate a register directly. 2780 Reg = State.AllocateReg(IntRegs); 2781 } 2782 } else if (ValVT == MVT::i32 || (ValVT == MVT::f32 && AllocateFloatsInIntReg)) { 2783 Reg = State.AllocateReg(IntRegs); 2784 // If this is the first part of an i64 arg, 2785 // the allocated register must be either A0 or A2. 2786 if (isI64 && (Reg == Mips::A1 || Reg == Mips::A3)) 2787 Reg = State.AllocateReg(IntRegs); 2788 LocVT = MVT::i32; 2789 } else if (ValVT == MVT::f64 && AllocateFloatsInIntReg) { 2790 // Allocate int register and shadow next int register. If first 2791 // available register is Mips::A1 or Mips::A3, shadow it too. 2792 Reg = State.AllocateReg(IntRegs); 2793 if (Reg == Mips::A1 || Reg == Mips::A3) 2794 Reg = State.AllocateReg(IntRegs); 2795 State.AllocateReg(IntRegs); 2796 LocVT = MVT::i32; 2797 } else if (ValVT.isFloatingPoint() && !AllocateFloatsInIntReg) { 2798 // we are guaranteed to find an available float register 2799 if (ValVT == MVT::f32) { 2800 Reg = State.AllocateReg(F32Regs); 2801 // Shadow int register 2802 State.AllocateReg(IntRegs); 2803 } else { 2804 Reg = State.AllocateReg(F64Regs); 2805 // Shadow int registers 2806 unsigned Reg2 = State.AllocateReg(IntRegs); 2807 if (Reg2 == Mips::A1 || Reg2 == Mips::A3) 2808 State.AllocateReg(IntRegs); 2809 State.AllocateReg(IntRegs); 2810 } 2811 } else 2812 llvm_unreachable("Cannot handle this ValVT."); 2813 2814 if (!Reg) { 2815 unsigned Offset = State.AllocateStack(ValVT.getStoreSize(), OrigAlign); 2816 State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo)); 2817 } else 2818 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); 2819 2820 return false; 2821 } 2822 2823 static bool CC_MipsO32_FP32(unsigned ValNo, MVT ValVT, 2824 MVT LocVT, CCValAssign::LocInfo LocInfo, 2825 ISD::ArgFlagsTy ArgFlags, CCState &State) { 2826 static const MCPhysReg F64Regs[] = { Mips::D6, Mips::D7 }; 2827 2828 return CC_MipsO32(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State, F64Regs); 2829 } 2830 2831 static bool CC_MipsO32_FP64(unsigned ValNo, MVT ValVT, 2832 MVT LocVT, CCValAssign::LocInfo LocInfo, 2833 ISD::ArgFlagsTy ArgFlags, CCState &State) { 2834 static const MCPhysReg F64Regs[] = { Mips::D12_64, Mips::D14_64 }; 2835 2836 return CC_MipsO32(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State, F64Regs); 2837 } 2838 2839 static bool CC_MipsO32(unsigned ValNo, MVT ValVT, MVT LocVT, 2840 CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, 2841 CCState &State) LLVM_ATTRIBUTE_UNUSED; 2842 2843 #include "MipsGenCallingConv.inc" 2844 2845 //===----------------------------------------------------------------------===// 2846 // Call Calling Convention Implementation 2847 //===----------------------------------------------------------------------===// 2848 2849 // Return next O32 integer argument register. 2850 static unsigned getNextIntArgReg(unsigned Reg) { 2851 assert((Reg == Mips::A0) || (Reg == Mips::A2)); 2852 return (Reg == Mips::A0) ? Mips::A1 : Mips::A3; 2853 } 2854 2855 SDValue MipsTargetLowering::passArgOnStack(SDValue StackPtr, unsigned Offset, 2856 SDValue Chain, SDValue Arg, 2857 const SDLoc &DL, bool IsTailCall, 2858 SelectionDAG &DAG) const { 2859 if (!IsTailCall) { 2860 SDValue PtrOff = 2861 DAG.getNode(ISD::ADD, DL, getPointerTy(DAG.getDataLayout()), StackPtr, 2862 DAG.getIntPtrConstant(Offset, DL)); 2863 return DAG.getStore(Chain, DL, Arg, PtrOff, MachinePointerInfo()); 2864 } 2865 2866 MachineFrameInfo &MFI = DAG.getMachineFunction().getFrameInfo(); 2867 int FI = MFI.CreateFixedObject(Arg.getValueSizeInBits() / 8, Offset, false); 2868 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy(DAG.getDataLayout())); 2869 return DAG.getStore(Chain, DL, Arg, FIN, MachinePointerInfo(), 2870 /* Alignment = */ 0, MachineMemOperand::MOVolatile); 2871 } 2872 2873 void MipsTargetLowering:: 2874 getOpndList(SmallVectorImpl<SDValue> &Ops, 2875 std::deque<std::pair<unsigned, SDValue>> &RegsToPass, 2876 bool IsPICCall, bool GlobalOrExternal, bool InternalLinkage, 2877 bool IsCallReloc, CallLoweringInfo &CLI, SDValue Callee, 2878 SDValue Chain) const { 2879 // Insert node "GP copy globalreg" before call to function. 2880 // 2881 // R_MIPS_CALL* operators (emitted when non-internal functions are called 2882 // in PIC mode) allow symbols to be resolved via lazy binding. 2883 // The lazy binding stub requires GP to point to the GOT. 2884 // Note that we don't need GP to point to the GOT for indirect calls 2885 // (when R_MIPS_CALL* is not used for the call) because Mips linker generates 2886 // lazy binding stub for a function only when R_MIPS_CALL* are the only relocs 2887 // used for the function (that is, Mips linker doesn't generate lazy binding 2888 // stub for a function whose address is taken in the program). 2889 if (IsPICCall && !InternalLinkage && IsCallReloc) { 2890 unsigned GPReg = ABI.IsN64() ? Mips::GP_64 : Mips::GP; 2891 EVT Ty = ABI.IsN64() ? MVT::i64 : MVT::i32; 2892 RegsToPass.push_back(std::make_pair(GPReg, getGlobalReg(CLI.DAG, Ty))); 2893 } 2894 2895 // Build a sequence of copy-to-reg nodes chained together with token 2896 // chain and flag operands which copy the outgoing args into registers. 2897 // The InFlag in necessary since all emitted instructions must be 2898 // stuck together. 2899 SDValue InFlag; 2900 2901 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) { 2902 Chain = CLI.DAG.getCopyToReg(Chain, CLI.DL, RegsToPass[i].first, 2903 RegsToPass[i].second, InFlag); 2904 InFlag = Chain.getValue(1); 2905 } 2906 2907 // Add argument registers to the end of the list so that they are 2908 // known live into the call. 2909 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) 2910 Ops.push_back(CLI.DAG.getRegister(RegsToPass[i].first, 2911 RegsToPass[i].second.getValueType())); 2912 2913 // Add a register mask operand representing the call-preserved registers. 2914 const TargetRegisterInfo *TRI = Subtarget.getRegisterInfo(); 2915 const uint32_t *Mask = 2916 TRI->getCallPreservedMask(CLI.DAG.getMachineFunction(), CLI.CallConv); 2917 assert(Mask && "Missing call preserved mask for calling convention"); 2918 if (Subtarget.inMips16HardFloat()) { 2919 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(CLI.Callee)) { 2920 StringRef Sym = G->getGlobal()->getName(); 2921 Function *F = G->getGlobal()->getParent()->getFunction(Sym); 2922 if (F && F->hasFnAttribute("__Mips16RetHelper")) { 2923 Mask = MipsRegisterInfo::getMips16RetHelperMask(); 2924 } 2925 } 2926 } 2927 Ops.push_back(CLI.DAG.getRegisterMask(Mask)); 2928 2929 if (InFlag.getNode()) 2930 Ops.push_back(InFlag); 2931 } 2932 2933 /// LowerCall - functions arguments are copied from virtual regs to 2934 /// (physical regs)/(stack frame), CALLSEQ_START and CALLSEQ_END are emitted. 2935 SDValue 2936 MipsTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI, 2937 SmallVectorImpl<SDValue> &InVals) const { 2938 SelectionDAG &DAG = CLI.DAG; 2939 SDLoc DL = CLI.DL; 2940 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs; 2941 SmallVectorImpl<SDValue> &OutVals = CLI.OutVals; 2942 SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins; 2943 SDValue Chain = CLI.Chain; 2944 SDValue Callee = CLI.Callee; 2945 bool &IsTailCall = CLI.IsTailCall; 2946 CallingConv::ID CallConv = CLI.CallConv; 2947 bool IsVarArg = CLI.IsVarArg; 2948 2949 MachineFunction &MF = DAG.getMachineFunction(); 2950 MachineFrameInfo &MFI = MF.getFrameInfo(); 2951 const TargetFrameLowering *TFL = Subtarget.getFrameLowering(); 2952 MipsFunctionInfo *FuncInfo = MF.getInfo<MipsFunctionInfo>(); 2953 bool IsPIC = isPositionIndependent(); 2954 2955 // Analyze operands of the call, assigning locations to each operand. 2956 SmallVector<CCValAssign, 16> ArgLocs; 2957 MipsCCState CCInfo( 2958 CallConv, IsVarArg, DAG.getMachineFunction(), ArgLocs, *DAG.getContext(), 2959 MipsCCState::getSpecialCallingConvForCallee(Callee.getNode(), Subtarget)); 2960 2961 // Allocate the reserved argument area. It seems strange to do this from the 2962 // caller side but removing it breaks the frame size calculation. 2963 CCInfo.AllocateStack(ABI.GetCalleeAllocdArgSizeInBytes(CallConv), 1); 2964 2965 const ExternalSymbolSDNode *ES = 2966 dyn_cast_or_null<const ExternalSymbolSDNode>(Callee.getNode()); 2967 CCInfo.AnalyzeCallOperands(Outs, CC_Mips, CLI.getArgs(), 2968 ES ? ES->getSymbol() : nullptr); 2969 2970 // Get a count of how many bytes are to be pushed on the stack. 2971 unsigned NextStackOffset = CCInfo.getNextStackOffset(); 2972 2973 // Check if it's really possible to do a tail call. Restrict it to functions 2974 // that are part of this compilation unit. 2975 bool InternalLinkage = false; 2976 if (IsTailCall) { 2977 IsTailCall = isEligibleForTailCallOptimization( 2978 CCInfo, NextStackOffset, *MF.getInfo<MipsFunctionInfo>()); 2979 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) { 2980 InternalLinkage = G->getGlobal()->hasInternalLinkage(); 2981 IsTailCall &= (InternalLinkage || G->getGlobal()->hasLocalLinkage() || 2982 G->getGlobal()->hasPrivateLinkage() || 2983 G->getGlobal()->hasHiddenVisibility() || 2984 G->getGlobal()->hasProtectedVisibility()); 2985 } 2986 } 2987 if (!IsTailCall && CLI.CS && CLI.CS.isMustTailCall()) 2988 report_fatal_error("failed to perform tail call elimination on a call " 2989 "site marked musttail"); 2990 2991 if (IsTailCall) 2992 ++NumTailCalls; 2993 2994 // Chain is the output chain of the last Load/Store or CopyToReg node. 2995 // ByValChain is the output chain of the last Memcpy node created for copying 2996 // byval arguments to the stack. 2997 unsigned StackAlignment = TFL->getStackAlignment(); 2998 NextStackOffset = alignTo(NextStackOffset, StackAlignment); 2999 SDValue NextStackOffsetVal = DAG.getIntPtrConstant(NextStackOffset, DL, true); 3000 3001 if (!IsTailCall) 3002 Chain = DAG.getCALLSEQ_START(Chain, NextStackOffset, 0, DL); 3003 3004 SDValue StackPtr = 3005 DAG.getCopyFromReg(Chain, DL, ABI.IsN64() ? Mips::SP_64 : Mips::SP, 3006 getPointerTy(DAG.getDataLayout())); 3007 3008 std::deque<std::pair<unsigned, SDValue>> RegsToPass; 3009 SmallVector<SDValue, 8> MemOpChains; 3010 3011 CCInfo.rewindByValRegsInfo(); 3012 3013 // Walk the register/memloc assignments, inserting copies/loads. 3014 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { 3015 SDValue Arg = OutVals[i]; 3016 CCValAssign &VA = ArgLocs[i]; 3017 MVT ValVT = VA.getValVT(), LocVT = VA.getLocVT(); 3018 ISD::ArgFlagsTy Flags = Outs[i].Flags; 3019 bool UseUpperBits = false; 3020 3021 // ByVal Arg. 3022 if (Flags.isByVal()) { 3023 unsigned FirstByValReg, LastByValReg; 3024 unsigned ByValIdx = CCInfo.getInRegsParamsProcessed(); 3025 CCInfo.getInRegsParamInfo(ByValIdx, FirstByValReg, LastByValReg); 3026 3027 assert(Flags.getByValSize() && 3028 "ByVal args of size 0 should have been ignored by front-end."); 3029 assert(ByValIdx < CCInfo.getInRegsParamsCount()); 3030 assert(!IsTailCall && 3031 "Do not tail-call optimize if there is a byval argument."); 3032 passByValArg(Chain, DL, RegsToPass, MemOpChains, StackPtr, MFI, DAG, Arg, 3033 FirstByValReg, LastByValReg, Flags, Subtarget.isLittle(), 3034 VA); 3035 CCInfo.nextInRegsParam(); 3036 continue; 3037 } 3038 3039 // Promote the value if needed. 3040 switch (VA.getLocInfo()) { 3041 default: 3042 llvm_unreachable("Unknown loc info!"); 3043 case CCValAssign::Full: 3044 if (VA.isRegLoc()) { 3045 if ((ValVT == MVT::f32 && LocVT == MVT::i32) || 3046 (ValVT == MVT::f64 && LocVT == MVT::i64) || 3047 (ValVT == MVT::i64 && LocVT == MVT::f64)) 3048 Arg = DAG.getNode(ISD::BITCAST, DL, LocVT, Arg); 3049 else if (ValVT == MVT::f64 && LocVT == MVT::i32) { 3050 SDValue Lo = DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32, 3051 Arg, DAG.getConstant(0, DL, MVT::i32)); 3052 SDValue Hi = DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32, 3053 Arg, DAG.getConstant(1, DL, MVT::i32)); 3054 if (!Subtarget.isLittle()) 3055 std::swap(Lo, Hi); 3056 unsigned LocRegLo = VA.getLocReg(); 3057 unsigned LocRegHigh = getNextIntArgReg(LocRegLo); 3058 RegsToPass.push_back(std::make_pair(LocRegLo, Lo)); 3059 RegsToPass.push_back(std::make_pair(LocRegHigh, Hi)); 3060 continue; 3061 } 3062 } 3063 break; 3064 case CCValAssign::BCvt: 3065 Arg = DAG.getNode(ISD::BITCAST, DL, LocVT, Arg); 3066 break; 3067 case CCValAssign::SExtUpper: 3068 UseUpperBits = true; 3069 LLVM_FALLTHROUGH; 3070 case CCValAssign::SExt: 3071 Arg = DAG.getNode(ISD::SIGN_EXTEND, DL, LocVT, Arg); 3072 break; 3073 case CCValAssign::ZExtUpper: 3074 UseUpperBits = true; 3075 LLVM_FALLTHROUGH; 3076 case CCValAssign::ZExt: 3077 Arg = DAG.getNode(ISD::ZERO_EXTEND, DL, LocVT, Arg); 3078 break; 3079 case CCValAssign::AExtUpper: 3080 UseUpperBits = true; 3081 LLVM_FALLTHROUGH; 3082 case CCValAssign::AExt: 3083 Arg = DAG.getNode(ISD::ANY_EXTEND, DL, LocVT, Arg); 3084 break; 3085 } 3086 3087 if (UseUpperBits) { 3088 unsigned ValSizeInBits = Outs[i].ArgVT.getSizeInBits(); 3089 unsigned LocSizeInBits = VA.getLocVT().getSizeInBits(); 3090 Arg = DAG.getNode( 3091 ISD::SHL, DL, VA.getLocVT(), Arg, 3092 DAG.getConstant(LocSizeInBits - ValSizeInBits, DL, VA.getLocVT())); 3093 } 3094 3095 // Arguments that can be passed on register must be kept at 3096 // RegsToPass vector 3097 if (VA.isRegLoc()) { 3098 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg)); 3099 continue; 3100 } 3101 3102 // Register can't get to this point... 3103 assert(VA.isMemLoc()); 3104 3105 // emit ISD::STORE whichs stores the 3106 // parameter value to a stack Location 3107 MemOpChains.push_back(passArgOnStack(StackPtr, VA.getLocMemOffset(), 3108 Chain, Arg, DL, IsTailCall, DAG)); 3109 } 3110 3111 // Transform all store nodes into one single node because all store 3112 // nodes are independent of each other. 3113 if (!MemOpChains.empty()) 3114 Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, MemOpChains); 3115 3116 // If the callee is a GlobalAddress/ExternalSymbol node (quite common, every 3117 // direct call is) turn it into a TargetGlobalAddress/TargetExternalSymbol 3118 // node so that legalize doesn't hack it. 3119 3120 EVT Ty = Callee.getValueType(); 3121 bool GlobalOrExternal = false, IsCallReloc = false; 3122 3123 // The long-calls feature is ignored in case of PIC. 3124 // While we do not support -mshared / -mno-shared properly, 3125 // ignore long-calls in case of -mabicalls too. 3126 if (!Subtarget.isABICalls() && !IsPIC) { 3127 // If the function should be called using "long call", 3128 // get its address into a register to prevent using 3129 // of the `jal` instruction for the direct call. 3130 if (auto *N = dyn_cast<ExternalSymbolSDNode>(Callee)) { 3131 if (Subtarget.useLongCalls()) 3132 Callee = Subtarget.hasSym32() 3133 ? getAddrNonPIC(N, SDLoc(N), Ty, DAG) 3134 : getAddrNonPICSym64(N, SDLoc(N), Ty, DAG); 3135 } else if (auto *N = dyn_cast<GlobalAddressSDNode>(Callee)) { 3136 bool UseLongCalls = Subtarget.useLongCalls(); 3137 // If the function has long-call/far/near attribute 3138 // it overrides command line switch pased to the backend. 3139 if (auto *F = dyn_cast<Function>(N->getGlobal())) { 3140 if (F->hasFnAttribute("long-call")) 3141 UseLongCalls = true; 3142 else if (F->hasFnAttribute("short-call")) 3143 UseLongCalls = false; 3144 } 3145 if (UseLongCalls) 3146 Callee = Subtarget.hasSym32() 3147 ? getAddrNonPIC(N, SDLoc(N), Ty, DAG) 3148 : getAddrNonPICSym64(N, SDLoc(N), Ty, DAG); 3149 } 3150 } 3151 3152 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) { 3153 if (IsPIC) { 3154 const GlobalValue *Val = G->getGlobal(); 3155 InternalLinkage = Val->hasInternalLinkage(); 3156 3157 if (InternalLinkage) 3158 Callee = getAddrLocal(G, DL, Ty, DAG, ABI.IsN32() || ABI.IsN64()); 3159 else if (LargeGOT) { 3160 Callee = getAddrGlobalLargeGOT(G, DL, Ty, DAG, MipsII::MO_CALL_HI16, 3161 MipsII::MO_CALL_LO16, Chain, 3162 FuncInfo->callPtrInfo(Val)); 3163 IsCallReloc = true; 3164 } else { 3165 Callee = getAddrGlobal(G, DL, Ty, DAG, MipsII::MO_GOT_CALL, Chain, 3166 FuncInfo->callPtrInfo(Val)); 3167 IsCallReloc = true; 3168 } 3169 } else 3170 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), DL, 3171 getPointerTy(DAG.getDataLayout()), 0, 3172 MipsII::MO_NO_FLAG); 3173 GlobalOrExternal = true; 3174 } 3175 else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) { 3176 const char *Sym = S->getSymbol(); 3177 3178 if (!IsPIC) // static 3179 Callee = DAG.getTargetExternalSymbol( 3180 Sym, getPointerTy(DAG.getDataLayout()), MipsII::MO_NO_FLAG); 3181 else if (LargeGOT) { 3182 Callee = getAddrGlobalLargeGOT(S, DL, Ty, DAG, MipsII::MO_CALL_HI16, 3183 MipsII::MO_CALL_LO16, Chain, 3184 FuncInfo->callPtrInfo(Sym)); 3185 IsCallReloc = true; 3186 } else { // PIC 3187 Callee = getAddrGlobal(S, DL, Ty, DAG, MipsII::MO_GOT_CALL, Chain, 3188 FuncInfo->callPtrInfo(Sym)); 3189 IsCallReloc = true; 3190 } 3191 3192 GlobalOrExternal = true; 3193 } 3194 3195 SmallVector<SDValue, 8> Ops(1, Chain); 3196 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue); 3197 3198 getOpndList(Ops, RegsToPass, IsPIC, GlobalOrExternal, InternalLinkage, 3199 IsCallReloc, CLI, Callee, Chain); 3200 3201 if (IsTailCall) { 3202 MF.getFrameInfo().setHasTailCall(); 3203 return DAG.getNode(MipsISD::TailCall, DL, MVT::Other, Ops); 3204 } 3205 3206 Chain = DAG.getNode(MipsISD::JmpLink, DL, NodeTys, Ops); 3207 SDValue InFlag = Chain.getValue(1); 3208 3209 // Create the CALLSEQ_END node. 3210 Chain = DAG.getCALLSEQ_END(Chain, NextStackOffsetVal, 3211 DAG.getIntPtrConstant(0, DL, true), InFlag, DL); 3212 InFlag = Chain.getValue(1); 3213 3214 // Handle result values, copying them out of physregs into vregs that we 3215 // return. 3216 return LowerCallResult(Chain, InFlag, CallConv, IsVarArg, Ins, DL, DAG, 3217 InVals, CLI); 3218 } 3219 3220 /// LowerCallResult - Lower the result values of a call into the 3221 /// appropriate copies out of appropriate physical registers. 3222 SDValue MipsTargetLowering::LowerCallResult( 3223 SDValue Chain, SDValue InFlag, CallingConv::ID CallConv, bool IsVarArg, 3224 const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &DL, 3225 SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals, 3226 TargetLowering::CallLoweringInfo &CLI) const { 3227 // Assign locations to each value returned by this call. 3228 SmallVector<CCValAssign, 16> RVLocs; 3229 MipsCCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), RVLocs, 3230 *DAG.getContext()); 3231 3232 const ExternalSymbolSDNode *ES = 3233 dyn_cast_or_null<const ExternalSymbolSDNode>(CLI.Callee.getNode()); 3234 CCInfo.AnalyzeCallResult(Ins, RetCC_Mips, CLI.RetTy, 3235 ES ? ES->getSymbol() : nullptr); 3236 3237 // Copy all of the result registers out of their specified physreg. 3238 for (unsigned i = 0; i != RVLocs.size(); ++i) { 3239 CCValAssign &VA = RVLocs[i]; 3240 assert(VA.isRegLoc() && "Can only return in registers!"); 3241 3242 SDValue Val = DAG.getCopyFromReg(Chain, DL, RVLocs[i].getLocReg(), 3243 RVLocs[i].getLocVT(), InFlag); 3244 Chain = Val.getValue(1); 3245 InFlag = Val.getValue(2); 3246 3247 if (VA.isUpperBitsInLoc()) { 3248 unsigned ValSizeInBits = Ins[i].ArgVT.getSizeInBits(); 3249 unsigned LocSizeInBits = VA.getLocVT().getSizeInBits(); 3250 unsigned Shift = 3251 VA.getLocInfo() == CCValAssign::ZExtUpper ? ISD::SRL : ISD::SRA; 3252 Val = DAG.getNode( 3253 Shift, DL, VA.getLocVT(), Val, 3254 DAG.getConstant(LocSizeInBits - ValSizeInBits, DL, VA.getLocVT())); 3255 } 3256 3257 switch (VA.getLocInfo()) { 3258 default: 3259 llvm_unreachable("Unknown loc info!"); 3260 case CCValAssign::Full: 3261 break; 3262 case CCValAssign::BCvt: 3263 Val = DAG.getNode(ISD::BITCAST, DL, VA.getValVT(), Val); 3264 break; 3265 case CCValAssign::AExt: 3266 case CCValAssign::AExtUpper: 3267 Val = DAG.getNode(ISD::TRUNCATE, DL, VA.getValVT(), Val); 3268 break; 3269 case CCValAssign::ZExt: 3270 case CCValAssign::ZExtUpper: 3271 Val = DAG.getNode(ISD::AssertZext, DL, VA.getLocVT(), Val, 3272 DAG.getValueType(VA.getValVT())); 3273 Val = DAG.getNode(ISD::TRUNCATE, DL, VA.getValVT(), Val); 3274 break; 3275 case CCValAssign::SExt: 3276 case CCValAssign::SExtUpper: 3277 Val = DAG.getNode(ISD::AssertSext, DL, VA.getLocVT(), Val, 3278 DAG.getValueType(VA.getValVT())); 3279 Val = DAG.getNode(ISD::TRUNCATE, DL, VA.getValVT(), Val); 3280 break; 3281 } 3282 3283 InVals.push_back(Val); 3284 } 3285 3286 return Chain; 3287 } 3288 3289 static SDValue UnpackFromArgumentSlot(SDValue Val, const CCValAssign &VA, 3290 EVT ArgVT, const SDLoc &DL, 3291 SelectionDAG &DAG) { 3292 MVT LocVT = VA.getLocVT(); 3293 EVT ValVT = VA.getValVT(); 3294 3295 // Shift into the upper bits if necessary. 3296 switch (VA.getLocInfo()) { 3297 default: 3298 break; 3299 case CCValAssign::AExtUpper: 3300 case CCValAssign::SExtUpper: 3301 case CCValAssign::ZExtUpper: { 3302 unsigned ValSizeInBits = ArgVT.getSizeInBits(); 3303 unsigned LocSizeInBits = VA.getLocVT().getSizeInBits(); 3304 unsigned Opcode = 3305 VA.getLocInfo() == CCValAssign::ZExtUpper ? ISD::SRL : ISD::SRA; 3306 Val = DAG.getNode( 3307 Opcode, DL, VA.getLocVT(), Val, 3308 DAG.getConstant(LocSizeInBits - ValSizeInBits, DL, VA.getLocVT())); 3309 break; 3310 } 3311 } 3312 3313 // If this is an value smaller than the argument slot size (32-bit for O32, 3314 // 64-bit for N32/N64), it has been promoted in some way to the argument slot 3315 // size. Extract the value and insert any appropriate assertions regarding 3316 // sign/zero extension. 3317 switch (VA.getLocInfo()) { 3318 default: 3319 llvm_unreachable("Unknown loc info!"); 3320 case CCValAssign::Full: 3321 break; 3322 case CCValAssign::AExtUpper: 3323 case CCValAssign::AExt: 3324 Val = DAG.getNode(ISD::TRUNCATE, DL, ValVT, Val); 3325 break; 3326 case CCValAssign::SExtUpper: 3327 case CCValAssign::SExt: 3328 Val = DAG.getNode(ISD::AssertSext, DL, LocVT, Val, DAG.getValueType(ValVT)); 3329 Val = DAG.getNode(ISD::TRUNCATE, DL, ValVT, Val); 3330 break; 3331 case CCValAssign::ZExtUpper: 3332 case CCValAssign::ZExt: 3333 Val = DAG.getNode(ISD::AssertZext, DL, LocVT, Val, DAG.getValueType(ValVT)); 3334 Val = DAG.getNode(ISD::TRUNCATE, DL, ValVT, Val); 3335 break; 3336 case CCValAssign::BCvt: 3337 Val = DAG.getNode(ISD::BITCAST, DL, ValVT, Val); 3338 break; 3339 } 3340 3341 return Val; 3342 } 3343 3344 //===----------------------------------------------------------------------===// 3345 // Formal Arguments Calling Convention Implementation 3346 //===----------------------------------------------------------------------===// 3347 /// LowerFormalArguments - transform physical registers into virtual registers 3348 /// and generate load operations for arguments places on the stack. 3349 SDValue MipsTargetLowering::LowerFormalArguments( 3350 SDValue Chain, CallingConv::ID CallConv, bool IsVarArg, 3351 const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &DL, 3352 SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const { 3353 MachineFunction &MF = DAG.getMachineFunction(); 3354 MachineFrameInfo &MFI = MF.getFrameInfo(); 3355 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>(); 3356 3357 MipsFI->setVarArgsFrameIndex(0); 3358 3359 // Used with vargs to acumulate store chains. 3360 std::vector<SDValue> OutChains; 3361 3362 // Assign locations to all of the incoming arguments. 3363 SmallVector<CCValAssign, 16> ArgLocs; 3364 MipsCCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), ArgLocs, 3365 *DAG.getContext()); 3366 CCInfo.AllocateStack(ABI.GetCalleeAllocdArgSizeInBytes(CallConv), 1); 3367 const Function *Func = DAG.getMachineFunction().getFunction(); 3368 Function::const_arg_iterator FuncArg = Func->arg_begin(); 3369 3370 if (Func->hasFnAttribute("interrupt") && !Func->arg_empty()) 3371 report_fatal_error( 3372 "Functions with the interrupt attribute cannot have arguments!"); 3373 3374 CCInfo.AnalyzeFormalArguments(Ins, CC_Mips_FixedArg); 3375 MipsFI->setFormalArgInfo(CCInfo.getNextStackOffset(), 3376 CCInfo.getInRegsParamsCount() > 0); 3377 3378 unsigned CurArgIdx = 0; 3379 CCInfo.rewindByValRegsInfo(); 3380 3381 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { 3382 CCValAssign &VA = ArgLocs[i]; 3383 if (Ins[i].isOrigArg()) { 3384 std::advance(FuncArg, Ins[i].getOrigArgIndex() - CurArgIdx); 3385 CurArgIdx = Ins[i].getOrigArgIndex(); 3386 } 3387 EVT ValVT = VA.getValVT(); 3388 ISD::ArgFlagsTy Flags = Ins[i].Flags; 3389 bool IsRegLoc = VA.isRegLoc(); 3390 3391 if (Flags.isByVal()) { 3392 assert(Ins[i].isOrigArg() && "Byval arguments cannot be implicit"); 3393 unsigned FirstByValReg, LastByValReg; 3394 unsigned ByValIdx = CCInfo.getInRegsParamsProcessed(); 3395 CCInfo.getInRegsParamInfo(ByValIdx, FirstByValReg, LastByValReg); 3396 3397 assert(Flags.getByValSize() && 3398 "ByVal args of size 0 should have been ignored by front-end."); 3399 assert(ByValIdx < CCInfo.getInRegsParamsCount()); 3400 copyByValRegs(Chain, DL, OutChains, DAG, Flags, InVals, &*FuncArg, 3401 FirstByValReg, LastByValReg, VA, CCInfo); 3402 CCInfo.nextInRegsParam(); 3403 continue; 3404 } 3405 3406 // Arguments stored on registers 3407 if (IsRegLoc) { 3408 MVT RegVT = VA.getLocVT(); 3409 unsigned ArgReg = VA.getLocReg(); 3410 const TargetRegisterClass *RC = getRegClassFor(RegVT); 3411 3412 // Transform the arguments stored on 3413 // physical registers into virtual ones 3414 unsigned Reg = addLiveIn(DAG.getMachineFunction(), ArgReg, RC); 3415 SDValue ArgValue = DAG.getCopyFromReg(Chain, DL, Reg, RegVT); 3416 3417 ArgValue = UnpackFromArgumentSlot(ArgValue, VA, Ins[i].ArgVT, DL, DAG); 3418 3419 // Handle floating point arguments passed in integer registers and 3420 // long double arguments passed in floating point registers. 3421 if ((RegVT == MVT::i32 && ValVT == MVT::f32) || 3422 (RegVT == MVT::i64 && ValVT == MVT::f64) || 3423 (RegVT == MVT::f64 && ValVT == MVT::i64)) 3424 ArgValue = DAG.getNode(ISD::BITCAST, DL, ValVT, ArgValue); 3425 else if (ABI.IsO32() && RegVT == MVT::i32 && 3426 ValVT == MVT::f64) { 3427 unsigned Reg2 = addLiveIn(DAG.getMachineFunction(), 3428 getNextIntArgReg(ArgReg), RC); 3429 SDValue ArgValue2 = DAG.getCopyFromReg(Chain, DL, Reg2, RegVT); 3430 if (!Subtarget.isLittle()) 3431 std::swap(ArgValue, ArgValue2); 3432 ArgValue = DAG.getNode(MipsISD::BuildPairF64, DL, MVT::f64, 3433 ArgValue, ArgValue2); 3434 } 3435 3436 InVals.push_back(ArgValue); 3437 } else { // VA.isRegLoc() 3438 MVT LocVT = VA.getLocVT(); 3439 3440 if (ABI.IsO32()) { 3441 // We ought to be able to use LocVT directly but O32 sets it to i32 3442 // when allocating floating point values to integer registers. 3443 // This shouldn't influence how we load the value into registers unless 3444 // we are targeting softfloat. 3445 if (VA.getValVT().isFloatingPoint() && !Subtarget.useSoftFloat()) 3446 LocVT = VA.getValVT(); 3447 } 3448 3449 // sanity check 3450 assert(VA.isMemLoc()); 3451 3452 // The stack pointer offset is relative to the caller stack frame. 3453 int FI = MFI.CreateFixedObject(LocVT.getSizeInBits() / 8, 3454 VA.getLocMemOffset(), true); 3455 3456 // Create load nodes to retrieve arguments from the stack 3457 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy(DAG.getDataLayout())); 3458 SDValue ArgValue = DAG.getLoad( 3459 LocVT, DL, Chain, FIN, 3460 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), FI)); 3461 OutChains.push_back(ArgValue.getValue(1)); 3462 3463 ArgValue = UnpackFromArgumentSlot(ArgValue, VA, Ins[i].ArgVT, DL, DAG); 3464 3465 InVals.push_back(ArgValue); 3466 } 3467 } 3468 3469 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { 3470 // The mips ABIs for returning structs by value requires that we copy 3471 // the sret argument into $v0 for the return. Save the argument into 3472 // a virtual register so that we can access it from the return points. 3473 if (Ins[i].Flags.isSRet()) { 3474 unsigned Reg = MipsFI->getSRetReturnReg(); 3475 if (!Reg) { 3476 Reg = MF.getRegInfo().createVirtualRegister( 3477 getRegClassFor(ABI.IsN64() ? MVT::i64 : MVT::i32)); 3478 MipsFI->setSRetReturnReg(Reg); 3479 } 3480 SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), DL, Reg, InVals[i]); 3481 Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, Copy, Chain); 3482 break; 3483 } 3484 } 3485 3486 if (IsVarArg) 3487 writeVarArgRegs(OutChains, Chain, DL, DAG, CCInfo); 3488 3489 // All stores are grouped in one node to allow the matching between 3490 // the size of Ins and InVals. This only happens when on varg functions 3491 if (!OutChains.empty()) { 3492 OutChains.push_back(Chain); 3493 Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, OutChains); 3494 } 3495 3496 return Chain; 3497 } 3498 3499 //===----------------------------------------------------------------------===// 3500 // Return Value Calling Convention Implementation 3501 //===----------------------------------------------------------------------===// 3502 3503 bool 3504 MipsTargetLowering::CanLowerReturn(CallingConv::ID CallConv, 3505 MachineFunction &MF, bool IsVarArg, 3506 const SmallVectorImpl<ISD::OutputArg> &Outs, 3507 LLVMContext &Context) const { 3508 SmallVector<CCValAssign, 16> RVLocs; 3509 MipsCCState CCInfo(CallConv, IsVarArg, MF, RVLocs, Context); 3510 return CCInfo.CheckReturn(Outs, RetCC_Mips); 3511 } 3512 3513 bool 3514 MipsTargetLowering::shouldSignExtendTypeInLibCall(EVT Type, bool IsSigned) const { 3515 if (Subtarget.hasMips3() && Subtarget.useSoftFloat()) { 3516 if (Type == MVT::i32) 3517 return true; 3518 } 3519 return IsSigned; 3520 } 3521 3522 SDValue 3523 MipsTargetLowering::LowerInterruptReturn(SmallVectorImpl<SDValue> &RetOps, 3524 const SDLoc &DL, 3525 SelectionDAG &DAG) const { 3526 MachineFunction &MF = DAG.getMachineFunction(); 3527 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>(); 3528 3529 MipsFI->setISR(); 3530 3531 return DAG.getNode(MipsISD::ERet, DL, MVT::Other, RetOps); 3532 } 3533 3534 SDValue 3535 MipsTargetLowering::LowerReturn(SDValue Chain, CallingConv::ID CallConv, 3536 bool IsVarArg, 3537 const SmallVectorImpl<ISD::OutputArg> &Outs, 3538 const SmallVectorImpl<SDValue> &OutVals, 3539 const SDLoc &DL, SelectionDAG &DAG) const { 3540 // CCValAssign - represent the assignment of 3541 // the return value to a location 3542 SmallVector<CCValAssign, 16> RVLocs; 3543 MachineFunction &MF = DAG.getMachineFunction(); 3544 3545 // CCState - Info about the registers and stack slot. 3546 MipsCCState CCInfo(CallConv, IsVarArg, MF, RVLocs, *DAG.getContext()); 3547 3548 // Analyze return values. 3549 CCInfo.AnalyzeReturn(Outs, RetCC_Mips); 3550 3551 SDValue Flag; 3552 SmallVector<SDValue, 4> RetOps(1, Chain); 3553 3554 // Copy the result values into the output registers. 3555 for (unsigned i = 0; i != RVLocs.size(); ++i) { 3556 SDValue Val = OutVals[i]; 3557 CCValAssign &VA = RVLocs[i]; 3558 assert(VA.isRegLoc() && "Can only return in registers!"); 3559 bool UseUpperBits = false; 3560 3561 switch (VA.getLocInfo()) { 3562 default: 3563 llvm_unreachable("Unknown loc info!"); 3564 case CCValAssign::Full: 3565 break; 3566 case CCValAssign::BCvt: 3567 Val = DAG.getNode(ISD::BITCAST, DL, VA.getLocVT(), Val); 3568 break; 3569 case CCValAssign::AExtUpper: 3570 UseUpperBits = true; 3571 LLVM_FALLTHROUGH; 3572 case CCValAssign::AExt: 3573 Val = DAG.getNode(ISD::ANY_EXTEND, DL, VA.getLocVT(), Val); 3574 break; 3575 case CCValAssign::ZExtUpper: 3576 UseUpperBits = true; 3577 LLVM_FALLTHROUGH; 3578 case CCValAssign::ZExt: 3579 Val = DAG.getNode(ISD::ZERO_EXTEND, DL, VA.getLocVT(), Val); 3580 break; 3581 case CCValAssign::SExtUpper: 3582 UseUpperBits = true; 3583 LLVM_FALLTHROUGH; 3584 case CCValAssign::SExt: 3585 Val = DAG.getNode(ISD::SIGN_EXTEND, DL, VA.getLocVT(), Val); 3586 break; 3587 } 3588 3589 if (UseUpperBits) { 3590 unsigned ValSizeInBits = Outs[i].ArgVT.getSizeInBits(); 3591 unsigned LocSizeInBits = VA.getLocVT().getSizeInBits(); 3592 Val = DAG.getNode( 3593 ISD::SHL, DL, VA.getLocVT(), Val, 3594 DAG.getConstant(LocSizeInBits - ValSizeInBits, DL, VA.getLocVT())); 3595 } 3596 3597 Chain = DAG.getCopyToReg(Chain, DL, VA.getLocReg(), Val, Flag); 3598 3599 // Guarantee that all emitted copies are stuck together with flags. 3600 Flag = Chain.getValue(1); 3601 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT())); 3602 } 3603 3604 // The mips ABIs for returning structs by value requires that we copy 3605 // the sret argument into $v0 for the return. We saved the argument into 3606 // a virtual register in the entry block, so now we copy the value out 3607 // and into $v0. 3608 if (MF.getFunction()->hasStructRetAttr()) { 3609 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>(); 3610 unsigned Reg = MipsFI->getSRetReturnReg(); 3611 3612 if (!Reg) 3613 llvm_unreachable("sret virtual register not created in the entry block"); 3614 SDValue Val = 3615 DAG.getCopyFromReg(Chain, DL, Reg, getPointerTy(DAG.getDataLayout())); 3616 unsigned V0 = ABI.IsN64() ? Mips::V0_64 : Mips::V0; 3617 3618 Chain = DAG.getCopyToReg(Chain, DL, V0, Val, Flag); 3619 Flag = Chain.getValue(1); 3620 RetOps.push_back(DAG.getRegister(V0, getPointerTy(DAG.getDataLayout()))); 3621 } 3622 3623 RetOps[0] = Chain; // Update chain. 3624 3625 // Add the flag if we have it. 3626 if (Flag.getNode()) 3627 RetOps.push_back(Flag); 3628 3629 // ISRs must use "eret". 3630 if (DAG.getMachineFunction().getFunction()->hasFnAttribute("interrupt")) 3631 return LowerInterruptReturn(RetOps, DL, DAG); 3632 3633 // Standard return on Mips is a "jr $ra" 3634 return DAG.getNode(MipsISD::Ret, DL, MVT::Other, RetOps); 3635 } 3636 3637 //===----------------------------------------------------------------------===// 3638 // Mips Inline Assembly Support 3639 //===----------------------------------------------------------------------===// 3640 3641 /// getConstraintType - Given a constraint letter, return the type of 3642 /// constraint it is for this target. 3643 MipsTargetLowering::ConstraintType 3644 MipsTargetLowering::getConstraintType(StringRef Constraint) const { 3645 // Mips specific constraints 3646 // GCC config/mips/constraints.md 3647 // 3648 // 'd' : An address register. Equivalent to r 3649 // unless generating MIPS16 code. 3650 // 'y' : Equivalent to r; retained for 3651 // backwards compatibility. 3652 // 'c' : A register suitable for use in an indirect 3653 // jump. This will always be $25 for -mabicalls. 3654 // 'l' : The lo register. 1 word storage. 3655 // 'x' : The hilo register pair. Double word storage. 3656 if (Constraint.size() == 1) { 3657 switch (Constraint[0]) { 3658 default : break; 3659 case 'd': 3660 case 'y': 3661 case 'f': 3662 case 'c': 3663 case 'l': 3664 case 'x': 3665 return C_RegisterClass; 3666 case 'R': 3667 return C_Memory; 3668 } 3669 } 3670 3671 if (Constraint == "ZC") 3672 return C_Memory; 3673 3674 return TargetLowering::getConstraintType(Constraint); 3675 } 3676 3677 /// Examine constraint type and operand type and determine a weight value. 3678 /// This object must already have been set up with the operand type 3679 /// and the current alternative constraint selected. 3680 TargetLowering::ConstraintWeight 3681 MipsTargetLowering::getSingleConstraintMatchWeight( 3682 AsmOperandInfo &info, const char *constraint) const { 3683 ConstraintWeight weight = CW_Invalid; 3684 Value *CallOperandVal = info.CallOperandVal; 3685 // If we don't have a value, we can't do a match, 3686 // but allow it at the lowest weight. 3687 if (!CallOperandVal) 3688 return CW_Default; 3689 Type *type = CallOperandVal->getType(); 3690 // Look at the constraint type. 3691 switch (*constraint) { 3692 default: 3693 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint); 3694 break; 3695 case 'd': 3696 case 'y': 3697 if (type->isIntegerTy()) 3698 weight = CW_Register; 3699 break; 3700 case 'f': // FPU or MSA register 3701 if (Subtarget.hasMSA() && type->isVectorTy() && 3702 cast<VectorType>(type)->getBitWidth() == 128) 3703 weight = CW_Register; 3704 else if (type->isFloatTy()) 3705 weight = CW_Register; 3706 break; 3707 case 'c': // $25 for indirect jumps 3708 case 'l': // lo register 3709 case 'x': // hilo register pair 3710 if (type->isIntegerTy()) 3711 weight = CW_SpecificReg; 3712 break; 3713 case 'I': // signed 16 bit immediate 3714 case 'J': // integer zero 3715 case 'K': // unsigned 16 bit immediate 3716 case 'L': // signed 32 bit immediate where lower 16 bits are 0 3717 case 'N': // immediate in the range of -65535 to -1 (inclusive) 3718 case 'O': // signed 15 bit immediate (+- 16383) 3719 case 'P': // immediate in the range of 65535 to 1 (inclusive) 3720 if (isa<ConstantInt>(CallOperandVal)) 3721 weight = CW_Constant; 3722 break; 3723 case 'R': 3724 weight = CW_Memory; 3725 break; 3726 } 3727 return weight; 3728 } 3729 3730 /// This is a helper function to parse a physical register string and split it 3731 /// into non-numeric and numeric parts (Prefix and Reg). The first boolean flag 3732 /// that is returned indicates whether parsing was successful. The second flag 3733 /// is true if the numeric part exists. 3734 static std::pair<bool, bool> parsePhysicalReg(StringRef C, StringRef &Prefix, 3735 unsigned long long &Reg) { 3736 if (C.front() != '{' || C.back() != '}') 3737 return std::make_pair(false, false); 3738 3739 // Search for the first numeric character. 3740 StringRef::const_iterator I, B = C.begin() + 1, E = C.end() - 1; 3741 I = std::find_if(B, E, isdigit); 3742 3743 Prefix = StringRef(B, I - B); 3744 3745 // The second flag is set to false if no numeric characters were found. 3746 if (I == E) 3747 return std::make_pair(true, false); 3748 3749 // Parse the numeric characters. 3750 return std::make_pair(!getAsUnsignedInteger(StringRef(I, E - I), 10, Reg), 3751 true); 3752 } 3753 3754 std::pair<unsigned, const TargetRegisterClass *> MipsTargetLowering:: 3755 parseRegForInlineAsmConstraint(StringRef C, MVT VT) const { 3756 const TargetRegisterInfo *TRI = 3757 Subtarget.getRegisterInfo(); 3758 const TargetRegisterClass *RC; 3759 StringRef Prefix; 3760 unsigned long long Reg; 3761 3762 std::pair<bool, bool> R = parsePhysicalReg(C, Prefix, Reg); 3763 3764 if (!R.first) 3765 return std::make_pair(0U, nullptr); 3766 3767 if ((Prefix == "hi" || Prefix == "lo")) { // Parse hi/lo. 3768 // No numeric characters follow "hi" or "lo". 3769 if (R.second) 3770 return std::make_pair(0U, nullptr); 3771 3772 RC = TRI->getRegClass(Prefix == "hi" ? 3773 Mips::HI32RegClassID : Mips::LO32RegClassID); 3774 return std::make_pair(*(RC->begin()), RC); 3775 } else if (Prefix.startswith("$msa")) { 3776 // Parse $msa(ir|csr|access|save|modify|request|map|unmap) 3777 3778 // No numeric characters follow the name. 3779 if (R.second) 3780 return std::make_pair(0U, nullptr); 3781 3782 Reg = StringSwitch<unsigned long long>(Prefix) 3783 .Case("$msair", Mips::MSAIR) 3784 .Case("$msacsr", Mips::MSACSR) 3785 .Case("$msaaccess", Mips::MSAAccess) 3786 .Case("$msasave", Mips::MSASave) 3787 .Case("$msamodify", Mips::MSAModify) 3788 .Case("$msarequest", Mips::MSARequest) 3789 .Case("$msamap", Mips::MSAMap) 3790 .Case("$msaunmap", Mips::MSAUnmap) 3791 .Default(0); 3792 3793 if (!Reg) 3794 return std::make_pair(0U, nullptr); 3795 3796 RC = TRI->getRegClass(Mips::MSACtrlRegClassID); 3797 return std::make_pair(Reg, RC); 3798 } 3799 3800 if (!R.second) 3801 return std::make_pair(0U, nullptr); 3802 3803 if (Prefix == "$f") { // Parse $f0-$f31. 3804 // If the size of FP registers is 64-bit or Reg is an even number, select 3805 // the 64-bit register class. Otherwise, select the 32-bit register class. 3806 if (VT == MVT::Other) 3807 VT = (Subtarget.isFP64bit() || !(Reg % 2)) ? MVT::f64 : MVT::f32; 3808 3809 RC = getRegClassFor(VT); 3810 3811 if (RC == &Mips::AFGR64RegClass) { 3812 assert(Reg % 2 == 0); 3813 Reg >>= 1; 3814 } 3815 } else if (Prefix == "$fcc") // Parse $fcc0-$fcc7. 3816 RC = TRI->getRegClass(Mips::FCCRegClassID); 3817 else if (Prefix == "$w") { // Parse $w0-$w31. 3818 RC = getRegClassFor((VT == MVT::Other) ? MVT::v16i8 : VT); 3819 } else { // Parse $0-$31. 3820 assert(Prefix == "$"); 3821 RC = getRegClassFor((VT == MVT::Other) ? MVT::i32 : VT); 3822 } 3823 3824 assert(Reg < RC->getNumRegs()); 3825 return std::make_pair(*(RC->begin() + Reg), RC); 3826 } 3827 3828 /// Given a register class constraint, like 'r', if this corresponds directly 3829 /// to an LLVM register class, return a register of 0 and the register class 3830 /// pointer. 3831 std::pair<unsigned, const TargetRegisterClass *> 3832 MipsTargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, 3833 StringRef Constraint, 3834 MVT VT) const { 3835 if (Constraint.size() == 1) { 3836 switch (Constraint[0]) { 3837 case 'd': // Address register. Same as 'r' unless generating MIPS16 code. 3838 case 'y': // Same as 'r'. Exists for compatibility. 3839 case 'r': 3840 if (VT == MVT::i32 || VT == MVT::i16 || VT == MVT::i8) { 3841 if (Subtarget.inMips16Mode()) 3842 return std::make_pair(0U, &Mips::CPU16RegsRegClass); 3843 return std::make_pair(0U, &Mips::GPR32RegClass); 3844 } 3845 if (VT == MVT::i64 && !Subtarget.isGP64bit()) 3846 return std::make_pair(0U, &Mips::GPR32RegClass); 3847 if (VT == MVT::i64 && Subtarget.isGP64bit()) 3848 return std::make_pair(0U, &Mips::GPR64RegClass); 3849 // This will generate an error message 3850 return std::make_pair(0U, nullptr); 3851 case 'f': // FPU or MSA register 3852 if (VT == MVT::v16i8) 3853 return std::make_pair(0U, &Mips::MSA128BRegClass); 3854 else if (VT == MVT::v8i16 || VT == MVT::v8f16) 3855 return std::make_pair(0U, &Mips::MSA128HRegClass); 3856 else if (VT == MVT::v4i32 || VT == MVT::v4f32) 3857 return std::make_pair(0U, &Mips::MSA128WRegClass); 3858 else if (VT == MVT::v2i64 || VT == MVT::v2f64) 3859 return std::make_pair(0U, &Mips::MSA128DRegClass); 3860 else if (VT == MVT::f32) 3861 return std::make_pair(0U, &Mips::FGR32RegClass); 3862 else if ((VT == MVT::f64) && (!Subtarget.isSingleFloat())) { 3863 if (Subtarget.isFP64bit()) 3864 return std::make_pair(0U, &Mips::FGR64RegClass); 3865 return std::make_pair(0U, &Mips::AFGR64RegClass); 3866 } 3867 break; 3868 case 'c': // register suitable for indirect jump 3869 if (VT == MVT::i32) 3870 return std::make_pair((unsigned)Mips::T9, &Mips::GPR32RegClass); 3871 assert(VT == MVT::i64 && "Unexpected type."); 3872 return std::make_pair((unsigned)Mips::T9_64, &Mips::GPR64RegClass); 3873 case 'l': // register suitable for indirect jump 3874 if (VT == MVT::i32) 3875 return std::make_pair((unsigned)Mips::LO0, &Mips::LO32RegClass); 3876 return std::make_pair((unsigned)Mips::LO0_64, &Mips::LO64RegClass); 3877 case 'x': // register suitable for indirect jump 3878 // Fixme: Not triggering the use of both hi and low 3879 // This will generate an error message 3880 return std::make_pair(0U, nullptr); 3881 } 3882 } 3883 3884 std::pair<unsigned, const TargetRegisterClass *> R; 3885 R = parseRegForInlineAsmConstraint(Constraint, VT); 3886 3887 if (R.second) 3888 return R; 3889 3890 return TargetLowering::getRegForInlineAsmConstraint(TRI, Constraint, VT); 3891 } 3892 3893 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops 3894 /// vector. If it is invalid, don't add anything to Ops. 3895 void MipsTargetLowering::LowerAsmOperandForConstraint(SDValue Op, 3896 std::string &Constraint, 3897 std::vector<SDValue>&Ops, 3898 SelectionDAG &DAG) const { 3899 SDLoc DL(Op); 3900 SDValue Result; 3901 3902 // Only support length 1 constraints for now. 3903 if (Constraint.length() > 1) return; 3904 3905 char ConstraintLetter = Constraint[0]; 3906 switch (ConstraintLetter) { 3907 default: break; // This will fall through to the generic implementation 3908 case 'I': // Signed 16 bit constant 3909 // If this fails, the parent routine will give an error 3910 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 3911 EVT Type = Op.getValueType(); 3912 int64_t Val = C->getSExtValue(); 3913 if (isInt<16>(Val)) { 3914 Result = DAG.getTargetConstant(Val, DL, Type); 3915 break; 3916 } 3917 } 3918 return; 3919 case 'J': // integer zero 3920 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 3921 EVT Type = Op.getValueType(); 3922 int64_t Val = C->getZExtValue(); 3923 if (Val == 0) { 3924 Result = DAG.getTargetConstant(0, DL, Type); 3925 break; 3926 } 3927 } 3928 return; 3929 case 'K': // unsigned 16 bit immediate 3930 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 3931 EVT Type = Op.getValueType(); 3932 uint64_t Val = (uint64_t)C->getZExtValue(); 3933 if (isUInt<16>(Val)) { 3934 Result = DAG.getTargetConstant(Val, DL, Type); 3935 break; 3936 } 3937 } 3938 return; 3939 case 'L': // signed 32 bit immediate where lower 16 bits are 0 3940 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 3941 EVT Type = Op.getValueType(); 3942 int64_t Val = C->getSExtValue(); 3943 if ((isInt<32>(Val)) && ((Val & 0xffff) == 0)){ 3944 Result = DAG.getTargetConstant(Val, DL, Type); 3945 break; 3946 } 3947 } 3948 return; 3949 case 'N': // immediate in the range of -65535 to -1 (inclusive) 3950 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 3951 EVT Type = Op.getValueType(); 3952 int64_t Val = C->getSExtValue(); 3953 if ((Val >= -65535) && (Val <= -1)) { 3954 Result = DAG.getTargetConstant(Val, DL, Type); 3955 break; 3956 } 3957 } 3958 return; 3959 case 'O': // signed 15 bit immediate 3960 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 3961 EVT Type = Op.getValueType(); 3962 int64_t Val = C->getSExtValue(); 3963 if ((isInt<15>(Val))) { 3964 Result = DAG.getTargetConstant(Val, DL, Type); 3965 break; 3966 } 3967 } 3968 return; 3969 case 'P': // immediate in the range of 1 to 65535 (inclusive) 3970 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 3971 EVT Type = Op.getValueType(); 3972 int64_t Val = C->getSExtValue(); 3973 if ((Val <= 65535) && (Val >= 1)) { 3974 Result = DAG.getTargetConstant(Val, DL, Type); 3975 break; 3976 } 3977 } 3978 return; 3979 } 3980 3981 if (Result.getNode()) { 3982 Ops.push_back(Result); 3983 return; 3984 } 3985 3986 TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG); 3987 } 3988 3989 bool MipsTargetLowering::isLegalAddressingMode(const DataLayout &DL, 3990 const AddrMode &AM, Type *Ty, 3991 unsigned AS, Instruction *I) const { 3992 // No global is ever allowed as a base. 3993 if (AM.BaseGV) 3994 return false; 3995 3996 switch (AM.Scale) { 3997 case 0: // "r+i" or just "i", depending on HasBaseReg. 3998 break; 3999 case 1: 4000 if (!AM.HasBaseReg) // allow "r+i". 4001 break; 4002 return false; // disallow "r+r" or "r+r+i". 4003 default: 4004 return false; 4005 } 4006 4007 return true; 4008 } 4009 4010 bool 4011 MipsTargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const { 4012 // The Mips target isn't yet aware of offsets. 4013 return false; 4014 } 4015 4016 EVT MipsTargetLowering::getOptimalMemOpType(uint64_t Size, unsigned DstAlign, 4017 unsigned SrcAlign, 4018 bool IsMemset, bool ZeroMemset, 4019 bool MemcpyStrSrc, 4020 MachineFunction &MF) const { 4021 if (Subtarget.hasMips64()) 4022 return MVT::i64; 4023 4024 return MVT::i32; 4025 } 4026 4027 bool MipsTargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const { 4028 if (VT != MVT::f32 && VT != MVT::f64) 4029 return false; 4030 if (Imm.isNegZero()) 4031 return false; 4032 return Imm.isZero(); 4033 } 4034 4035 unsigned MipsTargetLowering::getJumpTableEncoding() const { 4036 4037 // FIXME: For space reasons this should be: EK_GPRel32BlockAddress. 4038 if (ABI.IsN64() && isPositionIndependent()) 4039 return MachineJumpTableInfo::EK_GPRel64BlockAddress; 4040 4041 return TargetLowering::getJumpTableEncoding(); 4042 } 4043 4044 bool MipsTargetLowering::useSoftFloat() const { 4045 return Subtarget.useSoftFloat(); 4046 } 4047 4048 void MipsTargetLowering::copyByValRegs( 4049 SDValue Chain, const SDLoc &DL, std::vector<SDValue> &OutChains, 4050 SelectionDAG &DAG, const ISD::ArgFlagsTy &Flags, 4051 SmallVectorImpl<SDValue> &InVals, const Argument *FuncArg, 4052 unsigned FirstReg, unsigned LastReg, const CCValAssign &VA, 4053 MipsCCState &State) const { 4054 MachineFunction &MF = DAG.getMachineFunction(); 4055 MachineFrameInfo &MFI = MF.getFrameInfo(); 4056 unsigned GPRSizeInBytes = Subtarget.getGPRSizeInBytes(); 4057 unsigned NumRegs = LastReg - FirstReg; 4058 unsigned RegAreaSize = NumRegs * GPRSizeInBytes; 4059 unsigned FrameObjSize = std::max(Flags.getByValSize(), RegAreaSize); 4060 int FrameObjOffset; 4061 ArrayRef<MCPhysReg> ByValArgRegs = ABI.GetByValArgRegs(); 4062 4063 if (RegAreaSize) 4064 FrameObjOffset = 4065 (int)ABI.GetCalleeAllocdArgSizeInBytes(State.getCallingConv()) - 4066 (int)((ByValArgRegs.size() - FirstReg) * GPRSizeInBytes); 4067 else 4068 FrameObjOffset = VA.getLocMemOffset(); 4069 4070 // Create frame object. 4071 EVT PtrTy = getPointerTy(DAG.getDataLayout()); 4072 int FI = MFI.CreateFixedObject(FrameObjSize, FrameObjOffset, true); 4073 SDValue FIN = DAG.getFrameIndex(FI, PtrTy); 4074 InVals.push_back(FIN); 4075 4076 if (!NumRegs) 4077 return; 4078 4079 // Copy arg registers. 4080 MVT RegTy = MVT::getIntegerVT(GPRSizeInBytes * 8); 4081 const TargetRegisterClass *RC = getRegClassFor(RegTy); 4082 4083 for (unsigned I = 0; I < NumRegs; ++I) { 4084 unsigned ArgReg = ByValArgRegs[FirstReg + I]; 4085 unsigned VReg = addLiveIn(MF, ArgReg, RC); 4086 unsigned Offset = I * GPRSizeInBytes; 4087 SDValue StorePtr = DAG.getNode(ISD::ADD, DL, PtrTy, FIN, 4088 DAG.getConstant(Offset, DL, PtrTy)); 4089 SDValue Store = DAG.getStore(Chain, DL, DAG.getRegister(VReg, RegTy), 4090 StorePtr, MachinePointerInfo(FuncArg, Offset)); 4091 OutChains.push_back(Store); 4092 } 4093 } 4094 4095 // Copy byVal arg to registers and stack. 4096 void MipsTargetLowering::passByValArg( 4097 SDValue Chain, const SDLoc &DL, 4098 std::deque<std::pair<unsigned, SDValue>> &RegsToPass, 4099 SmallVectorImpl<SDValue> &MemOpChains, SDValue StackPtr, 4100 MachineFrameInfo &MFI, SelectionDAG &DAG, SDValue Arg, unsigned FirstReg, 4101 unsigned LastReg, const ISD::ArgFlagsTy &Flags, bool isLittle, 4102 const CCValAssign &VA) const { 4103 unsigned ByValSizeInBytes = Flags.getByValSize(); 4104 unsigned OffsetInBytes = 0; // From beginning of struct 4105 unsigned RegSizeInBytes = Subtarget.getGPRSizeInBytes(); 4106 unsigned Alignment = std::min(Flags.getByValAlign(), RegSizeInBytes); 4107 EVT PtrTy = getPointerTy(DAG.getDataLayout()), 4108 RegTy = MVT::getIntegerVT(RegSizeInBytes * 8); 4109 unsigned NumRegs = LastReg - FirstReg; 4110 4111 if (NumRegs) { 4112 ArrayRef<MCPhysReg> ArgRegs = ABI.GetByValArgRegs(); 4113 bool LeftoverBytes = (NumRegs * RegSizeInBytes > ByValSizeInBytes); 4114 unsigned I = 0; 4115 4116 // Copy words to registers. 4117 for (; I < NumRegs - LeftoverBytes; ++I, OffsetInBytes += RegSizeInBytes) { 4118 SDValue LoadPtr = DAG.getNode(ISD::ADD, DL, PtrTy, Arg, 4119 DAG.getConstant(OffsetInBytes, DL, PtrTy)); 4120 SDValue LoadVal = DAG.getLoad(RegTy, DL, Chain, LoadPtr, 4121 MachinePointerInfo(), Alignment); 4122 MemOpChains.push_back(LoadVal.getValue(1)); 4123 unsigned ArgReg = ArgRegs[FirstReg + I]; 4124 RegsToPass.push_back(std::make_pair(ArgReg, LoadVal)); 4125 } 4126 4127 // Return if the struct has been fully copied. 4128 if (ByValSizeInBytes == OffsetInBytes) 4129 return; 4130 4131 // Copy the remainder of the byval argument with sub-word loads and shifts. 4132 if (LeftoverBytes) { 4133 SDValue Val; 4134 4135 for (unsigned LoadSizeInBytes = RegSizeInBytes / 2, TotalBytesLoaded = 0; 4136 OffsetInBytes < ByValSizeInBytes; LoadSizeInBytes /= 2) { 4137 unsigned RemainingSizeInBytes = ByValSizeInBytes - OffsetInBytes; 4138 4139 if (RemainingSizeInBytes < LoadSizeInBytes) 4140 continue; 4141 4142 // Load subword. 4143 SDValue LoadPtr = DAG.getNode(ISD::ADD, DL, PtrTy, Arg, 4144 DAG.getConstant(OffsetInBytes, DL, 4145 PtrTy)); 4146 SDValue LoadVal = DAG.getExtLoad( 4147 ISD::ZEXTLOAD, DL, RegTy, Chain, LoadPtr, MachinePointerInfo(), 4148 MVT::getIntegerVT(LoadSizeInBytes * 8), Alignment); 4149 MemOpChains.push_back(LoadVal.getValue(1)); 4150 4151 // Shift the loaded value. 4152 unsigned Shamt; 4153 4154 if (isLittle) 4155 Shamt = TotalBytesLoaded * 8; 4156 else 4157 Shamt = (RegSizeInBytes - (TotalBytesLoaded + LoadSizeInBytes)) * 8; 4158 4159 SDValue Shift = DAG.getNode(ISD::SHL, DL, RegTy, LoadVal, 4160 DAG.getConstant(Shamt, DL, MVT::i32)); 4161 4162 if (Val.getNode()) 4163 Val = DAG.getNode(ISD::OR, DL, RegTy, Val, Shift); 4164 else 4165 Val = Shift; 4166 4167 OffsetInBytes += LoadSizeInBytes; 4168 TotalBytesLoaded += LoadSizeInBytes; 4169 Alignment = std::min(Alignment, LoadSizeInBytes); 4170 } 4171 4172 unsigned ArgReg = ArgRegs[FirstReg + I]; 4173 RegsToPass.push_back(std::make_pair(ArgReg, Val)); 4174 return; 4175 } 4176 } 4177 4178 // Copy remainder of byval arg to it with memcpy. 4179 unsigned MemCpySize = ByValSizeInBytes - OffsetInBytes; 4180 SDValue Src = DAG.getNode(ISD::ADD, DL, PtrTy, Arg, 4181 DAG.getConstant(OffsetInBytes, DL, PtrTy)); 4182 SDValue Dst = DAG.getNode(ISD::ADD, DL, PtrTy, StackPtr, 4183 DAG.getIntPtrConstant(VA.getLocMemOffset(), DL)); 4184 Chain = DAG.getMemcpy(Chain, DL, Dst, Src, 4185 DAG.getConstant(MemCpySize, DL, PtrTy), 4186 Alignment, /*isVolatile=*/false, /*AlwaysInline=*/false, 4187 /*isTailCall=*/false, 4188 MachinePointerInfo(), MachinePointerInfo()); 4189 MemOpChains.push_back(Chain); 4190 } 4191 4192 void MipsTargetLowering::writeVarArgRegs(std::vector<SDValue> &OutChains, 4193 SDValue Chain, const SDLoc &DL, 4194 SelectionDAG &DAG, 4195 CCState &State) const { 4196 ArrayRef<MCPhysReg> ArgRegs = ABI.GetVarArgRegs(); 4197 unsigned Idx = State.getFirstUnallocated(ArgRegs); 4198 unsigned RegSizeInBytes = Subtarget.getGPRSizeInBytes(); 4199 MVT RegTy = MVT::getIntegerVT(RegSizeInBytes * 8); 4200 const TargetRegisterClass *RC = getRegClassFor(RegTy); 4201 MachineFunction &MF = DAG.getMachineFunction(); 4202 MachineFrameInfo &MFI = MF.getFrameInfo(); 4203 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>(); 4204 4205 // Offset of the first variable argument from stack pointer. 4206 int VaArgOffset; 4207 4208 if (ArgRegs.size() == Idx) 4209 VaArgOffset = alignTo(State.getNextStackOffset(), RegSizeInBytes); 4210 else { 4211 VaArgOffset = 4212 (int)ABI.GetCalleeAllocdArgSizeInBytes(State.getCallingConv()) - 4213 (int)(RegSizeInBytes * (ArgRegs.size() - Idx)); 4214 } 4215 4216 // Record the frame index of the first variable argument 4217 // which is a value necessary to VASTART. 4218 int FI = MFI.CreateFixedObject(RegSizeInBytes, VaArgOffset, true); 4219 MipsFI->setVarArgsFrameIndex(FI); 4220 4221 // Copy the integer registers that have not been used for argument passing 4222 // to the argument register save area. For O32, the save area is allocated 4223 // in the caller's stack frame, while for N32/64, it is allocated in the 4224 // callee's stack frame. 4225 for (unsigned I = Idx; I < ArgRegs.size(); 4226 ++I, VaArgOffset += RegSizeInBytes) { 4227 unsigned Reg = addLiveIn(MF, ArgRegs[I], RC); 4228 SDValue ArgValue = DAG.getCopyFromReg(Chain, DL, Reg, RegTy); 4229 FI = MFI.CreateFixedObject(RegSizeInBytes, VaArgOffset, true); 4230 SDValue PtrOff = DAG.getFrameIndex(FI, getPointerTy(DAG.getDataLayout())); 4231 SDValue Store = 4232 DAG.getStore(Chain, DL, ArgValue, PtrOff, MachinePointerInfo()); 4233 cast<StoreSDNode>(Store.getNode())->getMemOperand()->setValue( 4234 (Value *)nullptr); 4235 OutChains.push_back(Store); 4236 } 4237 } 4238 4239 void MipsTargetLowering::HandleByVal(CCState *State, unsigned &Size, 4240 unsigned Align) const { 4241 const TargetFrameLowering *TFL = Subtarget.getFrameLowering(); 4242 4243 assert(Size && "Byval argument's size shouldn't be 0."); 4244 4245 Align = std::min(Align, TFL->getStackAlignment()); 4246 4247 unsigned FirstReg = 0; 4248 unsigned NumRegs = 0; 4249 4250 if (State->getCallingConv() != CallingConv::Fast) { 4251 unsigned RegSizeInBytes = Subtarget.getGPRSizeInBytes(); 4252 ArrayRef<MCPhysReg> IntArgRegs = ABI.GetByValArgRegs(); 4253 // FIXME: The O32 case actually describes no shadow registers. 4254 const MCPhysReg *ShadowRegs = 4255 ABI.IsO32() ? IntArgRegs.data() : Mips64DPRegs; 4256 4257 // We used to check the size as well but we can't do that anymore since 4258 // CCState::HandleByVal() rounds up the size after calling this function. 4259 assert(!(Align % RegSizeInBytes) && 4260 "Byval argument's alignment should be a multiple of" 4261 "RegSizeInBytes."); 4262 4263 FirstReg = State->getFirstUnallocated(IntArgRegs); 4264 4265 // If Align > RegSizeInBytes, the first arg register must be even. 4266 // FIXME: This condition happens to do the right thing but it's not the 4267 // right way to test it. We want to check that the stack frame offset 4268 // of the register is aligned. 4269 if ((Align > RegSizeInBytes) && (FirstReg % 2)) { 4270 State->AllocateReg(IntArgRegs[FirstReg], ShadowRegs[FirstReg]); 4271 ++FirstReg; 4272 } 4273 4274 // Mark the registers allocated. 4275 Size = alignTo(Size, RegSizeInBytes); 4276 for (unsigned I = FirstReg; Size > 0 && (I < IntArgRegs.size()); 4277 Size -= RegSizeInBytes, ++I, ++NumRegs) 4278 State->AllocateReg(IntArgRegs[I], ShadowRegs[I]); 4279 } 4280 4281 State->addInRegsParamInfo(FirstReg, FirstReg + NumRegs); 4282 } 4283 4284 MachineBasicBlock *MipsTargetLowering::emitPseudoSELECT(MachineInstr &MI, 4285 MachineBasicBlock *BB, 4286 bool isFPCmp, 4287 unsigned Opc) const { 4288 assert(!(Subtarget.hasMips4() || Subtarget.hasMips32()) && 4289 "Subtarget already supports SELECT nodes with the use of" 4290 "conditional-move instructions."); 4291 4292 const TargetInstrInfo *TII = 4293 Subtarget.getInstrInfo(); 4294 DebugLoc DL = MI.getDebugLoc(); 4295 4296 // To "insert" a SELECT instruction, we actually have to insert the 4297 // diamond control-flow pattern. The incoming instruction knows the 4298 // destination vreg to set, the condition code register to branch on, the 4299 // true/false values to select between, and a branch opcode to use. 4300 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 4301 MachineFunction::iterator It = ++BB->getIterator(); 4302 4303 // thisMBB: 4304 // ... 4305 // TrueVal = ... 4306 // setcc r1, r2, r3 4307 // bNE r1, r0, copy1MBB 4308 // fallthrough --> copy0MBB 4309 MachineBasicBlock *thisMBB = BB; 4310 MachineFunction *F = BB->getParent(); 4311 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB); 4312 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB); 4313 F->insert(It, copy0MBB); 4314 F->insert(It, sinkMBB); 4315 4316 // Transfer the remainder of BB and its successor edges to sinkMBB. 4317 sinkMBB->splice(sinkMBB->begin(), BB, 4318 std::next(MachineBasicBlock::iterator(MI)), BB->end()); 4319 sinkMBB->transferSuccessorsAndUpdatePHIs(BB); 4320 4321 // Next, add the true and fallthrough blocks as its successors. 4322 BB->addSuccessor(copy0MBB); 4323 BB->addSuccessor(sinkMBB); 4324 4325 if (isFPCmp) { 4326 // bc1[tf] cc, sinkMBB 4327 BuildMI(BB, DL, TII->get(Opc)) 4328 .addReg(MI.getOperand(1).getReg()) 4329 .addMBB(sinkMBB); 4330 } else { 4331 // bne rs, $0, sinkMBB 4332 BuildMI(BB, DL, TII->get(Opc)) 4333 .addReg(MI.getOperand(1).getReg()) 4334 .addReg(Mips::ZERO) 4335 .addMBB(sinkMBB); 4336 } 4337 4338 // copy0MBB: 4339 // %FalseValue = ... 4340 // # fallthrough to sinkMBB 4341 BB = copy0MBB; 4342 4343 // Update machine-CFG edges 4344 BB->addSuccessor(sinkMBB); 4345 4346 // sinkMBB: 4347 // %Result = phi [ %TrueValue, thisMBB ], [ %FalseValue, copy0MBB ] 4348 // ... 4349 BB = sinkMBB; 4350 4351 BuildMI(*BB, BB->begin(), DL, TII->get(Mips::PHI), MI.getOperand(0).getReg()) 4352 .addReg(MI.getOperand(2).getReg()) 4353 .addMBB(thisMBB) 4354 .addReg(MI.getOperand(3).getReg()) 4355 .addMBB(copy0MBB); 4356 4357 MI.eraseFromParent(); // The pseudo instruction is gone now. 4358 4359 return BB; 4360 } 4361 4362 // FIXME? Maybe this could be a TableGen attribute on some registers and 4363 // this table could be generated automatically from RegInfo. 4364 unsigned MipsTargetLowering::getRegisterByName(const char* RegName, EVT VT, 4365 SelectionDAG &DAG) const { 4366 // Named registers is expected to be fairly rare. For now, just support $28 4367 // since the linux kernel uses it. 4368 if (Subtarget.isGP64bit()) { 4369 unsigned Reg = StringSwitch<unsigned>(RegName) 4370 .Case("$28", Mips::GP_64) 4371 .Default(0); 4372 if (Reg) 4373 return Reg; 4374 } else { 4375 unsigned Reg = StringSwitch<unsigned>(RegName) 4376 .Case("$28", Mips::GP) 4377 .Default(0); 4378 if (Reg) 4379 return Reg; 4380 } 4381 report_fatal_error("Invalid register name global variable"); 4382 } 4383