1 //===- MipsISelLowering.cpp - Mips DAG Lowering Implementation ------------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file defines the interfaces that Mips uses to lower LLVM code into a 11 // selection DAG. 12 // 13 //===----------------------------------------------------------------------===// 14 15 #include "MipsISelLowering.h" 16 #include "InstPrinter/MipsInstPrinter.h" 17 #include "MCTargetDesc/MipsBaseInfo.h" 18 #include "MCTargetDesc/MipsMCTargetDesc.h" 19 #include "MipsCCState.h" 20 #include "MipsInstrInfo.h" 21 #include "MipsMachineFunction.h" 22 #include "MipsRegisterInfo.h" 23 #include "MipsSubtarget.h" 24 #include "MipsTargetMachine.h" 25 #include "MipsTargetObjectFile.h" 26 #include "llvm/ADT/APFloat.h" 27 #include "llvm/ADT/ArrayRef.h" 28 #include "llvm/ADT/SmallVector.h" 29 #include "llvm/ADT/Statistic.h" 30 #include "llvm/ADT/StringRef.h" 31 #include "llvm/ADT/StringSwitch.h" 32 #include "llvm/CodeGen/CallingConvLower.h" 33 #include "llvm/CodeGen/FunctionLoweringInfo.h" 34 #include "llvm/CodeGen/ISDOpcodes.h" 35 #include "llvm/CodeGen/MachineBasicBlock.h" 36 #include "llvm/CodeGen/MachineFrameInfo.h" 37 #include "llvm/CodeGen/MachineFunction.h" 38 #include "llvm/CodeGen/MachineInstr.h" 39 #include "llvm/CodeGen/MachineInstrBuilder.h" 40 #include "llvm/CodeGen/MachineJumpTableInfo.h" 41 #include "llvm/CodeGen/MachineMemOperand.h" 42 #include "llvm/CodeGen/MachineOperand.h" 43 #include "llvm/CodeGen/MachineRegisterInfo.h" 44 #include "llvm/CodeGen/RuntimeLibcalls.h" 45 #include "llvm/CodeGen/SelectionDAG.h" 46 #include "llvm/CodeGen/SelectionDAGNodes.h" 47 #include "llvm/CodeGen/TargetFrameLowering.h" 48 #include "llvm/CodeGen/TargetInstrInfo.h" 49 #include "llvm/CodeGen/TargetRegisterInfo.h" 50 #include "llvm/CodeGen/ValueTypes.h" 51 #include "llvm/IR/CallingConv.h" 52 #include "llvm/IR/Constants.h" 53 #include "llvm/IR/DataLayout.h" 54 #include "llvm/IR/DebugLoc.h" 55 #include "llvm/IR/DerivedTypes.h" 56 #include "llvm/IR/Function.h" 57 #include "llvm/IR/GlobalValue.h" 58 #include "llvm/IR/Type.h" 59 #include "llvm/IR/Value.h" 60 #include "llvm/MC/MCRegisterInfo.h" 61 #include "llvm/Support/Casting.h" 62 #include "llvm/Support/CodeGen.h" 63 #include "llvm/Support/CommandLine.h" 64 #include "llvm/Support/Compiler.h" 65 #include "llvm/Support/ErrorHandling.h" 66 #include "llvm/Support/MachineValueType.h" 67 #include "llvm/Support/MathExtras.h" 68 #include "llvm/Target/TargetMachine.h" 69 #include "llvm/Target/TargetOptions.h" 70 #include <algorithm> 71 #include <cassert> 72 #include <cctype> 73 #include <cstdint> 74 #include <deque> 75 #include <iterator> 76 #include <utility> 77 #include <vector> 78 79 using namespace llvm; 80 81 #define DEBUG_TYPE "mips-lower" 82 83 STATISTIC(NumTailCalls, "Number of tail calls"); 84 85 static cl::opt<bool> 86 LargeGOT("mxgot", cl::Hidden, 87 cl::desc("MIPS: Enable GOT larger than 64k."), cl::init(false)); 88 89 static cl::opt<bool> 90 NoZeroDivCheck("mno-check-zero-division", cl::Hidden, 91 cl::desc("MIPS: Don't trap on integer division by zero."), 92 cl::init(false)); 93 94 static const MCPhysReg Mips64DPRegs[8] = { 95 Mips::D12_64, Mips::D13_64, Mips::D14_64, Mips::D15_64, 96 Mips::D16_64, Mips::D17_64, Mips::D18_64, Mips::D19_64 97 }; 98 99 // If I is a shifted mask, set the size (Size) and the first bit of the 100 // mask (Pos), and return true. 101 // For example, if I is 0x003ff800, (Pos, Size) = (11, 11). 102 static bool isShiftedMask(uint64_t I, uint64_t &Pos, uint64_t &Size) { 103 if (!isShiftedMask_64(I)) 104 return false; 105 106 Size = countPopulation(I); 107 Pos = countTrailingZeros(I); 108 return true; 109 } 110 111 // The MIPS MSA ABI passes vector arguments in the integer register set. 112 // The number of integer registers used is dependant on the ABI used. 113 MVT MipsTargetLowering::getRegisterTypeForCallingConv(MVT VT) const { 114 if (VT.isVector() && Subtarget.hasMSA()) 115 return Subtarget.isABI_O32() ? MVT::i32 : MVT::i64; 116 return MipsTargetLowering::getRegisterType(VT); 117 } 118 119 MVT MipsTargetLowering::getRegisterTypeForCallingConv(LLVMContext &Context, 120 EVT VT) const { 121 if (VT.isVector()) { 122 if (Subtarget.isABI_O32()) { 123 return MVT::i32; 124 } else { 125 return (VT.getSizeInBits() == 32) ? MVT::i32 : MVT::i64; 126 } 127 } 128 return MipsTargetLowering::getRegisterType(Context, VT); 129 } 130 131 unsigned MipsTargetLowering::getNumRegistersForCallingConv(LLVMContext &Context, 132 EVT VT) const { 133 if (VT.isVector()) 134 return std::max((VT.getSizeInBits() / (Subtarget.isABI_O32() ? 32 : 64)), 135 1U); 136 return MipsTargetLowering::getNumRegisters(Context, VT); 137 } 138 139 unsigned MipsTargetLowering::getVectorTypeBreakdownForCallingConv( 140 LLVMContext &Context, EVT VT, EVT &IntermediateVT, 141 unsigned &NumIntermediates, MVT &RegisterVT) const { 142 // Break down vector types to either 2 i64s or 4 i32s. 143 RegisterVT = getRegisterTypeForCallingConv(Context, VT) ; 144 IntermediateVT = RegisterVT; 145 NumIntermediates = VT.getSizeInBits() < RegisterVT.getSizeInBits() 146 ? VT.getVectorNumElements() 147 : VT.getSizeInBits() / RegisterVT.getSizeInBits(); 148 149 return NumIntermediates; 150 } 151 152 SDValue MipsTargetLowering::getGlobalReg(SelectionDAG &DAG, EVT Ty) const { 153 MipsFunctionInfo *FI = DAG.getMachineFunction().getInfo<MipsFunctionInfo>(); 154 return DAG.getRegister(FI->getGlobalBaseReg(), Ty); 155 } 156 157 SDValue MipsTargetLowering::getTargetNode(GlobalAddressSDNode *N, EVT Ty, 158 SelectionDAG &DAG, 159 unsigned Flag) const { 160 return DAG.getTargetGlobalAddress(N->getGlobal(), SDLoc(N), Ty, 0, Flag); 161 } 162 163 SDValue MipsTargetLowering::getTargetNode(ExternalSymbolSDNode *N, EVT Ty, 164 SelectionDAG &DAG, 165 unsigned Flag) const { 166 return DAG.getTargetExternalSymbol(N->getSymbol(), Ty, Flag); 167 } 168 169 SDValue MipsTargetLowering::getTargetNode(BlockAddressSDNode *N, EVT Ty, 170 SelectionDAG &DAG, 171 unsigned Flag) const { 172 return DAG.getTargetBlockAddress(N->getBlockAddress(), Ty, 0, Flag); 173 } 174 175 SDValue MipsTargetLowering::getTargetNode(JumpTableSDNode *N, EVT Ty, 176 SelectionDAG &DAG, 177 unsigned Flag) const { 178 return DAG.getTargetJumpTable(N->getIndex(), Ty, Flag); 179 } 180 181 SDValue MipsTargetLowering::getTargetNode(ConstantPoolSDNode *N, EVT Ty, 182 SelectionDAG &DAG, 183 unsigned Flag) const { 184 return DAG.getTargetConstantPool(N->getConstVal(), Ty, N->getAlignment(), 185 N->getOffset(), Flag); 186 } 187 188 const char *MipsTargetLowering::getTargetNodeName(unsigned Opcode) const { 189 switch ((MipsISD::NodeType)Opcode) { 190 case MipsISD::FIRST_NUMBER: break; 191 case MipsISD::JmpLink: return "MipsISD::JmpLink"; 192 case MipsISD::TailCall: return "MipsISD::TailCall"; 193 case MipsISD::Highest: return "MipsISD::Highest"; 194 case MipsISD::Higher: return "MipsISD::Higher"; 195 case MipsISD::Hi: return "MipsISD::Hi"; 196 case MipsISD::Lo: return "MipsISD::Lo"; 197 case MipsISD::GotHi: return "MipsISD::GotHi"; 198 case MipsISD::GPRel: return "MipsISD::GPRel"; 199 case MipsISD::ThreadPointer: return "MipsISD::ThreadPointer"; 200 case MipsISD::Ret: return "MipsISD::Ret"; 201 case MipsISD::ERet: return "MipsISD::ERet"; 202 case MipsISD::EH_RETURN: return "MipsISD::EH_RETURN"; 203 case MipsISD::FPBrcond: return "MipsISD::FPBrcond"; 204 case MipsISD::FPCmp: return "MipsISD::FPCmp"; 205 case MipsISD::FSELECT: return "MipsISD::FSELECT"; 206 case MipsISD::MTC1_D64: return "MipsISD::MTC1_D64"; 207 case MipsISD::CMovFP_T: return "MipsISD::CMovFP_T"; 208 case MipsISD::CMovFP_F: return "MipsISD::CMovFP_F"; 209 case MipsISD::TruncIntFP: return "MipsISD::TruncIntFP"; 210 case MipsISD::MFHI: return "MipsISD::MFHI"; 211 case MipsISD::MFLO: return "MipsISD::MFLO"; 212 case MipsISD::MTLOHI: return "MipsISD::MTLOHI"; 213 case MipsISD::Mult: return "MipsISD::Mult"; 214 case MipsISD::Multu: return "MipsISD::Multu"; 215 case MipsISD::MAdd: return "MipsISD::MAdd"; 216 case MipsISD::MAddu: return "MipsISD::MAddu"; 217 case MipsISD::MSub: return "MipsISD::MSub"; 218 case MipsISD::MSubu: return "MipsISD::MSubu"; 219 case MipsISD::DivRem: return "MipsISD::DivRem"; 220 case MipsISD::DivRemU: return "MipsISD::DivRemU"; 221 case MipsISD::DivRem16: return "MipsISD::DivRem16"; 222 case MipsISD::DivRemU16: return "MipsISD::DivRemU16"; 223 case MipsISD::BuildPairF64: return "MipsISD::BuildPairF64"; 224 case MipsISD::ExtractElementF64: return "MipsISD::ExtractElementF64"; 225 case MipsISD::Wrapper: return "MipsISD::Wrapper"; 226 case MipsISD::DynAlloc: return "MipsISD::DynAlloc"; 227 case MipsISD::Sync: return "MipsISD::Sync"; 228 case MipsISD::Ext: return "MipsISD::Ext"; 229 case MipsISD::Ins: return "MipsISD::Ins"; 230 case MipsISD::CIns: return "MipsISD::CIns"; 231 case MipsISD::LWL: return "MipsISD::LWL"; 232 case MipsISD::LWR: return "MipsISD::LWR"; 233 case MipsISD::SWL: return "MipsISD::SWL"; 234 case MipsISD::SWR: return "MipsISD::SWR"; 235 case MipsISD::LDL: return "MipsISD::LDL"; 236 case MipsISD::LDR: return "MipsISD::LDR"; 237 case MipsISD::SDL: return "MipsISD::SDL"; 238 case MipsISD::SDR: return "MipsISD::SDR"; 239 case MipsISD::EXTP: return "MipsISD::EXTP"; 240 case MipsISD::EXTPDP: return "MipsISD::EXTPDP"; 241 case MipsISD::EXTR_S_H: return "MipsISD::EXTR_S_H"; 242 case MipsISD::EXTR_W: return "MipsISD::EXTR_W"; 243 case MipsISD::EXTR_R_W: return "MipsISD::EXTR_R_W"; 244 case MipsISD::EXTR_RS_W: return "MipsISD::EXTR_RS_W"; 245 case MipsISD::SHILO: return "MipsISD::SHILO"; 246 case MipsISD::MTHLIP: return "MipsISD::MTHLIP"; 247 case MipsISD::MULSAQ_S_W_PH: return "MipsISD::MULSAQ_S_W_PH"; 248 case MipsISD::MAQ_S_W_PHL: return "MipsISD::MAQ_S_W_PHL"; 249 case MipsISD::MAQ_S_W_PHR: return "MipsISD::MAQ_S_W_PHR"; 250 case MipsISD::MAQ_SA_W_PHL: return "MipsISD::MAQ_SA_W_PHL"; 251 case MipsISD::MAQ_SA_W_PHR: return "MipsISD::MAQ_SA_W_PHR"; 252 case MipsISD::DPAU_H_QBL: return "MipsISD::DPAU_H_QBL"; 253 case MipsISD::DPAU_H_QBR: return "MipsISD::DPAU_H_QBR"; 254 case MipsISD::DPSU_H_QBL: return "MipsISD::DPSU_H_QBL"; 255 case MipsISD::DPSU_H_QBR: return "MipsISD::DPSU_H_QBR"; 256 case MipsISD::DPAQ_S_W_PH: return "MipsISD::DPAQ_S_W_PH"; 257 case MipsISD::DPSQ_S_W_PH: return "MipsISD::DPSQ_S_W_PH"; 258 case MipsISD::DPAQ_SA_L_W: return "MipsISD::DPAQ_SA_L_W"; 259 case MipsISD::DPSQ_SA_L_W: return "MipsISD::DPSQ_SA_L_W"; 260 case MipsISD::DPA_W_PH: return "MipsISD::DPA_W_PH"; 261 case MipsISD::DPS_W_PH: return "MipsISD::DPS_W_PH"; 262 case MipsISD::DPAQX_S_W_PH: return "MipsISD::DPAQX_S_W_PH"; 263 case MipsISD::DPAQX_SA_W_PH: return "MipsISD::DPAQX_SA_W_PH"; 264 case MipsISD::DPAX_W_PH: return "MipsISD::DPAX_W_PH"; 265 case MipsISD::DPSX_W_PH: return "MipsISD::DPSX_W_PH"; 266 case MipsISD::DPSQX_S_W_PH: return "MipsISD::DPSQX_S_W_PH"; 267 case MipsISD::DPSQX_SA_W_PH: return "MipsISD::DPSQX_SA_W_PH"; 268 case MipsISD::MULSA_W_PH: return "MipsISD::MULSA_W_PH"; 269 case MipsISD::MULT: return "MipsISD::MULT"; 270 case MipsISD::MULTU: return "MipsISD::MULTU"; 271 case MipsISD::MADD_DSP: return "MipsISD::MADD_DSP"; 272 case MipsISD::MADDU_DSP: return "MipsISD::MADDU_DSP"; 273 case MipsISD::MSUB_DSP: return "MipsISD::MSUB_DSP"; 274 case MipsISD::MSUBU_DSP: return "MipsISD::MSUBU_DSP"; 275 case MipsISD::SHLL_DSP: return "MipsISD::SHLL_DSP"; 276 case MipsISD::SHRA_DSP: return "MipsISD::SHRA_DSP"; 277 case MipsISD::SHRL_DSP: return "MipsISD::SHRL_DSP"; 278 case MipsISD::SETCC_DSP: return "MipsISD::SETCC_DSP"; 279 case MipsISD::SELECT_CC_DSP: return "MipsISD::SELECT_CC_DSP"; 280 case MipsISD::VALL_ZERO: return "MipsISD::VALL_ZERO"; 281 case MipsISD::VANY_ZERO: return "MipsISD::VANY_ZERO"; 282 case MipsISD::VALL_NONZERO: return "MipsISD::VALL_NONZERO"; 283 case MipsISD::VANY_NONZERO: return "MipsISD::VANY_NONZERO"; 284 case MipsISD::VCEQ: return "MipsISD::VCEQ"; 285 case MipsISD::VCLE_S: return "MipsISD::VCLE_S"; 286 case MipsISD::VCLE_U: return "MipsISD::VCLE_U"; 287 case MipsISD::VCLT_S: return "MipsISD::VCLT_S"; 288 case MipsISD::VCLT_U: return "MipsISD::VCLT_U"; 289 case MipsISD::VEXTRACT_SEXT_ELT: return "MipsISD::VEXTRACT_SEXT_ELT"; 290 case MipsISD::VEXTRACT_ZEXT_ELT: return "MipsISD::VEXTRACT_ZEXT_ELT"; 291 case MipsISD::VNOR: return "MipsISD::VNOR"; 292 case MipsISD::VSHF: return "MipsISD::VSHF"; 293 case MipsISD::SHF: return "MipsISD::SHF"; 294 case MipsISD::ILVEV: return "MipsISD::ILVEV"; 295 case MipsISD::ILVOD: return "MipsISD::ILVOD"; 296 case MipsISD::ILVL: return "MipsISD::ILVL"; 297 case MipsISD::ILVR: return "MipsISD::ILVR"; 298 case MipsISD::PCKEV: return "MipsISD::PCKEV"; 299 case MipsISD::PCKOD: return "MipsISD::PCKOD"; 300 case MipsISD::INSVE: return "MipsISD::INSVE"; 301 } 302 return nullptr; 303 } 304 305 MipsTargetLowering::MipsTargetLowering(const MipsTargetMachine &TM, 306 const MipsSubtarget &STI) 307 : TargetLowering(TM), Subtarget(STI), ABI(TM.getABI()) { 308 // Mips does not have i1 type, so use i32 for 309 // setcc operations results (slt, sgt, ...). 310 setBooleanContents(ZeroOrOneBooleanContent); 311 setBooleanVectorContents(ZeroOrNegativeOneBooleanContent); 312 // The cmp.cond.fmt instruction in MIPS32r6/MIPS64r6 uses 0 and -1 like MSA 313 // does. Integer booleans still use 0 and 1. 314 if (Subtarget.hasMips32r6()) 315 setBooleanContents(ZeroOrOneBooleanContent, 316 ZeroOrNegativeOneBooleanContent); 317 318 // Load extented operations for i1 types must be promoted 319 for (MVT VT : MVT::integer_valuetypes()) { 320 setLoadExtAction(ISD::EXTLOAD, VT, MVT::i1, Promote); 321 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i1, Promote); 322 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i1, Promote); 323 } 324 325 // MIPS doesn't have extending float->double load/store. Set LoadExtAction 326 // for f32, f16 327 for (MVT VT : MVT::fp_valuetypes()) { 328 setLoadExtAction(ISD::EXTLOAD, VT, MVT::f32, Expand); 329 setLoadExtAction(ISD::EXTLOAD, VT, MVT::f16, Expand); 330 } 331 332 // Set LoadExtAction for f16 vectors to Expand 333 for (MVT VT : MVT::fp_vector_valuetypes()) { 334 MVT F16VT = MVT::getVectorVT(MVT::f16, VT.getVectorNumElements()); 335 if (F16VT.isValid()) 336 setLoadExtAction(ISD::EXTLOAD, VT, F16VT, Expand); 337 } 338 339 setTruncStoreAction(MVT::f32, MVT::f16, Expand); 340 setTruncStoreAction(MVT::f64, MVT::f16, Expand); 341 342 setTruncStoreAction(MVT::f64, MVT::f32, Expand); 343 344 // Used by legalize types to correctly generate the setcc result. 345 // Without this, every float setcc comes with a AND/OR with the result, 346 // we don't want this, since the fpcmp result goes to a flag register, 347 // which is used implicitly by brcond and select operations. 348 AddPromotedToType(ISD::SETCC, MVT::i1, MVT::i32); 349 350 // Mips Custom Operations 351 setOperationAction(ISD::BR_JT, MVT::Other, Expand); 352 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom); 353 setOperationAction(ISD::BlockAddress, MVT::i32, Custom); 354 setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom); 355 setOperationAction(ISD::JumpTable, MVT::i32, Custom); 356 setOperationAction(ISD::ConstantPool, MVT::i32, Custom); 357 setOperationAction(ISD::SELECT, MVT::f32, Custom); 358 setOperationAction(ISD::SELECT, MVT::f64, Custom); 359 setOperationAction(ISD::SELECT, MVT::i32, Custom); 360 setOperationAction(ISD::SETCC, MVT::f32, Custom); 361 setOperationAction(ISD::SETCC, MVT::f64, Custom); 362 setOperationAction(ISD::BRCOND, MVT::Other, Custom); 363 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom); 364 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom); 365 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom); 366 367 if (Subtarget.isGP64bit()) { 368 setOperationAction(ISD::GlobalAddress, MVT::i64, Custom); 369 setOperationAction(ISD::BlockAddress, MVT::i64, Custom); 370 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom); 371 setOperationAction(ISD::JumpTable, MVT::i64, Custom); 372 setOperationAction(ISD::ConstantPool, MVT::i64, Custom); 373 setOperationAction(ISD::SELECT, MVT::i64, Custom); 374 setOperationAction(ISD::LOAD, MVT::i64, Custom); 375 setOperationAction(ISD::STORE, MVT::i64, Custom); 376 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom); 377 setOperationAction(ISD::SHL_PARTS, MVT::i64, Custom); 378 setOperationAction(ISD::SRA_PARTS, MVT::i64, Custom); 379 setOperationAction(ISD::SRL_PARTS, MVT::i64, Custom); 380 } 381 382 if (!Subtarget.isGP64bit()) { 383 setOperationAction(ISD::SHL_PARTS, MVT::i32, Custom); 384 setOperationAction(ISD::SRA_PARTS, MVT::i32, Custom); 385 setOperationAction(ISD::SRL_PARTS, MVT::i32, Custom); 386 } 387 388 setOperationAction(ISD::EH_DWARF_CFA, MVT::i32, Custom); 389 if (Subtarget.isGP64bit()) 390 setOperationAction(ISD::EH_DWARF_CFA, MVT::i64, Custom); 391 392 setOperationAction(ISD::SDIV, MVT::i32, Expand); 393 setOperationAction(ISD::SREM, MVT::i32, Expand); 394 setOperationAction(ISD::UDIV, MVT::i32, Expand); 395 setOperationAction(ISD::UREM, MVT::i32, Expand); 396 setOperationAction(ISD::SDIV, MVT::i64, Expand); 397 setOperationAction(ISD::SREM, MVT::i64, Expand); 398 setOperationAction(ISD::UDIV, MVT::i64, Expand); 399 setOperationAction(ISD::UREM, MVT::i64, Expand); 400 401 if (!(Subtarget.hasDSP() && Subtarget.hasMips32r2())) { 402 setOperationAction(ISD::ADDC, MVT::i32, Expand); 403 setOperationAction(ISD::ADDE, MVT::i32, Expand); 404 } 405 406 setOperationAction(ISD::ADDC, MVT::i64, Expand); 407 setOperationAction(ISD::ADDE, MVT::i64, Expand); 408 setOperationAction(ISD::SUBC, MVT::i32, Expand); 409 setOperationAction(ISD::SUBE, MVT::i32, Expand); 410 setOperationAction(ISD::SUBC, MVT::i64, Expand); 411 setOperationAction(ISD::SUBE, MVT::i64, Expand); 412 413 // Operations not directly supported by Mips. 414 setOperationAction(ISD::BR_CC, MVT::f32, Expand); 415 setOperationAction(ISD::BR_CC, MVT::f64, Expand); 416 setOperationAction(ISD::BR_CC, MVT::i32, Expand); 417 setOperationAction(ISD::BR_CC, MVT::i64, Expand); 418 setOperationAction(ISD::SELECT_CC, MVT::i32, Expand); 419 setOperationAction(ISD::SELECT_CC, MVT::i64, Expand); 420 setOperationAction(ISD::SELECT_CC, MVT::f32, Expand); 421 setOperationAction(ISD::SELECT_CC, MVT::f64, Expand); 422 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand); 423 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Expand); 424 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand); 425 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Expand); 426 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand); 427 if (Subtarget.hasCnMips()) { 428 setOperationAction(ISD::CTPOP, MVT::i32, Legal); 429 setOperationAction(ISD::CTPOP, MVT::i64, Legal); 430 } else { 431 setOperationAction(ISD::CTPOP, MVT::i32, Expand); 432 setOperationAction(ISD::CTPOP, MVT::i64, Expand); 433 } 434 setOperationAction(ISD::CTTZ, MVT::i32, Expand); 435 setOperationAction(ISD::CTTZ, MVT::i64, Expand); 436 setOperationAction(ISD::ROTL, MVT::i32, Expand); 437 setOperationAction(ISD::ROTL, MVT::i64, Expand); 438 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Expand); 439 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64, Expand); 440 441 if (!Subtarget.hasMips32r2()) 442 setOperationAction(ISD::ROTR, MVT::i32, Expand); 443 444 if (!Subtarget.hasMips64r2()) 445 setOperationAction(ISD::ROTR, MVT::i64, Expand); 446 447 setOperationAction(ISD::FSIN, MVT::f32, Expand); 448 setOperationAction(ISD::FSIN, MVT::f64, Expand); 449 setOperationAction(ISD::FCOS, MVT::f32, Expand); 450 setOperationAction(ISD::FCOS, MVT::f64, Expand); 451 setOperationAction(ISD::FSINCOS, MVT::f32, Expand); 452 setOperationAction(ISD::FSINCOS, MVT::f64, Expand); 453 setOperationAction(ISD::FPOW, MVT::f32, Expand); 454 setOperationAction(ISD::FPOW, MVT::f64, Expand); 455 setOperationAction(ISD::FLOG, MVT::f32, Expand); 456 setOperationAction(ISD::FLOG2, MVT::f32, Expand); 457 setOperationAction(ISD::FLOG10, MVT::f32, Expand); 458 setOperationAction(ISD::FEXP, MVT::f32, Expand); 459 setOperationAction(ISD::FMA, MVT::f32, Expand); 460 setOperationAction(ISD::FMA, MVT::f64, Expand); 461 setOperationAction(ISD::FREM, MVT::f32, Expand); 462 setOperationAction(ISD::FREM, MVT::f64, Expand); 463 464 // Lower f16 conversion operations into library calls 465 setOperationAction(ISD::FP16_TO_FP, MVT::f32, Expand); 466 setOperationAction(ISD::FP_TO_FP16, MVT::f32, Expand); 467 setOperationAction(ISD::FP16_TO_FP, MVT::f64, Expand); 468 setOperationAction(ISD::FP_TO_FP16, MVT::f64, Expand); 469 470 setOperationAction(ISD::EH_RETURN, MVT::Other, Custom); 471 472 setOperationAction(ISD::VASTART, MVT::Other, Custom); 473 setOperationAction(ISD::VAARG, MVT::Other, Custom); 474 setOperationAction(ISD::VACOPY, MVT::Other, Expand); 475 setOperationAction(ISD::VAEND, MVT::Other, Expand); 476 477 // Use the default for now 478 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand); 479 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand); 480 481 if (!Subtarget.isGP64bit()) { 482 setOperationAction(ISD::ATOMIC_LOAD, MVT::i64, Expand); 483 setOperationAction(ISD::ATOMIC_STORE, MVT::i64, Expand); 484 } 485 486 if (!Subtarget.hasMips32r2()) { 487 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8, Expand); 488 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand); 489 } 490 491 // MIPS16 lacks MIPS32's clz and clo instructions. 492 if (!Subtarget.hasMips32() || Subtarget.inMips16Mode()) 493 setOperationAction(ISD::CTLZ, MVT::i32, Expand); 494 if (!Subtarget.hasMips64()) 495 setOperationAction(ISD::CTLZ, MVT::i64, Expand); 496 497 if (!Subtarget.hasMips32r2()) 498 setOperationAction(ISD::BSWAP, MVT::i32, Expand); 499 if (!Subtarget.hasMips64r2()) 500 setOperationAction(ISD::BSWAP, MVT::i64, Expand); 501 502 if (Subtarget.isGP64bit()) { 503 setLoadExtAction(ISD::SEXTLOAD, MVT::i64, MVT::i32, Custom); 504 setLoadExtAction(ISD::ZEXTLOAD, MVT::i64, MVT::i32, Custom); 505 setLoadExtAction(ISD::EXTLOAD, MVT::i64, MVT::i32, Custom); 506 setTruncStoreAction(MVT::i64, MVT::i32, Custom); 507 } 508 509 setOperationAction(ISD::TRAP, MVT::Other, Legal); 510 511 setTargetDAGCombine(ISD::SDIVREM); 512 setTargetDAGCombine(ISD::UDIVREM); 513 setTargetDAGCombine(ISD::SELECT); 514 setTargetDAGCombine(ISD::AND); 515 setTargetDAGCombine(ISD::OR); 516 setTargetDAGCombine(ISD::ADD); 517 setTargetDAGCombine(ISD::SUB); 518 setTargetDAGCombine(ISD::AssertZext); 519 setTargetDAGCombine(ISD::SHL); 520 521 if (ABI.IsO32()) { 522 // These libcalls are not available in 32-bit. 523 setLibcallName(RTLIB::SHL_I128, nullptr); 524 setLibcallName(RTLIB::SRL_I128, nullptr); 525 setLibcallName(RTLIB::SRA_I128, nullptr); 526 } 527 528 setMinFunctionAlignment(Subtarget.isGP64bit() ? 3 : 2); 529 530 // The arguments on the stack are defined in terms of 4-byte slots on O32 531 // and 8-byte slots on N32/N64. 532 setMinStackArgumentAlignment((ABI.IsN32() || ABI.IsN64()) ? 8 : 4); 533 534 setStackPointerRegisterToSaveRestore(ABI.IsN64() ? Mips::SP_64 : Mips::SP); 535 536 MaxStoresPerMemcpy = 16; 537 538 isMicroMips = Subtarget.inMicroMipsMode(); 539 } 540 541 const MipsTargetLowering *MipsTargetLowering::create(const MipsTargetMachine &TM, 542 const MipsSubtarget &STI) { 543 if (STI.inMips16Mode()) 544 return createMips16TargetLowering(TM, STI); 545 546 return createMipsSETargetLowering(TM, STI); 547 } 548 549 // Create a fast isel object. 550 FastISel * 551 MipsTargetLowering::createFastISel(FunctionLoweringInfo &funcInfo, 552 const TargetLibraryInfo *libInfo) const { 553 const MipsTargetMachine &TM = 554 static_cast<const MipsTargetMachine &>(funcInfo.MF->getTarget()); 555 556 // We support only the standard encoding [MIPS32,MIPS32R5] ISAs. 557 bool UseFastISel = TM.Options.EnableFastISel && Subtarget.hasMips32() && 558 !Subtarget.hasMips32r6() && !Subtarget.inMips16Mode() && 559 !Subtarget.inMicroMipsMode(); 560 561 // Disable if either of the following is true: 562 // We do not generate PIC, the ABI is not O32, LargeGOT is being used. 563 if (!TM.isPositionIndependent() || !TM.getABI().IsO32() || LargeGOT) 564 UseFastISel = false; 565 566 return UseFastISel ? Mips::createFastISel(funcInfo, libInfo) : nullptr; 567 } 568 569 EVT MipsTargetLowering::getSetCCResultType(const DataLayout &, LLVMContext &, 570 EVT VT) const { 571 if (!VT.isVector()) 572 return MVT::i32; 573 return VT.changeVectorElementTypeToInteger(); 574 } 575 576 static SDValue performDivRemCombine(SDNode *N, SelectionDAG &DAG, 577 TargetLowering::DAGCombinerInfo &DCI, 578 const MipsSubtarget &Subtarget) { 579 if (DCI.isBeforeLegalizeOps()) 580 return SDValue(); 581 582 EVT Ty = N->getValueType(0); 583 unsigned LO = (Ty == MVT::i32) ? Mips::LO0 : Mips::LO0_64; 584 unsigned HI = (Ty == MVT::i32) ? Mips::HI0 : Mips::HI0_64; 585 unsigned Opc = N->getOpcode() == ISD::SDIVREM ? MipsISD::DivRem16 : 586 MipsISD::DivRemU16; 587 SDLoc DL(N); 588 589 SDValue DivRem = DAG.getNode(Opc, DL, MVT::Glue, 590 N->getOperand(0), N->getOperand(1)); 591 SDValue InChain = DAG.getEntryNode(); 592 SDValue InGlue = DivRem; 593 594 // insert MFLO 595 if (N->hasAnyUseOfValue(0)) { 596 SDValue CopyFromLo = DAG.getCopyFromReg(InChain, DL, LO, Ty, 597 InGlue); 598 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), CopyFromLo); 599 InChain = CopyFromLo.getValue(1); 600 InGlue = CopyFromLo.getValue(2); 601 } 602 603 // insert MFHI 604 if (N->hasAnyUseOfValue(1)) { 605 SDValue CopyFromHi = DAG.getCopyFromReg(InChain, DL, 606 HI, Ty, InGlue); 607 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), CopyFromHi); 608 } 609 610 return SDValue(); 611 } 612 613 static Mips::CondCode condCodeToFCC(ISD::CondCode CC) { 614 switch (CC) { 615 default: llvm_unreachable("Unknown fp condition code!"); 616 case ISD::SETEQ: 617 case ISD::SETOEQ: return Mips::FCOND_OEQ; 618 case ISD::SETUNE: return Mips::FCOND_UNE; 619 case ISD::SETLT: 620 case ISD::SETOLT: return Mips::FCOND_OLT; 621 case ISD::SETGT: 622 case ISD::SETOGT: return Mips::FCOND_OGT; 623 case ISD::SETLE: 624 case ISD::SETOLE: return Mips::FCOND_OLE; 625 case ISD::SETGE: 626 case ISD::SETOGE: return Mips::FCOND_OGE; 627 case ISD::SETULT: return Mips::FCOND_ULT; 628 case ISD::SETULE: return Mips::FCOND_ULE; 629 case ISD::SETUGT: return Mips::FCOND_UGT; 630 case ISD::SETUGE: return Mips::FCOND_UGE; 631 case ISD::SETUO: return Mips::FCOND_UN; 632 case ISD::SETO: return Mips::FCOND_OR; 633 case ISD::SETNE: 634 case ISD::SETONE: return Mips::FCOND_ONE; 635 case ISD::SETUEQ: return Mips::FCOND_UEQ; 636 } 637 } 638 639 /// This function returns true if the floating point conditional branches and 640 /// conditional moves which use condition code CC should be inverted. 641 static bool invertFPCondCodeUser(Mips::CondCode CC) { 642 if (CC >= Mips::FCOND_F && CC <= Mips::FCOND_NGT) 643 return false; 644 645 assert((CC >= Mips::FCOND_T && CC <= Mips::FCOND_GT) && 646 "Illegal Condition Code"); 647 648 return true; 649 } 650 651 // Creates and returns an FPCmp node from a setcc node. 652 // Returns Op if setcc is not a floating point comparison. 653 static SDValue createFPCmp(SelectionDAG &DAG, const SDValue &Op) { 654 // must be a SETCC node 655 if (Op.getOpcode() != ISD::SETCC) 656 return Op; 657 658 SDValue LHS = Op.getOperand(0); 659 660 if (!LHS.getValueType().isFloatingPoint()) 661 return Op; 662 663 SDValue RHS = Op.getOperand(1); 664 SDLoc DL(Op); 665 666 // Assume the 3rd operand is a CondCodeSDNode. Add code to check the type of 667 // node if necessary. 668 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get(); 669 670 return DAG.getNode(MipsISD::FPCmp, DL, MVT::Glue, LHS, RHS, 671 DAG.getConstant(condCodeToFCC(CC), DL, MVT::i32)); 672 } 673 674 // Creates and returns a CMovFPT/F node. 675 static SDValue createCMovFP(SelectionDAG &DAG, SDValue Cond, SDValue True, 676 SDValue False, const SDLoc &DL) { 677 ConstantSDNode *CC = cast<ConstantSDNode>(Cond.getOperand(2)); 678 bool invert = invertFPCondCodeUser((Mips::CondCode)CC->getSExtValue()); 679 SDValue FCC0 = DAG.getRegister(Mips::FCC0, MVT::i32); 680 681 return DAG.getNode((invert ? MipsISD::CMovFP_F : MipsISD::CMovFP_T), DL, 682 True.getValueType(), True, FCC0, False, Cond); 683 } 684 685 static SDValue performSELECTCombine(SDNode *N, SelectionDAG &DAG, 686 TargetLowering::DAGCombinerInfo &DCI, 687 const MipsSubtarget &Subtarget) { 688 if (DCI.isBeforeLegalizeOps()) 689 return SDValue(); 690 691 SDValue SetCC = N->getOperand(0); 692 693 if ((SetCC.getOpcode() != ISD::SETCC) || 694 !SetCC.getOperand(0).getValueType().isInteger()) 695 return SDValue(); 696 697 SDValue False = N->getOperand(2); 698 EVT FalseTy = False.getValueType(); 699 700 if (!FalseTy.isInteger()) 701 return SDValue(); 702 703 ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(False); 704 705 // If the RHS (False) is 0, we swap the order of the operands 706 // of ISD::SELECT (obviously also inverting the condition) so that we can 707 // take advantage of conditional moves using the $0 register. 708 // Example: 709 // return (a != 0) ? x : 0; 710 // load $reg, x 711 // movz $reg, $0, a 712 if (!FalseC) 713 return SDValue(); 714 715 const SDLoc DL(N); 716 717 if (!FalseC->getZExtValue()) { 718 ISD::CondCode CC = cast<CondCodeSDNode>(SetCC.getOperand(2))->get(); 719 SDValue True = N->getOperand(1); 720 721 SetCC = DAG.getSetCC(DL, SetCC.getValueType(), SetCC.getOperand(0), 722 SetCC.getOperand(1), ISD::getSetCCInverse(CC, true)); 723 724 return DAG.getNode(ISD::SELECT, DL, FalseTy, SetCC, False, True); 725 } 726 727 // If both operands are integer constants there's a possibility that we 728 // can do some interesting optimizations. 729 SDValue True = N->getOperand(1); 730 ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(True); 731 732 if (!TrueC || !True.getValueType().isInteger()) 733 return SDValue(); 734 735 // We'll also ignore MVT::i64 operands as this optimizations proves 736 // to be ineffective because of the required sign extensions as the result 737 // of a SETCC operator is always MVT::i32 for non-vector types. 738 if (True.getValueType() == MVT::i64) 739 return SDValue(); 740 741 int64_t Diff = TrueC->getSExtValue() - FalseC->getSExtValue(); 742 743 // 1) (a < x) ? y : y-1 744 // slti $reg1, a, x 745 // addiu $reg2, $reg1, y-1 746 if (Diff == 1) 747 return DAG.getNode(ISD::ADD, DL, SetCC.getValueType(), SetCC, False); 748 749 // 2) (a < x) ? y-1 : y 750 // slti $reg1, a, x 751 // xor $reg1, $reg1, 1 752 // addiu $reg2, $reg1, y-1 753 if (Diff == -1) { 754 ISD::CondCode CC = cast<CondCodeSDNode>(SetCC.getOperand(2))->get(); 755 SetCC = DAG.getSetCC(DL, SetCC.getValueType(), SetCC.getOperand(0), 756 SetCC.getOperand(1), ISD::getSetCCInverse(CC, true)); 757 return DAG.getNode(ISD::ADD, DL, SetCC.getValueType(), SetCC, True); 758 } 759 760 // Couldn't optimize. 761 return SDValue(); 762 } 763 764 static SDValue performCMovFPCombine(SDNode *N, SelectionDAG &DAG, 765 TargetLowering::DAGCombinerInfo &DCI, 766 const MipsSubtarget &Subtarget) { 767 if (DCI.isBeforeLegalizeOps()) 768 return SDValue(); 769 770 SDValue ValueIfTrue = N->getOperand(0), ValueIfFalse = N->getOperand(2); 771 772 ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(ValueIfFalse); 773 if (!FalseC || FalseC->getZExtValue()) 774 return SDValue(); 775 776 // Since RHS (False) is 0, we swap the order of the True/False operands 777 // (obviously also inverting the condition) so that we can 778 // take advantage of conditional moves using the $0 register. 779 // Example: 780 // return (a != 0) ? x : 0; 781 // load $reg, x 782 // movz $reg, $0, a 783 unsigned Opc = (N->getOpcode() == MipsISD::CMovFP_T) ? MipsISD::CMovFP_F : 784 MipsISD::CMovFP_T; 785 786 SDValue FCC = N->getOperand(1), Glue = N->getOperand(3); 787 return DAG.getNode(Opc, SDLoc(N), ValueIfFalse.getValueType(), 788 ValueIfFalse, FCC, ValueIfTrue, Glue); 789 } 790 791 static SDValue performANDCombine(SDNode *N, SelectionDAG &DAG, 792 TargetLowering::DAGCombinerInfo &DCI, 793 const MipsSubtarget &Subtarget) { 794 if (DCI.isBeforeLegalizeOps() || !Subtarget.hasExtractInsert()) 795 return SDValue(); 796 797 SDValue FirstOperand = N->getOperand(0); 798 unsigned FirstOperandOpc = FirstOperand.getOpcode(); 799 SDValue Mask = N->getOperand(1); 800 EVT ValTy = N->getValueType(0); 801 SDLoc DL(N); 802 803 uint64_t Pos = 0, SMPos, SMSize; 804 ConstantSDNode *CN; 805 SDValue NewOperand; 806 unsigned Opc; 807 808 // Op's second operand must be a shifted mask. 809 if (!(CN = dyn_cast<ConstantSDNode>(Mask)) || 810 !isShiftedMask(CN->getZExtValue(), SMPos, SMSize)) 811 return SDValue(); 812 813 if (FirstOperandOpc == ISD::SRA || FirstOperandOpc == ISD::SRL) { 814 // Pattern match EXT. 815 // $dst = and ((sra or srl) $src , pos), (2**size - 1) 816 // => ext $dst, $src, pos, size 817 818 // The second operand of the shift must be an immediate. 819 if (!(CN = dyn_cast<ConstantSDNode>(FirstOperand.getOperand(1)))) 820 return SDValue(); 821 822 Pos = CN->getZExtValue(); 823 824 // Return if the shifted mask does not start at bit 0 or the sum of its size 825 // and Pos exceeds the word's size. 826 if (SMPos != 0 || Pos + SMSize > ValTy.getSizeInBits()) 827 return SDValue(); 828 829 Opc = MipsISD::Ext; 830 NewOperand = FirstOperand.getOperand(0); 831 } else if (FirstOperandOpc == ISD::SHL && Subtarget.hasCnMips()) { 832 // Pattern match CINS. 833 // $dst = and (shl $src , pos), mask 834 // => cins $dst, $src, pos, size 835 // mask is a shifted mask with consecutive 1's, pos = shift amount, 836 // size = population count. 837 838 // The second operand of the shift must be an immediate. 839 if (!(CN = dyn_cast<ConstantSDNode>(FirstOperand.getOperand(1)))) 840 return SDValue(); 841 842 Pos = CN->getZExtValue(); 843 844 if (SMPos != Pos || Pos >= ValTy.getSizeInBits() || SMSize >= 32 || 845 Pos + SMSize > ValTy.getSizeInBits()) 846 return SDValue(); 847 848 NewOperand = FirstOperand.getOperand(0); 849 // SMSize is 'location' (position) in this case, not size. 850 SMSize--; 851 Opc = MipsISD::CIns; 852 } else { 853 // Pattern match EXT. 854 // $dst = and $src, (2**size - 1) , if size > 16 855 // => ext $dst, $src, pos, size , pos = 0 856 857 // If the mask is <= 0xffff, andi can be used instead. 858 if (CN->getZExtValue() <= 0xffff) 859 return SDValue(); 860 861 // Return if the mask doesn't start at position 0. 862 if (SMPos) 863 return SDValue(); 864 865 Opc = MipsISD::Ext; 866 NewOperand = FirstOperand; 867 } 868 return DAG.getNode(Opc, DL, ValTy, NewOperand, 869 DAG.getConstant(Pos, DL, MVT::i32), 870 DAG.getConstant(SMSize, DL, MVT::i32)); 871 } 872 873 static SDValue performORCombine(SDNode *N, SelectionDAG &DAG, 874 TargetLowering::DAGCombinerInfo &DCI, 875 const MipsSubtarget &Subtarget) { 876 // Pattern match INS. 877 // $dst = or (and $src1 , mask0), (and (shl $src, pos), mask1), 878 // where mask1 = (2**size - 1) << pos, mask0 = ~mask1 879 // => ins $dst, $src, size, pos, $src1 880 if (DCI.isBeforeLegalizeOps() || !Subtarget.hasExtractInsert()) 881 return SDValue(); 882 883 SDValue And0 = N->getOperand(0), And1 = N->getOperand(1); 884 uint64_t SMPos0, SMSize0, SMPos1, SMSize1; 885 ConstantSDNode *CN, *CN1; 886 887 // See if Op's first operand matches (and $src1 , mask0). 888 if (And0.getOpcode() != ISD::AND) 889 return SDValue(); 890 891 if (!(CN = dyn_cast<ConstantSDNode>(And0.getOperand(1))) || 892 !isShiftedMask(~CN->getSExtValue(), SMPos0, SMSize0)) 893 return SDValue(); 894 895 // See if Op's second operand matches (and (shl $src, pos), mask1). 896 if (And1.getOpcode() == ISD::AND && 897 And1.getOperand(0).getOpcode() == ISD::SHL) { 898 899 if (!(CN = dyn_cast<ConstantSDNode>(And1.getOperand(1))) || 900 !isShiftedMask(CN->getZExtValue(), SMPos1, SMSize1)) 901 return SDValue(); 902 903 // The shift masks must have the same position and size. 904 if (SMPos0 != SMPos1 || SMSize0 != SMSize1) 905 return SDValue(); 906 907 SDValue Shl = And1.getOperand(0); 908 909 if (!(CN = dyn_cast<ConstantSDNode>(Shl.getOperand(1)))) 910 return SDValue(); 911 912 unsigned Shamt = CN->getZExtValue(); 913 914 // Return if the shift amount and the first bit position of mask are not the 915 // same. 916 EVT ValTy = N->getValueType(0); 917 if ((Shamt != SMPos0) || (SMPos0 + SMSize0 > ValTy.getSizeInBits())) 918 return SDValue(); 919 920 SDLoc DL(N); 921 return DAG.getNode(MipsISD::Ins, DL, ValTy, Shl.getOperand(0), 922 DAG.getConstant(SMPos0, DL, MVT::i32), 923 DAG.getConstant(SMSize0, DL, MVT::i32), 924 And0.getOperand(0)); 925 } else { 926 // Pattern match DINS. 927 // $dst = or (and $src, mask0), mask1 928 // where mask0 = ((1 << SMSize0) -1) << SMPos0 929 // => dins $dst, $src, pos, size 930 if (~CN->getSExtValue() == ((((int64_t)1 << SMSize0) - 1) << SMPos0) && 931 ((SMSize0 + SMPos0 <= 64 && Subtarget.hasMips64r2()) || 932 (SMSize0 + SMPos0 <= 32))) { 933 // Check if AND instruction has constant as argument 934 bool isConstCase = And1.getOpcode() != ISD::AND; 935 if (And1.getOpcode() == ISD::AND) { 936 if (!(CN1 = dyn_cast<ConstantSDNode>(And1->getOperand(1)))) 937 return SDValue(); 938 } else { 939 if (!(CN1 = dyn_cast<ConstantSDNode>(N->getOperand(1)))) 940 return SDValue(); 941 } 942 // Don't generate INS if constant OR operand doesn't fit into bits 943 // cleared by constant AND operand. 944 if (CN->getSExtValue() & CN1->getSExtValue()) 945 return SDValue(); 946 947 SDLoc DL(N); 948 EVT ValTy = N->getOperand(0)->getValueType(0); 949 SDValue Const1; 950 SDValue SrlX; 951 if (!isConstCase) { 952 Const1 = DAG.getConstant(SMPos0, DL, MVT::i32); 953 SrlX = DAG.getNode(ISD::SRL, DL, And1->getValueType(0), And1, Const1); 954 } 955 return DAG.getNode( 956 MipsISD::Ins, DL, N->getValueType(0), 957 isConstCase 958 ? DAG.getConstant(CN1->getSExtValue() >> SMPos0, DL, ValTy) 959 : SrlX, 960 DAG.getConstant(SMPos0, DL, MVT::i32), 961 DAG.getConstant(ValTy.getSizeInBits() / 8 < 8 ? SMSize0 & 31 962 : SMSize0, 963 DL, MVT::i32), 964 And0->getOperand(0)); 965 966 } 967 return SDValue(); 968 } 969 } 970 971 static SDValue performMADD_MSUBCombine(SDNode *ROOTNode, SelectionDAG &CurDAG, 972 const MipsSubtarget &Subtarget) { 973 // ROOTNode must have a multiplication as an operand for the match to be 974 // successful. 975 if (ROOTNode->getOperand(0).getOpcode() != ISD::MUL && 976 ROOTNode->getOperand(1).getOpcode() != ISD::MUL) 977 return SDValue(); 978 979 // We don't handle vector types here. 980 if (ROOTNode->getValueType(0).isVector()) 981 return SDValue(); 982 983 // For MIPS64, madd / msub instructions are inefficent to use with 64 bit 984 // arithmetic. E.g. 985 // (add (mul a b) c) => 986 // let res = (madd (mthi (drotr c 32))x(mtlo c) a b) in 987 // MIPS64: (or (dsll (mfhi res) 32) (dsrl (dsll (mflo res) 32) 32) 988 // or 989 // MIPS64R2: (dins (mflo res) (mfhi res) 32 32) 990 // 991 // The overhead of setting up the Hi/Lo registers and reassembling the 992 // result makes this a dubious optimzation for MIPS64. The core of the 993 // problem is that Hi/Lo contain the upper and lower 32 bits of the 994 // operand and result. 995 // 996 // It requires a chain of 4 add/mul for MIPS64R2 to get better code 997 // density than doing it naively, 5 for MIPS64. Additionally, using 998 // madd/msub on MIPS64 requires the operands actually be 32 bit sign 999 // extended operands, not true 64 bit values. 1000 // 1001 // FIXME: For the moment, disable this completely for MIPS64. 1002 if (Subtarget.hasMips64()) 1003 return SDValue(); 1004 1005 SDValue Mult = ROOTNode->getOperand(0).getOpcode() == ISD::MUL 1006 ? ROOTNode->getOperand(0) 1007 : ROOTNode->getOperand(1); 1008 1009 SDValue AddOperand = ROOTNode->getOperand(0).getOpcode() == ISD::MUL 1010 ? ROOTNode->getOperand(1) 1011 : ROOTNode->getOperand(0); 1012 1013 // Transform this to a MADD only if the user of this node is the add. 1014 // If there are other users of the mul, this function returns here. 1015 if (!Mult.hasOneUse()) 1016 return SDValue(); 1017 1018 // maddu and madd are unusual instructions in that on MIPS64 bits 63..31 1019 // must be in canonical form, i.e. sign extended. For MIPS32, the operands 1020 // of the multiply must have 32 or more sign bits, otherwise we cannot 1021 // perform this optimization. We have to check this here as we're performing 1022 // this optimization pre-legalization. 1023 SDValue MultLHS = Mult->getOperand(0); 1024 SDValue MultRHS = Mult->getOperand(1); 1025 1026 bool IsSigned = MultLHS->getOpcode() == ISD::SIGN_EXTEND && 1027 MultRHS->getOpcode() == ISD::SIGN_EXTEND; 1028 bool IsUnsigned = MultLHS->getOpcode() == ISD::ZERO_EXTEND && 1029 MultRHS->getOpcode() == ISD::ZERO_EXTEND; 1030 1031 if (!IsSigned && !IsUnsigned) 1032 return SDValue(); 1033 1034 // Initialize accumulator. 1035 SDLoc DL(ROOTNode); 1036 SDValue TopHalf; 1037 SDValue BottomHalf; 1038 BottomHalf = CurDAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32, AddOperand, 1039 CurDAG.getIntPtrConstant(0, DL)); 1040 1041 TopHalf = CurDAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32, AddOperand, 1042 CurDAG.getIntPtrConstant(1, DL)); 1043 SDValue ACCIn = CurDAG.getNode(MipsISD::MTLOHI, DL, MVT::Untyped, 1044 BottomHalf, 1045 TopHalf); 1046 1047 // Create MipsMAdd(u) / MipsMSub(u) node. 1048 bool IsAdd = ROOTNode->getOpcode() == ISD::ADD; 1049 unsigned Opcode = IsAdd ? (IsUnsigned ? MipsISD::MAddu : MipsISD::MAdd) 1050 : (IsUnsigned ? MipsISD::MSubu : MipsISD::MSub); 1051 SDValue MAddOps[3] = { 1052 CurDAG.getNode(ISD::TRUNCATE, DL, MVT::i32, Mult->getOperand(0)), 1053 CurDAG.getNode(ISD::TRUNCATE, DL, MVT::i32, Mult->getOperand(1)), ACCIn}; 1054 EVT VTs[2] = {MVT::i32, MVT::i32}; 1055 SDValue MAdd = CurDAG.getNode(Opcode, DL, VTs, MAddOps); 1056 1057 SDValue ResLo = CurDAG.getNode(MipsISD::MFLO, DL, MVT::i32, MAdd); 1058 SDValue ResHi = CurDAG.getNode(MipsISD::MFHI, DL, MVT::i32, MAdd); 1059 SDValue Combined = 1060 CurDAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, ResLo, ResHi); 1061 return Combined; 1062 } 1063 1064 static SDValue performSUBCombine(SDNode *N, SelectionDAG &DAG, 1065 TargetLowering::DAGCombinerInfo &DCI, 1066 const MipsSubtarget &Subtarget) { 1067 // (sub v0 (mul v1, v2)) => (msub v1, v2, v0) 1068 if (DCI.isBeforeLegalizeOps()) { 1069 if (Subtarget.hasMips32() && !Subtarget.hasMips32r6() && 1070 !Subtarget.inMips16Mode() && N->getValueType(0) == MVT::i64) 1071 return performMADD_MSUBCombine(N, DAG, Subtarget); 1072 1073 return SDValue(); 1074 } 1075 1076 return SDValue(); 1077 } 1078 1079 static SDValue performADDCombine(SDNode *N, SelectionDAG &DAG, 1080 TargetLowering::DAGCombinerInfo &DCI, 1081 const MipsSubtarget &Subtarget) { 1082 // (add v0 (mul v1, v2)) => (madd v1, v2, v0) 1083 if (DCI.isBeforeLegalizeOps()) { 1084 if (Subtarget.hasMips32() && !Subtarget.hasMips32r6() && 1085 !Subtarget.inMips16Mode() && N->getValueType(0) == MVT::i64) 1086 return performMADD_MSUBCombine(N, DAG, Subtarget); 1087 1088 return SDValue(); 1089 } 1090 1091 // (add v0, (add v1, abs_lo(tjt))) => (add (add v0, v1), abs_lo(tjt)) 1092 SDValue Add = N->getOperand(1); 1093 1094 if (Add.getOpcode() != ISD::ADD) 1095 return SDValue(); 1096 1097 SDValue Lo = Add.getOperand(1); 1098 1099 if ((Lo.getOpcode() != MipsISD::Lo) || 1100 (Lo.getOperand(0).getOpcode() != ISD::TargetJumpTable)) 1101 return SDValue(); 1102 1103 EVT ValTy = N->getValueType(0); 1104 SDLoc DL(N); 1105 1106 SDValue Add1 = DAG.getNode(ISD::ADD, DL, ValTy, N->getOperand(0), 1107 Add.getOperand(0)); 1108 return DAG.getNode(ISD::ADD, DL, ValTy, Add1, Lo); 1109 } 1110 1111 static SDValue performSHLCombine(SDNode *N, SelectionDAG &DAG, 1112 TargetLowering::DAGCombinerInfo &DCI, 1113 const MipsSubtarget &Subtarget) { 1114 // Pattern match CINS. 1115 // $dst = shl (and $src , imm), pos 1116 // => cins $dst, $src, pos, size 1117 1118 if (DCI.isBeforeLegalizeOps() || !Subtarget.hasCnMips()) 1119 return SDValue(); 1120 1121 SDValue FirstOperand = N->getOperand(0); 1122 unsigned FirstOperandOpc = FirstOperand.getOpcode(); 1123 SDValue SecondOperand = N->getOperand(1); 1124 EVT ValTy = N->getValueType(0); 1125 SDLoc DL(N); 1126 1127 uint64_t Pos = 0, SMPos, SMSize; 1128 ConstantSDNode *CN; 1129 SDValue NewOperand; 1130 1131 // The second operand of the shift must be an immediate. 1132 if (!(CN = dyn_cast<ConstantSDNode>(SecondOperand))) 1133 return SDValue(); 1134 1135 Pos = CN->getZExtValue(); 1136 1137 if (Pos >= ValTy.getSizeInBits()) 1138 return SDValue(); 1139 1140 if (FirstOperandOpc != ISD::AND) 1141 return SDValue(); 1142 1143 // AND's second operand must be a shifted mask. 1144 if (!(CN = dyn_cast<ConstantSDNode>(FirstOperand.getOperand(1))) || 1145 !isShiftedMask(CN->getZExtValue(), SMPos, SMSize)) 1146 return SDValue(); 1147 1148 // Return if the shifted mask does not start at bit 0 or the sum of its size 1149 // and Pos exceeds the word's size. 1150 if (SMPos != 0 || SMSize > 32 || Pos + SMSize > ValTy.getSizeInBits()) 1151 return SDValue(); 1152 1153 NewOperand = FirstOperand.getOperand(0); 1154 // SMSize is 'location' (position) in this case, not size. 1155 SMSize--; 1156 1157 return DAG.getNode(MipsISD::CIns, DL, ValTy, NewOperand, 1158 DAG.getConstant(Pos, DL, MVT::i32), 1159 DAG.getConstant(SMSize, DL, MVT::i32)); 1160 } 1161 1162 SDValue MipsTargetLowering::PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) 1163 const { 1164 SelectionDAG &DAG = DCI.DAG; 1165 unsigned Opc = N->getOpcode(); 1166 1167 switch (Opc) { 1168 default: break; 1169 case ISD::SDIVREM: 1170 case ISD::UDIVREM: 1171 return performDivRemCombine(N, DAG, DCI, Subtarget); 1172 case ISD::SELECT: 1173 return performSELECTCombine(N, DAG, DCI, Subtarget); 1174 case MipsISD::CMovFP_F: 1175 case MipsISD::CMovFP_T: 1176 return performCMovFPCombine(N, DAG, DCI, Subtarget); 1177 case ISD::AND: 1178 return performANDCombine(N, DAG, DCI, Subtarget); 1179 case ISD::OR: 1180 return performORCombine(N, DAG, DCI, Subtarget); 1181 case ISD::ADD: 1182 return performADDCombine(N, DAG, DCI, Subtarget); 1183 case ISD::SHL: 1184 return performSHLCombine(N, DAG, DCI, Subtarget); 1185 case ISD::SUB: 1186 return performSUBCombine(N, DAG, DCI, Subtarget); 1187 } 1188 1189 return SDValue(); 1190 } 1191 1192 bool MipsTargetLowering::isCheapToSpeculateCttz() const { 1193 return Subtarget.hasMips32(); 1194 } 1195 1196 bool MipsTargetLowering::isCheapToSpeculateCtlz() const { 1197 return Subtarget.hasMips32(); 1198 } 1199 1200 void 1201 MipsTargetLowering::LowerOperationWrapper(SDNode *N, 1202 SmallVectorImpl<SDValue> &Results, 1203 SelectionDAG &DAG) const { 1204 SDValue Res = LowerOperation(SDValue(N, 0), DAG); 1205 1206 for (unsigned I = 0, E = Res->getNumValues(); I != E; ++I) 1207 Results.push_back(Res.getValue(I)); 1208 } 1209 1210 void 1211 MipsTargetLowering::ReplaceNodeResults(SDNode *N, 1212 SmallVectorImpl<SDValue> &Results, 1213 SelectionDAG &DAG) const { 1214 return LowerOperationWrapper(N, Results, DAG); 1215 } 1216 1217 SDValue MipsTargetLowering:: 1218 LowerOperation(SDValue Op, SelectionDAG &DAG) const 1219 { 1220 switch (Op.getOpcode()) 1221 { 1222 case ISD::BRCOND: return lowerBRCOND(Op, DAG); 1223 case ISD::ConstantPool: return lowerConstantPool(Op, DAG); 1224 case ISD::GlobalAddress: return lowerGlobalAddress(Op, DAG); 1225 case ISD::BlockAddress: return lowerBlockAddress(Op, DAG); 1226 case ISD::GlobalTLSAddress: return lowerGlobalTLSAddress(Op, DAG); 1227 case ISD::JumpTable: return lowerJumpTable(Op, DAG); 1228 case ISD::SELECT: return lowerSELECT(Op, DAG); 1229 case ISD::SETCC: return lowerSETCC(Op, DAG); 1230 case ISD::VASTART: return lowerVASTART(Op, DAG); 1231 case ISD::VAARG: return lowerVAARG(Op, DAG); 1232 case ISD::FCOPYSIGN: return lowerFCOPYSIGN(Op, DAG); 1233 case ISD::FRAMEADDR: return lowerFRAMEADDR(Op, DAG); 1234 case ISD::RETURNADDR: return lowerRETURNADDR(Op, DAG); 1235 case ISD::EH_RETURN: return lowerEH_RETURN(Op, DAG); 1236 case ISD::ATOMIC_FENCE: return lowerATOMIC_FENCE(Op, DAG); 1237 case ISD::SHL_PARTS: return lowerShiftLeftParts(Op, DAG); 1238 case ISD::SRA_PARTS: return lowerShiftRightParts(Op, DAG, true); 1239 case ISD::SRL_PARTS: return lowerShiftRightParts(Op, DAG, false); 1240 case ISD::LOAD: return lowerLOAD(Op, DAG); 1241 case ISD::STORE: return lowerSTORE(Op, DAG); 1242 case ISD::EH_DWARF_CFA: return lowerEH_DWARF_CFA(Op, DAG); 1243 case ISD::FP_TO_SINT: return lowerFP_TO_SINT(Op, DAG); 1244 } 1245 return SDValue(); 1246 } 1247 1248 //===----------------------------------------------------------------------===// 1249 // Lower helper functions 1250 //===----------------------------------------------------------------------===// 1251 1252 // addLiveIn - This helper function adds the specified physical register to the 1253 // MachineFunction as a live in value. It also creates a corresponding 1254 // virtual register for it. 1255 static unsigned 1256 addLiveIn(MachineFunction &MF, unsigned PReg, const TargetRegisterClass *RC) 1257 { 1258 unsigned VReg = MF.getRegInfo().createVirtualRegister(RC); 1259 MF.getRegInfo().addLiveIn(PReg, VReg); 1260 return VReg; 1261 } 1262 1263 static MachineBasicBlock *insertDivByZeroTrap(MachineInstr &MI, 1264 MachineBasicBlock &MBB, 1265 const TargetInstrInfo &TII, 1266 bool Is64Bit, bool IsMicroMips) { 1267 if (NoZeroDivCheck) 1268 return &MBB; 1269 1270 // Insert instruction "teq $divisor_reg, $zero, 7". 1271 MachineBasicBlock::iterator I(MI); 1272 MachineInstrBuilder MIB; 1273 MachineOperand &Divisor = MI.getOperand(2); 1274 MIB = BuildMI(MBB, std::next(I), MI.getDebugLoc(), 1275 TII.get(IsMicroMips ? Mips::TEQ_MM : Mips::TEQ)) 1276 .addReg(Divisor.getReg(), getKillRegState(Divisor.isKill())) 1277 .addReg(Mips::ZERO) 1278 .addImm(7); 1279 1280 // Use the 32-bit sub-register if this is a 64-bit division. 1281 if (Is64Bit) 1282 MIB->getOperand(0).setSubReg(Mips::sub_32); 1283 1284 // Clear Divisor's kill flag. 1285 Divisor.setIsKill(false); 1286 1287 // We would normally delete the original instruction here but in this case 1288 // we only needed to inject an additional instruction rather than replace it. 1289 1290 return &MBB; 1291 } 1292 1293 MachineBasicBlock * 1294 MipsTargetLowering::EmitInstrWithCustomInserter(MachineInstr &MI, 1295 MachineBasicBlock *BB) const { 1296 switch (MI.getOpcode()) { 1297 default: 1298 llvm_unreachable("Unexpected instr type to insert"); 1299 case Mips::ATOMIC_LOAD_ADD_I8: 1300 return emitAtomicBinaryPartword(MI, BB, 1, Mips::ADDu); 1301 case Mips::ATOMIC_LOAD_ADD_I16: 1302 return emitAtomicBinaryPartword(MI, BB, 2, Mips::ADDu); 1303 case Mips::ATOMIC_LOAD_ADD_I32: 1304 return emitAtomicBinary(MI, BB, 4, Mips::ADDu); 1305 case Mips::ATOMIC_LOAD_ADD_I64: 1306 return emitAtomicBinary(MI, BB, 8, Mips::DADDu); 1307 1308 case Mips::ATOMIC_LOAD_AND_I8: 1309 return emitAtomicBinaryPartword(MI, BB, 1, Mips::AND); 1310 case Mips::ATOMIC_LOAD_AND_I16: 1311 return emitAtomicBinaryPartword(MI, BB, 2, Mips::AND); 1312 case Mips::ATOMIC_LOAD_AND_I32: 1313 return emitAtomicBinary(MI, BB, 4, Mips::AND); 1314 case Mips::ATOMIC_LOAD_AND_I64: 1315 return emitAtomicBinary(MI, BB, 8, Mips::AND64); 1316 1317 case Mips::ATOMIC_LOAD_OR_I8: 1318 return emitAtomicBinaryPartword(MI, BB, 1, Mips::OR); 1319 case Mips::ATOMIC_LOAD_OR_I16: 1320 return emitAtomicBinaryPartword(MI, BB, 2, Mips::OR); 1321 case Mips::ATOMIC_LOAD_OR_I32: 1322 return emitAtomicBinary(MI, BB, 4, Mips::OR); 1323 case Mips::ATOMIC_LOAD_OR_I64: 1324 return emitAtomicBinary(MI, BB, 8, Mips::OR64); 1325 1326 case Mips::ATOMIC_LOAD_XOR_I8: 1327 return emitAtomicBinaryPartword(MI, BB, 1, Mips::XOR); 1328 case Mips::ATOMIC_LOAD_XOR_I16: 1329 return emitAtomicBinaryPartword(MI, BB, 2, Mips::XOR); 1330 case Mips::ATOMIC_LOAD_XOR_I32: 1331 return emitAtomicBinary(MI, BB, 4, Mips::XOR); 1332 case Mips::ATOMIC_LOAD_XOR_I64: 1333 return emitAtomicBinary(MI, BB, 8, Mips::XOR64); 1334 1335 case Mips::ATOMIC_LOAD_NAND_I8: 1336 return emitAtomicBinaryPartword(MI, BB, 1, 0, true); 1337 case Mips::ATOMIC_LOAD_NAND_I16: 1338 return emitAtomicBinaryPartword(MI, BB, 2, 0, true); 1339 case Mips::ATOMIC_LOAD_NAND_I32: 1340 return emitAtomicBinary(MI, BB, 4, 0, true); 1341 case Mips::ATOMIC_LOAD_NAND_I64: 1342 return emitAtomicBinary(MI, BB, 8, 0, true); 1343 1344 case Mips::ATOMIC_LOAD_SUB_I8: 1345 return emitAtomicBinaryPartword(MI, BB, 1, Mips::SUBu); 1346 case Mips::ATOMIC_LOAD_SUB_I16: 1347 return emitAtomicBinaryPartword(MI, BB, 2, Mips::SUBu); 1348 case Mips::ATOMIC_LOAD_SUB_I32: 1349 return emitAtomicBinary(MI, BB, 4, Mips::SUBu); 1350 case Mips::ATOMIC_LOAD_SUB_I64: 1351 return emitAtomicBinary(MI, BB, 8, Mips::DSUBu); 1352 1353 case Mips::ATOMIC_SWAP_I8: 1354 return emitAtomicBinaryPartword(MI, BB, 1, 0); 1355 case Mips::ATOMIC_SWAP_I16: 1356 return emitAtomicBinaryPartword(MI, BB, 2, 0); 1357 case Mips::ATOMIC_SWAP_I32: 1358 return emitAtomicBinary(MI, BB, 4, 0); 1359 case Mips::ATOMIC_SWAP_I64: 1360 return emitAtomicBinary(MI, BB, 8, 0); 1361 1362 case Mips::ATOMIC_CMP_SWAP_I8: 1363 return emitAtomicCmpSwapPartword(MI, BB, 1); 1364 case Mips::ATOMIC_CMP_SWAP_I16: 1365 return emitAtomicCmpSwapPartword(MI, BB, 2); 1366 case Mips::ATOMIC_CMP_SWAP_I32: 1367 return emitAtomicCmpSwap(MI, BB, 4); 1368 case Mips::ATOMIC_CMP_SWAP_I64: 1369 return emitAtomicCmpSwap(MI, BB, 8); 1370 case Mips::PseudoSDIV: 1371 case Mips::PseudoUDIV: 1372 case Mips::DIV: 1373 case Mips::DIVU: 1374 case Mips::MOD: 1375 case Mips::MODU: 1376 return insertDivByZeroTrap(MI, *BB, *Subtarget.getInstrInfo(), false, 1377 false); 1378 case Mips::SDIV_MM_Pseudo: 1379 case Mips::UDIV_MM_Pseudo: 1380 case Mips::SDIV_MM: 1381 case Mips::UDIV_MM: 1382 case Mips::DIV_MMR6: 1383 case Mips::DIVU_MMR6: 1384 case Mips::MOD_MMR6: 1385 case Mips::MODU_MMR6: 1386 return insertDivByZeroTrap(MI, *BB, *Subtarget.getInstrInfo(), false, true); 1387 case Mips::PseudoDSDIV: 1388 case Mips::PseudoDUDIV: 1389 case Mips::DDIV: 1390 case Mips::DDIVU: 1391 case Mips::DMOD: 1392 case Mips::DMODU: 1393 return insertDivByZeroTrap(MI, *BB, *Subtarget.getInstrInfo(), true, false); 1394 1395 case Mips::PseudoSELECT_I: 1396 case Mips::PseudoSELECT_I64: 1397 case Mips::PseudoSELECT_S: 1398 case Mips::PseudoSELECT_D32: 1399 case Mips::PseudoSELECT_D64: 1400 return emitPseudoSELECT(MI, BB, false, Mips::BNE); 1401 case Mips::PseudoSELECTFP_F_I: 1402 case Mips::PseudoSELECTFP_F_I64: 1403 case Mips::PseudoSELECTFP_F_S: 1404 case Mips::PseudoSELECTFP_F_D32: 1405 case Mips::PseudoSELECTFP_F_D64: 1406 return emitPseudoSELECT(MI, BB, true, Mips::BC1F); 1407 case Mips::PseudoSELECTFP_T_I: 1408 case Mips::PseudoSELECTFP_T_I64: 1409 case Mips::PseudoSELECTFP_T_S: 1410 case Mips::PseudoSELECTFP_T_D32: 1411 case Mips::PseudoSELECTFP_T_D64: 1412 return emitPseudoSELECT(MI, BB, true, Mips::BC1T); 1413 } 1414 } 1415 1416 // This function also handles Mips::ATOMIC_SWAP_I32 (when BinOpcode == 0), and 1417 // Mips::ATOMIC_LOAD_NAND_I32 (when Nand == true) 1418 MachineBasicBlock *MipsTargetLowering::emitAtomicBinary(MachineInstr &MI, 1419 MachineBasicBlock *BB, 1420 unsigned Size, 1421 unsigned BinOpcode, 1422 bool Nand) const { 1423 assert((Size == 4 || Size == 8) && "Unsupported size for EmitAtomicBinary."); 1424 1425 MachineFunction *MF = BB->getParent(); 1426 MachineRegisterInfo &RegInfo = MF->getRegInfo(); 1427 const TargetRegisterClass *RC = getRegClassFor(MVT::getIntegerVT(Size * 8)); 1428 const TargetInstrInfo *TII = Subtarget.getInstrInfo(); 1429 const bool ArePtrs64bit = ABI.ArePtrs64bit(); 1430 DebugLoc DL = MI.getDebugLoc(); 1431 unsigned LL, SC, AND, NOR, ZERO, BEQ; 1432 1433 if (Size == 4) { 1434 if (isMicroMips) { 1435 LL = Mips::LL_MM; 1436 SC = Mips::SC_MM; 1437 } else { 1438 LL = Subtarget.hasMips32r6() 1439 ? (ArePtrs64bit ? Mips::LL64_R6 : Mips::LL_R6) 1440 : (ArePtrs64bit ? Mips::LL64 : Mips::LL); 1441 SC = Subtarget.hasMips32r6() 1442 ? (ArePtrs64bit ? Mips::SC64_R6 : Mips::SC_R6) 1443 : (ArePtrs64bit ? Mips::SC64 : Mips::SC); 1444 } 1445 1446 AND = Mips::AND; 1447 NOR = Mips::NOR; 1448 ZERO = Mips::ZERO; 1449 BEQ = Mips::BEQ; 1450 } else { 1451 LL = Subtarget.hasMips64r6() ? Mips::LLD_R6 : Mips::LLD; 1452 SC = Subtarget.hasMips64r6() ? Mips::SCD_R6 : Mips::SCD; 1453 AND = Mips::AND64; 1454 NOR = Mips::NOR64; 1455 ZERO = Mips::ZERO_64; 1456 BEQ = Mips::BEQ64; 1457 } 1458 1459 unsigned OldVal = MI.getOperand(0).getReg(); 1460 unsigned Ptr = MI.getOperand(1).getReg(); 1461 unsigned Incr = MI.getOperand(2).getReg(); 1462 1463 unsigned StoreVal = RegInfo.createVirtualRegister(RC); 1464 unsigned AndRes = RegInfo.createVirtualRegister(RC); 1465 unsigned Success = RegInfo.createVirtualRegister(RC); 1466 1467 // insert new blocks after the current block 1468 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 1469 MachineBasicBlock *loopMBB = MF->CreateMachineBasicBlock(LLVM_BB); 1470 MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB); 1471 MachineFunction::iterator It = ++BB->getIterator(); 1472 MF->insert(It, loopMBB); 1473 MF->insert(It, exitMBB); 1474 1475 // Transfer the remainder of BB and its successor edges to exitMBB. 1476 exitMBB->splice(exitMBB->begin(), BB, 1477 std::next(MachineBasicBlock::iterator(MI)), BB->end()); 1478 exitMBB->transferSuccessorsAndUpdatePHIs(BB); 1479 1480 // thisMBB: 1481 // ... 1482 // fallthrough --> loopMBB 1483 BB->addSuccessor(loopMBB); 1484 loopMBB->addSuccessor(loopMBB); 1485 loopMBB->addSuccessor(exitMBB); 1486 1487 // loopMBB: 1488 // ll oldval, 0(ptr) 1489 // <binop> storeval, oldval, incr 1490 // sc success, storeval, 0(ptr) 1491 // beq success, $0, loopMBB 1492 BB = loopMBB; 1493 BuildMI(BB, DL, TII->get(LL), OldVal).addReg(Ptr).addImm(0); 1494 if (Nand) { 1495 // and andres, oldval, incr 1496 // nor storeval, $0, andres 1497 BuildMI(BB, DL, TII->get(AND), AndRes).addReg(OldVal).addReg(Incr); 1498 BuildMI(BB, DL, TII->get(NOR), StoreVal).addReg(ZERO).addReg(AndRes); 1499 } else if (BinOpcode) { 1500 // <binop> storeval, oldval, incr 1501 BuildMI(BB, DL, TII->get(BinOpcode), StoreVal).addReg(OldVal).addReg(Incr); 1502 } else { 1503 StoreVal = Incr; 1504 } 1505 BuildMI(BB, DL, TII->get(SC), Success).addReg(StoreVal).addReg(Ptr).addImm(0); 1506 BuildMI(BB, DL, TII->get(BEQ)).addReg(Success).addReg(ZERO).addMBB(loopMBB); 1507 1508 MI.eraseFromParent(); // The instruction is gone now. 1509 1510 return exitMBB; 1511 } 1512 1513 MachineBasicBlock *MipsTargetLowering::emitSignExtendToI32InReg( 1514 MachineInstr &MI, MachineBasicBlock *BB, unsigned Size, unsigned DstReg, 1515 unsigned SrcReg) const { 1516 const TargetInstrInfo *TII = Subtarget.getInstrInfo(); 1517 const DebugLoc &DL = MI.getDebugLoc(); 1518 1519 if (Subtarget.hasMips32r2() && Size == 1) { 1520 BuildMI(BB, DL, TII->get(Mips::SEB), DstReg).addReg(SrcReg); 1521 return BB; 1522 } 1523 1524 if (Subtarget.hasMips32r2() && Size == 2) { 1525 BuildMI(BB, DL, TII->get(Mips::SEH), DstReg).addReg(SrcReg); 1526 return BB; 1527 } 1528 1529 MachineFunction *MF = BB->getParent(); 1530 MachineRegisterInfo &RegInfo = MF->getRegInfo(); 1531 const TargetRegisterClass *RC = getRegClassFor(MVT::i32); 1532 unsigned ScrReg = RegInfo.createVirtualRegister(RC); 1533 1534 assert(Size < 32); 1535 int64_t ShiftImm = 32 - (Size * 8); 1536 1537 BuildMI(BB, DL, TII->get(Mips::SLL), ScrReg).addReg(SrcReg).addImm(ShiftImm); 1538 BuildMI(BB, DL, TII->get(Mips::SRA), DstReg).addReg(ScrReg).addImm(ShiftImm); 1539 1540 return BB; 1541 } 1542 1543 MachineBasicBlock *MipsTargetLowering::emitAtomicBinaryPartword( 1544 MachineInstr &MI, MachineBasicBlock *BB, unsigned Size, unsigned BinOpcode, 1545 bool Nand) const { 1546 assert((Size == 1 || Size == 2) && 1547 "Unsupported size for EmitAtomicBinaryPartial."); 1548 1549 MachineFunction *MF = BB->getParent(); 1550 MachineRegisterInfo &RegInfo = MF->getRegInfo(); 1551 const TargetRegisterClass *RC = getRegClassFor(MVT::i32); 1552 const bool ArePtrs64bit = ABI.ArePtrs64bit(); 1553 const TargetRegisterClass *RCp = 1554 getRegClassFor(ArePtrs64bit ? MVT::i64 : MVT::i32); 1555 const TargetInstrInfo *TII = Subtarget.getInstrInfo(); 1556 DebugLoc DL = MI.getDebugLoc(); 1557 1558 unsigned Dest = MI.getOperand(0).getReg(); 1559 unsigned Ptr = MI.getOperand(1).getReg(); 1560 unsigned Incr = MI.getOperand(2).getReg(); 1561 1562 unsigned AlignedAddr = RegInfo.createVirtualRegister(RCp); 1563 unsigned ShiftAmt = RegInfo.createVirtualRegister(RC); 1564 unsigned Mask = RegInfo.createVirtualRegister(RC); 1565 unsigned Mask2 = RegInfo.createVirtualRegister(RC); 1566 unsigned NewVal = RegInfo.createVirtualRegister(RC); 1567 unsigned OldVal = RegInfo.createVirtualRegister(RC); 1568 unsigned Incr2 = RegInfo.createVirtualRegister(RC); 1569 unsigned MaskLSB2 = RegInfo.createVirtualRegister(RCp); 1570 unsigned PtrLSB2 = RegInfo.createVirtualRegister(RC); 1571 unsigned MaskUpper = RegInfo.createVirtualRegister(RC); 1572 unsigned AndRes = RegInfo.createVirtualRegister(RC); 1573 unsigned BinOpRes = RegInfo.createVirtualRegister(RC); 1574 unsigned MaskedOldVal0 = RegInfo.createVirtualRegister(RC); 1575 unsigned StoreVal = RegInfo.createVirtualRegister(RC); 1576 unsigned MaskedOldVal1 = RegInfo.createVirtualRegister(RC); 1577 unsigned SrlRes = RegInfo.createVirtualRegister(RC); 1578 unsigned Success = RegInfo.createVirtualRegister(RC); 1579 1580 unsigned LL, SC; 1581 if (isMicroMips) { 1582 LL = Mips::LL_MM; 1583 SC = Mips::SC_MM; 1584 } else { 1585 LL = Subtarget.hasMips32r6() ? (ArePtrs64bit ? Mips::LL64_R6 : Mips::LL_R6) 1586 : (ArePtrs64bit ? Mips::LL64 : Mips::LL); 1587 SC = Subtarget.hasMips32r6() ? (ArePtrs64bit ? Mips::SC64_R6 : Mips::SC_R6) 1588 : (ArePtrs64bit ? Mips::SC64 : Mips::SC); 1589 } 1590 1591 // insert new blocks after the current block 1592 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 1593 MachineBasicBlock *loopMBB = MF->CreateMachineBasicBlock(LLVM_BB); 1594 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(LLVM_BB); 1595 MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB); 1596 MachineFunction::iterator It = ++BB->getIterator(); 1597 MF->insert(It, loopMBB); 1598 MF->insert(It, sinkMBB); 1599 MF->insert(It, exitMBB); 1600 1601 // Transfer the remainder of BB and its successor edges to exitMBB. 1602 exitMBB->splice(exitMBB->begin(), BB, 1603 std::next(MachineBasicBlock::iterator(MI)), BB->end()); 1604 exitMBB->transferSuccessorsAndUpdatePHIs(BB); 1605 1606 BB->addSuccessor(loopMBB); 1607 loopMBB->addSuccessor(loopMBB); 1608 loopMBB->addSuccessor(sinkMBB); 1609 sinkMBB->addSuccessor(exitMBB); 1610 1611 // thisMBB: 1612 // addiu masklsb2,$0,-4 # 0xfffffffc 1613 // and alignedaddr,ptr,masklsb2 1614 // andi ptrlsb2,ptr,3 1615 // sll shiftamt,ptrlsb2,3 1616 // ori maskupper,$0,255 # 0xff 1617 // sll mask,maskupper,shiftamt 1618 // nor mask2,$0,mask 1619 // sll incr2,incr,shiftamt 1620 1621 int64_t MaskImm = (Size == 1) ? 255 : 65535; 1622 BuildMI(BB, DL, TII->get(ABI.GetPtrAddiuOp()), MaskLSB2) 1623 .addReg(ABI.GetNullPtr()).addImm(-4); 1624 BuildMI(BB, DL, TII->get(ABI.GetPtrAndOp()), AlignedAddr) 1625 .addReg(Ptr).addReg(MaskLSB2); 1626 BuildMI(BB, DL, TII->get(Mips::ANDi), PtrLSB2) 1627 .addReg(Ptr, 0, ArePtrs64bit ? Mips::sub_32 : 0).addImm(3); 1628 if (Subtarget.isLittle()) { 1629 BuildMI(BB, DL, TII->get(Mips::SLL), ShiftAmt).addReg(PtrLSB2).addImm(3); 1630 } else { 1631 unsigned Off = RegInfo.createVirtualRegister(RC); 1632 BuildMI(BB, DL, TII->get(Mips::XORi), Off) 1633 .addReg(PtrLSB2).addImm((Size == 1) ? 3 : 2); 1634 BuildMI(BB, DL, TII->get(Mips::SLL), ShiftAmt).addReg(Off).addImm(3); 1635 } 1636 BuildMI(BB, DL, TII->get(Mips::ORi), MaskUpper) 1637 .addReg(Mips::ZERO).addImm(MaskImm); 1638 BuildMI(BB, DL, TII->get(Mips::SLLV), Mask) 1639 .addReg(MaskUpper).addReg(ShiftAmt); 1640 BuildMI(BB, DL, TII->get(Mips::NOR), Mask2).addReg(Mips::ZERO).addReg(Mask); 1641 BuildMI(BB, DL, TII->get(Mips::SLLV), Incr2).addReg(Incr).addReg(ShiftAmt); 1642 1643 // atomic.load.binop 1644 // loopMBB: 1645 // ll oldval,0(alignedaddr) 1646 // binop binopres,oldval,incr2 1647 // and newval,binopres,mask 1648 // and maskedoldval0,oldval,mask2 1649 // or storeval,maskedoldval0,newval 1650 // sc success,storeval,0(alignedaddr) 1651 // beq success,$0,loopMBB 1652 1653 // atomic.swap 1654 // loopMBB: 1655 // ll oldval,0(alignedaddr) 1656 // and newval,incr2,mask 1657 // and maskedoldval0,oldval,mask2 1658 // or storeval,maskedoldval0,newval 1659 // sc success,storeval,0(alignedaddr) 1660 // beq success,$0,loopMBB 1661 1662 BB = loopMBB; 1663 BuildMI(BB, DL, TII->get(LL), OldVal).addReg(AlignedAddr).addImm(0); 1664 if (Nand) { 1665 // and andres, oldval, incr2 1666 // nor binopres, $0, andres 1667 // and newval, binopres, mask 1668 BuildMI(BB, DL, TII->get(Mips::AND), AndRes).addReg(OldVal).addReg(Incr2); 1669 BuildMI(BB, DL, TII->get(Mips::NOR), BinOpRes) 1670 .addReg(Mips::ZERO).addReg(AndRes); 1671 BuildMI(BB, DL, TII->get(Mips::AND), NewVal).addReg(BinOpRes).addReg(Mask); 1672 } else if (BinOpcode) { 1673 // <binop> binopres, oldval, incr2 1674 // and newval, binopres, mask 1675 BuildMI(BB, DL, TII->get(BinOpcode), BinOpRes).addReg(OldVal).addReg(Incr2); 1676 BuildMI(BB, DL, TII->get(Mips::AND), NewVal).addReg(BinOpRes).addReg(Mask); 1677 } else { // atomic.swap 1678 // and newval, incr2, mask 1679 BuildMI(BB, DL, TII->get(Mips::AND), NewVal).addReg(Incr2).addReg(Mask); 1680 } 1681 1682 BuildMI(BB, DL, TII->get(Mips::AND), MaskedOldVal0) 1683 .addReg(OldVal).addReg(Mask2); 1684 BuildMI(BB, DL, TII->get(Mips::OR), StoreVal) 1685 .addReg(MaskedOldVal0).addReg(NewVal); 1686 BuildMI(BB, DL, TII->get(SC), Success) 1687 .addReg(StoreVal).addReg(AlignedAddr).addImm(0); 1688 BuildMI(BB, DL, TII->get(Mips::BEQ)) 1689 .addReg(Success).addReg(Mips::ZERO).addMBB(loopMBB); 1690 1691 // sinkMBB: 1692 // and maskedoldval1,oldval,mask 1693 // srl srlres,maskedoldval1,shiftamt 1694 // sign_extend dest,srlres 1695 BB = sinkMBB; 1696 1697 BuildMI(BB, DL, TII->get(Mips::AND), MaskedOldVal1) 1698 .addReg(OldVal).addReg(Mask); 1699 BuildMI(BB, DL, TII->get(Mips::SRLV), SrlRes) 1700 .addReg(MaskedOldVal1).addReg(ShiftAmt); 1701 BB = emitSignExtendToI32InReg(MI, BB, Size, Dest, SrlRes); 1702 1703 MI.eraseFromParent(); // The instruction is gone now. 1704 1705 return exitMBB; 1706 } 1707 1708 MachineBasicBlock *MipsTargetLowering::emitAtomicCmpSwap(MachineInstr &MI, 1709 MachineBasicBlock *BB, 1710 unsigned Size) const { 1711 assert((Size == 4 || Size == 8) && "Unsupported size for EmitAtomicCmpSwap."); 1712 1713 MachineFunction *MF = BB->getParent(); 1714 MachineRegisterInfo &RegInfo = MF->getRegInfo(); 1715 const TargetRegisterClass *RC = getRegClassFor(MVT::getIntegerVT(Size * 8)); 1716 const TargetInstrInfo *TII = Subtarget.getInstrInfo(); 1717 const bool ArePtrs64bit = ABI.ArePtrs64bit(); 1718 DebugLoc DL = MI.getDebugLoc(); 1719 unsigned LL, SC, ZERO, BNE, BEQ; 1720 1721 if (Size == 4) { 1722 if (isMicroMips) { 1723 LL = Mips::LL_MM; 1724 SC = Mips::SC_MM; 1725 } else { 1726 LL = Subtarget.hasMips32r6() 1727 ? (ArePtrs64bit ? Mips::LL64_R6 : Mips::LL_R6) 1728 : (ArePtrs64bit ? Mips::LL64 : Mips::LL); 1729 SC = Subtarget.hasMips32r6() 1730 ? (ArePtrs64bit ? Mips::SC64_R6 : Mips::SC_R6) 1731 : (ArePtrs64bit ? Mips::SC64 : Mips::SC); 1732 } 1733 1734 ZERO = Mips::ZERO; 1735 BNE = Mips::BNE; 1736 BEQ = Mips::BEQ; 1737 } else { 1738 LL = Subtarget.hasMips64r6() ? Mips::LLD_R6 : Mips::LLD; 1739 SC = Subtarget.hasMips64r6() ? Mips::SCD_R6 : Mips::SCD; 1740 ZERO = Mips::ZERO_64; 1741 BNE = Mips::BNE64; 1742 BEQ = Mips::BEQ64; 1743 } 1744 1745 unsigned Dest = MI.getOperand(0).getReg(); 1746 unsigned Ptr = MI.getOperand(1).getReg(); 1747 unsigned OldVal = MI.getOperand(2).getReg(); 1748 unsigned NewVal = MI.getOperand(3).getReg(); 1749 1750 unsigned Success = RegInfo.createVirtualRegister(RC); 1751 1752 // insert new blocks after the current block 1753 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 1754 MachineBasicBlock *loop1MBB = MF->CreateMachineBasicBlock(LLVM_BB); 1755 MachineBasicBlock *loop2MBB = MF->CreateMachineBasicBlock(LLVM_BB); 1756 MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB); 1757 MachineFunction::iterator It = ++BB->getIterator(); 1758 MF->insert(It, loop1MBB); 1759 MF->insert(It, loop2MBB); 1760 MF->insert(It, exitMBB); 1761 1762 // Transfer the remainder of BB and its successor edges to exitMBB. 1763 exitMBB->splice(exitMBB->begin(), BB, 1764 std::next(MachineBasicBlock::iterator(MI)), BB->end()); 1765 exitMBB->transferSuccessorsAndUpdatePHIs(BB); 1766 1767 // thisMBB: 1768 // ... 1769 // fallthrough --> loop1MBB 1770 BB->addSuccessor(loop1MBB); 1771 loop1MBB->addSuccessor(exitMBB); 1772 loop1MBB->addSuccessor(loop2MBB); 1773 loop2MBB->addSuccessor(loop1MBB); 1774 loop2MBB->addSuccessor(exitMBB); 1775 1776 // loop1MBB: 1777 // ll dest, 0(ptr) 1778 // bne dest, oldval, exitMBB 1779 BB = loop1MBB; 1780 BuildMI(BB, DL, TII->get(LL), Dest).addReg(Ptr).addImm(0); 1781 BuildMI(BB, DL, TII->get(BNE)) 1782 .addReg(Dest).addReg(OldVal).addMBB(exitMBB); 1783 1784 // loop2MBB: 1785 // sc success, newval, 0(ptr) 1786 // beq success, $0, loop1MBB 1787 BB = loop2MBB; 1788 BuildMI(BB, DL, TII->get(SC), Success) 1789 .addReg(NewVal).addReg(Ptr).addImm(0); 1790 BuildMI(BB, DL, TII->get(BEQ)) 1791 .addReg(Success).addReg(ZERO).addMBB(loop1MBB); 1792 1793 MI.eraseFromParent(); // The instruction is gone now. 1794 1795 return exitMBB; 1796 } 1797 1798 MachineBasicBlock *MipsTargetLowering::emitAtomicCmpSwapPartword( 1799 MachineInstr &MI, MachineBasicBlock *BB, unsigned Size) const { 1800 assert((Size == 1 || Size == 2) && 1801 "Unsupported size for EmitAtomicCmpSwapPartial."); 1802 1803 MachineFunction *MF = BB->getParent(); 1804 MachineRegisterInfo &RegInfo = MF->getRegInfo(); 1805 const TargetRegisterClass *RC = getRegClassFor(MVT::i32); 1806 const bool ArePtrs64bit = ABI.ArePtrs64bit(); 1807 const TargetRegisterClass *RCp = 1808 getRegClassFor(ArePtrs64bit ? MVT::i64 : MVT::i32); 1809 const TargetInstrInfo *TII = Subtarget.getInstrInfo(); 1810 DebugLoc DL = MI.getDebugLoc(); 1811 1812 unsigned Dest = MI.getOperand(0).getReg(); 1813 unsigned Ptr = MI.getOperand(1).getReg(); 1814 unsigned CmpVal = MI.getOperand(2).getReg(); 1815 unsigned NewVal = MI.getOperand(3).getReg(); 1816 1817 unsigned AlignedAddr = RegInfo.createVirtualRegister(RCp); 1818 unsigned ShiftAmt = RegInfo.createVirtualRegister(RC); 1819 unsigned Mask = RegInfo.createVirtualRegister(RC); 1820 unsigned Mask2 = RegInfo.createVirtualRegister(RC); 1821 unsigned ShiftedCmpVal = RegInfo.createVirtualRegister(RC); 1822 unsigned OldVal = RegInfo.createVirtualRegister(RC); 1823 unsigned MaskedOldVal0 = RegInfo.createVirtualRegister(RC); 1824 unsigned ShiftedNewVal = RegInfo.createVirtualRegister(RC); 1825 unsigned MaskLSB2 = RegInfo.createVirtualRegister(RCp); 1826 unsigned PtrLSB2 = RegInfo.createVirtualRegister(RC); 1827 unsigned MaskUpper = RegInfo.createVirtualRegister(RC); 1828 unsigned MaskedCmpVal = RegInfo.createVirtualRegister(RC); 1829 unsigned MaskedNewVal = RegInfo.createVirtualRegister(RC); 1830 unsigned MaskedOldVal1 = RegInfo.createVirtualRegister(RC); 1831 unsigned StoreVal = RegInfo.createVirtualRegister(RC); 1832 unsigned SrlRes = RegInfo.createVirtualRegister(RC); 1833 unsigned Success = RegInfo.createVirtualRegister(RC); 1834 unsigned LL, SC; 1835 1836 if (isMicroMips) { 1837 LL = Mips::LL_MM; 1838 SC = Mips::SC_MM; 1839 } else { 1840 LL = Subtarget.hasMips32r6() ? (ArePtrs64bit ? Mips::LL64_R6 : Mips::LL_R6) 1841 : (ArePtrs64bit ? Mips::LL64 : Mips::LL); 1842 SC = Subtarget.hasMips32r6() ? (ArePtrs64bit ? Mips::SC64_R6 : Mips::SC_R6) 1843 : (ArePtrs64bit ? Mips::SC64 : Mips::SC); 1844 } 1845 1846 // insert new blocks after the current block 1847 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 1848 MachineBasicBlock *loop1MBB = MF->CreateMachineBasicBlock(LLVM_BB); 1849 MachineBasicBlock *loop2MBB = MF->CreateMachineBasicBlock(LLVM_BB); 1850 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(LLVM_BB); 1851 MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB); 1852 MachineFunction::iterator It = ++BB->getIterator(); 1853 MF->insert(It, loop1MBB); 1854 MF->insert(It, loop2MBB); 1855 MF->insert(It, sinkMBB); 1856 MF->insert(It, exitMBB); 1857 1858 // Transfer the remainder of BB and its successor edges to exitMBB. 1859 exitMBB->splice(exitMBB->begin(), BB, 1860 std::next(MachineBasicBlock::iterator(MI)), BB->end()); 1861 exitMBB->transferSuccessorsAndUpdatePHIs(BB); 1862 1863 BB->addSuccessor(loop1MBB); 1864 loop1MBB->addSuccessor(sinkMBB); 1865 loop1MBB->addSuccessor(loop2MBB); 1866 loop2MBB->addSuccessor(loop1MBB); 1867 loop2MBB->addSuccessor(sinkMBB); 1868 sinkMBB->addSuccessor(exitMBB); 1869 1870 // FIXME: computation of newval2 can be moved to loop2MBB. 1871 // thisMBB: 1872 // addiu masklsb2,$0,-4 # 0xfffffffc 1873 // and alignedaddr,ptr,masklsb2 1874 // andi ptrlsb2,ptr,3 1875 // xori ptrlsb2,ptrlsb2,3 # Only for BE 1876 // sll shiftamt,ptrlsb2,3 1877 // ori maskupper,$0,255 # 0xff 1878 // sll mask,maskupper,shiftamt 1879 // nor mask2,$0,mask 1880 // andi maskedcmpval,cmpval,255 1881 // sll shiftedcmpval,maskedcmpval,shiftamt 1882 // andi maskednewval,newval,255 1883 // sll shiftednewval,maskednewval,shiftamt 1884 int64_t MaskImm = (Size == 1) ? 255 : 65535; 1885 BuildMI(BB, DL, TII->get(ArePtrs64bit ? Mips::DADDiu : Mips::ADDiu), MaskLSB2) 1886 .addReg(ABI.GetNullPtr()).addImm(-4); 1887 BuildMI(BB, DL, TII->get(ArePtrs64bit ? Mips::AND64 : Mips::AND), AlignedAddr) 1888 .addReg(Ptr).addReg(MaskLSB2); 1889 BuildMI(BB, DL, TII->get(Mips::ANDi), PtrLSB2) 1890 .addReg(Ptr, 0, ArePtrs64bit ? Mips::sub_32 : 0).addImm(3); 1891 if (Subtarget.isLittle()) { 1892 BuildMI(BB, DL, TII->get(Mips::SLL), ShiftAmt).addReg(PtrLSB2).addImm(3); 1893 } else { 1894 unsigned Off = RegInfo.createVirtualRegister(RC); 1895 BuildMI(BB, DL, TII->get(Mips::XORi), Off) 1896 .addReg(PtrLSB2).addImm((Size == 1) ? 3 : 2); 1897 BuildMI(BB, DL, TII->get(Mips::SLL), ShiftAmt).addReg(Off).addImm(3); 1898 } 1899 BuildMI(BB, DL, TII->get(Mips::ORi), MaskUpper) 1900 .addReg(Mips::ZERO).addImm(MaskImm); 1901 BuildMI(BB, DL, TII->get(Mips::SLLV), Mask) 1902 .addReg(MaskUpper).addReg(ShiftAmt); 1903 BuildMI(BB, DL, TII->get(Mips::NOR), Mask2).addReg(Mips::ZERO).addReg(Mask); 1904 BuildMI(BB, DL, TII->get(Mips::ANDi), MaskedCmpVal) 1905 .addReg(CmpVal).addImm(MaskImm); 1906 BuildMI(BB, DL, TII->get(Mips::SLLV), ShiftedCmpVal) 1907 .addReg(MaskedCmpVal).addReg(ShiftAmt); 1908 BuildMI(BB, DL, TII->get(Mips::ANDi), MaskedNewVal) 1909 .addReg(NewVal).addImm(MaskImm); 1910 BuildMI(BB, DL, TII->get(Mips::SLLV), ShiftedNewVal) 1911 .addReg(MaskedNewVal).addReg(ShiftAmt); 1912 1913 // loop1MBB: 1914 // ll oldval,0(alginedaddr) 1915 // and maskedoldval0,oldval,mask 1916 // bne maskedoldval0,shiftedcmpval,sinkMBB 1917 BB = loop1MBB; 1918 BuildMI(BB, DL, TII->get(LL), OldVal).addReg(AlignedAddr).addImm(0); 1919 BuildMI(BB, DL, TII->get(Mips::AND), MaskedOldVal0) 1920 .addReg(OldVal).addReg(Mask); 1921 BuildMI(BB, DL, TII->get(Mips::BNE)) 1922 .addReg(MaskedOldVal0).addReg(ShiftedCmpVal).addMBB(sinkMBB); 1923 1924 // loop2MBB: 1925 // and maskedoldval1,oldval,mask2 1926 // or storeval,maskedoldval1,shiftednewval 1927 // sc success,storeval,0(alignedaddr) 1928 // beq success,$0,loop1MBB 1929 BB = loop2MBB; 1930 BuildMI(BB, DL, TII->get(Mips::AND), MaskedOldVal1) 1931 .addReg(OldVal).addReg(Mask2); 1932 BuildMI(BB, DL, TII->get(Mips::OR), StoreVal) 1933 .addReg(MaskedOldVal1).addReg(ShiftedNewVal); 1934 BuildMI(BB, DL, TII->get(SC), Success) 1935 .addReg(StoreVal).addReg(AlignedAddr).addImm(0); 1936 BuildMI(BB, DL, TII->get(Mips::BEQ)) 1937 .addReg(Success).addReg(Mips::ZERO).addMBB(loop1MBB); 1938 1939 // sinkMBB: 1940 // srl srlres,maskedoldval0,shiftamt 1941 // sign_extend dest,srlres 1942 BB = sinkMBB; 1943 1944 BuildMI(BB, DL, TII->get(Mips::SRLV), SrlRes) 1945 .addReg(MaskedOldVal0).addReg(ShiftAmt); 1946 BB = emitSignExtendToI32InReg(MI, BB, Size, Dest, SrlRes); 1947 1948 MI.eraseFromParent(); // The instruction is gone now. 1949 1950 return exitMBB; 1951 } 1952 1953 SDValue MipsTargetLowering::lowerBRCOND(SDValue Op, SelectionDAG &DAG) const { 1954 // The first operand is the chain, the second is the condition, the third is 1955 // the block to branch to if the condition is true. 1956 SDValue Chain = Op.getOperand(0); 1957 SDValue Dest = Op.getOperand(2); 1958 SDLoc DL(Op); 1959 1960 assert(!Subtarget.hasMips32r6() && !Subtarget.hasMips64r6()); 1961 SDValue CondRes = createFPCmp(DAG, Op.getOperand(1)); 1962 1963 // Return if flag is not set by a floating point comparison. 1964 if (CondRes.getOpcode() != MipsISD::FPCmp) 1965 return Op; 1966 1967 SDValue CCNode = CondRes.getOperand(2); 1968 Mips::CondCode CC = 1969 (Mips::CondCode)cast<ConstantSDNode>(CCNode)->getZExtValue(); 1970 unsigned Opc = invertFPCondCodeUser(CC) ? Mips::BRANCH_F : Mips::BRANCH_T; 1971 SDValue BrCode = DAG.getConstant(Opc, DL, MVT::i32); 1972 SDValue FCC0 = DAG.getRegister(Mips::FCC0, MVT::i32); 1973 return DAG.getNode(MipsISD::FPBrcond, DL, Op.getValueType(), Chain, BrCode, 1974 FCC0, Dest, CondRes); 1975 } 1976 1977 SDValue MipsTargetLowering:: 1978 lowerSELECT(SDValue Op, SelectionDAG &DAG) const 1979 { 1980 assert(!Subtarget.hasMips32r6() && !Subtarget.hasMips64r6()); 1981 SDValue Cond = createFPCmp(DAG, Op.getOperand(0)); 1982 1983 // Return if flag is not set by a floating point comparison. 1984 if (Cond.getOpcode() != MipsISD::FPCmp) 1985 return Op; 1986 1987 return createCMovFP(DAG, Cond, Op.getOperand(1), Op.getOperand(2), 1988 SDLoc(Op)); 1989 } 1990 1991 SDValue MipsTargetLowering::lowerSETCC(SDValue Op, SelectionDAG &DAG) const { 1992 assert(!Subtarget.hasMips32r6() && !Subtarget.hasMips64r6()); 1993 SDValue Cond = createFPCmp(DAG, Op); 1994 1995 assert(Cond.getOpcode() == MipsISD::FPCmp && 1996 "Floating point operand expected."); 1997 1998 SDLoc DL(Op); 1999 SDValue True = DAG.getConstant(1, DL, MVT::i32); 2000 SDValue False = DAG.getConstant(0, DL, MVT::i32); 2001 2002 return createCMovFP(DAG, Cond, True, False, DL); 2003 } 2004 2005 SDValue MipsTargetLowering::lowerGlobalAddress(SDValue Op, 2006 SelectionDAG &DAG) const { 2007 EVT Ty = Op.getValueType(); 2008 GlobalAddressSDNode *N = cast<GlobalAddressSDNode>(Op); 2009 const GlobalValue *GV = N->getGlobal(); 2010 2011 if (!isPositionIndependent()) { 2012 const MipsTargetObjectFile *TLOF = 2013 static_cast<const MipsTargetObjectFile *>( 2014 getTargetMachine().getObjFileLowering()); 2015 const GlobalObject *GO = GV->getBaseObject(); 2016 if (GO && TLOF->IsGlobalInSmallSection(GO, getTargetMachine())) 2017 // %gp_rel relocation 2018 return getAddrGPRel(N, SDLoc(N), Ty, DAG, ABI.IsN64()); 2019 2020 // %hi/%lo relocation 2021 return Subtarget.hasSym32() ? getAddrNonPIC(N, SDLoc(N), Ty, DAG) 2022 // %highest/%higher/%hi/%lo relocation 2023 : getAddrNonPICSym64(N, SDLoc(N), Ty, DAG); 2024 } 2025 2026 // Every other architecture would use shouldAssumeDSOLocal in here, but 2027 // mips is special. 2028 // * In PIC code mips requires got loads even for local statics! 2029 // * To save on got entries, for local statics the got entry contains the 2030 // page and an additional add instruction takes care of the low bits. 2031 // * It is legal to access a hidden symbol with a non hidden undefined, 2032 // so one cannot guarantee that all access to a hidden symbol will know 2033 // it is hidden. 2034 // * Mips linkers don't support creating a page and a full got entry for 2035 // the same symbol. 2036 // * Given all that, we have to use a full got entry for hidden symbols :-( 2037 if (GV->hasLocalLinkage()) 2038 return getAddrLocal(N, SDLoc(N), Ty, DAG, ABI.IsN32() || ABI.IsN64()); 2039 2040 if (LargeGOT) 2041 return getAddrGlobalLargeGOT( 2042 N, SDLoc(N), Ty, DAG, MipsII::MO_GOT_HI16, MipsII::MO_GOT_LO16, 2043 DAG.getEntryNode(), 2044 MachinePointerInfo::getGOT(DAG.getMachineFunction())); 2045 2046 return getAddrGlobal( 2047 N, SDLoc(N), Ty, DAG, 2048 (ABI.IsN32() || ABI.IsN64()) ? MipsII::MO_GOT_DISP : MipsII::MO_GOT, 2049 DAG.getEntryNode(), MachinePointerInfo::getGOT(DAG.getMachineFunction())); 2050 } 2051 2052 SDValue MipsTargetLowering::lowerBlockAddress(SDValue Op, 2053 SelectionDAG &DAG) const { 2054 BlockAddressSDNode *N = cast<BlockAddressSDNode>(Op); 2055 EVT Ty = Op.getValueType(); 2056 2057 if (!isPositionIndependent()) 2058 return Subtarget.hasSym32() ? getAddrNonPIC(N, SDLoc(N), Ty, DAG) 2059 : getAddrNonPICSym64(N, SDLoc(N), Ty, DAG); 2060 2061 return getAddrLocal(N, SDLoc(N), Ty, DAG, ABI.IsN32() || ABI.IsN64()); 2062 } 2063 2064 SDValue MipsTargetLowering:: 2065 lowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const 2066 { 2067 // If the relocation model is PIC, use the General Dynamic TLS Model or 2068 // Local Dynamic TLS model, otherwise use the Initial Exec or 2069 // Local Exec TLS Model. 2070 2071 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op); 2072 if (DAG.getTarget().useEmulatedTLS()) 2073 return LowerToTLSEmulatedModel(GA, DAG); 2074 2075 SDLoc DL(GA); 2076 const GlobalValue *GV = GA->getGlobal(); 2077 EVT PtrVT = getPointerTy(DAG.getDataLayout()); 2078 2079 TLSModel::Model model = getTargetMachine().getTLSModel(GV); 2080 2081 if (model == TLSModel::GeneralDynamic || model == TLSModel::LocalDynamic) { 2082 // General Dynamic and Local Dynamic TLS Model. 2083 unsigned Flag = (model == TLSModel::LocalDynamic) ? MipsII::MO_TLSLDM 2084 : MipsII::MO_TLSGD; 2085 2086 SDValue TGA = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, Flag); 2087 SDValue Argument = DAG.getNode(MipsISD::Wrapper, DL, PtrVT, 2088 getGlobalReg(DAG, PtrVT), TGA); 2089 unsigned PtrSize = PtrVT.getSizeInBits(); 2090 IntegerType *PtrTy = Type::getIntNTy(*DAG.getContext(), PtrSize); 2091 2092 SDValue TlsGetAddr = DAG.getExternalSymbol("__tls_get_addr", PtrVT); 2093 2094 ArgListTy Args; 2095 ArgListEntry Entry; 2096 Entry.Node = Argument; 2097 Entry.Ty = PtrTy; 2098 Args.push_back(Entry); 2099 2100 TargetLowering::CallLoweringInfo CLI(DAG); 2101 CLI.setDebugLoc(DL) 2102 .setChain(DAG.getEntryNode()) 2103 .setLibCallee(CallingConv::C, PtrTy, TlsGetAddr, std::move(Args)); 2104 std::pair<SDValue, SDValue> CallResult = LowerCallTo(CLI); 2105 2106 SDValue Ret = CallResult.first; 2107 2108 if (model != TLSModel::LocalDynamic) 2109 return Ret; 2110 2111 SDValue TGAHi = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, 2112 MipsII::MO_DTPREL_HI); 2113 SDValue Hi = DAG.getNode(MipsISD::Hi, DL, PtrVT, TGAHi); 2114 SDValue TGALo = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, 2115 MipsII::MO_DTPREL_LO); 2116 SDValue Lo = DAG.getNode(MipsISD::Lo, DL, PtrVT, TGALo); 2117 SDValue Add = DAG.getNode(ISD::ADD, DL, PtrVT, Hi, Ret); 2118 return DAG.getNode(ISD::ADD, DL, PtrVT, Add, Lo); 2119 } 2120 2121 SDValue Offset; 2122 if (model == TLSModel::InitialExec) { 2123 // Initial Exec TLS Model 2124 SDValue TGA = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, 2125 MipsII::MO_GOTTPREL); 2126 TGA = DAG.getNode(MipsISD::Wrapper, DL, PtrVT, getGlobalReg(DAG, PtrVT), 2127 TGA); 2128 Offset = 2129 DAG.getLoad(PtrVT, DL, DAG.getEntryNode(), TGA, MachinePointerInfo()); 2130 } else { 2131 // Local Exec TLS Model 2132 assert(model == TLSModel::LocalExec); 2133 SDValue TGAHi = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, 2134 MipsII::MO_TPREL_HI); 2135 SDValue TGALo = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, 2136 MipsII::MO_TPREL_LO); 2137 SDValue Hi = DAG.getNode(MipsISD::Hi, DL, PtrVT, TGAHi); 2138 SDValue Lo = DAG.getNode(MipsISD::Lo, DL, PtrVT, TGALo); 2139 Offset = DAG.getNode(ISD::ADD, DL, PtrVT, Hi, Lo); 2140 } 2141 2142 SDValue ThreadPointer = DAG.getNode(MipsISD::ThreadPointer, DL, PtrVT); 2143 return DAG.getNode(ISD::ADD, DL, PtrVT, ThreadPointer, Offset); 2144 } 2145 2146 SDValue MipsTargetLowering:: 2147 lowerJumpTable(SDValue Op, SelectionDAG &DAG) const 2148 { 2149 JumpTableSDNode *N = cast<JumpTableSDNode>(Op); 2150 EVT Ty = Op.getValueType(); 2151 2152 if (!isPositionIndependent()) 2153 return Subtarget.hasSym32() ? getAddrNonPIC(N, SDLoc(N), Ty, DAG) 2154 : getAddrNonPICSym64(N, SDLoc(N), Ty, DAG); 2155 2156 return getAddrLocal(N, SDLoc(N), Ty, DAG, ABI.IsN32() || ABI.IsN64()); 2157 } 2158 2159 SDValue MipsTargetLowering:: 2160 lowerConstantPool(SDValue Op, SelectionDAG &DAG) const 2161 { 2162 ConstantPoolSDNode *N = cast<ConstantPoolSDNode>(Op); 2163 EVT Ty = Op.getValueType(); 2164 2165 if (!isPositionIndependent()) { 2166 const MipsTargetObjectFile *TLOF = 2167 static_cast<const MipsTargetObjectFile *>( 2168 getTargetMachine().getObjFileLowering()); 2169 2170 if (TLOF->IsConstantInSmallSection(DAG.getDataLayout(), N->getConstVal(), 2171 getTargetMachine())) 2172 // %gp_rel relocation 2173 return getAddrGPRel(N, SDLoc(N), Ty, DAG, ABI.IsN64()); 2174 2175 return Subtarget.hasSym32() ? getAddrNonPIC(N, SDLoc(N), Ty, DAG) 2176 : getAddrNonPICSym64(N, SDLoc(N), Ty, DAG); 2177 } 2178 2179 return getAddrLocal(N, SDLoc(N), Ty, DAG, ABI.IsN32() || ABI.IsN64()); 2180 } 2181 2182 SDValue MipsTargetLowering::lowerVASTART(SDValue Op, SelectionDAG &DAG) const { 2183 MachineFunction &MF = DAG.getMachineFunction(); 2184 MipsFunctionInfo *FuncInfo = MF.getInfo<MipsFunctionInfo>(); 2185 2186 SDLoc DL(Op); 2187 SDValue FI = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), 2188 getPointerTy(MF.getDataLayout())); 2189 2190 // vastart just stores the address of the VarArgsFrameIndex slot into the 2191 // memory location argument. 2192 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue(); 2193 return DAG.getStore(Op.getOperand(0), DL, FI, Op.getOperand(1), 2194 MachinePointerInfo(SV)); 2195 } 2196 2197 SDValue MipsTargetLowering::lowerVAARG(SDValue Op, SelectionDAG &DAG) const { 2198 SDNode *Node = Op.getNode(); 2199 EVT VT = Node->getValueType(0); 2200 SDValue Chain = Node->getOperand(0); 2201 SDValue VAListPtr = Node->getOperand(1); 2202 unsigned Align = Node->getConstantOperandVal(3); 2203 const Value *SV = cast<SrcValueSDNode>(Node->getOperand(2))->getValue(); 2204 SDLoc DL(Node); 2205 unsigned ArgSlotSizeInBytes = (ABI.IsN32() || ABI.IsN64()) ? 8 : 4; 2206 2207 SDValue VAListLoad = DAG.getLoad(getPointerTy(DAG.getDataLayout()), DL, Chain, 2208 VAListPtr, MachinePointerInfo(SV)); 2209 SDValue VAList = VAListLoad; 2210 2211 // Re-align the pointer if necessary. 2212 // It should only ever be necessary for 64-bit types on O32 since the minimum 2213 // argument alignment is the same as the maximum type alignment for N32/N64. 2214 // 2215 // FIXME: We currently align too often. The code generator doesn't notice 2216 // when the pointer is still aligned from the last va_arg (or pair of 2217 // va_args for the i64 on O32 case). 2218 if (Align > getMinStackArgumentAlignment()) { 2219 assert(((Align & (Align-1)) == 0) && "Expected Align to be a power of 2"); 2220 2221 VAList = DAG.getNode(ISD::ADD, DL, VAList.getValueType(), VAList, 2222 DAG.getConstant(Align - 1, DL, VAList.getValueType())); 2223 2224 VAList = DAG.getNode(ISD::AND, DL, VAList.getValueType(), VAList, 2225 DAG.getConstant(-(int64_t)Align, DL, 2226 VAList.getValueType())); 2227 } 2228 2229 // Increment the pointer, VAList, to the next vaarg. 2230 auto &TD = DAG.getDataLayout(); 2231 unsigned ArgSizeInBytes = 2232 TD.getTypeAllocSize(VT.getTypeForEVT(*DAG.getContext())); 2233 SDValue Tmp3 = 2234 DAG.getNode(ISD::ADD, DL, VAList.getValueType(), VAList, 2235 DAG.getConstant(alignTo(ArgSizeInBytes, ArgSlotSizeInBytes), 2236 DL, VAList.getValueType())); 2237 // Store the incremented VAList to the legalized pointer 2238 Chain = DAG.getStore(VAListLoad.getValue(1), DL, Tmp3, VAListPtr, 2239 MachinePointerInfo(SV)); 2240 2241 // In big-endian mode we must adjust the pointer when the load size is smaller 2242 // than the argument slot size. We must also reduce the known alignment to 2243 // match. For example in the N64 ABI, we must add 4 bytes to the offset to get 2244 // the correct half of the slot, and reduce the alignment from 8 (slot 2245 // alignment) down to 4 (type alignment). 2246 if (!Subtarget.isLittle() && ArgSizeInBytes < ArgSlotSizeInBytes) { 2247 unsigned Adjustment = ArgSlotSizeInBytes - ArgSizeInBytes; 2248 VAList = DAG.getNode(ISD::ADD, DL, VAListPtr.getValueType(), VAList, 2249 DAG.getIntPtrConstant(Adjustment, DL)); 2250 } 2251 // Load the actual argument out of the pointer VAList 2252 return DAG.getLoad(VT, DL, Chain, VAList, MachinePointerInfo()); 2253 } 2254 2255 static SDValue lowerFCOPYSIGN32(SDValue Op, SelectionDAG &DAG, 2256 bool HasExtractInsert) { 2257 EVT TyX = Op.getOperand(0).getValueType(); 2258 EVT TyY = Op.getOperand(1).getValueType(); 2259 SDLoc DL(Op); 2260 SDValue Const1 = DAG.getConstant(1, DL, MVT::i32); 2261 SDValue Const31 = DAG.getConstant(31, DL, MVT::i32); 2262 SDValue Res; 2263 2264 // If operand is of type f64, extract the upper 32-bit. Otherwise, bitcast it 2265 // to i32. 2266 SDValue X = (TyX == MVT::f32) ? 2267 DAG.getNode(ISD::BITCAST, DL, MVT::i32, Op.getOperand(0)) : 2268 DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32, Op.getOperand(0), 2269 Const1); 2270 SDValue Y = (TyY == MVT::f32) ? 2271 DAG.getNode(ISD::BITCAST, DL, MVT::i32, Op.getOperand(1)) : 2272 DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32, Op.getOperand(1), 2273 Const1); 2274 2275 if (HasExtractInsert) { 2276 // ext E, Y, 31, 1 ; extract bit31 of Y 2277 // ins X, E, 31, 1 ; insert extracted bit at bit31 of X 2278 SDValue E = DAG.getNode(MipsISD::Ext, DL, MVT::i32, Y, Const31, Const1); 2279 Res = DAG.getNode(MipsISD::Ins, DL, MVT::i32, E, Const31, Const1, X); 2280 } else { 2281 // sll SllX, X, 1 2282 // srl SrlX, SllX, 1 2283 // srl SrlY, Y, 31 2284 // sll SllY, SrlX, 31 2285 // or Or, SrlX, SllY 2286 SDValue SllX = DAG.getNode(ISD::SHL, DL, MVT::i32, X, Const1); 2287 SDValue SrlX = DAG.getNode(ISD::SRL, DL, MVT::i32, SllX, Const1); 2288 SDValue SrlY = DAG.getNode(ISD::SRL, DL, MVT::i32, Y, Const31); 2289 SDValue SllY = DAG.getNode(ISD::SHL, DL, MVT::i32, SrlY, Const31); 2290 Res = DAG.getNode(ISD::OR, DL, MVT::i32, SrlX, SllY); 2291 } 2292 2293 if (TyX == MVT::f32) 2294 return DAG.getNode(ISD::BITCAST, DL, Op.getOperand(0).getValueType(), Res); 2295 2296 SDValue LowX = DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32, 2297 Op.getOperand(0), 2298 DAG.getConstant(0, DL, MVT::i32)); 2299 return DAG.getNode(MipsISD::BuildPairF64, DL, MVT::f64, LowX, Res); 2300 } 2301 2302 static SDValue lowerFCOPYSIGN64(SDValue Op, SelectionDAG &DAG, 2303 bool HasExtractInsert) { 2304 unsigned WidthX = Op.getOperand(0).getValueSizeInBits(); 2305 unsigned WidthY = Op.getOperand(1).getValueSizeInBits(); 2306 EVT TyX = MVT::getIntegerVT(WidthX), TyY = MVT::getIntegerVT(WidthY); 2307 SDLoc DL(Op); 2308 SDValue Const1 = DAG.getConstant(1, DL, MVT::i32); 2309 2310 // Bitcast to integer nodes. 2311 SDValue X = DAG.getNode(ISD::BITCAST, DL, TyX, Op.getOperand(0)); 2312 SDValue Y = DAG.getNode(ISD::BITCAST, DL, TyY, Op.getOperand(1)); 2313 2314 if (HasExtractInsert) { 2315 // ext E, Y, width(Y) - 1, 1 ; extract bit width(Y)-1 of Y 2316 // ins X, E, width(X) - 1, 1 ; insert extracted bit at bit width(X)-1 of X 2317 SDValue E = DAG.getNode(MipsISD::Ext, DL, TyY, Y, 2318 DAG.getConstant(WidthY - 1, DL, MVT::i32), Const1); 2319 2320 if (WidthX > WidthY) 2321 E = DAG.getNode(ISD::ZERO_EXTEND, DL, TyX, E); 2322 else if (WidthY > WidthX) 2323 E = DAG.getNode(ISD::TRUNCATE, DL, TyX, E); 2324 2325 SDValue I = DAG.getNode(MipsISD::Ins, DL, TyX, E, 2326 DAG.getConstant(WidthX - 1, DL, MVT::i32), Const1, 2327 X); 2328 return DAG.getNode(ISD::BITCAST, DL, Op.getOperand(0).getValueType(), I); 2329 } 2330 2331 // (d)sll SllX, X, 1 2332 // (d)srl SrlX, SllX, 1 2333 // (d)srl SrlY, Y, width(Y)-1 2334 // (d)sll SllY, SrlX, width(Y)-1 2335 // or Or, SrlX, SllY 2336 SDValue SllX = DAG.getNode(ISD::SHL, DL, TyX, X, Const1); 2337 SDValue SrlX = DAG.getNode(ISD::SRL, DL, TyX, SllX, Const1); 2338 SDValue SrlY = DAG.getNode(ISD::SRL, DL, TyY, Y, 2339 DAG.getConstant(WidthY - 1, DL, MVT::i32)); 2340 2341 if (WidthX > WidthY) 2342 SrlY = DAG.getNode(ISD::ZERO_EXTEND, DL, TyX, SrlY); 2343 else if (WidthY > WidthX) 2344 SrlY = DAG.getNode(ISD::TRUNCATE, DL, TyX, SrlY); 2345 2346 SDValue SllY = DAG.getNode(ISD::SHL, DL, TyX, SrlY, 2347 DAG.getConstant(WidthX - 1, DL, MVT::i32)); 2348 SDValue Or = DAG.getNode(ISD::OR, DL, TyX, SrlX, SllY); 2349 return DAG.getNode(ISD::BITCAST, DL, Op.getOperand(0).getValueType(), Or); 2350 } 2351 2352 SDValue 2353 MipsTargetLowering::lowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const { 2354 if (Subtarget.isGP64bit()) 2355 return lowerFCOPYSIGN64(Op, DAG, Subtarget.hasExtractInsert()); 2356 2357 return lowerFCOPYSIGN32(Op, DAG, Subtarget.hasExtractInsert()); 2358 } 2359 2360 SDValue MipsTargetLowering:: 2361 lowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const { 2362 // check the depth 2363 assert((cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue() == 0) && 2364 "Frame address can only be determined for current frame."); 2365 2366 MachineFrameInfo &MFI = DAG.getMachineFunction().getFrameInfo(); 2367 MFI.setFrameAddressIsTaken(true); 2368 EVT VT = Op.getValueType(); 2369 SDLoc DL(Op); 2370 SDValue FrameAddr = DAG.getCopyFromReg( 2371 DAG.getEntryNode(), DL, ABI.IsN64() ? Mips::FP_64 : Mips::FP, VT); 2372 return FrameAddr; 2373 } 2374 2375 SDValue MipsTargetLowering::lowerRETURNADDR(SDValue Op, 2376 SelectionDAG &DAG) const { 2377 if (verifyReturnAddressArgumentIsConstant(Op, DAG)) 2378 return SDValue(); 2379 2380 // check the depth 2381 assert((cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue() == 0) && 2382 "Return address can be determined only for current frame."); 2383 2384 MachineFunction &MF = DAG.getMachineFunction(); 2385 MachineFrameInfo &MFI = MF.getFrameInfo(); 2386 MVT VT = Op.getSimpleValueType(); 2387 unsigned RA = ABI.IsN64() ? Mips::RA_64 : Mips::RA; 2388 MFI.setReturnAddressIsTaken(true); 2389 2390 // Return RA, which contains the return address. Mark it an implicit live-in. 2391 unsigned Reg = MF.addLiveIn(RA, getRegClassFor(VT)); 2392 return DAG.getCopyFromReg(DAG.getEntryNode(), SDLoc(Op), Reg, VT); 2393 } 2394 2395 // An EH_RETURN is the result of lowering llvm.eh.return which in turn is 2396 // generated from __builtin_eh_return (offset, handler) 2397 // The effect of this is to adjust the stack pointer by "offset" 2398 // and then branch to "handler". 2399 SDValue MipsTargetLowering::lowerEH_RETURN(SDValue Op, SelectionDAG &DAG) 2400 const { 2401 MachineFunction &MF = DAG.getMachineFunction(); 2402 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>(); 2403 2404 MipsFI->setCallsEhReturn(); 2405 SDValue Chain = Op.getOperand(0); 2406 SDValue Offset = Op.getOperand(1); 2407 SDValue Handler = Op.getOperand(2); 2408 SDLoc DL(Op); 2409 EVT Ty = ABI.IsN64() ? MVT::i64 : MVT::i32; 2410 2411 // Store stack offset in V1, store jump target in V0. Glue CopyToReg and 2412 // EH_RETURN nodes, so that instructions are emitted back-to-back. 2413 unsigned OffsetReg = ABI.IsN64() ? Mips::V1_64 : Mips::V1; 2414 unsigned AddrReg = ABI.IsN64() ? Mips::V0_64 : Mips::V0; 2415 Chain = DAG.getCopyToReg(Chain, DL, OffsetReg, Offset, SDValue()); 2416 Chain = DAG.getCopyToReg(Chain, DL, AddrReg, Handler, Chain.getValue(1)); 2417 return DAG.getNode(MipsISD::EH_RETURN, DL, MVT::Other, Chain, 2418 DAG.getRegister(OffsetReg, Ty), 2419 DAG.getRegister(AddrReg, getPointerTy(MF.getDataLayout())), 2420 Chain.getValue(1)); 2421 } 2422 2423 SDValue MipsTargetLowering::lowerATOMIC_FENCE(SDValue Op, 2424 SelectionDAG &DAG) const { 2425 // FIXME: Need pseudo-fence for 'singlethread' fences 2426 // FIXME: Set SType for weaker fences where supported/appropriate. 2427 unsigned SType = 0; 2428 SDLoc DL(Op); 2429 return DAG.getNode(MipsISD::Sync, DL, MVT::Other, Op.getOperand(0), 2430 DAG.getConstant(SType, DL, MVT::i32)); 2431 } 2432 2433 SDValue MipsTargetLowering::lowerShiftLeftParts(SDValue Op, 2434 SelectionDAG &DAG) const { 2435 SDLoc DL(Op); 2436 MVT VT = Subtarget.isGP64bit() ? MVT::i64 : MVT::i32; 2437 2438 SDValue Lo = Op.getOperand(0), Hi = Op.getOperand(1); 2439 SDValue Shamt = Op.getOperand(2); 2440 // if shamt < (VT.bits): 2441 // lo = (shl lo, shamt) 2442 // hi = (or (shl hi, shamt) (srl (srl lo, 1), ~shamt)) 2443 // else: 2444 // lo = 0 2445 // hi = (shl lo, shamt[4:0]) 2446 SDValue Not = DAG.getNode(ISD::XOR, DL, MVT::i32, Shamt, 2447 DAG.getConstant(-1, DL, MVT::i32)); 2448 SDValue ShiftRight1Lo = DAG.getNode(ISD::SRL, DL, VT, Lo, 2449 DAG.getConstant(1, DL, VT)); 2450 SDValue ShiftRightLo = DAG.getNode(ISD::SRL, DL, VT, ShiftRight1Lo, Not); 2451 SDValue ShiftLeftHi = DAG.getNode(ISD::SHL, DL, VT, Hi, Shamt); 2452 SDValue Or = DAG.getNode(ISD::OR, DL, VT, ShiftLeftHi, ShiftRightLo); 2453 SDValue ShiftLeftLo = DAG.getNode(ISD::SHL, DL, VT, Lo, Shamt); 2454 SDValue Cond = DAG.getNode(ISD::AND, DL, MVT::i32, Shamt, 2455 DAG.getConstant(VT.getSizeInBits(), DL, MVT::i32)); 2456 Lo = DAG.getNode(ISD::SELECT, DL, VT, Cond, 2457 DAG.getConstant(0, DL, VT), ShiftLeftLo); 2458 Hi = DAG.getNode(ISD::SELECT, DL, VT, Cond, ShiftLeftLo, Or); 2459 2460 SDValue Ops[2] = {Lo, Hi}; 2461 return DAG.getMergeValues(Ops, DL); 2462 } 2463 2464 SDValue MipsTargetLowering::lowerShiftRightParts(SDValue Op, SelectionDAG &DAG, 2465 bool IsSRA) const { 2466 SDLoc DL(Op); 2467 SDValue Lo = Op.getOperand(0), Hi = Op.getOperand(1); 2468 SDValue Shamt = Op.getOperand(2); 2469 MVT VT = Subtarget.isGP64bit() ? MVT::i64 : MVT::i32; 2470 2471 // if shamt < (VT.bits): 2472 // lo = (or (shl (shl hi, 1), ~shamt) (srl lo, shamt)) 2473 // if isSRA: 2474 // hi = (sra hi, shamt) 2475 // else: 2476 // hi = (srl hi, shamt) 2477 // else: 2478 // if isSRA: 2479 // lo = (sra hi, shamt[4:0]) 2480 // hi = (sra hi, 31) 2481 // else: 2482 // lo = (srl hi, shamt[4:0]) 2483 // hi = 0 2484 SDValue Not = DAG.getNode(ISD::XOR, DL, MVT::i32, Shamt, 2485 DAG.getConstant(-1, DL, MVT::i32)); 2486 SDValue ShiftLeft1Hi = DAG.getNode(ISD::SHL, DL, VT, Hi, 2487 DAG.getConstant(1, DL, VT)); 2488 SDValue ShiftLeftHi = DAG.getNode(ISD::SHL, DL, VT, ShiftLeft1Hi, Not); 2489 SDValue ShiftRightLo = DAG.getNode(ISD::SRL, DL, VT, Lo, Shamt); 2490 SDValue Or = DAG.getNode(ISD::OR, DL, VT, ShiftLeftHi, ShiftRightLo); 2491 SDValue ShiftRightHi = DAG.getNode(IsSRA ? ISD::SRA : ISD::SRL, 2492 DL, VT, Hi, Shamt); 2493 SDValue Cond = DAG.getNode(ISD::AND, DL, MVT::i32, Shamt, 2494 DAG.getConstant(VT.getSizeInBits(), DL, MVT::i32)); 2495 SDValue Ext = DAG.getNode(ISD::SRA, DL, VT, Hi, 2496 DAG.getConstant(VT.getSizeInBits() - 1, DL, VT)); 2497 Lo = DAG.getNode(ISD::SELECT, DL, VT, Cond, ShiftRightHi, Or); 2498 Hi = DAG.getNode(ISD::SELECT, DL, VT, Cond, 2499 IsSRA ? Ext : DAG.getConstant(0, DL, VT), ShiftRightHi); 2500 2501 SDValue Ops[2] = {Lo, Hi}; 2502 return DAG.getMergeValues(Ops, DL); 2503 } 2504 2505 static SDValue createLoadLR(unsigned Opc, SelectionDAG &DAG, LoadSDNode *LD, 2506 SDValue Chain, SDValue Src, unsigned Offset) { 2507 SDValue Ptr = LD->getBasePtr(); 2508 EVT VT = LD->getValueType(0), MemVT = LD->getMemoryVT(); 2509 EVT BasePtrVT = Ptr.getValueType(); 2510 SDLoc DL(LD); 2511 SDVTList VTList = DAG.getVTList(VT, MVT::Other); 2512 2513 if (Offset) 2514 Ptr = DAG.getNode(ISD::ADD, DL, BasePtrVT, Ptr, 2515 DAG.getConstant(Offset, DL, BasePtrVT)); 2516 2517 SDValue Ops[] = { Chain, Ptr, Src }; 2518 return DAG.getMemIntrinsicNode(Opc, DL, VTList, Ops, MemVT, 2519 LD->getMemOperand()); 2520 } 2521 2522 // Expand an unaligned 32 or 64-bit integer load node. 2523 SDValue MipsTargetLowering::lowerLOAD(SDValue Op, SelectionDAG &DAG) const { 2524 LoadSDNode *LD = cast<LoadSDNode>(Op); 2525 EVT MemVT = LD->getMemoryVT(); 2526 2527 if (Subtarget.systemSupportsUnalignedAccess()) 2528 return Op; 2529 2530 // Return if load is aligned or if MemVT is neither i32 nor i64. 2531 if ((LD->getAlignment() >= MemVT.getSizeInBits() / 8) || 2532 ((MemVT != MVT::i32) && (MemVT != MVT::i64))) 2533 return SDValue(); 2534 2535 bool IsLittle = Subtarget.isLittle(); 2536 EVT VT = Op.getValueType(); 2537 ISD::LoadExtType ExtType = LD->getExtensionType(); 2538 SDValue Chain = LD->getChain(), Undef = DAG.getUNDEF(VT); 2539 2540 assert((VT == MVT::i32) || (VT == MVT::i64)); 2541 2542 // Expand 2543 // (set dst, (i64 (load baseptr))) 2544 // to 2545 // (set tmp, (ldl (add baseptr, 7), undef)) 2546 // (set dst, (ldr baseptr, tmp)) 2547 if ((VT == MVT::i64) && (ExtType == ISD::NON_EXTLOAD)) { 2548 SDValue LDL = createLoadLR(MipsISD::LDL, DAG, LD, Chain, Undef, 2549 IsLittle ? 7 : 0); 2550 return createLoadLR(MipsISD::LDR, DAG, LD, LDL.getValue(1), LDL, 2551 IsLittle ? 0 : 7); 2552 } 2553 2554 SDValue LWL = createLoadLR(MipsISD::LWL, DAG, LD, Chain, Undef, 2555 IsLittle ? 3 : 0); 2556 SDValue LWR = createLoadLR(MipsISD::LWR, DAG, LD, LWL.getValue(1), LWL, 2557 IsLittle ? 0 : 3); 2558 2559 // Expand 2560 // (set dst, (i32 (load baseptr))) or 2561 // (set dst, (i64 (sextload baseptr))) or 2562 // (set dst, (i64 (extload baseptr))) 2563 // to 2564 // (set tmp, (lwl (add baseptr, 3), undef)) 2565 // (set dst, (lwr baseptr, tmp)) 2566 if ((VT == MVT::i32) || (ExtType == ISD::SEXTLOAD) || 2567 (ExtType == ISD::EXTLOAD)) 2568 return LWR; 2569 2570 assert((VT == MVT::i64) && (ExtType == ISD::ZEXTLOAD)); 2571 2572 // Expand 2573 // (set dst, (i64 (zextload baseptr))) 2574 // to 2575 // (set tmp0, (lwl (add baseptr, 3), undef)) 2576 // (set tmp1, (lwr baseptr, tmp0)) 2577 // (set tmp2, (shl tmp1, 32)) 2578 // (set dst, (srl tmp2, 32)) 2579 SDLoc DL(LD); 2580 SDValue Const32 = DAG.getConstant(32, DL, MVT::i32); 2581 SDValue SLL = DAG.getNode(ISD::SHL, DL, MVT::i64, LWR, Const32); 2582 SDValue SRL = DAG.getNode(ISD::SRL, DL, MVT::i64, SLL, Const32); 2583 SDValue Ops[] = { SRL, LWR.getValue(1) }; 2584 return DAG.getMergeValues(Ops, DL); 2585 } 2586 2587 static SDValue createStoreLR(unsigned Opc, SelectionDAG &DAG, StoreSDNode *SD, 2588 SDValue Chain, unsigned Offset) { 2589 SDValue Ptr = SD->getBasePtr(), Value = SD->getValue(); 2590 EVT MemVT = SD->getMemoryVT(), BasePtrVT = Ptr.getValueType(); 2591 SDLoc DL(SD); 2592 SDVTList VTList = DAG.getVTList(MVT::Other); 2593 2594 if (Offset) 2595 Ptr = DAG.getNode(ISD::ADD, DL, BasePtrVT, Ptr, 2596 DAG.getConstant(Offset, DL, BasePtrVT)); 2597 2598 SDValue Ops[] = { Chain, Value, Ptr }; 2599 return DAG.getMemIntrinsicNode(Opc, DL, VTList, Ops, MemVT, 2600 SD->getMemOperand()); 2601 } 2602 2603 // Expand an unaligned 32 or 64-bit integer store node. 2604 static SDValue lowerUnalignedIntStore(StoreSDNode *SD, SelectionDAG &DAG, 2605 bool IsLittle) { 2606 SDValue Value = SD->getValue(), Chain = SD->getChain(); 2607 EVT VT = Value.getValueType(); 2608 2609 // Expand 2610 // (store val, baseptr) or 2611 // (truncstore val, baseptr) 2612 // to 2613 // (swl val, (add baseptr, 3)) 2614 // (swr val, baseptr) 2615 if ((VT == MVT::i32) || SD->isTruncatingStore()) { 2616 SDValue SWL = createStoreLR(MipsISD::SWL, DAG, SD, Chain, 2617 IsLittle ? 3 : 0); 2618 return createStoreLR(MipsISD::SWR, DAG, SD, SWL, IsLittle ? 0 : 3); 2619 } 2620 2621 assert(VT == MVT::i64); 2622 2623 // Expand 2624 // (store val, baseptr) 2625 // to 2626 // (sdl val, (add baseptr, 7)) 2627 // (sdr val, baseptr) 2628 SDValue SDL = createStoreLR(MipsISD::SDL, DAG, SD, Chain, IsLittle ? 7 : 0); 2629 return createStoreLR(MipsISD::SDR, DAG, SD, SDL, IsLittle ? 0 : 7); 2630 } 2631 2632 // Lower (store (fp_to_sint $fp) $ptr) to (store (TruncIntFP $fp), $ptr). 2633 static SDValue lowerFP_TO_SINT_STORE(StoreSDNode *SD, SelectionDAG &DAG) { 2634 SDValue Val = SD->getValue(); 2635 2636 if (Val.getOpcode() != ISD::FP_TO_SINT) 2637 return SDValue(); 2638 2639 EVT FPTy = EVT::getFloatingPointVT(Val.getValueSizeInBits()); 2640 SDValue Tr = DAG.getNode(MipsISD::TruncIntFP, SDLoc(Val), FPTy, 2641 Val.getOperand(0)); 2642 return DAG.getStore(SD->getChain(), SDLoc(SD), Tr, SD->getBasePtr(), 2643 SD->getPointerInfo(), SD->getAlignment(), 2644 SD->getMemOperand()->getFlags()); 2645 } 2646 2647 SDValue MipsTargetLowering::lowerSTORE(SDValue Op, SelectionDAG &DAG) const { 2648 StoreSDNode *SD = cast<StoreSDNode>(Op); 2649 EVT MemVT = SD->getMemoryVT(); 2650 2651 // Lower unaligned integer stores. 2652 if (!Subtarget.systemSupportsUnalignedAccess() && 2653 (SD->getAlignment() < MemVT.getSizeInBits() / 8) && 2654 ((MemVT == MVT::i32) || (MemVT == MVT::i64))) 2655 return lowerUnalignedIntStore(SD, DAG, Subtarget.isLittle()); 2656 2657 return lowerFP_TO_SINT_STORE(SD, DAG); 2658 } 2659 2660 SDValue MipsTargetLowering::lowerEH_DWARF_CFA(SDValue Op, 2661 SelectionDAG &DAG) const { 2662 2663 // Return a fixed StackObject with offset 0 which points to the old stack 2664 // pointer. 2665 MachineFrameInfo &MFI = DAG.getMachineFunction().getFrameInfo(); 2666 EVT ValTy = Op->getValueType(0); 2667 int FI = MFI.CreateFixedObject(Op.getValueSizeInBits() / 8, 0, false); 2668 return DAG.getFrameIndex(FI, ValTy); 2669 } 2670 2671 SDValue MipsTargetLowering::lowerFP_TO_SINT(SDValue Op, 2672 SelectionDAG &DAG) const { 2673 EVT FPTy = EVT::getFloatingPointVT(Op.getValueSizeInBits()); 2674 SDValue Trunc = DAG.getNode(MipsISD::TruncIntFP, SDLoc(Op), FPTy, 2675 Op.getOperand(0)); 2676 return DAG.getNode(ISD::BITCAST, SDLoc(Op), Op.getValueType(), Trunc); 2677 } 2678 2679 //===----------------------------------------------------------------------===// 2680 // Calling Convention Implementation 2681 //===----------------------------------------------------------------------===// 2682 2683 //===----------------------------------------------------------------------===// 2684 // TODO: Implement a generic logic using tblgen that can support this. 2685 // Mips O32 ABI rules: 2686 // --- 2687 // i32 - Passed in A0, A1, A2, A3 and stack 2688 // f32 - Only passed in f32 registers if no int reg has been used yet to hold 2689 // an argument. Otherwise, passed in A1, A2, A3 and stack. 2690 // f64 - Only passed in two aliased f32 registers if no int reg has been used 2691 // yet to hold an argument. Otherwise, use A2, A3 and stack. If A1 is 2692 // not used, it must be shadowed. If only A3 is available, shadow it and 2693 // go to stack. 2694 // vXiX - Received as scalarized i32s, passed in A0 - A3 and the stack. 2695 // vXf32 - Passed in either a pair of registers {A0, A1}, {A2, A3} or {A0 - A3} 2696 // with the remainder spilled to the stack. 2697 // vXf64 - Passed in either {A0, A1, A2, A3} or {A2, A3} and in both cases 2698 // spilling the remainder to the stack. 2699 // 2700 // For vararg functions, all arguments are passed in A0, A1, A2, A3 and stack. 2701 //===----------------------------------------------------------------------===// 2702 2703 static bool CC_MipsO32(unsigned ValNo, MVT ValVT, MVT LocVT, 2704 CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, 2705 CCState &State, ArrayRef<MCPhysReg> F64Regs) { 2706 const MipsSubtarget &Subtarget = static_cast<const MipsSubtarget &>( 2707 State.getMachineFunction().getSubtarget()); 2708 2709 static const MCPhysReg IntRegs[] = { Mips::A0, Mips::A1, Mips::A2, Mips::A3 }; 2710 2711 const MipsCCState * MipsState = static_cast<MipsCCState *>(&State); 2712 2713 static const MCPhysReg F32Regs[] = { Mips::F12, Mips::F14 }; 2714 2715 static const MCPhysReg FloatVectorIntRegs[] = { Mips::A0, Mips::A2 }; 2716 2717 // Do not process byval args here. 2718 if (ArgFlags.isByVal()) 2719 return true; 2720 2721 // Promote i8 and i16 2722 if (ArgFlags.isInReg() && !Subtarget.isLittle()) { 2723 if (LocVT == MVT::i8 || LocVT == MVT::i16 || LocVT == MVT::i32) { 2724 LocVT = MVT::i32; 2725 if (ArgFlags.isSExt()) 2726 LocInfo = CCValAssign::SExtUpper; 2727 else if (ArgFlags.isZExt()) 2728 LocInfo = CCValAssign::ZExtUpper; 2729 else 2730 LocInfo = CCValAssign::AExtUpper; 2731 } 2732 } 2733 2734 // Promote i8 and i16 2735 if (LocVT == MVT::i8 || LocVT == MVT::i16) { 2736 LocVT = MVT::i32; 2737 if (ArgFlags.isSExt()) 2738 LocInfo = CCValAssign::SExt; 2739 else if (ArgFlags.isZExt()) 2740 LocInfo = CCValAssign::ZExt; 2741 else 2742 LocInfo = CCValAssign::AExt; 2743 } 2744 2745 unsigned Reg; 2746 2747 // f32 and f64 are allocated in A0, A1, A2, A3 when either of the following 2748 // is true: function is vararg, argument is 3rd or higher, there is previous 2749 // argument which is not f32 or f64. 2750 bool AllocateFloatsInIntReg = State.isVarArg() || ValNo > 1 || 2751 State.getFirstUnallocated(F32Regs) != ValNo; 2752 unsigned OrigAlign = ArgFlags.getOrigAlign(); 2753 bool isI64 = (ValVT == MVT::i32 && OrigAlign == 8); 2754 bool isVectorFloat = MipsState->WasOriginalArgVectorFloat(ValNo); 2755 2756 // The MIPS vector ABI for floats passes them in a pair of registers 2757 if (ValVT == MVT::i32 && isVectorFloat) { 2758 // This is the start of an vector that was scalarized into an unknown number 2759 // of components. It doesn't matter how many there are. Allocate one of the 2760 // notional 8 byte aligned registers which map onto the argument stack, and 2761 // shadow the register lost to alignment requirements. 2762 if (ArgFlags.isSplit()) { 2763 Reg = State.AllocateReg(FloatVectorIntRegs); 2764 if (Reg == Mips::A2) 2765 State.AllocateReg(Mips::A1); 2766 else if (Reg == 0) 2767 State.AllocateReg(Mips::A3); 2768 } else { 2769 // If we're an intermediate component of the split, we can just attempt to 2770 // allocate a register directly. 2771 Reg = State.AllocateReg(IntRegs); 2772 } 2773 } else if (ValVT == MVT::i32 || (ValVT == MVT::f32 && AllocateFloatsInIntReg)) { 2774 Reg = State.AllocateReg(IntRegs); 2775 // If this is the first part of an i64 arg, 2776 // the allocated register must be either A0 or A2. 2777 if (isI64 && (Reg == Mips::A1 || Reg == Mips::A3)) 2778 Reg = State.AllocateReg(IntRegs); 2779 LocVT = MVT::i32; 2780 } else if (ValVT == MVT::f64 && AllocateFloatsInIntReg) { 2781 // Allocate int register and shadow next int register. If first 2782 // available register is Mips::A1 or Mips::A3, shadow it too. 2783 Reg = State.AllocateReg(IntRegs); 2784 if (Reg == Mips::A1 || Reg == Mips::A3) 2785 Reg = State.AllocateReg(IntRegs); 2786 State.AllocateReg(IntRegs); 2787 LocVT = MVT::i32; 2788 } else if (ValVT.isFloatingPoint() && !AllocateFloatsInIntReg) { 2789 // we are guaranteed to find an available float register 2790 if (ValVT == MVT::f32) { 2791 Reg = State.AllocateReg(F32Regs); 2792 // Shadow int register 2793 State.AllocateReg(IntRegs); 2794 } else { 2795 Reg = State.AllocateReg(F64Regs); 2796 // Shadow int registers 2797 unsigned Reg2 = State.AllocateReg(IntRegs); 2798 if (Reg2 == Mips::A1 || Reg2 == Mips::A3) 2799 State.AllocateReg(IntRegs); 2800 State.AllocateReg(IntRegs); 2801 } 2802 } else 2803 llvm_unreachable("Cannot handle this ValVT."); 2804 2805 if (!Reg) { 2806 unsigned Offset = State.AllocateStack(ValVT.getStoreSize(), OrigAlign); 2807 State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo)); 2808 } else 2809 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); 2810 2811 return false; 2812 } 2813 2814 static bool CC_MipsO32_FP32(unsigned ValNo, MVT ValVT, 2815 MVT LocVT, CCValAssign::LocInfo LocInfo, 2816 ISD::ArgFlagsTy ArgFlags, CCState &State) { 2817 static const MCPhysReg F64Regs[] = { Mips::D6, Mips::D7 }; 2818 2819 return CC_MipsO32(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State, F64Regs); 2820 } 2821 2822 static bool CC_MipsO32_FP64(unsigned ValNo, MVT ValVT, 2823 MVT LocVT, CCValAssign::LocInfo LocInfo, 2824 ISD::ArgFlagsTy ArgFlags, CCState &State) { 2825 static const MCPhysReg F64Regs[] = { Mips::D12_64, Mips::D14_64 }; 2826 2827 return CC_MipsO32(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State, F64Regs); 2828 } 2829 2830 static bool CC_MipsO32(unsigned ValNo, MVT ValVT, MVT LocVT, 2831 CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, 2832 CCState &State) LLVM_ATTRIBUTE_UNUSED; 2833 2834 #include "MipsGenCallingConv.inc" 2835 2836 CCAssignFn *MipsTargetLowering::CCAssignFnForCall() const{ 2837 return CC_Mips; 2838 } 2839 2840 CCAssignFn *MipsTargetLowering::CCAssignFnForReturn() const{ 2841 return RetCC_Mips; 2842 } 2843 //===----------------------------------------------------------------------===// 2844 // Call Calling Convention Implementation 2845 //===----------------------------------------------------------------------===// 2846 2847 // Return next O32 integer argument register. 2848 static unsigned getNextIntArgReg(unsigned Reg) { 2849 assert((Reg == Mips::A0) || (Reg == Mips::A2)); 2850 return (Reg == Mips::A0) ? Mips::A1 : Mips::A3; 2851 } 2852 2853 SDValue MipsTargetLowering::passArgOnStack(SDValue StackPtr, unsigned Offset, 2854 SDValue Chain, SDValue Arg, 2855 const SDLoc &DL, bool IsTailCall, 2856 SelectionDAG &DAG) const { 2857 if (!IsTailCall) { 2858 SDValue PtrOff = 2859 DAG.getNode(ISD::ADD, DL, getPointerTy(DAG.getDataLayout()), StackPtr, 2860 DAG.getIntPtrConstant(Offset, DL)); 2861 return DAG.getStore(Chain, DL, Arg, PtrOff, MachinePointerInfo()); 2862 } 2863 2864 MachineFrameInfo &MFI = DAG.getMachineFunction().getFrameInfo(); 2865 int FI = MFI.CreateFixedObject(Arg.getValueSizeInBits() / 8, Offset, false); 2866 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy(DAG.getDataLayout())); 2867 return DAG.getStore(Chain, DL, Arg, FIN, MachinePointerInfo(), 2868 /* Alignment = */ 0, MachineMemOperand::MOVolatile); 2869 } 2870 2871 void MipsTargetLowering:: 2872 getOpndList(SmallVectorImpl<SDValue> &Ops, 2873 std::deque<std::pair<unsigned, SDValue>> &RegsToPass, 2874 bool IsPICCall, bool GlobalOrExternal, bool InternalLinkage, 2875 bool IsCallReloc, CallLoweringInfo &CLI, SDValue Callee, 2876 SDValue Chain) const { 2877 // Insert node "GP copy globalreg" before call to function. 2878 // 2879 // R_MIPS_CALL* operators (emitted when non-internal functions are called 2880 // in PIC mode) allow symbols to be resolved via lazy binding. 2881 // The lazy binding stub requires GP to point to the GOT. 2882 // Note that we don't need GP to point to the GOT for indirect calls 2883 // (when R_MIPS_CALL* is not used for the call) because Mips linker generates 2884 // lazy binding stub for a function only when R_MIPS_CALL* are the only relocs 2885 // used for the function (that is, Mips linker doesn't generate lazy binding 2886 // stub for a function whose address is taken in the program). 2887 if (IsPICCall && !InternalLinkage && IsCallReloc) { 2888 unsigned GPReg = ABI.IsN64() ? Mips::GP_64 : Mips::GP; 2889 EVT Ty = ABI.IsN64() ? MVT::i64 : MVT::i32; 2890 RegsToPass.push_back(std::make_pair(GPReg, getGlobalReg(CLI.DAG, Ty))); 2891 } 2892 2893 // Build a sequence of copy-to-reg nodes chained together with token 2894 // chain and flag operands which copy the outgoing args into registers. 2895 // The InFlag in necessary since all emitted instructions must be 2896 // stuck together. 2897 SDValue InFlag; 2898 2899 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) { 2900 Chain = CLI.DAG.getCopyToReg(Chain, CLI.DL, RegsToPass[i].first, 2901 RegsToPass[i].second, InFlag); 2902 InFlag = Chain.getValue(1); 2903 } 2904 2905 // Add argument registers to the end of the list so that they are 2906 // known live into the call. 2907 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) 2908 Ops.push_back(CLI.DAG.getRegister(RegsToPass[i].first, 2909 RegsToPass[i].second.getValueType())); 2910 2911 // Add a register mask operand representing the call-preserved registers. 2912 const TargetRegisterInfo *TRI = Subtarget.getRegisterInfo(); 2913 const uint32_t *Mask = 2914 TRI->getCallPreservedMask(CLI.DAG.getMachineFunction(), CLI.CallConv); 2915 assert(Mask && "Missing call preserved mask for calling convention"); 2916 if (Subtarget.inMips16HardFloat()) { 2917 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(CLI.Callee)) { 2918 StringRef Sym = G->getGlobal()->getName(); 2919 Function *F = G->getGlobal()->getParent()->getFunction(Sym); 2920 if (F && F->hasFnAttribute("__Mips16RetHelper")) { 2921 Mask = MipsRegisterInfo::getMips16RetHelperMask(); 2922 } 2923 } 2924 } 2925 Ops.push_back(CLI.DAG.getRegisterMask(Mask)); 2926 2927 if (InFlag.getNode()) 2928 Ops.push_back(InFlag); 2929 } 2930 2931 /// LowerCall - functions arguments are copied from virtual regs to 2932 /// (physical regs)/(stack frame), CALLSEQ_START and CALLSEQ_END are emitted. 2933 SDValue 2934 MipsTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI, 2935 SmallVectorImpl<SDValue> &InVals) const { 2936 SelectionDAG &DAG = CLI.DAG; 2937 SDLoc DL = CLI.DL; 2938 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs; 2939 SmallVectorImpl<SDValue> &OutVals = CLI.OutVals; 2940 SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins; 2941 SDValue Chain = CLI.Chain; 2942 SDValue Callee = CLI.Callee; 2943 bool &IsTailCall = CLI.IsTailCall; 2944 CallingConv::ID CallConv = CLI.CallConv; 2945 bool IsVarArg = CLI.IsVarArg; 2946 2947 MachineFunction &MF = DAG.getMachineFunction(); 2948 MachineFrameInfo &MFI = MF.getFrameInfo(); 2949 const TargetFrameLowering *TFL = Subtarget.getFrameLowering(); 2950 MipsFunctionInfo *FuncInfo = MF.getInfo<MipsFunctionInfo>(); 2951 bool IsPIC = isPositionIndependent(); 2952 2953 // Analyze operands of the call, assigning locations to each operand. 2954 SmallVector<CCValAssign, 16> ArgLocs; 2955 MipsCCState CCInfo( 2956 CallConv, IsVarArg, DAG.getMachineFunction(), ArgLocs, *DAG.getContext(), 2957 MipsCCState::getSpecialCallingConvForCallee(Callee.getNode(), Subtarget)); 2958 2959 const ExternalSymbolSDNode *ES = 2960 dyn_cast_or_null<const ExternalSymbolSDNode>(Callee.getNode()); 2961 2962 // There is one case where CALLSEQ_START..CALLSEQ_END can be nested, which 2963 // is during the lowering of a call with a byval argument which produces 2964 // a call to memcpy. For the O32 case, this causes the caller to allocate 2965 // stack space for the reserved argument area for the callee, then recursively 2966 // again for the memcpy call. In the NEWABI case, this doesn't occur as those 2967 // ABIs mandate that the callee allocates the reserved argument area. We do 2968 // still produce nested CALLSEQ_START..CALLSEQ_END with zero space though. 2969 // 2970 // If the callee has a byval argument and memcpy is used, we are mandated 2971 // to already have produced a reserved argument area for the callee for O32. 2972 // Therefore, the reserved argument area can be reused for both calls. 2973 // 2974 // Other cases of calling memcpy cannot have a chain with a CALLSEQ_START 2975 // present, as we have yet to hook that node onto the chain. 2976 // 2977 // Hence, the CALLSEQ_START and CALLSEQ_END nodes can be eliminated in this 2978 // case. GCC does a similar trick, in that wherever possible, it calculates 2979 // the maximum out going argument area (including the reserved area), and 2980 // preallocates the stack space on entrance to the caller. 2981 // 2982 // FIXME: We should do the same for efficency and space. 2983 2984 // Note: The check on the calling convention below must match 2985 // MipsABIInfo::GetCalleeAllocdArgSizeInBytes(). 2986 bool MemcpyInByVal = ES && 2987 StringRef(ES->getSymbol()) == StringRef("memcpy") && 2988 CallConv != CallingConv::Fast && 2989 Chain.getOpcode() == ISD::CALLSEQ_START; 2990 2991 // Allocate the reserved argument area. It seems strange to do this from the 2992 // caller side but removing it breaks the frame size calculation. 2993 unsigned ReservedArgArea = 2994 MemcpyInByVal ? 0 : ABI.GetCalleeAllocdArgSizeInBytes(CallConv); 2995 CCInfo.AllocateStack(ReservedArgArea, 1); 2996 2997 CCInfo.AnalyzeCallOperands(Outs, CC_Mips, CLI.getArgs(), 2998 ES ? ES->getSymbol() : nullptr); 2999 3000 // Get a count of how many bytes are to be pushed on the stack. 3001 unsigned NextStackOffset = CCInfo.getNextStackOffset(); 3002 3003 // Check if it's really possible to do a tail call. Restrict it to functions 3004 // that are part of this compilation unit. 3005 bool InternalLinkage = false; 3006 if (IsTailCall) { 3007 IsTailCall = isEligibleForTailCallOptimization( 3008 CCInfo, NextStackOffset, *MF.getInfo<MipsFunctionInfo>()); 3009 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) { 3010 InternalLinkage = G->getGlobal()->hasInternalLinkage(); 3011 IsTailCall &= (InternalLinkage || G->getGlobal()->hasLocalLinkage() || 3012 G->getGlobal()->hasPrivateLinkage() || 3013 G->getGlobal()->hasHiddenVisibility() || 3014 G->getGlobal()->hasProtectedVisibility()); 3015 } 3016 } 3017 if (!IsTailCall && CLI.CS && CLI.CS.isMustTailCall()) 3018 report_fatal_error("failed to perform tail call elimination on a call " 3019 "site marked musttail"); 3020 3021 if (IsTailCall) 3022 ++NumTailCalls; 3023 3024 // Chain is the output chain of the last Load/Store or CopyToReg node. 3025 // ByValChain is the output chain of the last Memcpy node created for copying 3026 // byval arguments to the stack. 3027 unsigned StackAlignment = TFL->getStackAlignment(); 3028 NextStackOffset = alignTo(NextStackOffset, StackAlignment); 3029 SDValue NextStackOffsetVal = DAG.getIntPtrConstant(NextStackOffset, DL, true); 3030 3031 if (!(IsTailCall || MemcpyInByVal)) 3032 Chain = DAG.getCALLSEQ_START(Chain, NextStackOffset, 0, DL); 3033 3034 SDValue StackPtr = 3035 DAG.getCopyFromReg(Chain, DL, ABI.IsN64() ? Mips::SP_64 : Mips::SP, 3036 getPointerTy(DAG.getDataLayout())); 3037 3038 std::deque<std::pair<unsigned, SDValue>> RegsToPass; 3039 SmallVector<SDValue, 8> MemOpChains; 3040 3041 CCInfo.rewindByValRegsInfo(); 3042 3043 // Walk the register/memloc assignments, inserting copies/loads. 3044 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { 3045 SDValue Arg = OutVals[i]; 3046 CCValAssign &VA = ArgLocs[i]; 3047 MVT ValVT = VA.getValVT(), LocVT = VA.getLocVT(); 3048 ISD::ArgFlagsTy Flags = Outs[i].Flags; 3049 bool UseUpperBits = false; 3050 3051 // ByVal Arg. 3052 if (Flags.isByVal()) { 3053 unsigned FirstByValReg, LastByValReg; 3054 unsigned ByValIdx = CCInfo.getInRegsParamsProcessed(); 3055 CCInfo.getInRegsParamInfo(ByValIdx, FirstByValReg, LastByValReg); 3056 3057 assert(Flags.getByValSize() && 3058 "ByVal args of size 0 should have been ignored by front-end."); 3059 assert(ByValIdx < CCInfo.getInRegsParamsCount()); 3060 assert(!IsTailCall && 3061 "Do not tail-call optimize if there is a byval argument."); 3062 passByValArg(Chain, DL, RegsToPass, MemOpChains, StackPtr, MFI, DAG, Arg, 3063 FirstByValReg, LastByValReg, Flags, Subtarget.isLittle(), 3064 VA); 3065 CCInfo.nextInRegsParam(); 3066 continue; 3067 } 3068 3069 // Promote the value if needed. 3070 switch (VA.getLocInfo()) { 3071 default: 3072 llvm_unreachable("Unknown loc info!"); 3073 case CCValAssign::Full: 3074 if (VA.isRegLoc()) { 3075 if ((ValVT == MVT::f32 && LocVT == MVT::i32) || 3076 (ValVT == MVT::f64 && LocVT == MVT::i64) || 3077 (ValVT == MVT::i64 && LocVT == MVT::f64)) 3078 Arg = DAG.getNode(ISD::BITCAST, DL, LocVT, Arg); 3079 else if (ValVT == MVT::f64 && LocVT == MVT::i32) { 3080 SDValue Lo = DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32, 3081 Arg, DAG.getConstant(0, DL, MVT::i32)); 3082 SDValue Hi = DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32, 3083 Arg, DAG.getConstant(1, DL, MVT::i32)); 3084 if (!Subtarget.isLittle()) 3085 std::swap(Lo, Hi); 3086 unsigned LocRegLo = VA.getLocReg(); 3087 unsigned LocRegHigh = getNextIntArgReg(LocRegLo); 3088 RegsToPass.push_back(std::make_pair(LocRegLo, Lo)); 3089 RegsToPass.push_back(std::make_pair(LocRegHigh, Hi)); 3090 continue; 3091 } 3092 } 3093 break; 3094 case CCValAssign::BCvt: 3095 Arg = DAG.getNode(ISD::BITCAST, DL, LocVT, Arg); 3096 break; 3097 case CCValAssign::SExtUpper: 3098 UseUpperBits = true; 3099 LLVM_FALLTHROUGH; 3100 case CCValAssign::SExt: 3101 Arg = DAG.getNode(ISD::SIGN_EXTEND, DL, LocVT, Arg); 3102 break; 3103 case CCValAssign::ZExtUpper: 3104 UseUpperBits = true; 3105 LLVM_FALLTHROUGH; 3106 case CCValAssign::ZExt: 3107 Arg = DAG.getNode(ISD::ZERO_EXTEND, DL, LocVT, Arg); 3108 break; 3109 case CCValAssign::AExtUpper: 3110 UseUpperBits = true; 3111 LLVM_FALLTHROUGH; 3112 case CCValAssign::AExt: 3113 Arg = DAG.getNode(ISD::ANY_EXTEND, DL, LocVT, Arg); 3114 break; 3115 } 3116 3117 if (UseUpperBits) { 3118 unsigned ValSizeInBits = Outs[i].ArgVT.getSizeInBits(); 3119 unsigned LocSizeInBits = VA.getLocVT().getSizeInBits(); 3120 Arg = DAG.getNode( 3121 ISD::SHL, DL, VA.getLocVT(), Arg, 3122 DAG.getConstant(LocSizeInBits - ValSizeInBits, DL, VA.getLocVT())); 3123 } 3124 3125 // Arguments that can be passed on register must be kept at 3126 // RegsToPass vector 3127 if (VA.isRegLoc()) { 3128 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg)); 3129 continue; 3130 } 3131 3132 // Register can't get to this point... 3133 assert(VA.isMemLoc()); 3134 3135 // emit ISD::STORE whichs stores the 3136 // parameter value to a stack Location 3137 MemOpChains.push_back(passArgOnStack(StackPtr, VA.getLocMemOffset(), 3138 Chain, Arg, DL, IsTailCall, DAG)); 3139 } 3140 3141 // Transform all store nodes into one single node because all store 3142 // nodes are independent of each other. 3143 if (!MemOpChains.empty()) 3144 Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, MemOpChains); 3145 3146 // If the callee is a GlobalAddress/ExternalSymbol node (quite common, every 3147 // direct call is) turn it into a TargetGlobalAddress/TargetExternalSymbol 3148 // node so that legalize doesn't hack it. 3149 3150 EVT Ty = Callee.getValueType(); 3151 bool GlobalOrExternal = false, IsCallReloc = false; 3152 3153 // The long-calls feature is ignored in case of PIC. 3154 // While we do not support -mshared / -mno-shared properly, 3155 // ignore long-calls in case of -mabicalls too. 3156 if (!Subtarget.isABICalls() && !IsPIC) { 3157 // If the function should be called using "long call", 3158 // get its address into a register to prevent using 3159 // of the `jal` instruction for the direct call. 3160 if (auto *N = dyn_cast<ExternalSymbolSDNode>(Callee)) { 3161 if (Subtarget.useLongCalls()) 3162 Callee = Subtarget.hasSym32() 3163 ? getAddrNonPIC(N, SDLoc(N), Ty, DAG) 3164 : getAddrNonPICSym64(N, SDLoc(N), Ty, DAG); 3165 } else if (auto *N = dyn_cast<GlobalAddressSDNode>(Callee)) { 3166 bool UseLongCalls = Subtarget.useLongCalls(); 3167 // If the function has long-call/far/near attribute 3168 // it overrides command line switch pased to the backend. 3169 if (auto *F = dyn_cast<Function>(N->getGlobal())) { 3170 if (F->hasFnAttribute("long-call")) 3171 UseLongCalls = true; 3172 else if (F->hasFnAttribute("short-call")) 3173 UseLongCalls = false; 3174 } 3175 if (UseLongCalls) 3176 Callee = Subtarget.hasSym32() 3177 ? getAddrNonPIC(N, SDLoc(N), Ty, DAG) 3178 : getAddrNonPICSym64(N, SDLoc(N), Ty, DAG); 3179 } 3180 } 3181 3182 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) { 3183 if (IsPIC) { 3184 const GlobalValue *Val = G->getGlobal(); 3185 InternalLinkage = Val->hasInternalLinkage(); 3186 3187 if (InternalLinkage) 3188 Callee = getAddrLocal(G, DL, Ty, DAG, ABI.IsN32() || ABI.IsN64()); 3189 else if (LargeGOT) { 3190 Callee = getAddrGlobalLargeGOT(G, DL, Ty, DAG, MipsII::MO_CALL_HI16, 3191 MipsII::MO_CALL_LO16, Chain, 3192 FuncInfo->callPtrInfo(Val)); 3193 IsCallReloc = true; 3194 } else { 3195 Callee = getAddrGlobal(G, DL, Ty, DAG, MipsII::MO_GOT_CALL, Chain, 3196 FuncInfo->callPtrInfo(Val)); 3197 IsCallReloc = true; 3198 } 3199 } else 3200 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), DL, 3201 getPointerTy(DAG.getDataLayout()), 0, 3202 MipsII::MO_NO_FLAG); 3203 GlobalOrExternal = true; 3204 } 3205 else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) { 3206 const char *Sym = S->getSymbol(); 3207 3208 if (!IsPIC) // static 3209 Callee = DAG.getTargetExternalSymbol( 3210 Sym, getPointerTy(DAG.getDataLayout()), MipsII::MO_NO_FLAG); 3211 else if (LargeGOT) { 3212 Callee = getAddrGlobalLargeGOT(S, DL, Ty, DAG, MipsII::MO_CALL_HI16, 3213 MipsII::MO_CALL_LO16, Chain, 3214 FuncInfo->callPtrInfo(Sym)); 3215 IsCallReloc = true; 3216 } else { // PIC 3217 Callee = getAddrGlobal(S, DL, Ty, DAG, MipsII::MO_GOT_CALL, Chain, 3218 FuncInfo->callPtrInfo(Sym)); 3219 IsCallReloc = true; 3220 } 3221 3222 GlobalOrExternal = true; 3223 } 3224 3225 SmallVector<SDValue, 8> Ops(1, Chain); 3226 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue); 3227 3228 getOpndList(Ops, RegsToPass, IsPIC, GlobalOrExternal, InternalLinkage, 3229 IsCallReloc, CLI, Callee, Chain); 3230 3231 if (IsTailCall) { 3232 MF.getFrameInfo().setHasTailCall(); 3233 return DAG.getNode(MipsISD::TailCall, DL, MVT::Other, Ops); 3234 } 3235 3236 Chain = DAG.getNode(MipsISD::JmpLink, DL, NodeTys, Ops); 3237 SDValue InFlag = Chain.getValue(1); 3238 3239 // Create the CALLSEQ_END node in the case of where it is not a call to 3240 // memcpy. 3241 if (!(MemcpyInByVal)) { 3242 Chain = DAG.getCALLSEQ_END(Chain, NextStackOffsetVal, 3243 DAG.getIntPtrConstant(0, DL, true), InFlag, DL); 3244 InFlag = Chain.getValue(1); 3245 } 3246 3247 // Handle result values, copying them out of physregs into vregs that we 3248 // return. 3249 return LowerCallResult(Chain, InFlag, CallConv, IsVarArg, Ins, DL, DAG, 3250 InVals, CLI); 3251 } 3252 3253 /// LowerCallResult - Lower the result values of a call into the 3254 /// appropriate copies out of appropriate physical registers. 3255 SDValue MipsTargetLowering::LowerCallResult( 3256 SDValue Chain, SDValue InFlag, CallingConv::ID CallConv, bool IsVarArg, 3257 const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &DL, 3258 SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals, 3259 TargetLowering::CallLoweringInfo &CLI) const { 3260 // Assign locations to each value returned by this call. 3261 SmallVector<CCValAssign, 16> RVLocs; 3262 MipsCCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), RVLocs, 3263 *DAG.getContext()); 3264 3265 const ExternalSymbolSDNode *ES = 3266 dyn_cast_or_null<const ExternalSymbolSDNode>(CLI.Callee.getNode()); 3267 CCInfo.AnalyzeCallResult(Ins, RetCC_Mips, CLI.RetTy, 3268 ES ? ES->getSymbol() : nullptr); 3269 3270 // Copy all of the result registers out of their specified physreg. 3271 for (unsigned i = 0; i != RVLocs.size(); ++i) { 3272 CCValAssign &VA = RVLocs[i]; 3273 assert(VA.isRegLoc() && "Can only return in registers!"); 3274 3275 SDValue Val = DAG.getCopyFromReg(Chain, DL, RVLocs[i].getLocReg(), 3276 RVLocs[i].getLocVT(), InFlag); 3277 Chain = Val.getValue(1); 3278 InFlag = Val.getValue(2); 3279 3280 if (VA.isUpperBitsInLoc()) { 3281 unsigned ValSizeInBits = Ins[i].ArgVT.getSizeInBits(); 3282 unsigned LocSizeInBits = VA.getLocVT().getSizeInBits(); 3283 unsigned Shift = 3284 VA.getLocInfo() == CCValAssign::ZExtUpper ? ISD::SRL : ISD::SRA; 3285 Val = DAG.getNode( 3286 Shift, DL, VA.getLocVT(), Val, 3287 DAG.getConstant(LocSizeInBits - ValSizeInBits, DL, VA.getLocVT())); 3288 } 3289 3290 switch (VA.getLocInfo()) { 3291 default: 3292 llvm_unreachable("Unknown loc info!"); 3293 case CCValAssign::Full: 3294 break; 3295 case CCValAssign::BCvt: 3296 Val = DAG.getNode(ISD::BITCAST, DL, VA.getValVT(), Val); 3297 break; 3298 case CCValAssign::AExt: 3299 case CCValAssign::AExtUpper: 3300 Val = DAG.getNode(ISD::TRUNCATE, DL, VA.getValVT(), Val); 3301 break; 3302 case CCValAssign::ZExt: 3303 case CCValAssign::ZExtUpper: 3304 Val = DAG.getNode(ISD::AssertZext, DL, VA.getLocVT(), Val, 3305 DAG.getValueType(VA.getValVT())); 3306 Val = DAG.getNode(ISD::TRUNCATE, DL, VA.getValVT(), Val); 3307 break; 3308 case CCValAssign::SExt: 3309 case CCValAssign::SExtUpper: 3310 Val = DAG.getNode(ISD::AssertSext, DL, VA.getLocVT(), Val, 3311 DAG.getValueType(VA.getValVT())); 3312 Val = DAG.getNode(ISD::TRUNCATE, DL, VA.getValVT(), Val); 3313 break; 3314 } 3315 3316 InVals.push_back(Val); 3317 } 3318 3319 return Chain; 3320 } 3321 3322 static SDValue UnpackFromArgumentSlot(SDValue Val, const CCValAssign &VA, 3323 EVT ArgVT, const SDLoc &DL, 3324 SelectionDAG &DAG) { 3325 MVT LocVT = VA.getLocVT(); 3326 EVT ValVT = VA.getValVT(); 3327 3328 // Shift into the upper bits if necessary. 3329 switch (VA.getLocInfo()) { 3330 default: 3331 break; 3332 case CCValAssign::AExtUpper: 3333 case CCValAssign::SExtUpper: 3334 case CCValAssign::ZExtUpper: { 3335 unsigned ValSizeInBits = ArgVT.getSizeInBits(); 3336 unsigned LocSizeInBits = VA.getLocVT().getSizeInBits(); 3337 unsigned Opcode = 3338 VA.getLocInfo() == CCValAssign::ZExtUpper ? ISD::SRL : ISD::SRA; 3339 Val = DAG.getNode( 3340 Opcode, DL, VA.getLocVT(), Val, 3341 DAG.getConstant(LocSizeInBits - ValSizeInBits, DL, VA.getLocVT())); 3342 break; 3343 } 3344 } 3345 3346 // If this is an value smaller than the argument slot size (32-bit for O32, 3347 // 64-bit for N32/N64), it has been promoted in some way to the argument slot 3348 // size. Extract the value and insert any appropriate assertions regarding 3349 // sign/zero extension. 3350 switch (VA.getLocInfo()) { 3351 default: 3352 llvm_unreachable("Unknown loc info!"); 3353 case CCValAssign::Full: 3354 break; 3355 case CCValAssign::AExtUpper: 3356 case CCValAssign::AExt: 3357 Val = DAG.getNode(ISD::TRUNCATE, DL, ValVT, Val); 3358 break; 3359 case CCValAssign::SExtUpper: 3360 case CCValAssign::SExt: 3361 Val = DAG.getNode(ISD::AssertSext, DL, LocVT, Val, DAG.getValueType(ValVT)); 3362 Val = DAG.getNode(ISD::TRUNCATE, DL, ValVT, Val); 3363 break; 3364 case CCValAssign::ZExtUpper: 3365 case CCValAssign::ZExt: 3366 Val = DAG.getNode(ISD::AssertZext, DL, LocVT, Val, DAG.getValueType(ValVT)); 3367 Val = DAG.getNode(ISD::TRUNCATE, DL, ValVT, Val); 3368 break; 3369 case CCValAssign::BCvt: 3370 Val = DAG.getNode(ISD::BITCAST, DL, ValVT, Val); 3371 break; 3372 } 3373 3374 return Val; 3375 } 3376 3377 //===----------------------------------------------------------------------===// 3378 // Formal Arguments Calling Convention Implementation 3379 //===----------------------------------------------------------------------===// 3380 /// LowerFormalArguments - transform physical registers into virtual registers 3381 /// and generate load operations for arguments places on the stack. 3382 SDValue MipsTargetLowering::LowerFormalArguments( 3383 SDValue Chain, CallingConv::ID CallConv, bool IsVarArg, 3384 const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &DL, 3385 SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const { 3386 MachineFunction &MF = DAG.getMachineFunction(); 3387 MachineFrameInfo &MFI = MF.getFrameInfo(); 3388 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>(); 3389 3390 MipsFI->setVarArgsFrameIndex(0); 3391 3392 // Used with vargs to acumulate store chains. 3393 std::vector<SDValue> OutChains; 3394 3395 // Assign locations to all of the incoming arguments. 3396 SmallVector<CCValAssign, 16> ArgLocs; 3397 MipsCCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), ArgLocs, 3398 *DAG.getContext()); 3399 CCInfo.AllocateStack(ABI.GetCalleeAllocdArgSizeInBytes(CallConv), 1); 3400 const Function &Func = DAG.getMachineFunction().getFunction(); 3401 Function::const_arg_iterator FuncArg = Func.arg_begin(); 3402 3403 if (Func.hasFnAttribute("interrupt") && !Func.arg_empty()) 3404 report_fatal_error( 3405 "Functions with the interrupt attribute cannot have arguments!"); 3406 3407 CCInfo.AnalyzeFormalArguments(Ins, CC_Mips_FixedArg); 3408 MipsFI->setFormalArgInfo(CCInfo.getNextStackOffset(), 3409 CCInfo.getInRegsParamsCount() > 0); 3410 3411 unsigned CurArgIdx = 0; 3412 CCInfo.rewindByValRegsInfo(); 3413 3414 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { 3415 CCValAssign &VA = ArgLocs[i]; 3416 if (Ins[i].isOrigArg()) { 3417 std::advance(FuncArg, Ins[i].getOrigArgIndex() - CurArgIdx); 3418 CurArgIdx = Ins[i].getOrigArgIndex(); 3419 } 3420 EVT ValVT = VA.getValVT(); 3421 ISD::ArgFlagsTy Flags = Ins[i].Flags; 3422 bool IsRegLoc = VA.isRegLoc(); 3423 3424 if (Flags.isByVal()) { 3425 assert(Ins[i].isOrigArg() && "Byval arguments cannot be implicit"); 3426 unsigned FirstByValReg, LastByValReg; 3427 unsigned ByValIdx = CCInfo.getInRegsParamsProcessed(); 3428 CCInfo.getInRegsParamInfo(ByValIdx, FirstByValReg, LastByValReg); 3429 3430 assert(Flags.getByValSize() && 3431 "ByVal args of size 0 should have been ignored by front-end."); 3432 assert(ByValIdx < CCInfo.getInRegsParamsCount()); 3433 copyByValRegs(Chain, DL, OutChains, DAG, Flags, InVals, &*FuncArg, 3434 FirstByValReg, LastByValReg, VA, CCInfo); 3435 CCInfo.nextInRegsParam(); 3436 continue; 3437 } 3438 3439 // Arguments stored on registers 3440 if (IsRegLoc) { 3441 MVT RegVT = VA.getLocVT(); 3442 unsigned ArgReg = VA.getLocReg(); 3443 const TargetRegisterClass *RC = getRegClassFor(RegVT); 3444 3445 // Transform the arguments stored on 3446 // physical registers into virtual ones 3447 unsigned Reg = addLiveIn(DAG.getMachineFunction(), ArgReg, RC); 3448 SDValue ArgValue = DAG.getCopyFromReg(Chain, DL, Reg, RegVT); 3449 3450 ArgValue = UnpackFromArgumentSlot(ArgValue, VA, Ins[i].ArgVT, DL, DAG); 3451 3452 // Handle floating point arguments passed in integer registers and 3453 // long double arguments passed in floating point registers. 3454 if ((RegVT == MVT::i32 && ValVT == MVT::f32) || 3455 (RegVT == MVT::i64 && ValVT == MVT::f64) || 3456 (RegVT == MVT::f64 && ValVT == MVT::i64)) 3457 ArgValue = DAG.getNode(ISD::BITCAST, DL, ValVT, ArgValue); 3458 else if (ABI.IsO32() && RegVT == MVT::i32 && 3459 ValVT == MVT::f64) { 3460 unsigned Reg2 = addLiveIn(DAG.getMachineFunction(), 3461 getNextIntArgReg(ArgReg), RC); 3462 SDValue ArgValue2 = DAG.getCopyFromReg(Chain, DL, Reg2, RegVT); 3463 if (!Subtarget.isLittle()) 3464 std::swap(ArgValue, ArgValue2); 3465 ArgValue = DAG.getNode(MipsISD::BuildPairF64, DL, MVT::f64, 3466 ArgValue, ArgValue2); 3467 } 3468 3469 InVals.push_back(ArgValue); 3470 } else { // VA.isRegLoc() 3471 MVT LocVT = VA.getLocVT(); 3472 3473 if (ABI.IsO32()) { 3474 // We ought to be able to use LocVT directly but O32 sets it to i32 3475 // when allocating floating point values to integer registers. 3476 // This shouldn't influence how we load the value into registers unless 3477 // we are targeting softfloat. 3478 if (VA.getValVT().isFloatingPoint() && !Subtarget.useSoftFloat()) 3479 LocVT = VA.getValVT(); 3480 } 3481 3482 // sanity check 3483 assert(VA.isMemLoc()); 3484 3485 // The stack pointer offset is relative to the caller stack frame. 3486 int FI = MFI.CreateFixedObject(LocVT.getSizeInBits() / 8, 3487 VA.getLocMemOffset(), true); 3488 3489 // Create load nodes to retrieve arguments from the stack 3490 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy(DAG.getDataLayout())); 3491 SDValue ArgValue = DAG.getLoad( 3492 LocVT, DL, Chain, FIN, 3493 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), FI)); 3494 OutChains.push_back(ArgValue.getValue(1)); 3495 3496 ArgValue = UnpackFromArgumentSlot(ArgValue, VA, Ins[i].ArgVT, DL, DAG); 3497 3498 InVals.push_back(ArgValue); 3499 } 3500 } 3501 3502 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { 3503 // The mips ABIs for returning structs by value requires that we copy 3504 // the sret argument into $v0 for the return. Save the argument into 3505 // a virtual register so that we can access it from the return points. 3506 if (Ins[i].Flags.isSRet()) { 3507 unsigned Reg = MipsFI->getSRetReturnReg(); 3508 if (!Reg) { 3509 Reg = MF.getRegInfo().createVirtualRegister( 3510 getRegClassFor(ABI.IsN64() ? MVT::i64 : MVT::i32)); 3511 MipsFI->setSRetReturnReg(Reg); 3512 } 3513 SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), DL, Reg, InVals[i]); 3514 Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, Copy, Chain); 3515 break; 3516 } 3517 } 3518 3519 if (IsVarArg) 3520 writeVarArgRegs(OutChains, Chain, DL, DAG, CCInfo); 3521 3522 // All stores are grouped in one node to allow the matching between 3523 // the size of Ins and InVals. This only happens when on varg functions 3524 if (!OutChains.empty()) { 3525 OutChains.push_back(Chain); 3526 Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, OutChains); 3527 } 3528 3529 return Chain; 3530 } 3531 3532 //===----------------------------------------------------------------------===// 3533 // Return Value Calling Convention Implementation 3534 //===----------------------------------------------------------------------===// 3535 3536 bool 3537 MipsTargetLowering::CanLowerReturn(CallingConv::ID CallConv, 3538 MachineFunction &MF, bool IsVarArg, 3539 const SmallVectorImpl<ISD::OutputArg> &Outs, 3540 LLVMContext &Context) const { 3541 SmallVector<CCValAssign, 16> RVLocs; 3542 MipsCCState CCInfo(CallConv, IsVarArg, MF, RVLocs, Context); 3543 return CCInfo.CheckReturn(Outs, RetCC_Mips); 3544 } 3545 3546 bool 3547 MipsTargetLowering::shouldSignExtendTypeInLibCall(EVT Type, bool IsSigned) const { 3548 if ((ABI.IsN32() || ABI.IsN64()) && Type == MVT::i32) 3549 return true; 3550 3551 return IsSigned; 3552 } 3553 3554 SDValue 3555 MipsTargetLowering::LowerInterruptReturn(SmallVectorImpl<SDValue> &RetOps, 3556 const SDLoc &DL, 3557 SelectionDAG &DAG) const { 3558 MachineFunction &MF = DAG.getMachineFunction(); 3559 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>(); 3560 3561 MipsFI->setISR(); 3562 3563 return DAG.getNode(MipsISD::ERet, DL, MVT::Other, RetOps); 3564 } 3565 3566 SDValue 3567 MipsTargetLowering::LowerReturn(SDValue Chain, CallingConv::ID CallConv, 3568 bool IsVarArg, 3569 const SmallVectorImpl<ISD::OutputArg> &Outs, 3570 const SmallVectorImpl<SDValue> &OutVals, 3571 const SDLoc &DL, SelectionDAG &DAG) const { 3572 // CCValAssign - represent the assignment of 3573 // the return value to a location 3574 SmallVector<CCValAssign, 16> RVLocs; 3575 MachineFunction &MF = DAG.getMachineFunction(); 3576 3577 // CCState - Info about the registers and stack slot. 3578 MipsCCState CCInfo(CallConv, IsVarArg, MF, RVLocs, *DAG.getContext()); 3579 3580 // Analyze return values. 3581 CCInfo.AnalyzeReturn(Outs, RetCC_Mips); 3582 3583 SDValue Flag; 3584 SmallVector<SDValue, 4> RetOps(1, Chain); 3585 3586 // Copy the result values into the output registers. 3587 for (unsigned i = 0; i != RVLocs.size(); ++i) { 3588 SDValue Val = OutVals[i]; 3589 CCValAssign &VA = RVLocs[i]; 3590 assert(VA.isRegLoc() && "Can only return in registers!"); 3591 bool UseUpperBits = false; 3592 3593 switch (VA.getLocInfo()) { 3594 default: 3595 llvm_unreachable("Unknown loc info!"); 3596 case CCValAssign::Full: 3597 break; 3598 case CCValAssign::BCvt: 3599 Val = DAG.getNode(ISD::BITCAST, DL, VA.getLocVT(), Val); 3600 break; 3601 case CCValAssign::AExtUpper: 3602 UseUpperBits = true; 3603 LLVM_FALLTHROUGH; 3604 case CCValAssign::AExt: 3605 Val = DAG.getNode(ISD::ANY_EXTEND, DL, VA.getLocVT(), Val); 3606 break; 3607 case CCValAssign::ZExtUpper: 3608 UseUpperBits = true; 3609 LLVM_FALLTHROUGH; 3610 case CCValAssign::ZExt: 3611 Val = DAG.getNode(ISD::ZERO_EXTEND, DL, VA.getLocVT(), Val); 3612 break; 3613 case CCValAssign::SExtUpper: 3614 UseUpperBits = true; 3615 LLVM_FALLTHROUGH; 3616 case CCValAssign::SExt: 3617 Val = DAG.getNode(ISD::SIGN_EXTEND, DL, VA.getLocVT(), Val); 3618 break; 3619 } 3620 3621 if (UseUpperBits) { 3622 unsigned ValSizeInBits = Outs[i].ArgVT.getSizeInBits(); 3623 unsigned LocSizeInBits = VA.getLocVT().getSizeInBits(); 3624 Val = DAG.getNode( 3625 ISD::SHL, DL, VA.getLocVT(), Val, 3626 DAG.getConstant(LocSizeInBits - ValSizeInBits, DL, VA.getLocVT())); 3627 } 3628 3629 Chain = DAG.getCopyToReg(Chain, DL, VA.getLocReg(), Val, Flag); 3630 3631 // Guarantee that all emitted copies are stuck together with flags. 3632 Flag = Chain.getValue(1); 3633 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT())); 3634 } 3635 3636 // The mips ABIs for returning structs by value requires that we copy 3637 // the sret argument into $v0 for the return. We saved the argument into 3638 // a virtual register in the entry block, so now we copy the value out 3639 // and into $v0. 3640 if (MF.getFunction().hasStructRetAttr()) { 3641 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>(); 3642 unsigned Reg = MipsFI->getSRetReturnReg(); 3643 3644 if (!Reg) 3645 llvm_unreachable("sret virtual register not created in the entry block"); 3646 SDValue Val = 3647 DAG.getCopyFromReg(Chain, DL, Reg, getPointerTy(DAG.getDataLayout())); 3648 unsigned V0 = ABI.IsN64() ? Mips::V0_64 : Mips::V0; 3649 3650 Chain = DAG.getCopyToReg(Chain, DL, V0, Val, Flag); 3651 Flag = Chain.getValue(1); 3652 RetOps.push_back(DAG.getRegister(V0, getPointerTy(DAG.getDataLayout()))); 3653 } 3654 3655 RetOps[0] = Chain; // Update chain. 3656 3657 // Add the flag if we have it. 3658 if (Flag.getNode()) 3659 RetOps.push_back(Flag); 3660 3661 // ISRs must use "eret". 3662 if (DAG.getMachineFunction().getFunction().hasFnAttribute("interrupt")) 3663 return LowerInterruptReturn(RetOps, DL, DAG); 3664 3665 // Standard return on Mips is a "jr $ra" 3666 return DAG.getNode(MipsISD::Ret, DL, MVT::Other, RetOps); 3667 } 3668 3669 //===----------------------------------------------------------------------===// 3670 // Mips Inline Assembly Support 3671 //===----------------------------------------------------------------------===// 3672 3673 /// getConstraintType - Given a constraint letter, return the type of 3674 /// constraint it is for this target. 3675 MipsTargetLowering::ConstraintType 3676 MipsTargetLowering::getConstraintType(StringRef Constraint) const { 3677 // Mips specific constraints 3678 // GCC config/mips/constraints.md 3679 // 3680 // 'd' : An address register. Equivalent to r 3681 // unless generating MIPS16 code. 3682 // 'y' : Equivalent to r; retained for 3683 // backwards compatibility. 3684 // 'c' : A register suitable for use in an indirect 3685 // jump. This will always be $25 for -mabicalls. 3686 // 'l' : The lo register. 1 word storage. 3687 // 'x' : The hilo register pair. Double word storage. 3688 if (Constraint.size() == 1) { 3689 switch (Constraint[0]) { 3690 default : break; 3691 case 'd': 3692 case 'y': 3693 case 'f': 3694 case 'c': 3695 case 'l': 3696 case 'x': 3697 return C_RegisterClass; 3698 case 'R': 3699 return C_Memory; 3700 } 3701 } 3702 3703 if (Constraint == "ZC") 3704 return C_Memory; 3705 3706 return TargetLowering::getConstraintType(Constraint); 3707 } 3708 3709 /// Examine constraint type and operand type and determine a weight value. 3710 /// This object must already have been set up with the operand type 3711 /// and the current alternative constraint selected. 3712 TargetLowering::ConstraintWeight 3713 MipsTargetLowering::getSingleConstraintMatchWeight( 3714 AsmOperandInfo &info, const char *constraint) const { 3715 ConstraintWeight weight = CW_Invalid; 3716 Value *CallOperandVal = info.CallOperandVal; 3717 // If we don't have a value, we can't do a match, 3718 // but allow it at the lowest weight. 3719 if (!CallOperandVal) 3720 return CW_Default; 3721 Type *type = CallOperandVal->getType(); 3722 // Look at the constraint type. 3723 switch (*constraint) { 3724 default: 3725 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint); 3726 break; 3727 case 'd': 3728 case 'y': 3729 if (type->isIntegerTy()) 3730 weight = CW_Register; 3731 break; 3732 case 'f': // FPU or MSA register 3733 if (Subtarget.hasMSA() && type->isVectorTy() && 3734 cast<VectorType>(type)->getBitWidth() == 128) 3735 weight = CW_Register; 3736 else if (type->isFloatTy()) 3737 weight = CW_Register; 3738 break; 3739 case 'c': // $25 for indirect jumps 3740 case 'l': // lo register 3741 case 'x': // hilo register pair 3742 if (type->isIntegerTy()) 3743 weight = CW_SpecificReg; 3744 break; 3745 case 'I': // signed 16 bit immediate 3746 case 'J': // integer zero 3747 case 'K': // unsigned 16 bit immediate 3748 case 'L': // signed 32 bit immediate where lower 16 bits are 0 3749 case 'N': // immediate in the range of -65535 to -1 (inclusive) 3750 case 'O': // signed 15 bit immediate (+- 16383) 3751 case 'P': // immediate in the range of 65535 to 1 (inclusive) 3752 if (isa<ConstantInt>(CallOperandVal)) 3753 weight = CW_Constant; 3754 break; 3755 case 'R': 3756 weight = CW_Memory; 3757 break; 3758 } 3759 return weight; 3760 } 3761 3762 /// This is a helper function to parse a physical register string and split it 3763 /// into non-numeric and numeric parts (Prefix and Reg). The first boolean flag 3764 /// that is returned indicates whether parsing was successful. The second flag 3765 /// is true if the numeric part exists. 3766 static std::pair<bool, bool> parsePhysicalReg(StringRef C, StringRef &Prefix, 3767 unsigned long long &Reg) { 3768 if (C.front() != '{' || C.back() != '}') 3769 return std::make_pair(false, false); 3770 3771 // Search for the first numeric character. 3772 StringRef::const_iterator I, B = C.begin() + 1, E = C.end() - 1; 3773 I = std::find_if(B, E, isdigit); 3774 3775 Prefix = StringRef(B, I - B); 3776 3777 // The second flag is set to false if no numeric characters were found. 3778 if (I == E) 3779 return std::make_pair(true, false); 3780 3781 // Parse the numeric characters. 3782 return std::make_pair(!getAsUnsignedInteger(StringRef(I, E - I), 10, Reg), 3783 true); 3784 } 3785 3786 std::pair<unsigned, const TargetRegisterClass *> MipsTargetLowering:: 3787 parseRegForInlineAsmConstraint(StringRef C, MVT VT) const { 3788 const TargetRegisterInfo *TRI = 3789 Subtarget.getRegisterInfo(); 3790 const TargetRegisterClass *RC; 3791 StringRef Prefix; 3792 unsigned long long Reg; 3793 3794 std::pair<bool, bool> R = parsePhysicalReg(C, Prefix, Reg); 3795 3796 if (!R.first) 3797 return std::make_pair(0U, nullptr); 3798 3799 if ((Prefix == "hi" || Prefix == "lo")) { // Parse hi/lo. 3800 // No numeric characters follow "hi" or "lo". 3801 if (R.second) 3802 return std::make_pair(0U, nullptr); 3803 3804 RC = TRI->getRegClass(Prefix == "hi" ? 3805 Mips::HI32RegClassID : Mips::LO32RegClassID); 3806 return std::make_pair(*(RC->begin()), RC); 3807 } else if (Prefix.startswith("$msa")) { 3808 // Parse $msa(ir|csr|access|save|modify|request|map|unmap) 3809 3810 // No numeric characters follow the name. 3811 if (R.second) 3812 return std::make_pair(0U, nullptr); 3813 3814 Reg = StringSwitch<unsigned long long>(Prefix) 3815 .Case("$msair", Mips::MSAIR) 3816 .Case("$msacsr", Mips::MSACSR) 3817 .Case("$msaaccess", Mips::MSAAccess) 3818 .Case("$msasave", Mips::MSASave) 3819 .Case("$msamodify", Mips::MSAModify) 3820 .Case("$msarequest", Mips::MSARequest) 3821 .Case("$msamap", Mips::MSAMap) 3822 .Case("$msaunmap", Mips::MSAUnmap) 3823 .Default(0); 3824 3825 if (!Reg) 3826 return std::make_pair(0U, nullptr); 3827 3828 RC = TRI->getRegClass(Mips::MSACtrlRegClassID); 3829 return std::make_pair(Reg, RC); 3830 } 3831 3832 if (!R.second) 3833 return std::make_pair(0U, nullptr); 3834 3835 if (Prefix == "$f") { // Parse $f0-$f31. 3836 // If the size of FP registers is 64-bit or Reg is an even number, select 3837 // the 64-bit register class. Otherwise, select the 32-bit register class. 3838 if (VT == MVT::Other) 3839 VT = (Subtarget.isFP64bit() || !(Reg % 2)) ? MVT::f64 : MVT::f32; 3840 3841 RC = getRegClassFor(VT); 3842 3843 if (RC == &Mips::AFGR64RegClass) { 3844 assert(Reg % 2 == 0); 3845 Reg >>= 1; 3846 } 3847 } else if (Prefix == "$fcc") // Parse $fcc0-$fcc7. 3848 RC = TRI->getRegClass(Mips::FCCRegClassID); 3849 else if (Prefix == "$w") { // Parse $w0-$w31. 3850 RC = getRegClassFor((VT == MVT::Other) ? MVT::v16i8 : VT); 3851 } else { // Parse $0-$31. 3852 assert(Prefix == "$"); 3853 RC = getRegClassFor((VT == MVT::Other) ? MVT::i32 : VT); 3854 } 3855 3856 assert(Reg < RC->getNumRegs()); 3857 return std::make_pair(*(RC->begin() + Reg), RC); 3858 } 3859 3860 /// Given a register class constraint, like 'r', if this corresponds directly 3861 /// to an LLVM register class, return a register of 0 and the register class 3862 /// pointer. 3863 std::pair<unsigned, const TargetRegisterClass *> 3864 MipsTargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, 3865 StringRef Constraint, 3866 MVT VT) const { 3867 if (Constraint.size() == 1) { 3868 switch (Constraint[0]) { 3869 case 'd': // Address register. Same as 'r' unless generating MIPS16 code. 3870 case 'y': // Same as 'r'. Exists for compatibility. 3871 case 'r': 3872 if (VT == MVT::i32 || VT == MVT::i16 || VT == MVT::i8) { 3873 if (Subtarget.inMips16Mode()) 3874 return std::make_pair(0U, &Mips::CPU16RegsRegClass); 3875 return std::make_pair(0U, &Mips::GPR32RegClass); 3876 } 3877 if (VT == MVT::i64 && !Subtarget.isGP64bit()) 3878 return std::make_pair(0U, &Mips::GPR32RegClass); 3879 if (VT == MVT::i64 && Subtarget.isGP64bit()) 3880 return std::make_pair(0U, &Mips::GPR64RegClass); 3881 // This will generate an error message 3882 return std::make_pair(0U, nullptr); 3883 case 'f': // FPU or MSA register 3884 if (VT == MVT::v16i8) 3885 return std::make_pair(0U, &Mips::MSA128BRegClass); 3886 else if (VT == MVT::v8i16 || VT == MVT::v8f16) 3887 return std::make_pair(0U, &Mips::MSA128HRegClass); 3888 else if (VT == MVT::v4i32 || VT == MVT::v4f32) 3889 return std::make_pair(0U, &Mips::MSA128WRegClass); 3890 else if (VT == MVT::v2i64 || VT == MVT::v2f64) 3891 return std::make_pair(0U, &Mips::MSA128DRegClass); 3892 else if (VT == MVT::f32) 3893 return std::make_pair(0U, &Mips::FGR32RegClass); 3894 else if ((VT == MVT::f64) && (!Subtarget.isSingleFloat())) { 3895 if (Subtarget.isFP64bit()) 3896 return std::make_pair(0U, &Mips::FGR64RegClass); 3897 return std::make_pair(0U, &Mips::AFGR64RegClass); 3898 } 3899 break; 3900 case 'c': // register suitable for indirect jump 3901 if (VT == MVT::i32) 3902 return std::make_pair((unsigned)Mips::T9, &Mips::GPR32RegClass); 3903 if (VT == MVT::i64) 3904 return std::make_pair((unsigned)Mips::T9_64, &Mips::GPR64RegClass); 3905 // This will generate an error message 3906 return std::make_pair(0U, nullptr); 3907 case 'l': // use the `lo` register to store values 3908 // that are no bigger than a word 3909 if (VT == MVT::i32 || VT == MVT::i16 || VT == MVT::i8) 3910 return std::make_pair((unsigned)Mips::LO0, &Mips::LO32RegClass); 3911 return std::make_pair((unsigned)Mips::LO0_64, &Mips::LO64RegClass); 3912 case 'x': // use the concatenated `hi` and `lo` registers 3913 // to store doubleword values 3914 // Fixme: Not triggering the use of both hi and low 3915 // This will generate an error message 3916 return std::make_pair(0U, nullptr); 3917 } 3918 } 3919 3920 std::pair<unsigned, const TargetRegisterClass *> R; 3921 R = parseRegForInlineAsmConstraint(Constraint, VT); 3922 3923 if (R.second) 3924 return R; 3925 3926 return TargetLowering::getRegForInlineAsmConstraint(TRI, Constraint, VT); 3927 } 3928 3929 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops 3930 /// vector. If it is invalid, don't add anything to Ops. 3931 void MipsTargetLowering::LowerAsmOperandForConstraint(SDValue Op, 3932 std::string &Constraint, 3933 std::vector<SDValue>&Ops, 3934 SelectionDAG &DAG) const { 3935 SDLoc DL(Op); 3936 SDValue Result; 3937 3938 // Only support length 1 constraints for now. 3939 if (Constraint.length() > 1) return; 3940 3941 char ConstraintLetter = Constraint[0]; 3942 switch (ConstraintLetter) { 3943 default: break; // This will fall through to the generic implementation 3944 case 'I': // Signed 16 bit constant 3945 // If this fails, the parent routine will give an error 3946 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 3947 EVT Type = Op.getValueType(); 3948 int64_t Val = C->getSExtValue(); 3949 if (isInt<16>(Val)) { 3950 Result = DAG.getTargetConstant(Val, DL, Type); 3951 break; 3952 } 3953 } 3954 return; 3955 case 'J': // integer zero 3956 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 3957 EVT Type = Op.getValueType(); 3958 int64_t Val = C->getZExtValue(); 3959 if (Val == 0) { 3960 Result = DAG.getTargetConstant(0, DL, Type); 3961 break; 3962 } 3963 } 3964 return; 3965 case 'K': // unsigned 16 bit immediate 3966 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 3967 EVT Type = Op.getValueType(); 3968 uint64_t Val = (uint64_t)C->getZExtValue(); 3969 if (isUInt<16>(Val)) { 3970 Result = DAG.getTargetConstant(Val, DL, Type); 3971 break; 3972 } 3973 } 3974 return; 3975 case 'L': // signed 32 bit immediate where lower 16 bits are 0 3976 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 3977 EVT Type = Op.getValueType(); 3978 int64_t Val = C->getSExtValue(); 3979 if ((isInt<32>(Val)) && ((Val & 0xffff) == 0)){ 3980 Result = DAG.getTargetConstant(Val, DL, Type); 3981 break; 3982 } 3983 } 3984 return; 3985 case 'N': // immediate in the range of -65535 to -1 (inclusive) 3986 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 3987 EVT Type = Op.getValueType(); 3988 int64_t Val = C->getSExtValue(); 3989 if ((Val >= -65535) && (Val <= -1)) { 3990 Result = DAG.getTargetConstant(Val, DL, Type); 3991 break; 3992 } 3993 } 3994 return; 3995 case 'O': // signed 15 bit immediate 3996 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 3997 EVT Type = Op.getValueType(); 3998 int64_t Val = C->getSExtValue(); 3999 if ((isInt<15>(Val))) { 4000 Result = DAG.getTargetConstant(Val, DL, Type); 4001 break; 4002 } 4003 } 4004 return; 4005 case 'P': // immediate in the range of 1 to 65535 (inclusive) 4006 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 4007 EVT Type = Op.getValueType(); 4008 int64_t Val = C->getSExtValue(); 4009 if ((Val <= 65535) && (Val >= 1)) { 4010 Result = DAG.getTargetConstant(Val, DL, Type); 4011 break; 4012 } 4013 } 4014 return; 4015 } 4016 4017 if (Result.getNode()) { 4018 Ops.push_back(Result); 4019 return; 4020 } 4021 4022 TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG); 4023 } 4024 4025 bool MipsTargetLowering::isLegalAddressingMode(const DataLayout &DL, 4026 const AddrMode &AM, Type *Ty, 4027 unsigned AS, Instruction *I) const { 4028 // No global is ever allowed as a base. 4029 if (AM.BaseGV) 4030 return false; 4031 4032 switch (AM.Scale) { 4033 case 0: // "r+i" or just "i", depending on HasBaseReg. 4034 break; 4035 case 1: 4036 if (!AM.HasBaseReg) // allow "r+i". 4037 break; 4038 return false; // disallow "r+r" or "r+r+i". 4039 default: 4040 return false; 4041 } 4042 4043 return true; 4044 } 4045 4046 bool 4047 MipsTargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const { 4048 // The Mips target isn't yet aware of offsets. 4049 return false; 4050 } 4051 4052 EVT MipsTargetLowering::getOptimalMemOpType(uint64_t Size, unsigned DstAlign, 4053 unsigned SrcAlign, 4054 bool IsMemset, bool ZeroMemset, 4055 bool MemcpyStrSrc, 4056 MachineFunction &MF) const { 4057 if (Subtarget.hasMips64()) 4058 return MVT::i64; 4059 4060 return MVT::i32; 4061 } 4062 4063 bool MipsTargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const { 4064 if (VT != MVT::f32 && VT != MVT::f64) 4065 return false; 4066 if (Imm.isNegZero()) 4067 return false; 4068 return Imm.isZero(); 4069 } 4070 4071 unsigned MipsTargetLowering::getJumpTableEncoding() const { 4072 4073 // FIXME: For space reasons this should be: EK_GPRel32BlockAddress. 4074 if (ABI.IsN64() && isPositionIndependent()) 4075 return MachineJumpTableInfo::EK_GPRel64BlockAddress; 4076 4077 return TargetLowering::getJumpTableEncoding(); 4078 } 4079 4080 bool MipsTargetLowering::useSoftFloat() const { 4081 return Subtarget.useSoftFloat(); 4082 } 4083 4084 void MipsTargetLowering::copyByValRegs( 4085 SDValue Chain, const SDLoc &DL, std::vector<SDValue> &OutChains, 4086 SelectionDAG &DAG, const ISD::ArgFlagsTy &Flags, 4087 SmallVectorImpl<SDValue> &InVals, const Argument *FuncArg, 4088 unsigned FirstReg, unsigned LastReg, const CCValAssign &VA, 4089 MipsCCState &State) const { 4090 MachineFunction &MF = DAG.getMachineFunction(); 4091 MachineFrameInfo &MFI = MF.getFrameInfo(); 4092 unsigned GPRSizeInBytes = Subtarget.getGPRSizeInBytes(); 4093 unsigned NumRegs = LastReg - FirstReg; 4094 unsigned RegAreaSize = NumRegs * GPRSizeInBytes; 4095 unsigned FrameObjSize = std::max(Flags.getByValSize(), RegAreaSize); 4096 int FrameObjOffset; 4097 ArrayRef<MCPhysReg> ByValArgRegs = ABI.GetByValArgRegs(); 4098 4099 if (RegAreaSize) 4100 FrameObjOffset = 4101 (int)ABI.GetCalleeAllocdArgSizeInBytes(State.getCallingConv()) - 4102 (int)((ByValArgRegs.size() - FirstReg) * GPRSizeInBytes); 4103 else 4104 FrameObjOffset = VA.getLocMemOffset(); 4105 4106 // Create frame object. 4107 EVT PtrTy = getPointerTy(DAG.getDataLayout()); 4108 // Make the fixed object stored to mutable so that the load instructions 4109 // referencing it have their memory dependencies added. 4110 // Set the frame object as isAliased which clears the underlying objects 4111 // vector in ScheduleDAGInstrs::buildSchedGraph() resulting in addition of all 4112 // stores as dependencies for loads referencing this fixed object. 4113 int FI = MFI.CreateFixedObject(FrameObjSize, FrameObjOffset, false, true); 4114 SDValue FIN = DAG.getFrameIndex(FI, PtrTy); 4115 InVals.push_back(FIN); 4116 4117 if (!NumRegs) 4118 return; 4119 4120 // Copy arg registers. 4121 MVT RegTy = MVT::getIntegerVT(GPRSizeInBytes * 8); 4122 const TargetRegisterClass *RC = getRegClassFor(RegTy); 4123 4124 for (unsigned I = 0; I < NumRegs; ++I) { 4125 unsigned ArgReg = ByValArgRegs[FirstReg + I]; 4126 unsigned VReg = addLiveIn(MF, ArgReg, RC); 4127 unsigned Offset = I * GPRSizeInBytes; 4128 SDValue StorePtr = DAG.getNode(ISD::ADD, DL, PtrTy, FIN, 4129 DAG.getConstant(Offset, DL, PtrTy)); 4130 SDValue Store = DAG.getStore(Chain, DL, DAG.getRegister(VReg, RegTy), 4131 StorePtr, MachinePointerInfo(FuncArg, Offset)); 4132 OutChains.push_back(Store); 4133 } 4134 } 4135 4136 // Copy byVal arg to registers and stack. 4137 void MipsTargetLowering::passByValArg( 4138 SDValue Chain, const SDLoc &DL, 4139 std::deque<std::pair<unsigned, SDValue>> &RegsToPass, 4140 SmallVectorImpl<SDValue> &MemOpChains, SDValue StackPtr, 4141 MachineFrameInfo &MFI, SelectionDAG &DAG, SDValue Arg, unsigned FirstReg, 4142 unsigned LastReg, const ISD::ArgFlagsTy &Flags, bool isLittle, 4143 const CCValAssign &VA) const { 4144 unsigned ByValSizeInBytes = Flags.getByValSize(); 4145 unsigned OffsetInBytes = 0; // From beginning of struct 4146 unsigned RegSizeInBytes = Subtarget.getGPRSizeInBytes(); 4147 unsigned Alignment = std::min(Flags.getByValAlign(), RegSizeInBytes); 4148 EVT PtrTy = getPointerTy(DAG.getDataLayout()), 4149 RegTy = MVT::getIntegerVT(RegSizeInBytes * 8); 4150 unsigned NumRegs = LastReg - FirstReg; 4151 4152 if (NumRegs) { 4153 ArrayRef<MCPhysReg> ArgRegs = ABI.GetByValArgRegs(); 4154 bool LeftoverBytes = (NumRegs * RegSizeInBytes > ByValSizeInBytes); 4155 unsigned I = 0; 4156 4157 // Copy words to registers. 4158 for (; I < NumRegs - LeftoverBytes; ++I, OffsetInBytes += RegSizeInBytes) { 4159 SDValue LoadPtr = DAG.getNode(ISD::ADD, DL, PtrTy, Arg, 4160 DAG.getConstant(OffsetInBytes, DL, PtrTy)); 4161 SDValue LoadVal = DAG.getLoad(RegTy, DL, Chain, LoadPtr, 4162 MachinePointerInfo(), Alignment); 4163 MemOpChains.push_back(LoadVal.getValue(1)); 4164 unsigned ArgReg = ArgRegs[FirstReg + I]; 4165 RegsToPass.push_back(std::make_pair(ArgReg, LoadVal)); 4166 } 4167 4168 // Return if the struct has been fully copied. 4169 if (ByValSizeInBytes == OffsetInBytes) 4170 return; 4171 4172 // Copy the remainder of the byval argument with sub-word loads and shifts. 4173 if (LeftoverBytes) { 4174 SDValue Val; 4175 4176 for (unsigned LoadSizeInBytes = RegSizeInBytes / 2, TotalBytesLoaded = 0; 4177 OffsetInBytes < ByValSizeInBytes; LoadSizeInBytes /= 2) { 4178 unsigned RemainingSizeInBytes = ByValSizeInBytes - OffsetInBytes; 4179 4180 if (RemainingSizeInBytes < LoadSizeInBytes) 4181 continue; 4182 4183 // Load subword. 4184 SDValue LoadPtr = DAG.getNode(ISD::ADD, DL, PtrTy, Arg, 4185 DAG.getConstant(OffsetInBytes, DL, 4186 PtrTy)); 4187 SDValue LoadVal = DAG.getExtLoad( 4188 ISD::ZEXTLOAD, DL, RegTy, Chain, LoadPtr, MachinePointerInfo(), 4189 MVT::getIntegerVT(LoadSizeInBytes * 8), Alignment); 4190 MemOpChains.push_back(LoadVal.getValue(1)); 4191 4192 // Shift the loaded value. 4193 unsigned Shamt; 4194 4195 if (isLittle) 4196 Shamt = TotalBytesLoaded * 8; 4197 else 4198 Shamt = (RegSizeInBytes - (TotalBytesLoaded + LoadSizeInBytes)) * 8; 4199 4200 SDValue Shift = DAG.getNode(ISD::SHL, DL, RegTy, LoadVal, 4201 DAG.getConstant(Shamt, DL, MVT::i32)); 4202 4203 if (Val.getNode()) 4204 Val = DAG.getNode(ISD::OR, DL, RegTy, Val, Shift); 4205 else 4206 Val = Shift; 4207 4208 OffsetInBytes += LoadSizeInBytes; 4209 TotalBytesLoaded += LoadSizeInBytes; 4210 Alignment = std::min(Alignment, LoadSizeInBytes); 4211 } 4212 4213 unsigned ArgReg = ArgRegs[FirstReg + I]; 4214 RegsToPass.push_back(std::make_pair(ArgReg, Val)); 4215 return; 4216 } 4217 } 4218 4219 // Copy remainder of byval arg to it with memcpy. 4220 unsigned MemCpySize = ByValSizeInBytes - OffsetInBytes; 4221 SDValue Src = DAG.getNode(ISD::ADD, DL, PtrTy, Arg, 4222 DAG.getConstant(OffsetInBytes, DL, PtrTy)); 4223 SDValue Dst = DAG.getNode(ISD::ADD, DL, PtrTy, StackPtr, 4224 DAG.getIntPtrConstant(VA.getLocMemOffset(), DL)); 4225 Chain = DAG.getMemcpy(Chain, DL, Dst, Src, 4226 DAG.getConstant(MemCpySize, DL, PtrTy), 4227 Alignment, /*isVolatile=*/false, /*AlwaysInline=*/false, 4228 /*isTailCall=*/false, 4229 MachinePointerInfo(), MachinePointerInfo()); 4230 MemOpChains.push_back(Chain); 4231 } 4232 4233 void MipsTargetLowering::writeVarArgRegs(std::vector<SDValue> &OutChains, 4234 SDValue Chain, const SDLoc &DL, 4235 SelectionDAG &DAG, 4236 CCState &State) const { 4237 ArrayRef<MCPhysReg> ArgRegs = ABI.GetVarArgRegs(); 4238 unsigned Idx = State.getFirstUnallocated(ArgRegs); 4239 unsigned RegSizeInBytes = Subtarget.getGPRSizeInBytes(); 4240 MVT RegTy = MVT::getIntegerVT(RegSizeInBytes * 8); 4241 const TargetRegisterClass *RC = getRegClassFor(RegTy); 4242 MachineFunction &MF = DAG.getMachineFunction(); 4243 MachineFrameInfo &MFI = MF.getFrameInfo(); 4244 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>(); 4245 4246 // Offset of the first variable argument from stack pointer. 4247 int VaArgOffset; 4248 4249 if (ArgRegs.size() == Idx) 4250 VaArgOffset = alignTo(State.getNextStackOffset(), RegSizeInBytes); 4251 else { 4252 VaArgOffset = 4253 (int)ABI.GetCalleeAllocdArgSizeInBytes(State.getCallingConv()) - 4254 (int)(RegSizeInBytes * (ArgRegs.size() - Idx)); 4255 } 4256 4257 // Record the frame index of the first variable argument 4258 // which is a value necessary to VASTART. 4259 int FI = MFI.CreateFixedObject(RegSizeInBytes, VaArgOffset, true); 4260 MipsFI->setVarArgsFrameIndex(FI); 4261 4262 // Copy the integer registers that have not been used for argument passing 4263 // to the argument register save area. For O32, the save area is allocated 4264 // in the caller's stack frame, while for N32/64, it is allocated in the 4265 // callee's stack frame. 4266 for (unsigned I = Idx; I < ArgRegs.size(); 4267 ++I, VaArgOffset += RegSizeInBytes) { 4268 unsigned Reg = addLiveIn(MF, ArgRegs[I], RC); 4269 SDValue ArgValue = DAG.getCopyFromReg(Chain, DL, Reg, RegTy); 4270 FI = MFI.CreateFixedObject(RegSizeInBytes, VaArgOffset, true); 4271 SDValue PtrOff = DAG.getFrameIndex(FI, getPointerTy(DAG.getDataLayout())); 4272 SDValue Store = 4273 DAG.getStore(Chain, DL, ArgValue, PtrOff, MachinePointerInfo()); 4274 cast<StoreSDNode>(Store.getNode())->getMemOperand()->setValue( 4275 (Value *)nullptr); 4276 OutChains.push_back(Store); 4277 } 4278 } 4279 4280 void MipsTargetLowering::HandleByVal(CCState *State, unsigned &Size, 4281 unsigned Align) const { 4282 const TargetFrameLowering *TFL = Subtarget.getFrameLowering(); 4283 4284 assert(Size && "Byval argument's size shouldn't be 0."); 4285 4286 Align = std::min(Align, TFL->getStackAlignment()); 4287 4288 unsigned FirstReg = 0; 4289 unsigned NumRegs = 0; 4290 4291 if (State->getCallingConv() != CallingConv::Fast) { 4292 unsigned RegSizeInBytes = Subtarget.getGPRSizeInBytes(); 4293 ArrayRef<MCPhysReg> IntArgRegs = ABI.GetByValArgRegs(); 4294 // FIXME: The O32 case actually describes no shadow registers. 4295 const MCPhysReg *ShadowRegs = 4296 ABI.IsO32() ? IntArgRegs.data() : Mips64DPRegs; 4297 4298 // We used to check the size as well but we can't do that anymore since 4299 // CCState::HandleByVal() rounds up the size after calling this function. 4300 assert(!(Align % RegSizeInBytes) && 4301 "Byval argument's alignment should be a multiple of" 4302 "RegSizeInBytes."); 4303 4304 FirstReg = State->getFirstUnallocated(IntArgRegs); 4305 4306 // If Align > RegSizeInBytes, the first arg register must be even. 4307 // FIXME: This condition happens to do the right thing but it's not the 4308 // right way to test it. We want to check that the stack frame offset 4309 // of the register is aligned. 4310 if ((Align > RegSizeInBytes) && (FirstReg % 2)) { 4311 State->AllocateReg(IntArgRegs[FirstReg], ShadowRegs[FirstReg]); 4312 ++FirstReg; 4313 } 4314 4315 // Mark the registers allocated. 4316 Size = alignTo(Size, RegSizeInBytes); 4317 for (unsigned I = FirstReg; Size > 0 && (I < IntArgRegs.size()); 4318 Size -= RegSizeInBytes, ++I, ++NumRegs) 4319 State->AllocateReg(IntArgRegs[I], ShadowRegs[I]); 4320 } 4321 4322 State->addInRegsParamInfo(FirstReg, FirstReg + NumRegs); 4323 } 4324 4325 MachineBasicBlock *MipsTargetLowering::emitPseudoSELECT(MachineInstr &MI, 4326 MachineBasicBlock *BB, 4327 bool isFPCmp, 4328 unsigned Opc) const { 4329 assert(!(Subtarget.hasMips4() || Subtarget.hasMips32()) && 4330 "Subtarget already supports SELECT nodes with the use of" 4331 "conditional-move instructions."); 4332 4333 const TargetInstrInfo *TII = 4334 Subtarget.getInstrInfo(); 4335 DebugLoc DL = MI.getDebugLoc(); 4336 4337 // To "insert" a SELECT instruction, we actually have to insert the 4338 // diamond control-flow pattern. The incoming instruction knows the 4339 // destination vreg to set, the condition code register to branch on, the 4340 // true/false values to select between, and a branch opcode to use. 4341 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 4342 MachineFunction::iterator It = ++BB->getIterator(); 4343 4344 // thisMBB: 4345 // ... 4346 // TrueVal = ... 4347 // setcc r1, r2, r3 4348 // bNE r1, r0, copy1MBB 4349 // fallthrough --> copy0MBB 4350 MachineBasicBlock *thisMBB = BB; 4351 MachineFunction *F = BB->getParent(); 4352 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB); 4353 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB); 4354 F->insert(It, copy0MBB); 4355 F->insert(It, sinkMBB); 4356 4357 // Transfer the remainder of BB and its successor edges to sinkMBB. 4358 sinkMBB->splice(sinkMBB->begin(), BB, 4359 std::next(MachineBasicBlock::iterator(MI)), BB->end()); 4360 sinkMBB->transferSuccessorsAndUpdatePHIs(BB); 4361 4362 // Next, add the true and fallthrough blocks as its successors. 4363 BB->addSuccessor(copy0MBB); 4364 BB->addSuccessor(sinkMBB); 4365 4366 if (isFPCmp) { 4367 // bc1[tf] cc, sinkMBB 4368 BuildMI(BB, DL, TII->get(Opc)) 4369 .addReg(MI.getOperand(1).getReg()) 4370 .addMBB(sinkMBB); 4371 } else { 4372 // bne rs, $0, sinkMBB 4373 BuildMI(BB, DL, TII->get(Opc)) 4374 .addReg(MI.getOperand(1).getReg()) 4375 .addReg(Mips::ZERO) 4376 .addMBB(sinkMBB); 4377 } 4378 4379 // copy0MBB: 4380 // %FalseValue = ... 4381 // # fallthrough to sinkMBB 4382 BB = copy0MBB; 4383 4384 // Update machine-CFG edges 4385 BB->addSuccessor(sinkMBB); 4386 4387 // sinkMBB: 4388 // %Result = phi [ %TrueValue, thisMBB ], [ %FalseValue, copy0MBB ] 4389 // ... 4390 BB = sinkMBB; 4391 4392 BuildMI(*BB, BB->begin(), DL, TII->get(Mips::PHI), MI.getOperand(0).getReg()) 4393 .addReg(MI.getOperand(2).getReg()) 4394 .addMBB(thisMBB) 4395 .addReg(MI.getOperand(3).getReg()) 4396 .addMBB(copy0MBB); 4397 4398 MI.eraseFromParent(); // The pseudo instruction is gone now. 4399 4400 return BB; 4401 } 4402 4403 // FIXME? Maybe this could be a TableGen attribute on some registers and 4404 // this table could be generated automatically from RegInfo. 4405 unsigned MipsTargetLowering::getRegisterByName(const char* RegName, EVT VT, 4406 SelectionDAG &DAG) const { 4407 // Named registers is expected to be fairly rare. For now, just support $28 4408 // since the linux kernel uses it. 4409 if (Subtarget.isGP64bit()) { 4410 unsigned Reg = StringSwitch<unsigned>(RegName) 4411 .Case("$28", Mips::GP_64) 4412 .Default(0); 4413 if (Reg) 4414 return Reg; 4415 } else { 4416 unsigned Reg = StringSwitch<unsigned>(RegName) 4417 .Case("$28", Mips::GP) 4418 .Default(0); 4419 if (Reg) 4420 return Reg; 4421 } 4422 report_fatal_error("Invalid register name global variable"); 4423 } 4424