1 //===- MipsISelLowering.cpp - Mips DAG Lowering Implementation ------------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file defines the interfaces that Mips uses to lower LLVM code into a
11 // selection DAG.
12 //
13 //===----------------------------------------------------------------------===//
14 
15 #include "MipsISelLowering.h"
16 #include "InstPrinter/MipsInstPrinter.h"
17 #include "MCTargetDesc/MipsBaseInfo.h"
18 #include "MCTargetDesc/MipsMCTargetDesc.h"
19 #include "MipsCCState.h"
20 #include "MipsInstrInfo.h"
21 #include "MipsMachineFunction.h"
22 #include "MipsRegisterInfo.h"
23 #include "MipsSubtarget.h"
24 #include "MipsTargetMachine.h"
25 #include "MipsTargetObjectFile.h"
26 #include "llvm/ADT/APFloat.h"
27 #include "llvm/ADT/ArrayRef.h"
28 #include "llvm/ADT/SmallVector.h"
29 #include "llvm/ADT/Statistic.h"
30 #include "llvm/ADT/StringRef.h"
31 #include "llvm/ADT/StringSwitch.h"
32 #include "llvm/CodeGen/CallingConvLower.h"
33 #include "llvm/CodeGen/FunctionLoweringInfo.h"
34 #include "llvm/CodeGen/ISDOpcodes.h"
35 #include "llvm/CodeGen/MachineBasicBlock.h"
36 #include "llvm/CodeGen/MachineFrameInfo.h"
37 #include "llvm/CodeGen/MachineFunction.h"
38 #include "llvm/CodeGen/MachineInstr.h"
39 #include "llvm/CodeGen/MachineInstrBuilder.h"
40 #include "llvm/CodeGen/MachineJumpTableInfo.h"
41 #include "llvm/CodeGen/MachineMemOperand.h"
42 #include "llvm/CodeGen/MachineOperand.h"
43 #include "llvm/CodeGen/MachineRegisterInfo.h"
44 #include "llvm/CodeGen/RuntimeLibcalls.h"
45 #include "llvm/CodeGen/SelectionDAG.h"
46 #include "llvm/CodeGen/SelectionDAGNodes.h"
47 #include "llvm/CodeGen/TargetFrameLowering.h"
48 #include "llvm/CodeGen/TargetInstrInfo.h"
49 #include "llvm/CodeGen/TargetRegisterInfo.h"
50 #include "llvm/CodeGen/ValueTypes.h"
51 #include "llvm/IR/CallingConv.h"
52 #include "llvm/IR/Constants.h"
53 #include "llvm/IR/DataLayout.h"
54 #include "llvm/IR/DebugLoc.h"
55 #include "llvm/IR/DerivedTypes.h"
56 #include "llvm/IR/Function.h"
57 #include "llvm/IR/GlobalValue.h"
58 #include "llvm/IR/Type.h"
59 #include "llvm/IR/Value.h"
60 #include "llvm/MC/MCRegisterInfo.h"
61 #include "llvm/Support/Casting.h"
62 #include "llvm/Support/CodeGen.h"
63 #include "llvm/Support/CommandLine.h"
64 #include "llvm/Support/Compiler.h"
65 #include "llvm/Support/ErrorHandling.h"
66 #include "llvm/Support/MachineValueType.h"
67 #include "llvm/Support/MathExtras.h"
68 #include "llvm/Target/TargetMachine.h"
69 #include "llvm/Target/TargetOptions.h"
70 #include <algorithm>
71 #include <cassert>
72 #include <cctype>
73 #include <cstdint>
74 #include <deque>
75 #include <iterator>
76 #include <utility>
77 #include <vector>
78 
79 using namespace llvm;
80 
81 #define DEBUG_TYPE "mips-lower"
82 
83 STATISTIC(NumTailCalls, "Number of tail calls");
84 
85 static cl::opt<bool>
86 LargeGOT("mxgot", cl::Hidden,
87          cl::desc("MIPS: Enable GOT larger than 64k."), cl::init(false));
88 
89 static cl::opt<bool>
90 NoZeroDivCheck("mno-check-zero-division", cl::Hidden,
91                cl::desc("MIPS: Don't trap on integer division by zero."),
92                cl::init(false));
93 
94 static const MCPhysReg Mips64DPRegs[8] = {
95   Mips::D12_64, Mips::D13_64, Mips::D14_64, Mips::D15_64,
96   Mips::D16_64, Mips::D17_64, Mips::D18_64, Mips::D19_64
97 };
98 
99 // If I is a shifted mask, set the size (Size) and the first bit of the
100 // mask (Pos), and return true.
101 // For example, if I is 0x003ff800, (Pos, Size) = (11, 11).
102 static bool isShiftedMask(uint64_t I, uint64_t &Pos, uint64_t &Size) {
103   if (!isShiftedMask_64(I))
104     return false;
105 
106   Size = countPopulation(I);
107   Pos = countTrailingZeros(I);
108   return true;
109 }
110 
111 // The MIPS MSA ABI passes vector arguments in the integer register set.
112 // The number of integer registers used is dependant on the ABI used.
113 MVT MipsTargetLowering::getRegisterTypeForCallingConv(LLVMContext &Context,
114                                                       EVT VT) const {
115   if (VT.isVector()) {
116       if (Subtarget.isABI_O32()) {
117         return MVT::i32;
118       } else {
119         return (VT.getSizeInBits() == 32) ? MVT::i32 : MVT::i64;
120       }
121   }
122   return MipsTargetLowering::getRegisterType(Context, VT);
123 }
124 
125 unsigned MipsTargetLowering::getNumRegistersForCallingConv(LLVMContext &Context,
126                                                            EVT VT) const {
127   if (VT.isVector())
128     return std::max((VT.getSizeInBits() / (Subtarget.isABI_O32() ? 32 : 64)),
129                     1U);
130   return MipsTargetLowering::getNumRegisters(Context, VT);
131 }
132 
133 unsigned MipsTargetLowering::getVectorTypeBreakdownForCallingConv(
134     LLVMContext &Context, EVT VT, EVT &IntermediateVT,
135     unsigned &NumIntermediates, MVT &RegisterVT) const {
136   // Break down vector types to either 2 i64s or 4 i32s.
137   RegisterVT = getRegisterTypeForCallingConv(Context, VT) ;
138   IntermediateVT = RegisterVT;
139   NumIntermediates = VT.getSizeInBits() < RegisterVT.getSizeInBits()
140                          ? VT.getVectorNumElements()
141                          : VT.getSizeInBits() / RegisterVT.getSizeInBits();
142 
143   return NumIntermediates;
144 }
145 
146 SDValue MipsTargetLowering::getGlobalReg(SelectionDAG &DAG, EVT Ty) const {
147   MipsFunctionInfo *FI = DAG.getMachineFunction().getInfo<MipsFunctionInfo>();
148   return DAG.getRegister(FI->getGlobalBaseReg(), Ty);
149 }
150 
151 SDValue MipsTargetLowering::getTargetNode(GlobalAddressSDNode *N, EVT Ty,
152                                           SelectionDAG &DAG,
153                                           unsigned Flag) const {
154   return DAG.getTargetGlobalAddress(N->getGlobal(), SDLoc(N), Ty, 0, Flag);
155 }
156 
157 SDValue MipsTargetLowering::getTargetNode(ExternalSymbolSDNode *N, EVT Ty,
158                                           SelectionDAG &DAG,
159                                           unsigned Flag) const {
160   return DAG.getTargetExternalSymbol(N->getSymbol(), Ty, Flag);
161 }
162 
163 SDValue MipsTargetLowering::getTargetNode(BlockAddressSDNode *N, EVT Ty,
164                                           SelectionDAG &DAG,
165                                           unsigned Flag) const {
166   return DAG.getTargetBlockAddress(N->getBlockAddress(), Ty, 0, Flag);
167 }
168 
169 SDValue MipsTargetLowering::getTargetNode(JumpTableSDNode *N, EVT Ty,
170                                           SelectionDAG &DAG,
171                                           unsigned Flag) const {
172   return DAG.getTargetJumpTable(N->getIndex(), Ty, Flag);
173 }
174 
175 SDValue MipsTargetLowering::getTargetNode(ConstantPoolSDNode *N, EVT Ty,
176                                           SelectionDAG &DAG,
177                                           unsigned Flag) const {
178   return DAG.getTargetConstantPool(N->getConstVal(), Ty, N->getAlignment(),
179                                    N->getOffset(), Flag);
180 }
181 
182 const char *MipsTargetLowering::getTargetNodeName(unsigned Opcode) const {
183   switch ((MipsISD::NodeType)Opcode) {
184   case MipsISD::FIRST_NUMBER:      break;
185   case MipsISD::JmpLink:           return "MipsISD::JmpLink";
186   case MipsISD::TailCall:          return "MipsISD::TailCall";
187   case MipsISD::Highest:           return "MipsISD::Highest";
188   case MipsISD::Higher:            return "MipsISD::Higher";
189   case MipsISD::Hi:                return "MipsISD::Hi";
190   case MipsISD::Lo:                return "MipsISD::Lo";
191   case MipsISD::GotHi:             return "MipsISD::GotHi";
192   case MipsISD::GPRel:             return "MipsISD::GPRel";
193   case MipsISD::ThreadPointer:     return "MipsISD::ThreadPointer";
194   case MipsISD::Ret:               return "MipsISD::Ret";
195   case MipsISD::ERet:              return "MipsISD::ERet";
196   case MipsISD::EH_RETURN:         return "MipsISD::EH_RETURN";
197   case MipsISD::FMS:               return "MipsISD::FMS";
198   case MipsISD::FPBrcond:          return "MipsISD::FPBrcond";
199   case MipsISD::FPCmp:             return "MipsISD::FPCmp";
200   case MipsISD::FSELECT:           return "MipsISD::FSELECT";
201   case MipsISD::MTC1_D64:          return "MipsISD::MTC1_D64";
202   case MipsISD::CMovFP_T:          return "MipsISD::CMovFP_T";
203   case MipsISD::CMovFP_F:          return "MipsISD::CMovFP_F";
204   case MipsISD::TruncIntFP:        return "MipsISD::TruncIntFP";
205   case MipsISD::MFHI:              return "MipsISD::MFHI";
206   case MipsISD::MFLO:              return "MipsISD::MFLO";
207   case MipsISD::MTLOHI:            return "MipsISD::MTLOHI";
208   case MipsISD::Mult:              return "MipsISD::Mult";
209   case MipsISD::Multu:             return "MipsISD::Multu";
210   case MipsISD::MAdd:              return "MipsISD::MAdd";
211   case MipsISD::MAddu:             return "MipsISD::MAddu";
212   case MipsISD::MSub:              return "MipsISD::MSub";
213   case MipsISD::MSubu:             return "MipsISD::MSubu";
214   case MipsISD::DivRem:            return "MipsISD::DivRem";
215   case MipsISD::DivRemU:           return "MipsISD::DivRemU";
216   case MipsISD::DivRem16:          return "MipsISD::DivRem16";
217   case MipsISD::DivRemU16:         return "MipsISD::DivRemU16";
218   case MipsISD::BuildPairF64:      return "MipsISD::BuildPairF64";
219   case MipsISD::ExtractElementF64: return "MipsISD::ExtractElementF64";
220   case MipsISD::Wrapper:           return "MipsISD::Wrapper";
221   case MipsISD::DynAlloc:          return "MipsISD::DynAlloc";
222   case MipsISD::Sync:              return "MipsISD::Sync";
223   case MipsISD::Ext:               return "MipsISD::Ext";
224   case MipsISD::Ins:               return "MipsISD::Ins";
225   case MipsISD::CIns:              return "MipsISD::CIns";
226   case MipsISD::LWL:               return "MipsISD::LWL";
227   case MipsISD::LWR:               return "MipsISD::LWR";
228   case MipsISD::SWL:               return "MipsISD::SWL";
229   case MipsISD::SWR:               return "MipsISD::SWR";
230   case MipsISD::LDL:               return "MipsISD::LDL";
231   case MipsISD::LDR:               return "MipsISD::LDR";
232   case MipsISD::SDL:               return "MipsISD::SDL";
233   case MipsISD::SDR:               return "MipsISD::SDR";
234   case MipsISD::EXTP:              return "MipsISD::EXTP";
235   case MipsISD::EXTPDP:            return "MipsISD::EXTPDP";
236   case MipsISD::EXTR_S_H:          return "MipsISD::EXTR_S_H";
237   case MipsISD::EXTR_W:            return "MipsISD::EXTR_W";
238   case MipsISD::EXTR_R_W:          return "MipsISD::EXTR_R_W";
239   case MipsISD::EXTR_RS_W:         return "MipsISD::EXTR_RS_W";
240   case MipsISD::SHILO:             return "MipsISD::SHILO";
241   case MipsISD::MTHLIP:            return "MipsISD::MTHLIP";
242   case MipsISD::MULSAQ_S_W_PH:     return "MipsISD::MULSAQ_S_W_PH";
243   case MipsISD::MAQ_S_W_PHL:       return "MipsISD::MAQ_S_W_PHL";
244   case MipsISD::MAQ_S_W_PHR:       return "MipsISD::MAQ_S_W_PHR";
245   case MipsISD::MAQ_SA_W_PHL:      return "MipsISD::MAQ_SA_W_PHL";
246   case MipsISD::MAQ_SA_W_PHR:      return "MipsISD::MAQ_SA_W_PHR";
247   case MipsISD::DPAU_H_QBL:        return "MipsISD::DPAU_H_QBL";
248   case MipsISD::DPAU_H_QBR:        return "MipsISD::DPAU_H_QBR";
249   case MipsISD::DPSU_H_QBL:        return "MipsISD::DPSU_H_QBL";
250   case MipsISD::DPSU_H_QBR:        return "MipsISD::DPSU_H_QBR";
251   case MipsISD::DPAQ_S_W_PH:       return "MipsISD::DPAQ_S_W_PH";
252   case MipsISD::DPSQ_S_W_PH:       return "MipsISD::DPSQ_S_W_PH";
253   case MipsISD::DPAQ_SA_L_W:       return "MipsISD::DPAQ_SA_L_W";
254   case MipsISD::DPSQ_SA_L_W:       return "MipsISD::DPSQ_SA_L_W";
255   case MipsISD::DPA_W_PH:          return "MipsISD::DPA_W_PH";
256   case MipsISD::DPS_W_PH:          return "MipsISD::DPS_W_PH";
257   case MipsISD::DPAQX_S_W_PH:      return "MipsISD::DPAQX_S_W_PH";
258   case MipsISD::DPAQX_SA_W_PH:     return "MipsISD::DPAQX_SA_W_PH";
259   case MipsISD::DPAX_W_PH:         return "MipsISD::DPAX_W_PH";
260   case MipsISD::DPSX_W_PH:         return "MipsISD::DPSX_W_PH";
261   case MipsISD::DPSQX_S_W_PH:      return "MipsISD::DPSQX_S_W_PH";
262   case MipsISD::DPSQX_SA_W_PH:     return "MipsISD::DPSQX_SA_W_PH";
263   case MipsISD::MULSA_W_PH:        return "MipsISD::MULSA_W_PH";
264   case MipsISD::MULT:              return "MipsISD::MULT";
265   case MipsISD::MULTU:             return "MipsISD::MULTU";
266   case MipsISD::MADD_DSP:          return "MipsISD::MADD_DSP";
267   case MipsISD::MADDU_DSP:         return "MipsISD::MADDU_DSP";
268   case MipsISD::MSUB_DSP:          return "MipsISD::MSUB_DSP";
269   case MipsISD::MSUBU_DSP:         return "MipsISD::MSUBU_DSP";
270   case MipsISD::SHLL_DSP:          return "MipsISD::SHLL_DSP";
271   case MipsISD::SHRA_DSP:          return "MipsISD::SHRA_DSP";
272   case MipsISD::SHRL_DSP:          return "MipsISD::SHRL_DSP";
273   case MipsISD::SETCC_DSP:         return "MipsISD::SETCC_DSP";
274   case MipsISD::SELECT_CC_DSP:     return "MipsISD::SELECT_CC_DSP";
275   case MipsISD::VALL_ZERO:         return "MipsISD::VALL_ZERO";
276   case MipsISD::VANY_ZERO:         return "MipsISD::VANY_ZERO";
277   case MipsISD::VALL_NONZERO:      return "MipsISD::VALL_NONZERO";
278   case MipsISD::VANY_NONZERO:      return "MipsISD::VANY_NONZERO";
279   case MipsISD::VCEQ:              return "MipsISD::VCEQ";
280   case MipsISD::VCLE_S:            return "MipsISD::VCLE_S";
281   case MipsISD::VCLE_U:            return "MipsISD::VCLE_U";
282   case MipsISD::VCLT_S:            return "MipsISD::VCLT_S";
283   case MipsISD::VCLT_U:            return "MipsISD::VCLT_U";
284   case MipsISD::VEXTRACT_SEXT_ELT: return "MipsISD::VEXTRACT_SEXT_ELT";
285   case MipsISD::VEXTRACT_ZEXT_ELT: return "MipsISD::VEXTRACT_ZEXT_ELT";
286   case MipsISD::VNOR:              return "MipsISD::VNOR";
287   case MipsISD::VSHF:              return "MipsISD::VSHF";
288   case MipsISD::SHF:               return "MipsISD::SHF";
289   case MipsISD::ILVEV:             return "MipsISD::ILVEV";
290   case MipsISD::ILVOD:             return "MipsISD::ILVOD";
291   case MipsISD::ILVL:              return "MipsISD::ILVL";
292   case MipsISD::ILVR:              return "MipsISD::ILVR";
293   case MipsISD::PCKEV:             return "MipsISD::PCKEV";
294   case MipsISD::PCKOD:             return "MipsISD::PCKOD";
295   case MipsISD::INSVE:             return "MipsISD::INSVE";
296   }
297   return nullptr;
298 }
299 
300 MipsTargetLowering::MipsTargetLowering(const MipsTargetMachine &TM,
301                                        const MipsSubtarget &STI)
302     : TargetLowering(TM), Subtarget(STI), ABI(TM.getABI()) {
303   // Mips does not have i1 type, so use i32 for
304   // setcc operations results (slt, sgt, ...).
305   setBooleanContents(ZeroOrOneBooleanContent);
306   setBooleanVectorContents(ZeroOrNegativeOneBooleanContent);
307   // The cmp.cond.fmt instruction in MIPS32r6/MIPS64r6 uses 0 and -1 like MSA
308   // does. Integer booleans still use 0 and 1.
309   if (Subtarget.hasMips32r6())
310     setBooleanContents(ZeroOrOneBooleanContent,
311                        ZeroOrNegativeOneBooleanContent);
312 
313   // Load extented operations for i1 types must be promoted
314   for (MVT VT : MVT::integer_valuetypes()) {
315     setLoadExtAction(ISD::EXTLOAD,  VT, MVT::i1,  Promote);
316     setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i1,  Promote);
317     setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i1,  Promote);
318   }
319 
320   // MIPS doesn't have extending float->double load/store.  Set LoadExtAction
321   // for f32, f16
322   for (MVT VT : MVT::fp_valuetypes()) {
323     setLoadExtAction(ISD::EXTLOAD, VT, MVT::f32, Expand);
324     setLoadExtAction(ISD::EXTLOAD, VT, MVT::f16, Expand);
325   }
326 
327   // Set LoadExtAction for f16 vectors to Expand
328   for (MVT VT : MVT::fp_vector_valuetypes()) {
329     MVT F16VT = MVT::getVectorVT(MVT::f16, VT.getVectorNumElements());
330     if (F16VT.isValid())
331       setLoadExtAction(ISD::EXTLOAD, VT, F16VT, Expand);
332   }
333 
334   setTruncStoreAction(MVT::f32, MVT::f16, Expand);
335   setTruncStoreAction(MVT::f64, MVT::f16, Expand);
336 
337   setTruncStoreAction(MVT::f64, MVT::f32, Expand);
338 
339   // Used by legalize types to correctly generate the setcc result.
340   // Without this, every float setcc comes with a AND/OR with the result,
341   // we don't want this, since the fpcmp result goes to a flag register,
342   // which is used implicitly by brcond and select operations.
343   AddPromotedToType(ISD::SETCC, MVT::i1, MVT::i32);
344 
345   // Mips Custom Operations
346   setOperationAction(ISD::BR_JT,              MVT::Other, Expand);
347   setOperationAction(ISD::GlobalAddress,      MVT::i32,   Custom);
348   setOperationAction(ISD::BlockAddress,       MVT::i32,   Custom);
349   setOperationAction(ISD::GlobalTLSAddress,   MVT::i32,   Custom);
350   setOperationAction(ISD::JumpTable,          MVT::i32,   Custom);
351   setOperationAction(ISD::ConstantPool,       MVT::i32,   Custom);
352   setOperationAction(ISD::SELECT,             MVT::f32,   Custom);
353   setOperationAction(ISD::SELECT,             MVT::f64,   Custom);
354   setOperationAction(ISD::SELECT,             MVT::i32,   Custom);
355   setOperationAction(ISD::SETCC,              MVT::f32,   Custom);
356   setOperationAction(ISD::SETCC,              MVT::f64,   Custom);
357   setOperationAction(ISD::BRCOND,             MVT::Other, Custom);
358   setOperationAction(ISD::FCOPYSIGN,          MVT::f32,   Custom);
359   setOperationAction(ISD::FCOPYSIGN,          MVT::f64,   Custom);
360   setOperationAction(ISD::FP_TO_SINT,         MVT::i32,   Custom);
361 
362   if (Subtarget.isGP64bit()) {
363     setOperationAction(ISD::GlobalAddress,      MVT::i64,   Custom);
364     setOperationAction(ISD::BlockAddress,       MVT::i64,   Custom);
365     setOperationAction(ISD::GlobalTLSAddress,   MVT::i64,   Custom);
366     setOperationAction(ISD::JumpTable,          MVT::i64,   Custom);
367     setOperationAction(ISD::ConstantPool,       MVT::i64,   Custom);
368     setOperationAction(ISD::SELECT,             MVT::i64,   Custom);
369     setOperationAction(ISD::LOAD,               MVT::i64,   Custom);
370     setOperationAction(ISD::STORE,              MVT::i64,   Custom);
371     setOperationAction(ISD::FP_TO_SINT,         MVT::i64,   Custom);
372     setOperationAction(ISD::SHL_PARTS,          MVT::i64,   Custom);
373     setOperationAction(ISD::SRA_PARTS,          MVT::i64,   Custom);
374     setOperationAction(ISD::SRL_PARTS,          MVT::i64,   Custom);
375   }
376 
377   if (!Subtarget.isGP64bit()) {
378     setOperationAction(ISD::SHL_PARTS,          MVT::i32,   Custom);
379     setOperationAction(ISD::SRA_PARTS,          MVT::i32,   Custom);
380     setOperationAction(ISD::SRL_PARTS,          MVT::i32,   Custom);
381   }
382 
383   setOperationAction(ISD::EH_DWARF_CFA,         MVT::i32,   Custom);
384   if (Subtarget.isGP64bit())
385     setOperationAction(ISD::EH_DWARF_CFA,       MVT::i64,   Custom);
386 
387   setOperationAction(ISD::SDIV, MVT::i32, Expand);
388   setOperationAction(ISD::SREM, MVT::i32, Expand);
389   setOperationAction(ISD::UDIV, MVT::i32, Expand);
390   setOperationAction(ISD::UREM, MVT::i32, Expand);
391   setOperationAction(ISD::SDIV, MVT::i64, Expand);
392   setOperationAction(ISD::SREM, MVT::i64, Expand);
393   setOperationAction(ISD::UDIV, MVT::i64, Expand);
394   setOperationAction(ISD::UREM, MVT::i64, Expand);
395 
396   if (!(Subtarget.hasDSP() && Subtarget.hasMips32r2())) {
397     setOperationAction(ISD::ADDC, MVT::i32, Expand);
398     setOperationAction(ISD::ADDE, MVT::i32, Expand);
399   }
400 
401   setOperationAction(ISD::ADDC, MVT::i64, Expand);
402   setOperationAction(ISD::ADDE, MVT::i64, Expand);
403   setOperationAction(ISD::SUBC, MVT::i32, Expand);
404   setOperationAction(ISD::SUBE, MVT::i32, Expand);
405   setOperationAction(ISD::SUBC, MVT::i64, Expand);
406   setOperationAction(ISD::SUBE, MVT::i64, Expand);
407 
408   // Operations not directly supported by Mips.
409   setOperationAction(ISD::BR_CC,             MVT::f32,   Expand);
410   setOperationAction(ISD::BR_CC,             MVT::f64,   Expand);
411   setOperationAction(ISD::BR_CC,             MVT::i32,   Expand);
412   setOperationAction(ISD::BR_CC,             MVT::i64,   Expand);
413   setOperationAction(ISD::SELECT_CC,         MVT::i32,   Expand);
414   setOperationAction(ISD::SELECT_CC,         MVT::i64,   Expand);
415   setOperationAction(ISD::SELECT_CC,         MVT::f32,   Expand);
416   setOperationAction(ISD::SELECT_CC,         MVT::f64,   Expand);
417   setOperationAction(ISD::UINT_TO_FP,        MVT::i32,   Expand);
418   setOperationAction(ISD::UINT_TO_FP,        MVT::i64,   Expand);
419   setOperationAction(ISD::FP_TO_UINT,        MVT::i32,   Expand);
420   setOperationAction(ISD::FP_TO_UINT,        MVT::i64,   Expand);
421   setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1,    Expand);
422   if (Subtarget.hasCnMips()) {
423     setOperationAction(ISD::CTPOP,           MVT::i32,   Legal);
424     setOperationAction(ISD::CTPOP,           MVT::i64,   Legal);
425   } else {
426     setOperationAction(ISD::CTPOP,           MVT::i32,   Expand);
427     setOperationAction(ISD::CTPOP,           MVT::i64,   Expand);
428   }
429   setOperationAction(ISD::CTTZ,              MVT::i32,   Expand);
430   setOperationAction(ISD::CTTZ,              MVT::i64,   Expand);
431   setOperationAction(ISD::ROTL,              MVT::i32,   Expand);
432   setOperationAction(ISD::ROTL,              MVT::i64,   Expand);
433   setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32,  Expand);
434   setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64,  Expand);
435 
436   if (!Subtarget.hasMips32r2())
437     setOperationAction(ISD::ROTR, MVT::i32,   Expand);
438 
439   if (!Subtarget.hasMips64r2())
440     setOperationAction(ISD::ROTR, MVT::i64,   Expand);
441 
442   setOperationAction(ISD::FSIN,              MVT::f32,   Expand);
443   setOperationAction(ISD::FSIN,              MVT::f64,   Expand);
444   setOperationAction(ISD::FCOS,              MVT::f32,   Expand);
445   setOperationAction(ISD::FCOS,              MVT::f64,   Expand);
446   setOperationAction(ISD::FSINCOS,           MVT::f32,   Expand);
447   setOperationAction(ISD::FSINCOS,           MVT::f64,   Expand);
448   setOperationAction(ISD::FPOW,              MVT::f32,   Expand);
449   setOperationAction(ISD::FPOW,              MVT::f64,   Expand);
450   setOperationAction(ISD::FLOG,              MVT::f32,   Expand);
451   setOperationAction(ISD::FLOG2,             MVT::f32,   Expand);
452   setOperationAction(ISD::FLOG10,            MVT::f32,   Expand);
453   setOperationAction(ISD::FEXP,              MVT::f32,   Expand);
454   setOperationAction(ISD::FMA,               MVT::f32,   Expand);
455   setOperationAction(ISD::FMA,               MVT::f64,   Expand);
456   setOperationAction(ISD::FREM,              MVT::f32,   Expand);
457   setOperationAction(ISD::FREM,              MVT::f64,   Expand);
458 
459   // Lower f16 conversion operations into library calls
460   setOperationAction(ISD::FP16_TO_FP,        MVT::f32,   Expand);
461   setOperationAction(ISD::FP_TO_FP16,        MVT::f32,   Expand);
462   setOperationAction(ISD::FP16_TO_FP,        MVT::f64,   Expand);
463   setOperationAction(ISD::FP_TO_FP16,        MVT::f64,   Expand);
464 
465   setOperationAction(ISD::EH_RETURN, MVT::Other, Custom);
466 
467   setOperationAction(ISD::VASTART,           MVT::Other, Custom);
468   setOperationAction(ISD::VAARG,             MVT::Other, Custom);
469   setOperationAction(ISD::VACOPY,            MVT::Other, Expand);
470   setOperationAction(ISD::VAEND,             MVT::Other, Expand);
471 
472   // Use the default for now
473   setOperationAction(ISD::STACKSAVE,         MVT::Other, Expand);
474   setOperationAction(ISD::STACKRESTORE,      MVT::Other, Expand);
475 
476   if (!Subtarget.isGP64bit()) {
477     setOperationAction(ISD::ATOMIC_LOAD,     MVT::i64,   Expand);
478     setOperationAction(ISD::ATOMIC_STORE,    MVT::i64,   Expand);
479   }
480 
481   if (!Subtarget.hasMips32r2()) {
482     setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8,  Expand);
483     setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand);
484   }
485 
486   // MIPS16 lacks MIPS32's clz and clo instructions.
487   if (!Subtarget.hasMips32() || Subtarget.inMips16Mode())
488     setOperationAction(ISD::CTLZ, MVT::i32, Expand);
489   if (!Subtarget.hasMips64())
490     setOperationAction(ISD::CTLZ, MVT::i64, Expand);
491 
492   if (!Subtarget.hasMips32r2())
493     setOperationAction(ISD::BSWAP, MVT::i32, Expand);
494   if (!Subtarget.hasMips64r2())
495     setOperationAction(ISD::BSWAP, MVT::i64, Expand);
496 
497   if (Subtarget.isGP64bit()) {
498     setLoadExtAction(ISD::SEXTLOAD, MVT::i64, MVT::i32, Custom);
499     setLoadExtAction(ISD::ZEXTLOAD, MVT::i64, MVT::i32, Custom);
500     setLoadExtAction(ISD::EXTLOAD, MVT::i64, MVT::i32, Custom);
501     setTruncStoreAction(MVT::i64, MVT::i32, Custom);
502   }
503 
504   setOperationAction(ISD::TRAP, MVT::Other, Legal);
505 
506   setTargetDAGCombine(ISD::SDIVREM);
507   setTargetDAGCombine(ISD::UDIVREM);
508   setTargetDAGCombine(ISD::SELECT);
509   setTargetDAGCombine(ISD::AND);
510   setTargetDAGCombine(ISD::OR);
511   setTargetDAGCombine(ISD::ADD);
512   setTargetDAGCombine(ISD::SUB);
513   setTargetDAGCombine(ISD::AssertZext);
514   setTargetDAGCombine(ISD::SHL);
515 
516   if (ABI.IsO32()) {
517     // These libcalls are not available in 32-bit.
518     setLibcallName(RTLIB::SHL_I128, nullptr);
519     setLibcallName(RTLIB::SRL_I128, nullptr);
520     setLibcallName(RTLIB::SRA_I128, nullptr);
521   }
522 
523   setMinFunctionAlignment(Subtarget.isGP64bit() ? 3 : 2);
524 
525   // The arguments on the stack are defined in terms of 4-byte slots on O32
526   // and 8-byte slots on N32/N64.
527   setMinStackArgumentAlignment((ABI.IsN32() || ABI.IsN64()) ? 8 : 4);
528 
529   setStackPointerRegisterToSaveRestore(ABI.IsN64() ? Mips::SP_64 : Mips::SP);
530 
531   MaxStoresPerMemcpy = 16;
532 
533   isMicroMips = Subtarget.inMicroMipsMode();
534 }
535 
536 const MipsTargetLowering *MipsTargetLowering::create(const MipsTargetMachine &TM,
537                                                      const MipsSubtarget &STI) {
538   if (STI.inMips16Mode())
539     return createMips16TargetLowering(TM, STI);
540 
541   return createMipsSETargetLowering(TM, STI);
542 }
543 
544 // Create a fast isel object.
545 FastISel *
546 MipsTargetLowering::createFastISel(FunctionLoweringInfo &funcInfo,
547                                   const TargetLibraryInfo *libInfo) const {
548   const MipsTargetMachine &TM =
549       static_cast<const MipsTargetMachine &>(funcInfo.MF->getTarget());
550 
551   // We support only the standard encoding [MIPS32,MIPS32R5] ISAs.
552   bool UseFastISel = TM.Options.EnableFastISel && Subtarget.hasMips32() &&
553                      !Subtarget.hasMips32r6() && !Subtarget.inMips16Mode() &&
554                      !Subtarget.inMicroMipsMode();
555 
556   // Disable if either of the following is true:
557   // We do not generate PIC, the ABI is not O32, LargeGOT is being used.
558   if (!TM.isPositionIndependent() || !TM.getABI().IsO32() || LargeGOT)
559     UseFastISel = false;
560 
561   return UseFastISel ? Mips::createFastISel(funcInfo, libInfo) : nullptr;
562 }
563 
564 EVT MipsTargetLowering::getSetCCResultType(const DataLayout &, LLVMContext &,
565                                            EVT VT) const {
566   if (!VT.isVector())
567     return MVT::i32;
568   return VT.changeVectorElementTypeToInteger();
569 }
570 
571 static SDValue performDivRemCombine(SDNode *N, SelectionDAG &DAG,
572                                     TargetLowering::DAGCombinerInfo &DCI,
573                                     const MipsSubtarget &Subtarget) {
574   if (DCI.isBeforeLegalizeOps())
575     return SDValue();
576 
577   EVT Ty = N->getValueType(0);
578   unsigned LO = (Ty == MVT::i32) ? Mips::LO0 : Mips::LO0_64;
579   unsigned HI = (Ty == MVT::i32) ? Mips::HI0 : Mips::HI0_64;
580   unsigned Opc = N->getOpcode() == ISD::SDIVREM ? MipsISD::DivRem16 :
581                                                   MipsISD::DivRemU16;
582   SDLoc DL(N);
583 
584   SDValue DivRem = DAG.getNode(Opc, DL, MVT::Glue,
585                                N->getOperand(0), N->getOperand(1));
586   SDValue InChain = DAG.getEntryNode();
587   SDValue InGlue = DivRem;
588 
589   // insert MFLO
590   if (N->hasAnyUseOfValue(0)) {
591     SDValue CopyFromLo = DAG.getCopyFromReg(InChain, DL, LO, Ty,
592                                             InGlue);
593     DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), CopyFromLo);
594     InChain = CopyFromLo.getValue(1);
595     InGlue = CopyFromLo.getValue(2);
596   }
597 
598   // insert MFHI
599   if (N->hasAnyUseOfValue(1)) {
600     SDValue CopyFromHi = DAG.getCopyFromReg(InChain, DL,
601                                             HI, Ty, InGlue);
602     DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), CopyFromHi);
603   }
604 
605   return SDValue();
606 }
607 
608 static Mips::CondCode condCodeToFCC(ISD::CondCode CC) {
609   switch (CC) {
610   default: llvm_unreachable("Unknown fp condition code!");
611   case ISD::SETEQ:
612   case ISD::SETOEQ: return Mips::FCOND_OEQ;
613   case ISD::SETUNE: return Mips::FCOND_UNE;
614   case ISD::SETLT:
615   case ISD::SETOLT: return Mips::FCOND_OLT;
616   case ISD::SETGT:
617   case ISD::SETOGT: return Mips::FCOND_OGT;
618   case ISD::SETLE:
619   case ISD::SETOLE: return Mips::FCOND_OLE;
620   case ISD::SETGE:
621   case ISD::SETOGE: return Mips::FCOND_OGE;
622   case ISD::SETULT: return Mips::FCOND_ULT;
623   case ISD::SETULE: return Mips::FCOND_ULE;
624   case ISD::SETUGT: return Mips::FCOND_UGT;
625   case ISD::SETUGE: return Mips::FCOND_UGE;
626   case ISD::SETUO:  return Mips::FCOND_UN;
627   case ISD::SETO:   return Mips::FCOND_OR;
628   case ISD::SETNE:
629   case ISD::SETONE: return Mips::FCOND_ONE;
630   case ISD::SETUEQ: return Mips::FCOND_UEQ;
631   }
632 }
633 
634 /// This function returns true if the floating point conditional branches and
635 /// conditional moves which use condition code CC should be inverted.
636 static bool invertFPCondCodeUser(Mips::CondCode CC) {
637   if (CC >= Mips::FCOND_F && CC <= Mips::FCOND_NGT)
638     return false;
639 
640   assert((CC >= Mips::FCOND_T && CC <= Mips::FCOND_GT) &&
641          "Illegal Condition Code");
642 
643   return true;
644 }
645 
646 // Creates and returns an FPCmp node from a setcc node.
647 // Returns Op if setcc is not a floating point comparison.
648 static SDValue createFPCmp(SelectionDAG &DAG, const SDValue &Op) {
649   // must be a SETCC node
650   if (Op.getOpcode() != ISD::SETCC)
651     return Op;
652 
653   SDValue LHS = Op.getOperand(0);
654 
655   if (!LHS.getValueType().isFloatingPoint())
656     return Op;
657 
658   SDValue RHS = Op.getOperand(1);
659   SDLoc DL(Op);
660 
661   // Assume the 3rd operand is a CondCodeSDNode. Add code to check the type of
662   // node if necessary.
663   ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
664 
665   return DAG.getNode(MipsISD::FPCmp, DL, MVT::Glue, LHS, RHS,
666                      DAG.getConstant(condCodeToFCC(CC), DL, MVT::i32));
667 }
668 
669 // Creates and returns a CMovFPT/F node.
670 static SDValue createCMovFP(SelectionDAG &DAG, SDValue Cond, SDValue True,
671                             SDValue False, const SDLoc &DL) {
672   ConstantSDNode *CC = cast<ConstantSDNode>(Cond.getOperand(2));
673   bool invert = invertFPCondCodeUser((Mips::CondCode)CC->getSExtValue());
674   SDValue FCC0 = DAG.getRegister(Mips::FCC0, MVT::i32);
675 
676   return DAG.getNode((invert ? MipsISD::CMovFP_F : MipsISD::CMovFP_T), DL,
677                      True.getValueType(), True, FCC0, False, Cond);
678 }
679 
680 static SDValue performSELECTCombine(SDNode *N, SelectionDAG &DAG,
681                                     TargetLowering::DAGCombinerInfo &DCI,
682                                     const MipsSubtarget &Subtarget) {
683   if (DCI.isBeforeLegalizeOps())
684     return SDValue();
685 
686   SDValue SetCC = N->getOperand(0);
687 
688   if ((SetCC.getOpcode() != ISD::SETCC) ||
689       !SetCC.getOperand(0).getValueType().isInteger())
690     return SDValue();
691 
692   SDValue False = N->getOperand(2);
693   EVT FalseTy = False.getValueType();
694 
695   if (!FalseTy.isInteger())
696     return SDValue();
697 
698   ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(False);
699 
700   // If the RHS (False) is 0, we swap the order of the operands
701   // of ISD::SELECT (obviously also inverting the condition) so that we can
702   // take advantage of conditional moves using the $0 register.
703   // Example:
704   //   return (a != 0) ? x : 0;
705   //     load $reg, x
706   //     movz $reg, $0, a
707   if (!FalseC)
708     return SDValue();
709 
710   const SDLoc DL(N);
711 
712   if (!FalseC->getZExtValue()) {
713     ISD::CondCode CC = cast<CondCodeSDNode>(SetCC.getOperand(2))->get();
714     SDValue True = N->getOperand(1);
715 
716     SetCC = DAG.getSetCC(DL, SetCC.getValueType(), SetCC.getOperand(0),
717                          SetCC.getOperand(1), ISD::getSetCCInverse(CC, true));
718 
719     return DAG.getNode(ISD::SELECT, DL, FalseTy, SetCC, False, True);
720   }
721 
722   // If both operands are integer constants there's a possibility that we
723   // can do some interesting optimizations.
724   SDValue True = N->getOperand(1);
725   ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(True);
726 
727   if (!TrueC || !True.getValueType().isInteger())
728     return SDValue();
729 
730   // We'll also ignore MVT::i64 operands as this optimizations proves
731   // to be ineffective because of the required sign extensions as the result
732   // of a SETCC operator is always MVT::i32 for non-vector types.
733   if (True.getValueType() == MVT::i64)
734     return SDValue();
735 
736   int64_t Diff = TrueC->getSExtValue() - FalseC->getSExtValue();
737 
738   // 1)  (a < x) ? y : y-1
739   //  slti $reg1, a, x
740   //  addiu $reg2, $reg1, y-1
741   if (Diff == 1)
742     return DAG.getNode(ISD::ADD, DL, SetCC.getValueType(), SetCC, False);
743 
744   // 2)  (a < x) ? y-1 : y
745   //  slti $reg1, a, x
746   //  xor $reg1, $reg1, 1
747   //  addiu $reg2, $reg1, y-1
748   if (Diff == -1) {
749     ISD::CondCode CC = cast<CondCodeSDNode>(SetCC.getOperand(2))->get();
750     SetCC = DAG.getSetCC(DL, SetCC.getValueType(), SetCC.getOperand(0),
751                          SetCC.getOperand(1), ISD::getSetCCInverse(CC, true));
752     return DAG.getNode(ISD::ADD, DL, SetCC.getValueType(), SetCC, True);
753   }
754 
755   // Couldn't optimize.
756   return SDValue();
757 }
758 
759 static SDValue performCMovFPCombine(SDNode *N, SelectionDAG &DAG,
760                                     TargetLowering::DAGCombinerInfo &DCI,
761                                     const MipsSubtarget &Subtarget) {
762   if (DCI.isBeforeLegalizeOps())
763     return SDValue();
764 
765   SDValue ValueIfTrue = N->getOperand(0), ValueIfFalse = N->getOperand(2);
766 
767   ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(ValueIfFalse);
768   if (!FalseC || FalseC->getZExtValue())
769     return SDValue();
770 
771   // Since RHS (False) is 0, we swap the order of the True/False operands
772   // (obviously also inverting the condition) so that we can
773   // take advantage of conditional moves using the $0 register.
774   // Example:
775   //   return (a != 0) ? x : 0;
776   //     load $reg, x
777   //     movz $reg, $0, a
778   unsigned Opc = (N->getOpcode() == MipsISD::CMovFP_T) ? MipsISD::CMovFP_F :
779                                                          MipsISD::CMovFP_T;
780 
781   SDValue FCC = N->getOperand(1), Glue = N->getOperand(3);
782   return DAG.getNode(Opc, SDLoc(N), ValueIfFalse.getValueType(),
783                      ValueIfFalse, FCC, ValueIfTrue, Glue);
784 }
785 
786 static SDValue performANDCombine(SDNode *N, SelectionDAG &DAG,
787                                  TargetLowering::DAGCombinerInfo &DCI,
788                                  const MipsSubtarget &Subtarget) {
789   if (DCI.isBeforeLegalizeOps() || !Subtarget.hasExtractInsert())
790     return SDValue();
791 
792   SDValue FirstOperand = N->getOperand(0);
793   unsigned FirstOperandOpc = FirstOperand.getOpcode();
794   SDValue Mask = N->getOperand(1);
795   EVT ValTy = N->getValueType(0);
796   SDLoc DL(N);
797 
798   uint64_t Pos = 0, SMPos, SMSize;
799   ConstantSDNode *CN;
800   SDValue NewOperand;
801   unsigned Opc;
802 
803   // Op's second operand must be a shifted mask.
804   if (!(CN = dyn_cast<ConstantSDNode>(Mask)) ||
805       !isShiftedMask(CN->getZExtValue(), SMPos, SMSize))
806     return SDValue();
807 
808   if (FirstOperandOpc == ISD::SRA || FirstOperandOpc == ISD::SRL) {
809     // Pattern match EXT.
810     //  $dst = and ((sra or srl) $src , pos), (2**size - 1)
811     //  => ext $dst, $src, pos, size
812 
813     // The second operand of the shift must be an immediate.
814     if (!(CN = dyn_cast<ConstantSDNode>(FirstOperand.getOperand(1))))
815       return SDValue();
816 
817     Pos = CN->getZExtValue();
818 
819     // Return if the shifted mask does not start at bit 0 or the sum of its size
820     // and Pos exceeds the word's size.
821     if (SMPos != 0 || Pos + SMSize > ValTy.getSizeInBits())
822       return SDValue();
823 
824     Opc = MipsISD::Ext;
825     NewOperand = FirstOperand.getOperand(0);
826   } else if (FirstOperandOpc == ISD::SHL && Subtarget.hasCnMips()) {
827     // Pattern match CINS.
828     //  $dst = and (shl $src , pos), mask
829     //  => cins $dst, $src, pos, size
830     // mask is a shifted mask with consecutive 1's, pos = shift amount,
831     // size = population count.
832 
833     // The second operand of the shift must be an immediate.
834     if (!(CN = dyn_cast<ConstantSDNode>(FirstOperand.getOperand(1))))
835       return SDValue();
836 
837     Pos = CN->getZExtValue();
838 
839     if (SMPos != Pos || Pos >= ValTy.getSizeInBits() || SMSize >= 32 ||
840         Pos + SMSize > ValTy.getSizeInBits())
841       return SDValue();
842 
843     NewOperand = FirstOperand.getOperand(0);
844     // SMSize is 'location' (position) in this case, not size.
845     SMSize--;
846     Opc = MipsISD::CIns;
847   } else {
848     // Pattern match EXT.
849     //  $dst = and $src, (2**size - 1) , if size > 16
850     //  => ext $dst, $src, pos, size , pos = 0
851 
852     // If the mask is <= 0xffff, andi can be used instead.
853     if (CN->getZExtValue() <= 0xffff)
854       return SDValue();
855 
856     // Return if the mask doesn't start at position 0.
857     if (SMPos)
858       return SDValue();
859 
860     Opc = MipsISD::Ext;
861     NewOperand = FirstOperand;
862   }
863   return DAG.getNode(Opc, DL, ValTy, NewOperand,
864                      DAG.getConstant(Pos, DL, MVT::i32),
865                      DAG.getConstant(SMSize, DL, MVT::i32));
866 }
867 
868 static SDValue performORCombine(SDNode *N, SelectionDAG &DAG,
869                                 TargetLowering::DAGCombinerInfo &DCI,
870                                 const MipsSubtarget &Subtarget) {
871   // Pattern match INS.
872   //  $dst = or (and $src1 , mask0), (and (shl $src, pos), mask1),
873   //  where mask1 = (2**size - 1) << pos, mask0 = ~mask1
874   //  => ins $dst, $src, size, pos, $src1
875   if (DCI.isBeforeLegalizeOps() || !Subtarget.hasExtractInsert())
876     return SDValue();
877 
878   SDValue And0 = N->getOperand(0), And1 = N->getOperand(1);
879   uint64_t SMPos0, SMSize0, SMPos1, SMSize1;
880   ConstantSDNode *CN, *CN1;
881 
882   // See if Op's first operand matches (and $src1 , mask0).
883   if (And0.getOpcode() != ISD::AND)
884     return SDValue();
885 
886   if (!(CN = dyn_cast<ConstantSDNode>(And0.getOperand(1))) ||
887       !isShiftedMask(~CN->getSExtValue(), SMPos0, SMSize0))
888     return SDValue();
889 
890   // See if Op's second operand matches (and (shl $src, pos), mask1).
891   if (And1.getOpcode() == ISD::AND &&
892       And1.getOperand(0).getOpcode() == ISD::SHL) {
893 
894     if (!(CN = dyn_cast<ConstantSDNode>(And1.getOperand(1))) ||
895         !isShiftedMask(CN->getZExtValue(), SMPos1, SMSize1))
896       return SDValue();
897 
898     // The shift masks must have the same position and size.
899     if (SMPos0 != SMPos1 || SMSize0 != SMSize1)
900       return SDValue();
901 
902     SDValue Shl = And1.getOperand(0);
903 
904     if (!(CN = dyn_cast<ConstantSDNode>(Shl.getOperand(1))))
905       return SDValue();
906 
907     unsigned Shamt = CN->getZExtValue();
908 
909     // Return if the shift amount and the first bit position of mask are not the
910     // same.
911     EVT ValTy = N->getValueType(0);
912     if ((Shamt != SMPos0) || (SMPos0 + SMSize0 > ValTy.getSizeInBits()))
913       return SDValue();
914 
915     SDLoc DL(N);
916     return DAG.getNode(MipsISD::Ins, DL, ValTy, Shl.getOperand(0),
917                        DAG.getConstant(SMPos0, DL, MVT::i32),
918                        DAG.getConstant(SMSize0, DL, MVT::i32),
919                        And0.getOperand(0));
920   } else {
921     // Pattern match DINS.
922     //  $dst = or (and $src, mask0), mask1
923     //  where mask0 = ((1 << SMSize0) -1) << SMPos0
924     //  => dins $dst, $src, pos, size
925     if (~CN->getSExtValue() == ((((int64_t)1 << SMSize0) - 1) << SMPos0) &&
926         ((SMSize0 + SMPos0 <= 64 && Subtarget.hasMips64r2()) ||
927          (SMSize0 + SMPos0 <= 32))) {
928       // Check if AND instruction has constant as argument
929       bool isConstCase = And1.getOpcode() != ISD::AND;
930       if (And1.getOpcode() == ISD::AND) {
931         if (!(CN1 = dyn_cast<ConstantSDNode>(And1->getOperand(1))))
932           return SDValue();
933       } else {
934         if (!(CN1 = dyn_cast<ConstantSDNode>(N->getOperand(1))))
935           return SDValue();
936       }
937       // Don't generate INS if constant OR operand doesn't fit into bits
938       // cleared by constant AND operand.
939       if (CN->getSExtValue() & CN1->getSExtValue())
940         return SDValue();
941 
942       SDLoc DL(N);
943       EVT ValTy = N->getOperand(0)->getValueType(0);
944       SDValue Const1;
945       SDValue SrlX;
946       if (!isConstCase) {
947         Const1 = DAG.getConstant(SMPos0, DL, MVT::i32);
948         SrlX = DAG.getNode(ISD::SRL, DL, And1->getValueType(0), And1, Const1);
949       }
950       return DAG.getNode(
951           MipsISD::Ins, DL, N->getValueType(0),
952           isConstCase
953               ? DAG.getConstant(CN1->getSExtValue() >> SMPos0, DL, ValTy)
954               : SrlX,
955           DAG.getConstant(SMPos0, DL, MVT::i32),
956           DAG.getConstant(ValTy.getSizeInBits() / 8 < 8 ? SMSize0 & 31
957                                                         : SMSize0,
958                           DL, MVT::i32),
959           And0->getOperand(0));
960 
961     }
962     return SDValue();
963   }
964 }
965 
966 static SDValue performMADD_MSUBCombine(SDNode *ROOTNode, SelectionDAG &CurDAG,
967                                        const MipsSubtarget &Subtarget) {
968   // ROOTNode must have a multiplication as an operand for the match to be
969   // successful.
970   if (ROOTNode->getOperand(0).getOpcode() != ISD::MUL &&
971       ROOTNode->getOperand(1).getOpcode() != ISD::MUL)
972     return SDValue();
973 
974   // We don't handle vector types here.
975   if (ROOTNode->getValueType(0).isVector())
976     return SDValue();
977 
978   // For MIPS64, madd / msub instructions are inefficent to use with 64 bit
979   // arithmetic. E.g.
980   // (add (mul a b) c) =>
981   //   let res = (madd (mthi (drotr c 32))x(mtlo c) a b) in
982   //   MIPS64:   (or (dsll (mfhi res) 32) (dsrl (dsll (mflo res) 32) 32)
983   //   or
984   //   MIPS64R2: (dins (mflo res) (mfhi res) 32 32)
985   //
986   // The overhead of setting up the Hi/Lo registers and reassembling the
987   // result makes this a dubious optimzation for MIPS64. The core of the
988   // problem is that Hi/Lo contain the upper and lower 32 bits of the
989   // operand and result.
990   //
991   // It requires a chain of 4 add/mul for MIPS64R2 to get better code
992   // density than doing it naively, 5 for MIPS64. Additionally, using
993   // madd/msub on MIPS64 requires the operands actually be 32 bit sign
994   // extended operands, not true 64 bit values.
995   //
996   // FIXME: For the moment, disable this completely for MIPS64.
997   if (Subtarget.hasMips64())
998     return SDValue();
999 
1000   SDValue Mult = ROOTNode->getOperand(0).getOpcode() == ISD::MUL
1001                      ? ROOTNode->getOperand(0)
1002                      : ROOTNode->getOperand(1);
1003 
1004   SDValue AddOperand = ROOTNode->getOperand(0).getOpcode() == ISD::MUL
1005                      ? ROOTNode->getOperand(1)
1006                      : ROOTNode->getOperand(0);
1007 
1008   // Transform this to a MADD only if the user of this node is the add.
1009   // If there are other users of the mul, this function returns here.
1010   if (!Mult.hasOneUse())
1011     return SDValue();
1012 
1013   // maddu and madd are unusual instructions in that on MIPS64 bits 63..31
1014   // must be in canonical form, i.e. sign extended. For MIPS32, the operands
1015   // of the multiply must have 32 or more sign bits, otherwise we cannot
1016   // perform this optimization. We have to check this here as we're performing
1017   // this optimization pre-legalization.
1018   SDValue MultLHS = Mult->getOperand(0);
1019   SDValue MultRHS = Mult->getOperand(1);
1020 
1021   bool IsSigned = MultLHS->getOpcode() == ISD::SIGN_EXTEND &&
1022                   MultRHS->getOpcode() == ISD::SIGN_EXTEND;
1023   bool IsUnsigned = MultLHS->getOpcode() == ISD::ZERO_EXTEND &&
1024                     MultRHS->getOpcode() == ISD::ZERO_EXTEND;
1025 
1026   if (!IsSigned && !IsUnsigned)
1027     return SDValue();
1028 
1029   // Initialize accumulator.
1030   SDLoc DL(ROOTNode);
1031   SDValue TopHalf;
1032   SDValue BottomHalf;
1033   BottomHalf = CurDAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32, AddOperand,
1034                               CurDAG.getIntPtrConstant(0, DL));
1035 
1036   TopHalf = CurDAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32, AddOperand,
1037                            CurDAG.getIntPtrConstant(1, DL));
1038   SDValue ACCIn = CurDAG.getNode(MipsISD::MTLOHI, DL, MVT::Untyped,
1039                                   BottomHalf,
1040                                   TopHalf);
1041 
1042   // Create MipsMAdd(u) / MipsMSub(u) node.
1043   bool IsAdd = ROOTNode->getOpcode() == ISD::ADD;
1044   unsigned Opcode = IsAdd ? (IsUnsigned ? MipsISD::MAddu : MipsISD::MAdd)
1045                           : (IsUnsigned ? MipsISD::MSubu : MipsISD::MSub);
1046   SDValue MAddOps[3] = {
1047       CurDAG.getNode(ISD::TRUNCATE, DL, MVT::i32, Mult->getOperand(0)),
1048       CurDAG.getNode(ISD::TRUNCATE, DL, MVT::i32, Mult->getOperand(1)), ACCIn};
1049   EVT VTs[2] = {MVT::i32, MVT::i32};
1050   SDValue MAdd = CurDAG.getNode(Opcode, DL, VTs, MAddOps);
1051 
1052   SDValue ResLo = CurDAG.getNode(MipsISD::MFLO, DL, MVT::i32, MAdd);
1053   SDValue ResHi = CurDAG.getNode(MipsISD::MFHI, DL, MVT::i32, MAdd);
1054   SDValue Combined =
1055       CurDAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, ResLo, ResHi);
1056   return Combined;
1057 }
1058 
1059 static SDValue performSUBCombine(SDNode *N, SelectionDAG &DAG,
1060                                  TargetLowering::DAGCombinerInfo &DCI,
1061                                  const MipsSubtarget &Subtarget) {
1062   // (sub v0 (mul v1, v2)) => (msub v1, v2, v0)
1063   if (DCI.isBeforeLegalizeOps()) {
1064     if (Subtarget.hasMips32() && !Subtarget.hasMips32r6() &&
1065         !Subtarget.inMips16Mode() && N->getValueType(0) == MVT::i64)
1066       return performMADD_MSUBCombine(N, DAG, Subtarget);
1067 
1068     return SDValue();
1069   }
1070 
1071   return SDValue();
1072 }
1073 
1074 static SDValue performADDCombine(SDNode *N, SelectionDAG &DAG,
1075                                  TargetLowering::DAGCombinerInfo &DCI,
1076                                  const MipsSubtarget &Subtarget) {
1077   // (add v0 (mul v1, v2)) => (madd v1, v2, v0)
1078   if (DCI.isBeforeLegalizeOps()) {
1079     if (Subtarget.hasMips32() && !Subtarget.hasMips32r6() &&
1080         !Subtarget.inMips16Mode() && N->getValueType(0) == MVT::i64)
1081       return performMADD_MSUBCombine(N, DAG, Subtarget);
1082 
1083     return SDValue();
1084   }
1085 
1086   // (add v0, (add v1, abs_lo(tjt))) => (add (add v0, v1), abs_lo(tjt))
1087   SDValue Add = N->getOperand(1);
1088 
1089   if (Add.getOpcode() != ISD::ADD)
1090     return SDValue();
1091 
1092   SDValue Lo = Add.getOperand(1);
1093 
1094   if ((Lo.getOpcode() != MipsISD::Lo) ||
1095       (Lo.getOperand(0).getOpcode() != ISD::TargetJumpTable))
1096     return SDValue();
1097 
1098   EVT ValTy = N->getValueType(0);
1099   SDLoc DL(N);
1100 
1101   SDValue Add1 = DAG.getNode(ISD::ADD, DL, ValTy, N->getOperand(0),
1102                              Add.getOperand(0));
1103   return DAG.getNode(ISD::ADD, DL, ValTy, Add1, Lo);
1104 }
1105 
1106 static SDValue performSHLCombine(SDNode *N, SelectionDAG &DAG,
1107                                  TargetLowering::DAGCombinerInfo &DCI,
1108                                  const MipsSubtarget &Subtarget) {
1109   // Pattern match CINS.
1110   //  $dst = shl (and $src , imm), pos
1111   //  => cins $dst, $src, pos, size
1112 
1113   if (DCI.isBeforeLegalizeOps() || !Subtarget.hasCnMips())
1114     return SDValue();
1115 
1116   SDValue FirstOperand = N->getOperand(0);
1117   unsigned FirstOperandOpc = FirstOperand.getOpcode();
1118   SDValue SecondOperand = N->getOperand(1);
1119   EVT ValTy = N->getValueType(0);
1120   SDLoc DL(N);
1121 
1122   uint64_t Pos = 0, SMPos, SMSize;
1123   ConstantSDNode *CN;
1124   SDValue NewOperand;
1125 
1126   // The second operand of the shift must be an immediate.
1127   if (!(CN = dyn_cast<ConstantSDNode>(SecondOperand)))
1128     return SDValue();
1129 
1130   Pos = CN->getZExtValue();
1131 
1132   if (Pos >= ValTy.getSizeInBits())
1133     return SDValue();
1134 
1135   if (FirstOperandOpc != ISD::AND)
1136     return SDValue();
1137 
1138   // AND's second operand must be a shifted mask.
1139   if (!(CN = dyn_cast<ConstantSDNode>(FirstOperand.getOperand(1))) ||
1140       !isShiftedMask(CN->getZExtValue(), SMPos, SMSize))
1141     return SDValue();
1142 
1143   // Return if the shifted mask does not start at bit 0 or the sum of its size
1144   // and Pos exceeds the word's size.
1145   if (SMPos != 0 || SMSize > 32 || Pos + SMSize > ValTy.getSizeInBits())
1146     return SDValue();
1147 
1148   NewOperand = FirstOperand.getOperand(0);
1149   // SMSize is 'location' (position) in this case, not size.
1150   SMSize--;
1151 
1152   return DAG.getNode(MipsISD::CIns, DL, ValTy, NewOperand,
1153                      DAG.getConstant(Pos, DL, MVT::i32),
1154                      DAG.getConstant(SMSize, DL, MVT::i32));
1155 }
1156 
1157 SDValue  MipsTargetLowering::PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI)
1158   const {
1159   SelectionDAG &DAG = DCI.DAG;
1160   unsigned Opc = N->getOpcode();
1161 
1162   switch (Opc) {
1163   default: break;
1164   case ISD::SDIVREM:
1165   case ISD::UDIVREM:
1166     return performDivRemCombine(N, DAG, DCI, Subtarget);
1167   case ISD::SELECT:
1168     return performSELECTCombine(N, DAG, DCI, Subtarget);
1169   case MipsISD::CMovFP_F:
1170   case MipsISD::CMovFP_T:
1171     return performCMovFPCombine(N, DAG, DCI, Subtarget);
1172   case ISD::AND:
1173     return performANDCombine(N, DAG, DCI, Subtarget);
1174   case ISD::OR:
1175     return performORCombine(N, DAG, DCI, Subtarget);
1176   case ISD::ADD:
1177     return performADDCombine(N, DAG, DCI, Subtarget);
1178   case ISD::SHL:
1179     return performSHLCombine(N, DAG, DCI, Subtarget);
1180   case ISD::SUB:
1181     return performSUBCombine(N, DAG, DCI, Subtarget);
1182   }
1183 
1184   return SDValue();
1185 }
1186 
1187 bool MipsTargetLowering::isCheapToSpeculateCttz() const {
1188   return Subtarget.hasMips32();
1189 }
1190 
1191 bool MipsTargetLowering::isCheapToSpeculateCtlz() const {
1192   return Subtarget.hasMips32();
1193 }
1194 
1195 void
1196 MipsTargetLowering::LowerOperationWrapper(SDNode *N,
1197                                           SmallVectorImpl<SDValue> &Results,
1198                                           SelectionDAG &DAG) const {
1199   SDValue Res = LowerOperation(SDValue(N, 0), DAG);
1200 
1201   for (unsigned I = 0, E = Res->getNumValues(); I != E; ++I)
1202     Results.push_back(Res.getValue(I));
1203 }
1204 
1205 void
1206 MipsTargetLowering::ReplaceNodeResults(SDNode *N,
1207                                        SmallVectorImpl<SDValue> &Results,
1208                                        SelectionDAG &DAG) const {
1209   return LowerOperationWrapper(N, Results, DAG);
1210 }
1211 
1212 SDValue MipsTargetLowering::
1213 LowerOperation(SDValue Op, SelectionDAG &DAG) const
1214 {
1215   switch (Op.getOpcode())
1216   {
1217   case ISD::BRCOND:             return lowerBRCOND(Op, DAG);
1218   case ISD::ConstantPool:       return lowerConstantPool(Op, DAG);
1219   case ISD::GlobalAddress:      return lowerGlobalAddress(Op, DAG);
1220   case ISD::BlockAddress:       return lowerBlockAddress(Op, DAG);
1221   case ISD::GlobalTLSAddress:   return lowerGlobalTLSAddress(Op, DAG);
1222   case ISD::JumpTable:          return lowerJumpTable(Op, DAG);
1223   case ISD::SELECT:             return lowerSELECT(Op, DAG);
1224   case ISD::SETCC:              return lowerSETCC(Op, DAG);
1225   case ISD::VASTART:            return lowerVASTART(Op, DAG);
1226   case ISD::VAARG:              return lowerVAARG(Op, DAG);
1227   case ISD::FCOPYSIGN:          return lowerFCOPYSIGN(Op, DAG);
1228   case ISD::FRAMEADDR:          return lowerFRAMEADDR(Op, DAG);
1229   case ISD::RETURNADDR:         return lowerRETURNADDR(Op, DAG);
1230   case ISD::EH_RETURN:          return lowerEH_RETURN(Op, DAG);
1231   case ISD::ATOMIC_FENCE:       return lowerATOMIC_FENCE(Op, DAG);
1232   case ISD::SHL_PARTS:          return lowerShiftLeftParts(Op, DAG);
1233   case ISD::SRA_PARTS:          return lowerShiftRightParts(Op, DAG, true);
1234   case ISD::SRL_PARTS:          return lowerShiftRightParts(Op, DAG, false);
1235   case ISD::LOAD:               return lowerLOAD(Op, DAG);
1236   case ISD::STORE:              return lowerSTORE(Op, DAG);
1237   case ISD::EH_DWARF_CFA:       return lowerEH_DWARF_CFA(Op, DAG);
1238   case ISD::FP_TO_SINT:         return lowerFP_TO_SINT(Op, DAG);
1239   }
1240   return SDValue();
1241 }
1242 
1243 //===----------------------------------------------------------------------===//
1244 //  Lower helper functions
1245 //===----------------------------------------------------------------------===//
1246 
1247 // addLiveIn - This helper function adds the specified physical register to the
1248 // MachineFunction as a live in value.  It also creates a corresponding
1249 // virtual register for it.
1250 static unsigned
1251 addLiveIn(MachineFunction &MF, unsigned PReg, const TargetRegisterClass *RC)
1252 {
1253   unsigned VReg = MF.getRegInfo().createVirtualRegister(RC);
1254   MF.getRegInfo().addLiveIn(PReg, VReg);
1255   return VReg;
1256 }
1257 
1258 static MachineBasicBlock *insertDivByZeroTrap(MachineInstr &MI,
1259                                               MachineBasicBlock &MBB,
1260                                               const TargetInstrInfo &TII,
1261                                               bool Is64Bit, bool IsMicroMips) {
1262   if (NoZeroDivCheck)
1263     return &MBB;
1264 
1265   // Insert instruction "teq $divisor_reg, $zero, 7".
1266   MachineBasicBlock::iterator I(MI);
1267   MachineInstrBuilder MIB;
1268   MachineOperand &Divisor = MI.getOperand(2);
1269   MIB = BuildMI(MBB, std::next(I), MI.getDebugLoc(),
1270                 TII.get(IsMicroMips ? Mips::TEQ_MM : Mips::TEQ))
1271             .addReg(Divisor.getReg(), getKillRegState(Divisor.isKill()))
1272             .addReg(Mips::ZERO)
1273             .addImm(7);
1274 
1275   // Use the 32-bit sub-register if this is a 64-bit division.
1276   if (Is64Bit)
1277     MIB->getOperand(0).setSubReg(Mips::sub_32);
1278 
1279   // Clear Divisor's kill flag.
1280   Divisor.setIsKill(false);
1281 
1282   // We would normally delete the original instruction here but in this case
1283   // we only needed to inject an additional instruction rather than replace it.
1284 
1285   return &MBB;
1286 }
1287 
1288 MachineBasicBlock *
1289 MipsTargetLowering::EmitInstrWithCustomInserter(MachineInstr &MI,
1290                                                 MachineBasicBlock *BB) const {
1291   switch (MI.getOpcode()) {
1292   default:
1293     llvm_unreachable("Unexpected instr type to insert");
1294   case Mips::ATOMIC_LOAD_ADD_I8:
1295     return emitAtomicBinaryPartword(MI, BB, 1, Mips::ADDu);
1296   case Mips::ATOMIC_LOAD_ADD_I16:
1297     return emitAtomicBinaryPartword(MI, BB, 2, Mips::ADDu);
1298   case Mips::ATOMIC_LOAD_ADD_I32:
1299     return emitAtomicBinary(MI, BB, 4, Mips::ADDu);
1300   case Mips::ATOMIC_LOAD_ADD_I64:
1301     return emitAtomicBinary(MI, BB, 8, Mips::DADDu);
1302 
1303   case Mips::ATOMIC_LOAD_AND_I8:
1304     return emitAtomicBinaryPartword(MI, BB, 1, Mips::AND);
1305   case Mips::ATOMIC_LOAD_AND_I16:
1306     return emitAtomicBinaryPartword(MI, BB, 2, Mips::AND);
1307   case Mips::ATOMIC_LOAD_AND_I32:
1308     return emitAtomicBinary(MI, BB, 4, Mips::AND);
1309   case Mips::ATOMIC_LOAD_AND_I64:
1310     return emitAtomicBinary(MI, BB, 8, Mips::AND64);
1311 
1312   case Mips::ATOMIC_LOAD_OR_I8:
1313     return emitAtomicBinaryPartword(MI, BB, 1, Mips::OR);
1314   case Mips::ATOMIC_LOAD_OR_I16:
1315     return emitAtomicBinaryPartword(MI, BB, 2, Mips::OR);
1316   case Mips::ATOMIC_LOAD_OR_I32:
1317     return emitAtomicBinary(MI, BB, 4, Mips::OR);
1318   case Mips::ATOMIC_LOAD_OR_I64:
1319     return emitAtomicBinary(MI, BB, 8, Mips::OR64);
1320 
1321   case Mips::ATOMIC_LOAD_XOR_I8:
1322     return emitAtomicBinaryPartword(MI, BB, 1, Mips::XOR);
1323   case Mips::ATOMIC_LOAD_XOR_I16:
1324     return emitAtomicBinaryPartword(MI, BB, 2, Mips::XOR);
1325   case Mips::ATOMIC_LOAD_XOR_I32:
1326     return emitAtomicBinary(MI, BB, 4, Mips::XOR);
1327   case Mips::ATOMIC_LOAD_XOR_I64:
1328     return emitAtomicBinary(MI, BB, 8, Mips::XOR64);
1329 
1330   case Mips::ATOMIC_LOAD_NAND_I8:
1331     return emitAtomicBinaryPartword(MI, BB, 1, 0, true);
1332   case Mips::ATOMIC_LOAD_NAND_I16:
1333     return emitAtomicBinaryPartword(MI, BB, 2, 0, true);
1334   case Mips::ATOMIC_LOAD_NAND_I32:
1335     return emitAtomicBinary(MI, BB, 4, 0, true);
1336   case Mips::ATOMIC_LOAD_NAND_I64:
1337     return emitAtomicBinary(MI, BB, 8, 0, true);
1338 
1339   case Mips::ATOMIC_LOAD_SUB_I8:
1340     return emitAtomicBinaryPartword(MI, BB, 1, Mips::SUBu);
1341   case Mips::ATOMIC_LOAD_SUB_I16:
1342     return emitAtomicBinaryPartword(MI, BB, 2, Mips::SUBu);
1343   case Mips::ATOMIC_LOAD_SUB_I32:
1344     return emitAtomicBinary(MI, BB, 4, Mips::SUBu);
1345   case Mips::ATOMIC_LOAD_SUB_I64:
1346     return emitAtomicBinary(MI, BB, 8, Mips::DSUBu);
1347 
1348   case Mips::ATOMIC_SWAP_I8:
1349     return emitAtomicBinaryPartword(MI, BB, 1, 0);
1350   case Mips::ATOMIC_SWAP_I16:
1351     return emitAtomicBinaryPartword(MI, BB, 2, 0);
1352   case Mips::ATOMIC_SWAP_I32:
1353     return emitAtomicBinary(MI, BB, 4, 0);
1354   case Mips::ATOMIC_SWAP_I64:
1355     return emitAtomicBinary(MI, BB, 8, 0);
1356 
1357   case Mips::ATOMIC_CMP_SWAP_I8:
1358     return emitAtomicCmpSwapPartword(MI, BB, 1);
1359   case Mips::ATOMIC_CMP_SWAP_I16:
1360     return emitAtomicCmpSwapPartword(MI, BB, 2);
1361   case Mips::ATOMIC_CMP_SWAP_I32:
1362     return emitAtomicCmpSwap(MI, BB, 4);
1363   case Mips::ATOMIC_CMP_SWAP_I64:
1364     return emitAtomicCmpSwap(MI, BB, 8);
1365   case Mips::PseudoSDIV:
1366   case Mips::PseudoUDIV:
1367   case Mips::DIV:
1368   case Mips::DIVU:
1369   case Mips::MOD:
1370   case Mips::MODU:
1371     return insertDivByZeroTrap(MI, *BB, *Subtarget.getInstrInfo(), false,
1372                                false);
1373   case Mips::SDIV_MM_Pseudo:
1374   case Mips::UDIV_MM_Pseudo:
1375   case Mips::SDIV_MM:
1376   case Mips::UDIV_MM:
1377   case Mips::DIV_MMR6:
1378   case Mips::DIVU_MMR6:
1379   case Mips::MOD_MMR6:
1380   case Mips::MODU_MMR6:
1381     return insertDivByZeroTrap(MI, *BB, *Subtarget.getInstrInfo(), false, true);
1382   case Mips::PseudoDSDIV:
1383   case Mips::PseudoDUDIV:
1384   case Mips::DDIV:
1385   case Mips::DDIVU:
1386   case Mips::DMOD:
1387   case Mips::DMODU:
1388     return insertDivByZeroTrap(MI, *BB, *Subtarget.getInstrInfo(), true, false);
1389 
1390   case Mips::PseudoSELECT_I:
1391   case Mips::PseudoSELECT_I64:
1392   case Mips::PseudoSELECT_S:
1393   case Mips::PseudoSELECT_D32:
1394   case Mips::PseudoSELECT_D64:
1395     return emitPseudoSELECT(MI, BB, false, Mips::BNE);
1396   case Mips::PseudoSELECTFP_F_I:
1397   case Mips::PseudoSELECTFP_F_I64:
1398   case Mips::PseudoSELECTFP_F_S:
1399   case Mips::PseudoSELECTFP_F_D32:
1400   case Mips::PseudoSELECTFP_F_D64:
1401     return emitPseudoSELECT(MI, BB, true, Mips::BC1F);
1402   case Mips::PseudoSELECTFP_T_I:
1403   case Mips::PseudoSELECTFP_T_I64:
1404   case Mips::PseudoSELECTFP_T_S:
1405   case Mips::PseudoSELECTFP_T_D32:
1406   case Mips::PseudoSELECTFP_T_D64:
1407     return emitPseudoSELECT(MI, BB, true, Mips::BC1T);
1408   }
1409 }
1410 
1411 // This function also handles Mips::ATOMIC_SWAP_I32 (when BinOpcode == 0), and
1412 // Mips::ATOMIC_LOAD_NAND_I32 (when Nand == true)
1413 MachineBasicBlock *MipsTargetLowering::emitAtomicBinary(MachineInstr &MI,
1414                                                         MachineBasicBlock *BB,
1415                                                         unsigned Size,
1416                                                         unsigned BinOpcode,
1417                                                         bool Nand) const {
1418   assert((Size == 4 || Size == 8) && "Unsupported size for EmitAtomicBinary.");
1419 
1420   MachineFunction *MF = BB->getParent();
1421   MachineRegisterInfo &RegInfo = MF->getRegInfo();
1422   const TargetRegisterClass *RC = getRegClassFor(MVT::getIntegerVT(Size * 8));
1423   const TargetInstrInfo *TII = Subtarget.getInstrInfo();
1424   const bool ArePtrs64bit = ABI.ArePtrs64bit();
1425   DebugLoc DL = MI.getDebugLoc();
1426   unsigned LL, SC, AND, NOR, ZERO, BEQ;
1427 
1428   if (Size == 4) {
1429     if (isMicroMips) {
1430       LL = Subtarget.hasMips32r6() ? Mips::LL_MMR6 : Mips::LL_MM;
1431       SC = Subtarget.hasMips32r6() ? Mips::SC_MMR6 : Mips::SC_MM;
1432     } else {
1433       LL = Subtarget.hasMips32r6()
1434                ? (ArePtrs64bit ? Mips::LL64_R6 : Mips::LL_R6)
1435                : (ArePtrs64bit ? Mips::LL64 : Mips::LL);
1436       SC = Subtarget.hasMips32r6()
1437                ? (ArePtrs64bit ? Mips::SC64_R6 : Mips::SC_R6)
1438                : (ArePtrs64bit ? Mips::SC64 : Mips::SC);
1439     }
1440 
1441     AND = Mips::AND;
1442     NOR = Mips::NOR;
1443     ZERO = Mips::ZERO;
1444     BEQ = Mips::BEQ;
1445   } else {
1446     LL = Subtarget.hasMips64r6() ? Mips::LLD_R6 : Mips::LLD;
1447     SC = Subtarget.hasMips64r6() ? Mips::SCD_R6 : Mips::SCD;
1448     AND = Mips::AND64;
1449     NOR = Mips::NOR64;
1450     ZERO = Mips::ZERO_64;
1451     BEQ = Mips::BEQ64;
1452   }
1453 
1454   unsigned OldVal = MI.getOperand(0).getReg();
1455   unsigned Ptr = MI.getOperand(1).getReg();
1456   unsigned Incr = MI.getOperand(2).getReg();
1457 
1458   unsigned StoreVal = RegInfo.createVirtualRegister(RC);
1459   unsigned AndRes = RegInfo.createVirtualRegister(RC);
1460   unsigned Success = RegInfo.createVirtualRegister(RC);
1461 
1462   // insert new blocks after the current block
1463   const BasicBlock *LLVM_BB = BB->getBasicBlock();
1464   MachineBasicBlock *loopMBB = MF->CreateMachineBasicBlock(LLVM_BB);
1465   MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB);
1466   MachineFunction::iterator It = ++BB->getIterator();
1467   MF->insert(It, loopMBB);
1468   MF->insert(It, exitMBB);
1469 
1470   // Transfer the remainder of BB and its successor edges to exitMBB.
1471   exitMBB->splice(exitMBB->begin(), BB,
1472                   std::next(MachineBasicBlock::iterator(MI)), BB->end());
1473   exitMBB->transferSuccessorsAndUpdatePHIs(BB);
1474 
1475   //  thisMBB:
1476   //    ...
1477   //    fallthrough --> loopMBB
1478   BB->addSuccessor(loopMBB);
1479   loopMBB->addSuccessor(loopMBB);
1480   loopMBB->addSuccessor(exitMBB);
1481 
1482   //  loopMBB:
1483   //    ll oldval, 0(ptr)
1484   //    <binop> storeval, oldval, incr
1485   //    sc success, storeval, 0(ptr)
1486   //    beq success, $0, loopMBB
1487   BB = loopMBB;
1488   BuildMI(BB, DL, TII->get(LL), OldVal).addReg(Ptr).addImm(0);
1489   if (Nand) {
1490     //  and andres, oldval, incr
1491     //  nor storeval, $0, andres
1492     BuildMI(BB, DL, TII->get(AND), AndRes).addReg(OldVal).addReg(Incr);
1493     BuildMI(BB, DL, TII->get(NOR), StoreVal).addReg(ZERO).addReg(AndRes);
1494   } else if (BinOpcode) {
1495     //  <binop> storeval, oldval, incr
1496     BuildMI(BB, DL, TII->get(BinOpcode), StoreVal).addReg(OldVal).addReg(Incr);
1497   } else {
1498     StoreVal = Incr;
1499   }
1500   BuildMI(BB, DL, TII->get(SC), Success).addReg(StoreVal).addReg(Ptr).addImm(0);
1501   BuildMI(BB, DL, TII->get(BEQ)).addReg(Success).addReg(ZERO).addMBB(loopMBB);
1502 
1503   MI.eraseFromParent(); // The instruction is gone now.
1504 
1505   return exitMBB;
1506 }
1507 
1508 MachineBasicBlock *MipsTargetLowering::emitSignExtendToI32InReg(
1509     MachineInstr &MI, MachineBasicBlock *BB, unsigned Size, unsigned DstReg,
1510     unsigned SrcReg) const {
1511   const TargetInstrInfo *TII = Subtarget.getInstrInfo();
1512   const DebugLoc &DL = MI.getDebugLoc();
1513 
1514   if (Subtarget.hasMips32r2() && Size == 1) {
1515     BuildMI(BB, DL, TII->get(Mips::SEB), DstReg).addReg(SrcReg);
1516     return BB;
1517   }
1518 
1519   if (Subtarget.hasMips32r2() && Size == 2) {
1520     BuildMI(BB, DL, TII->get(Mips::SEH), DstReg).addReg(SrcReg);
1521     return BB;
1522   }
1523 
1524   MachineFunction *MF = BB->getParent();
1525   MachineRegisterInfo &RegInfo = MF->getRegInfo();
1526   const TargetRegisterClass *RC = getRegClassFor(MVT::i32);
1527   unsigned ScrReg = RegInfo.createVirtualRegister(RC);
1528 
1529   assert(Size < 32);
1530   int64_t ShiftImm = 32 - (Size * 8);
1531 
1532   BuildMI(BB, DL, TII->get(Mips::SLL), ScrReg).addReg(SrcReg).addImm(ShiftImm);
1533   BuildMI(BB, DL, TII->get(Mips::SRA), DstReg).addReg(ScrReg).addImm(ShiftImm);
1534 
1535   return BB;
1536 }
1537 
1538 MachineBasicBlock *MipsTargetLowering::emitAtomicBinaryPartword(
1539     MachineInstr &MI, MachineBasicBlock *BB, unsigned Size, unsigned BinOpcode,
1540     bool Nand) const {
1541   assert((Size == 1 || Size == 2) &&
1542          "Unsupported size for EmitAtomicBinaryPartial.");
1543 
1544   MachineFunction *MF = BB->getParent();
1545   MachineRegisterInfo &RegInfo = MF->getRegInfo();
1546   const TargetRegisterClass *RC = getRegClassFor(MVT::i32);
1547   const bool ArePtrs64bit = ABI.ArePtrs64bit();
1548   const TargetRegisterClass *RCp =
1549     getRegClassFor(ArePtrs64bit ? MVT::i64 : MVT::i32);
1550   const TargetInstrInfo *TII = Subtarget.getInstrInfo();
1551   DebugLoc DL = MI.getDebugLoc();
1552 
1553   unsigned Dest = MI.getOperand(0).getReg();
1554   unsigned Ptr = MI.getOperand(1).getReg();
1555   unsigned Incr = MI.getOperand(2).getReg();
1556 
1557   unsigned AlignedAddr = RegInfo.createVirtualRegister(RCp);
1558   unsigned ShiftAmt = RegInfo.createVirtualRegister(RC);
1559   unsigned Mask = RegInfo.createVirtualRegister(RC);
1560   unsigned Mask2 = RegInfo.createVirtualRegister(RC);
1561   unsigned NewVal = RegInfo.createVirtualRegister(RC);
1562   unsigned OldVal = RegInfo.createVirtualRegister(RC);
1563   unsigned Incr2 = RegInfo.createVirtualRegister(RC);
1564   unsigned MaskLSB2 = RegInfo.createVirtualRegister(RCp);
1565   unsigned PtrLSB2 = RegInfo.createVirtualRegister(RC);
1566   unsigned MaskUpper = RegInfo.createVirtualRegister(RC);
1567   unsigned AndRes = RegInfo.createVirtualRegister(RC);
1568   unsigned BinOpRes = RegInfo.createVirtualRegister(RC);
1569   unsigned MaskedOldVal0 = RegInfo.createVirtualRegister(RC);
1570   unsigned StoreVal = RegInfo.createVirtualRegister(RC);
1571   unsigned MaskedOldVal1 = RegInfo.createVirtualRegister(RC);
1572   unsigned SrlRes = RegInfo.createVirtualRegister(RC);
1573   unsigned Success = RegInfo.createVirtualRegister(RC);
1574 
1575   unsigned LL, SC;
1576   if (isMicroMips) {
1577     LL = Subtarget.hasMips32r6() ? Mips::LL_MMR6 : Mips::LL_MM;
1578     SC = Subtarget.hasMips32r6() ? Mips::SC_MMR6 : Mips::SC_MM;
1579   } else {
1580     LL = Subtarget.hasMips32r6() ? (ArePtrs64bit ? Mips::LL64_R6 : Mips::LL_R6)
1581                                  : (ArePtrs64bit ? Mips::LL64 : Mips::LL);
1582     SC = Subtarget.hasMips32r6() ? (ArePtrs64bit ? Mips::SC64_R6 : Mips::SC_R6)
1583                                  : (ArePtrs64bit ? Mips::SC64 : Mips::SC);
1584   }
1585 
1586   // insert new blocks after the current block
1587   const BasicBlock *LLVM_BB = BB->getBasicBlock();
1588   MachineBasicBlock *loopMBB = MF->CreateMachineBasicBlock(LLVM_BB);
1589   MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(LLVM_BB);
1590   MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB);
1591   MachineFunction::iterator It = ++BB->getIterator();
1592   MF->insert(It, loopMBB);
1593   MF->insert(It, sinkMBB);
1594   MF->insert(It, exitMBB);
1595 
1596   // Transfer the remainder of BB and its successor edges to exitMBB.
1597   exitMBB->splice(exitMBB->begin(), BB,
1598                   std::next(MachineBasicBlock::iterator(MI)), BB->end());
1599   exitMBB->transferSuccessorsAndUpdatePHIs(BB);
1600 
1601   BB->addSuccessor(loopMBB);
1602   loopMBB->addSuccessor(loopMBB);
1603   loopMBB->addSuccessor(sinkMBB);
1604   sinkMBB->addSuccessor(exitMBB);
1605 
1606   //  thisMBB:
1607   //    addiu   masklsb2,$0,-4                # 0xfffffffc
1608   //    and     alignedaddr,ptr,masklsb2
1609   //    andi    ptrlsb2,ptr,3
1610   //    sll     shiftamt,ptrlsb2,3
1611   //    ori     maskupper,$0,255               # 0xff
1612   //    sll     mask,maskupper,shiftamt
1613   //    nor     mask2,$0,mask
1614   //    sll     incr2,incr,shiftamt
1615 
1616   int64_t MaskImm = (Size == 1) ? 255 : 65535;
1617   BuildMI(BB, DL, TII->get(ABI.GetPtrAddiuOp()), MaskLSB2)
1618     .addReg(ABI.GetNullPtr()).addImm(-4);
1619   BuildMI(BB, DL, TII->get(ABI.GetPtrAndOp()), AlignedAddr)
1620     .addReg(Ptr).addReg(MaskLSB2);
1621   BuildMI(BB, DL, TII->get(Mips::ANDi), PtrLSB2)
1622       .addReg(Ptr, 0, ArePtrs64bit ? Mips::sub_32 : 0).addImm(3);
1623   if (Subtarget.isLittle()) {
1624     BuildMI(BB, DL, TII->get(Mips::SLL), ShiftAmt).addReg(PtrLSB2).addImm(3);
1625   } else {
1626     unsigned Off = RegInfo.createVirtualRegister(RC);
1627     BuildMI(BB, DL, TII->get(Mips::XORi), Off)
1628       .addReg(PtrLSB2).addImm((Size == 1) ? 3 : 2);
1629     BuildMI(BB, DL, TII->get(Mips::SLL), ShiftAmt).addReg(Off).addImm(3);
1630   }
1631   BuildMI(BB, DL, TII->get(Mips::ORi), MaskUpper)
1632     .addReg(Mips::ZERO).addImm(MaskImm);
1633   BuildMI(BB, DL, TII->get(Mips::SLLV), Mask)
1634     .addReg(MaskUpper).addReg(ShiftAmt);
1635   BuildMI(BB, DL, TII->get(Mips::NOR), Mask2).addReg(Mips::ZERO).addReg(Mask);
1636   BuildMI(BB, DL, TII->get(Mips::SLLV), Incr2).addReg(Incr).addReg(ShiftAmt);
1637 
1638   // atomic.load.binop
1639   // loopMBB:
1640   //   ll      oldval,0(alignedaddr)
1641   //   binop   binopres,oldval,incr2
1642   //   and     newval,binopres,mask
1643   //   and     maskedoldval0,oldval,mask2
1644   //   or      storeval,maskedoldval0,newval
1645   //   sc      success,storeval,0(alignedaddr)
1646   //   beq     success,$0,loopMBB
1647 
1648   // atomic.swap
1649   // loopMBB:
1650   //   ll      oldval,0(alignedaddr)
1651   //   and     newval,incr2,mask
1652   //   and     maskedoldval0,oldval,mask2
1653   //   or      storeval,maskedoldval0,newval
1654   //   sc      success,storeval,0(alignedaddr)
1655   //   beq     success,$0,loopMBB
1656 
1657   BB = loopMBB;
1658   BuildMI(BB, DL, TII->get(LL), OldVal).addReg(AlignedAddr).addImm(0);
1659   if (Nand) {
1660     //  and andres, oldval, incr2
1661     //  nor binopres, $0, andres
1662     //  and newval, binopres, mask
1663     BuildMI(BB, DL, TII->get(Mips::AND), AndRes).addReg(OldVal).addReg(Incr2);
1664     BuildMI(BB, DL, TII->get(Mips::NOR), BinOpRes)
1665       .addReg(Mips::ZERO).addReg(AndRes);
1666     BuildMI(BB, DL, TII->get(Mips::AND), NewVal).addReg(BinOpRes).addReg(Mask);
1667   } else if (BinOpcode) {
1668     //  <binop> binopres, oldval, incr2
1669     //  and newval, binopres, mask
1670     BuildMI(BB, DL, TII->get(BinOpcode), BinOpRes).addReg(OldVal).addReg(Incr2);
1671     BuildMI(BB, DL, TII->get(Mips::AND), NewVal).addReg(BinOpRes).addReg(Mask);
1672   } else { // atomic.swap
1673     //  and newval, incr2, mask
1674     BuildMI(BB, DL, TII->get(Mips::AND), NewVal).addReg(Incr2).addReg(Mask);
1675   }
1676 
1677   BuildMI(BB, DL, TII->get(Mips::AND), MaskedOldVal0)
1678     .addReg(OldVal).addReg(Mask2);
1679   BuildMI(BB, DL, TII->get(Mips::OR), StoreVal)
1680     .addReg(MaskedOldVal0).addReg(NewVal);
1681   BuildMI(BB, DL, TII->get(SC), Success)
1682     .addReg(StoreVal).addReg(AlignedAddr).addImm(0);
1683   BuildMI(BB, DL, TII->get(Mips::BEQ))
1684     .addReg(Success).addReg(Mips::ZERO).addMBB(loopMBB);
1685 
1686   //  sinkMBB:
1687   //    and     maskedoldval1,oldval,mask
1688   //    srl     srlres,maskedoldval1,shiftamt
1689   //    sign_extend dest,srlres
1690   BB = sinkMBB;
1691 
1692   BuildMI(BB, DL, TII->get(Mips::AND), MaskedOldVal1)
1693     .addReg(OldVal).addReg(Mask);
1694   BuildMI(BB, DL, TII->get(Mips::SRLV), SrlRes)
1695       .addReg(MaskedOldVal1).addReg(ShiftAmt);
1696   BB = emitSignExtendToI32InReg(MI, BB, Size, Dest, SrlRes);
1697 
1698   MI.eraseFromParent(); // The instruction is gone now.
1699 
1700   return exitMBB;
1701 }
1702 
1703 MachineBasicBlock *MipsTargetLowering::emitAtomicCmpSwap(MachineInstr &MI,
1704                                                          MachineBasicBlock *BB,
1705                                                          unsigned Size) const {
1706   assert((Size == 4 || Size == 8) && "Unsupported size for EmitAtomicCmpSwap.");
1707 
1708   MachineFunction *MF = BB->getParent();
1709   MachineRegisterInfo &RegInfo = MF->getRegInfo();
1710   const TargetRegisterClass *RC = getRegClassFor(MVT::getIntegerVT(Size * 8));
1711   const TargetInstrInfo *TII = Subtarget.getInstrInfo();
1712   const bool ArePtrs64bit = ABI.ArePtrs64bit();
1713   DebugLoc DL = MI.getDebugLoc();
1714   unsigned LL, SC, ZERO, BNE, BEQ;
1715 
1716   if (Size == 4) {
1717     if (isMicroMips) {
1718       LL = Subtarget.hasMips32r6() ? Mips::LL_MMR6 : Mips::LL_MM;
1719       SC = Subtarget.hasMips32r6() ? Mips::SC_MMR6 : Mips::SC_MM;
1720     } else {
1721       LL = Subtarget.hasMips32r6()
1722                ? (ArePtrs64bit ? Mips::LL64_R6 : Mips::LL_R6)
1723                : (ArePtrs64bit ? Mips::LL64 : Mips::LL);
1724       SC = Subtarget.hasMips32r6()
1725                ? (ArePtrs64bit ? Mips::SC64_R6 : Mips::SC_R6)
1726                : (ArePtrs64bit ? Mips::SC64 : Mips::SC);
1727     }
1728 
1729     ZERO = Mips::ZERO;
1730     BNE = Mips::BNE;
1731     BEQ = Mips::BEQ;
1732   } else {
1733     LL = Subtarget.hasMips64r6() ? Mips::LLD_R6 : Mips::LLD;
1734     SC = Subtarget.hasMips64r6() ? Mips::SCD_R6 : Mips::SCD;
1735     ZERO = Mips::ZERO_64;
1736     BNE = Mips::BNE64;
1737     BEQ = Mips::BEQ64;
1738   }
1739 
1740   unsigned Dest = MI.getOperand(0).getReg();
1741   unsigned Ptr = MI.getOperand(1).getReg();
1742   unsigned OldVal = MI.getOperand(2).getReg();
1743   unsigned NewVal = MI.getOperand(3).getReg();
1744 
1745   unsigned Success = RegInfo.createVirtualRegister(RC);
1746 
1747   // insert new blocks after the current block
1748   const BasicBlock *LLVM_BB = BB->getBasicBlock();
1749   MachineBasicBlock *loop1MBB = MF->CreateMachineBasicBlock(LLVM_BB);
1750   MachineBasicBlock *loop2MBB = MF->CreateMachineBasicBlock(LLVM_BB);
1751   MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB);
1752   MachineFunction::iterator It = ++BB->getIterator();
1753   MF->insert(It, loop1MBB);
1754   MF->insert(It, loop2MBB);
1755   MF->insert(It, exitMBB);
1756 
1757   // Transfer the remainder of BB and its successor edges to exitMBB.
1758   exitMBB->splice(exitMBB->begin(), BB,
1759                   std::next(MachineBasicBlock::iterator(MI)), BB->end());
1760   exitMBB->transferSuccessorsAndUpdatePHIs(BB);
1761 
1762   //  thisMBB:
1763   //    ...
1764   //    fallthrough --> loop1MBB
1765   BB->addSuccessor(loop1MBB);
1766   loop1MBB->addSuccessor(exitMBB);
1767   loop1MBB->addSuccessor(loop2MBB);
1768   loop2MBB->addSuccessor(loop1MBB);
1769   loop2MBB->addSuccessor(exitMBB);
1770 
1771   // loop1MBB:
1772   //   ll dest, 0(ptr)
1773   //   bne dest, oldval, exitMBB
1774   BB = loop1MBB;
1775   BuildMI(BB, DL, TII->get(LL), Dest).addReg(Ptr).addImm(0);
1776   BuildMI(BB, DL, TII->get(BNE))
1777     .addReg(Dest).addReg(OldVal).addMBB(exitMBB);
1778 
1779   // loop2MBB:
1780   //   sc success, newval, 0(ptr)
1781   //   beq success, $0, loop1MBB
1782   BB = loop2MBB;
1783   BuildMI(BB, DL, TII->get(SC), Success)
1784     .addReg(NewVal).addReg(Ptr).addImm(0);
1785   BuildMI(BB, DL, TII->get(BEQ))
1786     .addReg(Success).addReg(ZERO).addMBB(loop1MBB);
1787 
1788   MI.eraseFromParent(); // The instruction is gone now.
1789 
1790   return exitMBB;
1791 }
1792 
1793 MachineBasicBlock *MipsTargetLowering::emitAtomicCmpSwapPartword(
1794     MachineInstr &MI, MachineBasicBlock *BB, unsigned Size) const {
1795   assert((Size == 1 || Size == 2) &&
1796       "Unsupported size for EmitAtomicCmpSwapPartial.");
1797 
1798   MachineFunction *MF = BB->getParent();
1799   MachineRegisterInfo &RegInfo = MF->getRegInfo();
1800   const TargetRegisterClass *RC = getRegClassFor(MVT::i32);
1801   const bool ArePtrs64bit = ABI.ArePtrs64bit();
1802   const TargetRegisterClass *RCp =
1803     getRegClassFor(ArePtrs64bit ? MVT::i64 : MVT::i32);
1804   const TargetInstrInfo *TII = Subtarget.getInstrInfo();
1805   DebugLoc DL = MI.getDebugLoc();
1806 
1807   unsigned Dest = MI.getOperand(0).getReg();
1808   unsigned Ptr = MI.getOperand(1).getReg();
1809   unsigned CmpVal = MI.getOperand(2).getReg();
1810   unsigned NewVal = MI.getOperand(3).getReg();
1811 
1812   unsigned AlignedAddr = RegInfo.createVirtualRegister(RCp);
1813   unsigned ShiftAmt = RegInfo.createVirtualRegister(RC);
1814   unsigned Mask = RegInfo.createVirtualRegister(RC);
1815   unsigned Mask2 = RegInfo.createVirtualRegister(RC);
1816   unsigned ShiftedCmpVal = RegInfo.createVirtualRegister(RC);
1817   unsigned OldVal = RegInfo.createVirtualRegister(RC);
1818   unsigned MaskedOldVal0 = RegInfo.createVirtualRegister(RC);
1819   unsigned ShiftedNewVal = RegInfo.createVirtualRegister(RC);
1820   unsigned MaskLSB2 = RegInfo.createVirtualRegister(RCp);
1821   unsigned PtrLSB2 = RegInfo.createVirtualRegister(RC);
1822   unsigned MaskUpper = RegInfo.createVirtualRegister(RC);
1823   unsigned MaskedCmpVal = RegInfo.createVirtualRegister(RC);
1824   unsigned MaskedNewVal = RegInfo.createVirtualRegister(RC);
1825   unsigned MaskedOldVal1 = RegInfo.createVirtualRegister(RC);
1826   unsigned StoreVal = RegInfo.createVirtualRegister(RC);
1827   unsigned SrlRes = RegInfo.createVirtualRegister(RC);
1828   unsigned Success = RegInfo.createVirtualRegister(RC);
1829   unsigned LL, SC;
1830 
1831   if (isMicroMips) {
1832     LL = Subtarget.hasMips32r6() ? Mips::LL_MMR6 : Mips::LL_MM;
1833     SC = Subtarget.hasMips32r6() ? Mips::SC_MMR6 : Mips::SC_MM;
1834   } else {
1835     LL = Subtarget.hasMips32r6() ? (ArePtrs64bit ? Mips::LL64_R6 : Mips::LL_R6)
1836                                  : (ArePtrs64bit ? Mips::LL64 : Mips::LL);
1837     SC = Subtarget.hasMips32r6() ? (ArePtrs64bit ? Mips::SC64_R6 : Mips::SC_R6)
1838                                  : (ArePtrs64bit ? Mips::SC64 : Mips::SC);
1839   }
1840 
1841   // insert new blocks after the current block
1842   const BasicBlock *LLVM_BB = BB->getBasicBlock();
1843   MachineBasicBlock *loop1MBB = MF->CreateMachineBasicBlock(LLVM_BB);
1844   MachineBasicBlock *loop2MBB = MF->CreateMachineBasicBlock(LLVM_BB);
1845   MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(LLVM_BB);
1846   MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB);
1847   MachineFunction::iterator It = ++BB->getIterator();
1848   MF->insert(It, loop1MBB);
1849   MF->insert(It, loop2MBB);
1850   MF->insert(It, sinkMBB);
1851   MF->insert(It, exitMBB);
1852 
1853   // Transfer the remainder of BB and its successor edges to exitMBB.
1854   exitMBB->splice(exitMBB->begin(), BB,
1855                   std::next(MachineBasicBlock::iterator(MI)), BB->end());
1856   exitMBB->transferSuccessorsAndUpdatePHIs(BB);
1857 
1858   BB->addSuccessor(loop1MBB);
1859   loop1MBB->addSuccessor(sinkMBB);
1860   loop1MBB->addSuccessor(loop2MBB);
1861   loop2MBB->addSuccessor(loop1MBB);
1862   loop2MBB->addSuccessor(sinkMBB);
1863   sinkMBB->addSuccessor(exitMBB);
1864 
1865   // FIXME: computation of newval2 can be moved to loop2MBB.
1866   //  thisMBB:
1867   //    addiu   masklsb2,$0,-4                # 0xfffffffc
1868   //    and     alignedaddr,ptr,masklsb2
1869   //    andi    ptrlsb2,ptr,3
1870   //    xori    ptrlsb2,ptrlsb2,3              # Only for BE
1871   //    sll     shiftamt,ptrlsb2,3
1872   //    ori     maskupper,$0,255               # 0xff
1873   //    sll     mask,maskupper,shiftamt
1874   //    nor     mask2,$0,mask
1875   //    andi    maskedcmpval,cmpval,255
1876   //    sll     shiftedcmpval,maskedcmpval,shiftamt
1877   //    andi    maskednewval,newval,255
1878   //    sll     shiftednewval,maskednewval,shiftamt
1879   int64_t MaskImm = (Size == 1) ? 255 : 65535;
1880   BuildMI(BB, DL, TII->get(ArePtrs64bit ? Mips::DADDiu : Mips::ADDiu), MaskLSB2)
1881     .addReg(ABI.GetNullPtr()).addImm(-4);
1882   BuildMI(BB, DL, TII->get(ArePtrs64bit ? Mips::AND64 : Mips::AND), AlignedAddr)
1883     .addReg(Ptr).addReg(MaskLSB2);
1884   BuildMI(BB, DL, TII->get(Mips::ANDi), PtrLSB2)
1885       .addReg(Ptr, 0, ArePtrs64bit ? Mips::sub_32 : 0).addImm(3);
1886   if (Subtarget.isLittle()) {
1887     BuildMI(BB, DL, TII->get(Mips::SLL), ShiftAmt).addReg(PtrLSB2).addImm(3);
1888   } else {
1889     unsigned Off = RegInfo.createVirtualRegister(RC);
1890     BuildMI(BB, DL, TII->get(Mips::XORi), Off)
1891       .addReg(PtrLSB2).addImm((Size == 1) ? 3 : 2);
1892     BuildMI(BB, DL, TII->get(Mips::SLL), ShiftAmt).addReg(Off).addImm(3);
1893   }
1894   BuildMI(BB, DL, TII->get(Mips::ORi), MaskUpper)
1895     .addReg(Mips::ZERO).addImm(MaskImm);
1896   BuildMI(BB, DL, TII->get(Mips::SLLV), Mask)
1897     .addReg(MaskUpper).addReg(ShiftAmt);
1898   BuildMI(BB, DL, TII->get(Mips::NOR), Mask2).addReg(Mips::ZERO).addReg(Mask);
1899   BuildMI(BB, DL, TII->get(Mips::ANDi), MaskedCmpVal)
1900     .addReg(CmpVal).addImm(MaskImm);
1901   BuildMI(BB, DL, TII->get(Mips::SLLV), ShiftedCmpVal)
1902     .addReg(MaskedCmpVal).addReg(ShiftAmt);
1903   BuildMI(BB, DL, TII->get(Mips::ANDi), MaskedNewVal)
1904     .addReg(NewVal).addImm(MaskImm);
1905   BuildMI(BB, DL, TII->get(Mips::SLLV), ShiftedNewVal)
1906     .addReg(MaskedNewVal).addReg(ShiftAmt);
1907 
1908   //  loop1MBB:
1909   //    ll      oldval,0(alginedaddr)
1910   //    and     maskedoldval0,oldval,mask
1911   //    bne     maskedoldval0,shiftedcmpval,sinkMBB
1912   BB = loop1MBB;
1913   BuildMI(BB, DL, TII->get(LL), OldVal).addReg(AlignedAddr).addImm(0);
1914   BuildMI(BB, DL, TII->get(Mips::AND), MaskedOldVal0)
1915     .addReg(OldVal).addReg(Mask);
1916   BuildMI(BB, DL, TII->get(Mips::BNE))
1917     .addReg(MaskedOldVal0).addReg(ShiftedCmpVal).addMBB(sinkMBB);
1918 
1919   //  loop2MBB:
1920   //    and     maskedoldval1,oldval,mask2
1921   //    or      storeval,maskedoldval1,shiftednewval
1922   //    sc      success,storeval,0(alignedaddr)
1923   //    beq     success,$0,loop1MBB
1924   BB = loop2MBB;
1925   BuildMI(BB, DL, TII->get(Mips::AND), MaskedOldVal1)
1926     .addReg(OldVal).addReg(Mask2);
1927   BuildMI(BB, DL, TII->get(Mips::OR), StoreVal)
1928     .addReg(MaskedOldVal1).addReg(ShiftedNewVal);
1929   BuildMI(BB, DL, TII->get(SC), Success)
1930       .addReg(StoreVal).addReg(AlignedAddr).addImm(0);
1931   BuildMI(BB, DL, TII->get(Mips::BEQ))
1932       .addReg(Success).addReg(Mips::ZERO).addMBB(loop1MBB);
1933 
1934   //  sinkMBB:
1935   //    srl     srlres,maskedoldval0,shiftamt
1936   //    sign_extend dest,srlres
1937   BB = sinkMBB;
1938 
1939   BuildMI(BB, DL, TII->get(Mips::SRLV), SrlRes)
1940       .addReg(MaskedOldVal0).addReg(ShiftAmt);
1941   BB = emitSignExtendToI32InReg(MI, BB, Size, Dest, SrlRes);
1942 
1943   MI.eraseFromParent(); // The instruction is gone now.
1944 
1945   return exitMBB;
1946 }
1947 
1948 SDValue MipsTargetLowering::lowerBRCOND(SDValue Op, SelectionDAG &DAG) const {
1949   // The first operand is the chain, the second is the condition, the third is
1950   // the block to branch to if the condition is true.
1951   SDValue Chain = Op.getOperand(0);
1952   SDValue Dest = Op.getOperand(2);
1953   SDLoc DL(Op);
1954 
1955   assert(!Subtarget.hasMips32r6() && !Subtarget.hasMips64r6());
1956   SDValue CondRes = createFPCmp(DAG, Op.getOperand(1));
1957 
1958   // Return if flag is not set by a floating point comparison.
1959   if (CondRes.getOpcode() != MipsISD::FPCmp)
1960     return Op;
1961 
1962   SDValue CCNode  = CondRes.getOperand(2);
1963   Mips::CondCode CC =
1964     (Mips::CondCode)cast<ConstantSDNode>(CCNode)->getZExtValue();
1965   unsigned Opc = invertFPCondCodeUser(CC) ? Mips::BRANCH_F : Mips::BRANCH_T;
1966   SDValue BrCode = DAG.getConstant(Opc, DL, MVT::i32);
1967   SDValue FCC0 = DAG.getRegister(Mips::FCC0, MVT::i32);
1968   return DAG.getNode(MipsISD::FPBrcond, DL, Op.getValueType(), Chain, BrCode,
1969                      FCC0, Dest, CondRes);
1970 }
1971 
1972 SDValue MipsTargetLowering::
1973 lowerSELECT(SDValue Op, SelectionDAG &DAG) const
1974 {
1975   assert(!Subtarget.hasMips32r6() && !Subtarget.hasMips64r6());
1976   SDValue Cond = createFPCmp(DAG, Op.getOperand(0));
1977 
1978   // Return if flag is not set by a floating point comparison.
1979   if (Cond.getOpcode() != MipsISD::FPCmp)
1980     return Op;
1981 
1982   return createCMovFP(DAG, Cond, Op.getOperand(1), Op.getOperand(2),
1983                       SDLoc(Op));
1984 }
1985 
1986 SDValue MipsTargetLowering::lowerSETCC(SDValue Op, SelectionDAG &DAG) const {
1987   assert(!Subtarget.hasMips32r6() && !Subtarget.hasMips64r6());
1988   SDValue Cond = createFPCmp(DAG, Op);
1989 
1990   assert(Cond.getOpcode() == MipsISD::FPCmp &&
1991          "Floating point operand expected.");
1992 
1993   SDLoc DL(Op);
1994   SDValue True  = DAG.getConstant(1, DL, MVT::i32);
1995   SDValue False = DAG.getConstant(0, DL, MVT::i32);
1996 
1997   return createCMovFP(DAG, Cond, True, False, DL);
1998 }
1999 
2000 SDValue MipsTargetLowering::lowerGlobalAddress(SDValue Op,
2001                                                SelectionDAG &DAG) const {
2002   EVT Ty = Op.getValueType();
2003   GlobalAddressSDNode *N = cast<GlobalAddressSDNode>(Op);
2004   const GlobalValue *GV = N->getGlobal();
2005 
2006   if (!isPositionIndependent()) {
2007     const MipsTargetObjectFile *TLOF =
2008         static_cast<const MipsTargetObjectFile *>(
2009             getTargetMachine().getObjFileLowering());
2010     const GlobalObject *GO = GV->getBaseObject();
2011     if (GO && TLOF->IsGlobalInSmallSection(GO, getTargetMachine()))
2012       // %gp_rel relocation
2013       return getAddrGPRel(N, SDLoc(N), Ty, DAG, ABI.IsN64());
2014 
2015                                  // %hi/%lo relocation
2016     return Subtarget.hasSym32() ? getAddrNonPIC(N, SDLoc(N), Ty, DAG)
2017                                  // %highest/%higher/%hi/%lo relocation
2018                                  : getAddrNonPICSym64(N, SDLoc(N), Ty, DAG);
2019   }
2020 
2021   // Every other architecture would use shouldAssumeDSOLocal in here, but
2022   // mips is special.
2023   // * In PIC code mips requires got loads even for local statics!
2024   // * To save on got entries, for local statics the got entry contains the
2025   //   page and an additional add instruction takes care of the low bits.
2026   // * It is legal to access a hidden symbol with a non hidden undefined,
2027   //   so one cannot guarantee that all access to a hidden symbol will know
2028   //   it is hidden.
2029   // * Mips linkers don't support creating a page and a full got entry for
2030   //   the same symbol.
2031   // * Given all that, we have to use a full got entry for hidden symbols :-(
2032   if (GV->hasLocalLinkage())
2033     return getAddrLocal(N, SDLoc(N), Ty, DAG, ABI.IsN32() || ABI.IsN64());
2034 
2035   if (LargeGOT)
2036     return getAddrGlobalLargeGOT(
2037         N, SDLoc(N), Ty, DAG, MipsII::MO_GOT_HI16, MipsII::MO_GOT_LO16,
2038         DAG.getEntryNode(),
2039         MachinePointerInfo::getGOT(DAG.getMachineFunction()));
2040 
2041   return getAddrGlobal(
2042       N, SDLoc(N), Ty, DAG,
2043       (ABI.IsN32() || ABI.IsN64()) ? MipsII::MO_GOT_DISP : MipsII::MO_GOT,
2044       DAG.getEntryNode(), MachinePointerInfo::getGOT(DAG.getMachineFunction()));
2045 }
2046 
2047 SDValue MipsTargetLowering::lowerBlockAddress(SDValue Op,
2048                                               SelectionDAG &DAG) const {
2049   BlockAddressSDNode *N = cast<BlockAddressSDNode>(Op);
2050   EVT Ty = Op.getValueType();
2051 
2052   if (!isPositionIndependent())
2053     return Subtarget.hasSym32() ? getAddrNonPIC(N, SDLoc(N), Ty, DAG)
2054                                 : getAddrNonPICSym64(N, SDLoc(N), Ty, DAG);
2055 
2056   return getAddrLocal(N, SDLoc(N), Ty, DAG, ABI.IsN32() || ABI.IsN64());
2057 }
2058 
2059 SDValue MipsTargetLowering::
2060 lowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const
2061 {
2062   // If the relocation model is PIC, use the General Dynamic TLS Model or
2063   // Local Dynamic TLS model, otherwise use the Initial Exec or
2064   // Local Exec TLS Model.
2065 
2066   GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
2067   if (DAG.getTarget().useEmulatedTLS())
2068     return LowerToTLSEmulatedModel(GA, DAG);
2069 
2070   SDLoc DL(GA);
2071   const GlobalValue *GV = GA->getGlobal();
2072   EVT PtrVT = getPointerTy(DAG.getDataLayout());
2073 
2074   TLSModel::Model model = getTargetMachine().getTLSModel(GV);
2075 
2076   if (model == TLSModel::GeneralDynamic || model == TLSModel::LocalDynamic) {
2077     // General Dynamic and Local Dynamic TLS Model.
2078     unsigned Flag = (model == TLSModel::LocalDynamic) ? MipsII::MO_TLSLDM
2079                                                       : MipsII::MO_TLSGD;
2080 
2081     SDValue TGA = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, Flag);
2082     SDValue Argument = DAG.getNode(MipsISD::Wrapper, DL, PtrVT,
2083                                    getGlobalReg(DAG, PtrVT), TGA);
2084     unsigned PtrSize = PtrVT.getSizeInBits();
2085     IntegerType *PtrTy = Type::getIntNTy(*DAG.getContext(), PtrSize);
2086 
2087     SDValue TlsGetAddr = DAG.getExternalSymbol("__tls_get_addr", PtrVT);
2088 
2089     ArgListTy Args;
2090     ArgListEntry Entry;
2091     Entry.Node = Argument;
2092     Entry.Ty = PtrTy;
2093     Args.push_back(Entry);
2094 
2095     TargetLowering::CallLoweringInfo CLI(DAG);
2096     CLI.setDebugLoc(DL)
2097         .setChain(DAG.getEntryNode())
2098         .setLibCallee(CallingConv::C, PtrTy, TlsGetAddr, std::move(Args));
2099     std::pair<SDValue, SDValue> CallResult = LowerCallTo(CLI);
2100 
2101     SDValue Ret = CallResult.first;
2102 
2103     if (model != TLSModel::LocalDynamic)
2104       return Ret;
2105 
2106     SDValue TGAHi = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0,
2107                                                MipsII::MO_DTPREL_HI);
2108     SDValue Hi = DAG.getNode(MipsISD::Hi, DL, PtrVT, TGAHi);
2109     SDValue TGALo = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0,
2110                                                MipsII::MO_DTPREL_LO);
2111     SDValue Lo = DAG.getNode(MipsISD::Lo, DL, PtrVT, TGALo);
2112     SDValue Add = DAG.getNode(ISD::ADD, DL, PtrVT, Hi, Ret);
2113     return DAG.getNode(ISD::ADD, DL, PtrVT, Add, Lo);
2114   }
2115 
2116   SDValue Offset;
2117   if (model == TLSModel::InitialExec) {
2118     // Initial Exec TLS Model
2119     SDValue TGA = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0,
2120                                              MipsII::MO_GOTTPREL);
2121     TGA = DAG.getNode(MipsISD::Wrapper, DL, PtrVT, getGlobalReg(DAG, PtrVT),
2122                       TGA);
2123     Offset =
2124         DAG.getLoad(PtrVT, DL, DAG.getEntryNode(), TGA, MachinePointerInfo());
2125   } else {
2126     // Local Exec TLS Model
2127     assert(model == TLSModel::LocalExec);
2128     SDValue TGAHi = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0,
2129                                                MipsII::MO_TPREL_HI);
2130     SDValue TGALo = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0,
2131                                                MipsII::MO_TPREL_LO);
2132     SDValue Hi = DAG.getNode(MipsISD::Hi, DL, PtrVT, TGAHi);
2133     SDValue Lo = DAG.getNode(MipsISD::Lo, DL, PtrVT, TGALo);
2134     Offset = DAG.getNode(ISD::ADD, DL, PtrVT, Hi, Lo);
2135   }
2136 
2137   SDValue ThreadPointer = DAG.getNode(MipsISD::ThreadPointer, DL, PtrVT);
2138   return DAG.getNode(ISD::ADD, DL, PtrVT, ThreadPointer, Offset);
2139 }
2140 
2141 SDValue MipsTargetLowering::
2142 lowerJumpTable(SDValue Op, SelectionDAG &DAG) const
2143 {
2144   JumpTableSDNode *N = cast<JumpTableSDNode>(Op);
2145   EVT Ty = Op.getValueType();
2146 
2147   if (!isPositionIndependent())
2148     return Subtarget.hasSym32() ? getAddrNonPIC(N, SDLoc(N), Ty, DAG)
2149                                 : getAddrNonPICSym64(N, SDLoc(N), Ty, DAG);
2150 
2151   return getAddrLocal(N, SDLoc(N), Ty, DAG, ABI.IsN32() || ABI.IsN64());
2152 }
2153 
2154 SDValue MipsTargetLowering::
2155 lowerConstantPool(SDValue Op, SelectionDAG &DAG) const
2156 {
2157   ConstantPoolSDNode *N = cast<ConstantPoolSDNode>(Op);
2158   EVT Ty = Op.getValueType();
2159 
2160   if (!isPositionIndependent()) {
2161     const MipsTargetObjectFile *TLOF =
2162         static_cast<const MipsTargetObjectFile *>(
2163             getTargetMachine().getObjFileLowering());
2164 
2165     if (TLOF->IsConstantInSmallSection(DAG.getDataLayout(), N->getConstVal(),
2166                                        getTargetMachine()))
2167       // %gp_rel relocation
2168       return getAddrGPRel(N, SDLoc(N), Ty, DAG, ABI.IsN64());
2169 
2170     return Subtarget.hasSym32() ? getAddrNonPIC(N, SDLoc(N), Ty, DAG)
2171                                 : getAddrNonPICSym64(N, SDLoc(N), Ty, DAG);
2172   }
2173 
2174  return getAddrLocal(N, SDLoc(N), Ty, DAG, ABI.IsN32() || ABI.IsN64());
2175 }
2176 
2177 SDValue MipsTargetLowering::lowerVASTART(SDValue Op, SelectionDAG &DAG) const {
2178   MachineFunction &MF = DAG.getMachineFunction();
2179   MipsFunctionInfo *FuncInfo = MF.getInfo<MipsFunctionInfo>();
2180 
2181   SDLoc DL(Op);
2182   SDValue FI = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
2183                                  getPointerTy(MF.getDataLayout()));
2184 
2185   // vastart just stores the address of the VarArgsFrameIndex slot into the
2186   // memory location argument.
2187   const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
2188   return DAG.getStore(Op.getOperand(0), DL, FI, Op.getOperand(1),
2189                       MachinePointerInfo(SV));
2190 }
2191 
2192 SDValue MipsTargetLowering::lowerVAARG(SDValue Op, SelectionDAG &DAG) const {
2193   SDNode *Node = Op.getNode();
2194   EVT VT = Node->getValueType(0);
2195   SDValue Chain = Node->getOperand(0);
2196   SDValue VAListPtr = Node->getOperand(1);
2197   unsigned Align = Node->getConstantOperandVal(3);
2198   const Value *SV = cast<SrcValueSDNode>(Node->getOperand(2))->getValue();
2199   SDLoc DL(Node);
2200   unsigned ArgSlotSizeInBytes = (ABI.IsN32() || ABI.IsN64()) ? 8 : 4;
2201 
2202   SDValue VAListLoad = DAG.getLoad(getPointerTy(DAG.getDataLayout()), DL, Chain,
2203                                    VAListPtr, MachinePointerInfo(SV));
2204   SDValue VAList = VAListLoad;
2205 
2206   // Re-align the pointer if necessary.
2207   // It should only ever be necessary for 64-bit types on O32 since the minimum
2208   // argument alignment is the same as the maximum type alignment for N32/N64.
2209   //
2210   // FIXME: We currently align too often. The code generator doesn't notice
2211   //        when the pointer is still aligned from the last va_arg (or pair of
2212   //        va_args for the i64 on O32 case).
2213   if (Align > getMinStackArgumentAlignment()) {
2214     assert(((Align & (Align-1)) == 0) && "Expected Align to be a power of 2");
2215 
2216     VAList = DAG.getNode(ISD::ADD, DL, VAList.getValueType(), VAList,
2217                          DAG.getConstant(Align - 1, DL, VAList.getValueType()));
2218 
2219     VAList = DAG.getNode(ISD::AND, DL, VAList.getValueType(), VAList,
2220                          DAG.getConstant(-(int64_t)Align, DL,
2221                                          VAList.getValueType()));
2222   }
2223 
2224   // Increment the pointer, VAList, to the next vaarg.
2225   auto &TD = DAG.getDataLayout();
2226   unsigned ArgSizeInBytes =
2227       TD.getTypeAllocSize(VT.getTypeForEVT(*DAG.getContext()));
2228   SDValue Tmp3 =
2229       DAG.getNode(ISD::ADD, DL, VAList.getValueType(), VAList,
2230                   DAG.getConstant(alignTo(ArgSizeInBytes, ArgSlotSizeInBytes),
2231                                   DL, VAList.getValueType()));
2232   // Store the incremented VAList to the legalized pointer
2233   Chain = DAG.getStore(VAListLoad.getValue(1), DL, Tmp3, VAListPtr,
2234                        MachinePointerInfo(SV));
2235 
2236   // In big-endian mode we must adjust the pointer when the load size is smaller
2237   // than the argument slot size. We must also reduce the known alignment to
2238   // match. For example in the N64 ABI, we must add 4 bytes to the offset to get
2239   // the correct half of the slot, and reduce the alignment from 8 (slot
2240   // alignment) down to 4 (type alignment).
2241   if (!Subtarget.isLittle() && ArgSizeInBytes < ArgSlotSizeInBytes) {
2242     unsigned Adjustment = ArgSlotSizeInBytes - ArgSizeInBytes;
2243     VAList = DAG.getNode(ISD::ADD, DL, VAListPtr.getValueType(), VAList,
2244                          DAG.getIntPtrConstant(Adjustment, DL));
2245   }
2246   // Load the actual argument out of the pointer VAList
2247   return DAG.getLoad(VT, DL, Chain, VAList, MachinePointerInfo());
2248 }
2249 
2250 static SDValue lowerFCOPYSIGN32(SDValue Op, SelectionDAG &DAG,
2251                                 bool HasExtractInsert) {
2252   EVT TyX = Op.getOperand(0).getValueType();
2253   EVT TyY = Op.getOperand(1).getValueType();
2254   SDLoc DL(Op);
2255   SDValue Const1 = DAG.getConstant(1, DL, MVT::i32);
2256   SDValue Const31 = DAG.getConstant(31, DL, MVT::i32);
2257   SDValue Res;
2258 
2259   // If operand is of type f64, extract the upper 32-bit. Otherwise, bitcast it
2260   // to i32.
2261   SDValue X = (TyX == MVT::f32) ?
2262     DAG.getNode(ISD::BITCAST, DL, MVT::i32, Op.getOperand(0)) :
2263     DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32, Op.getOperand(0),
2264                 Const1);
2265   SDValue Y = (TyY == MVT::f32) ?
2266     DAG.getNode(ISD::BITCAST, DL, MVT::i32, Op.getOperand(1)) :
2267     DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32, Op.getOperand(1),
2268                 Const1);
2269 
2270   if (HasExtractInsert) {
2271     // ext  E, Y, 31, 1  ; extract bit31 of Y
2272     // ins  X, E, 31, 1  ; insert extracted bit at bit31 of X
2273     SDValue E = DAG.getNode(MipsISD::Ext, DL, MVT::i32, Y, Const31, Const1);
2274     Res = DAG.getNode(MipsISD::Ins, DL, MVT::i32, E, Const31, Const1, X);
2275   } else {
2276     // sll SllX, X, 1
2277     // srl SrlX, SllX, 1
2278     // srl SrlY, Y, 31
2279     // sll SllY, SrlX, 31
2280     // or  Or, SrlX, SllY
2281     SDValue SllX = DAG.getNode(ISD::SHL, DL, MVT::i32, X, Const1);
2282     SDValue SrlX = DAG.getNode(ISD::SRL, DL, MVT::i32, SllX, Const1);
2283     SDValue SrlY = DAG.getNode(ISD::SRL, DL, MVT::i32, Y, Const31);
2284     SDValue SllY = DAG.getNode(ISD::SHL, DL, MVT::i32, SrlY, Const31);
2285     Res = DAG.getNode(ISD::OR, DL, MVT::i32, SrlX, SllY);
2286   }
2287 
2288   if (TyX == MVT::f32)
2289     return DAG.getNode(ISD::BITCAST, DL, Op.getOperand(0).getValueType(), Res);
2290 
2291   SDValue LowX = DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32,
2292                              Op.getOperand(0),
2293                              DAG.getConstant(0, DL, MVT::i32));
2294   return DAG.getNode(MipsISD::BuildPairF64, DL, MVT::f64, LowX, Res);
2295 }
2296 
2297 static SDValue lowerFCOPYSIGN64(SDValue Op, SelectionDAG &DAG,
2298                                 bool HasExtractInsert) {
2299   unsigned WidthX = Op.getOperand(0).getValueSizeInBits();
2300   unsigned WidthY = Op.getOperand(1).getValueSizeInBits();
2301   EVT TyX = MVT::getIntegerVT(WidthX), TyY = MVT::getIntegerVT(WidthY);
2302   SDLoc DL(Op);
2303   SDValue Const1 = DAG.getConstant(1, DL, MVT::i32);
2304 
2305   // Bitcast to integer nodes.
2306   SDValue X = DAG.getNode(ISD::BITCAST, DL, TyX, Op.getOperand(0));
2307   SDValue Y = DAG.getNode(ISD::BITCAST, DL, TyY, Op.getOperand(1));
2308 
2309   if (HasExtractInsert) {
2310     // ext  E, Y, width(Y) - 1, 1  ; extract bit width(Y)-1 of Y
2311     // ins  X, E, width(X) - 1, 1  ; insert extracted bit at bit width(X)-1 of X
2312     SDValue E = DAG.getNode(MipsISD::Ext, DL, TyY, Y,
2313                             DAG.getConstant(WidthY - 1, DL, MVT::i32), Const1);
2314 
2315     if (WidthX > WidthY)
2316       E = DAG.getNode(ISD::ZERO_EXTEND, DL, TyX, E);
2317     else if (WidthY > WidthX)
2318       E = DAG.getNode(ISD::TRUNCATE, DL, TyX, E);
2319 
2320     SDValue I = DAG.getNode(MipsISD::Ins, DL, TyX, E,
2321                             DAG.getConstant(WidthX - 1, DL, MVT::i32), Const1,
2322                             X);
2323     return DAG.getNode(ISD::BITCAST, DL, Op.getOperand(0).getValueType(), I);
2324   }
2325 
2326   // (d)sll SllX, X, 1
2327   // (d)srl SrlX, SllX, 1
2328   // (d)srl SrlY, Y, width(Y)-1
2329   // (d)sll SllY, SrlX, width(Y)-1
2330   // or     Or, SrlX, SllY
2331   SDValue SllX = DAG.getNode(ISD::SHL, DL, TyX, X, Const1);
2332   SDValue SrlX = DAG.getNode(ISD::SRL, DL, TyX, SllX, Const1);
2333   SDValue SrlY = DAG.getNode(ISD::SRL, DL, TyY, Y,
2334                              DAG.getConstant(WidthY - 1, DL, MVT::i32));
2335 
2336   if (WidthX > WidthY)
2337     SrlY = DAG.getNode(ISD::ZERO_EXTEND, DL, TyX, SrlY);
2338   else if (WidthY > WidthX)
2339     SrlY = DAG.getNode(ISD::TRUNCATE, DL, TyX, SrlY);
2340 
2341   SDValue SllY = DAG.getNode(ISD::SHL, DL, TyX, SrlY,
2342                              DAG.getConstant(WidthX - 1, DL, MVT::i32));
2343   SDValue Or = DAG.getNode(ISD::OR, DL, TyX, SrlX, SllY);
2344   return DAG.getNode(ISD::BITCAST, DL, Op.getOperand(0).getValueType(), Or);
2345 }
2346 
2347 SDValue
2348 MipsTargetLowering::lowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const {
2349   if (Subtarget.isGP64bit())
2350     return lowerFCOPYSIGN64(Op, DAG, Subtarget.hasExtractInsert());
2351 
2352   return lowerFCOPYSIGN32(Op, DAG, Subtarget.hasExtractInsert());
2353 }
2354 
2355 SDValue MipsTargetLowering::
2356 lowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const {
2357   // check the depth
2358   assert((cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue() == 0) &&
2359          "Frame address can only be determined for current frame.");
2360 
2361   MachineFrameInfo &MFI = DAG.getMachineFunction().getFrameInfo();
2362   MFI.setFrameAddressIsTaken(true);
2363   EVT VT = Op.getValueType();
2364   SDLoc DL(Op);
2365   SDValue FrameAddr = DAG.getCopyFromReg(
2366       DAG.getEntryNode(), DL, ABI.IsN64() ? Mips::FP_64 : Mips::FP, VT);
2367   return FrameAddr;
2368 }
2369 
2370 SDValue MipsTargetLowering::lowerRETURNADDR(SDValue Op,
2371                                             SelectionDAG &DAG) const {
2372   if (verifyReturnAddressArgumentIsConstant(Op, DAG))
2373     return SDValue();
2374 
2375   // check the depth
2376   assert((cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue() == 0) &&
2377          "Return address can be determined only for current frame.");
2378 
2379   MachineFunction &MF = DAG.getMachineFunction();
2380   MachineFrameInfo &MFI = MF.getFrameInfo();
2381   MVT VT = Op.getSimpleValueType();
2382   unsigned RA = ABI.IsN64() ? Mips::RA_64 : Mips::RA;
2383   MFI.setReturnAddressIsTaken(true);
2384 
2385   // Return RA, which contains the return address. Mark it an implicit live-in.
2386   unsigned Reg = MF.addLiveIn(RA, getRegClassFor(VT));
2387   return DAG.getCopyFromReg(DAG.getEntryNode(), SDLoc(Op), Reg, VT);
2388 }
2389 
2390 // An EH_RETURN is the result of lowering llvm.eh.return which in turn is
2391 // generated from __builtin_eh_return (offset, handler)
2392 // The effect of this is to adjust the stack pointer by "offset"
2393 // and then branch to "handler".
2394 SDValue MipsTargetLowering::lowerEH_RETURN(SDValue Op, SelectionDAG &DAG)
2395                                                                      const {
2396   MachineFunction &MF = DAG.getMachineFunction();
2397   MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
2398 
2399   MipsFI->setCallsEhReturn();
2400   SDValue Chain     = Op.getOperand(0);
2401   SDValue Offset    = Op.getOperand(1);
2402   SDValue Handler   = Op.getOperand(2);
2403   SDLoc DL(Op);
2404   EVT Ty = ABI.IsN64() ? MVT::i64 : MVT::i32;
2405 
2406   // Store stack offset in V1, store jump target in V0. Glue CopyToReg and
2407   // EH_RETURN nodes, so that instructions are emitted back-to-back.
2408   unsigned OffsetReg = ABI.IsN64() ? Mips::V1_64 : Mips::V1;
2409   unsigned AddrReg = ABI.IsN64() ? Mips::V0_64 : Mips::V0;
2410   Chain = DAG.getCopyToReg(Chain, DL, OffsetReg, Offset, SDValue());
2411   Chain = DAG.getCopyToReg(Chain, DL, AddrReg, Handler, Chain.getValue(1));
2412   return DAG.getNode(MipsISD::EH_RETURN, DL, MVT::Other, Chain,
2413                      DAG.getRegister(OffsetReg, Ty),
2414                      DAG.getRegister(AddrReg, getPointerTy(MF.getDataLayout())),
2415                      Chain.getValue(1));
2416 }
2417 
2418 SDValue MipsTargetLowering::lowerATOMIC_FENCE(SDValue Op,
2419                                               SelectionDAG &DAG) const {
2420   // FIXME: Need pseudo-fence for 'singlethread' fences
2421   // FIXME: Set SType for weaker fences where supported/appropriate.
2422   unsigned SType = 0;
2423   SDLoc DL(Op);
2424   return DAG.getNode(MipsISD::Sync, DL, MVT::Other, Op.getOperand(0),
2425                      DAG.getConstant(SType, DL, MVT::i32));
2426 }
2427 
2428 SDValue MipsTargetLowering::lowerShiftLeftParts(SDValue Op,
2429                                                 SelectionDAG &DAG) const {
2430   SDLoc DL(Op);
2431   MVT VT = Subtarget.isGP64bit() ? MVT::i64 : MVT::i32;
2432 
2433   SDValue Lo = Op.getOperand(0), Hi = Op.getOperand(1);
2434   SDValue Shamt = Op.getOperand(2);
2435   // if shamt < (VT.bits):
2436   //  lo = (shl lo, shamt)
2437   //  hi = (or (shl hi, shamt) (srl (srl lo, 1), ~shamt))
2438   // else:
2439   //  lo = 0
2440   //  hi = (shl lo, shamt[4:0])
2441   SDValue Not = DAG.getNode(ISD::XOR, DL, MVT::i32, Shamt,
2442                             DAG.getConstant(-1, DL, MVT::i32));
2443   SDValue ShiftRight1Lo = DAG.getNode(ISD::SRL, DL, VT, Lo,
2444                                       DAG.getConstant(1, DL, VT));
2445   SDValue ShiftRightLo = DAG.getNode(ISD::SRL, DL, VT, ShiftRight1Lo, Not);
2446   SDValue ShiftLeftHi = DAG.getNode(ISD::SHL, DL, VT, Hi, Shamt);
2447   SDValue Or = DAG.getNode(ISD::OR, DL, VT, ShiftLeftHi, ShiftRightLo);
2448   SDValue ShiftLeftLo = DAG.getNode(ISD::SHL, DL, VT, Lo, Shamt);
2449   SDValue Cond = DAG.getNode(ISD::AND, DL, MVT::i32, Shamt,
2450                              DAG.getConstant(VT.getSizeInBits(), DL, MVT::i32));
2451   Lo = DAG.getNode(ISD::SELECT, DL, VT, Cond,
2452                    DAG.getConstant(0, DL, VT), ShiftLeftLo);
2453   Hi = DAG.getNode(ISD::SELECT, DL, VT, Cond, ShiftLeftLo, Or);
2454 
2455   SDValue Ops[2] = {Lo, Hi};
2456   return DAG.getMergeValues(Ops, DL);
2457 }
2458 
2459 SDValue MipsTargetLowering::lowerShiftRightParts(SDValue Op, SelectionDAG &DAG,
2460                                                  bool IsSRA) const {
2461   SDLoc DL(Op);
2462   SDValue Lo = Op.getOperand(0), Hi = Op.getOperand(1);
2463   SDValue Shamt = Op.getOperand(2);
2464   MVT VT = Subtarget.isGP64bit() ? MVT::i64 : MVT::i32;
2465 
2466   // if shamt < (VT.bits):
2467   //  lo = (or (shl (shl hi, 1), ~shamt) (srl lo, shamt))
2468   //  if isSRA:
2469   //    hi = (sra hi, shamt)
2470   //  else:
2471   //    hi = (srl hi, shamt)
2472   // else:
2473   //  if isSRA:
2474   //   lo = (sra hi, shamt[4:0])
2475   //   hi = (sra hi, 31)
2476   //  else:
2477   //   lo = (srl hi, shamt[4:0])
2478   //   hi = 0
2479   SDValue Not = DAG.getNode(ISD::XOR, DL, MVT::i32, Shamt,
2480                             DAG.getConstant(-1, DL, MVT::i32));
2481   SDValue ShiftLeft1Hi = DAG.getNode(ISD::SHL, DL, VT, Hi,
2482                                      DAG.getConstant(1, DL, VT));
2483   SDValue ShiftLeftHi = DAG.getNode(ISD::SHL, DL, VT, ShiftLeft1Hi, Not);
2484   SDValue ShiftRightLo = DAG.getNode(ISD::SRL, DL, VT, Lo, Shamt);
2485   SDValue Or = DAG.getNode(ISD::OR, DL, VT, ShiftLeftHi, ShiftRightLo);
2486   SDValue ShiftRightHi = DAG.getNode(IsSRA ? ISD::SRA : ISD::SRL,
2487                                      DL, VT, Hi, Shamt);
2488   SDValue Cond = DAG.getNode(ISD::AND, DL, MVT::i32, Shamt,
2489                              DAG.getConstant(VT.getSizeInBits(), DL, MVT::i32));
2490   SDValue Ext = DAG.getNode(ISD::SRA, DL, VT, Hi,
2491                             DAG.getConstant(VT.getSizeInBits() - 1, DL, VT));
2492   Lo = DAG.getNode(ISD::SELECT, DL, VT, Cond, ShiftRightHi, Or);
2493   Hi = DAG.getNode(ISD::SELECT, DL, VT, Cond,
2494                    IsSRA ? Ext : DAG.getConstant(0, DL, VT), ShiftRightHi);
2495 
2496   SDValue Ops[2] = {Lo, Hi};
2497   return DAG.getMergeValues(Ops, DL);
2498 }
2499 
2500 static SDValue createLoadLR(unsigned Opc, SelectionDAG &DAG, LoadSDNode *LD,
2501                             SDValue Chain, SDValue Src, unsigned Offset) {
2502   SDValue Ptr = LD->getBasePtr();
2503   EVT VT = LD->getValueType(0), MemVT = LD->getMemoryVT();
2504   EVT BasePtrVT = Ptr.getValueType();
2505   SDLoc DL(LD);
2506   SDVTList VTList = DAG.getVTList(VT, MVT::Other);
2507 
2508   if (Offset)
2509     Ptr = DAG.getNode(ISD::ADD, DL, BasePtrVT, Ptr,
2510                       DAG.getConstant(Offset, DL, BasePtrVT));
2511 
2512   SDValue Ops[] = { Chain, Ptr, Src };
2513   return DAG.getMemIntrinsicNode(Opc, DL, VTList, Ops, MemVT,
2514                                  LD->getMemOperand());
2515 }
2516 
2517 // Expand an unaligned 32 or 64-bit integer load node.
2518 SDValue MipsTargetLowering::lowerLOAD(SDValue Op, SelectionDAG &DAG) const {
2519   LoadSDNode *LD = cast<LoadSDNode>(Op);
2520   EVT MemVT = LD->getMemoryVT();
2521 
2522   if (Subtarget.systemSupportsUnalignedAccess())
2523     return Op;
2524 
2525   // Return if load is aligned or if MemVT is neither i32 nor i64.
2526   if ((LD->getAlignment() >= MemVT.getSizeInBits() / 8) ||
2527       ((MemVT != MVT::i32) && (MemVT != MVT::i64)))
2528     return SDValue();
2529 
2530   bool IsLittle = Subtarget.isLittle();
2531   EVT VT = Op.getValueType();
2532   ISD::LoadExtType ExtType = LD->getExtensionType();
2533   SDValue Chain = LD->getChain(), Undef = DAG.getUNDEF(VT);
2534 
2535   assert((VT == MVT::i32) || (VT == MVT::i64));
2536 
2537   // Expand
2538   //  (set dst, (i64 (load baseptr)))
2539   // to
2540   //  (set tmp, (ldl (add baseptr, 7), undef))
2541   //  (set dst, (ldr baseptr, tmp))
2542   if ((VT == MVT::i64) && (ExtType == ISD::NON_EXTLOAD)) {
2543     SDValue LDL = createLoadLR(MipsISD::LDL, DAG, LD, Chain, Undef,
2544                                IsLittle ? 7 : 0);
2545     return createLoadLR(MipsISD::LDR, DAG, LD, LDL.getValue(1), LDL,
2546                         IsLittle ? 0 : 7);
2547   }
2548 
2549   SDValue LWL = createLoadLR(MipsISD::LWL, DAG, LD, Chain, Undef,
2550                              IsLittle ? 3 : 0);
2551   SDValue LWR = createLoadLR(MipsISD::LWR, DAG, LD, LWL.getValue(1), LWL,
2552                              IsLittle ? 0 : 3);
2553 
2554   // Expand
2555   //  (set dst, (i32 (load baseptr))) or
2556   //  (set dst, (i64 (sextload baseptr))) or
2557   //  (set dst, (i64 (extload baseptr)))
2558   // to
2559   //  (set tmp, (lwl (add baseptr, 3), undef))
2560   //  (set dst, (lwr baseptr, tmp))
2561   if ((VT == MVT::i32) || (ExtType == ISD::SEXTLOAD) ||
2562       (ExtType == ISD::EXTLOAD))
2563     return LWR;
2564 
2565   assert((VT == MVT::i64) && (ExtType == ISD::ZEXTLOAD));
2566 
2567   // Expand
2568   //  (set dst, (i64 (zextload baseptr)))
2569   // to
2570   //  (set tmp0, (lwl (add baseptr, 3), undef))
2571   //  (set tmp1, (lwr baseptr, tmp0))
2572   //  (set tmp2, (shl tmp1, 32))
2573   //  (set dst, (srl tmp2, 32))
2574   SDLoc DL(LD);
2575   SDValue Const32 = DAG.getConstant(32, DL, MVT::i32);
2576   SDValue SLL = DAG.getNode(ISD::SHL, DL, MVT::i64, LWR, Const32);
2577   SDValue SRL = DAG.getNode(ISD::SRL, DL, MVT::i64, SLL, Const32);
2578   SDValue Ops[] = { SRL, LWR.getValue(1) };
2579   return DAG.getMergeValues(Ops, DL);
2580 }
2581 
2582 static SDValue createStoreLR(unsigned Opc, SelectionDAG &DAG, StoreSDNode *SD,
2583                              SDValue Chain, unsigned Offset) {
2584   SDValue Ptr = SD->getBasePtr(), Value = SD->getValue();
2585   EVT MemVT = SD->getMemoryVT(), BasePtrVT = Ptr.getValueType();
2586   SDLoc DL(SD);
2587   SDVTList VTList = DAG.getVTList(MVT::Other);
2588 
2589   if (Offset)
2590     Ptr = DAG.getNode(ISD::ADD, DL, BasePtrVT, Ptr,
2591                       DAG.getConstant(Offset, DL, BasePtrVT));
2592 
2593   SDValue Ops[] = { Chain, Value, Ptr };
2594   return DAG.getMemIntrinsicNode(Opc, DL, VTList, Ops, MemVT,
2595                                  SD->getMemOperand());
2596 }
2597 
2598 // Expand an unaligned 32 or 64-bit integer store node.
2599 static SDValue lowerUnalignedIntStore(StoreSDNode *SD, SelectionDAG &DAG,
2600                                       bool IsLittle) {
2601   SDValue Value = SD->getValue(), Chain = SD->getChain();
2602   EVT VT = Value.getValueType();
2603 
2604   // Expand
2605   //  (store val, baseptr) or
2606   //  (truncstore val, baseptr)
2607   // to
2608   //  (swl val, (add baseptr, 3))
2609   //  (swr val, baseptr)
2610   if ((VT == MVT::i32) || SD->isTruncatingStore()) {
2611     SDValue SWL = createStoreLR(MipsISD::SWL, DAG, SD, Chain,
2612                                 IsLittle ? 3 : 0);
2613     return createStoreLR(MipsISD::SWR, DAG, SD, SWL, IsLittle ? 0 : 3);
2614   }
2615 
2616   assert(VT == MVT::i64);
2617 
2618   // Expand
2619   //  (store val, baseptr)
2620   // to
2621   //  (sdl val, (add baseptr, 7))
2622   //  (sdr val, baseptr)
2623   SDValue SDL = createStoreLR(MipsISD::SDL, DAG, SD, Chain, IsLittle ? 7 : 0);
2624   return createStoreLR(MipsISD::SDR, DAG, SD, SDL, IsLittle ? 0 : 7);
2625 }
2626 
2627 // Lower (store (fp_to_sint $fp) $ptr) to (store (TruncIntFP $fp), $ptr).
2628 static SDValue lowerFP_TO_SINT_STORE(StoreSDNode *SD, SelectionDAG &DAG) {
2629   SDValue Val = SD->getValue();
2630 
2631   if (Val.getOpcode() != ISD::FP_TO_SINT)
2632     return SDValue();
2633 
2634   EVT FPTy = EVT::getFloatingPointVT(Val.getValueSizeInBits());
2635   SDValue Tr = DAG.getNode(MipsISD::TruncIntFP, SDLoc(Val), FPTy,
2636                            Val.getOperand(0));
2637   return DAG.getStore(SD->getChain(), SDLoc(SD), Tr, SD->getBasePtr(),
2638                       SD->getPointerInfo(), SD->getAlignment(),
2639                       SD->getMemOperand()->getFlags());
2640 }
2641 
2642 SDValue MipsTargetLowering::lowerSTORE(SDValue Op, SelectionDAG &DAG) const {
2643   StoreSDNode *SD = cast<StoreSDNode>(Op);
2644   EVT MemVT = SD->getMemoryVT();
2645 
2646   // Lower unaligned integer stores.
2647   if (!Subtarget.systemSupportsUnalignedAccess() &&
2648       (SD->getAlignment() < MemVT.getSizeInBits() / 8) &&
2649       ((MemVT == MVT::i32) || (MemVT == MVT::i64)))
2650     return lowerUnalignedIntStore(SD, DAG, Subtarget.isLittle());
2651 
2652   return lowerFP_TO_SINT_STORE(SD, DAG);
2653 }
2654 
2655 SDValue MipsTargetLowering::lowerEH_DWARF_CFA(SDValue Op,
2656                                               SelectionDAG &DAG) const {
2657 
2658   // Return a fixed StackObject with offset 0 which points to the old stack
2659   // pointer.
2660   MachineFrameInfo &MFI = DAG.getMachineFunction().getFrameInfo();
2661   EVT ValTy = Op->getValueType(0);
2662   int FI = MFI.CreateFixedObject(Op.getValueSizeInBits() / 8, 0, false);
2663   return DAG.getFrameIndex(FI, ValTy);
2664 }
2665 
2666 SDValue MipsTargetLowering::lowerFP_TO_SINT(SDValue Op,
2667                                             SelectionDAG &DAG) const {
2668   EVT FPTy = EVT::getFloatingPointVT(Op.getValueSizeInBits());
2669   SDValue Trunc = DAG.getNode(MipsISD::TruncIntFP, SDLoc(Op), FPTy,
2670                               Op.getOperand(0));
2671   return DAG.getNode(ISD::BITCAST, SDLoc(Op), Op.getValueType(), Trunc);
2672 }
2673 
2674 //===----------------------------------------------------------------------===//
2675 //                      Calling Convention Implementation
2676 //===----------------------------------------------------------------------===//
2677 
2678 //===----------------------------------------------------------------------===//
2679 // TODO: Implement a generic logic using tblgen that can support this.
2680 // Mips O32 ABI rules:
2681 // ---
2682 // i32 - Passed in A0, A1, A2, A3 and stack
2683 // f32 - Only passed in f32 registers if no int reg has been used yet to hold
2684 //       an argument. Otherwise, passed in A1, A2, A3 and stack.
2685 // f64 - Only passed in two aliased f32 registers if no int reg has been used
2686 //       yet to hold an argument. Otherwise, use A2, A3 and stack. If A1 is
2687 //       not used, it must be shadowed. If only A3 is available, shadow it and
2688 //       go to stack.
2689 // vXiX - Received as scalarized i32s, passed in A0 - A3 and the stack.
2690 // vXf32 - Passed in either a pair of registers {A0, A1}, {A2, A3} or {A0 - A3}
2691 //         with the remainder spilled to the stack.
2692 // vXf64 - Passed in either {A0, A1, A2, A3} or {A2, A3} and in both cases
2693 //         spilling the remainder to the stack.
2694 //
2695 //  For vararg functions, all arguments are passed in A0, A1, A2, A3 and stack.
2696 //===----------------------------------------------------------------------===//
2697 
2698 static bool CC_MipsO32(unsigned ValNo, MVT ValVT, MVT LocVT,
2699                        CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags,
2700                        CCState &State, ArrayRef<MCPhysReg> F64Regs) {
2701   const MipsSubtarget &Subtarget = static_cast<const MipsSubtarget &>(
2702       State.getMachineFunction().getSubtarget());
2703 
2704   static const MCPhysReg IntRegs[] = { Mips::A0, Mips::A1, Mips::A2, Mips::A3 };
2705 
2706   const MipsCCState * MipsState = static_cast<MipsCCState *>(&State);
2707 
2708   static const MCPhysReg F32Regs[] = { Mips::F12, Mips::F14 };
2709 
2710   static const MCPhysReg FloatVectorIntRegs[] = { Mips::A0, Mips::A2 };
2711 
2712   // Do not process byval args here.
2713   if (ArgFlags.isByVal())
2714     return true;
2715 
2716   // Promote i8 and i16
2717   if (ArgFlags.isInReg() && !Subtarget.isLittle()) {
2718     if (LocVT == MVT::i8 || LocVT == MVT::i16 || LocVT == MVT::i32) {
2719       LocVT = MVT::i32;
2720       if (ArgFlags.isSExt())
2721         LocInfo = CCValAssign::SExtUpper;
2722       else if (ArgFlags.isZExt())
2723         LocInfo = CCValAssign::ZExtUpper;
2724       else
2725         LocInfo = CCValAssign::AExtUpper;
2726     }
2727   }
2728 
2729   // Promote i8 and i16
2730   if (LocVT == MVT::i8 || LocVT == MVT::i16) {
2731     LocVT = MVT::i32;
2732     if (ArgFlags.isSExt())
2733       LocInfo = CCValAssign::SExt;
2734     else if (ArgFlags.isZExt())
2735       LocInfo = CCValAssign::ZExt;
2736     else
2737       LocInfo = CCValAssign::AExt;
2738   }
2739 
2740   unsigned Reg;
2741 
2742   // f32 and f64 are allocated in A0, A1, A2, A3 when either of the following
2743   // is true: function is vararg, argument is 3rd or higher, there is previous
2744   // argument which is not f32 or f64.
2745   bool AllocateFloatsInIntReg = State.isVarArg() || ValNo > 1 ||
2746                                 State.getFirstUnallocated(F32Regs) != ValNo;
2747   unsigned OrigAlign = ArgFlags.getOrigAlign();
2748   bool isI64 = (ValVT == MVT::i32 && OrigAlign == 8);
2749   bool isVectorFloat = MipsState->WasOriginalArgVectorFloat(ValNo);
2750 
2751   // The MIPS vector ABI for floats passes them in a pair of registers
2752   if (ValVT == MVT::i32 && isVectorFloat) {
2753     // This is the start of an vector that was scalarized into an unknown number
2754     // of components. It doesn't matter how many there are. Allocate one of the
2755     // notional 8 byte aligned registers which map onto the argument stack, and
2756     // shadow the register lost to alignment requirements.
2757     if (ArgFlags.isSplit()) {
2758       Reg = State.AllocateReg(FloatVectorIntRegs);
2759       if (Reg == Mips::A2)
2760         State.AllocateReg(Mips::A1);
2761       else if (Reg == 0)
2762         State.AllocateReg(Mips::A3);
2763     } else {
2764       // If we're an intermediate component of the split, we can just attempt to
2765       // allocate a register directly.
2766       Reg = State.AllocateReg(IntRegs);
2767     }
2768   } else if (ValVT == MVT::i32 || (ValVT == MVT::f32 && AllocateFloatsInIntReg)) {
2769     Reg = State.AllocateReg(IntRegs);
2770     // If this is the first part of an i64 arg,
2771     // the allocated register must be either A0 or A2.
2772     if (isI64 && (Reg == Mips::A1 || Reg == Mips::A3))
2773       Reg = State.AllocateReg(IntRegs);
2774     LocVT = MVT::i32;
2775   } else if (ValVT == MVT::f64 && AllocateFloatsInIntReg) {
2776     // Allocate int register and shadow next int register. If first
2777     // available register is Mips::A1 or Mips::A3, shadow it too.
2778     Reg = State.AllocateReg(IntRegs);
2779     if (Reg == Mips::A1 || Reg == Mips::A3)
2780       Reg = State.AllocateReg(IntRegs);
2781     State.AllocateReg(IntRegs);
2782     LocVT = MVT::i32;
2783   } else if (ValVT.isFloatingPoint() && !AllocateFloatsInIntReg) {
2784     // we are guaranteed to find an available float register
2785     if (ValVT == MVT::f32) {
2786       Reg = State.AllocateReg(F32Regs);
2787       // Shadow int register
2788       State.AllocateReg(IntRegs);
2789     } else {
2790       Reg = State.AllocateReg(F64Regs);
2791       // Shadow int registers
2792       unsigned Reg2 = State.AllocateReg(IntRegs);
2793       if (Reg2 == Mips::A1 || Reg2 == Mips::A3)
2794         State.AllocateReg(IntRegs);
2795       State.AllocateReg(IntRegs);
2796     }
2797   } else
2798     llvm_unreachable("Cannot handle this ValVT.");
2799 
2800   if (!Reg) {
2801     unsigned Offset = State.AllocateStack(ValVT.getStoreSize(), OrigAlign);
2802     State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo));
2803   } else
2804     State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
2805 
2806   return false;
2807 }
2808 
2809 static bool CC_MipsO32_FP32(unsigned ValNo, MVT ValVT,
2810                             MVT LocVT, CCValAssign::LocInfo LocInfo,
2811                             ISD::ArgFlagsTy ArgFlags, CCState &State) {
2812   static const MCPhysReg F64Regs[] = { Mips::D6, Mips::D7 };
2813 
2814   return CC_MipsO32(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State, F64Regs);
2815 }
2816 
2817 static bool CC_MipsO32_FP64(unsigned ValNo, MVT ValVT,
2818                             MVT LocVT, CCValAssign::LocInfo LocInfo,
2819                             ISD::ArgFlagsTy ArgFlags, CCState &State) {
2820   static const MCPhysReg F64Regs[] = { Mips::D12_64, Mips::D14_64 };
2821 
2822   return CC_MipsO32(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State, F64Regs);
2823 }
2824 
2825 static bool CC_MipsO32(unsigned ValNo, MVT ValVT, MVT LocVT,
2826                        CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags,
2827                        CCState &State) LLVM_ATTRIBUTE_UNUSED;
2828 
2829 #include "MipsGenCallingConv.inc"
2830 
2831  CCAssignFn *MipsTargetLowering::CCAssignFnForCall() const{
2832    return CC_Mips;
2833  }
2834 
2835  CCAssignFn *MipsTargetLowering::CCAssignFnForReturn() const{
2836    return RetCC_Mips;
2837  }
2838 //===----------------------------------------------------------------------===//
2839 //                  Call Calling Convention Implementation
2840 //===----------------------------------------------------------------------===//
2841 
2842 // Return next O32 integer argument register.
2843 static unsigned getNextIntArgReg(unsigned Reg) {
2844   assert((Reg == Mips::A0) || (Reg == Mips::A2));
2845   return (Reg == Mips::A0) ? Mips::A1 : Mips::A3;
2846 }
2847 
2848 SDValue MipsTargetLowering::passArgOnStack(SDValue StackPtr, unsigned Offset,
2849                                            SDValue Chain, SDValue Arg,
2850                                            const SDLoc &DL, bool IsTailCall,
2851                                            SelectionDAG &DAG) const {
2852   if (!IsTailCall) {
2853     SDValue PtrOff =
2854         DAG.getNode(ISD::ADD, DL, getPointerTy(DAG.getDataLayout()), StackPtr,
2855                     DAG.getIntPtrConstant(Offset, DL));
2856     return DAG.getStore(Chain, DL, Arg, PtrOff, MachinePointerInfo());
2857   }
2858 
2859   MachineFrameInfo &MFI = DAG.getMachineFunction().getFrameInfo();
2860   int FI = MFI.CreateFixedObject(Arg.getValueSizeInBits() / 8, Offset, false);
2861   SDValue FIN = DAG.getFrameIndex(FI, getPointerTy(DAG.getDataLayout()));
2862   return DAG.getStore(Chain, DL, Arg, FIN, MachinePointerInfo(),
2863                       /* Alignment = */ 0, MachineMemOperand::MOVolatile);
2864 }
2865 
2866 void MipsTargetLowering::
2867 getOpndList(SmallVectorImpl<SDValue> &Ops,
2868             std::deque<std::pair<unsigned, SDValue>> &RegsToPass,
2869             bool IsPICCall, bool GlobalOrExternal, bool InternalLinkage,
2870             bool IsCallReloc, CallLoweringInfo &CLI, SDValue Callee,
2871             SDValue Chain) const {
2872   // Insert node "GP copy globalreg" before call to function.
2873   //
2874   // R_MIPS_CALL* operators (emitted when non-internal functions are called
2875   // in PIC mode) allow symbols to be resolved via lazy binding.
2876   // The lazy binding stub requires GP to point to the GOT.
2877   // Note that we don't need GP to point to the GOT for indirect calls
2878   // (when R_MIPS_CALL* is not used for the call) because Mips linker generates
2879   // lazy binding stub for a function only when R_MIPS_CALL* are the only relocs
2880   // used for the function (that is, Mips linker doesn't generate lazy binding
2881   // stub for a function whose address is taken in the program).
2882   if (IsPICCall && !InternalLinkage && IsCallReloc) {
2883     unsigned GPReg = ABI.IsN64() ? Mips::GP_64 : Mips::GP;
2884     EVT Ty = ABI.IsN64() ? MVT::i64 : MVT::i32;
2885     RegsToPass.push_back(std::make_pair(GPReg, getGlobalReg(CLI.DAG, Ty)));
2886   }
2887 
2888   // Build a sequence of copy-to-reg nodes chained together with token
2889   // chain and flag operands which copy the outgoing args into registers.
2890   // The InFlag in necessary since all emitted instructions must be
2891   // stuck together.
2892   SDValue InFlag;
2893 
2894   for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
2895     Chain = CLI.DAG.getCopyToReg(Chain, CLI.DL, RegsToPass[i].first,
2896                                  RegsToPass[i].second, InFlag);
2897     InFlag = Chain.getValue(1);
2898   }
2899 
2900   // Add argument registers to the end of the list so that they are
2901   // known live into the call.
2902   for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
2903     Ops.push_back(CLI.DAG.getRegister(RegsToPass[i].first,
2904                                       RegsToPass[i].second.getValueType()));
2905 
2906   // Add a register mask operand representing the call-preserved registers.
2907   const TargetRegisterInfo *TRI = Subtarget.getRegisterInfo();
2908   const uint32_t *Mask =
2909       TRI->getCallPreservedMask(CLI.DAG.getMachineFunction(), CLI.CallConv);
2910   assert(Mask && "Missing call preserved mask for calling convention");
2911   if (Subtarget.inMips16HardFloat()) {
2912     if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(CLI.Callee)) {
2913       StringRef Sym = G->getGlobal()->getName();
2914       Function *F = G->getGlobal()->getParent()->getFunction(Sym);
2915       if (F && F->hasFnAttribute("__Mips16RetHelper")) {
2916         Mask = MipsRegisterInfo::getMips16RetHelperMask();
2917       }
2918     }
2919   }
2920   Ops.push_back(CLI.DAG.getRegisterMask(Mask));
2921 
2922   if (InFlag.getNode())
2923     Ops.push_back(InFlag);
2924 }
2925 
2926 /// LowerCall - functions arguments are copied from virtual regs to
2927 /// (physical regs)/(stack frame), CALLSEQ_START and CALLSEQ_END are emitted.
2928 SDValue
2929 MipsTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
2930                               SmallVectorImpl<SDValue> &InVals) const {
2931   SelectionDAG &DAG                     = CLI.DAG;
2932   SDLoc DL                              = CLI.DL;
2933   SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;
2934   SmallVectorImpl<SDValue> &OutVals     = CLI.OutVals;
2935   SmallVectorImpl<ISD::InputArg> &Ins   = CLI.Ins;
2936   SDValue Chain                         = CLI.Chain;
2937   SDValue Callee                        = CLI.Callee;
2938   bool &IsTailCall                      = CLI.IsTailCall;
2939   CallingConv::ID CallConv              = CLI.CallConv;
2940   bool IsVarArg                         = CLI.IsVarArg;
2941 
2942   MachineFunction &MF = DAG.getMachineFunction();
2943   MachineFrameInfo &MFI = MF.getFrameInfo();
2944   const TargetFrameLowering *TFL = Subtarget.getFrameLowering();
2945   MipsFunctionInfo *FuncInfo = MF.getInfo<MipsFunctionInfo>();
2946   bool IsPIC = isPositionIndependent();
2947 
2948   // Analyze operands of the call, assigning locations to each operand.
2949   SmallVector<CCValAssign, 16> ArgLocs;
2950   MipsCCState CCInfo(
2951       CallConv, IsVarArg, DAG.getMachineFunction(), ArgLocs, *DAG.getContext(),
2952       MipsCCState::getSpecialCallingConvForCallee(Callee.getNode(), Subtarget));
2953 
2954   const ExternalSymbolSDNode *ES =
2955       dyn_cast_or_null<const ExternalSymbolSDNode>(Callee.getNode());
2956 
2957   // There is one case where CALLSEQ_START..CALLSEQ_END can be nested, which
2958   // is during the lowering of a call with a byval argument which produces
2959   // a call to memcpy. For the O32 case, this causes the caller to allocate
2960   // stack space for the reserved argument area for the callee, then recursively
2961   // again for the memcpy call. In the NEWABI case, this doesn't occur as those
2962   // ABIs mandate that the callee allocates the reserved argument area. We do
2963   // still produce nested CALLSEQ_START..CALLSEQ_END with zero space though.
2964   //
2965   // If the callee has a byval argument and memcpy is used, we are mandated
2966   // to already have produced a reserved argument area for the callee for O32.
2967   // Therefore, the reserved argument area can be reused for both calls.
2968   //
2969   // Other cases of calling memcpy cannot have a chain with a CALLSEQ_START
2970   // present, as we have yet to hook that node onto the chain.
2971   //
2972   // Hence, the CALLSEQ_START and CALLSEQ_END nodes can be eliminated in this
2973   // case. GCC does a similar trick, in that wherever possible, it calculates
2974   // the maximum out going argument area (including the reserved area), and
2975   // preallocates the stack space on entrance to the caller.
2976   //
2977   // FIXME: We should do the same for efficency and space.
2978 
2979   // Note: The check on the calling convention below must match
2980   //       MipsABIInfo::GetCalleeAllocdArgSizeInBytes().
2981   bool MemcpyInByVal = ES &&
2982                        StringRef(ES->getSymbol()) == StringRef("memcpy") &&
2983                        CallConv != CallingConv::Fast &&
2984                        Chain.getOpcode() == ISD::CALLSEQ_START;
2985 
2986   // Allocate the reserved argument area. It seems strange to do this from the
2987   // caller side but removing it breaks the frame size calculation.
2988   unsigned ReservedArgArea =
2989       MemcpyInByVal ? 0 : ABI.GetCalleeAllocdArgSizeInBytes(CallConv);
2990   CCInfo.AllocateStack(ReservedArgArea, 1);
2991 
2992   CCInfo.AnalyzeCallOperands(Outs, CC_Mips, CLI.getArgs(),
2993                              ES ? ES->getSymbol() : nullptr);
2994 
2995   // Get a count of how many bytes are to be pushed on the stack.
2996   unsigned NextStackOffset = CCInfo.getNextStackOffset();
2997 
2998   // Check if it's really possible to do a tail call. Restrict it to functions
2999   // that are part of this compilation unit.
3000   bool InternalLinkage = false;
3001   if (IsTailCall) {
3002     IsTailCall = isEligibleForTailCallOptimization(
3003         CCInfo, NextStackOffset, *MF.getInfo<MipsFunctionInfo>());
3004      if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
3005       InternalLinkage = G->getGlobal()->hasInternalLinkage();
3006       IsTailCall &= (InternalLinkage || G->getGlobal()->hasLocalLinkage() ||
3007                      G->getGlobal()->hasPrivateLinkage() ||
3008                      G->getGlobal()->hasHiddenVisibility() ||
3009                      G->getGlobal()->hasProtectedVisibility());
3010      }
3011   }
3012   if (!IsTailCall && CLI.CS && CLI.CS.isMustTailCall())
3013     report_fatal_error("failed to perform tail call elimination on a call "
3014                        "site marked musttail");
3015 
3016   if (IsTailCall)
3017     ++NumTailCalls;
3018 
3019   // Chain is the output chain of the last Load/Store or CopyToReg node.
3020   // ByValChain is the output chain of the last Memcpy node created for copying
3021   // byval arguments to the stack.
3022   unsigned StackAlignment = TFL->getStackAlignment();
3023   NextStackOffset = alignTo(NextStackOffset, StackAlignment);
3024   SDValue NextStackOffsetVal = DAG.getIntPtrConstant(NextStackOffset, DL, true);
3025 
3026   if (!(IsTailCall || MemcpyInByVal))
3027     Chain = DAG.getCALLSEQ_START(Chain, NextStackOffset, 0, DL);
3028 
3029   SDValue StackPtr =
3030       DAG.getCopyFromReg(Chain, DL, ABI.IsN64() ? Mips::SP_64 : Mips::SP,
3031                          getPointerTy(DAG.getDataLayout()));
3032 
3033   std::deque<std::pair<unsigned, SDValue>> RegsToPass;
3034   SmallVector<SDValue, 8> MemOpChains;
3035 
3036   CCInfo.rewindByValRegsInfo();
3037 
3038   // Walk the register/memloc assignments, inserting copies/loads.
3039   for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
3040     SDValue Arg = OutVals[i];
3041     CCValAssign &VA = ArgLocs[i];
3042     MVT ValVT = VA.getValVT(), LocVT = VA.getLocVT();
3043     ISD::ArgFlagsTy Flags = Outs[i].Flags;
3044     bool UseUpperBits = false;
3045 
3046     // ByVal Arg.
3047     if (Flags.isByVal()) {
3048       unsigned FirstByValReg, LastByValReg;
3049       unsigned ByValIdx = CCInfo.getInRegsParamsProcessed();
3050       CCInfo.getInRegsParamInfo(ByValIdx, FirstByValReg, LastByValReg);
3051 
3052       assert(Flags.getByValSize() &&
3053              "ByVal args of size 0 should have been ignored by front-end.");
3054       assert(ByValIdx < CCInfo.getInRegsParamsCount());
3055       assert(!IsTailCall &&
3056              "Do not tail-call optimize if there is a byval argument.");
3057       passByValArg(Chain, DL, RegsToPass, MemOpChains, StackPtr, MFI, DAG, Arg,
3058                    FirstByValReg, LastByValReg, Flags, Subtarget.isLittle(),
3059                    VA);
3060       CCInfo.nextInRegsParam();
3061       continue;
3062     }
3063 
3064     // Promote the value if needed.
3065     switch (VA.getLocInfo()) {
3066     default:
3067       llvm_unreachable("Unknown loc info!");
3068     case CCValAssign::Full:
3069       if (VA.isRegLoc()) {
3070         if ((ValVT == MVT::f32 && LocVT == MVT::i32) ||
3071             (ValVT == MVT::f64 && LocVT == MVT::i64) ||
3072             (ValVT == MVT::i64 && LocVT == MVT::f64))
3073           Arg = DAG.getNode(ISD::BITCAST, DL, LocVT, Arg);
3074         else if (ValVT == MVT::f64 && LocVT == MVT::i32) {
3075           SDValue Lo = DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32,
3076                                    Arg, DAG.getConstant(0, DL, MVT::i32));
3077           SDValue Hi = DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32,
3078                                    Arg, DAG.getConstant(1, DL, MVT::i32));
3079           if (!Subtarget.isLittle())
3080             std::swap(Lo, Hi);
3081           unsigned LocRegLo = VA.getLocReg();
3082           unsigned LocRegHigh = getNextIntArgReg(LocRegLo);
3083           RegsToPass.push_back(std::make_pair(LocRegLo, Lo));
3084           RegsToPass.push_back(std::make_pair(LocRegHigh, Hi));
3085           continue;
3086         }
3087       }
3088       break;
3089     case CCValAssign::BCvt:
3090       Arg = DAG.getNode(ISD::BITCAST, DL, LocVT, Arg);
3091       break;
3092     case CCValAssign::SExtUpper:
3093       UseUpperBits = true;
3094       LLVM_FALLTHROUGH;
3095     case CCValAssign::SExt:
3096       Arg = DAG.getNode(ISD::SIGN_EXTEND, DL, LocVT, Arg);
3097       break;
3098     case CCValAssign::ZExtUpper:
3099       UseUpperBits = true;
3100       LLVM_FALLTHROUGH;
3101     case CCValAssign::ZExt:
3102       Arg = DAG.getNode(ISD::ZERO_EXTEND, DL, LocVT, Arg);
3103       break;
3104     case CCValAssign::AExtUpper:
3105       UseUpperBits = true;
3106       LLVM_FALLTHROUGH;
3107     case CCValAssign::AExt:
3108       Arg = DAG.getNode(ISD::ANY_EXTEND, DL, LocVT, Arg);
3109       break;
3110     }
3111 
3112     if (UseUpperBits) {
3113       unsigned ValSizeInBits = Outs[i].ArgVT.getSizeInBits();
3114       unsigned LocSizeInBits = VA.getLocVT().getSizeInBits();
3115       Arg = DAG.getNode(
3116           ISD::SHL, DL, VA.getLocVT(), Arg,
3117           DAG.getConstant(LocSizeInBits - ValSizeInBits, DL, VA.getLocVT()));
3118     }
3119 
3120     // Arguments that can be passed on register must be kept at
3121     // RegsToPass vector
3122     if (VA.isRegLoc()) {
3123       RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
3124       continue;
3125     }
3126 
3127     // Register can't get to this point...
3128     assert(VA.isMemLoc());
3129 
3130     // emit ISD::STORE whichs stores the
3131     // parameter value to a stack Location
3132     MemOpChains.push_back(passArgOnStack(StackPtr, VA.getLocMemOffset(),
3133                                          Chain, Arg, DL, IsTailCall, DAG));
3134   }
3135 
3136   // Transform all store nodes into one single node because all store
3137   // nodes are independent of each other.
3138   if (!MemOpChains.empty())
3139     Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, MemOpChains);
3140 
3141   // If the callee is a GlobalAddress/ExternalSymbol node (quite common, every
3142   // direct call is) turn it into a TargetGlobalAddress/TargetExternalSymbol
3143   // node so that legalize doesn't hack it.
3144 
3145   EVT Ty = Callee.getValueType();
3146   bool GlobalOrExternal = false, IsCallReloc = false;
3147 
3148   // The long-calls feature is ignored in case of PIC.
3149   // While we do not support -mshared / -mno-shared properly,
3150   // ignore long-calls in case of -mabicalls too.
3151   if (!Subtarget.isABICalls() && !IsPIC) {
3152     // If the function should be called using "long call",
3153     // get its address into a register to prevent using
3154     // of the `jal` instruction for the direct call.
3155     if (auto *N = dyn_cast<ExternalSymbolSDNode>(Callee)) {
3156       if (Subtarget.useLongCalls())
3157         Callee = Subtarget.hasSym32()
3158                      ? getAddrNonPIC(N, SDLoc(N), Ty, DAG)
3159                      : getAddrNonPICSym64(N, SDLoc(N), Ty, DAG);
3160     } else if (auto *N = dyn_cast<GlobalAddressSDNode>(Callee)) {
3161       bool UseLongCalls = Subtarget.useLongCalls();
3162       // If the function has long-call/far/near attribute
3163       // it overrides command line switch pased to the backend.
3164       if (auto *F = dyn_cast<Function>(N->getGlobal())) {
3165         if (F->hasFnAttribute("long-call"))
3166           UseLongCalls = true;
3167         else if (F->hasFnAttribute("short-call"))
3168           UseLongCalls = false;
3169       }
3170       if (UseLongCalls)
3171         Callee = Subtarget.hasSym32()
3172                      ? getAddrNonPIC(N, SDLoc(N), Ty, DAG)
3173                      : getAddrNonPICSym64(N, SDLoc(N), Ty, DAG);
3174     }
3175   }
3176 
3177   if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
3178     if (IsPIC) {
3179       const GlobalValue *Val = G->getGlobal();
3180       InternalLinkage = Val->hasInternalLinkage();
3181 
3182       if (InternalLinkage)
3183         Callee = getAddrLocal(G, DL, Ty, DAG, ABI.IsN32() || ABI.IsN64());
3184       else if (LargeGOT) {
3185         Callee = getAddrGlobalLargeGOT(G, DL, Ty, DAG, MipsII::MO_CALL_HI16,
3186                                        MipsII::MO_CALL_LO16, Chain,
3187                                        FuncInfo->callPtrInfo(Val));
3188         IsCallReloc = true;
3189       } else {
3190         Callee = getAddrGlobal(G, DL, Ty, DAG, MipsII::MO_GOT_CALL, Chain,
3191                                FuncInfo->callPtrInfo(Val));
3192         IsCallReloc = true;
3193       }
3194     } else
3195       Callee = DAG.getTargetGlobalAddress(G->getGlobal(), DL,
3196                                           getPointerTy(DAG.getDataLayout()), 0,
3197                                           MipsII::MO_NO_FLAG);
3198     GlobalOrExternal = true;
3199   }
3200   else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
3201     const char *Sym = S->getSymbol();
3202 
3203     if (!IsPIC) // static
3204       Callee = DAG.getTargetExternalSymbol(
3205           Sym, getPointerTy(DAG.getDataLayout()), MipsII::MO_NO_FLAG);
3206     else if (LargeGOT) {
3207       Callee = getAddrGlobalLargeGOT(S, DL, Ty, DAG, MipsII::MO_CALL_HI16,
3208                                      MipsII::MO_CALL_LO16, Chain,
3209                                      FuncInfo->callPtrInfo(Sym));
3210       IsCallReloc = true;
3211     } else { // PIC
3212       Callee = getAddrGlobal(S, DL, Ty, DAG, MipsII::MO_GOT_CALL, Chain,
3213                              FuncInfo->callPtrInfo(Sym));
3214       IsCallReloc = true;
3215     }
3216 
3217     GlobalOrExternal = true;
3218   }
3219 
3220   SmallVector<SDValue, 8> Ops(1, Chain);
3221   SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
3222 
3223   getOpndList(Ops, RegsToPass, IsPIC, GlobalOrExternal, InternalLinkage,
3224               IsCallReloc, CLI, Callee, Chain);
3225 
3226   if (IsTailCall) {
3227     MF.getFrameInfo().setHasTailCall();
3228     return DAG.getNode(MipsISD::TailCall, DL, MVT::Other, Ops);
3229   }
3230 
3231   Chain = DAG.getNode(MipsISD::JmpLink, DL, NodeTys, Ops);
3232   SDValue InFlag = Chain.getValue(1);
3233 
3234   // Create the CALLSEQ_END node in the case of where it is not a call to
3235   // memcpy.
3236   if (!(MemcpyInByVal)) {
3237     Chain = DAG.getCALLSEQ_END(Chain, NextStackOffsetVal,
3238                                DAG.getIntPtrConstant(0, DL, true), InFlag, DL);
3239     InFlag = Chain.getValue(1);
3240   }
3241 
3242   // Handle result values, copying them out of physregs into vregs that we
3243   // return.
3244   return LowerCallResult(Chain, InFlag, CallConv, IsVarArg, Ins, DL, DAG,
3245                          InVals, CLI);
3246 }
3247 
3248 /// LowerCallResult - Lower the result values of a call into the
3249 /// appropriate copies out of appropriate physical registers.
3250 SDValue MipsTargetLowering::LowerCallResult(
3251     SDValue Chain, SDValue InFlag, CallingConv::ID CallConv, bool IsVarArg,
3252     const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &DL,
3253     SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals,
3254     TargetLowering::CallLoweringInfo &CLI) const {
3255   // Assign locations to each value returned by this call.
3256   SmallVector<CCValAssign, 16> RVLocs;
3257   MipsCCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), RVLocs,
3258                      *DAG.getContext());
3259 
3260   const ExternalSymbolSDNode *ES =
3261       dyn_cast_or_null<const ExternalSymbolSDNode>(CLI.Callee.getNode());
3262   CCInfo.AnalyzeCallResult(Ins, RetCC_Mips, CLI.RetTy,
3263                            ES ? ES->getSymbol() : nullptr);
3264 
3265   // Copy all of the result registers out of their specified physreg.
3266   for (unsigned i = 0; i != RVLocs.size(); ++i) {
3267     CCValAssign &VA = RVLocs[i];
3268     assert(VA.isRegLoc() && "Can only return in registers!");
3269 
3270     SDValue Val = DAG.getCopyFromReg(Chain, DL, RVLocs[i].getLocReg(),
3271                                      RVLocs[i].getLocVT(), InFlag);
3272     Chain = Val.getValue(1);
3273     InFlag = Val.getValue(2);
3274 
3275     if (VA.isUpperBitsInLoc()) {
3276       unsigned ValSizeInBits = Ins[i].ArgVT.getSizeInBits();
3277       unsigned LocSizeInBits = VA.getLocVT().getSizeInBits();
3278       unsigned Shift =
3279           VA.getLocInfo() == CCValAssign::ZExtUpper ? ISD::SRL : ISD::SRA;
3280       Val = DAG.getNode(
3281           Shift, DL, VA.getLocVT(), Val,
3282           DAG.getConstant(LocSizeInBits - ValSizeInBits, DL, VA.getLocVT()));
3283     }
3284 
3285     switch (VA.getLocInfo()) {
3286     default:
3287       llvm_unreachable("Unknown loc info!");
3288     case CCValAssign::Full:
3289       break;
3290     case CCValAssign::BCvt:
3291       Val = DAG.getNode(ISD::BITCAST, DL, VA.getValVT(), Val);
3292       break;
3293     case CCValAssign::AExt:
3294     case CCValAssign::AExtUpper:
3295       Val = DAG.getNode(ISD::TRUNCATE, DL, VA.getValVT(), Val);
3296       break;
3297     case CCValAssign::ZExt:
3298     case CCValAssign::ZExtUpper:
3299       Val = DAG.getNode(ISD::AssertZext, DL, VA.getLocVT(), Val,
3300                         DAG.getValueType(VA.getValVT()));
3301       Val = DAG.getNode(ISD::TRUNCATE, DL, VA.getValVT(), Val);
3302       break;
3303     case CCValAssign::SExt:
3304     case CCValAssign::SExtUpper:
3305       Val = DAG.getNode(ISD::AssertSext, DL, VA.getLocVT(), Val,
3306                         DAG.getValueType(VA.getValVT()));
3307       Val = DAG.getNode(ISD::TRUNCATE, DL, VA.getValVT(), Val);
3308       break;
3309     }
3310 
3311     InVals.push_back(Val);
3312   }
3313 
3314   return Chain;
3315 }
3316 
3317 static SDValue UnpackFromArgumentSlot(SDValue Val, const CCValAssign &VA,
3318                                       EVT ArgVT, const SDLoc &DL,
3319                                       SelectionDAG &DAG) {
3320   MVT LocVT = VA.getLocVT();
3321   EVT ValVT = VA.getValVT();
3322 
3323   // Shift into the upper bits if necessary.
3324   switch (VA.getLocInfo()) {
3325   default:
3326     break;
3327   case CCValAssign::AExtUpper:
3328   case CCValAssign::SExtUpper:
3329   case CCValAssign::ZExtUpper: {
3330     unsigned ValSizeInBits = ArgVT.getSizeInBits();
3331     unsigned LocSizeInBits = VA.getLocVT().getSizeInBits();
3332     unsigned Opcode =
3333         VA.getLocInfo() == CCValAssign::ZExtUpper ? ISD::SRL : ISD::SRA;
3334     Val = DAG.getNode(
3335         Opcode, DL, VA.getLocVT(), Val,
3336         DAG.getConstant(LocSizeInBits - ValSizeInBits, DL, VA.getLocVT()));
3337     break;
3338   }
3339   }
3340 
3341   // If this is an value smaller than the argument slot size (32-bit for O32,
3342   // 64-bit for N32/N64), it has been promoted in some way to the argument slot
3343   // size. Extract the value and insert any appropriate assertions regarding
3344   // sign/zero extension.
3345   switch (VA.getLocInfo()) {
3346   default:
3347     llvm_unreachable("Unknown loc info!");
3348   case CCValAssign::Full:
3349     break;
3350   case CCValAssign::AExtUpper:
3351   case CCValAssign::AExt:
3352     Val = DAG.getNode(ISD::TRUNCATE, DL, ValVT, Val);
3353     break;
3354   case CCValAssign::SExtUpper:
3355   case CCValAssign::SExt:
3356     Val = DAG.getNode(ISD::AssertSext, DL, LocVT, Val, DAG.getValueType(ValVT));
3357     Val = DAG.getNode(ISD::TRUNCATE, DL, ValVT, Val);
3358     break;
3359   case CCValAssign::ZExtUpper:
3360   case CCValAssign::ZExt:
3361     Val = DAG.getNode(ISD::AssertZext, DL, LocVT, Val, DAG.getValueType(ValVT));
3362     Val = DAG.getNode(ISD::TRUNCATE, DL, ValVT, Val);
3363     break;
3364   case CCValAssign::BCvt:
3365     Val = DAG.getNode(ISD::BITCAST, DL, ValVT, Val);
3366     break;
3367   }
3368 
3369   return Val;
3370 }
3371 
3372 //===----------------------------------------------------------------------===//
3373 //             Formal Arguments Calling Convention Implementation
3374 //===----------------------------------------------------------------------===//
3375 /// LowerFormalArguments - transform physical registers into virtual registers
3376 /// and generate load operations for arguments places on the stack.
3377 SDValue MipsTargetLowering::LowerFormalArguments(
3378     SDValue Chain, CallingConv::ID CallConv, bool IsVarArg,
3379     const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &DL,
3380     SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const {
3381   MachineFunction &MF = DAG.getMachineFunction();
3382   MachineFrameInfo &MFI = MF.getFrameInfo();
3383   MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
3384 
3385   MipsFI->setVarArgsFrameIndex(0);
3386 
3387   // Used with vargs to acumulate store chains.
3388   std::vector<SDValue> OutChains;
3389 
3390   // Assign locations to all of the incoming arguments.
3391   SmallVector<CCValAssign, 16> ArgLocs;
3392   MipsCCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), ArgLocs,
3393                      *DAG.getContext());
3394   CCInfo.AllocateStack(ABI.GetCalleeAllocdArgSizeInBytes(CallConv), 1);
3395   const Function &Func = DAG.getMachineFunction().getFunction();
3396   Function::const_arg_iterator FuncArg = Func.arg_begin();
3397 
3398   if (Func.hasFnAttribute("interrupt") && !Func.arg_empty())
3399     report_fatal_error(
3400         "Functions with the interrupt attribute cannot have arguments!");
3401 
3402   CCInfo.AnalyzeFormalArguments(Ins, CC_Mips_FixedArg);
3403   MipsFI->setFormalArgInfo(CCInfo.getNextStackOffset(),
3404                            CCInfo.getInRegsParamsCount() > 0);
3405 
3406   unsigned CurArgIdx = 0;
3407   CCInfo.rewindByValRegsInfo();
3408 
3409   for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
3410     CCValAssign &VA = ArgLocs[i];
3411     if (Ins[i].isOrigArg()) {
3412       std::advance(FuncArg, Ins[i].getOrigArgIndex() - CurArgIdx);
3413       CurArgIdx = Ins[i].getOrigArgIndex();
3414     }
3415     EVT ValVT = VA.getValVT();
3416     ISD::ArgFlagsTy Flags = Ins[i].Flags;
3417     bool IsRegLoc = VA.isRegLoc();
3418 
3419     if (Flags.isByVal()) {
3420       assert(Ins[i].isOrigArg() && "Byval arguments cannot be implicit");
3421       unsigned FirstByValReg, LastByValReg;
3422       unsigned ByValIdx = CCInfo.getInRegsParamsProcessed();
3423       CCInfo.getInRegsParamInfo(ByValIdx, FirstByValReg, LastByValReg);
3424 
3425       assert(Flags.getByValSize() &&
3426              "ByVal args of size 0 should have been ignored by front-end.");
3427       assert(ByValIdx < CCInfo.getInRegsParamsCount());
3428       copyByValRegs(Chain, DL, OutChains, DAG, Flags, InVals, &*FuncArg,
3429                     FirstByValReg, LastByValReg, VA, CCInfo);
3430       CCInfo.nextInRegsParam();
3431       continue;
3432     }
3433 
3434     // Arguments stored on registers
3435     if (IsRegLoc) {
3436       MVT RegVT = VA.getLocVT();
3437       unsigned ArgReg = VA.getLocReg();
3438       const TargetRegisterClass *RC = getRegClassFor(RegVT);
3439 
3440       // Transform the arguments stored on
3441       // physical registers into virtual ones
3442       unsigned Reg = addLiveIn(DAG.getMachineFunction(), ArgReg, RC);
3443       SDValue ArgValue = DAG.getCopyFromReg(Chain, DL, Reg, RegVT);
3444 
3445       ArgValue = UnpackFromArgumentSlot(ArgValue, VA, Ins[i].ArgVT, DL, DAG);
3446 
3447       // Handle floating point arguments passed in integer registers and
3448       // long double arguments passed in floating point registers.
3449       if ((RegVT == MVT::i32 && ValVT == MVT::f32) ||
3450           (RegVT == MVT::i64 && ValVT == MVT::f64) ||
3451           (RegVT == MVT::f64 && ValVT == MVT::i64))
3452         ArgValue = DAG.getNode(ISD::BITCAST, DL, ValVT, ArgValue);
3453       else if (ABI.IsO32() && RegVT == MVT::i32 &&
3454                ValVT == MVT::f64) {
3455         unsigned Reg2 = addLiveIn(DAG.getMachineFunction(),
3456                                   getNextIntArgReg(ArgReg), RC);
3457         SDValue ArgValue2 = DAG.getCopyFromReg(Chain, DL, Reg2, RegVT);
3458         if (!Subtarget.isLittle())
3459           std::swap(ArgValue, ArgValue2);
3460         ArgValue = DAG.getNode(MipsISD::BuildPairF64, DL, MVT::f64,
3461                                ArgValue, ArgValue2);
3462       }
3463 
3464       InVals.push_back(ArgValue);
3465     } else { // VA.isRegLoc()
3466       MVT LocVT = VA.getLocVT();
3467 
3468       if (ABI.IsO32()) {
3469         // We ought to be able to use LocVT directly but O32 sets it to i32
3470         // when allocating floating point values to integer registers.
3471         // This shouldn't influence how we load the value into registers unless
3472         // we are targeting softfloat.
3473         if (VA.getValVT().isFloatingPoint() && !Subtarget.useSoftFloat())
3474           LocVT = VA.getValVT();
3475       }
3476 
3477       // sanity check
3478       assert(VA.isMemLoc());
3479 
3480       // The stack pointer offset is relative to the caller stack frame.
3481       int FI = MFI.CreateFixedObject(LocVT.getSizeInBits() / 8,
3482                                      VA.getLocMemOffset(), true);
3483 
3484       // Create load nodes to retrieve arguments from the stack
3485       SDValue FIN = DAG.getFrameIndex(FI, getPointerTy(DAG.getDataLayout()));
3486       SDValue ArgValue = DAG.getLoad(
3487           LocVT, DL, Chain, FIN,
3488           MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), FI));
3489       OutChains.push_back(ArgValue.getValue(1));
3490 
3491       ArgValue = UnpackFromArgumentSlot(ArgValue, VA, Ins[i].ArgVT, DL, DAG);
3492 
3493       InVals.push_back(ArgValue);
3494     }
3495   }
3496 
3497   for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
3498     // The mips ABIs for returning structs by value requires that we copy
3499     // the sret argument into $v0 for the return. Save the argument into
3500     // a virtual register so that we can access it from the return points.
3501     if (Ins[i].Flags.isSRet()) {
3502       unsigned Reg = MipsFI->getSRetReturnReg();
3503       if (!Reg) {
3504         Reg = MF.getRegInfo().createVirtualRegister(
3505             getRegClassFor(ABI.IsN64() ? MVT::i64 : MVT::i32));
3506         MipsFI->setSRetReturnReg(Reg);
3507       }
3508       SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), DL, Reg, InVals[i]);
3509       Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, Copy, Chain);
3510       break;
3511     }
3512   }
3513 
3514   if (IsVarArg)
3515     writeVarArgRegs(OutChains, Chain, DL, DAG, CCInfo);
3516 
3517   // All stores are grouped in one node to allow the matching between
3518   // the size of Ins and InVals. This only happens when on varg functions
3519   if (!OutChains.empty()) {
3520     OutChains.push_back(Chain);
3521     Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, OutChains);
3522   }
3523 
3524   return Chain;
3525 }
3526 
3527 //===----------------------------------------------------------------------===//
3528 //               Return Value Calling Convention Implementation
3529 //===----------------------------------------------------------------------===//
3530 
3531 bool
3532 MipsTargetLowering::CanLowerReturn(CallingConv::ID CallConv,
3533                                    MachineFunction &MF, bool IsVarArg,
3534                                    const SmallVectorImpl<ISD::OutputArg> &Outs,
3535                                    LLVMContext &Context) const {
3536   SmallVector<CCValAssign, 16> RVLocs;
3537   MipsCCState CCInfo(CallConv, IsVarArg, MF, RVLocs, Context);
3538   return CCInfo.CheckReturn(Outs, RetCC_Mips);
3539 }
3540 
3541 bool
3542 MipsTargetLowering::shouldSignExtendTypeInLibCall(EVT Type, bool IsSigned) const {
3543   if ((ABI.IsN32() || ABI.IsN64()) && Type == MVT::i32)
3544       return true;
3545 
3546   return IsSigned;
3547 }
3548 
3549 SDValue
3550 MipsTargetLowering::LowerInterruptReturn(SmallVectorImpl<SDValue> &RetOps,
3551                                          const SDLoc &DL,
3552                                          SelectionDAG &DAG) const {
3553   MachineFunction &MF = DAG.getMachineFunction();
3554   MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
3555 
3556   MipsFI->setISR();
3557 
3558   return DAG.getNode(MipsISD::ERet, DL, MVT::Other, RetOps);
3559 }
3560 
3561 SDValue
3562 MipsTargetLowering::LowerReturn(SDValue Chain, CallingConv::ID CallConv,
3563                                 bool IsVarArg,
3564                                 const SmallVectorImpl<ISD::OutputArg> &Outs,
3565                                 const SmallVectorImpl<SDValue> &OutVals,
3566                                 const SDLoc &DL, SelectionDAG &DAG) const {
3567   // CCValAssign - represent the assignment of
3568   // the return value to a location
3569   SmallVector<CCValAssign, 16> RVLocs;
3570   MachineFunction &MF = DAG.getMachineFunction();
3571 
3572   // CCState - Info about the registers and stack slot.
3573   MipsCCState CCInfo(CallConv, IsVarArg, MF, RVLocs, *DAG.getContext());
3574 
3575   // Analyze return values.
3576   CCInfo.AnalyzeReturn(Outs, RetCC_Mips);
3577 
3578   SDValue Flag;
3579   SmallVector<SDValue, 4> RetOps(1, Chain);
3580 
3581   // Copy the result values into the output registers.
3582   for (unsigned i = 0; i != RVLocs.size(); ++i) {
3583     SDValue Val = OutVals[i];
3584     CCValAssign &VA = RVLocs[i];
3585     assert(VA.isRegLoc() && "Can only return in registers!");
3586     bool UseUpperBits = false;
3587 
3588     switch (VA.getLocInfo()) {
3589     default:
3590       llvm_unreachable("Unknown loc info!");
3591     case CCValAssign::Full:
3592       break;
3593     case CCValAssign::BCvt:
3594       Val = DAG.getNode(ISD::BITCAST, DL, VA.getLocVT(), Val);
3595       break;
3596     case CCValAssign::AExtUpper:
3597       UseUpperBits = true;
3598       LLVM_FALLTHROUGH;
3599     case CCValAssign::AExt:
3600       Val = DAG.getNode(ISD::ANY_EXTEND, DL, VA.getLocVT(), Val);
3601       break;
3602     case CCValAssign::ZExtUpper:
3603       UseUpperBits = true;
3604       LLVM_FALLTHROUGH;
3605     case CCValAssign::ZExt:
3606       Val = DAG.getNode(ISD::ZERO_EXTEND, DL, VA.getLocVT(), Val);
3607       break;
3608     case CCValAssign::SExtUpper:
3609       UseUpperBits = true;
3610       LLVM_FALLTHROUGH;
3611     case CCValAssign::SExt:
3612       Val = DAG.getNode(ISD::SIGN_EXTEND, DL, VA.getLocVT(), Val);
3613       break;
3614     }
3615 
3616     if (UseUpperBits) {
3617       unsigned ValSizeInBits = Outs[i].ArgVT.getSizeInBits();
3618       unsigned LocSizeInBits = VA.getLocVT().getSizeInBits();
3619       Val = DAG.getNode(
3620           ISD::SHL, DL, VA.getLocVT(), Val,
3621           DAG.getConstant(LocSizeInBits - ValSizeInBits, DL, VA.getLocVT()));
3622     }
3623 
3624     Chain = DAG.getCopyToReg(Chain, DL, VA.getLocReg(), Val, Flag);
3625 
3626     // Guarantee that all emitted copies are stuck together with flags.
3627     Flag = Chain.getValue(1);
3628     RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
3629   }
3630 
3631   // The mips ABIs for returning structs by value requires that we copy
3632   // the sret argument into $v0 for the return. We saved the argument into
3633   // a virtual register in the entry block, so now we copy the value out
3634   // and into $v0.
3635   if (MF.getFunction().hasStructRetAttr()) {
3636     MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
3637     unsigned Reg = MipsFI->getSRetReturnReg();
3638 
3639     if (!Reg)
3640       llvm_unreachable("sret virtual register not created in the entry block");
3641     SDValue Val =
3642         DAG.getCopyFromReg(Chain, DL, Reg, getPointerTy(DAG.getDataLayout()));
3643     unsigned V0 = ABI.IsN64() ? Mips::V0_64 : Mips::V0;
3644 
3645     Chain = DAG.getCopyToReg(Chain, DL, V0, Val, Flag);
3646     Flag = Chain.getValue(1);
3647     RetOps.push_back(DAG.getRegister(V0, getPointerTy(DAG.getDataLayout())));
3648   }
3649 
3650   RetOps[0] = Chain;  // Update chain.
3651 
3652   // Add the flag if we have it.
3653   if (Flag.getNode())
3654     RetOps.push_back(Flag);
3655 
3656   // ISRs must use "eret".
3657   if (DAG.getMachineFunction().getFunction().hasFnAttribute("interrupt"))
3658     return LowerInterruptReturn(RetOps, DL, DAG);
3659 
3660   // Standard return on Mips is a "jr $ra"
3661   return DAG.getNode(MipsISD::Ret, DL, MVT::Other, RetOps);
3662 }
3663 
3664 //===----------------------------------------------------------------------===//
3665 //                           Mips Inline Assembly Support
3666 //===----------------------------------------------------------------------===//
3667 
3668 /// getConstraintType - Given a constraint letter, return the type of
3669 /// constraint it is for this target.
3670 MipsTargetLowering::ConstraintType
3671 MipsTargetLowering::getConstraintType(StringRef Constraint) const {
3672   // Mips specific constraints
3673   // GCC config/mips/constraints.md
3674   //
3675   // 'd' : An address register. Equivalent to r
3676   //       unless generating MIPS16 code.
3677   // 'y' : Equivalent to r; retained for
3678   //       backwards compatibility.
3679   // 'c' : A register suitable for use in an indirect
3680   //       jump. This will always be $25 for -mabicalls.
3681   // 'l' : The lo register. 1 word storage.
3682   // 'x' : The hilo register pair. Double word storage.
3683   if (Constraint.size() == 1) {
3684     switch (Constraint[0]) {
3685       default : break;
3686       case 'd':
3687       case 'y':
3688       case 'f':
3689       case 'c':
3690       case 'l':
3691       case 'x':
3692         return C_RegisterClass;
3693       case 'R':
3694         return C_Memory;
3695     }
3696   }
3697 
3698   if (Constraint == "ZC")
3699     return C_Memory;
3700 
3701   return TargetLowering::getConstraintType(Constraint);
3702 }
3703 
3704 /// Examine constraint type and operand type and determine a weight value.
3705 /// This object must already have been set up with the operand type
3706 /// and the current alternative constraint selected.
3707 TargetLowering::ConstraintWeight
3708 MipsTargetLowering::getSingleConstraintMatchWeight(
3709     AsmOperandInfo &info, const char *constraint) const {
3710   ConstraintWeight weight = CW_Invalid;
3711   Value *CallOperandVal = info.CallOperandVal;
3712     // If we don't have a value, we can't do a match,
3713     // but allow it at the lowest weight.
3714   if (!CallOperandVal)
3715     return CW_Default;
3716   Type *type = CallOperandVal->getType();
3717   // Look at the constraint type.
3718   switch (*constraint) {
3719   default:
3720     weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint);
3721     break;
3722   case 'd':
3723   case 'y':
3724     if (type->isIntegerTy())
3725       weight = CW_Register;
3726     break;
3727   case 'f': // FPU or MSA register
3728     if (Subtarget.hasMSA() && type->isVectorTy() &&
3729         cast<VectorType>(type)->getBitWidth() == 128)
3730       weight = CW_Register;
3731     else if (type->isFloatTy())
3732       weight = CW_Register;
3733     break;
3734   case 'c': // $25 for indirect jumps
3735   case 'l': // lo register
3736   case 'x': // hilo register pair
3737     if (type->isIntegerTy())
3738       weight = CW_SpecificReg;
3739     break;
3740   case 'I': // signed 16 bit immediate
3741   case 'J': // integer zero
3742   case 'K': // unsigned 16 bit immediate
3743   case 'L': // signed 32 bit immediate where lower 16 bits are 0
3744   case 'N': // immediate in the range of -65535 to -1 (inclusive)
3745   case 'O': // signed 15 bit immediate (+- 16383)
3746   case 'P': // immediate in the range of 65535 to 1 (inclusive)
3747     if (isa<ConstantInt>(CallOperandVal))
3748       weight = CW_Constant;
3749     break;
3750   case 'R':
3751     weight = CW_Memory;
3752     break;
3753   }
3754   return weight;
3755 }
3756 
3757 /// This is a helper function to parse a physical register string and split it
3758 /// into non-numeric and numeric parts (Prefix and Reg). The first boolean flag
3759 /// that is returned indicates whether parsing was successful. The second flag
3760 /// is true if the numeric part exists.
3761 static std::pair<bool, bool> parsePhysicalReg(StringRef C, StringRef &Prefix,
3762                                               unsigned long long &Reg) {
3763   if (C.front() != '{' || C.back() != '}')
3764     return std::make_pair(false, false);
3765 
3766   // Search for the first numeric character.
3767   StringRef::const_iterator I, B = C.begin() + 1, E = C.end() - 1;
3768   I = std::find_if(B, E, isdigit);
3769 
3770   Prefix = StringRef(B, I - B);
3771 
3772   // The second flag is set to false if no numeric characters were found.
3773   if (I == E)
3774     return std::make_pair(true, false);
3775 
3776   // Parse the numeric characters.
3777   return std::make_pair(!getAsUnsignedInteger(StringRef(I, E - I), 10, Reg),
3778                         true);
3779 }
3780 
3781 std::pair<unsigned, const TargetRegisterClass *> MipsTargetLowering::
3782 parseRegForInlineAsmConstraint(StringRef C, MVT VT) const {
3783   const TargetRegisterInfo *TRI =
3784       Subtarget.getRegisterInfo();
3785   const TargetRegisterClass *RC;
3786   StringRef Prefix;
3787   unsigned long long Reg;
3788 
3789   std::pair<bool, bool> R = parsePhysicalReg(C, Prefix, Reg);
3790 
3791   if (!R.first)
3792     return std::make_pair(0U, nullptr);
3793 
3794   if ((Prefix == "hi" || Prefix == "lo")) { // Parse hi/lo.
3795     // No numeric characters follow "hi" or "lo".
3796     if (R.second)
3797       return std::make_pair(0U, nullptr);
3798 
3799     RC = TRI->getRegClass(Prefix == "hi" ?
3800                           Mips::HI32RegClassID : Mips::LO32RegClassID);
3801     return std::make_pair(*(RC->begin()), RC);
3802   } else if (Prefix.startswith("$msa")) {
3803     // Parse $msa(ir|csr|access|save|modify|request|map|unmap)
3804 
3805     // No numeric characters follow the name.
3806     if (R.second)
3807       return std::make_pair(0U, nullptr);
3808 
3809     Reg = StringSwitch<unsigned long long>(Prefix)
3810               .Case("$msair", Mips::MSAIR)
3811               .Case("$msacsr", Mips::MSACSR)
3812               .Case("$msaaccess", Mips::MSAAccess)
3813               .Case("$msasave", Mips::MSASave)
3814               .Case("$msamodify", Mips::MSAModify)
3815               .Case("$msarequest", Mips::MSARequest)
3816               .Case("$msamap", Mips::MSAMap)
3817               .Case("$msaunmap", Mips::MSAUnmap)
3818               .Default(0);
3819 
3820     if (!Reg)
3821       return std::make_pair(0U, nullptr);
3822 
3823     RC = TRI->getRegClass(Mips::MSACtrlRegClassID);
3824     return std::make_pair(Reg, RC);
3825   }
3826 
3827   if (!R.second)
3828     return std::make_pair(0U, nullptr);
3829 
3830   if (Prefix == "$f") { // Parse $f0-$f31.
3831     // If the size of FP registers is 64-bit or Reg is an even number, select
3832     // the 64-bit register class. Otherwise, select the 32-bit register class.
3833     if (VT == MVT::Other)
3834       VT = (Subtarget.isFP64bit() || !(Reg % 2)) ? MVT::f64 : MVT::f32;
3835 
3836     RC = getRegClassFor(VT);
3837 
3838     if (RC == &Mips::AFGR64RegClass) {
3839       assert(Reg % 2 == 0);
3840       Reg >>= 1;
3841     }
3842   } else if (Prefix == "$fcc") // Parse $fcc0-$fcc7.
3843     RC = TRI->getRegClass(Mips::FCCRegClassID);
3844   else if (Prefix == "$w") { // Parse $w0-$w31.
3845     RC = getRegClassFor((VT == MVT::Other) ? MVT::v16i8 : VT);
3846   } else { // Parse $0-$31.
3847     assert(Prefix == "$");
3848     RC = getRegClassFor((VT == MVT::Other) ? MVT::i32 : VT);
3849   }
3850 
3851   assert(Reg < RC->getNumRegs());
3852   return std::make_pair(*(RC->begin() + Reg), RC);
3853 }
3854 
3855 /// Given a register class constraint, like 'r', if this corresponds directly
3856 /// to an LLVM register class, return a register of 0 and the register class
3857 /// pointer.
3858 std::pair<unsigned, const TargetRegisterClass *>
3859 MipsTargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
3860                                                  StringRef Constraint,
3861                                                  MVT VT) const {
3862   if (Constraint.size() == 1) {
3863     switch (Constraint[0]) {
3864     case 'd': // Address register. Same as 'r' unless generating MIPS16 code.
3865     case 'y': // Same as 'r'. Exists for compatibility.
3866     case 'r':
3867       if (VT == MVT::i32 || VT == MVT::i16 || VT == MVT::i8) {
3868         if (Subtarget.inMips16Mode())
3869           return std::make_pair(0U, &Mips::CPU16RegsRegClass);
3870         return std::make_pair(0U, &Mips::GPR32RegClass);
3871       }
3872       if (VT == MVT::i64 && !Subtarget.isGP64bit())
3873         return std::make_pair(0U, &Mips::GPR32RegClass);
3874       if (VT == MVT::i64 && Subtarget.isGP64bit())
3875         return std::make_pair(0U, &Mips::GPR64RegClass);
3876       // This will generate an error message
3877       return std::make_pair(0U, nullptr);
3878     case 'f': // FPU or MSA register
3879       if (VT == MVT::v16i8)
3880         return std::make_pair(0U, &Mips::MSA128BRegClass);
3881       else if (VT == MVT::v8i16 || VT == MVT::v8f16)
3882         return std::make_pair(0U, &Mips::MSA128HRegClass);
3883       else if (VT == MVT::v4i32 || VT == MVT::v4f32)
3884         return std::make_pair(0U, &Mips::MSA128WRegClass);
3885       else if (VT == MVT::v2i64 || VT == MVT::v2f64)
3886         return std::make_pair(0U, &Mips::MSA128DRegClass);
3887       else if (VT == MVT::f32)
3888         return std::make_pair(0U, &Mips::FGR32RegClass);
3889       else if ((VT == MVT::f64) && (!Subtarget.isSingleFloat())) {
3890         if (Subtarget.isFP64bit())
3891           return std::make_pair(0U, &Mips::FGR64RegClass);
3892         return std::make_pair(0U, &Mips::AFGR64RegClass);
3893       }
3894       break;
3895     case 'c': // register suitable for indirect jump
3896       if (VT == MVT::i32)
3897         return std::make_pair((unsigned)Mips::T9, &Mips::GPR32RegClass);
3898       if (VT == MVT::i64)
3899         return std::make_pair((unsigned)Mips::T9_64, &Mips::GPR64RegClass);
3900       // This will generate an error message
3901       return std::make_pair(0U, nullptr);
3902     case 'l': // use the `lo` register to store values
3903               // that are no bigger than a word
3904       if (VT == MVT::i32 || VT == MVT::i16 || VT == MVT::i8)
3905         return std::make_pair((unsigned)Mips::LO0, &Mips::LO32RegClass);
3906       return std::make_pair((unsigned)Mips::LO0_64, &Mips::LO64RegClass);
3907     case 'x': // use the concatenated `hi` and `lo` registers
3908               // to store doubleword values
3909       // Fixme: Not triggering the use of both hi and low
3910       // This will generate an error message
3911       return std::make_pair(0U, nullptr);
3912     }
3913   }
3914 
3915   std::pair<unsigned, const TargetRegisterClass *> R;
3916   R = parseRegForInlineAsmConstraint(Constraint, VT);
3917 
3918   if (R.second)
3919     return R;
3920 
3921   return TargetLowering::getRegForInlineAsmConstraint(TRI, Constraint, VT);
3922 }
3923 
3924 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
3925 /// vector.  If it is invalid, don't add anything to Ops.
3926 void MipsTargetLowering::LowerAsmOperandForConstraint(SDValue Op,
3927                                                      std::string &Constraint,
3928                                                      std::vector<SDValue>&Ops,
3929                                                      SelectionDAG &DAG) const {
3930   SDLoc DL(Op);
3931   SDValue Result;
3932 
3933   // Only support length 1 constraints for now.
3934   if (Constraint.length() > 1) return;
3935 
3936   char ConstraintLetter = Constraint[0];
3937   switch (ConstraintLetter) {
3938   default: break; // This will fall through to the generic implementation
3939   case 'I': // Signed 16 bit constant
3940     // If this fails, the parent routine will give an error
3941     if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
3942       EVT Type = Op.getValueType();
3943       int64_t Val = C->getSExtValue();
3944       if (isInt<16>(Val)) {
3945         Result = DAG.getTargetConstant(Val, DL, Type);
3946         break;
3947       }
3948     }
3949     return;
3950   case 'J': // integer zero
3951     if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
3952       EVT Type = Op.getValueType();
3953       int64_t Val = C->getZExtValue();
3954       if (Val == 0) {
3955         Result = DAG.getTargetConstant(0, DL, Type);
3956         break;
3957       }
3958     }
3959     return;
3960   case 'K': // unsigned 16 bit immediate
3961     if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
3962       EVT Type = Op.getValueType();
3963       uint64_t Val = (uint64_t)C->getZExtValue();
3964       if (isUInt<16>(Val)) {
3965         Result = DAG.getTargetConstant(Val, DL, Type);
3966         break;
3967       }
3968     }
3969     return;
3970   case 'L': // signed 32 bit immediate where lower 16 bits are 0
3971     if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
3972       EVT Type = Op.getValueType();
3973       int64_t Val = C->getSExtValue();
3974       if ((isInt<32>(Val)) && ((Val & 0xffff) == 0)){
3975         Result = DAG.getTargetConstant(Val, DL, Type);
3976         break;
3977       }
3978     }
3979     return;
3980   case 'N': // immediate in the range of -65535 to -1 (inclusive)
3981     if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
3982       EVT Type = Op.getValueType();
3983       int64_t Val = C->getSExtValue();
3984       if ((Val >= -65535) && (Val <= -1)) {
3985         Result = DAG.getTargetConstant(Val, DL, Type);
3986         break;
3987       }
3988     }
3989     return;
3990   case 'O': // signed 15 bit immediate
3991     if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
3992       EVT Type = Op.getValueType();
3993       int64_t Val = C->getSExtValue();
3994       if ((isInt<15>(Val))) {
3995         Result = DAG.getTargetConstant(Val, DL, Type);
3996         break;
3997       }
3998     }
3999     return;
4000   case 'P': // immediate in the range of 1 to 65535 (inclusive)
4001     if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
4002       EVT Type = Op.getValueType();
4003       int64_t Val = C->getSExtValue();
4004       if ((Val <= 65535) && (Val >= 1)) {
4005         Result = DAG.getTargetConstant(Val, DL, Type);
4006         break;
4007       }
4008     }
4009     return;
4010   }
4011 
4012   if (Result.getNode()) {
4013     Ops.push_back(Result);
4014     return;
4015   }
4016 
4017   TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
4018 }
4019 
4020 bool MipsTargetLowering::isLegalAddressingMode(const DataLayout &DL,
4021                                                const AddrMode &AM, Type *Ty,
4022                                                unsigned AS, Instruction *I) const {
4023   // No global is ever allowed as a base.
4024   if (AM.BaseGV)
4025     return false;
4026 
4027   switch (AM.Scale) {
4028   case 0: // "r+i" or just "i", depending on HasBaseReg.
4029     break;
4030   case 1:
4031     if (!AM.HasBaseReg) // allow "r+i".
4032       break;
4033     return false; // disallow "r+r" or "r+r+i".
4034   default:
4035     return false;
4036   }
4037 
4038   return true;
4039 }
4040 
4041 bool
4042 MipsTargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const {
4043   // The Mips target isn't yet aware of offsets.
4044   return false;
4045 }
4046 
4047 EVT MipsTargetLowering::getOptimalMemOpType(uint64_t Size, unsigned DstAlign,
4048                                             unsigned SrcAlign,
4049                                             bool IsMemset, bool ZeroMemset,
4050                                             bool MemcpyStrSrc,
4051                                             MachineFunction &MF) const {
4052   if (Subtarget.hasMips64())
4053     return MVT::i64;
4054 
4055   return MVT::i32;
4056 }
4057 
4058 bool MipsTargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
4059   if (VT != MVT::f32 && VT != MVT::f64)
4060     return false;
4061   if (Imm.isNegZero())
4062     return false;
4063   return Imm.isZero();
4064 }
4065 
4066 unsigned MipsTargetLowering::getJumpTableEncoding() const {
4067 
4068   // FIXME: For space reasons this should be: EK_GPRel32BlockAddress.
4069   if (ABI.IsN64() && isPositionIndependent())
4070     return MachineJumpTableInfo::EK_GPRel64BlockAddress;
4071 
4072   return TargetLowering::getJumpTableEncoding();
4073 }
4074 
4075 bool MipsTargetLowering::useSoftFloat() const {
4076   return Subtarget.useSoftFloat();
4077 }
4078 
4079 void MipsTargetLowering::copyByValRegs(
4080     SDValue Chain, const SDLoc &DL, std::vector<SDValue> &OutChains,
4081     SelectionDAG &DAG, const ISD::ArgFlagsTy &Flags,
4082     SmallVectorImpl<SDValue> &InVals, const Argument *FuncArg,
4083     unsigned FirstReg, unsigned LastReg, const CCValAssign &VA,
4084     MipsCCState &State) const {
4085   MachineFunction &MF = DAG.getMachineFunction();
4086   MachineFrameInfo &MFI = MF.getFrameInfo();
4087   unsigned GPRSizeInBytes = Subtarget.getGPRSizeInBytes();
4088   unsigned NumRegs = LastReg - FirstReg;
4089   unsigned RegAreaSize = NumRegs * GPRSizeInBytes;
4090   unsigned FrameObjSize = std::max(Flags.getByValSize(), RegAreaSize);
4091   int FrameObjOffset;
4092   ArrayRef<MCPhysReg> ByValArgRegs = ABI.GetByValArgRegs();
4093 
4094   if (RegAreaSize)
4095     FrameObjOffset =
4096         (int)ABI.GetCalleeAllocdArgSizeInBytes(State.getCallingConv()) -
4097         (int)((ByValArgRegs.size() - FirstReg) * GPRSizeInBytes);
4098   else
4099     FrameObjOffset = VA.getLocMemOffset();
4100 
4101   // Create frame object.
4102   EVT PtrTy = getPointerTy(DAG.getDataLayout());
4103   // Make the fixed object stored to mutable so that the load instructions
4104   // referencing it have their memory dependencies added.
4105   // Set the frame object as isAliased which clears the underlying objects
4106   // vector in ScheduleDAGInstrs::buildSchedGraph() resulting in addition of all
4107   // stores as dependencies for loads referencing this fixed object.
4108   int FI = MFI.CreateFixedObject(FrameObjSize, FrameObjOffset, false, true);
4109   SDValue FIN = DAG.getFrameIndex(FI, PtrTy);
4110   InVals.push_back(FIN);
4111 
4112   if (!NumRegs)
4113     return;
4114 
4115   // Copy arg registers.
4116   MVT RegTy = MVT::getIntegerVT(GPRSizeInBytes * 8);
4117   const TargetRegisterClass *RC = getRegClassFor(RegTy);
4118 
4119   for (unsigned I = 0; I < NumRegs; ++I) {
4120     unsigned ArgReg = ByValArgRegs[FirstReg + I];
4121     unsigned VReg = addLiveIn(MF, ArgReg, RC);
4122     unsigned Offset = I * GPRSizeInBytes;
4123     SDValue StorePtr = DAG.getNode(ISD::ADD, DL, PtrTy, FIN,
4124                                    DAG.getConstant(Offset, DL, PtrTy));
4125     SDValue Store = DAG.getStore(Chain, DL, DAG.getRegister(VReg, RegTy),
4126                                  StorePtr, MachinePointerInfo(FuncArg, Offset));
4127     OutChains.push_back(Store);
4128   }
4129 }
4130 
4131 // Copy byVal arg to registers and stack.
4132 void MipsTargetLowering::passByValArg(
4133     SDValue Chain, const SDLoc &DL,
4134     std::deque<std::pair<unsigned, SDValue>> &RegsToPass,
4135     SmallVectorImpl<SDValue> &MemOpChains, SDValue StackPtr,
4136     MachineFrameInfo &MFI, SelectionDAG &DAG, SDValue Arg, unsigned FirstReg,
4137     unsigned LastReg, const ISD::ArgFlagsTy &Flags, bool isLittle,
4138     const CCValAssign &VA) const {
4139   unsigned ByValSizeInBytes = Flags.getByValSize();
4140   unsigned OffsetInBytes = 0; // From beginning of struct
4141   unsigned RegSizeInBytes = Subtarget.getGPRSizeInBytes();
4142   unsigned Alignment = std::min(Flags.getByValAlign(), RegSizeInBytes);
4143   EVT PtrTy = getPointerTy(DAG.getDataLayout()),
4144       RegTy = MVT::getIntegerVT(RegSizeInBytes * 8);
4145   unsigned NumRegs = LastReg - FirstReg;
4146 
4147   if (NumRegs) {
4148     ArrayRef<MCPhysReg> ArgRegs = ABI.GetByValArgRegs();
4149     bool LeftoverBytes = (NumRegs * RegSizeInBytes > ByValSizeInBytes);
4150     unsigned I = 0;
4151 
4152     // Copy words to registers.
4153     for (; I < NumRegs - LeftoverBytes; ++I, OffsetInBytes += RegSizeInBytes) {
4154       SDValue LoadPtr = DAG.getNode(ISD::ADD, DL, PtrTy, Arg,
4155                                     DAG.getConstant(OffsetInBytes, DL, PtrTy));
4156       SDValue LoadVal = DAG.getLoad(RegTy, DL, Chain, LoadPtr,
4157                                     MachinePointerInfo(), Alignment);
4158       MemOpChains.push_back(LoadVal.getValue(1));
4159       unsigned ArgReg = ArgRegs[FirstReg + I];
4160       RegsToPass.push_back(std::make_pair(ArgReg, LoadVal));
4161     }
4162 
4163     // Return if the struct has been fully copied.
4164     if (ByValSizeInBytes == OffsetInBytes)
4165       return;
4166 
4167     // Copy the remainder of the byval argument with sub-word loads and shifts.
4168     if (LeftoverBytes) {
4169       SDValue Val;
4170 
4171       for (unsigned LoadSizeInBytes = RegSizeInBytes / 2, TotalBytesLoaded = 0;
4172            OffsetInBytes < ByValSizeInBytes; LoadSizeInBytes /= 2) {
4173         unsigned RemainingSizeInBytes = ByValSizeInBytes - OffsetInBytes;
4174 
4175         if (RemainingSizeInBytes < LoadSizeInBytes)
4176           continue;
4177 
4178         // Load subword.
4179         SDValue LoadPtr = DAG.getNode(ISD::ADD, DL, PtrTy, Arg,
4180                                       DAG.getConstant(OffsetInBytes, DL,
4181                                                       PtrTy));
4182         SDValue LoadVal = DAG.getExtLoad(
4183             ISD::ZEXTLOAD, DL, RegTy, Chain, LoadPtr, MachinePointerInfo(),
4184             MVT::getIntegerVT(LoadSizeInBytes * 8), Alignment);
4185         MemOpChains.push_back(LoadVal.getValue(1));
4186 
4187         // Shift the loaded value.
4188         unsigned Shamt;
4189 
4190         if (isLittle)
4191           Shamt = TotalBytesLoaded * 8;
4192         else
4193           Shamt = (RegSizeInBytes - (TotalBytesLoaded + LoadSizeInBytes)) * 8;
4194 
4195         SDValue Shift = DAG.getNode(ISD::SHL, DL, RegTy, LoadVal,
4196                                     DAG.getConstant(Shamt, DL, MVT::i32));
4197 
4198         if (Val.getNode())
4199           Val = DAG.getNode(ISD::OR, DL, RegTy, Val, Shift);
4200         else
4201           Val = Shift;
4202 
4203         OffsetInBytes += LoadSizeInBytes;
4204         TotalBytesLoaded += LoadSizeInBytes;
4205         Alignment = std::min(Alignment, LoadSizeInBytes);
4206       }
4207 
4208       unsigned ArgReg = ArgRegs[FirstReg + I];
4209       RegsToPass.push_back(std::make_pair(ArgReg, Val));
4210       return;
4211     }
4212   }
4213 
4214   // Copy remainder of byval arg to it with memcpy.
4215   unsigned MemCpySize = ByValSizeInBytes - OffsetInBytes;
4216   SDValue Src = DAG.getNode(ISD::ADD, DL, PtrTy, Arg,
4217                             DAG.getConstant(OffsetInBytes, DL, PtrTy));
4218   SDValue Dst = DAG.getNode(ISD::ADD, DL, PtrTy, StackPtr,
4219                             DAG.getIntPtrConstant(VA.getLocMemOffset(), DL));
4220   Chain = DAG.getMemcpy(Chain, DL, Dst, Src,
4221                         DAG.getConstant(MemCpySize, DL, PtrTy),
4222                         Alignment, /*isVolatile=*/false, /*AlwaysInline=*/false,
4223                         /*isTailCall=*/false,
4224                         MachinePointerInfo(), MachinePointerInfo());
4225   MemOpChains.push_back(Chain);
4226 }
4227 
4228 void MipsTargetLowering::writeVarArgRegs(std::vector<SDValue> &OutChains,
4229                                          SDValue Chain, const SDLoc &DL,
4230                                          SelectionDAG &DAG,
4231                                          CCState &State) const {
4232   ArrayRef<MCPhysReg> ArgRegs = ABI.GetVarArgRegs();
4233   unsigned Idx = State.getFirstUnallocated(ArgRegs);
4234   unsigned RegSizeInBytes = Subtarget.getGPRSizeInBytes();
4235   MVT RegTy = MVT::getIntegerVT(RegSizeInBytes * 8);
4236   const TargetRegisterClass *RC = getRegClassFor(RegTy);
4237   MachineFunction &MF = DAG.getMachineFunction();
4238   MachineFrameInfo &MFI = MF.getFrameInfo();
4239   MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
4240 
4241   // Offset of the first variable argument from stack pointer.
4242   int VaArgOffset;
4243 
4244   if (ArgRegs.size() == Idx)
4245     VaArgOffset = alignTo(State.getNextStackOffset(), RegSizeInBytes);
4246   else {
4247     VaArgOffset =
4248         (int)ABI.GetCalleeAllocdArgSizeInBytes(State.getCallingConv()) -
4249         (int)(RegSizeInBytes * (ArgRegs.size() - Idx));
4250   }
4251 
4252   // Record the frame index of the first variable argument
4253   // which is a value necessary to VASTART.
4254   int FI = MFI.CreateFixedObject(RegSizeInBytes, VaArgOffset, true);
4255   MipsFI->setVarArgsFrameIndex(FI);
4256 
4257   // Copy the integer registers that have not been used for argument passing
4258   // to the argument register save area. For O32, the save area is allocated
4259   // in the caller's stack frame, while for N32/64, it is allocated in the
4260   // callee's stack frame.
4261   for (unsigned I = Idx; I < ArgRegs.size();
4262        ++I, VaArgOffset += RegSizeInBytes) {
4263     unsigned Reg = addLiveIn(MF, ArgRegs[I], RC);
4264     SDValue ArgValue = DAG.getCopyFromReg(Chain, DL, Reg, RegTy);
4265     FI = MFI.CreateFixedObject(RegSizeInBytes, VaArgOffset, true);
4266     SDValue PtrOff = DAG.getFrameIndex(FI, getPointerTy(DAG.getDataLayout()));
4267     SDValue Store =
4268         DAG.getStore(Chain, DL, ArgValue, PtrOff, MachinePointerInfo());
4269     cast<StoreSDNode>(Store.getNode())->getMemOperand()->setValue(
4270         (Value *)nullptr);
4271     OutChains.push_back(Store);
4272   }
4273 }
4274 
4275 void MipsTargetLowering::HandleByVal(CCState *State, unsigned &Size,
4276                                      unsigned Align) const {
4277   const TargetFrameLowering *TFL = Subtarget.getFrameLowering();
4278 
4279   assert(Size && "Byval argument's size shouldn't be 0.");
4280 
4281   Align = std::min(Align, TFL->getStackAlignment());
4282 
4283   unsigned FirstReg = 0;
4284   unsigned NumRegs = 0;
4285 
4286   if (State->getCallingConv() != CallingConv::Fast) {
4287     unsigned RegSizeInBytes = Subtarget.getGPRSizeInBytes();
4288     ArrayRef<MCPhysReg> IntArgRegs = ABI.GetByValArgRegs();
4289     // FIXME: The O32 case actually describes no shadow registers.
4290     const MCPhysReg *ShadowRegs =
4291         ABI.IsO32() ? IntArgRegs.data() : Mips64DPRegs;
4292 
4293     // We used to check the size as well but we can't do that anymore since
4294     // CCState::HandleByVal() rounds up the size after calling this function.
4295     assert(!(Align % RegSizeInBytes) &&
4296            "Byval argument's alignment should be a multiple of"
4297            "RegSizeInBytes.");
4298 
4299     FirstReg = State->getFirstUnallocated(IntArgRegs);
4300 
4301     // If Align > RegSizeInBytes, the first arg register must be even.
4302     // FIXME: This condition happens to do the right thing but it's not the
4303     //        right way to test it. We want to check that the stack frame offset
4304     //        of the register is aligned.
4305     if ((Align > RegSizeInBytes) && (FirstReg % 2)) {
4306       State->AllocateReg(IntArgRegs[FirstReg], ShadowRegs[FirstReg]);
4307       ++FirstReg;
4308     }
4309 
4310     // Mark the registers allocated.
4311     Size = alignTo(Size, RegSizeInBytes);
4312     for (unsigned I = FirstReg; Size > 0 && (I < IntArgRegs.size());
4313          Size -= RegSizeInBytes, ++I, ++NumRegs)
4314       State->AllocateReg(IntArgRegs[I], ShadowRegs[I]);
4315   }
4316 
4317   State->addInRegsParamInfo(FirstReg, FirstReg + NumRegs);
4318 }
4319 
4320 MachineBasicBlock *MipsTargetLowering::emitPseudoSELECT(MachineInstr &MI,
4321                                                         MachineBasicBlock *BB,
4322                                                         bool isFPCmp,
4323                                                         unsigned Opc) const {
4324   assert(!(Subtarget.hasMips4() || Subtarget.hasMips32()) &&
4325          "Subtarget already supports SELECT nodes with the use of"
4326          "conditional-move instructions.");
4327 
4328   const TargetInstrInfo *TII =
4329       Subtarget.getInstrInfo();
4330   DebugLoc DL = MI.getDebugLoc();
4331 
4332   // To "insert" a SELECT instruction, we actually have to insert the
4333   // diamond control-flow pattern.  The incoming instruction knows the
4334   // destination vreg to set, the condition code register to branch on, the
4335   // true/false values to select between, and a branch opcode to use.
4336   const BasicBlock *LLVM_BB = BB->getBasicBlock();
4337   MachineFunction::iterator It = ++BB->getIterator();
4338 
4339   //  thisMBB:
4340   //  ...
4341   //   TrueVal = ...
4342   //   setcc r1, r2, r3
4343   //   bNE   r1, r0, copy1MBB
4344   //   fallthrough --> copy0MBB
4345   MachineBasicBlock *thisMBB  = BB;
4346   MachineFunction *F = BB->getParent();
4347   MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
4348   MachineBasicBlock *sinkMBB  = F->CreateMachineBasicBlock(LLVM_BB);
4349   F->insert(It, copy0MBB);
4350   F->insert(It, sinkMBB);
4351 
4352   // Transfer the remainder of BB and its successor edges to sinkMBB.
4353   sinkMBB->splice(sinkMBB->begin(), BB,
4354                   std::next(MachineBasicBlock::iterator(MI)), BB->end());
4355   sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
4356 
4357   // Next, add the true and fallthrough blocks as its successors.
4358   BB->addSuccessor(copy0MBB);
4359   BB->addSuccessor(sinkMBB);
4360 
4361   if (isFPCmp) {
4362     // bc1[tf] cc, sinkMBB
4363     BuildMI(BB, DL, TII->get(Opc))
4364         .addReg(MI.getOperand(1).getReg())
4365         .addMBB(sinkMBB);
4366   } else {
4367     // bne rs, $0, sinkMBB
4368     BuildMI(BB, DL, TII->get(Opc))
4369         .addReg(MI.getOperand(1).getReg())
4370         .addReg(Mips::ZERO)
4371         .addMBB(sinkMBB);
4372   }
4373 
4374   //  copy0MBB:
4375   //   %FalseValue = ...
4376   //   # fallthrough to sinkMBB
4377   BB = copy0MBB;
4378 
4379   // Update machine-CFG edges
4380   BB->addSuccessor(sinkMBB);
4381 
4382   //  sinkMBB:
4383   //   %Result = phi [ %TrueValue, thisMBB ], [ %FalseValue, copy0MBB ]
4384   //  ...
4385   BB = sinkMBB;
4386 
4387   BuildMI(*BB, BB->begin(), DL, TII->get(Mips::PHI), MI.getOperand(0).getReg())
4388       .addReg(MI.getOperand(2).getReg())
4389       .addMBB(thisMBB)
4390       .addReg(MI.getOperand(3).getReg())
4391       .addMBB(copy0MBB);
4392 
4393   MI.eraseFromParent(); // The pseudo instruction is gone now.
4394 
4395   return BB;
4396 }
4397 
4398 // FIXME? Maybe this could be a TableGen attribute on some registers and
4399 // this table could be generated automatically from RegInfo.
4400 unsigned MipsTargetLowering::getRegisterByName(const char* RegName, EVT VT,
4401                                                SelectionDAG &DAG) const {
4402   // Named registers is expected to be fairly rare. For now, just support $28
4403   // since the linux kernel uses it.
4404   if (Subtarget.isGP64bit()) {
4405     unsigned Reg = StringSwitch<unsigned>(RegName)
4406                          .Case("$28", Mips::GP_64)
4407                          .Default(0);
4408     if (Reg)
4409       return Reg;
4410   } else {
4411     unsigned Reg = StringSwitch<unsigned>(RegName)
4412                          .Case("$28", Mips::GP)
4413                          .Default(0);
4414     if (Reg)
4415       return Reg;
4416   }
4417   report_fatal_error("Invalid register name global variable");
4418 }
4419