1 //===-- MipsISelLowering.cpp - Mips DAG Lowering Implementation -----------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file defines the interfaces that Mips uses to lower LLVM code into a 11 // selection DAG. 12 // 13 //===----------------------------------------------------------------------===// 14 15 #define DEBUG_TYPE "mips-lower" 16 #include "MipsISelLowering.h" 17 #include "MipsMachineFunction.h" 18 #include "MipsTargetMachine.h" 19 #include "MipsTargetObjectFile.h" 20 #include "MipsSubtarget.h" 21 #include "llvm/DerivedTypes.h" 22 #include "llvm/Function.h" 23 #include "llvm/GlobalVariable.h" 24 #include "llvm/Intrinsics.h" 25 #include "llvm/CallingConv.h" 26 #include "InstPrinter/MipsInstPrinter.h" 27 #include "llvm/CodeGen/CallingConvLower.h" 28 #include "llvm/CodeGen/MachineFrameInfo.h" 29 #include "llvm/CodeGen/MachineFunction.h" 30 #include "llvm/CodeGen/MachineInstrBuilder.h" 31 #include "llvm/CodeGen/MachineRegisterInfo.h" 32 #include "llvm/CodeGen/SelectionDAGISel.h" 33 #include "llvm/CodeGen/ValueTypes.h" 34 #include "llvm/Support/Debug.h" 35 #include "llvm/Support/ErrorHandling.h" 36 using namespace llvm; 37 38 // If I is a shifted mask, set the size (Size) and the first bit of the 39 // mask (Pos), and return true. 40 // For example, if I is 0x003ff800, (Pos, Size) = (11, 11). 41 static bool IsShiftedMask(uint64_t I, uint64_t &Pos, uint64_t &Size) { 42 if (!isUInt<32>(I) || !isShiftedMask_32(I)) 43 return false; 44 45 Size = CountPopulation_32(I); 46 Pos = CountTrailingZeros_32(I); 47 return true; 48 } 49 50 const char *MipsTargetLowering::getTargetNodeName(unsigned Opcode) const { 51 switch (Opcode) { 52 case MipsISD::JmpLink: return "MipsISD::JmpLink"; 53 case MipsISD::Hi: return "MipsISD::Hi"; 54 case MipsISD::Lo: return "MipsISD::Lo"; 55 case MipsISD::GPRel: return "MipsISD::GPRel"; 56 case MipsISD::TlsGd: return "MipsISD::TlsGd"; 57 case MipsISD::TprelHi: return "MipsISD::TprelHi"; 58 case MipsISD::TprelLo: return "MipsISD::TprelLo"; 59 case MipsISD::ThreadPointer: return "MipsISD::ThreadPointer"; 60 case MipsISD::Ret: return "MipsISD::Ret"; 61 case MipsISD::FPBrcond: return "MipsISD::FPBrcond"; 62 case MipsISD::FPCmp: return "MipsISD::FPCmp"; 63 case MipsISD::CMovFP_T: return "MipsISD::CMovFP_T"; 64 case MipsISD::CMovFP_F: return "MipsISD::CMovFP_F"; 65 case MipsISD::FPRound: return "MipsISD::FPRound"; 66 case MipsISD::MAdd: return "MipsISD::MAdd"; 67 case MipsISD::MAddu: return "MipsISD::MAddu"; 68 case MipsISD::MSub: return "MipsISD::MSub"; 69 case MipsISD::MSubu: return "MipsISD::MSubu"; 70 case MipsISD::DivRem: return "MipsISD::DivRem"; 71 case MipsISD::DivRemU: return "MipsISD::DivRemU"; 72 case MipsISD::BuildPairF64: return "MipsISD::BuildPairF64"; 73 case MipsISD::ExtractElementF64: return "MipsISD::ExtractElementF64"; 74 case MipsISD::WrapperPIC: return "MipsISD::WrapperPIC"; 75 case MipsISD::DynAlloc: return "MipsISD::DynAlloc"; 76 case MipsISD::Sync: return "MipsISD::Sync"; 77 case MipsISD::Ext: return "MipsISD::Ext"; 78 case MipsISD::Ins: return "MipsISD::Ins"; 79 default: return NULL; 80 } 81 } 82 83 MipsTargetLowering:: 84 MipsTargetLowering(MipsTargetMachine &TM) 85 : TargetLowering(TM, new MipsTargetObjectFile()) { 86 Subtarget = &TM.getSubtarget<MipsSubtarget>(); 87 88 // Mips does not have i1 type, so use i32 for 89 // setcc operations results (slt, sgt, ...). 90 setBooleanContents(ZeroOrOneBooleanContent); 91 setBooleanVectorContents(ZeroOrOneBooleanContent); // FIXME: Is this correct? 92 93 // Set up the register classes 94 addRegisterClass(MVT::i32, Mips::CPURegsRegisterClass); 95 addRegisterClass(MVT::f32, Mips::FGR32RegisterClass); 96 97 // When dealing with single precision only, use libcalls 98 if (!Subtarget->isSingleFloat()) 99 if (!Subtarget->isFP64bit()) 100 addRegisterClass(MVT::f64, Mips::AFGR64RegisterClass); 101 102 // Load extented operations for i1 types must be promoted 103 setLoadExtAction(ISD::EXTLOAD, MVT::i1, Promote); 104 setLoadExtAction(ISD::ZEXTLOAD, MVT::i1, Promote); 105 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote); 106 107 // MIPS doesn't have extending float->double load/store 108 setLoadExtAction(ISD::EXTLOAD, MVT::f32, Expand); 109 setTruncStoreAction(MVT::f64, MVT::f32, Expand); 110 111 // Used by legalize types to correctly generate the setcc result. 112 // Without this, every float setcc comes with a AND/OR with the result, 113 // we don't want this, since the fpcmp result goes to a flag register, 114 // which is used implicitly by brcond and select operations. 115 AddPromotedToType(ISD::SETCC, MVT::i1, MVT::i32); 116 117 // Mips Custom Operations 118 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom); 119 setOperationAction(ISD::BlockAddress, MVT::i32, Custom); 120 setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom); 121 setOperationAction(ISD::JumpTable, MVT::i32, Custom); 122 setOperationAction(ISD::ConstantPool, MVT::i32, Custom); 123 setOperationAction(ISD::SELECT, MVT::f32, Custom); 124 setOperationAction(ISD::SELECT, MVT::f64, Custom); 125 setOperationAction(ISD::SELECT, MVT::i32, Custom); 126 setOperationAction(ISD::BRCOND, MVT::Other, Custom); 127 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Custom); 128 setOperationAction(ISD::VASTART, MVT::Other, Custom); 129 130 setOperationAction(ISD::SDIV, MVT::i32, Expand); 131 setOperationAction(ISD::SREM, MVT::i32, Expand); 132 setOperationAction(ISD::UDIV, MVT::i32, Expand); 133 setOperationAction(ISD::UREM, MVT::i32, Expand); 134 135 // Operations not directly supported by Mips. 136 setOperationAction(ISD::BR_JT, MVT::Other, Expand); 137 setOperationAction(ISD::BR_CC, MVT::Other, Expand); 138 setOperationAction(ISD::SELECT_CC, MVT::Other, Expand); 139 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand); 140 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand); 141 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand); 142 setOperationAction(ISD::CTPOP, MVT::i32, Expand); 143 setOperationAction(ISD::CTTZ, MVT::i32, Expand); 144 setOperationAction(ISD::ROTL, MVT::i32, Expand); 145 146 if (!Subtarget->isMips32r2()) 147 setOperationAction(ISD::ROTR, MVT::i32, Expand); 148 149 setOperationAction(ISD::SHL_PARTS, MVT::i32, Expand); 150 setOperationAction(ISD::SRA_PARTS, MVT::i32, Expand); 151 setOperationAction(ISD::SRL_PARTS, MVT::i32, Expand); 152 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom); 153 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom); 154 setOperationAction(ISD::FSIN, MVT::f32, Expand); 155 setOperationAction(ISD::FSIN, MVT::f64, Expand); 156 setOperationAction(ISD::FCOS, MVT::f32, Expand); 157 setOperationAction(ISD::FCOS, MVT::f64, Expand); 158 setOperationAction(ISD::FPOWI, MVT::f32, Expand); 159 setOperationAction(ISD::FPOW, MVT::f32, Expand); 160 setOperationAction(ISD::FPOW, MVT::f64, Expand); 161 setOperationAction(ISD::FLOG, MVT::f32, Expand); 162 setOperationAction(ISD::FLOG2, MVT::f32, Expand); 163 setOperationAction(ISD::FLOG10, MVT::f32, Expand); 164 setOperationAction(ISD::FEXP, MVT::f32, Expand); 165 setOperationAction(ISD::FMA, MVT::f32, Expand); 166 setOperationAction(ISD::FMA, MVT::f64, Expand); 167 168 setOperationAction(ISD::EXCEPTIONADDR, MVT::i32, Expand); 169 setOperationAction(ISD::EHSELECTION, MVT::i32, Expand); 170 171 setOperationAction(ISD::VAARG, MVT::Other, Expand); 172 setOperationAction(ISD::VACOPY, MVT::Other, Expand); 173 setOperationAction(ISD::VAEND, MVT::Other, Expand); 174 175 // Use the default for now 176 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand); 177 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand); 178 179 setOperationAction(ISD::MEMBARRIER, MVT::Other, Custom); 180 setOperationAction(ISD::ATOMIC_FENCE, MVT::Other, Custom); 181 182 setOperationAction(ISD::ATOMIC_LOAD, MVT::i32, Expand); 183 setOperationAction(ISD::ATOMIC_STORE, MVT::i32, Expand); 184 185 setInsertFencesForAtomic(true); 186 187 if (Subtarget->isSingleFloat()) 188 setOperationAction(ISD::SELECT_CC, MVT::f64, Expand); 189 190 if (!Subtarget->hasSEInReg()) { 191 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8, Expand); 192 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand); 193 } 194 195 if (!Subtarget->hasBitCount()) 196 setOperationAction(ISD::CTLZ, MVT::i32, Expand); 197 198 if (!Subtarget->hasSwap()) 199 setOperationAction(ISD::BSWAP, MVT::i32, Expand); 200 201 setTargetDAGCombine(ISD::ADDE); 202 setTargetDAGCombine(ISD::SUBE); 203 setTargetDAGCombine(ISD::SDIVREM); 204 setTargetDAGCombine(ISD::UDIVREM); 205 setTargetDAGCombine(ISD::SETCC); 206 setTargetDAGCombine(ISD::AND); 207 setTargetDAGCombine(ISD::OR); 208 209 setMinFunctionAlignment(2); 210 211 setStackPointerRegisterToSaveRestore(Mips::SP); 212 computeRegisterProperties(); 213 214 setExceptionPointerRegister(Mips::A0); 215 setExceptionSelectorRegister(Mips::A1); 216 } 217 218 bool MipsTargetLowering::allowsUnalignedMemoryAccesses(EVT VT) const { 219 MVT::SimpleValueType SVT = VT.getSimpleVT().SimpleTy; 220 return SVT == MVT::i32 || SVT == MVT::i16; 221 } 222 223 EVT MipsTargetLowering::getSetCCResultType(EVT VT) const { 224 return MVT::i32; 225 } 226 227 // SelectMadd - 228 // Transforms a subgraph in CurDAG if the following pattern is found: 229 // (addc multLo, Lo0), (adde multHi, Hi0), 230 // where, 231 // multHi/Lo: product of multiplication 232 // Lo0: initial value of Lo register 233 // Hi0: initial value of Hi register 234 // Return true if pattern matching was successful. 235 static bool SelectMadd(SDNode* ADDENode, SelectionDAG* CurDAG) { 236 // ADDENode's second operand must be a flag output of an ADDC node in order 237 // for the matching to be successful. 238 SDNode* ADDCNode = ADDENode->getOperand(2).getNode(); 239 240 if (ADDCNode->getOpcode() != ISD::ADDC) 241 return false; 242 243 SDValue MultHi = ADDENode->getOperand(0); 244 SDValue MultLo = ADDCNode->getOperand(0); 245 SDNode* MultNode = MultHi.getNode(); 246 unsigned MultOpc = MultHi.getOpcode(); 247 248 // MultHi and MultLo must be generated by the same node, 249 if (MultLo.getNode() != MultNode) 250 return false; 251 252 // and it must be a multiplication. 253 if (MultOpc != ISD::SMUL_LOHI && MultOpc != ISD::UMUL_LOHI) 254 return false; 255 256 // MultLo amd MultHi must be the first and second output of MultNode 257 // respectively. 258 if (MultHi.getResNo() != 1 || MultLo.getResNo() != 0) 259 return false; 260 261 // Transform this to a MADD only if ADDENode and ADDCNode are the only users 262 // of the values of MultNode, in which case MultNode will be removed in later 263 // phases. 264 // If there exist users other than ADDENode or ADDCNode, this function returns 265 // here, which will result in MultNode being mapped to a single MULT 266 // instruction node rather than a pair of MULT and MADD instructions being 267 // produced. 268 if (!MultHi.hasOneUse() || !MultLo.hasOneUse()) 269 return false; 270 271 SDValue Chain = CurDAG->getEntryNode(); 272 DebugLoc dl = ADDENode->getDebugLoc(); 273 274 // create MipsMAdd(u) node 275 MultOpc = MultOpc == ISD::UMUL_LOHI ? MipsISD::MAddu : MipsISD::MAdd; 276 277 SDValue MAdd = CurDAG->getNode(MultOpc, dl, 278 MVT::Glue, 279 MultNode->getOperand(0),// Factor 0 280 MultNode->getOperand(1),// Factor 1 281 ADDCNode->getOperand(1),// Lo0 282 ADDENode->getOperand(1));// Hi0 283 284 // create CopyFromReg nodes 285 SDValue CopyFromLo = CurDAG->getCopyFromReg(Chain, dl, Mips::LO, MVT::i32, 286 MAdd); 287 SDValue CopyFromHi = CurDAG->getCopyFromReg(CopyFromLo.getValue(1), dl, 288 Mips::HI, MVT::i32, 289 CopyFromLo.getValue(2)); 290 291 // replace uses of adde and addc here 292 if (!SDValue(ADDCNode, 0).use_empty()) 293 CurDAG->ReplaceAllUsesOfValueWith(SDValue(ADDCNode, 0), CopyFromLo); 294 295 if (!SDValue(ADDENode, 0).use_empty()) 296 CurDAG->ReplaceAllUsesOfValueWith(SDValue(ADDENode, 0), CopyFromHi); 297 298 return true; 299 } 300 301 // SelectMsub - 302 // Transforms a subgraph in CurDAG if the following pattern is found: 303 // (addc Lo0, multLo), (sube Hi0, multHi), 304 // where, 305 // multHi/Lo: product of multiplication 306 // Lo0: initial value of Lo register 307 // Hi0: initial value of Hi register 308 // Return true if pattern matching was successful. 309 static bool SelectMsub(SDNode* SUBENode, SelectionDAG* CurDAG) { 310 // SUBENode's second operand must be a flag output of an SUBC node in order 311 // for the matching to be successful. 312 SDNode* SUBCNode = SUBENode->getOperand(2).getNode(); 313 314 if (SUBCNode->getOpcode() != ISD::SUBC) 315 return false; 316 317 SDValue MultHi = SUBENode->getOperand(1); 318 SDValue MultLo = SUBCNode->getOperand(1); 319 SDNode* MultNode = MultHi.getNode(); 320 unsigned MultOpc = MultHi.getOpcode(); 321 322 // MultHi and MultLo must be generated by the same node, 323 if (MultLo.getNode() != MultNode) 324 return false; 325 326 // and it must be a multiplication. 327 if (MultOpc != ISD::SMUL_LOHI && MultOpc != ISD::UMUL_LOHI) 328 return false; 329 330 // MultLo amd MultHi must be the first and second output of MultNode 331 // respectively. 332 if (MultHi.getResNo() != 1 || MultLo.getResNo() != 0) 333 return false; 334 335 // Transform this to a MSUB only if SUBENode and SUBCNode are the only users 336 // of the values of MultNode, in which case MultNode will be removed in later 337 // phases. 338 // If there exist users other than SUBENode or SUBCNode, this function returns 339 // here, which will result in MultNode being mapped to a single MULT 340 // instruction node rather than a pair of MULT and MSUB instructions being 341 // produced. 342 if (!MultHi.hasOneUse() || !MultLo.hasOneUse()) 343 return false; 344 345 SDValue Chain = CurDAG->getEntryNode(); 346 DebugLoc dl = SUBENode->getDebugLoc(); 347 348 // create MipsSub(u) node 349 MultOpc = MultOpc == ISD::UMUL_LOHI ? MipsISD::MSubu : MipsISD::MSub; 350 351 SDValue MSub = CurDAG->getNode(MultOpc, dl, 352 MVT::Glue, 353 MultNode->getOperand(0),// Factor 0 354 MultNode->getOperand(1),// Factor 1 355 SUBCNode->getOperand(0),// Lo0 356 SUBENode->getOperand(0));// Hi0 357 358 // create CopyFromReg nodes 359 SDValue CopyFromLo = CurDAG->getCopyFromReg(Chain, dl, Mips::LO, MVT::i32, 360 MSub); 361 SDValue CopyFromHi = CurDAG->getCopyFromReg(CopyFromLo.getValue(1), dl, 362 Mips::HI, MVT::i32, 363 CopyFromLo.getValue(2)); 364 365 // replace uses of sube and subc here 366 if (!SDValue(SUBCNode, 0).use_empty()) 367 CurDAG->ReplaceAllUsesOfValueWith(SDValue(SUBCNode, 0), CopyFromLo); 368 369 if (!SDValue(SUBENode, 0).use_empty()) 370 CurDAG->ReplaceAllUsesOfValueWith(SDValue(SUBENode, 0), CopyFromHi); 371 372 return true; 373 } 374 375 static SDValue PerformADDECombine(SDNode *N, SelectionDAG& DAG, 376 TargetLowering::DAGCombinerInfo &DCI, 377 const MipsSubtarget* Subtarget) { 378 if (DCI.isBeforeLegalize()) 379 return SDValue(); 380 381 if (Subtarget->isMips32() && SelectMadd(N, &DAG)) 382 return SDValue(N, 0); 383 384 return SDValue(); 385 } 386 387 static SDValue PerformSUBECombine(SDNode *N, SelectionDAG& DAG, 388 TargetLowering::DAGCombinerInfo &DCI, 389 const MipsSubtarget* Subtarget) { 390 if (DCI.isBeforeLegalize()) 391 return SDValue(); 392 393 if (Subtarget->isMips32() && SelectMsub(N, &DAG)) 394 return SDValue(N, 0); 395 396 return SDValue(); 397 } 398 399 static SDValue PerformDivRemCombine(SDNode *N, SelectionDAG& DAG, 400 TargetLowering::DAGCombinerInfo &DCI, 401 const MipsSubtarget* Subtarget) { 402 if (DCI.isBeforeLegalizeOps()) 403 return SDValue(); 404 405 unsigned opc = N->getOpcode() == ISD::SDIVREM ? MipsISD::DivRem : 406 MipsISD::DivRemU; 407 DebugLoc dl = N->getDebugLoc(); 408 409 SDValue DivRem = DAG.getNode(opc, dl, MVT::Glue, 410 N->getOperand(0), N->getOperand(1)); 411 SDValue InChain = DAG.getEntryNode(); 412 SDValue InGlue = DivRem; 413 414 // insert MFLO 415 if (N->hasAnyUseOfValue(0)) { 416 SDValue CopyFromLo = DAG.getCopyFromReg(InChain, dl, Mips::LO, MVT::i32, 417 InGlue); 418 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), CopyFromLo); 419 InChain = CopyFromLo.getValue(1); 420 InGlue = CopyFromLo.getValue(2); 421 } 422 423 // insert MFHI 424 if (N->hasAnyUseOfValue(1)) { 425 SDValue CopyFromHi = DAG.getCopyFromReg(InChain, dl, 426 Mips::HI, MVT::i32, InGlue); 427 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), CopyFromHi); 428 } 429 430 return SDValue(); 431 } 432 433 static Mips::CondCode FPCondCCodeToFCC(ISD::CondCode CC) { 434 switch (CC) { 435 default: llvm_unreachable("Unknown fp condition code!"); 436 case ISD::SETEQ: 437 case ISD::SETOEQ: return Mips::FCOND_OEQ; 438 case ISD::SETUNE: return Mips::FCOND_UNE; 439 case ISD::SETLT: 440 case ISD::SETOLT: return Mips::FCOND_OLT; 441 case ISD::SETGT: 442 case ISD::SETOGT: return Mips::FCOND_OGT; 443 case ISD::SETLE: 444 case ISD::SETOLE: return Mips::FCOND_OLE; 445 case ISD::SETGE: 446 case ISD::SETOGE: return Mips::FCOND_OGE; 447 case ISD::SETULT: return Mips::FCOND_ULT; 448 case ISD::SETULE: return Mips::FCOND_ULE; 449 case ISD::SETUGT: return Mips::FCOND_UGT; 450 case ISD::SETUGE: return Mips::FCOND_UGE; 451 case ISD::SETUO: return Mips::FCOND_UN; 452 case ISD::SETO: return Mips::FCOND_OR; 453 case ISD::SETNE: 454 case ISD::SETONE: return Mips::FCOND_ONE; 455 case ISD::SETUEQ: return Mips::FCOND_UEQ; 456 } 457 } 458 459 460 // Returns true if condition code has to be inverted. 461 static bool InvertFPCondCode(Mips::CondCode CC) { 462 if (CC >= Mips::FCOND_F && CC <= Mips::FCOND_NGT) 463 return false; 464 465 if (CC >= Mips::FCOND_T && CC <= Mips::FCOND_GT) 466 return true; 467 468 assert(false && "Illegal Condition Code"); 469 return false; 470 } 471 472 // Creates and returns an FPCmp node from a setcc node. 473 // Returns Op if setcc is not a floating point comparison. 474 static SDValue CreateFPCmp(SelectionDAG& DAG, const SDValue& Op) { 475 // must be a SETCC node 476 if (Op.getOpcode() != ISD::SETCC) 477 return Op; 478 479 SDValue LHS = Op.getOperand(0); 480 481 if (!LHS.getValueType().isFloatingPoint()) 482 return Op; 483 484 SDValue RHS = Op.getOperand(1); 485 DebugLoc dl = Op.getDebugLoc(); 486 487 // Assume the 3rd operand is a CondCodeSDNode. Add code to check the type of 488 // node if necessary. 489 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get(); 490 491 return DAG.getNode(MipsISD::FPCmp, dl, MVT::Glue, LHS, RHS, 492 DAG.getConstant(FPCondCCodeToFCC(CC), MVT::i32)); 493 } 494 495 // Creates and returns a CMovFPT/F node. 496 static SDValue CreateCMovFP(SelectionDAG& DAG, SDValue Cond, SDValue True, 497 SDValue False, DebugLoc DL) { 498 bool invert = InvertFPCondCode((Mips::CondCode) 499 cast<ConstantSDNode>(Cond.getOperand(2)) 500 ->getSExtValue()); 501 502 return DAG.getNode((invert ? MipsISD::CMovFP_F : MipsISD::CMovFP_T), DL, 503 True.getValueType(), True, False, Cond); 504 } 505 506 static SDValue PerformSETCCCombine(SDNode *N, SelectionDAG& DAG, 507 TargetLowering::DAGCombinerInfo &DCI, 508 const MipsSubtarget* Subtarget) { 509 if (DCI.isBeforeLegalizeOps()) 510 return SDValue(); 511 512 SDValue Cond = CreateFPCmp(DAG, SDValue(N, 0)); 513 514 if (Cond.getOpcode() != MipsISD::FPCmp) 515 return SDValue(); 516 517 SDValue True = DAG.getConstant(1, MVT::i32); 518 SDValue False = DAG.getConstant(0, MVT::i32); 519 520 return CreateCMovFP(DAG, Cond, True, False, N->getDebugLoc()); 521 } 522 523 static SDValue PerformANDCombine(SDNode *N, SelectionDAG& DAG, 524 TargetLowering::DAGCombinerInfo &DCI, 525 const MipsSubtarget* Subtarget) { 526 // Pattern match EXT. 527 // $dst = and ((sra or srl) $src , pos), (2**size - 1) 528 // => ext $dst, $src, size, pos 529 if (DCI.isBeforeLegalizeOps() || !Subtarget->isMips32r2()) 530 return SDValue(); 531 532 SDValue ShiftRight = N->getOperand(0), Mask = N->getOperand(1); 533 534 // Op's first operand must be a shift right. 535 if (ShiftRight.getOpcode() != ISD::SRA && ShiftRight.getOpcode() != ISD::SRL) 536 return SDValue(); 537 538 // The second operand of the shift must be an immediate. 539 uint64_t Pos; 540 ConstantSDNode *CN; 541 if (!(CN = dyn_cast<ConstantSDNode>(ShiftRight.getOperand(1)))) 542 return SDValue(); 543 544 Pos = CN->getZExtValue(); 545 546 uint64_t SMPos, SMSize; 547 // Op's second operand must be a shifted mask. 548 if (!(CN = dyn_cast<ConstantSDNode>(Mask)) || 549 !IsShiftedMask(CN->getZExtValue(), SMPos, SMSize)) 550 return SDValue(); 551 552 // Return if the shifted mask does not start at bit 0 or the sum of its size 553 // and Pos exceeds the word's size. 554 if (SMPos != 0 || Pos + SMSize > 32) 555 return SDValue(); 556 557 return DAG.getNode(MipsISD::Ext, N->getDebugLoc(), MVT::i32, 558 ShiftRight.getOperand(0), 559 DAG.getConstant(Pos, MVT::i32), 560 DAG.getConstant(SMSize, MVT::i32)); 561 } 562 563 static SDValue PerformORCombine(SDNode *N, SelectionDAG& DAG, 564 TargetLowering::DAGCombinerInfo &DCI, 565 const MipsSubtarget* Subtarget) { 566 // Pattern match INS. 567 // $dst = or (and $src1 , mask0), (and (shl $src, pos), mask1), 568 // where mask1 = (2**size - 1) << pos, mask0 = ~mask1 569 // => ins $dst, $src, size, pos, $src1 570 if (DCI.isBeforeLegalizeOps() || !Subtarget->isMips32r2()) 571 return SDValue(); 572 573 SDValue And0 = N->getOperand(0), And1 = N->getOperand(1); 574 uint64_t SMPos0, SMSize0, SMPos1, SMSize1; 575 ConstantSDNode *CN; 576 577 // See if Op's first operand matches (and $src1 , mask0). 578 if (And0.getOpcode() != ISD::AND) 579 return SDValue(); 580 581 if (!(CN = dyn_cast<ConstantSDNode>(And0.getOperand(1))) || 582 !IsShiftedMask(~CN->getSExtValue(), SMPos0, SMSize0)) 583 return SDValue(); 584 585 // See if Op's second operand matches (and (shl $src, pos), mask1). 586 if (And1.getOpcode() != ISD::AND) 587 return SDValue(); 588 589 if (!(CN = dyn_cast<ConstantSDNode>(And1.getOperand(1))) || 590 !IsShiftedMask(CN->getZExtValue(), SMPos1, SMSize1)) 591 return SDValue(); 592 593 // The shift masks must have the same position and size. 594 if (SMPos0 != SMPos1 || SMSize0 != SMSize1) 595 return SDValue(); 596 597 SDValue Shl = And1.getOperand(0); 598 if (Shl.getOpcode() != ISD::SHL) 599 return SDValue(); 600 601 if (!(CN = dyn_cast<ConstantSDNode>(Shl.getOperand(1)))) 602 return SDValue(); 603 604 unsigned Shamt = CN->getZExtValue(); 605 606 // Return if the shift amount and the first bit position of mask are not the 607 // same. 608 if (Shamt != SMPos0) 609 return SDValue(); 610 611 return DAG.getNode(MipsISD::Ins, N->getDebugLoc(), MVT::i32, 612 Shl.getOperand(0), 613 DAG.getConstant(SMPos0, MVT::i32), 614 DAG.getConstant(SMSize0, MVT::i32), 615 And0.getOperand(0)); 616 } 617 618 SDValue MipsTargetLowering::PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) 619 const { 620 SelectionDAG &DAG = DCI.DAG; 621 unsigned opc = N->getOpcode(); 622 623 switch (opc) { 624 default: break; 625 case ISD::ADDE: 626 return PerformADDECombine(N, DAG, DCI, Subtarget); 627 case ISD::SUBE: 628 return PerformSUBECombine(N, DAG, DCI, Subtarget); 629 case ISD::SDIVREM: 630 case ISD::UDIVREM: 631 return PerformDivRemCombine(N, DAG, DCI, Subtarget); 632 case ISD::SETCC: 633 return PerformSETCCCombine(N, DAG, DCI, Subtarget); 634 case ISD::AND: 635 return PerformANDCombine(N, DAG, DCI, Subtarget); 636 case ISD::OR: 637 return PerformORCombine(N, DAG, DCI, Subtarget); 638 } 639 640 return SDValue(); 641 } 642 643 SDValue MipsTargetLowering:: 644 LowerOperation(SDValue Op, SelectionDAG &DAG) const 645 { 646 switch (Op.getOpcode()) 647 { 648 case ISD::BRCOND: return LowerBRCOND(Op, DAG); 649 case ISD::ConstantPool: return LowerConstantPool(Op, DAG); 650 case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG); 651 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG); 652 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG); 653 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG); 654 case ISD::JumpTable: return LowerJumpTable(Op, DAG); 655 case ISD::SELECT: return LowerSELECT(Op, DAG); 656 case ISD::VASTART: return LowerVASTART(Op, DAG); 657 case ISD::FCOPYSIGN: return LowerFCOPYSIGN(Op, DAG); 658 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG); 659 case ISD::MEMBARRIER: return LowerMEMBARRIER(Op, DAG); 660 case ISD::ATOMIC_FENCE: return LowerATOMIC_FENCE(Op, DAG); 661 } 662 return SDValue(); 663 } 664 665 //===----------------------------------------------------------------------===// 666 // Lower helper functions 667 //===----------------------------------------------------------------------===// 668 669 // AddLiveIn - This helper function adds the specified physical register to the 670 // MachineFunction as a live in value. It also creates a corresponding 671 // virtual register for it. 672 static unsigned 673 AddLiveIn(MachineFunction &MF, unsigned PReg, TargetRegisterClass *RC) 674 { 675 assert(RC->contains(PReg) && "Not the correct regclass!"); 676 unsigned VReg = MF.getRegInfo().createVirtualRegister(RC); 677 MF.getRegInfo().addLiveIn(PReg, VReg); 678 return VReg; 679 } 680 681 // Get fp branch code (not opcode) from condition code. 682 static Mips::FPBranchCode GetFPBranchCodeFromCond(Mips::CondCode CC) { 683 if (CC >= Mips::FCOND_F && CC <= Mips::FCOND_NGT) 684 return Mips::BRANCH_T; 685 686 if (CC >= Mips::FCOND_T && CC <= Mips::FCOND_GT) 687 return Mips::BRANCH_F; 688 689 return Mips::BRANCH_INVALID; 690 } 691 692 static MachineBasicBlock* ExpandCondMov(MachineInstr *MI, MachineBasicBlock *BB, 693 DebugLoc dl, 694 const MipsSubtarget* Subtarget, 695 const TargetInstrInfo *TII, 696 bool isFPCmp, unsigned Opc) { 697 // There is no need to expand CMov instructions if target has 698 // conditional moves. 699 if (Subtarget->hasCondMov()) 700 return BB; 701 702 // To "insert" a SELECT_CC instruction, we actually have to insert the 703 // diamond control-flow pattern. The incoming instruction knows the 704 // destination vreg to set, the condition code register to branch on, the 705 // true/false values to select between, and a branch opcode to use. 706 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 707 MachineFunction::iterator It = BB; 708 ++It; 709 710 // thisMBB: 711 // ... 712 // TrueVal = ... 713 // setcc r1, r2, r3 714 // bNE r1, r0, copy1MBB 715 // fallthrough --> copy0MBB 716 MachineBasicBlock *thisMBB = BB; 717 MachineFunction *F = BB->getParent(); 718 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB); 719 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB); 720 F->insert(It, copy0MBB); 721 F->insert(It, sinkMBB); 722 723 // Transfer the remainder of BB and its successor edges to sinkMBB. 724 sinkMBB->splice(sinkMBB->begin(), BB, 725 llvm::next(MachineBasicBlock::iterator(MI)), 726 BB->end()); 727 sinkMBB->transferSuccessorsAndUpdatePHIs(BB); 728 729 // Next, add the true and fallthrough blocks as its successors. 730 BB->addSuccessor(copy0MBB); 731 BB->addSuccessor(sinkMBB); 732 733 // Emit the right instruction according to the type of the operands compared 734 if (isFPCmp) 735 BuildMI(BB, dl, TII->get(Opc)).addMBB(sinkMBB); 736 else 737 BuildMI(BB, dl, TII->get(Opc)).addReg(MI->getOperand(2).getReg()) 738 .addReg(Mips::ZERO).addMBB(sinkMBB); 739 740 // copy0MBB: 741 // %FalseValue = ... 742 // # fallthrough to sinkMBB 743 BB = copy0MBB; 744 745 // Update machine-CFG edges 746 BB->addSuccessor(sinkMBB); 747 748 // sinkMBB: 749 // %Result = phi [ %TrueValue, thisMBB ], [ %FalseValue, copy0MBB ] 750 // ... 751 BB = sinkMBB; 752 753 if (isFPCmp) 754 BuildMI(*BB, BB->begin(), dl, 755 TII->get(Mips::PHI), MI->getOperand(0).getReg()) 756 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB) 757 .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB); 758 else 759 BuildMI(*BB, BB->begin(), dl, 760 TII->get(Mips::PHI), MI->getOperand(0).getReg()) 761 .addReg(MI->getOperand(3).getReg()).addMBB(thisMBB) 762 .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB); 763 764 MI->eraseFromParent(); // The pseudo instruction is gone now. 765 return BB; 766 } 767 768 MachineBasicBlock * 769 MipsTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI, 770 MachineBasicBlock *BB) const { 771 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 772 DebugLoc dl = MI->getDebugLoc(); 773 774 switch (MI->getOpcode()) { 775 default: 776 assert(false && "Unexpected instr type to insert"); 777 return NULL; 778 case Mips::MOVT: 779 case Mips::MOVT_S: 780 case Mips::MOVT_D: 781 return ExpandCondMov(MI, BB, dl, Subtarget, TII, true, Mips::BC1F); 782 case Mips::MOVF: 783 case Mips::MOVF_S: 784 case Mips::MOVF_D: 785 return ExpandCondMov(MI, BB, dl, Subtarget, TII, true, Mips::BC1T); 786 case Mips::MOVZ_I: 787 case Mips::MOVZ_S: 788 case Mips::MOVZ_D: 789 return ExpandCondMov(MI, BB, dl, Subtarget, TII, false, Mips::BNE); 790 case Mips::MOVN_I: 791 case Mips::MOVN_S: 792 case Mips::MOVN_D: 793 return ExpandCondMov(MI, BB, dl, Subtarget, TII, false, Mips::BEQ); 794 795 case Mips::ATOMIC_LOAD_ADD_I8: 796 return EmitAtomicBinaryPartword(MI, BB, 1, Mips::ADDu); 797 case Mips::ATOMIC_LOAD_ADD_I16: 798 return EmitAtomicBinaryPartword(MI, BB, 2, Mips::ADDu); 799 case Mips::ATOMIC_LOAD_ADD_I32: 800 return EmitAtomicBinary(MI, BB, 4, Mips::ADDu); 801 802 case Mips::ATOMIC_LOAD_AND_I8: 803 return EmitAtomicBinaryPartword(MI, BB, 1, Mips::AND); 804 case Mips::ATOMIC_LOAD_AND_I16: 805 return EmitAtomicBinaryPartword(MI, BB, 2, Mips::AND); 806 case Mips::ATOMIC_LOAD_AND_I32: 807 return EmitAtomicBinary(MI, BB, 4, Mips::AND); 808 809 case Mips::ATOMIC_LOAD_OR_I8: 810 return EmitAtomicBinaryPartword(MI, BB, 1, Mips::OR); 811 case Mips::ATOMIC_LOAD_OR_I16: 812 return EmitAtomicBinaryPartword(MI, BB, 2, Mips::OR); 813 case Mips::ATOMIC_LOAD_OR_I32: 814 return EmitAtomicBinary(MI, BB, 4, Mips::OR); 815 816 case Mips::ATOMIC_LOAD_XOR_I8: 817 return EmitAtomicBinaryPartword(MI, BB, 1, Mips::XOR); 818 case Mips::ATOMIC_LOAD_XOR_I16: 819 return EmitAtomicBinaryPartword(MI, BB, 2, Mips::XOR); 820 case Mips::ATOMIC_LOAD_XOR_I32: 821 return EmitAtomicBinary(MI, BB, 4, Mips::XOR); 822 823 case Mips::ATOMIC_LOAD_NAND_I8: 824 return EmitAtomicBinaryPartword(MI, BB, 1, 0, true); 825 case Mips::ATOMIC_LOAD_NAND_I16: 826 return EmitAtomicBinaryPartword(MI, BB, 2, 0, true); 827 case Mips::ATOMIC_LOAD_NAND_I32: 828 return EmitAtomicBinary(MI, BB, 4, 0, true); 829 830 case Mips::ATOMIC_LOAD_SUB_I8: 831 return EmitAtomicBinaryPartword(MI, BB, 1, Mips::SUBu); 832 case Mips::ATOMIC_LOAD_SUB_I16: 833 return EmitAtomicBinaryPartword(MI, BB, 2, Mips::SUBu); 834 case Mips::ATOMIC_LOAD_SUB_I32: 835 return EmitAtomicBinary(MI, BB, 4, Mips::SUBu); 836 837 case Mips::ATOMIC_SWAP_I8: 838 return EmitAtomicBinaryPartword(MI, BB, 1, 0); 839 case Mips::ATOMIC_SWAP_I16: 840 return EmitAtomicBinaryPartword(MI, BB, 2, 0); 841 case Mips::ATOMIC_SWAP_I32: 842 return EmitAtomicBinary(MI, BB, 4, 0); 843 844 case Mips::ATOMIC_CMP_SWAP_I8: 845 return EmitAtomicCmpSwapPartword(MI, BB, 1); 846 case Mips::ATOMIC_CMP_SWAP_I16: 847 return EmitAtomicCmpSwapPartword(MI, BB, 2); 848 case Mips::ATOMIC_CMP_SWAP_I32: 849 return EmitAtomicCmpSwap(MI, BB, 4); 850 } 851 } 852 853 // This function also handles Mips::ATOMIC_SWAP_I32 (when BinOpcode == 0), and 854 // Mips::ATOMIC_LOAD_NAND_I32 (when Nand == true) 855 MachineBasicBlock * 856 MipsTargetLowering::EmitAtomicBinary(MachineInstr *MI, MachineBasicBlock *BB, 857 unsigned Size, unsigned BinOpcode, 858 bool Nand) const { 859 assert(Size == 4 && "Unsupported size for EmitAtomicBinary."); 860 861 MachineFunction *MF = BB->getParent(); 862 MachineRegisterInfo &RegInfo = MF->getRegInfo(); 863 const TargetRegisterClass *RC = getRegClassFor(MVT::i32); 864 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 865 DebugLoc dl = MI->getDebugLoc(); 866 867 unsigned OldVal = MI->getOperand(0).getReg(); 868 unsigned Ptr = MI->getOperand(1).getReg(); 869 unsigned Incr = MI->getOperand(2).getReg(); 870 871 unsigned StoreVal = RegInfo.createVirtualRegister(RC); 872 unsigned AndRes = RegInfo.createVirtualRegister(RC); 873 unsigned Success = RegInfo.createVirtualRegister(RC); 874 875 // insert new blocks after the current block 876 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 877 MachineBasicBlock *loopMBB = MF->CreateMachineBasicBlock(LLVM_BB); 878 MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB); 879 MachineFunction::iterator It = BB; 880 ++It; 881 MF->insert(It, loopMBB); 882 MF->insert(It, exitMBB); 883 884 // Transfer the remainder of BB and its successor edges to exitMBB. 885 exitMBB->splice(exitMBB->begin(), BB, 886 llvm::next(MachineBasicBlock::iterator(MI)), 887 BB->end()); 888 exitMBB->transferSuccessorsAndUpdatePHIs(BB); 889 890 // thisMBB: 891 // ... 892 // fallthrough --> loopMBB 893 BB->addSuccessor(loopMBB); 894 loopMBB->addSuccessor(loopMBB); 895 loopMBB->addSuccessor(exitMBB); 896 897 // loopMBB: 898 // ll oldval, 0(ptr) 899 // <binop> storeval, oldval, incr 900 // sc success, storeval, 0(ptr) 901 // beq success, $0, loopMBB 902 BB = loopMBB; 903 BuildMI(BB, dl, TII->get(Mips::LL), OldVal).addReg(Ptr).addImm(0); 904 if (Nand) { 905 // and andres, oldval, incr 906 // nor storeval, $0, andres 907 BuildMI(BB, dl, TII->get(Mips::AND), AndRes).addReg(OldVal).addReg(Incr); 908 BuildMI(BB, dl, TII->get(Mips::NOR), StoreVal) 909 .addReg(Mips::ZERO).addReg(AndRes); 910 } else if (BinOpcode) { 911 // <binop> storeval, oldval, incr 912 BuildMI(BB, dl, TII->get(BinOpcode), StoreVal).addReg(OldVal).addReg(Incr); 913 } else { 914 StoreVal = Incr; 915 } 916 BuildMI(BB, dl, TII->get(Mips::SC), Success) 917 .addReg(StoreVal).addReg(Ptr).addImm(0); 918 BuildMI(BB, dl, TII->get(Mips::BEQ)) 919 .addReg(Success).addReg(Mips::ZERO).addMBB(loopMBB); 920 921 MI->eraseFromParent(); // The instruction is gone now. 922 923 return exitMBB; 924 } 925 926 MachineBasicBlock * 927 MipsTargetLowering::EmitAtomicBinaryPartword(MachineInstr *MI, 928 MachineBasicBlock *BB, 929 unsigned Size, unsigned BinOpcode, 930 bool Nand) const { 931 assert((Size == 1 || Size == 2) && 932 "Unsupported size for EmitAtomicBinaryPartial."); 933 934 MachineFunction *MF = BB->getParent(); 935 MachineRegisterInfo &RegInfo = MF->getRegInfo(); 936 const TargetRegisterClass *RC = getRegClassFor(MVT::i32); 937 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 938 DebugLoc dl = MI->getDebugLoc(); 939 940 unsigned Dest = MI->getOperand(0).getReg(); 941 unsigned Ptr = MI->getOperand(1).getReg(); 942 unsigned Incr = MI->getOperand(2).getReg(); 943 944 unsigned AlignedAddr = RegInfo.createVirtualRegister(RC); 945 unsigned ShiftAmt = RegInfo.createVirtualRegister(RC); 946 unsigned Mask = RegInfo.createVirtualRegister(RC); 947 unsigned Mask2 = RegInfo.createVirtualRegister(RC); 948 unsigned NewVal = RegInfo.createVirtualRegister(RC); 949 unsigned OldVal = RegInfo.createVirtualRegister(RC); 950 unsigned Incr2 = RegInfo.createVirtualRegister(RC); 951 unsigned MaskLSB2 = RegInfo.createVirtualRegister(RC); 952 unsigned PtrLSB2 = RegInfo.createVirtualRegister(RC); 953 unsigned MaskUpper = RegInfo.createVirtualRegister(RC); 954 unsigned AndRes = RegInfo.createVirtualRegister(RC); 955 unsigned BinOpRes = RegInfo.createVirtualRegister(RC); 956 unsigned MaskedOldVal0 = RegInfo.createVirtualRegister(RC); 957 unsigned StoreVal = RegInfo.createVirtualRegister(RC); 958 unsigned MaskedOldVal1 = RegInfo.createVirtualRegister(RC); 959 unsigned SrlRes = RegInfo.createVirtualRegister(RC); 960 unsigned SllRes = RegInfo.createVirtualRegister(RC); 961 unsigned Success = RegInfo.createVirtualRegister(RC); 962 963 // insert new blocks after the current block 964 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 965 MachineBasicBlock *loopMBB = MF->CreateMachineBasicBlock(LLVM_BB); 966 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(LLVM_BB); 967 MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB); 968 MachineFunction::iterator It = BB; 969 ++It; 970 MF->insert(It, loopMBB); 971 MF->insert(It, sinkMBB); 972 MF->insert(It, exitMBB); 973 974 // Transfer the remainder of BB and its successor edges to exitMBB. 975 exitMBB->splice(exitMBB->begin(), BB, 976 llvm::next(MachineBasicBlock::iterator(MI)), 977 BB->end()); 978 exitMBB->transferSuccessorsAndUpdatePHIs(BB); 979 980 BB->addSuccessor(loopMBB); 981 loopMBB->addSuccessor(loopMBB); 982 loopMBB->addSuccessor(sinkMBB); 983 sinkMBB->addSuccessor(exitMBB); 984 985 // thisMBB: 986 // addiu masklsb2,$0,-4 # 0xfffffffc 987 // and alignedaddr,ptr,masklsb2 988 // andi ptrlsb2,ptr,3 989 // sll shiftamt,ptrlsb2,3 990 // ori maskupper,$0,255 # 0xff 991 // sll mask,maskupper,shiftamt 992 // nor mask2,$0,mask 993 // sll incr2,incr,shiftamt 994 995 int64_t MaskImm = (Size == 1) ? 255 : 65535; 996 BuildMI(BB, dl, TII->get(Mips::ADDiu), MaskLSB2) 997 .addReg(Mips::ZERO).addImm(-4); 998 BuildMI(BB, dl, TII->get(Mips::AND), AlignedAddr) 999 .addReg(Ptr).addReg(MaskLSB2); 1000 BuildMI(BB, dl, TII->get(Mips::ANDi), PtrLSB2).addReg(Ptr).addImm(3); 1001 BuildMI(BB, dl, TII->get(Mips::SLL), ShiftAmt).addReg(PtrLSB2).addImm(3); 1002 BuildMI(BB, dl, TII->get(Mips::ORi), MaskUpper) 1003 .addReg(Mips::ZERO).addImm(MaskImm); 1004 BuildMI(BB, dl, TII->get(Mips::SLLV), Mask) 1005 .addReg(ShiftAmt).addReg(MaskUpper); 1006 BuildMI(BB, dl, TII->get(Mips::NOR), Mask2).addReg(Mips::ZERO).addReg(Mask); 1007 BuildMI(BB, dl, TII->get(Mips::SLLV), Incr2).addReg(ShiftAmt).addReg(Incr); 1008 1009 1010 // atomic.load.binop 1011 // loopMBB: 1012 // ll oldval,0(alignedaddr) 1013 // binop binopres,oldval,incr2 1014 // and newval,binopres,mask 1015 // and maskedoldval0,oldval,mask2 1016 // or storeval,maskedoldval0,newval 1017 // sc success,storeval,0(alignedaddr) 1018 // beq success,$0,loopMBB 1019 1020 // atomic.swap 1021 // loopMBB: 1022 // ll oldval,0(alignedaddr) 1023 // and newval,incr2,mask 1024 // and maskedoldval0,oldval,mask2 1025 // or storeval,maskedoldval0,newval 1026 // sc success,storeval,0(alignedaddr) 1027 // beq success,$0,loopMBB 1028 1029 BB = loopMBB; 1030 BuildMI(BB, dl, TII->get(Mips::LL), OldVal).addReg(AlignedAddr).addImm(0); 1031 if (Nand) { 1032 // and andres, oldval, incr2 1033 // nor binopres, $0, andres 1034 // and newval, binopres, mask 1035 BuildMI(BB, dl, TII->get(Mips::AND), AndRes).addReg(OldVal).addReg(Incr2); 1036 BuildMI(BB, dl, TII->get(Mips::NOR), BinOpRes) 1037 .addReg(Mips::ZERO).addReg(AndRes); 1038 BuildMI(BB, dl, TII->get(Mips::AND), NewVal).addReg(BinOpRes).addReg(Mask); 1039 } else if (BinOpcode) { 1040 // <binop> binopres, oldval, incr2 1041 // and newval, binopres, mask 1042 BuildMI(BB, dl, TII->get(BinOpcode), BinOpRes).addReg(OldVal).addReg(Incr2); 1043 BuildMI(BB, dl, TII->get(Mips::AND), NewVal).addReg(BinOpRes).addReg(Mask); 1044 } else {// atomic.swap 1045 // and newval, incr2, mask 1046 BuildMI(BB, dl, TII->get(Mips::AND), NewVal).addReg(Incr2).addReg(Mask); 1047 } 1048 1049 BuildMI(BB, dl, TII->get(Mips::AND), MaskedOldVal0) 1050 .addReg(OldVal).addReg(Mask2); 1051 BuildMI(BB, dl, TII->get(Mips::OR), StoreVal) 1052 .addReg(MaskedOldVal0).addReg(NewVal); 1053 BuildMI(BB, dl, TII->get(Mips::SC), Success) 1054 .addReg(StoreVal).addReg(AlignedAddr).addImm(0); 1055 BuildMI(BB, dl, TII->get(Mips::BEQ)) 1056 .addReg(Success).addReg(Mips::ZERO).addMBB(loopMBB); 1057 1058 // sinkMBB: 1059 // and maskedoldval1,oldval,mask 1060 // srl srlres,maskedoldval1,shiftamt 1061 // sll sllres,srlres,24 1062 // sra dest,sllres,24 1063 BB = sinkMBB; 1064 int64_t ShiftImm = (Size == 1) ? 24 : 16; 1065 1066 BuildMI(BB, dl, TII->get(Mips::AND), MaskedOldVal1) 1067 .addReg(OldVal).addReg(Mask); 1068 BuildMI(BB, dl, TII->get(Mips::SRLV), SrlRes) 1069 .addReg(ShiftAmt).addReg(MaskedOldVal1); 1070 BuildMI(BB, dl, TII->get(Mips::SLL), SllRes) 1071 .addReg(SrlRes).addImm(ShiftImm); 1072 BuildMI(BB, dl, TII->get(Mips::SRA), Dest) 1073 .addReg(SllRes).addImm(ShiftImm); 1074 1075 MI->eraseFromParent(); // The instruction is gone now. 1076 1077 return exitMBB; 1078 } 1079 1080 MachineBasicBlock * 1081 MipsTargetLowering::EmitAtomicCmpSwap(MachineInstr *MI, 1082 MachineBasicBlock *BB, 1083 unsigned Size) const { 1084 assert(Size == 4 && "Unsupported size for EmitAtomicCmpSwap."); 1085 1086 MachineFunction *MF = BB->getParent(); 1087 MachineRegisterInfo &RegInfo = MF->getRegInfo(); 1088 const TargetRegisterClass *RC = getRegClassFor(MVT::i32); 1089 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 1090 DebugLoc dl = MI->getDebugLoc(); 1091 1092 unsigned Dest = MI->getOperand(0).getReg(); 1093 unsigned Ptr = MI->getOperand(1).getReg(); 1094 unsigned OldVal = MI->getOperand(2).getReg(); 1095 unsigned NewVal = MI->getOperand(3).getReg(); 1096 1097 unsigned Success = RegInfo.createVirtualRegister(RC); 1098 1099 // insert new blocks after the current block 1100 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 1101 MachineBasicBlock *loop1MBB = MF->CreateMachineBasicBlock(LLVM_BB); 1102 MachineBasicBlock *loop2MBB = MF->CreateMachineBasicBlock(LLVM_BB); 1103 MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB); 1104 MachineFunction::iterator It = BB; 1105 ++It; 1106 MF->insert(It, loop1MBB); 1107 MF->insert(It, loop2MBB); 1108 MF->insert(It, exitMBB); 1109 1110 // Transfer the remainder of BB and its successor edges to exitMBB. 1111 exitMBB->splice(exitMBB->begin(), BB, 1112 llvm::next(MachineBasicBlock::iterator(MI)), 1113 BB->end()); 1114 exitMBB->transferSuccessorsAndUpdatePHIs(BB); 1115 1116 // thisMBB: 1117 // ... 1118 // fallthrough --> loop1MBB 1119 BB->addSuccessor(loop1MBB); 1120 loop1MBB->addSuccessor(exitMBB); 1121 loop1MBB->addSuccessor(loop2MBB); 1122 loop2MBB->addSuccessor(loop1MBB); 1123 loop2MBB->addSuccessor(exitMBB); 1124 1125 // loop1MBB: 1126 // ll dest, 0(ptr) 1127 // bne dest, oldval, exitMBB 1128 BB = loop1MBB; 1129 BuildMI(BB, dl, TII->get(Mips::LL), Dest).addReg(Ptr).addImm(0); 1130 BuildMI(BB, dl, TII->get(Mips::BNE)) 1131 .addReg(Dest).addReg(OldVal).addMBB(exitMBB); 1132 1133 // loop2MBB: 1134 // sc success, newval, 0(ptr) 1135 // beq success, $0, loop1MBB 1136 BB = loop2MBB; 1137 BuildMI(BB, dl, TII->get(Mips::SC), Success) 1138 .addReg(NewVal).addReg(Ptr).addImm(0); 1139 BuildMI(BB, dl, TII->get(Mips::BEQ)) 1140 .addReg(Success).addReg(Mips::ZERO).addMBB(loop1MBB); 1141 1142 MI->eraseFromParent(); // The instruction is gone now. 1143 1144 return exitMBB; 1145 } 1146 1147 MachineBasicBlock * 1148 MipsTargetLowering::EmitAtomicCmpSwapPartword(MachineInstr *MI, 1149 MachineBasicBlock *BB, 1150 unsigned Size) const { 1151 assert((Size == 1 || Size == 2) && 1152 "Unsupported size for EmitAtomicCmpSwapPartial."); 1153 1154 MachineFunction *MF = BB->getParent(); 1155 MachineRegisterInfo &RegInfo = MF->getRegInfo(); 1156 const TargetRegisterClass *RC = getRegClassFor(MVT::i32); 1157 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 1158 DebugLoc dl = MI->getDebugLoc(); 1159 1160 unsigned Dest = MI->getOperand(0).getReg(); 1161 unsigned Ptr = MI->getOperand(1).getReg(); 1162 unsigned CmpVal = MI->getOperand(2).getReg(); 1163 unsigned NewVal = MI->getOperand(3).getReg(); 1164 1165 unsigned AlignedAddr = RegInfo.createVirtualRegister(RC); 1166 unsigned ShiftAmt = RegInfo.createVirtualRegister(RC); 1167 unsigned Mask = RegInfo.createVirtualRegister(RC); 1168 unsigned Mask2 = RegInfo.createVirtualRegister(RC); 1169 unsigned ShiftedCmpVal = RegInfo.createVirtualRegister(RC); 1170 unsigned OldVal = RegInfo.createVirtualRegister(RC); 1171 unsigned MaskedOldVal0 = RegInfo.createVirtualRegister(RC); 1172 unsigned ShiftedNewVal = RegInfo.createVirtualRegister(RC); 1173 unsigned MaskLSB2 = RegInfo.createVirtualRegister(RC); 1174 unsigned PtrLSB2 = RegInfo.createVirtualRegister(RC); 1175 unsigned MaskUpper = RegInfo.createVirtualRegister(RC); 1176 unsigned MaskedCmpVal = RegInfo.createVirtualRegister(RC); 1177 unsigned MaskedNewVal = RegInfo.createVirtualRegister(RC); 1178 unsigned MaskedOldVal1 = RegInfo.createVirtualRegister(RC); 1179 unsigned StoreVal = RegInfo.createVirtualRegister(RC); 1180 unsigned SrlRes = RegInfo.createVirtualRegister(RC); 1181 unsigned SllRes = RegInfo.createVirtualRegister(RC); 1182 unsigned Success = RegInfo.createVirtualRegister(RC); 1183 1184 // insert new blocks after the current block 1185 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 1186 MachineBasicBlock *loop1MBB = MF->CreateMachineBasicBlock(LLVM_BB); 1187 MachineBasicBlock *loop2MBB = MF->CreateMachineBasicBlock(LLVM_BB); 1188 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(LLVM_BB); 1189 MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB); 1190 MachineFunction::iterator It = BB; 1191 ++It; 1192 MF->insert(It, loop1MBB); 1193 MF->insert(It, loop2MBB); 1194 MF->insert(It, sinkMBB); 1195 MF->insert(It, exitMBB); 1196 1197 // Transfer the remainder of BB and its successor edges to exitMBB. 1198 exitMBB->splice(exitMBB->begin(), BB, 1199 llvm::next(MachineBasicBlock::iterator(MI)), 1200 BB->end()); 1201 exitMBB->transferSuccessorsAndUpdatePHIs(BB); 1202 1203 BB->addSuccessor(loop1MBB); 1204 loop1MBB->addSuccessor(sinkMBB); 1205 loop1MBB->addSuccessor(loop2MBB); 1206 loop2MBB->addSuccessor(loop1MBB); 1207 loop2MBB->addSuccessor(sinkMBB); 1208 sinkMBB->addSuccessor(exitMBB); 1209 1210 // FIXME: computation of newval2 can be moved to loop2MBB. 1211 // thisMBB: 1212 // addiu masklsb2,$0,-4 # 0xfffffffc 1213 // and alignedaddr,ptr,masklsb2 1214 // andi ptrlsb2,ptr,3 1215 // sll shiftamt,ptrlsb2,3 1216 // ori maskupper,$0,255 # 0xff 1217 // sll mask,maskupper,shiftamt 1218 // nor mask2,$0,mask 1219 // andi maskedcmpval,cmpval,255 1220 // sll shiftedcmpval,maskedcmpval,shiftamt 1221 // andi maskednewval,newval,255 1222 // sll shiftednewval,maskednewval,shiftamt 1223 int64_t MaskImm = (Size == 1) ? 255 : 65535; 1224 BuildMI(BB, dl, TII->get(Mips::ADDiu), MaskLSB2) 1225 .addReg(Mips::ZERO).addImm(-4); 1226 BuildMI(BB, dl, TII->get(Mips::AND), AlignedAddr) 1227 .addReg(Ptr).addReg(MaskLSB2); 1228 BuildMI(BB, dl, TII->get(Mips::ANDi), PtrLSB2).addReg(Ptr).addImm(3); 1229 BuildMI(BB, dl, TII->get(Mips::SLL), ShiftAmt).addReg(PtrLSB2).addImm(3); 1230 BuildMI(BB, dl, TII->get(Mips::ORi), MaskUpper) 1231 .addReg(Mips::ZERO).addImm(MaskImm); 1232 BuildMI(BB, dl, TII->get(Mips::SLLV), Mask) 1233 .addReg(ShiftAmt).addReg(MaskUpper); 1234 BuildMI(BB, dl, TII->get(Mips::NOR), Mask2).addReg(Mips::ZERO).addReg(Mask); 1235 BuildMI(BB, dl, TII->get(Mips::ANDi), MaskedCmpVal) 1236 .addReg(CmpVal).addImm(MaskImm); 1237 BuildMI(BB, dl, TII->get(Mips::SLLV), ShiftedCmpVal) 1238 .addReg(ShiftAmt).addReg(MaskedCmpVal); 1239 BuildMI(BB, dl, TII->get(Mips::ANDi), MaskedNewVal) 1240 .addReg(NewVal).addImm(MaskImm); 1241 BuildMI(BB, dl, TII->get(Mips::SLLV), ShiftedNewVal) 1242 .addReg(ShiftAmt).addReg(MaskedNewVal); 1243 1244 // loop1MBB: 1245 // ll oldval,0(alginedaddr) 1246 // and maskedoldval0,oldval,mask 1247 // bne maskedoldval0,shiftedcmpval,sinkMBB 1248 BB = loop1MBB; 1249 BuildMI(BB, dl, TII->get(Mips::LL), OldVal).addReg(AlignedAddr).addImm(0); 1250 BuildMI(BB, dl, TII->get(Mips::AND), MaskedOldVal0) 1251 .addReg(OldVal).addReg(Mask); 1252 BuildMI(BB, dl, TII->get(Mips::BNE)) 1253 .addReg(MaskedOldVal0).addReg(ShiftedCmpVal).addMBB(sinkMBB); 1254 1255 // loop2MBB: 1256 // and maskedoldval1,oldval,mask2 1257 // or storeval,maskedoldval1,shiftednewval 1258 // sc success,storeval,0(alignedaddr) 1259 // beq success,$0,loop1MBB 1260 BB = loop2MBB; 1261 BuildMI(BB, dl, TII->get(Mips::AND), MaskedOldVal1) 1262 .addReg(OldVal).addReg(Mask2); 1263 BuildMI(BB, dl, TII->get(Mips::OR), StoreVal) 1264 .addReg(MaskedOldVal1).addReg(ShiftedNewVal); 1265 BuildMI(BB, dl, TII->get(Mips::SC), Success) 1266 .addReg(StoreVal).addReg(AlignedAddr).addImm(0); 1267 BuildMI(BB, dl, TII->get(Mips::BEQ)) 1268 .addReg(Success).addReg(Mips::ZERO).addMBB(loop1MBB); 1269 1270 // sinkMBB: 1271 // srl srlres,maskedoldval0,shiftamt 1272 // sll sllres,srlres,24 1273 // sra dest,sllres,24 1274 BB = sinkMBB; 1275 int64_t ShiftImm = (Size == 1) ? 24 : 16; 1276 1277 BuildMI(BB, dl, TII->get(Mips::SRLV), SrlRes) 1278 .addReg(ShiftAmt).addReg(MaskedOldVal0); 1279 BuildMI(BB, dl, TII->get(Mips::SLL), SllRes) 1280 .addReg(SrlRes).addImm(ShiftImm); 1281 BuildMI(BB, dl, TII->get(Mips::SRA), Dest) 1282 .addReg(SllRes).addImm(ShiftImm); 1283 1284 MI->eraseFromParent(); // The instruction is gone now. 1285 1286 return exitMBB; 1287 } 1288 1289 //===----------------------------------------------------------------------===// 1290 // Misc Lower Operation implementation 1291 //===----------------------------------------------------------------------===// 1292 SDValue MipsTargetLowering:: 1293 LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const 1294 { 1295 MachineFunction &MF = DAG.getMachineFunction(); 1296 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>(); 1297 1298 assert(getTargetMachine().getFrameLowering()->getStackAlignment() >= 1299 cast<ConstantSDNode>(Op.getOperand(2).getNode())->getZExtValue() && 1300 "Cannot lower if the alignment of the allocated space is larger than \ 1301 that of the stack."); 1302 1303 SDValue Chain = Op.getOperand(0); 1304 SDValue Size = Op.getOperand(1); 1305 DebugLoc dl = Op.getDebugLoc(); 1306 1307 // Get a reference from Mips stack pointer 1308 SDValue StackPointer = DAG.getCopyFromReg(Chain, dl, Mips::SP, MVT::i32); 1309 1310 // Subtract the dynamic size from the actual stack size to 1311 // obtain the new stack size. 1312 SDValue Sub = DAG.getNode(ISD::SUB, dl, MVT::i32, StackPointer, Size); 1313 1314 // The Sub result contains the new stack start address, so it 1315 // must be placed in the stack pointer register. 1316 Chain = DAG.getCopyToReg(StackPointer.getValue(1), dl, Mips::SP, Sub, 1317 SDValue()); 1318 1319 // This node always has two return values: a new stack pointer 1320 // value and a chain 1321 SDVTList VTLs = DAG.getVTList(MVT::i32, MVT::Other); 1322 SDValue Ptr = DAG.getFrameIndex(MipsFI->getDynAllocFI(), getPointerTy()); 1323 SDValue Ops[] = { Chain, Ptr, Chain.getValue(1) }; 1324 1325 return DAG.getNode(MipsISD::DynAlloc, dl, VTLs, Ops, 3); 1326 } 1327 1328 SDValue MipsTargetLowering:: 1329 LowerBRCOND(SDValue Op, SelectionDAG &DAG) const 1330 { 1331 // The first operand is the chain, the second is the condition, the third is 1332 // the block to branch to if the condition is true. 1333 SDValue Chain = Op.getOperand(0); 1334 SDValue Dest = Op.getOperand(2); 1335 DebugLoc dl = Op.getDebugLoc(); 1336 1337 SDValue CondRes = CreateFPCmp(DAG, Op.getOperand(1)); 1338 1339 // Return if flag is not set by a floating point comparison. 1340 if (CondRes.getOpcode() != MipsISD::FPCmp) 1341 return Op; 1342 1343 SDValue CCNode = CondRes.getOperand(2); 1344 Mips::CondCode CC = 1345 (Mips::CondCode)cast<ConstantSDNode>(CCNode)->getZExtValue(); 1346 SDValue BrCode = DAG.getConstant(GetFPBranchCodeFromCond(CC), MVT::i32); 1347 1348 return DAG.getNode(MipsISD::FPBrcond, dl, Op.getValueType(), Chain, BrCode, 1349 Dest, CondRes); 1350 } 1351 1352 SDValue MipsTargetLowering:: 1353 LowerSELECT(SDValue Op, SelectionDAG &DAG) const 1354 { 1355 SDValue Cond = CreateFPCmp(DAG, Op.getOperand(0)); 1356 1357 // Return if flag is not set by a floating point comparison. 1358 if (Cond.getOpcode() != MipsISD::FPCmp) 1359 return Op; 1360 1361 return CreateCMovFP(DAG, Cond, Op.getOperand(1), Op.getOperand(2), 1362 Op.getDebugLoc()); 1363 } 1364 1365 SDValue MipsTargetLowering::LowerGlobalAddress(SDValue Op, 1366 SelectionDAG &DAG) const { 1367 // FIXME there isn't actually debug info here 1368 DebugLoc dl = Op.getDebugLoc(); 1369 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal(); 1370 1371 if (getTargetMachine().getRelocationModel() != Reloc::PIC_) { 1372 SDVTList VTs = DAG.getVTList(MVT::i32); 1373 1374 MipsTargetObjectFile &TLOF = (MipsTargetObjectFile&)getObjFileLowering(); 1375 1376 // %gp_rel relocation 1377 if (TLOF.IsGlobalInSmallSection(GV, getTargetMachine())) { 1378 SDValue GA = DAG.getTargetGlobalAddress(GV, dl, MVT::i32, 0, 1379 MipsII::MO_GPREL); 1380 SDValue GPRelNode = DAG.getNode(MipsISD::GPRel, dl, VTs, &GA, 1); 1381 SDValue GOT = DAG.getGLOBAL_OFFSET_TABLE(MVT::i32); 1382 return DAG.getNode(ISD::ADD, dl, MVT::i32, GOT, GPRelNode); 1383 } 1384 // %hi/%lo relocation 1385 SDValue GAHi = DAG.getTargetGlobalAddress(GV, dl, MVT::i32, 0, 1386 MipsII::MO_ABS_HI); 1387 SDValue GALo = DAG.getTargetGlobalAddress(GV, dl, MVT::i32, 0, 1388 MipsII::MO_ABS_LO); 1389 SDValue HiPart = DAG.getNode(MipsISD::Hi, dl, VTs, &GAHi, 1); 1390 SDValue Lo = DAG.getNode(MipsISD::Lo, dl, MVT::i32, GALo); 1391 return DAG.getNode(ISD::ADD, dl, MVT::i32, HiPart, Lo); 1392 } 1393 1394 SDValue GA = DAG.getTargetGlobalAddress(GV, dl, MVT::i32, 0, 1395 MipsII::MO_GOT); 1396 GA = DAG.getNode(MipsISD::WrapperPIC, dl, MVT::i32, GA); 1397 SDValue ResNode = DAG.getLoad(MVT::i32, dl, 1398 DAG.getEntryNode(), GA, MachinePointerInfo(), 1399 false, false, 0); 1400 // On functions and global targets not internal linked only 1401 // a load from got/GP is necessary for PIC to work. 1402 if (!GV->hasInternalLinkage() && 1403 (!GV->hasLocalLinkage() || isa<Function>(GV))) 1404 return ResNode; 1405 SDValue GALo = DAG.getTargetGlobalAddress(GV, dl, MVT::i32, 0, 1406 MipsII::MO_ABS_LO); 1407 SDValue Lo = DAG.getNode(MipsISD::Lo, dl, MVT::i32, GALo); 1408 return DAG.getNode(ISD::ADD, dl, MVT::i32, ResNode, Lo); 1409 } 1410 1411 SDValue MipsTargetLowering::LowerBlockAddress(SDValue Op, 1412 SelectionDAG &DAG) const { 1413 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress(); 1414 // FIXME there isn't actually debug info here 1415 DebugLoc dl = Op.getDebugLoc(); 1416 1417 if (getTargetMachine().getRelocationModel() != Reloc::PIC_) { 1418 // %hi/%lo relocation 1419 SDValue BAHi = DAG.getBlockAddress(BA, MVT::i32, true, 1420 MipsII::MO_ABS_HI); 1421 SDValue BALo = DAG.getBlockAddress(BA, MVT::i32, true, 1422 MipsII::MO_ABS_LO); 1423 SDValue Hi = DAG.getNode(MipsISD::Hi, dl, MVT::i32, BAHi); 1424 SDValue Lo = DAG.getNode(MipsISD::Lo, dl, MVT::i32, BALo); 1425 return DAG.getNode(ISD::ADD, dl, MVT::i32, Hi, Lo); 1426 } 1427 1428 SDValue BAGOTOffset = DAG.getBlockAddress(BA, MVT::i32, true, 1429 MipsII::MO_GOT); 1430 BAGOTOffset = DAG.getNode(MipsISD::WrapperPIC, dl, MVT::i32, BAGOTOffset); 1431 SDValue BALOOffset = DAG.getBlockAddress(BA, MVT::i32, true, 1432 MipsII::MO_ABS_LO); 1433 SDValue Load = DAG.getLoad(MVT::i32, dl, 1434 DAG.getEntryNode(), BAGOTOffset, 1435 MachinePointerInfo(), false, false, 0); 1436 SDValue Lo = DAG.getNode(MipsISD::Lo, dl, MVT::i32, BALOOffset); 1437 return DAG.getNode(ISD::ADD, dl, MVT::i32, Load, Lo); 1438 } 1439 1440 SDValue MipsTargetLowering:: 1441 LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const 1442 { 1443 // If the relocation model is PIC, use the General Dynamic TLS Model, 1444 // otherwise use the Initial Exec or Local Exec TLS Model. 1445 // TODO: implement Local Dynamic TLS model 1446 1447 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op); 1448 DebugLoc dl = GA->getDebugLoc(); 1449 const GlobalValue *GV = GA->getGlobal(); 1450 EVT PtrVT = getPointerTy(); 1451 1452 if (getTargetMachine().getRelocationModel() == Reloc::PIC_) { 1453 // General Dynamic TLS Model 1454 SDValue TGA = DAG.getTargetGlobalAddress(GV, dl, MVT::i32, 1455 0, MipsII::MO_TLSGD); 1456 SDValue Tlsgd = DAG.getNode(MipsISD::TlsGd, dl, MVT::i32, TGA); 1457 SDValue GP = DAG.getRegister(Mips::GP, MVT::i32); 1458 SDValue Argument = DAG.getNode(ISD::ADD, dl, MVT::i32, GP, Tlsgd); 1459 1460 ArgListTy Args; 1461 ArgListEntry Entry; 1462 Entry.Node = Argument; 1463 Entry.Ty = (Type *) Type::getInt32Ty(*DAG.getContext()); 1464 Args.push_back(Entry); 1465 std::pair<SDValue, SDValue> CallResult = 1466 LowerCallTo(DAG.getEntryNode(), 1467 (Type *) Type::getInt32Ty(*DAG.getContext()), 1468 false, false, false, false, 0, CallingConv::C, false, true, 1469 DAG.getExternalSymbol("__tls_get_addr", PtrVT), Args, DAG, 1470 dl); 1471 1472 return CallResult.first; 1473 } 1474 1475 SDValue Offset; 1476 if (GV->isDeclaration()) { 1477 // Initial Exec TLS Model 1478 SDValue TGA = DAG.getTargetGlobalAddress(GV, dl, MVT::i32, 0, 1479 MipsII::MO_GOTTPREL); 1480 Offset = DAG.getLoad(MVT::i32, dl, 1481 DAG.getEntryNode(), TGA, MachinePointerInfo(), 1482 false, false, 0); 1483 } else { 1484 // Local Exec TLS Model 1485 SDVTList VTs = DAG.getVTList(MVT::i32); 1486 SDValue TGAHi = DAG.getTargetGlobalAddress(GV, dl, MVT::i32, 0, 1487 MipsII::MO_TPREL_HI); 1488 SDValue TGALo = DAG.getTargetGlobalAddress(GV, dl, MVT::i32, 0, 1489 MipsII::MO_TPREL_LO); 1490 SDValue Hi = DAG.getNode(MipsISD::TprelHi, dl, VTs, &TGAHi, 1); 1491 SDValue Lo = DAG.getNode(MipsISD::TprelLo, dl, MVT::i32, TGALo); 1492 Offset = DAG.getNode(ISD::ADD, dl, MVT::i32, Hi, Lo); 1493 } 1494 1495 SDValue ThreadPointer = DAG.getNode(MipsISD::ThreadPointer, dl, PtrVT); 1496 return DAG.getNode(ISD::ADD, dl, PtrVT, ThreadPointer, Offset); 1497 } 1498 1499 SDValue MipsTargetLowering:: 1500 LowerJumpTable(SDValue Op, SelectionDAG &DAG) const 1501 { 1502 SDValue ResNode; 1503 SDValue HiPart; 1504 // FIXME there isn't actually debug info here 1505 DebugLoc dl = Op.getDebugLoc(); 1506 bool IsPIC = getTargetMachine().getRelocationModel() == Reloc::PIC_; 1507 unsigned char OpFlag = IsPIC ? MipsII::MO_GOT : MipsII::MO_ABS_HI; 1508 1509 EVT PtrVT = Op.getValueType(); 1510 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op); 1511 1512 SDValue JTI = DAG.getTargetJumpTable(JT->getIndex(), PtrVT, OpFlag); 1513 1514 if (!IsPIC) { 1515 SDValue Ops[] = { JTI }; 1516 HiPart = DAG.getNode(MipsISD::Hi, dl, DAG.getVTList(MVT::i32), Ops, 1); 1517 } else {// Emit Load from Global Pointer 1518 JTI = DAG.getNode(MipsISD::WrapperPIC, dl, MVT::i32, JTI); 1519 HiPart = DAG.getLoad(MVT::i32, dl, DAG.getEntryNode(), JTI, 1520 MachinePointerInfo(), 1521 false, false, 0); 1522 } 1523 1524 SDValue JTILo = DAG.getTargetJumpTable(JT->getIndex(), PtrVT, 1525 MipsII::MO_ABS_LO); 1526 SDValue Lo = DAG.getNode(MipsISD::Lo, dl, MVT::i32, JTILo); 1527 ResNode = DAG.getNode(ISD::ADD, dl, MVT::i32, HiPart, Lo); 1528 1529 return ResNode; 1530 } 1531 1532 SDValue MipsTargetLowering:: 1533 LowerConstantPool(SDValue Op, SelectionDAG &DAG) const 1534 { 1535 SDValue ResNode; 1536 ConstantPoolSDNode *N = cast<ConstantPoolSDNode>(Op); 1537 const Constant *C = N->getConstVal(); 1538 // FIXME there isn't actually debug info here 1539 DebugLoc dl = Op.getDebugLoc(); 1540 1541 // gp_rel relocation 1542 // FIXME: we should reference the constant pool using small data sections, 1543 // but the asm printer currently doesn't support this feature without 1544 // hacking it. This feature should come soon so we can uncomment the 1545 // stuff below. 1546 //if (IsInSmallSection(C->getType())) { 1547 // SDValue GPRelNode = DAG.getNode(MipsISD::GPRel, MVT::i32, CP); 1548 // SDValue GOT = DAG.getGLOBAL_OFFSET_TABLE(MVT::i32); 1549 // ResNode = DAG.getNode(ISD::ADD, MVT::i32, GOT, GPRelNode); 1550 1551 if (getTargetMachine().getRelocationModel() != Reloc::PIC_) { 1552 SDValue CPHi = DAG.getTargetConstantPool(C, MVT::i32, N->getAlignment(), 1553 N->getOffset(), MipsII::MO_ABS_HI); 1554 SDValue CPLo = DAG.getTargetConstantPool(C, MVT::i32, N->getAlignment(), 1555 N->getOffset(), MipsII::MO_ABS_LO); 1556 SDValue HiPart = DAG.getNode(MipsISD::Hi, dl, MVT::i32, CPHi); 1557 SDValue Lo = DAG.getNode(MipsISD::Lo, dl, MVT::i32, CPLo); 1558 ResNode = DAG.getNode(ISD::ADD, dl, MVT::i32, HiPart, Lo); 1559 } else { 1560 SDValue CP = DAG.getTargetConstantPool(C, MVT::i32, N->getAlignment(), 1561 N->getOffset(), MipsII::MO_GOT); 1562 CP = DAG.getNode(MipsISD::WrapperPIC, dl, MVT::i32, CP); 1563 SDValue Load = DAG.getLoad(MVT::i32, dl, DAG.getEntryNode(), 1564 CP, MachinePointerInfo::getConstantPool(), 1565 false, false, 0); 1566 SDValue CPLo = DAG.getTargetConstantPool(C, MVT::i32, N->getAlignment(), 1567 N->getOffset(), MipsII::MO_ABS_LO); 1568 SDValue Lo = DAG.getNode(MipsISD::Lo, dl, MVT::i32, CPLo); 1569 ResNode = DAG.getNode(ISD::ADD, dl, MVT::i32, Load, Lo); 1570 } 1571 1572 return ResNode; 1573 } 1574 1575 SDValue MipsTargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG) const { 1576 MachineFunction &MF = DAG.getMachineFunction(); 1577 MipsFunctionInfo *FuncInfo = MF.getInfo<MipsFunctionInfo>(); 1578 1579 DebugLoc dl = Op.getDebugLoc(); 1580 SDValue FI = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), 1581 getPointerTy()); 1582 1583 // vastart just stores the address of the VarArgsFrameIndex slot into the 1584 // memory location argument. 1585 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue(); 1586 return DAG.getStore(Op.getOperand(0), dl, FI, Op.getOperand(1), 1587 MachinePointerInfo(SV), 1588 false, false, 0); 1589 } 1590 1591 static SDValue LowerFCOPYSIGN32(SDValue Op, SelectionDAG &DAG) { 1592 // FIXME: Use ext/ins instructions if target architecture is Mips32r2. 1593 DebugLoc dl = Op.getDebugLoc(); 1594 SDValue Op0 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Op.getOperand(0)); 1595 SDValue Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Op.getOperand(1)); 1596 SDValue And0 = DAG.getNode(ISD::AND, dl, MVT::i32, Op0, 1597 DAG.getConstant(0x7fffffff, MVT::i32)); 1598 SDValue And1 = DAG.getNode(ISD::AND, dl, MVT::i32, Op1, 1599 DAG.getConstant(0x80000000, MVT::i32)); 1600 SDValue Result = DAG.getNode(ISD::OR, dl, MVT::i32, And0, And1); 1601 return DAG.getNode(ISD::BITCAST, dl, MVT::f32, Result); 1602 } 1603 1604 static SDValue LowerFCOPYSIGN64(SDValue Op, SelectionDAG &DAG, bool isLittle) { 1605 // FIXME: 1606 // Use ext/ins instructions if target architecture is Mips32r2. 1607 // Eliminate redundant mfc1 and mtc1 instructions. 1608 unsigned LoIdx = 0, HiIdx = 1; 1609 1610 if (!isLittle) 1611 std::swap(LoIdx, HiIdx); 1612 1613 DebugLoc dl = Op.getDebugLoc(); 1614 SDValue Word0 = DAG.getNode(MipsISD::ExtractElementF64, dl, MVT::i32, 1615 Op.getOperand(0), 1616 DAG.getConstant(LoIdx, MVT::i32)); 1617 SDValue Hi0 = DAG.getNode(MipsISD::ExtractElementF64, dl, MVT::i32, 1618 Op.getOperand(0), DAG.getConstant(HiIdx, MVT::i32)); 1619 SDValue Hi1 = DAG.getNode(MipsISD::ExtractElementF64, dl, MVT::i32, 1620 Op.getOperand(1), DAG.getConstant(HiIdx, MVT::i32)); 1621 SDValue And0 = DAG.getNode(ISD::AND, dl, MVT::i32, Hi0, 1622 DAG.getConstant(0x7fffffff, MVT::i32)); 1623 SDValue And1 = DAG.getNode(ISD::AND, dl, MVT::i32, Hi1, 1624 DAG.getConstant(0x80000000, MVT::i32)); 1625 SDValue Word1 = DAG.getNode(ISD::OR, dl, MVT::i32, And0, And1); 1626 1627 if (!isLittle) 1628 std::swap(Word0, Word1); 1629 1630 return DAG.getNode(MipsISD::BuildPairF64, dl, MVT::f64, Word0, Word1); 1631 } 1632 1633 SDValue MipsTargetLowering::LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) 1634 const { 1635 EVT Ty = Op.getValueType(); 1636 1637 assert(Ty == MVT::f32 || Ty == MVT::f64); 1638 1639 if (Ty == MVT::f32) 1640 return LowerFCOPYSIGN32(Op, DAG); 1641 else 1642 return LowerFCOPYSIGN64(Op, DAG, Subtarget->isLittle()); 1643 } 1644 1645 SDValue MipsTargetLowering:: 1646 LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const { 1647 // check the depth 1648 assert((cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue() == 0) && 1649 "Frame address can only be determined for current frame."); 1650 1651 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo(); 1652 MFI->setFrameAddressIsTaken(true); 1653 EVT VT = Op.getValueType(); 1654 DebugLoc dl = Op.getDebugLoc(); 1655 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, Mips::FP, VT); 1656 return FrameAddr; 1657 } 1658 1659 // TODO: set SType according to the desired memory barrier behavior. 1660 SDValue MipsTargetLowering::LowerMEMBARRIER(SDValue Op, 1661 SelectionDAG& DAG) const { 1662 unsigned SType = 0; 1663 DebugLoc dl = Op.getDebugLoc(); 1664 return DAG.getNode(MipsISD::Sync, dl, MVT::Other, Op.getOperand(0), 1665 DAG.getConstant(SType, MVT::i32)); 1666 } 1667 1668 SDValue MipsTargetLowering::LowerATOMIC_FENCE(SDValue Op, 1669 SelectionDAG& DAG) const { 1670 // FIXME: Need pseudo-fence for 'singlethread' fences 1671 // FIXME: Set SType for weaker fences where supported/appropriate. 1672 unsigned SType = 0; 1673 DebugLoc dl = Op.getDebugLoc(); 1674 return DAG.getNode(MipsISD::Sync, dl, MVT::Other, Op.getOperand(0), 1675 DAG.getConstant(SType, MVT::i32)); 1676 } 1677 1678 //===----------------------------------------------------------------------===// 1679 // Calling Convention Implementation 1680 //===----------------------------------------------------------------------===// 1681 1682 #include "MipsGenCallingConv.inc" 1683 1684 //===----------------------------------------------------------------------===// 1685 // TODO: Implement a generic logic using tblgen that can support this. 1686 // Mips O32 ABI rules: 1687 // --- 1688 // i32 - Passed in A0, A1, A2, A3 and stack 1689 // f32 - Only passed in f32 registers if no int reg has been used yet to hold 1690 // an argument. Otherwise, passed in A1, A2, A3 and stack. 1691 // f64 - Only passed in two aliased f32 registers if no int reg has been used 1692 // yet to hold an argument. Otherwise, use A2, A3 and stack. If A1 is 1693 // not used, it must be shadowed. If only A3 is avaiable, shadow it and 1694 // go to stack. 1695 // 1696 // For vararg functions, all arguments are passed in A0, A1, A2, A3 and stack. 1697 //===----------------------------------------------------------------------===// 1698 1699 static bool CC_MipsO32(unsigned ValNo, MVT ValVT, 1700 MVT LocVT, CCValAssign::LocInfo LocInfo, 1701 ISD::ArgFlagsTy ArgFlags, CCState &State) { 1702 1703 static const unsigned IntRegsSize=4, FloatRegsSize=2; 1704 1705 static const unsigned IntRegs[] = { 1706 Mips::A0, Mips::A1, Mips::A2, Mips::A3 1707 }; 1708 static const unsigned F32Regs[] = { 1709 Mips::F12, Mips::F14 1710 }; 1711 static const unsigned F64Regs[] = { 1712 Mips::D6, Mips::D7 1713 }; 1714 1715 // ByVal Args 1716 if (ArgFlags.isByVal()) { 1717 State.HandleByVal(ValNo, ValVT, LocVT, LocInfo, 1718 1 /*MinSize*/, 4 /*MinAlign*/, ArgFlags); 1719 unsigned NextReg = (State.getNextStackOffset() + 3) / 4; 1720 for (unsigned r = State.getFirstUnallocated(IntRegs, IntRegsSize); 1721 r < std::min(IntRegsSize, NextReg); ++r) 1722 State.AllocateReg(IntRegs[r]); 1723 return false; 1724 } 1725 1726 // Promote i8 and i16 1727 if (LocVT == MVT::i8 || LocVT == MVT::i16) { 1728 LocVT = MVT::i32; 1729 if (ArgFlags.isSExt()) 1730 LocInfo = CCValAssign::SExt; 1731 else if (ArgFlags.isZExt()) 1732 LocInfo = CCValAssign::ZExt; 1733 else 1734 LocInfo = CCValAssign::AExt; 1735 } 1736 1737 unsigned Reg; 1738 1739 // f32 and f64 are allocated in A0, A1, A2, A3 when either of the following 1740 // is true: function is vararg, argument is 3rd or higher, there is previous 1741 // argument which is not f32 or f64. 1742 bool AllocateFloatsInIntReg = State.isVarArg() || ValNo > 1 1743 || State.getFirstUnallocated(F32Regs, FloatRegsSize) != ValNo; 1744 unsigned OrigAlign = ArgFlags.getOrigAlign(); 1745 bool isI64 = (ValVT == MVT::i32 && OrigAlign == 8); 1746 1747 if (ValVT == MVT::i32 || (ValVT == MVT::f32 && AllocateFloatsInIntReg)) { 1748 Reg = State.AllocateReg(IntRegs, IntRegsSize); 1749 // If this is the first part of an i64 arg, 1750 // the allocated register must be either A0 or A2. 1751 if (isI64 && (Reg == Mips::A1 || Reg == Mips::A3)) 1752 Reg = State.AllocateReg(IntRegs, IntRegsSize); 1753 LocVT = MVT::i32; 1754 } else if (ValVT == MVT::f64 && AllocateFloatsInIntReg) { 1755 // Allocate int register and shadow next int register. If first 1756 // available register is Mips::A1 or Mips::A3, shadow it too. 1757 Reg = State.AllocateReg(IntRegs, IntRegsSize); 1758 if (Reg == Mips::A1 || Reg == Mips::A3) 1759 Reg = State.AllocateReg(IntRegs, IntRegsSize); 1760 State.AllocateReg(IntRegs, IntRegsSize); 1761 LocVT = MVT::i32; 1762 } else if (ValVT.isFloatingPoint() && !AllocateFloatsInIntReg) { 1763 // we are guaranteed to find an available float register 1764 if (ValVT == MVT::f32) { 1765 Reg = State.AllocateReg(F32Regs, FloatRegsSize); 1766 // Shadow int register 1767 State.AllocateReg(IntRegs, IntRegsSize); 1768 } else { 1769 Reg = State.AllocateReg(F64Regs, FloatRegsSize); 1770 // Shadow int registers 1771 unsigned Reg2 = State.AllocateReg(IntRegs, IntRegsSize); 1772 if (Reg2 == Mips::A1 || Reg2 == Mips::A3) 1773 State.AllocateReg(IntRegs, IntRegsSize); 1774 State.AllocateReg(IntRegs, IntRegsSize); 1775 } 1776 } else 1777 llvm_unreachable("Cannot handle this ValVT."); 1778 1779 unsigned SizeInBytes = ValVT.getSizeInBits() >> 3; 1780 unsigned Offset = State.AllocateStack(SizeInBytes, OrigAlign); 1781 1782 if (!Reg) 1783 State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo)); 1784 else 1785 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); 1786 1787 return false; // CC must always match 1788 } 1789 1790 //===----------------------------------------------------------------------===// 1791 // Call Calling Convention Implementation 1792 //===----------------------------------------------------------------------===// 1793 1794 static const unsigned O32IntRegsSize = 4; 1795 1796 static const unsigned O32IntRegs[] = { 1797 Mips::A0, Mips::A1, Mips::A2, Mips::A3 1798 }; 1799 1800 // Write ByVal Arg to arg registers and stack. 1801 static void 1802 WriteByValArg(SDValue& Chain, DebugLoc dl, 1803 SmallVector<std::pair<unsigned, SDValue>, 16>& RegsToPass, 1804 SmallVector<SDValue, 8>& MemOpChains, int& LastFI, 1805 MachineFrameInfo *MFI, SelectionDAG &DAG, SDValue Arg, 1806 const CCValAssign &VA, const ISD::ArgFlagsTy& Flags, 1807 MVT PtrType, bool isLittle) { 1808 unsigned LocMemOffset = VA.getLocMemOffset(); 1809 unsigned Offset = 0; 1810 uint32_t RemainingSize = Flags.getByValSize(); 1811 unsigned ByValAlign = Flags.getByValAlign(); 1812 1813 // Copy the first 4 words of byval arg to registers A0 - A3. 1814 // FIXME: Use a stricter alignment if it enables better optimization in passes 1815 // run later. 1816 for (; RemainingSize >= 4 && LocMemOffset < 4 * 4; 1817 Offset += 4, RemainingSize -= 4, LocMemOffset += 4) { 1818 SDValue LoadPtr = DAG.getNode(ISD::ADD, dl, MVT::i32, Arg, 1819 DAG.getConstant(Offset, MVT::i32)); 1820 SDValue LoadVal = DAG.getLoad(MVT::i32, dl, Chain, LoadPtr, 1821 MachinePointerInfo(), 1822 false, false, std::min(ByValAlign, 1823 (unsigned )4)); 1824 MemOpChains.push_back(LoadVal.getValue(1)); 1825 unsigned DstReg = O32IntRegs[LocMemOffset / 4]; 1826 RegsToPass.push_back(std::make_pair(DstReg, LoadVal)); 1827 } 1828 1829 if (RemainingSize == 0) 1830 return; 1831 1832 // If there still is a register available for argument passing, write the 1833 // remaining part of the structure to it using subword loads and shifts. 1834 if (LocMemOffset < 4 * 4) { 1835 assert(RemainingSize <= 3 && RemainingSize >= 1 && 1836 "There must be one to three bytes remaining."); 1837 unsigned LoadSize = (RemainingSize == 3 ? 2 : RemainingSize); 1838 SDValue LoadPtr = DAG.getNode(ISD::ADD, dl, MVT::i32, Arg, 1839 DAG.getConstant(Offset, MVT::i32)); 1840 unsigned Alignment = std::min(ByValAlign, (unsigned )4); 1841 SDValue LoadVal = DAG.getExtLoad(ISD::ZEXTLOAD, dl, MVT::i32, Chain, 1842 LoadPtr, MachinePointerInfo(), 1843 MVT::getIntegerVT(LoadSize * 8), false, 1844 false, Alignment); 1845 MemOpChains.push_back(LoadVal.getValue(1)); 1846 1847 // If target is big endian, shift it to the most significant half-word or 1848 // byte. 1849 if (!isLittle) 1850 LoadVal = DAG.getNode(ISD::SHL, dl, MVT::i32, LoadVal, 1851 DAG.getConstant(32 - LoadSize * 8, MVT::i32)); 1852 1853 Offset += LoadSize; 1854 RemainingSize -= LoadSize; 1855 1856 // Read second subword if necessary. 1857 if (RemainingSize != 0) { 1858 assert(RemainingSize == 1 && "There must be one byte remaining."); 1859 LoadPtr = DAG.getNode(ISD::ADD, dl, MVT::i32, Arg, 1860 DAG.getConstant(Offset, MVT::i32)); 1861 unsigned Alignment = std::min(ByValAlign, (unsigned )2); 1862 SDValue Subword = DAG.getExtLoad(ISD::ZEXTLOAD, dl, MVT::i32, Chain, 1863 LoadPtr, MachinePointerInfo(), 1864 MVT::i8, false, false, Alignment); 1865 MemOpChains.push_back(Subword.getValue(1)); 1866 // Insert the loaded byte to LoadVal. 1867 // FIXME: Use INS if supported by target. 1868 unsigned ShiftAmt = isLittle ? 16 : 8; 1869 SDValue Shift = DAG.getNode(ISD::SHL, dl, MVT::i32, Subword, 1870 DAG.getConstant(ShiftAmt, MVT::i32)); 1871 LoadVal = DAG.getNode(ISD::OR, dl, MVT::i32, LoadVal, Shift); 1872 } 1873 1874 unsigned DstReg = O32IntRegs[LocMemOffset / 4]; 1875 RegsToPass.push_back(std::make_pair(DstReg, LoadVal)); 1876 return; 1877 } 1878 1879 // Create a fixed object on stack at offset LocMemOffset and copy 1880 // remaining part of byval arg to it using memcpy. 1881 SDValue Src = DAG.getNode(ISD::ADD, dl, MVT::i32, Arg, 1882 DAG.getConstant(Offset, MVT::i32)); 1883 LastFI = MFI->CreateFixedObject(RemainingSize, LocMemOffset, true); 1884 SDValue Dst = DAG.getFrameIndex(LastFI, PtrType); 1885 Chain = DAG.getMemcpy(Chain, dl, Dst, Src, 1886 DAG.getConstant(RemainingSize, MVT::i32), 1887 std::min(ByValAlign, (unsigned)4), 1888 /*isVolatile=*/false, /*AlwaysInline=*/false, 1889 MachinePointerInfo(0), MachinePointerInfo(0)); 1890 MemOpChains.push_back(Chain); 1891 } 1892 1893 /// LowerCall - functions arguments are copied from virtual regs to 1894 /// (physical regs)/(stack frame), CALLSEQ_START and CALLSEQ_END are emitted. 1895 /// TODO: isTailCall. 1896 SDValue 1897 MipsTargetLowering::LowerCall(SDValue Chain, SDValue Callee, 1898 CallingConv::ID CallConv, bool isVarArg, 1899 bool &isTailCall, 1900 const SmallVectorImpl<ISD::OutputArg> &Outs, 1901 const SmallVectorImpl<SDValue> &OutVals, 1902 const SmallVectorImpl<ISD::InputArg> &Ins, 1903 DebugLoc dl, SelectionDAG &DAG, 1904 SmallVectorImpl<SDValue> &InVals) const { 1905 // MIPs target does not yet support tail call optimization. 1906 isTailCall = false; 1907 1908 MachineFunction &MF = DAG.getMachineFunction(); 1909 MachineFrameInfo *MFI = MF.getFrameInfo(); 1910 const TargetFrameLowering *TFL = MF.getTarget().getFrameLowering(); 1911 bool IsPIC = getTargetMachine().getRelocationModel() == Reloc::PIC_; 1912 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>(); 1913 1914 // Analyze operands of the call, assigning locations to each operand. 1915 SmallVector<CCValAssign, 16> ArgLocs; 1916 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), 1917 getTargetMachine(), ArgLocs, *DAG.getContext()); 1918 1919 if (Subtarget->isABI_O32()) 1920 CCInfo.AnalyzeCallOperands(Outs, CC_MipsO32); 1921 else 1922 CCInfo.AnalyzeCallOperands(Outs, CC_Mips); 1923 1924 // Get a count of how many bytes are to be pushed on the stack. 1925 unsigned NextStackOffset = CCInfo.getNextStackOffset(); 1926 1927 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NextStackOffset, 1928 true)); 1929 1930 // If this is the first call, create a stack frame object that points to 1931 // a location to which .cprestore saves $gp. 1932 if (IsPIC && !MipsFI->getGPFI()) 1933 MipsFI->setGPFI(MFI->CreateFixedObject(4, 0, true)); 1934 1935 // Get the frame index of the stack frame object that points to the location 1936 // of dynamically allocated area on the stack. 1937 int DynAllocFI = MipsFI->getDynAllocFI(); 1938 1939 // Update size of the maximum argument space. 1940 // For O32, a minimum of four words (16 bytes) of argument space is 1941 // allocated. 1942 if (Subtarget->isABI_O32()) 1943 NextStackOffset = std::max(NextStackOffset, (unsigned)16); 1944 1945 unsigned MaxCallFrameSize = MipsFI->getMaxCallFrameSize(); 1946 1947 if (MaxCallFrameSize < NextStackOffset) { 1948 MipsFI->setMaxCallFrameSize(NextStackOffset); 1949 1950 // Set the offsets relative to $sp of the $gp restore slot and dynamically 1951 // allocated stack space. These offsets must be aligned to a boundary 1952 // determined by the stack alignment of the ABI. 1953 unsigned StackAlignment = TFL->getStackAlignment(); 1954 NextStackOffset = (NextStackOffset + StackAlignment - 1) / 1955 StackAlignment * StackAlignment; 1956 1957 if (IsPIC) 1958 MFI->setObjectOffset(MipsFI->getGPFI(), NextStackOffset); 1959 1960 MFI->setObjectOffset(DynAllocFI, NextStackOffset); 1961 } 1962 1963 // With EABI is it possible to have 16 args on registers. 1964 SmallVector<std::pair<unsigned, SDValue>, 16> RegsToPass; 1965 SmallVector<SDValue, 8> MemOpChains; 1966 1967 int FirstFI = -MFI->getNumFixedObjects() - 1, LastFI = 0; 1968 1969 // Walk the register/memloc assignments, inserting copies/loads. 1970 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { 1971 SDValue Arg = OutVals[i]; 1972 CCValAssign &VA = ArgLocs[i]; 1973 1974 // Promote the value if needed. 1975 switch (VA.getLocInfo()) { 1976 default: llvm_unreachable("Unknown loc info!"); 1977 case CCValAssign::Full: 1978 if (Subtarget->isABI_O32() && VA.isRegLoc()) { 1979 if (VA.getValVT() == MVT::f32 && VA.getLocVT() == MVT::i32) 1980 Arg = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Arg); 1981 if (VA.getValVT() == MVT::f64 && VA.getLocVT() == MVT::i32) { 1982 SDValue Lo = DAG.getNode(MipsISD::ExtractElementF64, dl, MVT::i32, 1983 Arg, DAG.getConstant(0, MVT::i32)); 1984 SDValue Hi = DAG.getNode(MipsISD::ExtractElementF64, dl, MVT::i32, 1985 Arg, DAG.getConstant(1, MVT::i32)); 1986 if (!Subtarget->isLittle()) 1987 std::swap(Lo, Hi); 1988 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Lo)); 1989 RegsToPass.push_back(std::make_pair(VA.getLocReg()+1, Hi)); 1990 continue; 1991 } 1992 } 1993 break; 1994 case CCValAssign::SExt: 1995 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg); 1996 break; 1997 case CCValAssign::ZExt: 1998 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg); 1999 break; 2000 case CCValAssign::AExt: 2001 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg); 2002 break; 2003 } 2004 2005 // Arguments that can be passed on register must be kept at 2006 // RegsToPass vector 2007 if (VA.isRegLoc()) { 2008 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg)); 2009 continue; 2010 } 2011 2012 // Register can't get to this point... 2013 assert(VA.isMemLoc()); 2014 2015 // ByVal Arg. 2016 ISD::ArgFlagsTy Flags = Outs[i].Flags; 2017 if (Flags.isByVal()) { 2018 assert(Subtarget->isABI_O32() && 2019 "No support for ByVal args by ABIs other than O32 yet."); 2020 assert(Flags.getByValSize() && 2021 "ByVal args of size 0 should have been ignored by front-end."); 2022 WriteByValArg(Chain, dl, RegsToPass, MemOpChains, LastFI, MFI, DAG, Arg, 2023 VA, Flags, getPointerTy(), Subtarget->isLittle()); 2024 continue; 2025 } 2026 2027 // Create the frame index object for this incoming parameter 2028 LastFI = MFI->CreateFixedObject(VA.getValVT().getSizeInBits()/8, 2029 VA.getLocMemOffset(), true); 2030 SDValue PtrOff = DAG.getFrameIndex(LastFI, getPointerTy()); 2031 2032 // emit ISD::STORE whichs stores the 2033 // parameter value to a stack Location 2034 MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, PtrOff, 2035 MachinePointerInfo(), 2036 false, false, 0)); 2037 } 2038 2039 // Extend range of indices of frame objects for outgoing arguments that were 2040 // created during this function call. Skip this step if no such objects were 2041 // created. 2042 if (LastFI) 2043 MipsFI->extendOutArgFIRange(FirstFI, LastFI); 2044 2045 // Transform all store nodes into one single node because all store 2046 // nodes are independent of each other. 2047 if (!MemOpChains.empty()) 2048 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, 2049 &MemOpChains[0], MemOpChains.size()); 2050 2051 // If the callee is a GlobalAddress/ExternalSymbol node (quite common, every 2052 // direct call is) turn it into a TargetGlobalAddress/TargetExternalSymbol 2053 // node so that legalize doesn't hack it. 2054 unsigned char OpFlag = IsPIC ? MipsII::MO_GOT_CALL : MipsII::MO_NO_FLAG; 2055 bool LoadSymAddr = false; 2056 SDValue CalleeLo; 2057 2058 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) { 2059 if (IsPIC && G->getGlobal()->hasInternalLinkage()) { 2060 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), dl, 2061 getPointerTy(), 0,MipsII:: MO_GOT); 2062 CalleeLo = DAG.getTargetGlobalAddress(G->getGlobal(), dl, getPointerTy(), 2063 0, MipsII::MO_ABS_LO); 2064 } else { 2065 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), dl, 2066 getPointerTy(), 0, OpFlag); 2067 } 2068 2069 LoadSymAddr = true; 2070 } 2071 else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) { 2072 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), 2073 getPointerTy(), OpFlag); 2074 LoadSymAddr = true; 2075 } 2076 2077 SDValue InFlag; 2078 2079 // Create nodes that load address of callee and copy it to T9 2080 if (IsPIC) { 2081 if (LoadSymAddr) { 2082 // Load callee address 2083 Callee = DAG.getNode(MipsISD::WrapperPIC, dl, MVT::i32, Callee); 2084 SDValue LoadValue = DAG.getLoad(MVT::i32, dl, DAG.getEntryNode(), Callee, 2085 MachinePointerInfo::getGOT(), 2086 false, false, 0); 2087 2088 // Use GOT+LO if callee has internal linkage. 2089 if (CalleeLo.getNode()) { 2090 SDValue Lo = DAG.getNode(MipsISD::Lo, dl, MVT::i32, CalleeLo); 2091 Callee = DAG.getNode(ISD::ADD, dl, MVT::i32, LoadValue, Lo); 2092 } else 2093 Callee = LoadValue; 2094 } 2095 2096 // copy to T9 2097 Chain = DAG.getCopyToReg(Chain, dl, Mips::T9, Callee, SDValue(0, 0)); 2098 InFlag = Chain.getValue(1); 2099 Callee = DAG.getRegister(Mips::T9, MVT::i32); 2100 } 2101 2102 // Build a sequence of copy-to-reg nodes chained together with token 2103 // chain and flag operands which copy the outgoing args into registers. 2104 // The InFlag in necessary since all emitted instructions must be 2105 // stuck together. 2106 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) { 2107 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first, 2108 RegsToPass[i].second, InFlag); 2109 InFlag = Chain.getValue(1); 2110 } 2111 2112 // MipsJmpLink = #chain, #target_address, #opt_in_flags... 2113 // = Chain, Callee, Reg#1, Reg#2, ... 2114 // 2115 // Returns a chain & a flag for retval copy to use. 2116 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue); 2117 SmallVector<SDValue, 8> Ops; 2118 Ops.push_back(Chain); 2119 Ops.push_back(Callee); 2120 2121 // Add argument registers to the end of the list so that they are 2122 // known live into the call. 2123 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) 2124 Ops.push_back(DAG.getRegister(RegsToPass[i].first, 2125 RegsToPass[i].second.getValueType())); 2126 2127 if (InFlag.getNode()) 2128 Ops.push_back(InFlag); 2129 2130 Chain = DAG.getNode(MipsISD::JmpLink, dl, NodeTys, &Ops[0], Ops.size()); 2131 InFlag = Chain.getValue(1); 2132 2133 // Create the CALLSEQ_END node. 2134 Chain = DAG.getCALLSEQ_END(Chain, 2135 DAG.getIntPtrConstant(NextStackOffset, true), 2136 DAG.getIntPtrConstant(0, true), InFlag); 2137 InFlag = Chain.getValue(1); 2138 2139 // Handle result values, copying them out of physregs into vregs that we 2140 // return. 2141 return LowerCallResult(Chain, InFlag, CallConv, isVarArg, 2142 Ins, dl, DAG, InVals); 2143 } 2144 2145 /// LowerCallResult - Lower the result values of a call into the 2146 /// appropriate copies out of appropriate physical registers. 2147 SDValue 2148 MipsTargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag, 2149 CallingConv::ID CallConv, bool isVarArg, 2150 const SmallVectorImpl<ISD::InputArg> &Ins, 2151 DebugLoc dl, SelectionDAG &DAG, 2152 SmallVectorImpl<SDValue> &InVals) const { 2153 // Assign locations to each value returned by this call. 2154 SmallVector<CCValAssign, 16> RVLocs; 2155 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), 2156 getTargetMachine(), RVLocs, *DAG.getContext()); 2157 2158 CCInfo.AnalyzeCallResult(Ins, RetCC_Mips); 2159 2160 // Copy all of the result registers out of their specified physreg. 2161 for (unsigned i = 0; i != RVLocs.size(); ++i) { 2162 Chain = DAG.getCopyFromReg(Chain, dl, RVLocs[i].getLocReg(), 2163 RVLocs[i].getValVT(), InFlag).getValue(1); 2164 InFlag = Chain.getValue(2); 2165 InVals.push_back(Chain.getValue(0)); 2166 } 2167 2168 return Chain; 2169 } 2170 2171 //===----------------------------------------------------------------------===// 2172 // Formal Arguments Calling Convention Implementation 2173 //===----------------------------------------------------------------------===// 2174 static void ReadByValArg(MachineFunction &MF, SDValue Chain, DebugLoc dl, 2175 std::vector<SDValue>& OutChains, 2176 SelectionDAG &DAG, unsigned NumWords, SDValue FIN, 2177 const CCValAssign &VA, const ISD::ArgFlagsTy& Flags) { 2178 unsigned LocMem = VA.getLocMemOffset(); 2179 unsigned FirstWord = LocMem / 4; 2180 2181 // copy register A0 - A3 to frame object 2182 for (unsigned i = 0; i < NumWords; ++i) { 2183 unsigned CurWord = FirstWord + i; 2184 if (CurWord >= O32IntRegsSize) 2185 break; 2186 2187 unsigned SrcReg = O32IntRegs[CurWord]; 2188 unsigned Reg = AddLiveIn(MF, SrcReg, Mips::CPURegsRegisterClass); 2189 SDValue StorePtr = DAG.getNode(ISD::ADD, dl, MVT::i32, FIN, 2190 DAG.getConstant(i * 4, MVT::i32)); 2191 SDValue Store = DAG.getStore(Chain, dl, DAG.getRegister(Reg, MVT::i32), 2192 StorePtr, MachinePointerInfo(), false, 2193 false, 0); 2194 OutChains.push_back(Store); 2195 } 2196 } 2197 2198 /// LowerFormalArguments - transform physical registers into virtual registers 2199 /// and generate load operations for arguments places on the stack. 2200 SDValue 2201 MipsTargetLowering::LowerFormalArguments(SDValue Chain, 2202 CallingConv::ID CallConv, 2203 bool isVarArg, 2204 const SmallVectorImpl<ISD::InputArg> 2205 &Ins, 2206 DebugLoc dl, SelectionDAG &DAG, 2207 SmallVectorImpl<SDValue> &InVals) 2208 const { 2209 MachineFunction &MF = DAG.getMachineFunction(); 2210 MachineFrameInfo *MFI = MF.getFrameInfo(); 2211 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>(); 2212 2213 MipsFI->setVarArgsFrameIndex(0); 2214 2215 // Used with vargs to acumulate store chains. 2216 std::vector<SDValue> OutChains; 2217 2218 // Assign locations to all of the incoming arguments. 2219 SmallVector<CCValAssign, 16> ArgLocs; 2220 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), 2221 getTargetMachine(), ArgLocs, *DAG.getContext()); 2222 2223 if (Subtarget->isABI_O32()) 2224 CCInfo.AnalyzeFormalArguments(Ins, CC_MipsO32); 2225 else 2226 CCInfo.AnalyzeFormalArguments(Ins, CC_Mips); 2227 2228 int LastFI = 0;// MipsFI->LastInArgFI is 0 at the entry of this function. 2229 2230 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { 2231 CCValAssign &VA = ArgLocs[i]; 2232 2233 // Arguments stored on registers 2234 if (VA.isRegLoc()) { 2235 EVT RegVT = VA.getLocVT(); 2236 unsigned ArgReg = VA.getLocReg(); 2237 TargetRegisterClass *RC = 0; 2238 2239 if (RegVT == MVT::i32) 2240 RC = Mips::CPURegsRegisterClass; 2241 else if (RegVT == MVT::f32) 2242 RC = Mips::FGR32RegisterClass; 2243 else if (RegVT == MVT::f64) { 2244 if (!Subtarget->isSingleFloat()) 2245 RC = Mips::AFGR64RegisterClass; 2246 } else 2247 llvm_unreachable("RegVT not supported by FormalArguments Lowering"); 2248 2249 // Transform the arguments stored on 2250 // physical registers into virtual ones 2251 unsigned Reg = AddLiveIn(DAG.getMachineFunction(), ArgReg, RC); 2252 SDValue ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT); 2253 2254 // If this is an 8 or 16-bit value, it has been passed promoted 2255 // to 32 bits. Insert an assert[sz]ext to capture this, then 2256 // truncate to the right size. 2257 if (VA.getLocInfo() != CCValAssign::Full) { 2258 unsigned Opcode = 0; 2259 if (VA.getLocInfo() == CCValAssign::SExt) 2260 Opcode = ISD::AssertSext; 2261 else if (VA.getLocInfo() == CCValAssign::ZExt) 2262 Opcode = ISD::AssertZext; 2263 if (Opcode) 2264 ArgValue = DAG.getNode(Opcode, dl, RegVT, ArgValue, 2265 DAG.getValueType(VA.getValVT())); 2266 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue); 2267 } 2268 2269 // Handle O32 ABI cases: i32->f32 and (i32,i32)->f64 2270 if (Subtarget->isABI_O32()) { 2271 if (RegVT == MVT::i32 && VA.getValVT() == MVT::f32) 2272 ArgValue = DAG.getNode(ISD::BITCAST, dl, MVT::f32, ArgValue); 2273 if (RegVT == MVT::i32 && VA.getValVT() == MVT::f64) { 2274 unsigned Reg2 = AddLiveIn(DAG.getMachineFunction(), 2275 VA.getLocReg()+1, RC); 2276 SDValue ArgValue2 = DAG.getCopyFromReg(Chain, dl, Reg2, RegVT); 2277 if (!Subtarget->isLittle()) 2278 std::swap(ArgValue, ArgValue2); 2279 ArgValue = DAG.getNode(MipsISD::BuildPairF64, dl, MVT::f64, 2280 ArgValue, ArgValue2); 2281 } 2282 } 2283 2284 InVals.push_back(ArgValue); 2285 } else { // VA.isRegLoc() 2286 2287 // sanity check 2288 assert(VA.isMemLoc()); 2289 2290 ISD::ArgFlagsTy Flags = Ins[i].Flags; 2291 2292 if (Flags.isByVal()) { 2293 assert(Subtarget->isABI_O32() && 2294 "No support for ByVal args by ABIs other than O32 yet."); 2295 assert(Flags.getByValSize() && 2296 "ByVal args of size 0 should have been ignored by front-end."); 2297 unsigned NumWords = (Flags.getByValSize() + 3) / 4; 2298 LastFI = MFI->CreateFixedObject(NumWords * 4, VA.getLocMemOffset(), 2299 true); 2300 SDValue FIN = DAG.getFrameIndex(LastFI, getPointerTy()); 2301 InVals.push_back(FIN); 2302 ReadByValArg(MF, Chain, dl, OutChains, DAG, NumWords, FIN, VA, Flags); 2303 2304 continue; 2305 } 2306 2307 // The stack pointer offset is relative to the caller stack frame. 2308 LastFI = MFI->CreateFixedObject(VA.getValVT().getSizeInBits()/8, 2309 VA.getLocMemOffset(), true); 2310 2311 // Create load nodes to retrieve arguments from the stack 2312 SDValue FIN = DAG.getFrameIndex(LastFI, getPointerTy()); 2313 InVals.push_back(DAG.getLoad(VA.getValVT(), dl, Chain, FIN, 2314 MachinePointerInfo::getFixedStack(LastFI), 2315 false, false, 0)); 2316 } 2317 } 2318 2319 // The mips ABIs for returning structs by value requires that we copy 2320 // the sret argument into $v0 for the return. Save the argument into 2321 // a virtual register so that we can access it from the return points. 2322 if (DAG.getMachineFunction().getFunction()->hasStructRetAttr()) { 2323 unsigned Reg = MipsFI->getSRetReturnReg(); 2324 if (!Reg) { 2325 Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(MVT::i32)); 2326 MipsFI->setSRetReturnReg(Reg); 2327 } 2328 SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), dl, Reg, InVals[0]); 2329 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Copy, Chain); 2330 } 2331 2332 if (isVarArg && Subtarget->isABI_O32()) { 2333 // Record the frame index of the first variable argument 2334 // which is a value necessary to VASTART. 2335 unsigned NextStackOffset = CCInfo.getNextStackOffset(); 2336 assert(NextStackOffset % 4 == 0 && 2337 "NextStackOffset must be aligned to 4-byte boundaries."); 2338 LastFI = MFI->CreateFixedObject(4, NextStackOffset, true); 2339 MipsFI->setVarArgsFrameIndex(LastFI); 2340 2341 // If NextStackOffset is smaller than o32's 16-byte reserved argument area, 2342 // copy the integer registers that have not been used for argument passing 2343 // to the caller's stack frame. 2344 for (; NextStackOffset < 16; NextStackOffset += 4) { 2345 TargetRegisterClass *RC = Mips::CPURegsRegisterClass; 2346 unsigned Idx = NextStackOffset / 4; 2347 unsigned Reg = AddLiveIn(DAG.getMachineFunction(), O32IntRegs[Idx], RC); 2348 SDValue ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, MVT::i32); 2349 LastFI = MFI->CreateFixedObject(4, NextStackOffset, true); 2350 SDValue PtrOff = DAG.getFrameIndex(LastFI, getPointerTy()); 2351 OutChains.push_back(DAG.getStore(Chain, dl, ArgValue, PtrOff, 2352 MachinePointerInfo(), 2353 false, false, 0)); 2354 } 2355 } 2356 2357 MipsFI->setLastInArgFI(LastFI); 2358 2359 // All stores are grouped in one node to allow the matching between 2360 // the size of Ins and InVals. This only happens when on varg functions 2361 if (!OutChains.empty()) { 2362 OutChains.push_back(Chain); 2363 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, 2364 &OutChains[0], OutChains.size()); 2365 } 2366 2367 return Chain; 2368 } 2369 2370 //===----------------------------------------------------------------------===// 2371 // Return Value Calling Convention Implementation 2372 //===----------------------------------------------------------------------===// 2373 2374 SDValue 2375 MipsTargetLowering::LowerReturn(SDValue Chain, 2376 CallingConv::ID CallConv, bool isVarArg, 2377 const SmallVectorImpl<ISD::OutputArg> &Outs, 2378 const SmallVectorImpl<SDValue> &OutVals, 2379 DebugLoc dl, SelectionDAG &DAG) const { 2380 2381 // CCValAssign - represent the assignment of 2382 // the return value to a location 2383 SmallVector<CCValAssign, 16> RVLocs; 2384 2385 // CCState - Info about the registers and stack slot. 2386 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), 2387 getTargetMachine(), RVLocs, *DAG.getContext()); 2388 2389 // Analize return values. 2390 CCInfo.AnalyzeReturn(Outs, RetCC_Mips); 2391 2392 // If this is the first return lowered for this function, add 2393 // the regs to the liveout set for the function. 2394 if (DAG.getMachineFunction().getRegInfo().liveout_empty()) { 2395 for (unsigned i = 0; i != RVLocs.size(); ++i) 2396 if (RVLocs[i].isRegLoc()) 2397 DAG.getMachineFunction().getRegInfo().addLiveOut(RVLocs[i].getLocReg()); 2398 } 2399 2400 SDValue Flag; 2401 2402 // Copy the result values into the output registers. 2403 for (unsigned i = 0; i != RVLocs.size(); ++i) { 2404 CCValAssign &VA = RVLocs[i]; 2405 assert(VA.isRegLoc() && "Can only return in registers!"); 2406 2407 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), 2408 OutVals[i], Flag); 2409 2410 // guarantee that all emitted copies are 2411 // stuck together, avoiding something bad 2412 Flag = Chain.getValue(1); 2413 } 2414 2415 // The mips ABIs for returning structs by value requires that we copy 2416 // the sret argument into $v0 for the return. We saved the argument into 2417 // a virtual register in the entry block, so now we copy the value out 2418 // and into $v0. 2419 if (DAG.getMachineFunction().getFunction()->hasStructRetAttr()) { 2420 MachineFunction &MF = DAG.getMachineFunction(); 2421 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>(); 2422 unsigned Reg = MipsFI->getSRetReturnReg(); 2423 2424 if (!Reg) 2425 llvm_unreachable("sret virtual register not created in the entry block"); 2426 SDValue Val = DAG.getCopyFromReg(Chain, dl, Reg, getPointerTy()); 2427 2428 Chain = DAG.getCopyToReg(Chain, dl, Mips::V0, Val, Flag); 2429 Flag = Chain.getValue(1); 2430 } 2431 2432 // Return on Mips is always a "jr $ra" 2433 if (Flag.getNode()) 2434 return DAG.getNode(MipsISD::Ret, dl, MVT::Other, 2435 Chain, DAG.getRegister(Mips::RA, MVT::i32), Flag); 2436 else // Return Void 2437 return DAG.getNode(MipsISD::Ret, dl, MVT::Other, 2438 Chain, DAG.getRegister(Mips::RA, MVT::i32)); 2439 } 2440 2441 //===----------------------------------------------------------------------===// 2442 // Mips Inline Assembly Support 2443 //===----------------------------------------------------------------------===// 2444 2445 /// getConstraintType - Given a constraint letter, return the type of 2446 /// constraint it is for this target. 2447 MipsTargetLowering::ConstraintType MipsTargetLowering:: 2448 getConstraintType(const std::string &Constraint) const 2449 { 2450 // Mips specific constrainy 2451 // GCC config/mips/constraints.md 2452 // 2453 // 'd' : An address register. Equivalent to r 2454 // unless generating MIPS16 code. 2455 // 'y' : Equivalent to r; retained for 2456 // backwards compatibility. 2457 // 'f' : Floating Point registers. 2458 if (Constraint.size() == 1) { 2459 switch (Constraint[0]) { 2460 default : break; 2461 case 'd': 2462 case 'y': 2463 case 'f': 2464 return C_RegisterClass; 2465 break; 2466 } 2467 } 2468 return TargetLowering::getConstraintType(Constraint); 2469 } 2470 2471 /// Examine constraint type and operand type and determine a weight value. 2472 /// This object must already have been set up with the operand type 2473 /// and the current alternative constraint selected. 2474 TargetLowering::ConstraintWeight 2475 MipsTargetLowering::getSingleConstraintMatchWeight( 2476 AsmOperandInfo &info, const char *constraint) const { 2477 ConstraintWeight weight = CW_Invalid; 2478 Value *CallOperandVal = info.CallOperandVal; 2479 // If we don't have a value, we can't do a match, 2480 // but allow it at the lowest weight. 2481 if (CallOperandVal == NULL) 2482 return CW_Default; 2483 Type *type = CallOperandVal->getType(); 2484 // Look at the constraint type. 2485 switch (*constraint) { 2486 default: 2487 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint); 2488 break; 2489 case 'd': 2490 case 'y': 2491 if (type->isIntegerTy()) 2492 weight = CW_Register; 2493 break; 2494 case 'f': 2495 if (type->isFloatTy()) 2496 weight = CW_Register; 2497 break; 2498 } 2499 return weight; 2500 } 2501 2502 /// Given a register class constraint, like 'r', if this corresponds directly 2503 /// to an LLVM register class, return a register of 0 and the register class 2504 /// pointer. 2505 std::pair<unsigned, const TargetRegisterClass*> MipsTargetLowering:: 2506 getRegForInlineAsmConstraint(const std::string &Constraint, EVT VT) const 2507 { 2508 if (Constraint.size() == 1) { 2509 switch (Constraint[0]) { 2510 case 'd': // Address register. Same as 'r' unless generating MIPS16 code. 2511 case 'y': // Same as 'r'. Exists for compatibility. 2512 case 'r': 2513 return std::make_pair(0U, Mips::CPURegsRegisterClass); 2514 case 'f': 2515 if (VT == MVT::f32) 2516 return std::make_pair(0U, Mips::FGR32RegisterClass); 2517 if (VT == MVT::f64) 2518 if ((!Subtarget->isSingleFloat()) && (!Subtarget->isFP64bit())) 2519 return std::make_pair(0U, Mips::AFGR64RegisterClass); 2520 break; 2521 } 2522 } 2523 return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT); 2524 } 2525 2526 bool 2527 MipsTargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const { 2528 // The Mips target isn't yet aware of offsets. 2529 return false; 2530 } 2531 2532 bool MipsTargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const { 2533 if (VT != MVT::f32 && VT != MVT::f64) 2534 return false; 2535 if (Imm.isNegZero()) 2536 return false; 2537 return Imm.isZero(); 2538 } 2539