1 //===-- MipsISelLowering.cpp - Mips DAG Lowering Implementation -----------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file defines the interfaces that Mips uses to lower LLVM code into a 11 // selection DAG. 12 // 13 //===----------------------------------------------------------------------===// 14 #include "MipsISelLowering.h" 15 #include "InstPrinter/MipsInstPrinter.h" 16 #include "MCTargetDesc/MipsBaseInfo.h" 17 #include "MipsCCState.h" 18 #include "MipsMachineFunction.h" 19 #include "MipsSubtarget.h" 20 #include "MipsTargetMachine.h" 21 #include "MipsTargetObjectFile.h" 22 #include "llvm/ADT/Statistic.h" 23 #include "llvm/ADT/StringSwitch.h" 24 #include "llvm/CodeGen/CallingConvLower.h" 25 #include "llvm/CodeGen/MachineFrameInfo.h" 26 #include "llvm/CodeGen/MachineFunction.h" 27 #include "llvm/CodeGen/MachineInstrBuilder.h" 28 #include "llvm/CodeGen/MachineJumpTableInfo.h" 29 #include "llvm/CodeGen/MachineRegisterInfo.h" 30 #include "llvm/CodeGen/FunctionLoweringInfo.h" 31 #include "llvm/CodeGen/SelectionDAGISel.h" 32 #include "llvm/CodeGen/ValueTypes.h" 33 #include "llvm/IR/CallingConv.h" 34 #include "llvm/IR/DerivedTypes.h" 35 #include "llvm/IR/GlobalVariable.h" 36 #include "llvm/Support/CommandLine.h" 37 #include "llvm/Support/Debug.h" 38 #include "llvm/Support/ErrorHandling.h" 39 #include "llvm/Support/raw_ostream.h" 40 #include <cctype> 41 42 using namespace llvm; 43 44 #define DEBUG_TYPE "mips-lower" 45 46 STATISTIC(NumTailCalls, "Number of tail calls"); 47 48 static cl::opt<bool> 49 LargeGOT("mxgot", cl::Hidden, 50 cl::desc("MIPS: Enable GOT larger than 64k."), cl::init(false)); 51 52 static cl::opt<bool> 53 NoZeroDivCheck("mno-check-zero-division", cl::Hidden, 54 cl::desc("MIPS: Don't trap on integer division by zero."), 55 cl::init(false)); 56 57 static const MCPhysReg Mips64DPRegs[8] = { 58 Mips::D12_64, Mips::D13_64, Mips::D14_64, Mips::D15_64, 59 Mips::D16_64, Mips::D17_64, Mips::D18_64, Mips::D19_64 60 }; 61 62 // If I is a shifted mask, set the size (Size) and the first bit of the 63 // mask (Pos), and return true. 64 // For example, if I is 0x003ff800, (Pos, Size) = (11, 11). 65 static bool isShiftedMask(uint64_t I, uint64_t &Pos, uint64_t &Size) { 66 if (!isShiftedMask_64(I)) 67 return false; 68 69 Size = countPopulation(I); 70 Pos = countTrailingZeros(I); 71 return true; 72 } 73 74 SDValue MipsTargetLowering::getGlobalReg(SelectionDAG &DAG, EVT Ty) const { 75 MipsFunctionInfo *FI = DAG.getMachineFunction().getInfo<MipsFunctionInfo>(); 76 return DAG.getRegister(FI->getGlobalBaseReg(), Ty); 77 } 78 79 SDValue MipsTargetLowering::getTargetNode(GlobalAddressSDNode *N, EVT Ty, 80 SelectionDAG &DAG, 81 unsigned Flag) const { 82 return DAG.getTargetGlobalAddress(N->getGlobal(), SDLoc(N), Ty, 0, Flag); 83 } 84 85 SDValue MipsTargetLowering::getTargetNode(ExternalSymbolSDNode *N, EVT Ty, 86 SelectionDAG &DAG, 87 unsigned Flag) const { 88 return DAG.getTargetExternalSymbol(N->getSymbol(), Ty, Flag); 89 } 90 91 SDValue MipsTargetLowering::getTargetNode(BlockAddressSDNode *N, EVT Ty, 92 SelectionDAG &DAG, 93 unsigned Flag) const { 94 return DAG.getTargetBlockAddress(N->getBlockAddress(), Ty, 0, Flag); 95 } 96 97 SDValue MipsTargetLowering::getTargetNode(JumpTableSDNode *N, EVT Ty, 98 SelectionDAG &DAG, 99 unsigned Flag) const { 100 return DAG.getTargetJumpTable(N->getIndex(), Ty, Flag); 101 } 102 103 SDValue MipsTargetLowering::getTargetNode(ConstantPoolSDNode *N, EVT Ty, 104 SelectionDAG &DAG, 105 unsigned Flag) const { 106 return DAG.getTargetConstantPool(N->getConstVal(), Ty, N->getAlignment(), 107 N->getOffset(), Flag); 108 } 109 110 const char *MipsTargetLowering::getTargetNodeName(unsigned Opcode) const { 111 switch ((MipsISD::NodeType)Opcode) { 112 case MipsISD::FIRST_NUMBER: break; 113 case MipsISD::JmpLink: return "MipsISD::JmpLink"; 114 case MipsISD::TailCall: return "MipsISD::TailCall"; 115 case MipsISD::Hi: return "MipsISD::Hi"; 116 case MipsISD::Lo: return "MipsISD::Lo"; 117 case MipsISD::GPRel: return "MipsISD::GPRel"; 118 case MipsISD::ThreadPointer: return "MipsISD::ThreadPointer"; 119 case MipsISD::Ret: return "MipsISD::Ret"; 120 case MipsISD::ERet: return "MipsISD::ERet"; 121 case MipsISD::EH_RETURN: return "MipsISD::EH_RETURN"; 122 case MipsISD::FPBrcond: return "MipsISD::FPBrcond"; 123 case MipsISD::FPCmp: return "MipsISD::FPCmp"; 124 case MipsISD::CMovFP_T: return "MipsISD::CMovFP_T"; 125 case MipsISD::CMovFP_F: return "MipsISD::CMovFP_F"; 126 case MipsISD::TruncIntFP: return "MipsISD::TruncIntFP"; 127 case MipsISD::MFHI: return "MipsISD::MFHI"; 128 case MipsISD::MFLO: return "MipsISD::MFLO"; 129 case MipsISD::MTLOHI: return "MipsISD::MTLOHI"; 130 case MipsISD::Mult: return "MipsISD::Mult"; 131 case MipsISD::Multu: return "MipsISD::Multu"; 132 case MipsISD::MAdd: return "MipsISD::MAdd"; 133 case MipsISD::MAddu: return "MipsISD::MAddu"; 134 case MipsISD::MSub: return "MipsISD::MSub"; 135 case MipsISD::MSubu: return "MipsISD::MSubu"; 136 case MipsISD::DivRem: return "MipsISD::DivRem"; 137 case MipsISD::DivRemU: return "MipsISD::DivRemU"; 138 case MipsISD::DivRem16: return "MipsISD::DivRem16"; 139 case MipsISD::DivRemU16: return "MipsISD::DivRemU16"; 140 case MipsISD::BuildPairF64: return "MipsISD::BuildPairF64"; 141 case MipsISD::ExtractElementF64: return "MipsISD::ExtractElementF64"; 142 case MipsISD::Wrapper: return "MipsISD::Wrapper"; 143 case MipsISD::DynAlloc: return "MipsISD::DynAlloc"; 144 case MipsISD::Sync: return "MipsISD::Sync"; 145 case MipsISD::Ext: return "MipsISD::Ext"; 146 case MipsISD::Ins: return "MipsISD::Ins"; 147 case MipsISD::LWL: return "MipsISD::LWL"; 148 case MipsISD::LWR: return "MipsISD::LWR"; 149 case MipsISD::SWL: return "MipsISD::SWL"; 150 case MipsISD::SWR: return "MipsISD::SWR"; 151 case MipsISD::LDL: return "MipsISD::LDL"; 152 case MipsISD::LDR: return "MipsISD::LDR"; 153 case MipsISD::SDL: return "MipsISD::SDL"; 154 case MipsISD::SDR: return "MipsISD::SDR"; 155 case MipsISD::EXTP: return "MipsISD::EXTP"; 156 case MipsISD::EXTPDP: return "MipsISD::EXTPDP"; 157 case MipsISD::EXTR_S_H: return "MipsISD::EXTR_S_H"; 158 case MipsISD::EXTR_W: return "MipsISD::EXTR_W"; 159 case MipsISD::EXTR_R_W: return "MipsISD::EXTR_R_W"; 160 case MipsISD::EXTR_RS_W: return "MipsISD::EXTR_RS_W"; 161 case MipsISD::SHILO: return "MipsISD::SHILO"; 162 case MipsISD::MTHLIP: return "MipsISD::MTHLIP"; 163 case MipsISD::MULSAQ_S_W_PH: return "MipsISD::MULSAQ_S_W_PH"; 164 case MipsISD::MAQ_S_W_PHL: return "MipsISD::MAQ_S_W_PHL"; 165 case MipsISD::MAQ_S_W_PHR: return "MipsISD::MAQ_S_W_PHR"; 166 case MipsISD::MAQ_SA_W_PHL: return "MipsISD::MAQ_SA_W_PHL"; 167 case MipsISD::MAQ_SA_W_PHR: return "MipsISD::MAQ_SA_W_PHR"; 168 case MipsISD::DPAU_H_QBL: return "MipsISD::DPAU_H_QBL"; 169 case MipsISD::DPAU_H_QBR: return "MipsISD::DPAU_H_QBR"; 170 case MipsISD::DPSU_H_QBL: return "MipsISD::DPSU_H_QBL"; 171 case MipsISD::DPSU_H_QBR: return "MipsISD::DPSU_H_QBR"; 172 case MipsISD::DPAQ_S_W_PH: return "MipsISD::DPAQ_S_W_PH"; 173 case MipsISD::DPSQ_S_W_PH: return "MipsISD::DPSQ_S_W_PH"; 174 case MipsISD::DPAQ_SA_L_W: return "MipsISD::DPAQ_SA_L_W"; 175 case MipsISD::DPSQ_SA_L_W: return "MipsISD::DPSQ_SA_L_W"; 176 case MipsISD::DPA_W_PH: return "MipsISD::DPA_W_PH"; 177 case MipsISD::DPS_W_PH: return "MipsISD::DPS_W_PH"; 178 case MipsISD::DPAQX_S_W_PH: return "MipsISD::DPAQX_S_W_PH"; 179 case MipsISD::DPAQX_SA_W_PH: return "MipsISD::DPAQX_SA_W_PH"; 180 case MipsISD::DPAX_W_PH: return "MipsISD::DPAX_W_PH"; 181 case MipsISD::DPSX_W_PH: return "MipsISD::DPSX_W_PH"; 182 case MipsISD::DPSQX_S_W_PH: return "MipsISD::DPSQX_S_W_PH"; 183 case MipsISD::DPSQX_SA_W_PH: return "MipsISD::DPSQX_SA_W_PH"; 184 case MipsISD::MULSA_W_PH: return "MipsISD::MULSA_W_PH"; 185 case MipsISD::MULT: return "MipsISD::MULT"; 186 case MipsISD::MULTU: return "MipsISD::MULTU"; 187 case MipsISD::MADD_DSP: return "MipsISD::MADD_DSP"; 188 case MipsISD::MADDU_DSP: return "MipsISD::MADDU_DSP"; 189 case MipsISD::MSUB_DSP: return "MipsISD::MSUB_DSP"; 190 case MipsISD::MSUBU_DSP: return "MipsISD::MSUBU_DSP"; 191 case MipsISD::SHLL_DSP: return "MipsISD::SHLL_DSP"; 192 case MipsISD::SHRA_DSP: return "MipsISD::SHRA_DSP"; 193 case MipsISD::SHRL_DSP: return "MipsISD::SHRL_DSP"; 194 case MipsISD::SETCC_DSP: return "MipsISD::SETCC_DSP"; 195 case MipsISD::SELECT_CC_DSP: return "MipsISD::SELECT_CC_DSP"; 196 case MipsISD::VALL_ZERO: return "MipsISD::VALL_ZERO"; 197 case MipsISD::VANY_ZERO: return "MipsISD::VANY_ZERO"; 198 case MipsISD::VALL_NONZERO: return "MipsISD::VALL_NONZERO"; 199 case MipsISD::VANY_NONZERO: return "MipsISD::VANY_NONZERO"; 200 case MipsISD::VCEQ: return "MipsISD::VCEQ"; 201 case MipsISD::VCLE_S: return "MipsISD::VCLE_S"; 202 case MipsISD::VCLE_U: return "MipsISD::VCLE_U"; 203 case MipsISD::VCLT_S: return "MipsISD::VCLT_S"; 204 case MipsISD::VCLT_U: return "MipsISD::VCLT_U"; 205 case MipsISD::VSMAX: return "MipsISD::VSMAX"; 206 case MipsISD::VSMIN: return "MipsISD::VSMIN"; 207 case MipsISD::VUMAX: return "MipsISD::VUMAX"; 208 case MipsISD::VUMIN: return "MipsISD::VUMIN"; 209 case MipsISD::VEXTRACT_SEXT_ELT: return "MipsISD::VEXTRACT_SEXT_ELT"; 210 case MipsISD::VEXTRACT_ZEXT_ELT: return "MipsISD::VEXTRACT_ZEXT_ELT"; 211 case MipsISD::VNOR: return "MipsISD::VNOR"; 212 case MipsISD::VSHF: return "MipsISD::VSHF"; 213 case MipsISD::SHF: return "MipsISD::SHF"; 214 case MipsISD::ILVEV: return "MipsISD::ILVEV"; 215 case MipsISD::ILVOD: return "MipsISD::ILVOD"; 216 case MipsISD::ILVL: return "MipsISD::ILVL"; 217 case MipsISD::ILVR: return "MipsISD::ILVR"; 218 case MipsISD::PCKEV: return "MipsISD::PCKEV"; 219 case MipsISD::PCKOD: return "MipsISD::PCKOD"; 220 case MipsISD::INSVE: return "MipsISD::INSVE"; 221 } 222 return nullptr; 223 } 224 225 MipsTargetLowering::MipsTargetLowering(const MipsTargetMachine &TM, 226 const MipsSubtarget &STI) 227 : TargetLowering(TM), Subtarget(STI), ABI(TM.getABI()) { 228 // Mips does not have i1 type, so use i32 for 229 // setcc operations results (slt, sgt, ...). 230 setBooleanContents(ZeroOrOneBooleanContent); 231 setBooleanVectorContents(ZeroOrNegativeOneBooleanContent); 232 // The cmp.cond.fmt instruction in MIPS32r6/MIPS64r6 uses 0 and -1 like MSA 233 // does. Integer booleans still use 0 and 1. 234 if (Subtarget.hasMips32r6()) 235 setBooleanContents(ZeroOrOneBooleanContent, 236 ZeroOrNegativeOneBooleanContent); 237 238 // Load extented operations for i1 types must be promoted 239 for (MVT VT : MVT::integer_valuetypes()) { 240 setLoadExtAction(ISD::EXTLOAD, VT, MVT::i1, Promote); 241 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i1, Promote); 242 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i1, Promote); 243 } 244 245 // MIPS doesn't have extending float->double load/store. Set LoadExtAction 246 // for f32, f16 247 for (MVT VT : MVT::fp_valuetypes()) { 248 setLoadExtAction(ISD::EXTLOAD, VT, MVT::f32, Expand); 249 setLoadExtAction(ISD::EXTLOAD, VT, MVT::f16, Expand); 250 } 251 252 // Set LoadExtAction for f16 vectors to Expand 253 for (MVT VT : MVT::fp_vector_valuetypes()) { 254 MVT F16VT = MVT::getVectorVT(MVT::f16, VT.getVectorNumElements()); 255 if (F16VT.isValid()) 256 setLoadExtAction(ISD::EXTLOAD, VT, F16VT, Expand); 257 } 258 259 setTruncStoreAction(MVT::f32, MVT::f16, Expand); 260 setTruncStoreAction(MVT::f64, MVT::f16, Expand); 261 262 setTruncStoreAction(MVT::f64, MVT::f32, Expand); 263 264 // Used by legalize types to correctly generate the setcc result. 265 // Without this, every float setcc comes with a AND/OR with the result, 266 // we don't want this, since the fpcmp result goes to a flag register, 267 // which is used implicitly by brcond and select operations. 268 AddPromotedToType(ISD::SETCC, MVT::i1, MVT::i32); 269 270 // Mips Custom Operations 271 setOperationAction(ISD::BR_JT, MVT::Other, Custom); 272 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom); 273 setOperationAction(ISD::BlockAddress, MVT::i32, Custom); 274 setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom); 275 setOperationAction(ISD::JumpTable, MVT::i32, Custom); 276 setOperationAction(ISD::ConstantPool, MVT::i32, Custom); 277 setOperationAction(ISD::SELECT, MVT::f32, Custom); 278 setOperationAction(ISD::SELECT, MVT::f64, Custom); 279 setOperationAction(ISD::SELECT, MVT::i32, Custom); 280 setOperationAction(ISD::SETCC, MVT::f32, Custom); 281 setOperationAction(ISD::SETCC, MVT::f64, Custom); 282 setOperationAction(ISD::BRCOND, MVT::Other, Custom); 283 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom); 284 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom); 285 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom); 286 287 if (Subtarget.isGP64bit()) { 288 setOperationAction(ISD::GlobalAddress, MVT::i64, Custom); 289 setOperationAction(ISD::BlockAddress, MVT::i64, Custom); 290 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom); 291 setOperationAction(ISD::JumpTable, MVT::i64, Custom); 292 setOperationAction(ISD::ConstantPool, MVT::i64, Custom); 293 setOperationAction(ISD::SELECT, MVT::i64, Custom); 294 setOperationAction(ISD::LOAD, MVT::i64, Custom); 295 setOperationAction(ISD::STORE, MVT::i64, Custom); 296 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom); 297 setOperationAction(ISD::SHL_PARTS, MVT::i64, Custom); 298 setOperationAction(ISD::SRA_PARTS, MVT::i64, Custom); 299 setOperationAction(ISD::SRL_PARTS, MVT::i64, Custom); 300 } 301 302 if (!Subtarget.isGP64bit()) { 303 setOperationAction(ISD::SHL_PARTS, MVT::i32, Custom); 304 setOperationAction(ISD::SRA_PARTS, MVT::i32, Custom); 305 setOperationAction(ISD::SRL_PARTS, MVT::i32, Custom); 306 } 307 308 setOperationAction(ISD::ADD, MVT::i32, Custom); 309 if (Subtarget.isGP64bit()) 310 setOperationAction(ISD::ADD, MVT::i64, Custom); 311 312 setOperationAction(ISD::SDIV, MVT::i32, Expand); 313 setOperationAction(ISD::SREM, MVT::i32, Expand); 314 setOperationAction(ISD::UDIV, MVT::i32, Expand); 315 setOperationAction(ISD::UREM, MVT::i32, Expand); 316 setOperationAction(ISD::SDIV, MVT::i64, Expand); 317 setOperationAction(ISD::SREM, MVT::i64, Expand); 318 setOperationAction(ISD::UDIV, MVT::i64, Expand); 319 setOperationAction(ISD::UREM, MVT::i64, Expand); 320 321 // Operations not directly supported by Mips. 322 setOperationAction(ISD::BR_CC, MVT::f32, Expand); 323 setOperationAction(ISD::BR_CC, MVT::f64, Expand); 324 setOperationAction(ISD::BR_CC, MVT::i32, Expand); 325 setOperationAction(ISD::BR_CC, MVT::i64, Expand); 326 setOperationAction(ISD::SELECT_CC, MVT::i32, Expand); 327 setOperationAction(ISD::SELECT_CC, MVT::i64, Expand); 328 setOperationAction(ISD::SELECT_CC, MVT::f32, Expand); 329 setOperationAction(ISD::SELECT_CC, MVT::f64, Expand); 330 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand); 331 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Expand); 332 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand); 333 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Expand); 334 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand); 335 if (Subtarget.hasCnMips()) { 336 setOperationAction(ISD::CTPOP, MVT::i32, Legal); 337 setOperationAction(ISD::CTPOP, MVT::i64, Legal); 338 } else { 339 setOperationAction(ISD::CTPOP, MVT::i32, Expand); 340 setOperationAction(ISD::CTPOP, MVT::i64, Expand); 341 } 342 setOperationAction(ISD::CTTZ, MVT::i32, Expand); 343 setOperationAction(ISD::CTTZ, MVT::i64, Expand); 344 setOperationAction(ISD::ROTL, MVT::i32, Expand); 345 setOperationAction(ISD::ROTL, MVT::i64, Expand); 346 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Expand); 347 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64, Expand); 348 349 if (!Subtarget.hasMips32r2()) 350 setOperationAction(ISD::ROTR, MVT::i32, Expand); 351 352 if (!Subtarget.hasMips64r2()) 353 setOperationAction(ISD::ROTR, MVT::i64, Expand); 354 355 setOperationAction(ISD::FSIN, MVT::f32, Expand); 356 setOperationAction(ISD::FSIN, MVT::f64, Expand); 357 setOperationAction(ISD::FCOS, MVT::f32, Expand); 358 setOperationAction(ISD::FCOS, MVT::f64, Expand); 359 setOperationAction(ISD::FSINCOS, MVT::f32, Expand); 360 setOperationAction(ISD::FSINCOS, MVT::f64, Expand); 361 setOperationAction(ISD::FPOWI, MVT::f32, Expand); 362 setOperationAction(ISD::FPOW, MVT::f32, Expand); 363 setOperationAction(ISD::FPOW, MVT::f64, Expand); 364 setOperationAction(ISD::FLOG, MVT::f32, Expand); 365 setOperationAction(ISD::FLOG2, MVT::f32, Expand); 366 setOperationAction(ISD::FLOG10, MVT::f32, Expand); 367 setOperationAction(ISD::FEXP, MVT::f32, Expand); 368 setOperationAction(ISD::FMA, MVT::f32, Expand); 369 setOperationAction(ISD::FMA, MVT::f64, Expand); 370 setOperationAction(ISD::FREM, MVT::f32, Expand); 371 setOperationAction(ISD::FREM, MVT::f64, Expand); 372 373 // Lower f16 conversion operations into library calls 374 setOperationAction(ISD::FP16_TO_FP, MVT::f32, Expand); 375 setOperationAction(ISD::FP_TO_FP16, MVT::f32, Expand); 376 setOperationAction(ISD::FP16_TO_FP, MVT::f64, Expand); 377 setOperationAction(ISD::FP_TO_FP16, MVT::f64, Expand); 378 379 setOperationAction(ISD::EH_RETURN, MVT::Other, Custom); 380 381 setOperationAction(ISD::VASTART, MVT::Other, Custom); 382 setOperationAction(ISD::VAARG, MVT::Other, Custom); 383 setOperationAction(ISD::VACOPY, MVT::Other, Expand); 384 setOperationAction(ISD::VAEND, MVT::Other, Expand); 385 386 // Use the default for now 387 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand); 388 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand); 389 390 if (!Subtarget.isGP64bit()) { 391 setOperationAction(ISD::ATOMIC_LOAD, MVT::i64, Expand); 392 setOperationAction(ISD::ATOMIC_STORE, MVT::i64, Expand); 393 } 394 395 396 if (!Subtarget.hasMips32r2()) { 397 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8, Expand); 398 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand); 399 } 400 401 // MIPS16 lacks MIPS32's clz and clo instructions. 402 if (!Subtarget.hasMips32() || Subtarget.inMips16Mode()) 403 setOperationAction(ISD::CTLZ, MVT::i32, Expand); 404 if (!Subtarget.hasMips64()) 405 setOperationAction(ISD::CTLZ, MVT::i64, Expand); 406 407 if (!Subtarget.hasMips32r2()) 408 setOperationAction(ISD::BSWAP, MVT::i32, Expand); 409 if (!Subtarget.hasMips64r2()) 410 setOperationAction(ISD::BSWAP, MVT::i64, Expand); 411 412 if (Subtarget.isGP64bit()) { 413 setLoadExtAction(ISD::SEXTLOAD, MVT::i64, MVT::i32, Custom); 414 setLoadExtAction(ISD::ZEXTLOAD, MVT::i64, MVT::i32, Custom); 415 setLoadExtAction(ISD::EXTLOAD, MVT::i64, MVT::i32, Custom); 416 setTruncStoreAction(MVT::i64, MVT::i32, Custom); 417 } 418 419 setOperationAction(ISD::TRAP, MVT::Other, Legal); 420 421 setTargetDAGCombine(ISD::SDIVREM); 422 setTargetDAGCombine(ISD::UDIVREM); 423 setTargetDAGCombine(ISD::SELECT); 424 setTargetDAGCombine(ISD::AND); 425 setTargetDAGCombine(ISD::OR); 426 setTargetDAGCombine(ISD::ADD); 427 setTargetDAGCombine(ISD::AssertZext); 428 429 setMinFunctionAlignment(Subtarget.isGP64bit() ? 3 : 2); 430 431 // The arguments on the stack are defined in terms of 4-byte slots on O32 432 // and 8-byte slots on N32/N64. 433 setMinStackArgumentAlignment((ABI.IsN32() || ABI.IsN64()) ? 8 : 4); 434 435 setStackPointerRegisterToSaveRestore(ABI.IsN64() ? Mips::SP_64 : Mips::SP); 436 437 MaxStoresPerMemcpy = 16; 438 439 isMicroMips = Subtarget.inMicroMipsMode(); 440 } 441 442 const MipsTargetLowering *MipsTargetLowering::create(const MipsTargetMachine &TM, 443 const MipsSubtarget &STI) { 444 if (STI.inMips16Mode()) 445 return llvm::createMips16TargetLowering(TM, STI); 446 447 return llvm::createMipsSETargetLowering(TM, STI); 448 } 449 450 // Create a fast isel object. 451 FastISel * 452 MipsTargetLowering::createFastISel(FunctionLoweringInfo &funcInfo, 453 const TargetLibraryInfo *libInfo) const { 454 if (!funcInfo.MF->getTarget().Options.EnableFastISel) 455 return TargetLowering::createFastISel(funcInfo, libInfo); 456 return Mips::createFastISel(funcInfo, libInfo); 457 } 458 459 EVT MipsTargetLowering::getSetCCResultType(const DataLayout &, LLVMContext &, 460 EVT VT) const { 461 if (!VT.isVector()) 462 return MVT::i32; 463 return VT.changeVectorElementTypeToInteger(); 464 } 465 466 static SDValue performDivRemCombine(SDNode *N, SelectionDAG &DAG, 467 TargetLowering::DAGCombinerInfo &DCI, 468 const MipsSubtarget &Subtarget) { 469 if (DCI.isBeforeLegalizeOps()) 470 return SDValue(); 471 472 EVT Ty = N->getValueType(0); 473 unsigned LO = (Ty == MVT::i32) ? Mips::LO0 : Mips::LO0_64; 474 unsigned HI = (Ty == MVT::i32) ? Mips::HI0 : Mips::HI0_64; 475 unsigned Opc = N->getOpcode() == ISD::SDIVREM ? MipsISD::DivRem16 : 476 MipsISD::DivRemU16; 477 SDLoc DL(N); 478 479 SDValue DivRem = DAG.getNode(Opc, DL, MVT::Glue, 480 N->getOperand(0), N->getOperand(1)); 481 SDValue InChain = DAG.getEntryNode(); 482 SDValue InGlue = DivRem; 483 484 // insert MFLO 485 if (N->hasAnyUseOfValue(0)) { 486 SDValue CopyFromLo = DAG.getCopyFromReg(InChain, DL, LO, Ty, 487 InGlue); 488 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), CopyFromLo); 489 InChain = CopyFromLo.getValue(1); 490 InGlue = CopyFromLo.getValue(2); 491 } 492 493 // insert MFHI 494 if (N->hasAnyUseOfValue(1)) { 495 SDValue CopyFromHi = DAG.getCopyFromReg(InChain, DL, 496 HI, Ty, InGlue); 497 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), CopyFromHi); 498 } 499 500 return SDValue(); 501 } 502 503 static Mips::CondCode condCodeToFCC(ISD::CondCode CC) { 504 switch (CC) { 505 default: llvm_unreachable("Unknown fp condition code!"); 506 case ISD::SETEQ: 507 case ISD::SETOEQ: return Mips::FCOND_OEQ; 508 case ISD::SETUNE: return Mips::FCOND_UNE; 509 case ISD::SETLT: 510 case ISD::SETOLT: return Mips::FCOND_OLT; 511 case ISD::SETGT: 512 case ISD::SETOGT: return Mips::FCOND_OGT; 513 case ISD::SETLE: 514 case ISD::SETOLE: return Mips::FCOND_OLE; 515 case ISD::SETGE: 516 case ISD::SETOGE: return Mips::FCOND_OGE; 517 case ISD::SETULT: return Mips::FCOND_ULT; 518 case ISD::SETULE: return Mips::FCOND_ULE; 519 case ISD::SETUGT: return Mips::FCOND_UGT; 520 case ISD::SETUGE: return Mips::FCOND_UGE; 521 case ISD::SETUO: return Mips::FCOND_UN; 522 case ISD::SETO: return Mips::FCOND_OR; 523 case ISD::SETNE: 524 case ISD::SETONE: return Mips::FCOND_ONE; 525 case ISD::SETUEQ: return Mips::FCOND_UEQ; 526 } 527 } 528 529 530 /// This function returns true if the floating point conditional branches and 531 /// conditional moves which use condition code CC should be inverted. 532 static bool invertFPCondCodeUser(Mips::CondCode CC) { 533 if (CC >= Mips::FCOND_F && CC <= Mips::FCOND_NGT) 534 return false; 535 536 assert((CC >= Mips::FCOND_T && CC <= Mips::FCOND_GT) && 537 "Illegal Condition Code"); 538 539 return true; 540 } 541 542 // Creates and returns an FPCmp node from a setcc node. 543 // Returns Op if setcc is not a floating point comparison. 544 static SDValue createFPCmp(SelectionDAG &DAG, const SDValue &Op) { 545 // must be a SETCC node 546 if (Op.getOpcode() != ISD::SETCC) 547 return Op; 548 549 SDValue LHS = Op.getOperand(0); 550 551 if (!LHS.getValueType().isFloatingPoint()) 552 return Op; 553 554 SDValue RHS = Op.getOperand(1); 555 SDLoc DL(Op); 556 557 // Assume the 3rd operand is a CondCodeSDNode. Add code to check the type of 558 // node if necessary. 559 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get(); 560 561 return DAG.getNode(MipsISD::FPCmp, DL, MVT::Glue, LHS, RHS, 562 DAG.getConstant(condCodeToFCC(CC), DL, MVT::i32)); 563 } 564 565 // Creates and returns a CMovFPT/F node. 566 static SDValue createCMovFP(SelectionDAG &DAG, SDValue Cond, SDValue True, 567 SDValue False, SDLoc DL) { 568 ConstantSDNode *CC = cast<ConstantSDNode>(Cond.getOperand(2)); 569 bool invert = invertFPCondCodeUser((Mips::CondCode)CC->getSExtValue()); 570 SDValue FCC0 = DAG.getRegister(Mips::FCC0, MVT::i32); 571 572 return DAG.getNode((invert ? MipsISD::CMovFP_F : MipsISD::CMovFP_T), DL, 573 True.getValueType(), True, FCC0, False, Cond); 574 } 575 576 static SDValue performSELECTCombine(SDNode *N, SelectionDAG &DAG, 577 TargetLowering::DAGCombinerInfo &DCI, 578 const MipsSubtarget &Subtarget) { 579 if (DCI.isBeforeLegalizeOps()) 580 return SDValue(); 581 582 SDValue SetCC = N->getOperand(0); 583 584 if ((SetCC.getOpcode() != ISD::SETCC) || 585 !SetCC.getOperand(0).getValueType().isInteger()) 586 return SDValue(); 587 588 SDValue False = N->getOperand(2); 589 EVT FalseTy = False.getValueType(); 590 591 if (!FalseTy.isInteger()) 592 return SDValue(); 593 594 ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(False); 595 596 // If the RHS (False) is 0, we swap the order of the operands 597 // of ISD::SELECT (obviously also inverting the condition) so that we can 598 // take advantage of conditional moves using the $0 register. 599 // Example: 600 // return (a != 0) ? x : 0; 601 // load $reg, x 602 // movz $reg, $0, a 603 if (!FalseC) 604 return SDValue(); 605 606 const SDLoc DL(N); 607 608 if (!FalseC->getZExtValue()) { 609 ISD::CondCode CC = cast<CondCodeSDNode>(SetCC.getOperand(2))->get(); 610 SDValue True = N->getOperand(1); 611 612 SetCC = DAG.getSetCC(DL, SetCC.getValueType(), SetCC.getOperand(0), 613 SetCC.getOperand(1), ISD::getSetCCInverse(CC, true)); 614 615 return DAG.getNode(ISD::SELECT, DL, FalseTy, SetCC, False, True); 616 } 617 618 // If both operands are integer constants there's a possibility that we 619 // can do some interesting optimizations. 620 SDValue True = N->getOperand(1); 621 ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(True); 622 623 if (!TrueC || !True.getValueType().isInteger()) 624 return SDValue(); 625 626 // We'll also ignore MVT::i64 operands as this optimizations proves 627 // to be ineffective because of the required sign extensions as the result 628 // of a SETCC operator is always MVT::i32 for non-vector types. 629 if (True.getValueType() == MVT::i64) 630 return SDValue(); 631 632 int64_t Diff = TrueC->getSExtValue() - FalseC->getSExtValue(); 633 634 // 1) (a < x) ? y : y-1 635 // slti $reg1, a, x 636 // addiu $reg2, $reg1, y-1 637 if (Diff == 1) 638 return DAG.getNode(ISD::ADD, DL, SetCC.getValueType(), SetCC, False); 639 640 // 2) (a < x) ? y-1 : y 641 // slti $reg1, a, x 642 // xor $reg1, $reg1, 1 643 // addiu $reg2, $reg1, y-1 644 if (Diff == -1) { 645 ISD::CondCode CC = cast<CondCodeSDNode>(SetCC.getOperand(2))->get(); 646 SetCC = DAG.getSetCC(DL, SetCC.getValueType(), SetCC.getOperand(0), 647 SetCC.getOperand(1), ISD::getSetCCInverse(CC, true)); 648 return DAG.getNode(ISD::ADD, DL, SetCC.getValueType(), SetCC, True); 649 } 650 651 // Couldn't optimize. 652 return SDValue(); 653 } 654 655 static SDValue performCMovFPCombine(SDNode *N, SelectionDAG &DAG, 656 TargetLowering::DAGCombinerInfo &DCI, 657 const MipsSubtarget &Subtarget) { 658 if (DCI.isBeforeLegalizeOps()) 659 return SDValue(); 660 661 SDValue ValueIfTrue = N->getOperand(0), ValueIfFalse = N->getOperand(2); 662 663 ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(ValueIfFalse); 664 if (!FalseC || FalseC->getZExtValue()) 665 return SDValue(); 666 667 // Since RHS (False) is 0, we swap the order of the True/False operands 668 // (obviously also inverting the condition) so that we can 669 // take advantage of conditional moves using the $0 register. 670 // Example: 671 // return (a != 0) ? x : 0; 672 // load $reg, x 673 // movz $reg, $0, a 674 unsigned Opc = (N->getOpcode() == MipsISD::CMovFP_T) ? MipsISD::CMovFP_F : 675 MipsISD::CMovFP_T; 676 677 SDValue FCC = N->getOperand(1), Glue = N->getOperand(3); 678 return DAG.getNode(Opc, SDLoc(N), ValueIfFalse.getValueType(), 679 ValueIfFalse, FCC, ValueIfTrue, Glue); 680 } 681 682 static SDValue performANDCombine(SDNode *N, SelectionDAG &DAG, 683 TargetLowering::DAGCombinerInfo &DCI, 684 const MipsSubtarget &Subtarget) { 685 // Pattern match EXT. 686 // $dst = and ((sra or srl) $src , pos), (2**size - 1) 687 // => ext $dst, $src, size, pos 688 if (DCI.isBeforeLegalizeOps() || !Subtarget.hasExtractInsert()) 689 return SDValue(); 690 691 SDValue ShiftRight = N->getOperand(0), Mask = N->getOperand(1); 692 unsigned ShiftRightOpc = ShiftRight.getOpcode(); 693 694 // Op's first operand must be a shift right. 695 if (ShiftRightOpc != ISD::SRA && ShiftRightOpc != ISD::SRL) 696 return SDValue(); 697 698 // The second operand of the shift must be an immediate. 699 ConstantSDNode *CN; 700 if (!(CN = dyn_cast<ConstantSDNode>(ShiftRight.getOperand(1)))) 701 return SDValue(); 702 703 uint64_t Pos = CN->getZExtValue(); 704 uint64_t SMPos, SMSize; 705 706 // Op's second operand must be a shifted mask. 707 if (!(CN = dyn_cast<ConstantSDNode>(Mask)) || 708 !isShiftedMask(CN->getZExtValue(), SMPos, SMSize)) 709 return SDValue(); 710 711 // Return if the shifted mask does not start at bit 0 or the sum of its size 712 // and Pos exceeds the word's size. 713 EVT ValTy = N->getValueType(0); 714 if (SMPos != 0 || Pos + SMSize > ValTy.getSizeInBits()) 715 return SDValue(); 716 717 SDLoc DL(N); 718 return DAG.getNode(MipsISD::Ext, DL, ValTy, 719 ShiftRight.getOperand(0), 720 DAG.getConstant(Pos, DL, MVT::i32), 721 DAG.getConstant(SMSize, DL, MVT::i32)); 722 } 723 724 static SDValue performORCombine(SDNode *N, SelectionDAG &DAG, 725 TargetLowering::DAGCombinerInfo &DCI, 726 const MipsSubtarget &Subtarget) { 727 // Pattern match INS. 728 // $dst = or (and $src1 , mask0), (and (shl $src, pos), mask1), 729 // where mask1 = (2**size - 1) << pos, mask0 = ~mask1 730 // => ins $dst, $src, size, pos, $src1 731 if (DCI.isBeforeLegalizeOps() || !Subtarget.hasExtractInsert()) 732 return SDValue(); 733 734 SDValue And0 = N->getOperand(0), And1 = N->getOperand(1); 735 uint64_t SMPos0, SMSize0, SMPos1, SMSize1; 736 ConstantSDNode *CN; 737 738 // See if Op's first operand matches (and $src1 , mask0). 739 if (And0.getOpcode() != ISD::AND) 740 return SDValue(); 741 742 if (!(CN = dyn_cast<ConstantSDNode>(And0.getOperand(1))) || 743 !isShiftedMask(~CN->getSExtValue(), SMPos0, SMSize0)) 744 return SDValue(); 745 746 // See if Op's second operand matches (and (shl $src, pos), mask1). 747 if (And1.getOpcode() != ISD::AND) 748 return SDValue(); 749 750 if (!(CN = dyn_cast<ConstantSDNode>(And1.getOperand(1))) || 751 !isShiftedMask(CN->getZExtValue(), SMPos1, SMSize1)) 752 return SDValue(); 753 754 // The shift masks must have the same position and size. 755 if (SMPos0 != SMPos1 || SMSize0 != SMSize1) 756 return SDValue(); 757 758 SDValue Shl = And1.getOperand(0); 759 if (Shl.getOpcode() != ISD::SHL) 760 return SDValue(); 761 762 if (!(CN = dyn_cast<ConstantSDNode>(Shl.getOperand(1)))) 763 return SDValue(); 764 765 unsigned Shamt = CN->getZExtValue(); 766 767 // Return if the shift amount and the first bit position of mask are not the 768 // same. 769 EVT ValTy = N->getValueType(0); 770 if ((Shamt != SMPos0) || (SMPos0 + SMSize0 > ValTy.getSizeInBits())) 771 return SDValue(); 772 773 SDLoc DL(N); 774 return DAG.getNode(MipsISD::Ins, DL, ValTy, Shl.getOperand(0), 775 DAG.getConstant(SMPos0, DL, MVT::i32), 776 DAG.getConstant(SMSize0, DL, MVT::i32), 777 And0.getOperand(0)); 778 } 779 780 static SDValue performADDCombine(SDNode *N, SelectionDAG &DAG, 781 TargetLowering::DAGCombinerInfo &DCI, 782 const MipsSubtarget &Subtarget) { 783 // (add v0, (add v1, abs_lo(tjt))) => (add (add v0, v1), abs_lo(tjt)) 784 785 if (DCI.isBeforeLegalizeOps()) 786 return SDValue(); 787 788 SDValue Add = N->getOperand(1); 789 790 if (Add.getOpcode() != ISD::ADD) 791 return SDValue(); 792 793 SDValue Lo = Add.getOperand(1); 794 795 if ((Lo.getOpcode() != MipsISD::Lo) || 796 (Lo.getOperand(0).getOpcode() != ISD::TargetJumpTable)) 797 return SDValue(); 798 799 EVT ValTy = N->getValueType(0); 800 SDLoc DL(N); 801 802 SDValue Add1 = DAG.getNode(ISD::ADD, DL, ValTy, N->getOperand(0), 803 Add.getOperand(0)); 804 return DAG.getNode(ISD::ADD, DL, ValTy, Add1, Lo); 805 } 806 807 static SDValue performAssertZextCombine(SDNode *N, SelectionDAG &DAG, 808 TargetLowering::DAGCombinerInfo &DCI, 809 const MipsSubtarget &Subtarget) { 810 SDValue N0 = N->getOperand(0); 811 EVT NarrowerVT = cast<VTSDNode>(N->getOperand(1))->getVT(); 812 813 if (N0.getOpcode() != ISD::TRUNCATE) 814 return SDValue(); 815 816 if (N0.getOperand(0).getOpcode() != ISD::AssertZext) 817 return SDValue(); 818 819 // fold (AssertZext (trunc (AssertZext x))) -> (trunc (AssertZext x)) 820 // if the type of the extension of the innermost AssertZext node is 821 // smaller from that of the outermost node, eg: 822 // (AssertZext:i32 (trunc:i32 (AssertZext:i64 X, i32)), i8) 823 // -> (trunc:i32 (AssertZext X, i8)) 824 SDValue WiderAssertZext = N0.getOperand(0); 825 EVT WiderVT = cast<VTSDNode>(WiderAssertZext->getOperand(1))->getVT(); 826 827 if (NarrowerVT.bitsLT(WiderVT)) { 828 SDValue NewAssertZext = DAG.getNode( 829 ISD::AssertZext, SDLoc(N), WiderAssertZext.getValueType(), 830 WiderAssertZext.getOperand(0), DAG.getValueType(NarrowerVT)); 831 return DAG.getNode(ISD::TRUNCATE, SDLoc(N), N->getValueType(0), 832 NewAssertZext); 833 } 834 835 return SDValue(); 836 } 837 838 SDValue MipsTargetLowering::PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) 839 const { 840 SelectionDAG &DAG = DCI.DAG; 841 unsigned Opc = N->getOpcode(); 842 843 switch (Opc) { 844 default: break; 845 case ISD::SDIVREM: 846 case ISD::UDIVREM: 847 return performDivRemCombine(N, DAG, DCI, Subtarget); 848 case ISD::SELECT: 849 return performSELECTCombine(N, DAG, DCI, Subtarget); 850 case MipsISD::CMovFP_F: 851 case MipsISD::CMovFP_T: 852 return performCMovFPCombine(N, DAG, DCI, Subtarget); 853 case ISD::AND: 854 return performANDCombine(N, DAG, DCI, Subtarget); 855 case ISD::OR: 856 return performORCombine(N, DAG, DCI, Subtarget); 857 case ISD::ADD: 858 return performADDCombine(N, DAG, DCI, Subtarget); 859 case ISD::AssertZext: 860 return performAssertZextCombine(N, DAG, DCI, Subtarget); 861 } 862 863 return SDValue(); 864 } 865 866 bool MipsTargetLowering::isCheapToSpeculateCttz() const { 867 return Subtarget.hasMips32(); 868 } 869 870 bool MipsTargetLowering::isCheapToSpeculateCtlz() const { 871 return Subtarget.hasMips32(); 872 } 873 874 void 875 MipsTargetLowering::LowerOperationWrapper(SDNode *N, 876 SmallVectorImpl<SDValue> &Results, 877 SelectionDAG &DAG) const { 878 SDValue Res = LowerOperation(SDValue(N, 0), DAG); 879 880 for (unsigned I = 0, E = Res->getNumValues(); I != E; ++I) 881 Results.push_back(Res.getValue(I)); 882 } 883 884 void 885 MipsTargetLowering::ReplaceNodeResults(SDNode *N, 886 SmallVectorImpl<SDValue> &Results, 887 SelectionDAG &DAG) const { 888 return LowerOperationWrapper(N, Results, DAG); 889 } 890 891 SDValue MipsTargetLowering:: 892 LowerOperation(SDValue Op, SelectionDAG &DAG) const 893 { 894 switch (Op.getOpcode()) 895 { 896 case ISD::BR_JT: return lowerBR_JT(Op, DAG); 897 case ISD::BRCOND: return lowerBRCOND(Op, DAG); 898 case ISD::ConstantPool: return lowerConstantPool(Op, DAG); 899 case ISD::GlobalAddress: return lowerGlobalAddress(Op, DAG); 900 case ISD::BlockAddress: return lowerBlockAddress(Op, DAG); 901 case ISD::GlobalTLSAddress: return lowerGlobalTLSAddress(Op, DAG); 902 case ISD::JumpTable: return lowerJumpTable(Op, DAG); 903 case ISD::SELECT: return lowerSELECT(Op, DAG); 904 case ISD::SETCC: return lowerSETCC(Op, DAG); 905 case ISD::VASTART: return lowerVASTART(Op, DAG); 906 case ISD::VAARG: return lowerVAARG(Op, DAG); 907 case ISD::FCOPYSIGN: return lowerFCOPYSIGN(Op, DAG); 908 case ISD::FRAMEADDR: return lowerFRAMEADDR(Op, DAG); 909 case ISD::RETURNADDR: return lowerRETURNADDR(Op, DAG); 910 case ISD::EH_RETURN: return lowerEH_RETURN(Op, DAG); 911 case ISD::ATOMIC_FENCE: return lowerATOMIC_FENCE(Op, DAG); 912 case ISD::SHL_PARTS: return lowerShiftLeftParts(Op, DAG); 913 case ISD::SRA_PARTS: return lowerShiftRightParts(Op, DAG, true); 914 case ISD::SRL_PARTS: return lowerShiftRightParts(Op, DAG, false); 915 case ISD::LOAD: return lowerLOAD(Op, DAG); 916 case ISD::STORE: return lowerSTORE(Op, DAG); 917 case ISD::ADD: return lowerADD(Op, DAG); 918 case ISD::FP_TO_SINT: return lowerFP_TO_SINT(Op, DAG); 919 } 920 return SDValue(); 921 } 922 923 //===----------------------------------------------------------------------===// 924 // Lower helper functions 925 //===----------------------------------------------------------------------===// 926 927 // addLiveIn - This helper function adds the specified physical register to the 928 // MachineFunction as a live in value. It also creates a corresponding 929 // virtual register for it. 930 static unsigned 931 addLiveIn(MachineFunction &MF, unsigned PReg, const TargetRegisterClass *RC) 932 { 933 unsigned VReg = MF.getRegInfo().createVirtualRegister(RC); 934 MF.getRegInfo().addLiveIn(PReg, VReg); 935 return VReg; 936 } 937 938 static MachineBasicBlock *insertDivByZeroTrap(MachineInstr *MI, 939 MachineBasicBlock &MBB, 940 const TargetInstrInfo &TII, 941 bool Is64Bit, bool IsMicroMips) { 942 if (NoZeroDivCheck) 943 return &MBB; 944 945 // Insert instruction "teq $divisor_reg, $zero, 7". 946 MachineBasicBlock::iterator I(MI); 947 MachineInstrBuilder MIB; 948 MachineOperand &Divisor = MI->getOperand(2); 949 MIB = BuildMI(MBB, std::next(I), MI->getDebugLoc(), 950 TII.get(IsMicroMips ? Mips::TEQ_MM : Mips::TEQ)) 951 .addReg(Divisor.getReg(), getKillRegState(Divisor.isKill())) 952 .addReg(Mips::ZERO).addImm(7); 953 954 // Use the 32-bit sub-register if this is a 64-bit division. 955 if (Is64Bit) 956 MIB->getOperand(0).setSubReg(Mips::sub_32); 957 958 // Clear Divisor's kill flag. 959 Divisor.setIsKill(false); 960 961 // We would normally delete the original instruction here but in this case 962 // we only needed to inject an additional instruction rather than replace it. 963 964 return &MBB; 965 } 966 967 MachineBasicBlock * 968 MipsTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI, 969 MachineBasicBlock *BB) const { 970 switch (MI->getOpcode()) { 971 default: 972 llvm_unreachable("Unexpected instr type to insert"); 973 case Mips::ATOMIC_LOAD_ADD_I8: 974 return emitAtomicBinaryPartword(MI, BB, 1, Mips::ADDu); 975 case Mips::ATOMIC_LOAD_ADD_I16: 976 return emitAtomicBinaryPartword(MI, BB, 2, Mips::ADDu); 977 case Mips::ATOMIC_LOAD_ADD_I32: 978 return emitAtomicBinary(MI, BB, 4, Mips::ADDu); 979 case Mips::ATOMIC_LOAD_ADD_I64: 980 return emitAtomicBinary(MI, BB, 8, Mips::DADDu); 981 982 case Mips::ATOMIC_LOAD_AND_I8: 983 return emitAtomicBinaryPartword(MI, BB, 1, Mips::AND); 984 case Mips::ATOMIC_LOAD_AND_I16: 985 return emitAtomicBinaryPartword(MI, BB, 2, Mips::AND); 986 case Mips::ATOMIC_LOAD_AND_I32: 987 return emitAtomicBinary(MI, BB, 4, Mips::AND); 988 case Mips::ATOMIC_LOAD_AND_I64: 989 return emitAtomicBinary(MI, BB, 8, Mips::AND64); 990 991 case Mips::ATOMIC_LOAD_OR_I8: 992 return emitAtomicBinaryPartword(MI, BB, 1, Mips::OR); 993 case Mips::ATOMIC_LOAD_OR_I16: 994 return emitAtomicBinaryPartword(MI, BB, 2, Mips::OR); 995 case Mips::ATOMIC_LOAD_OR_I32: 996 return emitAtomicBinary(MI, BB, 4, Mips::OR); 997 case Mips::ATOMIC_LOAD_OR_I64: 998 return emitAtomicBinary(MI, BB, 8, Mips::OR64); 999 1000 case Mips::ATOMIC_LOAD_XOR_I8: 1001 return emitAtomicBinaryPartword(MI, BB, 1, Mips::XOR); 1002 case Mips::ATOMIC_LOAD_XOR_I16: 1003 return emitAtomicBinaryPartword(MI, BB, 2, Mips::XOR); 1004 case Mips::ATOMIC_LOAD_XOR_I32: 1005 return emitAtomicBinary(MI, BB, 4, Mips::XOR); 1006 case Mips::ATOMIC_LOAD_XOR_I64: 1007 return emitAtomicBinary(MI, BB, 8, Mips::XOR64); 1008 1009 case Mips::ATOMIC_LOAD_NAND_I8: 1010 return emitAtomicBinaryPartword(MI, BB, 1, 0, true); 1011 case Mips::ATOMIC_LOAD_NAND_I16: 1012 return emitAtomicBinaryPartword(MI, BB, 2, 0, true); 1013 case Mips::ATOMIC_LOAD_NAND_I32: 1014 return emitAtomicBinary(MI, BB, 4, 0, true); 1015 case Mips::ATOMIC_LOAD_NAND_I64: 1016 return emitAtomicBinary(MI, BB, 8, 0, true); 1017 1018 case Mips::ATOMIC_LOAD_SUB_I8: 1019 return emitAtomicBinaryPartword(MI, BB, 1, Mips::SUBu); 1020 case Mips::ATOMIC_LOAD_SUB_I16: 1021 return emitAtomicBinaryPartword(MI, BB, 2, Mips::SUBu); 1022 case Mips::ATOMIC_LOAD_SUB_I32: 1023 return emitAtomicBinary(MI, BB, 4, Mips::SUBu); 1024 case Mips::ATOMIC_LOAD_SUB_I64: 1025 return emitAtomicBinary(MI, BB, 8, Mips::DSUBu); 1026 1027 case Mips::ATOMIC_SWAP_I8: 1028 return emitAtomicBinaryPartword(MI, BB, 1, 0); 1029 case Mips::ATOMIC_SWAP_I16: 1030 return emitAtomicBinaryPartword(MI, BB, 2, 0); 1031 case Mips::ATOMIC_SWAP_I32: 1032 return emitAtomicBinary(MI, BB, 4, 0); 1033 case Mips::ATOMIC_SWAP_I64: 1034 return emitAtomicBinary(MI, BB, 8, 0); 1035 1036 case Mips::ATOMIC_CMP_SWAP_I8: 1037 return emitAtomicCmpSwapPartword(MI, BB, 1); 1038 case Mips::ATOMIC_CMP_SWAP_I16: 1039 return emitAtomicCmpSwapPartword(MI, BB, 2); 1040 case Mips::ATOMIC_CMP_SWAP_I32: 1041 return emitAtomicCmpSwap(MI, BB, 4); 1042 case Mips::ATOMIC_CMP_SWAP_I64: 1043 return emitAtomicCmpSwap(MI, BB, 8); 1044 case Mips::PseudoSDIV: 1045 case Mips::PseudoUDIV: 1046 case Mips::DIV: 1047 case Mips::DIVU: 1048 case Mips::MOD: 1049 case Mips::MODU: 1050 return insertDivByZeroTrap(MI, *BB, *Subtarget.getInstrInfo(), false, 1051 false); 1052 case Mips::SDIV_MM_Pseudo: 1053 case Mips::UDIV_MM_Pseudo: 1054 case Mips::SDIV_MM: 1055 case Mips::UDIV_MM: 1056 case Mips::DIV_MMR6: 1057 case Mips::DIVU_MMR6: 1058 case Mips::MOD_MMR6: 1059 case Mips::MODU_MMR6: 1060 return insertDivByZeroTrap(MI, *BB, *Subtarget.getInstrInfo(), false, true); 1061 case Mips::PseudoDSDIV: 1062 case Mips::PseudoDUDIV: 1063 case Mips::DDIV: 1064 case Mips::DDIVU: 1065 case Mips::DMOD: 1066 case Mips::DMODU: 1067 return insertDivByZeroTrap(MI, *BB, *Subtarget.getInstrInfo(), true, false); 1068 case Mips::DDIV_MM64R6: 1069 case Mips::DDIVU_MM64R6: 1070 case Mips::DMOD_MM64R6: 1071 case Mips::DMODU_MM64R6: 1072 return insertDivByZeroTrap(MI, *BB, *Subtarget.getInstrInfo(), true, true); 1073 case Mips::SEL_D: 1074 return emitSEL_D(MI, BB); 1075 1076 case Mips::PseudoSELECT_I: 1077 case Mips::PseudoSELECT_I64: 1078 case Mips::PseudoSELECT_S: 1079 case Mips::PseudoSELECT_D32: 1080 case Mips::PseudoSELECT_D64: 1081 return emitPseudoSELECT(MI, BB, false, Mips::BNE); 1082 case Mips::PseudoSELECTFP_F_I: 1083 case Mips::PseudoSELECTFP_F_I64: 1084 case Mips::PseudoSELECTFP_F_S: 1085 case Mips::PseudoSELECTFP_F_D32: 1086 case Mips::PseudoSELECTFP_F_D64: 1087 return emitPseudoSELECT(MI, BB, true, Mips::BC1F); 1088 case Mips::PseudoSELECTFP_T_I: 1089 case Mips::PseudoSELECTFP_T_I64: 1090 case Mips::PseudoSELECTFP_T_S: 1091 case Mips::PseudoSELECTFP_T_D32: 1092 case Mips::PseudoSELECTFP_T_D64: 1093 return emitPseudoSELECT(MI, BB, true, Mips::BC1T); 1094 } 1095 } 1096 1097 // This function also handles Mips::ATOMIC_SWAP_I32 (when BinOpcode == 0), and 1098 // Mips::ATOMIC_LOAD_NAND_I32 (when Nand == true) 1099 MachineBasicBlock * 1100 MipsTargetLowering::emitAtomicBinary(MachineInstr *MI, MachineBasicBlock *BB, 1101 unsigned Size, unsigned BinOpcode, 1102 bool Nand) const { 1103 assert((Size == 4 || Size == 8) && "Unsupported size for EmitAtomicBinary."); 1104 1105 MachineFunction *MF = BB->getParent(); 1106 MachineRegisterInfo &RegInfo = MF->getRegInfo(); 1107 const TargetRegisterClass *RC = getRegClassFor(MVT::getIntegerVT(Size * 8)); 1108 const TargetInstrInfo *TII = Subtarget.getInstrInfo(); 1109 DebugLoc DL = MI->getDebugLoc(); 1110 unsigned LL, SC, AND, NOR, ZERO, BEQ; 1111 1112 // FIXME: The below code should check for the ISA to emit the correct 64bit 1113 // operations when the size is 4. 1114 if (Size == 4) { 1115 if (isMicroMips) { 1116 LL = Mips::LL_MM; 1117 SC = Mips::SC_MM; 1118 } else { 1119 LL = Subtarget.hasMips32r6() ? Mips::LL_R6 : Mips::LL; 1120 SC = Subtarget.hasMips32r6() ? Mips::SC_R6 : Mips::SC; 1121 } 1122 AND = Mips::AND; 1123 NOR = Mips::NOR; 1124 ZERO = Mips::ZERO; 1125 BEQ = Mips::BEQ; 1126 } else { 1127 LL = Subtarget.hasMips64r6() ? Mips::LLD_R6 : Mips::LLD; 1128 SC = Subtarget.hasMips64r6() ? Mips::SCD_R6 : Mips::SCD; 1129 AND = Mips::AND64; 1130 NOR = Mips::NOR64; 1131 ZERO = Mips::ZERO_64; 1132 BEQ = Mips::BEQ64; 1133 } 1134 1135 unsigned OldVal = MI->getOperand(0).getReg(); 1136 unsigned Ptr = MI->getOperand(1).getReg(); 1137 unsigned Incr = MI->getOperand(2).getReg(); 1138 1139 unsigned StoreVal = RegInfo.createVirtualRegister(RC); 1140 unsigned AndRes = RegInfo.createVirtualRegister(RC); 1141 unsigned Success = RegInfo.createVirtualRegister(RC); 1142 1143 // insert new blocks after the current block 1144 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 1145 MachineBasicBlock *loopMBB = MF->CreateMachineBasicBlock(LLVM_BB); 1146 MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB); 1147 MachineFunction::iterator It = ++BB->getIterator(); 1148 MF->insert(It, loopMBB); 1149 MF->insert(It, exitMBB); 1150 1151 // Transfer the remainder of BB and its successor edges to exitMBB. 1152 exitMBB->splice(exitMBB->begin(), BB, 1153 std::next(MachineBasicBlock::iterator(MI)), BB->end()); 1154 exitMBB->transferSuccessorsAndUpdatePHIs(BB); 1155 1156 // thisMBB: 1157 // ... 1158 // fallthrough --> loopMBB 1159 BB->addSuccessor(loopMBB); 1160 loopMBB->addSuccessor(loopMBB); 1161 loopMBB->addSuccessor(exitMBB); 1162 1163 // loopMBB: 1164 // ll oldval, 0(ptr) 1165 // <binop> storeval, oldval, incr 1166 // sc success, storeval, 0(ptr) 1167 // beq success, $0, loopMBB 1168 BB = loopMBB; 1169 BuildMI(BB, DL, TII->get(LL), OldVal).addReg(Ptr).addImm(0); 1170 if (Nand) { 1171 // and andres, oldval, incr 1172 // nor storeval, $0, andres 1173 BuildMI(BB, DL, TII->get(AND), AndRes).addReg(OldVal).addReg(Incr); 1174 BuildMI(BB, DL, TII->get(NOR), StoreVal).addReg(ZERO).addReg(AndRes); 1175 } else if (BinOpcode) { 1176 // <binop> storeval, oldval, incr 1177 BuildMI(BB, DL, TII->get(BinOpcode), StoreVal).addReg(OldVal).addReg(Incr); 1178 } else { 1179 StoreVal = Incr; 1180 } 1181 BuildMI(BB, DL, TII->get(SC), Success).addReg(StoreVal).addReg(Ptr).addImm(0); 1182 BuildMI(BB, DL, TII->get(BEQ)).addReg(Success).addReg(ZERO).addMBB(loopMBB); 1183 1184 MI->eraseFromParent(); // The instruction is gone now. 1185 1186 return exitMBB; 1187 } 1188 1189 MachineBasicBlock *MipsTargetLowering::emitSignExtendToI32InReg( 1190 MachineInstr *MI, MachineBasicBlock *BB, unsigned Size, unsigned DstReg, 1191 unsigned SrcReg) const { 1192 const TargetInstrInfo *TII = Subtarget.getInstrInfo(); 1193 DebugLoc DL = MI->getDebugLoc(); 1194 1195 if (Subtarget.hasMips32r2() && Size == 1) { 1196 BuildMI(BB, DL, TII->get(Mips::SEB), DstReg).addReg(SrcReg); 1197 return BB; 1198 } 1199 1200 if (Subtarget.hasMips32r2() && Size == 2) { 1201 BuildMI(BB, DL, TII->get(Mips::SEH), DstReg).addReg(SrcReg); 1202 return BB; 1203 } 1204 1205 MachineFunction *MF = BB->getParent(); 1206 MachineRegisterInfo &RegInfo = MF->getRegInfo(); 1207 const TargetRegisterClass *RC = getRegClassFor(MVT::i32); 1208 unsigned ScrReg = RegInfo.createVirtualRegister(RC); 1209 1210 assert(Size < 32); 1211 int64_t ShiftImm = 32 - (Size * 8); 1212 1213 BuildMI(BB, DL, TII->get(Mips::SLL), ScrReg).addReg(SrcReg).addImm(ShiftImm); 1214 BuildMI(BB, DL, TII->get(Mips::SRA), DstReg).addReg(ScrReg).addImm(ShiftImm); 1215 1216 return BB; 1217 } 1218 1219 MachineBasicBlock *MipsTargetLowering::emitAtomicBinaryPartword( 1220 MachineInstr *MI, MachineBasicBlock *BB, unsigned Size, unsigned BinOpcode, 1221 bool Nand) const { 1222 assert((Size == 1 || Size == 2) && 1223 "Unsupported size for EmitAtomicBinaryPartial."); 1224 1225 MachineFunction *MF = BB->getParent(); 1226 MachineRegisterInfo &RegInfo = MF->getRegInfo(); 1227 const TargetRegisterClass *RC = getRegClassFor(MVT::i32); 1228 const TargetInstrInfo *TII = Subtarget.getInstrInfo(); 1229 DebugLoc DL = MI->getDebugLoc(); 1230 1231 unsigned Dest = MI->getOperand(0).getReg(); 1232 unsigned Ptr = MI->getOperand(1).getReg(); 1233 unsigned Incr = MI->getOperand(2).getReg(); 1234 1235 unsigned AlignedAddr = RegInfo.createVirtualRegister(RC); 1236 unsigned ShiftAmt = RegInfo.createVirtualRegister(RC); 1237 unsigned Mask = RegInfo.createVirtualRegister(RC); 1238 unsigned Mask2 = RegInfo.createVirtualRegister(RC); 1239 unsigned NewVal = RegInfo.createVirtualRegister(RC); 1240 unsigned OldVal = RegInfo.createVirtualRegister(RC); 1241 unsigned Incr2 = RegInfo.createVirtualRegister(RC); 1242 unsigned MaskLSB2 = RegInfo.createVirtualRegister(RC); 1243 unsigned PtrLSB2 = RegInfo.createVirtualRegister(RC); 1244 unsigned MaskUpper = RegInfo.createVirtualRegister(RC); 1245 unsigned AndRes = RegInfo.createVirtualRegister(RC); 1246 unsigned BinOpRes = RegInfo.createVirtualRegister(RC); 1247 unsigned MaskedOldVal0 = RegInfo.createVirtualRegister(RC); 1248 unsigned StoreVal = RegInfo.createVirtualRegister(RC); 1249 unsigned MaskedOldVal1 = RegInfo.createVirtualRegister(RC); 1250 unsigned SrlRes = RegInfo.createVirtualRegister(RC); 1251 unsigned Success = RegInfo.createVirtualRegister(RC); 1252 1253 // insert new blocks after the current block 1254 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 1255 MachineBasicBlock *loopMBB = MF->CreateMachineBasicBlock(LLVM_BB); 1256 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(LLVM_BB); 1257 MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB); 1258 MachineFunction::iterator It = ++BB->getIterator(); 1259 MF->insert(It, loopMBB); 1260 MF->insert(It, sinkMBB); 1261 MF->insert(It, exitMBB); 1262 1263 // Transfer the remainder of BB and its successor edges to exitMBB. 1264 exitMBB->splice(exitMBB->begin(), BB, 1265 std::next(MachineBasicBlock::iterator(MI)), BB->end()); 1266 exitMBB->transferSuccessorsAndUpdatePHIs(BB); 1267 1268 BB->addSuccessor(loopMBB); 1269 loopMBB->addSuccessor(loopMBB); 1270 loopMBB->addSuccessor(sinkMBB); 1271 sinkMBB->addSuccessor(exitMBB); 1272 1273 // thisMBB: 1274 // addiu masklsb2,$0,-4 # 0xfffffffc 1275 // and alignedaddr,ptr,masklsb2 1276 // andi ptrlsb2,ptr,3 1277 // sll shiftamt,ptrlsb2,3 1278 // ori maskupper,$0,255 # 0xff 1279 // sll mask,maskupper,shiftamt 1280 // nor mask2,$0,mask 1281 // sll incr2,incr,shiftamt 1282 1283 int64_t MaskImm = (Size == 1) ? 255 : 65535; 1284 BuildMI(BB, DL, TII->get(Mips::ADDiu), MaskLSB2) 1285 .addReg(Mips::ZERO).addImm(-4); 1286 BuildMI(BB, DL, TII->get(Mips::AND), AlignedAddr) 1287 .addReg(Ptr).addReg(MaskLSB2); 1288 BuildMI(BB, DL, TII->get(Mips::ANDi), PtrLSB2).addReg(Ptr).addImm(3); 1289 if (Subtarget.isLittle()) { 1290 BuildMI(BB, DL, TII->get(Mips::SLL), ShiftAmt).addReg(PtrLSB2).addImm(3); 1291 } else { 1292 unsigned Off = RegInfo.createVirtualRegister(RC); 1293 BuildMI(BB, DL, TII->get(Mips::XORi), Off) 1294 .addReg(PtrLSB2).addImm((Size == 1) ? 3 : 2); 1295 BuildMI(BB, DL, TII->get(Mips::SLL), ShiftAmt).addReg(Off).addImm(3); 1296 } 1297 BuildMI(BB, DL, TII->get(Mips::ORi), MaskUpper) 1298 .addReg(Mips::ZERO).addImm(MaskImm); 1299 BuildMI(BB, DL, TII->get(Mips::SLLV), Mask) 1300 .addReg(MaskUpper).addReg(ShiftAmt); 1301 BuildMI(BB, DL, TII->get(Mips::NOR), Mask2).addReg(Mips::ZERO).addReg(Mask); 1302 BuildMI(BB, DL, TII->get(Mips::SLLV), Incr2).addReg(Incr).addReg(ShiftAmt); 1303 1304 // atomic.load.binop 1305 // loopMBB: 1306 // ll oldval,0(alignedaddr) 1307 // binop binopres,oldval,incr2 1308 // and newval,binopres,mask 1309 // and maskedoldval0,oldval,mask2 1310 // or storeval,maskedoldval0,newval 1311 // sc success,storeval,0(alignedaddr) 1312 // beq success,$0,loopMBB 1313 1314 // atomic.swap 1315 // loopMBB: 1316 // ll oldval,0(alignedaddr) 1317 // and newval,incr2,mask 1318 // and maskedoldval0,oldval,mask2 1319 // or storeval,maskedoldval0,newval 1320 // sc success,storeval,0(alignedaddr) 1321 // beq success,$0,loopMBB 1322 1323 BB = loopMBB; 1324 unsigned LL = isMicroMips ? Mips::LL_MM : Mips::LL; 1325 BuildMI(BB, DL, TII->get(LL), OldVal).addReg(AlignedAddr).addImm(0); 1326 if (Nand) { 1327 // and andres, oldval, incr2 1328 // nor binopres, $0, andres 1329 // and newval, binopres, mask 1330 BuildMI(BB, DL, TII->get(Mips::AND), AndRes).addReg(OldVal).addReg(Incr2); 1331 BuildMI(BB, DL, TII->get(Mips::NOR), BinOpRes) 1332 .addReg(Mips::ZERO).addReg(AndRes); 1333 BuildMI(BB, DL, TII->get(Mips::AND), NewVal).addReg(BinOpRes).addReg(Mask); 1334 } else if (BinOpcode) { 1335 // <binop> binopres, oldval, incr2 1336 // and newval, binopres, mask 1337 BuildMI(BB, DL, TII->get(BinOpcode), BinOpRes).addReg(OldVal).addReg(Incr2); 1338 BuildMI(BB, DL, TII->get(Mips::AND), NewVal).addReg(BinOpRes).addReg(Mask); 1339 } else { // atomic.swap 1340 // and newval, incr2, mask 1341 BuildMI(BB, DL, TII->get(Mips::AND), NewVal).addReg(Incr2).addReg(Mask); 1342 } 1343 1344 BuildMI(BB, DL, TII->get(Mips::AND), MaskedOldVal0) 1345 .addReg(OldVal).addReg(Mask2); 1346 BuildMI(BB, DL, TII->get(Mips::OR), StoreVal) 1347 .addReg(MaskedOldVal0).addReg(NewVal); 1348 unsigned SC = isMicroMips ? Mips::SC_MM : Mips::SC; 1349 BuildMI(BB, DL, TII->get(SC), Success) 1350 .addReg(StoreVal).addReg(AlignedAddr).addImm(0); 1351 BuildMI(BB, DL, TII->get(Mips::BEQ)) 1352 .addReg(Success).addReg(Mips::ZERO).addMBB(loopMBB); 1353 1354 // sinkMBB: 1355 // and maskedoldval1,oldval,mask 1356 // srl srlres,maskedoldval1,shiftamt 1357 // sign_extend dest,srlres 1358 BB = sinkMBB; 1359 1360 BuildMI(BB, DL, TII->get(Mips::AND), MaskedOldVal1) 1361 .addReg(OldVal).addReg(Mask); 1362 BuildMI(BB, DL, TII->get(Mips::SRLV), SrlRes) 1363 .addReg(MaskedOldVal1).addReg(ShiftAmt); 1364 BB = emitSignExtendToI32InReg(MI, BB, Size, Dest, SrlRes); 1365 1366 MI->eraseFromParent(); // The instruction is gone now. 1367 1368 return exitMBB; 1369 } 1370 1371 MachineBasicBlock * MipsTargetLowering::emitAtomicCmpSwap(MachineInstr *MI, 1372 MachineBasicBlock *BB, 1373 unsigned Size) const { 1374 assert((Size == 4 || Size == 8) && "Unsupported size for EmitAtomicCmpSwap."); 1375 1376 MachineFunction *MF = BB->getParent(); 1377 MachineRegisterInfo &RegInfo = MF->getRegInfo(); 1378 const TargetRegisterClass *RC = getRegClassFor(MVT::getIntegerVT(Size * 8)); 1379 const TargetInstrInfo *TII = Subtarget.getInstrInfo(); 1380 DebugLoc DL = MI->getDebugLoc(); 1381 unsigned LL, SC, ZERO, BNE, BEQ; 1382 1383 if (Size == 4) { 1384 if (isMicroMips) { 1385 LL = Mips::LL_MM; 1386 SC = Mips::SC_MM; 1387 } else { 1388 LL = Subtarget.hasMips32r6() ? Mips::LL_R6 : Mips::LL; 1389 SC = Subtarget.hasMips32r6() ? Mips::SC_R6 : Mips::SC; 1390 } 1391 ZERO = Mips::ZERO; 1392 BNE = Mips::BNE; 1393 BEQ = Mips::BEQ; 1394 } else { 1395 LL = Subtarget.hasMips64r6() ? Mips::LLD_R6 : Mips::LLD; 1396 SC = Subtarget.hasMips64r6() ? Mips::SCD_R6 : Mips::SCD; 1397 ZERO = Mips::ZERO_64; 1398 BNE = Mips::BNE64; 1399 BEQ = Mips::BEQ64; 1400 } 1401 1402 unsigned Dest = MI->getOperand(0).getReg(); 1403 unsigned Ptr = MI->getOperand(1).getReg(); 1404 unsigned OldVal = MI->getOperand(2).getReg(); 1405 unsigned NewVal = MI->getOperand(3).getReg(); 1406 1407 unsigned Success = RegInfo.createVirtualRegister(RC); 1408 1409 // insert new blocks after the current block 1410 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 1411 MachineBasicBlock *loop1MBB = MF->CreateMachineBasicBlock(LLVM_BB); 1412 MachineBasicBlock *loop2MBB = MF->CreateMachineBasicBlock(LLVM_BB); 1413 MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB); 1414 MachineFunction::iterator It = ++BB->getIterator(); 1415 MF->insert(It, loop1MBB); 1416 MF->insert(It, loop2MBB); 1417 MF->insert(It, exitMBB); 1418 1419 // Transfer the remainder of BB and its successor edges to exitMBB. 1420 exitMBB->splice(exitMBB->begin(), BB, 1421 std::next(MachineBasicBlock::iterator(MI)), BB->end()); 1422 exitMBB->transferSuccessorsAndUpdatePHIs(BB); 1423 1424 // thisMBB: 1425 // ... 1426 // fallthrough --> loop1MBB 1427 BB->addSuccessor(loop1MBB); 1428 loop1MBB->addSuccessor(exitMBB); 1429 loop1MBB->addSuccessor(loop2MBB); 1430 loop2MBB->addSuccessor(loop1MBB); 1431 loop2MBB->addSuccessor(exitMBB); 1432 1433 // loop1MBB: 1434 // ll dest, 0(ptr) 1435 // bne dest, oldval, exitMBB 1436 BB = loop1MBB; 1437 BuildMI(BB, DL, TII->get(LL), Dest).addReg(Ptr).addImm(0); 1438 BuildMI(BB, DL, TII->get(BNE)) 1439 .addReg(Dest).addReg(OldVal).addMBB(exitMBB); 1440 1441 // loop2MBB: 1442 // sc success, newval, 0(ptr) 1443 // beq success, $0, loop1MBB 1444 BB = loop2MBB; 1445 BuildMI(BB, DL, TII->get(SC), Success) 1446 .addReg(NewVal).addReg(Ptr).addImm(0); 1447 BuildMI(BB, DL, TII->get(BEQ)) 1448 .addReg(Success).addReg(ZERO).addMBB(loop1MBB); 1449 1450 MI->eraseFromParent(); // The instruction is gone now. 1451 1452 return exitMBB; 1453 } 1454 1455 MachineBasicBlock * 1456 MipsTargetLowering::emitAtomicCmpSwapPartword(MachineInstr *MI, 1457 MachineBasicBlock *BB, 1458 unsigned Size) const { 1459 assert((Size == 1 || Size == 2) && 1460 "Unsupported size for EmitAtomicCmpSwapPartial."); 1461 1462 MachineFunction *MF = BB->getParent(); 1463 MachineRegisterInfo &RegInfo = MF->getRegInfo(); 1464 const TargetRegisterClass *RC = getRegClassFor(MVT::i32); 1465 bool ArePtrs64bit = ABI.ArePtrs64bit(); 1466 const TargetRegisterClass *RCp = 1467 getRegClassFor(ArePtrs64bit ? MVT::i64 : MVT::i32); 1468 const TargetInstrInfo *TII = Subtarget.getInstrInfo(); 1469 DebugLoc DL = MI->getDebugLoc(); 1470 1471 unsigned Dest = MI->getOperand(0).getReg(); 1472 unsigned Ptr = MI->getOperand(1).getReg(); 1473 unsigned CmpVal = MI->getOperand(2).getReg(); 1474 unsigned NewVal = MI->getOperand(3).getReg(); 1475 1476 unsigned AlignedAddr = RegInfo.createVirtualRegister(RCp); 1477 unsigned ShiftAmt = RegInfo.createVirtualRegister(RC); 1478 unsigned Mask = RegInfo.createVirtualRegister(RC); 1479 unsigned Mask2 = RegInfo.createVirtualRegister(RC); 1480 unsigned ShiftedCmpVal = RegInfo.createVirtualRegister(RC); 1481 unsigned OldVal = RegInfo.createVirtualRegister(RC); 1482 unsigned MaskedOldVal0 = RegInfo.createVirtualRegister(RC); 1483 unsigned ShiftedNewVal = RegInfo.createVirtualRegister(RC); 1484 unsigned MaskLSB2 = RegInfo.createVirtualRegister(RCp); 1485 unsigned PtrLSB2 = RegInfo.createVirtualRegister(RC); 1486 unsigned MaskUpper = RegInfo.createVirtualRegister(RC); 1487 unsigned MaskedCmpVal = RegInfo.createVirtualRegister(RC); 1488 unsigned MaskedNewVal = RegInfo.createVirtualRegister(RC); 1489 unsigned MaskedOldVal1 = RegInfo.createVirtualRegister(RC); 1490 unsigned StoreVal = RegInfo.createVirtualRegister(RC); 1491 unsigned SrlRes = RegInfo.createVirtualRegister(RC); 1492 unsigned Success = RegInfo.createVirtualRegister(RC); 1493 1494 // insert new blocks after the current block 1495 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 1496 MachineBasicBlock *loop1MBB = MF->CreateMachineBasicBlock(LLVM_BB); 1497 MachineBasicBlock *loop2MBB = MF->CreateMachineBasicBlock(LLVM_BB); 1498 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(LLVM_BB); 1499 MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB); 1500 MachineFunction::iterator It = ++BB->getIterator(); 1501 MF->insert(It, loop1MBB); 1502 MF->insert(It, loop2MBB); 1503 MF->insert(It, sinkMBB); 1504 MF->insert(It, exitMBB); 1505 1506 // Transfer the remainder of BB and its successor edges to exitMBB. 1507 exitMBB->splice(exitMBB->begin(), BB, 1508 std::next(MachineBasicBlock::iterator(MI)), BB->end()); 1509 exitMBB->transferSuccessorsAndUpdatePHIs(BB); 1510 1511 BB->addSuccessor(loop1MBB); 1512 loop1MBB->addSuccessor(sinkMBB); 1513 loop1MBB->addSuccessor(loop2MBB); 1514 loop2MBB->addSuccessor(loop1MBB); 1515 loop2MBB->addSuccessor(sinkMBB); 1516 sinkMBB->addSuccessor(exitMBB); 1517 1518 // FIXME: computation of newval2 can be moved to loop2MBB. 1519 // thisMBB: 1520 // addiu masklsb2,$0,-4 # 0xfffffffc 1521 // and alignedaddr,ptr,masklsb2 1522 // andi ptrlsb2,ptr,3 1523 // xori ptrlsb2,ptrlsb2,3 # Only for BE 1524 // sll shiftamt,ptrlsb2,3 1525 // ori maskupper,$0,255 # 0xff 1526 // sll mask,maskupper,shiftamt 1527 // nor mask2,$0,mask 1528 // andi maskedcmpval,cmpval,255 1529 // sll shiftedcmpval,maskedcmpval,shiftamt 1530 // andi maskednewval,newval,255 1531 // sll shiftednewval,maskednewval,shiftamt 1532 int64_t MaskImm = (Size == 1) ? 255 : 65535; 1533 BuildMI(BB, DL, TII->get(ArePtrs64bit ? Mips::DADDiu : Mips::ADDiu), MaskLSB2) 1534 .addReg(ABI.GetNullPtr()).addImm(-4); 1535 BuildMI(BB, DL, TII->get(ArePtrs64bit ? Mips::AND64 : Mips::AND), AlignedAddr) 1536 .addReg(Ptr).addReg(MaskLSB2); 1537 BuildMI(BB, DL, TII->get(Mips::ANDi), PtrLSB2) 1538 .addReg(Ptr, 0, ArePtrs64bit ? Mips::sub_32 : 0).addImm(3); 1539 if (Subtarget.isLittle()) { 1540 BuildMI(BB, DL, TII->get(Mips::SLL), ShiftAmt).addReg(PtrLSB2).addImm(3); 1541 } else { 1542 unsigned Off = RegInfo.createVirtualRegister(RC); 1543 BuildMI(BB, DL, TII->get(Mips::XORi), Off) 1544 .addReg(PtrLSB2).addImm((Size == 1) ? 3 : 2); 1545 BuildMI(BB, DL, TII->get(Mips::SLL), ShiftAmt).addReg(Off).addImm(3); 1546 } 1547 BuildMI(BB, DL, TII->get(Mips::ORi), MaskUpper) 1548 .addReg(Mips::ZERO).addImm(MaskImm); 1549 BuildMI(BB, DL, TII->get(Mips::SLLV), Mask) 1550 .addReg(MaskUpper).addReg(ShiftAmt); 1551 BuildMI(BB, DL, TII->get(Mips::NOR), Mask2).addReg(Mips::ZERO).addReg(Mask); 1552 BuildMI(BB, DL, TII->get(Mips::ANDi), MaskedCmpVal) 1553 .addReg(CmpVal).addImm(MaskImm); 1554 BuildMI(BB, DL, TII->get(Mips::SLLV), ShiftedCmpVal) 1555 .addReg(MaskedCmpVal).addReg(ShiftAmt); 1556 BuildMI(BB, DL, TII->get(Mips::ANDi), MaskedNewVal) 1557 .addReg(NewVal).addImm(MaskImm); 1558 BuildMI(BB, DL, TII->get(Mips::SLLV), ShiftedNewVal) 1559 .addReg(MaskedNewVal).addReg(ShiftAmt); 1560 1561 // loop1MBB: 1562 // ll oldval,0(alginedaddr) 1563 // and maskedoldval0,oldval,mask 1564 // bne maskedoldval0,shiftedcmpval,sinkMBB 1565 BB = loop1MBB; 1566 unsigned LL = isMicroMips ? Mips::LL_MM : Mips::LL; 1567 BuildMI(BB, DL, TII->get(LL), OldVal).addReg(AlignedAddr).addImm(0); 1568 BuildMI(BB, DL, TII->get(Mips::AND), MaskedOldVal0) 1569 .addReg(OldVal).addReg(Mask); 1570 BuildMI(BB, DL, TII->get(Mips::BNE)) 1571 .addReg(MaskedOldVal0).addReg(ShiftedCmpVal).addMBB(sinkMBB); 1572 1573 // loop2MBB: 1574 // and maskedoldval1,oldval,mask2 1575 // or storeval,maskedoldval1,shiftednewval 1576 // sc success,storeval,0(alignedaddr) 1577 // beq success,$0,loop1MBB 1578 BB = loop2MBB; 1579 BuildMI(BB, DL, TII->get(Mips::AND), MaskedOldVal1) 1580 .addReg(OldVal).addReg(Mask2); 1581 BuildMI(BB, DL, TII->get(Mips::OR), StoreVal) 1582 .addReg(MaskedOldVal1).addReg(ShiftedNewVal); 1583 unsigned SC = isMicroMips ? Mips::SC_MM : Mips::SC; 1584 BuildMI(BB, DL, TII->get(SC), Success) 1585 .addReg(StoreVal).addReg(AlignedAddr).addImm(0); 1586 BuildMI(BB, DL, TII->get(Mips::BEQ)) 1587 .addReg(Success).addReg(Mips::ZERO).addMBB(loop1MBB); 1588 1589 // sinkMBB: 1590 // srl srlres,maskedoldval0,shiftamt 1591 // sign_extend dest,srlres 1592 BB = sinkMBB; 1593 1594 BuildMI(BB, DL, TII->get(Mips::SRLV), SrlRes) 1595 .addReg(MaskedOldVal0).addReg(ShiftAmt); 1596 BB = emitSignExtendToI32InReg(MI, BB, Size, Dest, SrlRes); 1597 1598 MI->eraseFromParent(); // The instruction is gone now. 1599 1600 return exitMBB; 1601 } 1602 1603 MachineBasicBlock *MipsTargetLowering::emitSEL_D(MachineInstr *MI, 1604 MachineBasicBlock *BB) const { 1605 MachineFunction *MF = BB->getParent(); 1606 const TargetRegisterInfo *TRI = Subtarget.getRegisterInfo(); 1607 const TargetInstrInfo *TII = Subtarget.getInstrInfo(); 1608 MachineRegisterInfo &RegInfo = MF->getRegInfo(); 1609 DebugLoc DL = MI->getDebugLoc(); 1610 MachineBasicBlock::iterator II(MI); 1611 1612 unsigned Fc = MI->getOperand(1).getReg(); 1613 const auto &FGR64RegClass = TRI->getRegClass(Mips::FGR64RegClassID); 1614 1615 unsigned Fc2 = RegInfo.createVirtualRegister(FGR64RegClass); 1616 1617 BuildMI(*BB, II, DL, TII->get(Mips::SUBREG_TO_REG), Fc2) 1618 .addImm(0) 1619 .addReg(Fc) 1620 .addImm(Mips::sub_lo); 1621 1622 // We don't erase the original instruction, we just replace the condition 1623 // register with the 64-bit super-register. 1624 MI->getOperand(1).setReg(Fc2); 1625 1626 return BB; 1627 } 1628 1629 //===----------------------------------------------------------------------===// 1630 // Misc Lower Operation implementation 1631 //===----------------------------------------------------------------------===// 1632 SDValue MipsTargetLowering::lowerBR_JT(SDValue Op, SelectionDAG &DAG) const { 1633 SDValue Chain = Op.getOperand(0); 1634 SDValue Table = Op.getOperand(1); 1635 SDValue Index = Op.getOperand(2); 1636 SDLoc DL(Op); 1637 auto &TD = DAG.getDataLayout(); 1638 EVT PTy = getPointerTy(TD); 1639 unsigned EntrySize = 1640 DAG.getMachineFunction().getJumpTableInfo()->getEntrySize(TD); 1641 1642 Index = DAG.getNode(ISD::MUL, DL, PTy, Index, 1643 DAG.getConstant(EntrySize, DL, PTy)); 1644 SDValue Addr = DAG.getNode(ISD::ADD, DL, PTy, Index, Table); 1645 1646 EVT MemVT = EVT::getIntegerVT(*DAG.getContext(), EntrySize * 8); 1647 Addr = 1648 DAG.getExtLoad(ISD::SEXTLOAD, DL, PTy, Chain, Addr, 1649 MachinePointerInfo::getJumpTable(DAG.getMachineFunction()), 1650 MemVT, false, false, false, 0); 1651 Chain = Addr.getValue(1); 1652 1653 if ((getTargetMachine().getRelocationModel() == Reloc::PIC_) || ABI.IsN64()) { 1654 // For PIC, the sequence is: 1655 // BRIND(load(Jumptable + index) + RelocBase) 1656 // RelocBase can be JumpTable, GOT or some sort of global base. 1657 Addr = DAG.getNode(ISD::ADD, DL, PTy, Addr, 1658 getPICJumpTableRelocBase(Table, DAG)); 1659 } 1660 1661 return DAG.getNode(ISD::BRIND, DL, MVT::Other, Chain, Addr); 1662 } 1663 1664 SDValue MipsTargetLowering::lowerBRCOND(SDValue Op, SelectionDAG &DAG) const { 1665 // The first operand is the chain, the second is the condition, the third is 1666 // the block to branch to if the condition is true. 1667 SDValue Chain = Op.getOperand(0); 1668 SDValue Dest = Op.getOperand(2); 1669 SDLoc DL(Op); 1670 1671 assert(!Subtarget.hasMips32r6() && !Subtarget.hasMips64r6()); 1672 SDValue CondRes = createFPCmp(DAG, Op.getOperand(1)); 1673 1674 // Return if flag is not set by a floating point comparison. 1675 if (CondRes.getOpcode() != MipsISD::FPCmp) 1676 return Op; 1677 1678 SDValue CCNode = CondRes.getOperand(2); 1679 Mips::CondCode CC = 1680 (Mips::CondCode)cast<ConstantSDNode>(CCNode)->getZExtValue(); 1681 unsigned Opc = invertFPCondCodeUser(CC) ? Mips::BRANCH_F : Mips::BRANCH_T; 1682 SDValue BrCode = DAG.getConstant(Opc, DL, MVT::i32); 1683 SDValue FCC0 = DAG.getRegister(Mips::FCC0, MVT::i32); 1684 return DAG.getNode(MipsISD::FPBrcond, DL, Op.getValueType(), Chain, BrCode, 1685 FCC0, Dest, CondRes); 1686 } 1687 1688 SDValue MipsTargetLowering:: 1689 lowerSELECT(SDValue Op, SelectionDAG &DAG) const 1690 { 1691 assert(!Subtarget.hasMips32r6() && !Subtarget.hasMips64r6()); 1692 SDValue Cond = createFPCmp(DAG, Op.getOperand(0)); 1693 1694 // Return if flag is not set by a floating point comparison. 1695 if (Cond.getOpcode() != MipsISD::FPCmp) 1696 return Op; 1697 1698 return createCMovFP(DAG, Cond, Op.getOperand(1), Op.getOperand(2), 1699 SDLoc(Op)); 1700 } 1701 1702 SDValue MipsTargetLowering::lowerSETCC(SDValue Op, SelectionDAG &DAG) const { 1703 assert(!Subtarget.hasMips32r6() && !Subtarget.hasMips64r6()); 1704 SDValue Cond = createFPCmp(DAG, Op); 1705 1706 assert(Cond.getOpcode() == MipsISD::FPCmp && 1707 "Floating point operand expected."); 1708 1709 SDLoc DL(Op); 1710 SDValue True = DAG.getConstant(1, DL, MVT::i32); 1711 SDValue False = DAG.getConstant(0, DL, MVT::i32); 1712 1713 return createCMovFP(DAG, Cond, True, False, DL); 1714 } 1715 1716 SDValue MipsTargetLowering::lowerGlobalAddress(SDValue Op, 1717 SelectionDAG &DAG) const { 1718 EVT Ty = Op.getValueType(); 1719 GlobalAddressSDNode *N = cast<GlobalAddressSDNode>(Op); 1720 const GlobalValue *GV = N->getGlobal(); 1721 1722 if (getTargetMachine().getRelocationModel() != Reloc::PIC_ && !ABI.IsN64()) { 1723 const MipsTargetObjectFile *TLOF = 1724 static_cast<const MipsTargetObjectFile *>( 1725 getTargetMachine().getObjFileLowering()); 1726 if (TLOF->IsGlobalInSmallSection(GV, getTargetMachine())) 1727 // %gp_rel relocation 1728 return getAddrGPRel(N, SDLoc(N), Ty, DAG); 1729 1730 // %hi/%lo relocation 1731 return getAddrNonPIC(N, SDLoc(N), Ty, DAG); 1732 } 1733 1734 if (GV->hasInternalLinkage() || (GV->hasLocalLinkage() && !isa<Function>(GV))) 1735 return getAddrLocal(N, SDLoc(N), Ty, DAG, ABI.IsN32() || ABI.IsN64()); 1736 1737 if (LargeGOT) 1738 return getAddrGlobalLargeGOT( 1739 N, SDLoc(N), Ty, DAG, MipsII::MO_GOT_HI16, MipsII::MO_GOT_LO16, 1740 DAG.getEntryNode(), 1741 MachinePointerInfo::getGOT(DAG.getMachineFunction())); 1742 1743 return getAddrGlobal( 1744 N, SDLoc(N), Ty, DAG, 1745 (ABI.IsN32() || ABI.IsN64()) ? MipsII::MO_GOT_DISP : MipsII::MO_GOT16, 1746 DAG.getEntryNode(), MachinePointerInfo::getGOT(DAG.getMachineFunction())); 1747 } 1748 1749 SDValue MipsTargetLowering::lowerBlockAddress(SDValue Op, 1750 SelectionDAG &DAG) const { 1751 BlockAddressSDNode *N = cast<BlockAddressSDNode>(Op); 1752 EVT Ty = Op.getValueType(); 1753 1754 if (getTargetMachine().getRelocationModel() != Reloc::PIC_ && !ABI.IsN64()) 1755 return getAddrNonPIC(N, SDLoc(N), Ty, DAG); 1756 1757 return getAddrLocal(N, SDLoc(N), Ty, DAG, ABI.IsN32() || ABI.IsN64()); 1758 } 1759 1760 SDValue MipsTargetLowering:: 1761 lowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const 1762 { 1763 // If the relocation model is PIC, use the General Dynamic TLS Model or 1764 // Local Dynamic TLS model, otherwise use the Initial Exec or 1765 // Local Exec TLS Model. 1766 1767 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op); 1768 if (DAG.getTarget().Options.EmulatedTLS) 1769 return LowerToTLSEmulatedModel(GA, DAG); 1770 1771 SDLoc DL(GA); 1772 const GlobalValue *GV = GA->getGlobal(); 1773 EVT PtrVT = getPointerTy(DAG.getDataLayout()); 1774 1775 TLSModel::Model model = getTargetMachine().getTLSModel(GV); 1776 1777 if (model == TLSModel::GeneralDynamic || model == TLSModel::LocalDynamic) { 1778 // General Dynamic and Local Dynamic TLS Model. 1779 unsigned Flag = (model == TLSModel::LocalDynamic) ? MipsII::MO_TLSLDM 1780 : MipsII::MO_TLSGD; 1781 1782 SDValue TGA = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, Flag); 1783 SDValue Argument = DAG.getNode(MipsISD::Wrapper, DL, PtrVT, 1784 getGlobalReg(DAG, PtrVT), TGA); 1785 unsigned PtrSize = PtrVT.getSizeInBits(); 1786 IntegerType *PtrTy = Type::getIntNTy(*DAG.getContext(), PtrSize); 1787 1788 SDValue TlsGetAddr = DAG.getExternalSymbol("__tls_get_addr", PtrVT); 1789 1790 ArgListTy Args; 1791 ArgListEntry Entry; 1792 Entry.Node = Argument; 1793 Entry.Ty = PtrTy; 1794 Args.push_back(Entry); 1795 1796 TargetLowering::CallLoweringInfo CLI(DAG); 1797 CLI.setDebugLoc(DL).setChain(DAG.getEntryNode()) 1798 .setCallee(CallingConv::C, PtrTy, TlsGetAddr, std::move(Args), 0); 1799 std::pair<SDValue, SDValue> CallResult = LowerCallTo(CLI); 1800 1801 SDValue Ret = CallResult.first; 1802 1803 if (model != TLSModel::LocalDynamic) 1804 return Ret; 1805 1806 SDValue TGAHi = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, 1807 MipsII::MO_DTPREL_HI); 1808 SDValue Hi = DAG.getNode(MipsISD::Hi, DL, PtrVT, TGAHi); 1809 SDValue TGALo = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, 1810 MipsII::MO_DTPREL_LO); 1811 SDValue Lo = DAG.getNode(MipsISD::Lo, DL, PtrVT, TGALo); 1812 SDValue Add = DAG.getNode(ISD::ADD, DL, PtrVT, Hi, Ret); 1813 return DAG.getNode(ISD::ADD, DL, PtrVT, Add, Lo); 1814 } 1815 1816 SDValue Offset; 1817 if (model == TLSModel::InitialExec) { 1818 // Initial Exec TLS Model 1819 SDValue TGA = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, 1820 MipsII::MO_GOTTPREL); 1821 TGA = DAG.getNode(MipsISD::Wrapper, DL, PtrVT, getGlobalReg(DAG, PtrVT), 1822 TGA); 1823 Offset = DAG.getLoad(PtrVT, DL, 1824 DAG.getEntryNode(), TGA, MachinePointerInfo(), 1825 false, false, false, 0); 1826 } else { 1827 // Local Exec TLS Model 1828 assert(model == TLSModel::LocalExec); 1829 SDValue TGAHi = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, 1830 MipsII::MO_TPREL_HI); 1831 SDValue TGALo = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, 1832 MipsII::MO_TPREL_LO); 1833 SDValue Hi = DAG.getNode(MipsISD::Hi, DL, PtrVT, TGAHi); 1834 SDValue Lo = DAG.getNode(MipsISD::Lo, DL, PtrVT, TGALo); 1835 Offset = DAG.getNode(ISD::ADD, DL, PtrVT, Hi, Lo); 1836 } 1837 1838 SDValue ThreadPointer = DAG.getNode(MipsISD::ThreadPointer, DL, PtrVT); 1839 return DAG.getNode(ISD::ADD, DL, PtrVT, ThreadPointer, Offset); 1840 } 1841 1842 SDValue MipsTargetLowering:: 1843 lowerJumpTable(SDValue Op, SelectionDAG &DAG) const 1844 { 1845 JumpTableSDNode *N = cast<JumpTableSDNode>(Op); 1846 EVT Ty = Op.getValueType(); 1847 1848 if (getTargetMachine().getRelocationModel() != Reloc::PIC_ && !ABI.IsN64()) 1849 return getAddrNonPIC(N, SDLoc(N), Ty, DAG); 1850 1851 return getAddrLocal(N, SDLoc(N), Ty, DAG, ABI.IsN32() || ABI.IsN64()); 1852 } 1853 1854 SDValue MipsTargetLowering:: 1855 lowerConstantPool(SDValue Op, SelectionDAG &DAG) const 1856 { 1857 ConstantPoolSDNode *N = cast<ConstantPoolSDNode>(Op); 1858 EVT Ty = Op.getValueType(); 1859 1860 if (getTargetMachine().getRelocationModel() != Reloc::PIC_ && !ABI.IsN64()) { 1861 const MipsTargetObjectFile *TLOF = 1862 static_cast<const MipsTargetObjectFile *>( 1863 getTargetMachine().getObjFileLowering()); 1864 1865 if (TLOF->IsConstantInSmallSection(DAG.getDataLayout(), N->getConstVal(), 1866 getTargetMachine())) 1867 // %gp_rel relocation 1868 return getAddrGPRel(N, SDLoc(N), Ty, DAG); 1869 1870 return getAddrNonPIC(N, SDLoc(N), Ty, DAG); 1871 } 1872 1873 return getAddrLocal(N, SDLoc(N), Ty, DAG, ABI.IsN32() || ABI.IsN64()); 1874 } 1875 1876 SDValue MipsTargetLowering::lowerVASTART(SDValue Op, SelectionDAG &DAG) const { 1877 MachineFunction &MF = DAG.getMachineFunction(); 1878 MipsFunctionInfo *FuncInfo = MF.getInfo<MipsFunctionInfo>(); 1879 1880 SDLoc DL(Op); 1881 SDValue FI = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), 1882 getPointerTy(MF.getDataLayout())); 1883 1884 // vastart just stores the address of the VarArgsFrameIndex slot into the 1885 // memory location argument. 1886 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue(); 1887 return DAG.getStore(Op.getOperand(0), DL, FI, Op.getOperand(1), 1888 MachinePointerInfo(SV), false, false, 0); 1889 } 1890 1891 SDValue MipsTargetLowering::lowerVAARG(SDValue Op, SelectionDAG &DAG) const { 1892 SDNode *Node = Op.getNode(); 1893 EVT VT = Node->getValueType(0); 1894 SDValue Chain = Node->getOperand(0); 1895 SDValue VAListPtr = Node->getOperand(1); 1896 unsigned Align = Node->getConstantOperandVal(3); 1897 const Value *SV = cast<SrcValueSDNode>(Node->getOperand(2))->getValue(); 1898 SDLoc DL(Node); 1899 unsigned ArgSlotSizeInBytes = (ABI.IsN32() || ABI.IsN64()) ? 8 : 4; 1900 1901 SDValue VAListLoad = 1902 DAG.getLoad(getPointerTy(DAG.getDataLayout()), DL, Chain, VAListPtr, 1903 MachinePointerInfo(SV), false, false, false, 0); 1904 SDValue VAList = VAListLoad; 1905 1906 // Re-align the pointer if necessary. 1907 // It should only ever be necessary for 64-bit types on O32 since the minimum 1908 // argument alignment is the same as the maximum type alignment for N32/N64. 1909 // 1910 // FIXME: We currently align too often. The code generator doesn't notice 1911 // when the pointer is still aligned from the last va_arg (or pair of 1912 // va_args for the i64 on O32 case). 1913 if (Align > getMinStackArgumentAlignment()) { 1914 assert(((Align & (Align-1)) == 0) && "Expected Align to be a power of 2"); 1915 1916 VAList = DAG.getNode(ISD::ADD, DL, VAList.getValueType(), VAList, 1917 DAG.getConstant(Align - 1, DL, VAList.getValueType())); 1918 1919 VAList = DAG.getNode(ISD::AND, DL, VAList.getValueType(), VAList, 1920 DAG.getConstant(-(int64_t)Align, DL, 1921 VAList.getValueType())); 1922 } 1923 1924 // Increment the pointer, VAList, to the next vaarg. 1925 auto &TD = DAG.getDataLayout(); 1926 unsigned ArgSizeInBytes = 1927 TD.getTypeAllocSize(VT.getTypeForEVT(*DAG.getContext())); 1928 SDValue Tmp3 = 1929 DAG.getNode(ISD::ADD, DL, VAList.getValueType(), VAList, 1930 DAG.getConstant(alignTo(ArgSizeInBytes, ArgSlotSizeInBytes), 1931 DL, VAList.getValueType())); 1932 // Store the incremented VAList to the legalized pointer 1933 Chain = DAG.getStore(VAListLoad.getValue(1), DL, Tmp3, VAListPtr, 1934 MachinePointerInfo(SV), false, false, 0); 1935 1936 // In big-endian mode we must adjust the pointer when the load size is smaller 1937 // than the argument slot size. We must also reduce the known alignment to 1938 // match. For example in the N64 ABI, we must add 4 bytes to the offset to get 1939 // the correct half of the slot, and reduce the alignment from 8 (slot 1940 // alignment) down to 4 (type alignment). 1941 if (!Subtarget.isLittle() && ArgSizeInBytes < ArgSlotSizeInBytes) { 1942 unsigned Adjustment = ArgSlotSizeInBytes - ArgSizeInBytes; 1943 VAList = DAG.getNode(ISD::ADD, DL, VAListPtr.getValueType(), VAList, 1944 DAG.getIntPtrConstant(Adjustment, DL)); 1945 } 1946 // Load the actual argument out of the pointer VAList 1947 return DAG.getLoad(VT, DL, Chain, VAList, MachinePointerInfo(), false, false, 1948 false, 0); 1949 } 1950 1951 static SDValue lowerFCOPYSIGN32(SDValue Op, SelectionDAG &DAG, 1952 bool HasExtractInsert) { 1953 EVT TyX = Op.getOperand(0).getValueType(); 1954 EVT TyY = Op.getOperand(1).getValueType(); 1955 SDLoc DL(Op); 1956 SDValue Const1 = DAG.getConstant(1, DL, MVT::i32); 1957 SDValue Const31 = DAG.getConstant(31, DL, MVT::i32); 1958 SDValue Res; 1959 1960 // If operand is of type f64, extract the upper 32-bit. Otherwise, bitcast it 1961 // to i32. 1962 SDValue X = (TyX == MVT::f32) ? 1963 DAG.getNode(ISD::BITCAST, DL, MVT::i32, Op.getOperand(0)) : 1964 DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32, Op.getOperand(0), 1965 Const1); 1966 SDValue Y = (TyY == MVT::f32) ? 1967 DAG.getNode(ISD::BITCAST, DL, MVT::i32, Op.getOperand(1)) : 1968 DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32, Op.getOperand(1), 1969 Const1); 1970 1971 if (HasExtractInsert) { 1972 // ext E, Y, 31, 1 ; extract bit31 of Y 1973 // ins X, E, 31, 1 ; insert extracted bit at bit31 of X 1974 SDValue E = DAG.getNode(MipsISD::Ext, DL, MVT::i32, Y, Const31, Const1); 1975 Res = DAG.getNode(MipsISD::Ins, DL, MVT::i32, E, Const31, Const1, X); 1976 } else { 1977 // sll SllX, X, 1 1978 // srl SrlX, SllX, 1 1979 // srl SrlY, Y, 31 1980 // sll SllY, SrlX, 31 1981 // or Or, SrlX, SllY 1982 SDValue SllX = DAG.getNode(ISD::SHL, DL, MVT::i32, X, Const1); 1983 SDValue SrlX = DAG.getNode(ISD::SRL, DL, MVT::i32, SllX, Const1); 1984 SDValue SrlY = DAG.getNode(ISD::SRL, DL, MVT::i32, Y, Const31); 1985 SDValue SllY = DAG.getNode(ISD::SHL, DL, MVT::i32, SrlY, Const31); 1986 Res = DAG.getNode(ISD::OR, DL, MVT::i32, SrlX, SllY); 1987 } 1988 1989 if (TyX == MVT::f32) 1990 return DAG.getNode(ISD::BITCAST, DL, Op.getOperand(0).getValueType(), Res); 1991 1992 SDValue LowX = DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32, 1993 Op.getOperand(0), 1994 DAG.getConstant(0, DL, MVT::i32)); 1995 return DAG.getNode(MipsISD::BuildPairF64, DL, MVT::f64, LowX, Res); 1996 } 1997 1998 static SDValue lowerFCOPYSIGN64(SDValue Op, SelectionDAG &DAG, 1999 bool HasExtractInsert) { 2000 unsigned WidthX = Op.getOperand(0).getValueSizeInBits(); 2001 unsigned WidthY = Op.getOperand(1).getValueSizeInBits(); 2002 EVT TyX = MVT::getIntegerVT(WidthX), TyY = MVT::getIntegerVT(WidthY); 2003 SDLoc DL(Op); 2004 SDValue Const1 = DAG.getConstant(1, DL, MVT::i32); 2005 2006 // Bitcast to integer nodes. 2007 SDValue X = DAG.getNode(ISD::BITCAST, DL, TyX, Op.getOperand(0)); 2008 SDValue Y = DAG.getNode(ISD::BITCAST, DL, TyY, Op.getOperand(1)); 2009 2010 if (HasExtractInsert) { 2011 // ext E, Y, width(Y) - 1, 1 ; extract bit width(Y)-1 of Y 2012 // ins X, E, width(X) - 1, 1 ; insert extracted bit at bit width(X)-1 of X 2013 SDValue E = DAG.getNode(MipsISD::Ext, DL, TyY, Y, 2014 DAG.getConstant(WidthY - 1, DL, MVT::i32), Const1); 2015 2016 if (WidthX > WidthY) 2017 E = DAG.getNode(ISD::ZERO_EXTEND, DL, TyX, E); 2018 else if (WidthY > WidthX) 2019 E = DAG.getNode(ISD::TRUNCATE, DL, TyX, E); 2020 2021 SDValue I = DAG.getNode(MipsISD::Ins, DL, TyX, E, 2022 DAG.getConstant(WidthX - 1, DL, MVT::i32), Const1, 2023 X); 2024 return DAG.getNode(ISD::BITCAST, DL, Op.getOperand(0).getValueType(), I); 2025 } 2026 2027 // (d)sll SllX, X, 1 2028 // (d)srl SrlX, SllX, 1 2029 // (d)srl SrlY, Y, width(Y)-1 2030 // (d)sll SllY, SrlX, width(Y)-1 2031 // or Or, SrlX, SllY 2032 SDValue SllX = DAG.getNode(ISD::SHL, DL, TyX, X, Const1); 2033 SDValue SrlX = DAG.getNode(ISD::SRL, DL, TyX, SllX, Const1); 2034 SDValue SrlY = DAG.getNode(ISD::SRL, DL, TyY, Y, 2035 DAG.getConstant(WidthY - 1, DL, MVT::i32)); 2036 2037 if (WidthX > WidthY) 2038 SrlY = DAG.getNode(ISD::ZERO_EXTEND, DL, TyX, SrlY); 2039 else if (WidthY > WidthX) 2040 SrlY = DAG.getNode(ISD::TRUNCATE, DL, TyX, SrlY); 2041 2042 SDValue SllY = DAG.getNode(ISD::SHL, DL, TyX, SrlY, 2043 DAG.getConstant(WidthX - 1, DL, MVT::i32)); 2044 SDValue Or = DAG.getNode(ISD::OR, DL, TyX, SrlX, SllY); 2045 return DAG.getNode(ISD::BITCAST, DL, Op.getOperand(0).getValueType(), Or); 2046 } 2047 2048 SDValue 2049 MipsTargetLowering::lowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const { 2050 if (Subtarget.isGP64bit()) 2051 return lowerFCOPYSIGN64(Op, DAG, Subtarget.hasExtractInsert()); 2052 2053 return lowerFCOPYSIGN32(Op, DAG, Subtarget.hasExtractInsert()); 2054 } 2055 2056 SDValue MipsTargetLowering:: 2057 lowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const { 2058 // check the depth 2059 assert((cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue() == 0) && 2060 "Frame address can only be determined for current frame."); 2061 2062 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo(); 2063 MFI->setFrameAddressIsTaken(true); 2064 EVT VT = Op.getValueType(); 2065 SDLoc DL(Op); 2066 SDValue FrameAddr = DAG.getCopyFromReg( 2067 DAG.getEntryNode(), DL, ABI.IsN64() ? Mips::FP_64 : Mips::FP, VT); 2068 return FrameAddr; 2069 } 2070 2071 SDValue MipsTargetLowering::lowerRETURNADDR(SDValue Op, 2072 SelectionDAG &DAG) const { 2073 if (verifyReturnAddressArgumentIsConstant(Op, DAG)) 2074 return SDValue(); 2075 2076 // check the depth 2077 assert((cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue() == 0) && 2078 "Return address can be determined only for current frame."); 2079 2080 MachineFunction &MF = DAG.getMachineFunction(); 2081 MachineFrameInfo *MFI = MF.getFrameInfo(); 2082 MVT VT = Op.getSimpleValueType(); 2083 unsigned RA = ABI.IsN64() ? Mips::RA_64 : Mips::RA; 2084 MFI->setReturnAddressIsTaken(true); 2085 2086 // Return RA, which contains the return address. Mark it an implicit live-in. 2087 unsigned Reg = MF.addLiveIn(RA, getRegClassFor(VT)); 2088 return DAG.getCopyFromReg(DAG.getEntryNode(), SDLoc(Op), Reg, VT); 2089 } 2090 2091 // An EH_RETURN is the result of lowering llvm.eh.return which in turn is 2092 // generated from __builtin_eh_return (offset, handler) 2093 // The effect of this is to adjust the stack pointer by "offset" 2094 // and then branch to "handler". 2095 SDValue MipsTargetLowering::lowerEH_RETURN(SDValue Op, SelectionDAG &DAG) 2096 const { 2097 MachineFunction &MF = DAG.getMachineFunction(); 2098 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>(); 2099 2100 MipsFI->setCallsEhReturn(); 2101 SDValue Chain = Op.getOperand(0); 2102 SDValue Offset = Op.getOperand(1); 2103 SDValue Handler = Op.getOperand(2); 2104 SDLoc DL(Op); 2105 EVT Ty = ABI.IsN64() ? MVT::i64 : MVT::i32; 2106 2107 // Store stack offset in V1, store jump target in V0. Glue CopyToReg and 2108 // EH_RETURN nodes, so that instructions are emitted back-to-back. 2109 unsigned OffsetReg = ABI.IsN64() ? Mips::V1_64 : Mips::V1; 2110 unsigned AddrReg = ABI.IsN64() ? Mips::V0_64 : Mips::V0; 2111 Chain = DAG.getCopyToReg(Chain, DL, OffsetReg, Offset, SDValue()); 2112 Chain = DAG.getCopyToReg(Chain, DL, AddrReg, Handler, Chain.getValue(1)); 2113 return DAG.getNode(MipsISD::EH_RETURN, DL, MVT::Other, Chain, 2114 DAG.getRegister(OffsetReg, Ty), 2115 DAG.getRegister(AddrReg, getPointerTy(MF.getDataLayout())), 2116 Chain.getValue(1)); 2117 } 2118 2119 SDValue MipsTargetLowering::lowerATOMIC_FENCE(SDValue Op, 2120 SelectionDAG &DAG) const { 2121 // FIXME: Need pseudo-fence for 'singlethread' fences 2122 // FIXME: Set SType for weaker fences where supported/appropriate. 2123 unsigned SType = 0; 2124 SDLoc DL(Op); 2125 return DAG.getNode(MipsISD::Sync, DL, MVT::Other, Op.getOperand(0), 2126 DAG.getConstant(SType, DL, MVT::i32)); 2127 } 2128 2129 SDValue MipsTargetLowering::lowerShiftLeftParts(SDValue Op, 2130 SelectionDAG &DAG) const { 2131 SDLoc DL(Op); 2132 MVT VT = Subtarget.isGP64bit() ? MVT::i64 : MVT::i32; 2133 2134 SDValue Lo = Op.getOperand(0), Hi = Op.getOperand(1); 2135 SDValue Shamt = Op.getOperand(2); 2136 // if shamt < (VT.bits): 2137 // lo = (shl lo, shamt) 2138 // hi = (or (shl hi, shamt) (srl (srl lo, 1), ~shamt)) 2139 // else: 2140 // lo = 0 2141 // hi = (shl lo, shamt[4:0]) 2142 SDValue Not = DAG.getNode(ISD::XOR, DL, MVT::i32, Shamt, 2143 DAG.getConstant(-1, DL, MVT::i32)); 2144 SDValue ShiftRight1Lo = DAG.getNode(ISD::SRL, DL, VT, Lo, 2145 DAG.getConstant(1, DL, VT)); 2146 SDValue ShiftRightLo = DAG.getNode(ISD::SRL, DL, VT, ShiftRight1Lo, Not); 2147 SDValue ShiftLeftHi = DAG.getNode(ISD::SHL, DL, VT, Hi, Shamt); 2148 SDValue Or = DAG.getNode(ISD::OR, DL, VT, ShiftLeftHi, ShiftRightLo); 2149 SDValue ShiftLeftLo = DAG.getNode(ISD::SHL, DL, VT, Lo, Shamt); 2150 SDValue Cond = DAG.getNode(ISD::AND, DL, MVT::i32, Shamt, 2151 DAG.getConstant(VT.getSizeInBits(), DL, MVT::i32)); 2152 Lo = DAG.getNode(ISD::SELECT, DL, VT, Cond, 2153 DAG.getConstant(0, DL, VT), ShiftLeftLo); 2154 Hi = DAG.getNode(ISD::SELECT, DL, VT, Cond, ShiftLeftLo, Or); 2155 2156 SDValue Ops[2] = {Lo, Hi}; 2157 return DAG.getMergeValues(Ops, DL); 2158 } 2159 2160 SDValue MipsTargetLowering::lowerShiftRightParts(SDValue Op, SelectionDAG &DAG, 2161 bool IsSRA) const { 2162 SDLoc DL(Op); 2163 SDValue Lo = Op.getOperand(0), Hi = Op.getOperand(1); 2164 SDValue Shamt = Op.getOperand(2); 2165 MVT VT = Subtarget.isGP64bit() ? MVT::i64 : MVT::i32; 2166 2167 // if shamt < (VT.bits): 2168 // lo = (or (shl (shl hi, 1), ~shamt) (srl lo, shamt)) 2169 // if isSRA: 2170 // hi = (sra hi, shamt) 2171 // else: 2172 // hi = (srl hi, shamt) 2173 // else: 2174 // if isSRA: 2175 // lo = (sra hi, shamt[4:0]) 2176 // hi = (sra hi, 31) 2177 // else: 2178 // lo = (srl hi, shamt[4:0]) 2179 // hi = 0 2180 SDValue Not = DAG.getNode(ISD::XOR, DL, MVT::i32, Shamt, 2181 DAG.getConstant(-1, DL, MVT::i32)); 2182 SDValue ShiftLeft1Hi = DAG.getNode(ISD::SHL, DL, VT, Hi, 2183 DAG.getConstant(1, DL, VT)); 2184 SDValue ShiftLeftHi = DAG.getNode(ISD::SHL, DL, VT, ShiftLeft1Hi, Not); 2185 SDValue ShiftRightLo = DAG.getNode(ISD::SRL, DL, VT, Lo, Shamt); 2186 SDValue Or = DAG.getNode(ISD::OR, DL, VT, ShiftLeftHi, ShiftRightLo); 2187 SDValue ShiftRightHi = DAG.getNode(IsSRA ? ISD::SRA : ISD::SRL, 2188 DL, VT, Hi, Shamt); 2189 SDValue Cond = DAG.getNode(ISD::AND, DL, MVT::i32, Shamt, 2190 DAG.getConstant(VT.getSizeInBits(), DL, MVT::i32)); 2191 SDValue Ext = DAG.getNode(ISD::SRA, DL, VT, Hi, 2192 DAG.getConstant(VT.getSizeInBits() - 1, DL, VT)); 2193 Lo = DAG.getNode(ISD::SELECT, DL, VT, Cond, ShiftRightHi, Or); 2194 Hi = DAG.getNode(ISD::SELECT, DL, VT, Cond, 2195 IsSRA ? Ext : DAG.getConstant(0, DL, VT), ShiftRightHi); 2196 2197 SDValue Ops[2] = {Lo, Hi}; 2198 return DAG.getMergeValues(Ops, DL); 2199 } 2200 2201 static SDValue createLoadLR(unsigned Opc, SelectionDAG &DAG, LoadSDNode *LD, 2202 SDValue Chain, SDValue Src, unsigned Offset) { 2203 SDValue Ptr = LD->getBasePtr(); 2204 EVT VT = LD->getValueType(0), MemVT = LD->getMemoryVT(); 2205 EVT BasePtrVT = Ptr.getValueType(); 2206 SDLoc DL(LD); 2207 SDVTList VTList = DAG.getVTList(VT, MVT::Other); 2208 2209 if (Offset) 2210 Ptr = DAG.getNode(ISD::ADD, DL, BasePtrVT, Ptr, 2211 DAG.getConstant(Offset, DL, BasePtrVT)); 2212 2213 SDValue Ops[] = { Chain, Ptr, Src }; 2214 return DAG.getMemIntrinsicNode(Opc, DL, VTList, Ops, MemVT, 2215 LD->getMemOperand()); 2216 } 2217 2218 // Expand an unaligned 32 or 64-bit integer load node. 2219 SDValue MipsTargetLowering::lowerLOAD(SDValue Op, SelectionDAG &DAG) const { 2220 LoadSDNode *LD = cast<LoadSDNode>(Op); 2221 EVT MemVT = LD->getMemoryVT(); 2222 2223 if (Subtarget.systemSupportsUnalignedAccess()) 2224 return Op; 2225 2226 // Return if load is aligned or if MemVT is neither i32 nor i64. 2227 if ((LD->getAlignment() >= MemVT.getSizeInBits() / 8) || 2228 ((MemVT != MVT::i32) && (MemVT != MVT::i64))) 2229 return SDValue(); 2230 2231 bool IsLittle = Subtarget.isLittle(); 2232 EVT VT = Op.getValueType(); 2233 ISD::LoadExtType ExtType = LD->getExtensionType(); 2234 SDValue Chain = LD->getChain(), Undef = DAG.getUNDEF(VT); 2235 2236 assert((VT == MVT::i32) || (VT == MVT::i64)); 2237 2238 // Expand 2239 // (set dst, (i64 (load baseptr))) 2240 // to 2241 // (set tmp, (ldl (add baseptr, 7), undef)) 2242 // (set dst, (ldr baseptr, tmp)) 2243 if ((VT == MVT::i64) && (ExtType == ISD::NON_EXTLOAD)) { 2244 SDValue LDL = createLoadLR(MipsISD::LDL, DAG, LD, Chain, Undef, 2245 IsLittle ? 7 : 0); 2246 return createLoadLR(MipsISD::LDR, DAG, LD, LDL.getValue(1), LDL, 2247 IsLittle ? 0 : 7); 2248 } 2249 2250 SDValue LWL = createLoadLR(MipsISD::LWL, DAG, LD, Chain, Undef, 2251 IsLittle ? 3 : 0); 2252 SDValue LWR = createLoadLR(MipsISD::LWR, DAG, LD, LWL.getValue(1), LWL, 2253 IsLittle ? 0 : 3); 2254 2255 // Expand 2256 // (set dst, (i32 (load baseptr))) or 2257 // (set dst, (i64 (sextload baseptr))) or 2258 // (set dst, (i64 (extload baseptr))) 2259 // to 2260 // (set tmp, (lwl (add baseptr, 3), undef)) 2261 // (set dst, (lwr baseptr, tmp)) 2262 if ((VT == MVT::i32) || (ExtType == ISD::SEXTLOAD) || 2263 (ExtType == ISD::EXTLOAD)) 2264 return LWR; 2265 2266 assert((VT == MVT::i64) && (ExtType == ISD::ZEXTLOAD)); 2267 2268 // Expand 2269 // (set dst, (i64 (zextload baseptr))) 2270 // to 2271 // (set tmp0, (lwl (add baseptr, 3), undef)) 2272 // (set tmp1, (lwr baseptr, tmp0)) 2273 // (set tmp2, (shl tmp1, 32)) 2274 // (set dst, (srl tmp2, 32)) 2275 SDLoc DL(LD); 2276 SDValue Const32 = DAG.getConstant(32, DL, MVT::i32); 2277 SDValue SLL = DAG.getNode(ISD::SHL, DL, MVT::i64, LWR, Const32); 2278 SDValue SRL = DAG.getNode(ISD::SRL, DL, MVT::i64, SLL, Const32); 2279 SDValue Ops[] = { SRL, LWR.getValue(1) }; 2280 return DAG.getMergeValues(Ops, DL); 2281 } 2282 2283 static SDValue createStoreLR(unsigned Opc, SelectionDAG &DAG, StoreSDNode *SD, 2284 SDValue Chain, unsigned Offset) { 2285 SDValue Ptr = SD->getBasePtr(), Value = SD->getValue(); 2286 EVT MemVT = SD->getMemoryVT(), BasePtrVT = Ptr.getValueType(); 2287 SDLoc DL(SD); 2288 SDVTList VTList = DAG.getVTList(MVT::Other); 2289 2290 if (Offset) 2291 Ptr = DAG.getNode(ISD::ADD, DL, BasePtrVT, Ptr, 2292 DAG.getConstant(Offset, DL, BasePtrVT)); 2293 2294 SDValue Ops[] = { Chain, Value, Ptr }; 2295 return DAG.getMemIntrinsicNode(Opc, DL, VTList, Ops, MemVT, 2296 SD->getMemOperand()); 2297 } 2298 2299 // Expand an unaligned 32 or 64-bit integer store node. 2300 static SDValue lowerUnalignedIntStore(StoreSDNode *SD, SelectionDAG &DAG, 2301 bool IsLittle) { 2302 SDValue Value = SD->getValue(), Chain = SD->getChain(); 2303 EVT VT = Value.getValueType(); 2304 2305 // Expand 2306 // (store val, baseptr) or 2307 // (truncstore val, baseptr) 2308 // to 2309 // (swl val, (add baseptr, 3)) 2310 // (swr val, baseptr) 2311 if ((VT == MVT::i32) || SD->isTruncatingStore()) { 2312 SDValue SWL = createStoreLR(MipsISD::SWL, DAG, SD, Chain, 2313 IsLittle ? 3 : 0); 2314 return createStoreLR(MipsISD::SWR, DAG, SD, SWL, IsLittle ? 0 : 3); 2315 } 2316 2317 assert(VT == MVT::i64); 2318 2319 // Expand 2320 // (store val, baseptr) 2321 // to 2322 // (sdl val, (add baseptr, 7)) 2323 // (sdr val, baseptr) 2324 SDValue SDL = createStoreLR(MipsISD::SDL, DAG, SD, Chain, IsLittle ? 7 : 0); 2325 return createStoreLR(MipsISD::SDR, DAG, SD, SDL, IsLittle ? 0 : 7); 2326 } 2327 2328 // Lower (store (fp_to_sint $fp) $ptr) to (store (TruncIntFP $fp), $ptr). 2329 static SDValue lowerFP_TO_SINT_STORE(StoreSDNode *SD, SelectionDAG &DAG) { 2330 SDValue Val = SD->getValue(); 2331 2332 if (Val.getOpcode() != ISD::FP_TO_SINT) 2333 return SDValue(); 2334 2335 EVT FPTy = EVT::getFloatingPointVT(Val.getValueSizeInBits()); 2336 SDValue Tr = DAG.getNode(MipsISD::TruncIntFP, SDLoc(Val), FPTy, 2337 Val.getOperand(0)); 2338 2339 return DAG.getStore(SD->getChain(), SDLoc(SD), Tr, SD->getBasePtr(), 2340 SD->getPointerInfo(), SD->isVolatile(), 2341 SD->isNonTemporal(), SD->getAlignment()); 2342 } 2343 2344 SDValue MipsTargetLowering::lowerSTORE(SDValue Op, SelectionDAG &DAG) const { 2345 StoreSDNode *SD = cast<StoreSDNode>(Op); 2346 EVT MemVT = SD->getMemoryVT(); 2347 2348 // Lower unaligned integer stores. 2349 if (!Subtarget.systemSupportsUnalignedAccess() && 2350 (SD->getAlignment() < MemVT.getSizeInBits() / 8) && 2351 ((MemVT == MVT::i32) || (MemVT == MVT::i64))) 2352 return lowerUnalignedIntStore(SD, DAG, Subtarget.isLittle()); 2353 2354 return lowerFP_TO_SINT_STORE(SD, DAG); 2355 } 2356 2357 SDValue MipsTargetLowering::lowerADD(SDValue Op, SelectionDAG &DAG) const { 2358 if (Op->getOperand(0).getOpcode() != ISD::FRAMEADDR 2359 || cast<ConstantSDNode> 2360 (Op->getOperand(0).getOperand(0))->getZExtValue() != 0 2361 || Op->getOperand(1).getOpcode() != ISD::FRAME_TO_ARGS_OFFSET) 2362 return SDValue(); 2363 2364 // The pattern 2365 // (add (frameaddr 0), (frame_to_args_offset)) 2366 // results from lowering llvm.eh.dwarf.cfa intrinsic. Transform it to 2367 // (add FrameObject, 0) 2368 // where FrameObject is a fixed StackObject with offset 0 which points to 2369 // the old stack pointer. 2370 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo(); 2371 EVT ValTy = Op->getValueType(0); 2372 int FI = MFI->CreateFixedObject(Op.getValueSizeInBits() / 8, 0, false); 2373 SDValue InArgsAddr = DAG.getFrameIndex(FI, ValTy); 2374 SDLoc DL(Op); 2375 return DAG.getNode(ISD::ADD, DL, ValTy, InArgsAddr, 2376 DAG.getConstant(0, DL, ValTy)); 2377 } 2378 2379 SDValue MipsTargetLowering::lowerFP_TO_SINT(SDValue Op, 2380 SelectionDAG &DAG) const { 2381 EVT FPTy = EVT::getFloatingPointVT(Op.getValueSizeInBits()); 2382 SDValue Trunc = DAG.getNode(MipsISD::TruncIntFP, SDLoc(Op), FPTy, 2383 Op.getOperand(0)); 2384 return DAG.getNode(ISD::BITCAST, SDLoc(Op), Op.getValueType(), Trunc); 2385 } 2386 2387 //===----------------------------------------------------------------------===// 2388 // Calling Convention Implementation 2389 //===----------------------------------------------------------------------===// 2390 2391 //===----------------------------------------------------------------------===// 2392 // TODO: Implement a generic logic using tblgen that can support this. 2393 // Mips O32 ABI rules: 2394 // --- 2395 // i32 - Passed in A0, A1, A2, A3 and stack 2396 // f32 - Only passed in f32 registers if no int reg has been used yet to hold 2397 // an argument. Otherwise, passed in A1, A2, A3 and stack. 2398 // f64 - Only passed in two aliased f32 registers if no int reg has been used 2399 // yet to hold an argument. Otherwise, use A2, A3 and stack. If A1 is 2400 // not used, it must be shadowed. If only A3 is available, shadow it and 2401 // go to stack. 2402 // 2403 // For vararg functions, all arguments are passed in A0, A1, A2, A3 and stack. 2404 //===----------------------------------------------------------------------===// 2405 2406 static bool CC_MipsO32(unsigned ValNo, MVT ValVT, MVT LocVT, 2407 CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, 2408 CCState &State, ArrayRef<MCPhysReg> F64Regs) { 2409 const MipsSubtarget &Subtarget = static_cast<const MipsSubtarget &>( 2410 State.getMachineFunction().getSubtarget()); 2411 2412 static const MCPhysReg IntRegs[] = { Mips::A0, Mips::A1, Mips::A2, Mips::A3 }; 2413 static const MCPhysReg F32Regs[] = { Mips::F12, Mips::F14 }; 2414 2415 // Do not process byval args here. 2416 if (ArgFlags.isByVal()) 2417 return true; 2418 2419 // Promote i8 and i16 2420 if (ArgFlags.isInReg() && !Subtarget.isLittle()) { 2421 if (LocVT == MVT::i8 || LocVT == MVT::i16 || LocVT == MVT::i32) { 2422 LocVT = MVT::i32; 2423 if (ArgFlags.isSExt()) 2424 LocInfo = CCValAssign::SExtUpper; 2425 else if (ArgFlags.isZExt()) 2426 LocInfo = CCValAssign::ZExtUpper; 2427 else 2428 LocInfo = CCValAssign::AExtUpper; 2429 } 2430 } 2431 2432 // Promote i8 and i16 2433 if (LocVT == MVT::i8 || LocVT == MVT::i16) { 2434 LocVT = MVT::i32; 2435 if (ArgFlags.isSExt()) 2436 LocInfo = CCValAssign::SExt; 2437 else if (ArgFlags.isZExt()) 2438 LocInfo = CCValAssign::ZExt; 2439 else 2440 LocInfo = CCValAssign::AExt; 2441 } 2442 2443 unsigned Reg; 2444 2445 // f32 and f64 are allocated in A0, A1, A2, A3 when either of the following 2446 // is true: function is vararg, argument is 3rd or higher, there is previous 2447 // argument which is not f32 or f64. 2448 bool AllocateFloatsInIntReg = State.isVarArg() || ValNo > 1 || 2449 State.getFirstUnallocated(F32Regs) != ValNo; 2450 unsigned OrigAlign = ArgFlags.getOrigAlign(); 2451 bool isI64 = (ValVT == MVT::i32 && OrigAlign == 8); 2452 2453 if (ValVT == MVT::i32 || (ValVT == MVT::f32 && AllocateFloatsInIntReg)) { 2454 Reg = State.AllocateReg(IntRegs); 2455 // If this is the first part of an i64 arg, 2456 // the allocated register must be either A0 or A2. 2457 if (isI64 && (Reg == Mips::A1 || Reg == Mips::A3)) 2458 Reg = State.AllocateReg(IntRegs); 2459 LocVT = MVT::i32; 2460 } else if (ValVT == MVT::f64 && AllocateFloatsInIntReg) { 2461 // Allocate int register and shadow next int register. If first 2462 // available register is Mips::A1 or Mips::A3, shadow it too. 2463 Reg = State.AllocateReg(IntRegs); 2464 if (Reg == Mips::A1 || Reg == Mips::A3) 2465 Reg = State.AllocateReg(IntRegs); 2466 State.AllocateReg(IntRegs); 2467 LocVT = MVT::i32; 2468 } else if (ValVT.isFloatingPoint() && !AllocateFloatsInIntReg) { 2469 // we are guaranteed to find an available float register 2470 if (ValVT == MVT::f32) { 2471 Reg = State.AllocateReg(F32Regs); 2472 // Shadow int register 2473 State.AllocateReg(IntRegs); 2474 } else { 2475 Reg = State.AllocateReg(F64Regs); 2476 // Shadow int registers 2477 unsigned Reg2 = State.AllocateReg(IntRegs); 2478 if (Reg2 == Mips::A1 || Reg2 == Mips::A3) 2479 State.AllocateReg(IntRegs); 2480 State.AllocateReg(IntRegs); 2481 } 2482 } else 2483 llvm_unreachable("Cannot handle this ValVT."); 2484 2485 if (!Reg) { 2486 unsigned Offset = State.AllocateStack(ValVT.getSizeInBits() >> 3, 2487 OrigAlign); 2488 State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo)); 2489 } else 2490 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); 2491 2492 return false; 2493 } 2494 2495 static bool CC_MipsO32_FP32(unsigned ValNo, MVT ValVT, 2496 MVT LocVT, CCValAssign::LocInfo LocInfo, 2497 ISD::ArgFlagsTy ArgFlags, CCState &State) { 2498 static const MCPhysReg F64Regs[] = { Mips::D6, Mips::D7 }; 2499 2500 return CC_MipsO32(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State, F64Regs); 2501 } 2502 2503 static bool CC_MipsO32_FP64(unsigned ValNo, MVT ValVT, 2504 MVT LocVT, CCValAssign::LocInfo LocInfo, 2505 ISD::ArgFlagsTy ArgFlags, CCState &State) { 2506 static const MCPhysReg F64Regs[] = { Mips::D12_64, Mips::D14_64 }; 2507 2508 return CC_MipsO32(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State, F64Regs); 2509 } 2510 2511 static bool CC_MipsO32(unsigned ValNo, MVT ValVT, MVT LocVT, 2512 CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, 2513 CCState &State) LLVM_ATTRIBUTE_UNUSED; 2514 2515 #include "MipsGenCallingConv.inc" 2516 2517 //===----------------------------------------------------------------------===// 2518 // Call Calling Convention Implementation 2519 //===----------------------------------------------------------------------===// 2520 2521 // Return next O32 integer argument register. 2522 static unsigned getNextIntArgReg(unsigned Reg) { 2523 assert((Reg == Mips::A0) || (Reg == Mips::A2)); 2524 return (Reg == Mips::A0) ? Mips::A1 : Mips::A3; 2525 } 2526 2527 SDValue 2528 MipsTargetLowering::passArgOnStack(SDValue StackPtr, unsigned Offset, 2529 SDValue Chain, SDValue Arg, SDLoc DL, 2530 bool IsTailCall, SelectionDAG &DAG) const { 2531 if (!IsTailCall) { 2532 SDValue PtrOff = 2533 DAG.getNode(ISD::ADD, DL, getPointerTy(DAG.getDataLayout()), StackPtr, 2534 DAG.getIntPtrConstant(Offset, DL)); 2535 return DAG.getStore(Chain, DL, Arg, PtrOff, MachinePointerInfo(), false, 2536 false, 0); 2537 } 2538 2539 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo(); 2540 int FI = MFI->CreateFixedObject(Arg.getValueSizeInBits() / 8, Offset, false); 2541 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy(DAG.getDataLayout())); 2542 return DAG.getStore(Chain, DL, Arg, FIN, MachinePointerInfo(), 2543 /*isVolatile=*/ true, false, 0); 2544 } 2545 2546 void MipsTargetLowering:: 2547 getOpndList(SmallVectorImpl<SDValue> &Ops, 2548 std::deque< std::pair<unsigned, SDValue> > &RegsToPass, 2549 bool IsPICCall, bool GlobalOrExternal, bool InternalLinkage, 2550 bool IsCallReloc, CallLoweringInfo &CLI, SDValue Callee, 2551 SDValue Chain) const { 2552 // Insert node "GP copy globalreg" before call to function. 2553 // 2554 // R_MIPS_CALL* operators (emitted when non-internal functions are called 2555 // in PIC mode) allow symbols to be resolved via lazy binding. 2556 // The lazy binding stub requires GP to point to the GOT. 2557 // Note that we don't need GP to point to the GOT for indirect calls 2558 // (when R_MIPS_CALL* is not used for the call) because Mips linker generates 2559 // lazy binding stub for a function only when R_MIPS_CALL* are the only relocs 2560 // used for the function (that is, Mips linker doesn't generate lazy binding 2561 // stub for a function whose address is taken in the program). 2562 if (IsPICCall && !InternalLinkage && IsCallReloc) { 2563 unsigned GPReg = ABI.IsN64() ? Mips::GP_64 : Mips::GP; 2564 EVT Ty = ABI.IsN64() ? MVT::i64 : MVT::i32; 2565 RegsToPass.push_back(std::make_pair(GPReg, getGlobalReg(CLI.DAG, Ty))); 2566 } 2567 2568 // Build a sequence of copy-to-reg nodes chained together with token 2569 // chain and flag operands which copy the outgoing args into registers. 2570 // The InFlag in necessary since all emitted instructions must be 2571 // stuck together. 2572 SDValue InFlag; 2573 2574 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) { 2575 Chain = CLI.DAG.getCopyToReg(Chain, CLI.DL, RegsToPass[i].first, 2576 RegsToPass[i].second, InFlag); 2577 InFlag = Chain.getValue(1); 2578 } 2579 2580 // Add argument registers to the end of the list so that they are 2581 // known live into the call. 2582 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) 2583 Ops.push_back(CLI.DAG.getRegister(RegsToPass[i].first, 2584 RegsToPass[i].second.getValueType())); 2585 2586 // Add a register mask operand representing the call-preserved registers. 2587 const TargetRegisterInfo *TRI = Subtarget.getRegisterInfo(); 2588 const uint32_t *Mask = 2589 TRI->getCallPreservedMask(CLI.DAG.getMachineFunction(), CLI.CallConv); 2590 assert(Mask && "Missing call preserved mask for calling convention"); 2591 if (Subtarget.inMips16HardFloat()) { 2592 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(CLI.Callee)) { 2593 llvm::StringRef Sym = G->getGlobal()->getName(); 2594 Function *F = G->getGlobal()->getParent()->getFunction(Sym); 2595 if (F && F->hasFnAttribute("__Mips16RetHelper")) { 2596 Mask = MipsRegisterInfo::getMips16RetHelperMask(); 2597 } 2598 } 2599 } 2600 Ops.push_back(CLI.DAG.getRegisterMask(Mask)); 2601 2602 if (InFlag.getNode()) 2603 Ops.push_back(InFlag); 2604 } 2605 2606 /// LowerCall - functions arguments are copied from virtual regs to 2607 /// (physical regs)/(stack frame), CALLSEQ_START and CALLSEQ_END are emitted. 2608 SDValue 2609 MipsTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI, 2610 SmallVectorImpl<SDValue> &InVals) const { 2611 SelectionDAG &DAG = CLI.DAG; 2612 SDLoc DL = CLI.DL; 2613 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs; 2614 SmallVectorImpl<SDValue> &OutVals = CLI.OutVals; 2615 SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins; 2616 SDValue Chain = CLI.Chain; 2617 SDValue Callee = CLI.Callee; 2618 bool &IsTailCall = CLI.IsTailCall; 2619 CallingConv::ID CallConv = CLI.CallConv; 2620 bool IsVarArg = CLI.IsVarArg; 2621 2622 MachineFunction &MF = DAG.getMachineFunction(); 2623 MachineFrameInfo *MFI = MF.getFrameInfo(); 2624 const TargetFrameLowering *TFL = Subtarget.getFrameLowering(); 2625 MipsFunctionInfo *FuncInfo = MF.getInfo<MipsFunctionInfo>(); 2626 bool IsPIC = getTargetMachine().getRelocationModel() == Reloc::PIC_; 2627 2628 // Analyze operands of the call, assigning locations to each operand. 2629 SmallVector<CCValAssign, 16> ArgLocs; 2630 MipsCCState CCInfo( 2631 CallConv, IsVarArg, DAG.getMachineFunction(), ArgLocs, *DAG.getContext(), 2632 MipsCCState::getSpecialCallingConvForCallee(Callee.getNode(), Subtarget)); 2633 2634 // Allocate the reserved argument area. It seems strange to do this from the 2635 // caller side but removing it breaks the frame size calculation. 2636 CCInfo.AllocateStack(ABI.GetCalleeAllocdArgSizeInBytes(CallConv), 1); 2637 2638 CCInfo.AnalyzeCallOperands(Outs, CC_Mips, CLI.getArgs(), Callee.getNode()); 2639 2640 // Get a count of how many bytes are to be pushed on the stack. 2641 unsigned NextStackOffset = CCInfo.getNextStackOffset(); 2642 2643 // Check if it's really possible to do a tail call. 2644 if (IsTailCall) 2645 IsTailCall = isEligibleForTailCallOptimization( 2646 CCInfo, NextStackOffset, *MF.getInfo<MipsFunctionInfo>()); 2647 2648 if (!IsTailCall && CLI.CS && CLI.CS->isMustTailCall()) 2649 report_fatal_error("failed to perform tail call elimination on a call " 2650 "site marked musttail"); 2651 2652 if (IsTailCall) 2653 ++NumTailCalls; 2654 2655 // Chain is the output chain of the last Load/Store or CopyToReg node. 2656 // ByValChain is the output chain of the last Memcpy node created for copying 2657 // byval arguments to the stack. 2658 unsigned StackAlignment = TFL->getStackAlignment(); 2659 NextStackOffset = alignTo(NextStackOffset, StackAlignment); 2660 SDValue NextStackOffsetVal = DAG.getIntPtrConstant(NextStackOffset, DL, true); 2661 2662 if (!IsTailCall) 2663 Chain = DAG.getCALLSEQ_START(Chain, NextStackOffsetVal, DL); 2664 2665 SDValue StackPtr = 2666 DAG.getCopyFromReg(Chain, DL, ABI.IsN64() ? Mips::SP_64 : Mips::SP, 2667 getPointerTy(DAG.getDataLayout())); 2668 2669 // With EABI is it possible to have 16 args on registers. 2670 std::deque< std::pair<unsigned, SDValue> > RegsToPass; 2671 SmallVector<SDValue, 8> MemOpChains; 2672 2673 CCInfo.rewindByValRegsInfo(); 2674 2675 // Walk the register/memloc assignments, inserting copies/loads. 2676 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { 2677 SDValue Arg = OutVals[i]; 2678 CCValAssign &VA = ArgLocs[i]; 2679 MVT ValVT = VA.getValVT(), LocVT = VA.getLocVT(); 2680 ISD::ArgFlagsTy Flags = Outs[i].Flags; 2681 bool UseUpperBits = false; 2682 2683 // ByVal Arg. 2684 if (Flags.isByVal()) { 2685 unsigned FirstByValReg, LastByValReg; 2686 unsigned ByValIdx = CCInfo.getInRegsParamsProcessed(); 2687 CCInfo.getInRegsParamInfo(ByValIdx, FirstByValReg, LastByValReg); 2688 2689 assert(Flags.getByValSize() && 2690 "ByVal args of size 0 should have been ignored by front-end."); 2691 assert(ByValIdx < CCInfo.getInRegsParamsCount()); 2692 assert(!IsTailCall && 2693 "Do not tail-call optimize if there is a byval argument."); 2694 passByValArg(Chain, DL, RegsToPass, MemOpChains, StackPtr, MFI, DAG, Arg, 2695 FirstByValReg, LastByValReg, Flags, Subtarget.isLittle(), 2696 VA); 2697 CCInfo.nextInRegsParam(); 2698 continue; 2699 } 2700 2701 // Promote the value if needed. 2702 switch (VA.getLocInfo()) { 2703 default: 2704 llvm_unreachable("Unknown loc info!"); 2705 case CCValAssign::Full: 2706 if (VA.isRegLoc()) { 2707 if ((ValVT == MVT::f32 && LocVT == MVT::i32) || 2708 (ValVT == MVT::f64 && LocVT == MVT::i64) || 2709 (ValVT == MVT::i64 && LocVT == MVT::f64)) 2710 Arg = DAG.getNode(ISD::BITCAST, DL, LocVT, Arg); 2711 else if (ValVT == MVT::f64 && LocVT == MVT::i32) { 2712 SDValue Lo = DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32, 2713 Arg, DAG.getConstant(0, DL, MVT::i32)); 2714 SDValue Hi = DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32, 2715 Arg, DAG.getConstant(1, DL, MVT::i32)); 2716 if (!Subtarget.isLittle()) 2717 std::swap(Lo, Hi); 2718 unsigned LocRegLo = VA.getLocReg(); 2719 unsigned LocRegHigh = getNextIntArgReg(LocRegLo); 2720 RegsToPass.push_back(std::make_pair(LocRegLo, Lo)); 2721 RegsToPass.push_back(std::make_pair(LocRegHigh, Hi)); 2722 continue; 2723 } 2724 } 2725 break; 2726 case CCValAssign::BCvt: 2727 Arg = DAG.getNode(ISD::BITCAST, DL, LocVT, Arg); 2728 break; 2729 case CCValAssign::SExtUpper: 2730 UseUpperBits = true; 2731 // Fallthrough 2732 case CCValAssign::SExt: 2733 Arg = DAG.getNode(ISD::SIGN_EXTEND, DL, LocVT, Arg); 2734 break; 2735 case CCValAssign::ZExtUpper: 2736 UseUpperBits = true; 2737 // Fallthrough 2738 case CCValAssign::ZExt: 2739 Arg = DAG.getNode(ISD::ZERO_EXTEND, DL, LocVT, Arg); 2740 break; 2741 case CCValAssign::AExtUpper: 2742 UseUpperBits = true; 2743 // Fallthrough 2744 case CCValAssign::AExt: 2745 Arg = DAG.getNode(ISD::ANY_EXTEND, DL, LocVT, Arg); 2746 break; 2747 } 2748 2749 if (UseUpperBits) { 2750 unsigned ValSizeInBits = Outs[i].ArgVT.getSizeInBits(); 2751 unsigned LocSizeInBits = VA.getLocVT().getSizeInBits(); 2752 Arg = DAG.getNode( 2753 ISD::SHL, DL, VA.getLocVT(), Arg, 2754 DAG.getConstant(LocSizeInBits - ValSizeInBits, DL, VA.getLocVT())); 2755 } 2756 2757 // Arguments that can be passed on register must be kept at 2758 // RegsToPass vector 2759 if (VA.isRegLoc()) { 2760 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg)); 2761 continue; 2762 } 2763 2764 // Register can't get to this point... 2765 assert(VA.isMemLoc()); 2766 2767 // emit ISD::STORE whichs stores the 2768 // parameter value to a stack Location 2769 MemOpChains.push_back(passArgOnStack(StackPtr, VA.getLocMemOffset(), 2770 Chain, Arg, DL, IsTailCall, DAG)); 2771 } 2772 2773 // Transform all store nodes into one single node because all store 2774 // nodes are independent of each other. 2775 if (!MemOpChains.empty()) 2776 Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, MemOpChains); 2777 2778 // If the callee is a GlobalAddress/ExternalSymbol node (quite common, every 2779 // direct call is) turn it into a TargetGlobalAddress/TargetExternalSymbol 2780 // node so that legalize doesn't hack it. 2781 bool IsPICCall = (ABI.IsN64() || IsPIC); // true if calls are translated to 2782 // jalr $25 2783 bool GlobalOrExternal = false, InternalLinkage = false, IsCallReloc = false; 2784 SDValue CalleeLo; 2785 EVT Ty = Callee.getValueType(); 2786 2787 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) { 2788 if (IsPICCall) { 2789 const GlobalValue *Val = G->getGlobal(); 2790 InternalLinkage = Val->hasInternalLinkage(); 2791 2792 if (InternalLinkage) 2793 Callee = getAddrLocal(G, DL, Ty, DAG, ABI.IsN32() || ABI.IsN64()); 2794 else if (LargeGOT) { 2795 Callee = getAddrGlobalLargeGOT(G, DL, Ty, DAG, MipsII::MO_CALL_HI16, 2796 MipsII::MO_CALL_LO16, Chain, 2797 FuncInfo->callPtrInfo(Val)); 2798 IsCallReloc = true; 2799 } else { 2800 Callee = getAddrGlobal(G, DL, Ty, DAG, MipsII::MO_GOT_CALL, Chain, 2801 FuncInfo->callPtrInfo(Val)); 2802 IsCallReloc = true; 2803 } 2804 } else 2805 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), DL, 2806 getPointerTy(DAG.getDataLayout()), 0, 2807 MipsII::MO_NO_FLAG); 2808 GlobalOrExternal = true; 2809 } 2810 else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) { 2811 const char *Sym = S->getSymbol(); 2812 2813 if (!ABI.IsN64() && !IsPIC) // !N64 && static 2814 Callee = DAG.getTargetExternalSymbol( 2815 Sym, getPointerTy(DAG.getDataLayout()), MipsII::MO_NO_FLAG); 2816 else if (LargeGOT) { 2817 Callee = getAddrGlobalLargeGOT(S, DL, Ty, DAG, MipsII::MO_CALL_HI16, 2818 MipsII::MO_CALL_LO16, Chain, 2819 FuncInfo->callPtrInfo(Sym)); 2820 IsCallReloc = true; 2821 } else { // N64 || PIC 2822 Callee = getAddrGlobal(S, DL, Ty, DAG, MipsII::MO_GOT_CALL, Chain, 2823 FuncInfo->callPtrInfo(Sym)); 2824 IsCallReloc = true; 2825 } 2826 2827 GlobalOrExternal = true; 2828 } 2829 2830 SmallVector<SDValue, 8> Ops(1, Chain); 2831 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue); 2832 2833 getOpndList(Ops, RegsToPass, IsPICCall, GlobalOrExternal, InternalLinkage, 2834 IsCallReloc, CLI, Callee, Chain); 2835 2836 if (IsTailCall) 2837 return DAG.getNode(MipsISD::TailCall, DL, MVT::Other, Ops); 2838 2839 Chain = DAG.getNode(MipsISD::JmpLink, DL, NodeTys, Ops); 2840 SDValue InFlag = Chain.getValue(1); 2841 2842 // Create the CALLSEQ_END node. 2843 Chain = DAG.getCALLSEQ_END(Chain, NextStackOffsetVal, 2844 DAG.getIntPtrConstant(0, DL, true), InFlag, DL); 2845 InFlag = Chain.getValue(1); 2846 2847 // Handle result values, copying them out of physregs into vregs that we 2848 // return. 2849 return LowerCallResult(Chain, InFlag, CallConv, IsVarArg, Ins, DL, DAG, 2850 InVals, CLI); 2851 } 2852 2853 /// LowerCallResult - Lower the result values of a call into the 2854 /// appropriate copies out of appropriate physical registers. 2855 SDValue MipsTargetLowering::LowerCallResult( 2856 SDValue Chain, SDValue InFlag, CallingConv::ID CallConv, bool IsVarArg, 2857 const SmallVectorImpl<ISD::InputArg> &Ins, SDLoc DL, SelectionDAG &DAG, 2858 SmallVectorImpl<SDValue> &InVals, 2859 TargetLowering::CallLoweringInfo &CLI) const { 2860 // Assign locations to each value returned by this call. 2861 SmallVector<CCValAssign, 16> RVLocs; 2862 MipsCCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), RVLocs, 2863 *DAG.getContext()); 2864 CCInfo.AnalyzeCallResult(Ins, RetCC_Mips, CLI); 2865 2866 // Copy all of the result registers out of their specified physreg. 2867 for (unsigned i = 0; i != RVLocs.size(); ++i) { 2868 CCValAssign &VA = RVLocs[i]; 2869 assert(VA.isRegLoc() && "Can only return in registers!"); 2870 2871 SDValue Val = DAG.getCopyFromReg(Chain, DL, RVLocs[i].getLocReg(), 2872 RVLocs[i].getLocVT(), InFlag); 2873 Chain = Val.getValue(1); 2874 InFlag = Val.getValue(2); 2875 2876 if (VA.isUpperBitsInLoc()) { 2877 unsigned ValSizeInBits = Ins[i].ArgVT.getSizeInBits(); 2878 unsigned LocSizeInBits = VA.getLocVT().getSizeInBits(); 2879 unsigned Shift = 2880 VA.getLocInfo() == CCValAssign::ZExtUpper ? ISD::SRL : ISD::SRA; 2881 Val = DAG.getNode( 2882 Shift, DL, VA.getLocVT(), Val, 2883 DAG.getConstant(LocSizeInBits - ValSizeInBits, DL, VA.getLocVT())); 2884 } 2885 2886 switch (VA.getLocInfo()) { 2887 default: 2888 llvm_unreachable("Unknown loc info!"); 2889 case CCValAssign::Full: 2890 break; 2891 case CCValAssign::BCvt: 2892 Val = DAG.getNode(ISD::BITCAST, DL, VA.getValVT(), Val); 2893 break; 2894 case CCValAssign::AExt: 2895 case CCValAssign::AExtUpper: 2896 Val = DAG.getNode(ISD::TRUNCATE, DL, VA.getValVT(), Val); 2897 break; 2898 case CCValAssign::ZExt: 2899 case CCValAssign::ZExtUpper: 2900 Val = DAG.getNode(ISD::AssertZext, DL, VA.getLocVT(), Val, 2901 DAG.getValueType(VA.getValVT())); 2902 Val = DAG.getNode(ISD::TRUNCATE, DL, VA.getValVT(), Val); 2903 break; 2904 case CCValAssign::SExt: 2905 case CCValAssign::SExtUpper: 2906 Val = DAG.getNode(ISD::AssertSext, DL, VA.getLocVT(), Val, 2907 DAG.getValueType(VA.getValVT())); 2908 Val = DAG.getNode(ISD::TRUNCATE, DL, VA.getValVT(), Val); 2909 break; 2910 } 2911 2912 InVals.push_back(Val); 2913 } 2914 2915 return Chain; 2916 } 2917 2918 static SDValue UnpackFromArgumentSlot(SDValue Val, const CCValAssign &VA, 2919 EVT ArgVT, SDLoc DL, SelectionDAG &DAG) { 2920 MVT LocVT = VA.getLocVT(); 2921 EVT ValVT = VA.getValVT(); 2922 2923 // Shift into the upper bits if necessary. 2924 switch (VA.getLocInfo()) { 2925 default: 2926 break; 2927 case CCValAssign::AExtUpper: 2928 case CCValAssign::SExtUpper: 2929 case CCValAssign::ZExtUpper: { 2930 unsigned ValSizeInBits = ArgVT.getSizeInBits(); 2931 unsigned LocSizeInBits = VA.getLocVT().getSizeInBits(); 2932 unsigned Opcode = 2933 VA.getLocInfo() == CCValAssign::ZExtUpper ? ISD::SRL : ISD::SRA; 2934 Val = DAG.getNode( 2935 Opcode, DL, VA.getLocVT(), Val, 2936 DAG.getConstant(LocSizeInBits - ValSizeInBits, DL, VA.getLocVT())); 2937 break; 2938 } 2939 } 2940 2941 // If this is an value smaller than the argument slot size (32-bit for O32, 2942 // 64-bit for N32/N64), it has been promoted in some way to the argument slot 2943 // size. Extract the value and insert any appropriate assertions regarding 2944 // sign/zero extension. 2945 switch (VA.getLocInfo()) { 2946 default: 2947 llvm_unreachable("Unknown loc info!"); 2948 case CCValAssign::Full: 2949 break; 2950 case CCValAssign::AExtUpper: 2951 case CCValAssign::AExt: 2952 Val = DAG.getNode(ISD::TRUNCATE, DL, ValVT, Val); 2953 break; 2954 case CCValAssign::SExtUpper: 2955 case CCValAssign::SExt: 2956 Val = DAG.getNode(ISD::AssertSext, DL, LocVT, Val, DAG.getValueType(ValVT)); 2957 Val = DAG.getNode(ISD::TRUNCATE, DL, ValVT, Val); 2958 break; 2959 case CCValAssign::ZExtUpper: 2960 case CCValAssign::ZExt: 2961 Val = DAG.getNode(ISD::AssertZext, DL, LocVT, Val, DAG.getValueType(ValVT)); 2962 Val = DAG.getNode(ISD::TRUNCATE, DL, ValVT, Val); 2963 break; 2964 case CCValAssign::BCvt: 2965 Val = DAG.getNode(ISD::BITCAST, DL, ValVT, Val); 2966 break; 2967 } 2968 2969 return Val; 2970 } 2971 2972 //===----------------------------------------------------------------------===// 2973 // Formal Arguments Calling Convention Implementation 2974 //===----------------------------------------------------------------------===// 2975 /// LowerFormalArguments - transform physical registers into virtual registers 2976 /// and generate load operations for arguments places on the stack. 2977 SDValue 2978 MipsTargetLowering::LowerFormalArguments(SDValue Chain, 2979 CallingConv::ID CallConv, 2980 bool IsVarArg, 2981 const SmallVectorImpl<ISD::InputArg> &Ins, 2982 SDLoc DL, SelectionDAG &DAG, 2983 SmallVectorImpl<SDValue> &InVals) 2984 const { 2985 MachineFunction &MF = DAG.getMachineFunction(); 2986 MachineFrameInfo *MFI = MF.getFrameInfo(); 2987 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>(); 2988 2989 MipsFI->setVarArgsFrameIndex(0); 2990 2991 // Used with vargs to acumulate store chains. 2992 std::vector<SDValue> OutChains; 2993 2994 // Assign locations to all of the incoming arguments. 2995 SmallVector<CCValAssign, 16> ArgLocs; 2996 MipsCCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), ArgLocs, 2997 *DAG.getContext()); 2998 CCInfo.AllocateStack(ABI.GetCalleeAllocdArgSizeInBytes(CallConv), 1); 2999 const Function *Func = DAG.getMachineFunction().getFunction(); 3000 Function::const_arg_iterator FuncArg = Func->arg_begin(); 3001 3002 if (Func->hasFnAttribute("interrupt") && !Func->arg_empty()) 3003 report_fatal_error( 3004 "Functions with the interrupt attribute cannot have arguments!"); 3005 3006 CCInfo.AnalyzeFormalArguments(Ins, CC_Mips_FixedArg); 3007 MipsFI->setFormalArgInfo(CCInfo.getNextStackOffset(), 3008 CCInfo.getInRegsParamsCount() > 0); 3009 3010 unsigned CurArgIdx = 0; 3011 CCInfo.rewindByValRegsInfo(); 3012 3013 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { 3014 CCValAssign &VA = ArgLocs[i]; 3015 if (Ins[i].isOrigArg()) { 3016 std::advance(FuncArg, Ins[i].getOrigArgIndex() - CurArgIdx); 3017 CurArgIdx = Ins[i].getOrigArgIndex(); 3018 } 3019 EVT ValVT = VA.getValVT(); 3020 ISD::ArgFlagsTy Flags = Ins[i].Flags; 3021 bool IsRegLoc = VA.isRegLoc(); 3022 3023 if (Flags.isByVal()) { 3024 assert(Ins[i].isOrigArg() && "Byval arguments cannot be implicit"); 3025 unsigned FirstByValReg, LastByValReg; 3026 unsigned ByValIdx = CCInfo.getInRegsParamsProcessed(); 3027 CCInfo.getInRegsParamInfo(ByValIdx, FirstByValReg, LastByValReg); 3028 3029 assert(Flags.getByValSize() && 3030 "ByVal args of size 0 should have been ignored by front-end."); 3031 assert(ByValIdx < CCInfo.getInRegsParamsCount()); 3032 copyByValRegs(Chain, DL, OutChains, DAG, Flags, InVals, &*FuncArg, 3033 FirstByValReg, LastByValReg, VA, CCInfo); 3034 CCInfo.nextInRegsParam(); 3035 continue; 3036 } 3037 3038 // Arguments stored on registers 3039 if (IsRegLoc) { 3040 MVT RegVT = VA.getLocVT(); 3041 unsigned ArgReg = VA.getLocReg(); 3042 const TargetRegisterClass *RC = getRegClassFor(RegVT); 3043 3044 // Transform the arguments stored on 3045 // physical registers into virtual ones 3046 unsigned Reg = addLiveIn(DAG.getMachineFunction(), ArgReg, RC); 3047 SDValue ArgValue = DAG.getCopyFromReg(Chain, DL, Reg, RegVT); 3048 3049 ArgValue = UnpackFromArgumentSlot(ArgValue, VA, Ins[i].ArgVT, DL, DAG); 3050 3051 // Handle floating point arguments passed in integer registers and 3052 // long double arguments passed in floating point registers. 3053 if ((RegVT == MVT::i32 && ValVT == MVT::f32) || 3054 (RegVT == MVT::i64 && ValVT == MVT::f64) || 3055 (RegVT == MVT::f64 && ValVT == MVT::i64)) 3056 ArgValue = DAG.getNode(ISD::BITCAST, DL, ValVT, ArgValue); 3057 else if (ABI.IsO32() && RegVT == MVT::i32 && 3058 ValVT == MVT::f64) { 3059 unsigned Reg2 = addLiveIn(DAG.getMachineFunction(), 3060 getNextIntArgReg(ArgReg), RC); 3061 SDValue ArgValue2 = DAG.getCopyFromReg(Chain, DL, Reg2, RegVT); 3062 if (!Subtarget.isLittle()) 3063 std::swap(ArgValue, ArgValue2); 3064 ArgValue = DAG.getNode(MipsISD::BuildPairF64, DL, MVT::f64, 3065 ArgValue, ArgValue2); 3066 } 3067 3068 InVals.push_back(ArgValue); 3069 } else { // VA.isRegLoc() 3070 MVT LocVT = VA.getLocVT(); 3071 3072 if (ABI.IsO32()) { 3073 // We ought to be able to use LocVT directly but O32 sets it to i32 3074 // when allocating floating point values to integer registers. 3075 // This shouldn't influence how we load the value into registers unless 3076 // we are targeting softfloat. 3077 if (VA.getValVT().isFloatingPoint() && !Subtarget.useSoftFloat()) 3078 LocVT = VA.getValVT(); 3079 } 3080 3081 // sanity check 3082 assert(VA.isMemLoc()); 3083 3084 // The stack pointer offset is relative to the caller stack frame. 3085 int FI = MFI->CreateFixedObject(LocVT.getSizeInBits() / 8, 3086 VA.getLocMemOffset(), true); 3087 3088 // Create load nodes to retrieve arguments from the stack 3089 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy(DAG.getDataLayout())); 3090 SDValue ArgValue = DAG.getLoad( 3091 LocVT, DL, Chain, FIN, 3092 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), FI), 3093 false, false, false, 0); 3094 OutChains.push_back(ArgValue.getValue(1)); 3095 3096 ArgValue = UnpackFromArgumentSlot(ArgValue, VA, Ins[i].ArgVT, DL, DAG); 3097 3098 InVals.push_back(ArgValue); 3099 } 3100 } 3101 3102 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { 3103 // The mips ABIs for returning structs by value requires that we copy 3104 // the sret argument into $v0 for the return. Save the argument into 3105 // a virtual register so that we can access it from the return points. 3106 if (Ins[i].Flags.isSRet()) { 3107 unsigned Reg = MipsFI->getSRetReturnReg(); 3108 if (!Reg) { 3109 Reg = MF.getRegInfo().createVirtualRegister( 3110 getRegClassFor(ABI.IsN64() ? MVT::i64 : MVT::i32)); 3111 MipsFI->setSRetReturnReg(Reg); 3112 } 3113 SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), DL, Reg, InVals[i]); 3114 Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, Copy, Chain); 3115 break; 3116 } 3117 } 3118 3119 if (IsVarArg) 3120 writeVarArgRegs(OutChains, Chain, DL, DAG, CCInfo); 3121 3122 // All stores are grouped in one node to allow the matching between 3123 // the size of Ins and InVals. This only happens when on varg functions 3124 if (!OutChains.empty()) { 3125 OutChains.push_back(Chain); 3126 Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, OutChains); 3127 } 3128 3129 return Chain; 3130 } 3131 3132 //===----------------------------------------------------------------------===// 3133 // Return Value Calling Convention Implementation 3134 //===----------------------------------------------------------------------===// 3135 3136 bool 3137 MipsTargetLowering::CanLowerReturn(CallingConv::ID CallConv, 3138 MachineFunction &MF, bool IsVarArg, 3139 const SmallVectorImpl<ISD::OutputArg> &Outs, 3140 LLVMContext &Context) const { 3141 SmallVector<CCValAssign, 16> RVLocs; 3142 MipsCCState CCInfo(CallConv, IsVarArg, MF, RVLocs, Context); 3143 return CCInfo.CheckReturn(Outs, RetCC_Mips); 3144 } 3145 3146 bool 3147 MipsTargetLowering::shouldSignExtendTypeInLibCall(EVT Type, bool IsSigned) const { 3148 if (Subtarget.hasMips3() && Subtarget.useSoftFloat()) { 3149 if (Type == MVT::i32) 3150 return true; 3151 } 3152 return IsSigned; 3153 } 3154 3155 SDValue 3156 MipsTargetLowering::LowerInterruptReturn(SmallVectorImpl<SDValue> &RetOps, 3157 SDLoc DL, SelectionDAG &DAG) const { 3158 3159 MachineFunction &MF = DAG.getMachineFunction(); 3160 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>(); 3161 3162 MipsFI->setISR(); 3163 3164 return DAG.getNode(MipsISD::ERet, DL, MVT::Other, RetOps); 3165 } 3166 3167 SDValue 3168 MipsTargetLowering::LowerReturn(SDValue Chain, CallingConv::ID CallConv, 3169 bool IsVarArg, 3170 const SmallVectorImpl<ISD::OutputArg> &Outs, 3171 const SmallVectorImpl<SDValue> &OutVals, 3172 SDLoc DL, SelectionDAG &DAG) const { 3173 // CCValAssign - represent the assignment of 3174 // the return value to a location 3175 SmallVector<CCValAssign, 16> RVLocs; 3176 MachineFunction &MF = DAG.getMachineFunction(); 3177 3178 // CCState - Info about the registers and stack slot. 3179 MipsCCState CCInfo(CallConv, IsVarArg, MF, RVLocs, *DAG.getContext()); 3180 3181 // Analyze return values. 3182 CCInfo.AnalyzeReturn(Outs, RetCC_Mips); 3183 3184 SDValue Flag; 3185 SmallVector<SDValue, 4> RetOps(1, Chain); 3186 3187 // Copy the result values into the output registers. 3188 for (unsigned i = 0; i != RVLocs.size(); ++i) { 3189 SDValue Val = OutVals[i]; 3190 CCValAssign &VA = RVLocs[i]; 3191 assert(VA.isRegLoc() && "Can only return in registers!"); 3192 bool UseUpperBits = false; 3193 3194 switch (VA.getLocInfo()) { 3195 default: 3196 llvm_unreachable("Unknown loc info!"); 3197 case CCValAssign::Full: 3198 break; 3199 case CCValAssign::BCvt: 3200 Val = DAG.getNode(ISD::BITCAST, DL, VA.getLocVT(), Val); 3201 break; 3202 case CCValAssign::AExtUpper: 3203 UseUpperBits = true; 3204 // Fallthrough 3205 case CCValAssign::AExt: 3206 Val = DAG.getNode(ISD::ANY_EXTEND, DL, VA.getLocVT(), Val); 3207 break; 3208 case CCValAssign::ZExtUpper: 3209 UseUpperBits = true; 3210 // Fallthrough 3211 case CCValAssign::ZExt: 3212 Val = DAG.getNode(ISD::ZERO_EXTEND, DL, VA.getLocVT(), Val); 3213 break; 3214 case CCValAssign::SExtUpper: 3215 UseUpperBits = true; 3216 // Fallthrough 3217 case CCValAssign::SExt: 3218 Val = DAG.getNode(ISD::SIGN_EXTEND, DL, VA.getLocVT(), Val); 3219 break; 3220 } 3221 3222 if (UseUpperBits) { 3223 unsigned ValSizeInBits = Outs[i].ArgVT.getSizeInBits(); 3224 unsigned LocSizeInBits = VA.getLocVT().getSizeInBits(); 3225 Val = DAG.getNode( 3226 ISD::SHL, DL, VA.getLocVT(), Val, 3227 DAG.getConstant(LocSizeInBits - ValSizeInBits, DL, VA.getLocVT())); 3228 } 3229 3230 Chain = DAG.getCopyToReg(Chain, DL, VA.getLocReg(), Val, Flag); 3231 3232 // Guarantee that all emitted copies are stuck together with flags. 3233 Flag = Chain.getValue(1); 3234 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT())); 3235 } 3236 3237 // The mips ABIs for returning structs by value requires that we copy 3238 // the sret argument into $v0 for the return. We saved the argument into 3239 // a virtual register in the entry block, so now we copy the value out 3240 // and into $v0. 3241 if (MF.getFunction()->hasStructRetAttr()) { 3242 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>(); 3243 unsigned Reg = MipsFI->getSRetReturnReg(); 3244 3245 if (!Reg) 3246 llvm_unreachable("sret virtual register not created in the entry block"); 3247 SDValue Val = 3248 DAG.getCopyFromReg(Chain, DL, Reg, getPointerTy(DAG.getDataLayout())); 3249 unsigned V0 = ABI.IsN64() ? Mips::V0_64 : Mips::V0; 3250 3251 Chain = DAG.getCopyToReg(Chain, DL, V0, Val, Flag); 3252 Flag = Chain.getValue(1); 3253 RetOps.push_back(DAG.getRegister(V0, getPointerTy(DAG.getDataLayout()))); 3254 } 3255 3256 RetOps[0] = Chain; // Update chain. 3257 3258 // Add the flag if we have it. 3259 if (Flag.getNode()) 3260 RetOps.push_back(Flag); 3261 3262 // ISRs must use "eret". 3263 if (DAG.getMachineFunction().getFunction()->hasFnAttribute("interrupt")) 3264 return LowerInterruptReturn(RetOps, DL, DAG); 3265 3266 // Standard return on Mips is a "jr $ra" 3267 return DAG.getNode(MipsISD::Ret, DL, MVT::Other, RetOps); 3268 } 3269 3270 //===----------------------------------------------------------------------===// 3271 // Mips Inline Assembly Support 3272 //===----------------------------------------------------------------------===// 3273 3274 /// getConstraintType - Given a constraint letter, return the type of 3275 /// constraint it is for this target. 3276 MipsTargetLowering::ConstraintType 3277 MipsTargetLowering::getConstraintType(StringRef Constraint) const { 3278 // Mips specific constraints 3279 // GCC config/mips/constraints.md 3280 // 3281 // 'd' : An address register. Equivalent to r 3282 // unless generating MIPS16 code. 3283 // 'y' : Equivalent to r; retained for 3284 // backwards compatibility. 3285 // 'c' : A register suitable for use in an indirect 3286 // jump. This will always be $25 for -mabicalls. 3287 // 'l' : The lo register. 1 word storage. 3288 // 'x' : The hilo register pair. Double word storage. 3289 if (Constraint.size() == 1) { 3290 switch (Constraint[0]) { 3291 default : break; 3292 case 'd': 3293 case 'y': 3294 case 'f': 3295 case 'c': 3296 case 'l': 3297 case 'x': 3298 return C_RegisterClass; 3299 case 'R': 3300 return C_Memory; 3301 } 3302 } 3303 3304 if (Constraint == "ZC") 3305 return C_Memory; 3306 3307 return TargetLowering::getConstraintType(Constraint); 3308 } 3309 3310 /// Examine constraint type and operand type and determine a weight value. 3311 /// This object must already have been set up with the operand type 3312 /// and the current alternative constraint selected. 3313 TargetLowering::ConstraintWeight 3314 MipsTargetLowering::getSingleConstraintMatchWeight( 3315 AsmOperandInfo &info, const char *constraint) const { 3316 ConstraintWeight weight = CW_Invalid; 3317 Value *CallOperandVal = info.CallOperandVal; 3318 // If we don't have a value, we can't do a match, 3319 // but allow it at the lowest weight. 3320 if (!CallOperandVal) 3321 return CW_Default; 3322 Type *type = CallOperandVal->getType(); 3323 // Look at the constraint type. 3324 switch (*constraint) { 3325 default: 3326 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint); 3327 break; 3328 case 'd': 3329 case 'y': 3330 if (type->isIntegerTy()) 3331 weight = CW_Register; 3332 break; 3333 case 'f': // FPU or MSA register 3334 if (Subtarget.hasMSA() && type->isVectorTy() && 3335 cast<VectorType>(type)->getBitWidth() == 128) 3336 weight = CW_Register; 3337 else if (type->isFloatTy()) 3338 weight = CW_Register; 3339 break; 3340 case 'c': // $25 for indirect jumps 3341 case 'l': // lo register 3342 case 'x': // hilo register pair 3343 if (type->isIntegerTy()) 3344 weight = CW_SpecificReg; 3345 break; 3346 case 'I': // signed 16 bit immediate 3347 case 'J': // integer zero 3348 case 'K': // unsigned 16 bit immediate 3349 case 'L': // signed 32 bit immediate where lower 16 bits are 0 3350 case 'N': // immediate in the range of -65535 to -1 (inclusive) 3351 case 'O': // signed 15 bit immediate (+- 16383) 3352 case 'P': // immediate in the range of 65535 to 1 (inclusive) 3353 if (isa<ConstantInt>(CallOperandVal)) 3354 weight = CW_Constant; 3355 break; 3356 case 'R': 3357 weight = CW_Memory; 3358 break; 3359 } 3360 return weight; 3361 } 3362 3363 /// This is a helper function to parse a physical register string and split it 3364 /// into non-numeric and numeric parts (Prefix and Reg). The first boolean flag 3365 /// that is returned indicates whether parsing was successful. The second flag 3366 /// is true if the numeric part exists. 3367 static std::pair<bool, bool> parsePhysicalReg(StringRef C, StringRef &Prefix, 3368 unsigned long long &Reg) { 3369 if (C.front() != '{' || C.back() != '}') 3370 return std::make_pair(false, false); 3371 3372 // Search for the first numeric character. 3373 StringRef::const_iterator I, B = C.begin() + 1, E = C.end() - 1; 3374 I = std::find_if(B, E, isdigit); 3375 3376 Prefix = StringRef(B, I - B); 3377 3378 // The second flag is set to false if no numeric characters were found. 3379 if (I == E) 3380 return std::make_pair(true, false); 3381 3382 // Parse the numeric characters. 3383 return std::make_pair(!getAsUnsignedInteger(StringRef(I, E - I), 10, Reg), 3384 true); 3385 } 3386 3387 std::pair<unsigned, const TargetRegisterClass *> MipsTargetLowering:: 3388 parseRegForInlineAsmConstraint(StringRef C, MVT VT) const { 3389 const TargetRegisterInfo *TRI = 3390 Subtarget.getRegisterInfo(); 3391 const TargetRegisterClass *RC; 3392 StringRef Prefix; 3393 unsigned long long Reg; 3394 3395 std::pair<bool, bool> R = parsePhysicalReg(C, Prefix, Reg); 3396 3397 if (!R.first) 3398 return std::make_pair(0U, nullptr); 3399 3400 if ((Prefix == "hi" || Prefix == "lo")) { // Parse hi/lo. 3401 // No numeric characters follow "hi" or "lo". 3402 if (R.second) 3403 return std::make_pair(0U, nullptr); 3404 3405 RC = TRI->getRegClass(Prefix == "hi" ? 3406 Mips::HI32RegClassID : Mips::LO32RegClassID); 3407 return std::make_pair(*(RC->begin()), RC); 3408 } else if (Prefix.startswith("$msa")) { 3409 // Parse $msa(ir|csr|access|save|modify|request|map|unmap) 3410 3411 // No numeric characters follow the name. 3412 if (R.second) 3413 return std::make_pair(0U, nullptr); 3414 3415 Reg = StringSwitch<unsigned long long>(Prefix) 3416 .Case("$msair", Mips::MSAIR) 3417 .Case("$msacsr", Mips::MSACSR) 3418 .Case("$msaaccess", Mips::MSAAccess) 3419 .Case("$msasave", Mips::MSASave) 3420 .Case("$msamodify", Mips::MSAModify) 3421 .Case("$msarequest", Mips::MSARequest) 3422 .Case("$msamap", Mips::MSAMap) 3423 .Case("$msaunmap", Mips::MSAUnmap) 3424 .Default(0); 3425 3426 if (!Reg) 3427 return std::make_pair(0U, nullptr); 3428 3429 RC = TRI->getRegClass(Mips::MSACtrlRegClassID); 3430 return std::make_pair(Reg, RC); 3431 } 3432 3433 if (!R.second) 3434 return std::make_pair(0U, nullptr); 3435 3436 if (Prefix == "$f") { // Parse $f0-$f31. 3437 // If the size of FP registers is 64-bit or Reg is an even number, select 3438 // the 64-bit register class. Otherwise, select the 32-bit register class. 3439 if (VT == MVT::Other) 3440 VT = (Subtarget.isFP64bit() || !(Reg % 2)) ? MVT::f64 : MVT::f32; 3441 3442 RC = getRegClassFor(VT); 3443 3444 if (RC == &Mips::AFGR64RegClass) { 3445 assert(Reg % 2 == 0); 3446 Reg >>= 1; 3447 } 3448 } else if (Prefix == "$fcc") // Parse $fcc0-$fcc7. 3449 RC = TRI->getRegClass(Mips::FCCRegClassID); 3450 else if (Prefix == "$w") { // Parse $w0-$w31. 3451 RC = getRegClassFor((VT == MVT::Other) ? MVT::v16i8 : VT); 3452 } else { // Parse $0-$31. 3453 assert(Prefix == "$"); 3454 RC = getRegClassFor((VT == MVT::Other) ? MVT::i32 : VT); 3455 } 3456 3457 assert(Reg < RC->getNumRegs()); 3458 return std::make_pair(*(RC->begin() + Reg), RC); 3459 } 3460 3461 /// Given a register class constraint, like 'r', if this corresponds directly 3462 /// to an LLVM register class, return a register of 0 and the register class 3463 /// pointer. 3464 std::pair<unsigned, const TargetRegisterClass *> 3465 MipsTargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, 3466 StringRef Constraint, 3467 MVT VT) const { 3468 if (Constraint.size() == 1) { 3469 switch (Constraint[0]) { 3470 case 'd': // Address register. Same as 'r' unless generating MIPS16 code. 3471 case 'y': // Same as 'r'. Exists for compatibility. 3472 case 'r': 3473 if (VT == MVT::i32 || VT == MVT::i16 || VT == MVT::i8) { 3474 if (Subtarget.inMips16Mode()) 3475 return std::make_pair(0U, &Mips::CPU16RegsRegClass); 3476 return std::make_pair(0U, &Mips::GPR32RegClass); 3477 } 3478 if (VT == MVT::i64 && !Subtarget.isGP64bit()) 3479 return std::make_pair(0U, &Mips::GPR32RegClass); 3480 if (VT == MVT::i64 && Subtarget.isGP64bit()) 3481 return std::make_pair(0U, &Mips::GPR64RegClass); 3482 // This will generate an error message 3483 return std::make_pair(0U, nullptr); 3484 case 'f': // FPU or MSA register 3485 if (VT == MVT::v16i8) 3486 return std::make_pair(0U, &Mips::MSA128BRegClass); 3487 else if (VT == MVT::v8i16 || VT == MVT::v8f16) 3488 return std::make_pair(0U, &Mips::MSA128HRegClass); 3489 else if (VT == MVT::v4i32 || VT == MVT::v4f32) 3490 return std::make_pair(0U, &Mips::MSA128WRegClass); 3491 else if (VT == MVT::v2i64 || VT == MVT::v2f64) 3492 return std::make_pair(0U, &Mips::MSA128DRegClass); 3493 else if (VT == MVT::f32) 3494 return std::make_pair(0U, &Mips::FGR32RegClass); 3495 else if ((VT == MVT::f64) && (!Subtarget.isSingleFloat())) { 3496 if (Subtarget.isFP64bit()) 3497 return std::make_pair(0U, &Mips::FGR64RegClass); 3498 return std::make_pair(0U, &Mips::AFGR64RegClass); 3499 } 3500 break; 3501 case 'c': // register suitable for indirect jump 3502 if (VT == MVT::i32) 3503 return std::make_pair((unsigned)Mips::T9, &Mips::GPR32RegClass); 3504 assert(VT == MVT::i64 && "Unexpected type."); 3505 return std::make_pair((unsigned)Mips::T9_64, &Mips::GPR64RegClass); 3506 case 'l': // register suitable for indirect jump 3507 if (VT == MVT::i32) 3508 return std::make_pair((unsigned)Mips::LO0, &Mips::LO32RegClass); 3509 return std::make_pair((unsigned)Mips::LO0_64, &Mips::LO64RegClass); 3510 case 'x': // register suitable for indirect jump 3511 // Fixme: Not triggering the use of both hi and low 3512 // This will generate an error message 3513 return std::make_pair(0U, nullptr); 3514 } 3515 } 3516 3517 std::pair<unsigned, const TargetRegisterClass *> R; 3518 R = parseRegForInlineAsmConstraint(Constraint, VT); 3519 3520 if (R.second) 3521 return R; 3522 3523 return TargetLowering::getRegForInlineAsmConstraint(TRI, Constraint, VT); 3524 } 3525 3526 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops 3527 /// vector. If it is invalid, don't add anything to Ops. 3528 void MipsTargetLowering::LowerAsmOperandForConstraint(SDValue Op, 3529 std::string &Constraint, 3530 std::vector<SDValue>&Ops, 3531 SelectionDAG &DAG) const { 3532 SDLoc DL(Op); 3533 SDValue Result; 3534 3535 // Only support length 1 constraints for now. 3536 if (Constraint.length() > 1) return; 3537 3538 char ConstraintLetter = Constraint[0]; 3539 switch (ConstraintLetter) { 3540 default: break; // This will fall through to the generic implementation 3541 case 'I': // Signed 16 bit constant 3542 // If this fails, the parent routine will give an error 3543 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 3544 EVT Type = Op.getValueType(); 3545 int64_t Val = C->getSExtValue(); 3546 if (isInt<16>(Val)) { 3547 Result = DAG.getTargetConstant(Val, DL, Type); 3548 break; 3549 } 3550 } 3551 return; 3552 case 'J': // integer zero 3553 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 3554 EVT Type = Op.getValueType(); 3555 int64_t Val = C->getZExtValue(); 3556 if (Val == 0) { 3557 Result = DAG.getTargetConstant(0, DL, Type); 3558 break; 3559 } 3560 } 3561 return; 3562 case 'K': // unsigned 16 bit immediate 3563 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 3564 EVT Type = Op.getValueType(); 3565 uint64_t Val = (uint64_t)C->getZExtValue(); 3566 if (isUInt<16>(Val)) { 3567 Result = DAG.getTargetConstant(Val, DL, Type); 3568 break; 3569 } 3570 } 3571 return; 3572 case 'L': // signed 32 bit immediate where lower 16 bits are 0 3573 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 3574 EVT Type = Op.getValueType(); 3575 int64_t Val = C->getSExtValue(); 3576 if ((isInt<32>(Val)) && ((Val & 0xffff) == 0)){ 3577 Result = DAG.getTargetConstant(Val, DL, Type); 3578 break; 3579 } 3580 } 3581 return; 3582 case 'N': // immediate in the range of -65535 to -1 (inclusive) 3583 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 3584 EVT Type = Op.getValueType(); 3585 int64_t Val = C->getSExtValue(); 3586 if ((Val >= -65535) && (Val <= -1)) { 3587 Result = DAG.getTargetConstant(Val, DL, Type); 3588 break; 3589 } 3590 } 3591 return; 3592 case 'O': // signed 15 bit immediate 3593 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 3594 EVT Type = Op.getValueType(); 3595 int64_t Val = C->getSExtValue(); 3596 if ((isInt<15>(Val))) { 3597 Result = DAG.getTargetConstant(Val, DL, Type); 3598 break; 3599 } 3600 } 3601 return; 3602 case 'P': // immediate in the range of 1 to 65535 (inclusive) 3603 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 3604 EVT Type = Op.getValueType(); 3605 int64_t Val = C->getSExtValue(); 3606 if ((Val <= 65535) && (Val >= 1)) { 3607 Result = DAG.getTargetConstant(Val, DL, Type); 3608 break; 3609 } 3610 } 3611 return; 3612 } 3613 3614 if (Result.getNode()) { 3615 Ops.push_back(Result); 3616 return; 3617 } 3618 3619 TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG); 3620 } 3621 3622 bool MipsTargetLowering::isLegalAddressingMode(const DataLayout &DL, 3623 const AddrMode &AM, Type *Ty, 3624 unsigned AS) const { 3625 // No global is ever allowed as a base. 3626 if (AM.BaseGV) 3627 return false; 3628 3629 switch (AM.Scale) { 3630 case 0: // "r+i" or just "i", depending on HasBaseReg. 3631 break; 3632 case 1: 3633 if (!AM.HasBaseReg) // allow "r+i". 3634 break; 3635 return false; // disallow "r+r" or "r+r+i". 3636 default: 3637 return false; 3638 } 3639 3640 return true; 3641 } 3642 3643 bool 3644 MipsTargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const { 3645 // The Mips target isn't yet aware of offsets. 3646 return false; 3647 } 3648 3649 EVT MipsTargetLowering::getOptimalMemOpType(uint64_t Size, unsigned DstAlign, 3650 unsigned SrcAlign, 3651 bool IsMemset, bool ZeroMemset, 3652 bool MemcpyStrSrc, 3653 MachineFunction &MF) const { 3654 if (Subtarget.hasMips64()) 3655 return MVT::i64; 3656 3657 return MVT::i32; 3658 } 3659 3660 bool MipsTargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const { 3661 if (VT != MVT::f32 && VT != MVT::f64) 3662 return false; 3663 if (Imm.isNegZero()) 3664 return false; 3665 return Imm.isZero(); 3666 } 3667 3668 unsigned MipsTargetLowering::getJumpTableEncoding() const { 3669 if (ABI.IsN64()) 3670 return MachineJumpTableInfo::EK_GPRel64BlockAddress; 3671 3672 return TargetLowering::getJumpTableEncoding(); 3673 } 3674 3675 bool MipsTargetLowering::useSoftFloat() const { 3676 return Subtarget.useSoftFloat(); 3677 } 3678 3679 void MipsTargetLowering::copyByValRegs( 3680 SDValue Chain, SDLoc DL, std::vector<SDValue> &OutChains, SelectionDAG &DAG, 3681 const ISD::ArgFlagsTy &Flags, SmallVectorImpl<SDValue> &InVals, 3682 const Argument *FuncArg, unsigned FirstReg, unsigned LastReg, 3683 const CCValAssign &VA, MipsCCState &State) const { 3684 MachineFunction &MF = DAG.getMachineFunction(); 3685 MachineFrameInfo *MFI = MF.getFrameInfo(); 3686 unsigned GPRSizeInBytes = Subtarget.getGPRSizeInBytes(); 3687 unsigned NumRegs = LastReg - FirstReg; 3688 unsigned RegAreaSize = NumRegs * GPRSizeInBytes; 3689 unsigned FrameObjSize = std::max(Flags.getByValSize(), RegAreaSize); 3690 int FrameObjOffset; 3691 ArrayRef<MCPhysReg> ByValArgRegs = ABI.GetByValArgRegs(); 3692 3693 if (RegAreaSize) 3694 FrameObjOffset = 3695 (int)ABI.GetCalleeAllocdArgSizeInBytes(State.getCallingConv()) - 3696 (int)((ByValArgRegs.size() - FirstReg) * GPRSizeInBytes); 3697 else 3698 FrameObjOffset = VA.getLocMemOffset(); 3699 3700 // Create frame object. 3701 EVT PtrTy = getPointerTy(DAG.getDataLayout()); 3702 int FI = MFI->CreateFixedObject(FrameObjSize, FrameObjOffset, true); 3703 SDValue FIN = DAG.getFrameIndex(FI, PtrTy); 3704 InVals.push_back(FIN); 3705 3706 if (!NumRegs) 3707 return; 3708 3709 // Copy arg registers. 3710 MVT RegTy = MVT::getIntegerVT(GPRSizeInBytes * 8); 3711 const TargetRegisterClass *RC = getRegClassFor(RegTy); 3712 3713 for (unsigned I = 0; I < NumRegs; ++I) { 3714 unsigned ArgReg = ByValArgRegs[FirstReg + I]; 3715 unsigned VReg = addLiveIn(MF, ArgReg, RC); 3716 unsigned Offset = I * GPRSizeInBytes; 3717 SDValue StorePtr = DAG.getNode(ISD::ADD, DL, PtrTy, FIN, 3718 DAG.getConstant(Offset, DL, PtrTy)); 3719 SDValue Store = DAG.getStore(Chain, DL, DAG.getRegister(VReg, RegTy), 3720 StorePtr, MachinePointerInfo(FuncArg, Offset), 3721 false, false, 0); 3722 OutChains.push_back(Store); 3723 } 3724 } 3725 3726 // Copy byVal arg to registers and stack. 3727 void MipsTargetLowering::passByValArg( 3728 SDValue Chain, SDLoc DL, 3729 std::deque<std::pair<unsigned, SDValue>> &RegsToPass, 3730 SmallVectorImpl<SDValue> &MemOpChains, SDValue StackPtr, 3731 MachineFrameInfo *MFI, SelectionDAG &DAG, SDValue Arg, unsigned FirstReg, 3732 unsigned LastReg, const ISD::ArgFlagsTy &Flags, bool isLittle, 3733 const CCValAssign &VA) const { 3734 unsigned ByValSizeInBytes = Flags.getByValSize(); 3735 unsigned OffsetInBytes = 0; // From beginning of struct 3736 unsigned RegSizeInBytes = Subtarget.getGPRSizeInBytes(); 3737 unsigned Alignment = std::min(Flags.getByValAlign(), RegSizeInBytes); 3738 EVT PtrTy = getPointerTy(DAG.getDataLayout()), 3739 RegTy = MVT::getIntegerVT(RegSizeInBytes * 8); 3740 unsigned NumRegs = LastReg - FirstReg; 3741 3742 if (NumRegs) { 3743 ArrayRef<MCPhysReg> ArgRegs = ABI.GetByValArgRegs(); 3744 bool LeftoverBytes = (NumRegs * RegSizeInBytes > ByValSizeInBytes); 3745 unsigned I = 0; 3746 3747 // Copy words to registers. 3748 for (; I < NumRegs - LeftoverBytes; ++I, OffsetInBytes += RegSizeInBytes) { 3749 SDValue LoadPtr = DAG.getNode(ISD::ADD, DL, PtrTy, Arg, 3750 DAG.getConstant(OffsetInBytes, DL, PtrTy)); 3751 SDValue LoadVal = DAG.getLoad(RegTy, DL, Chain, LoadPtr, 3752 MachinePointerInfo(), false, false, false, 3753 Alignment); 3754 MemOpChains.push_back(LoadVal.getValue(1)); 3755 unsigned ArgReg = ArgRegs[FirstReg + I]; 3756 RegsToPass.push_back(std::make_pair(ArgReg, LoadVal)); 3757 } 3758 3759 // Return if the struct has been fully copied. 3760 if (ByValSizeInBytes == OffsetInBytes) 3761 return; 3762 3763 // Copy the remainder of the byval argument with sub-word loads and shifts. 3764 if (LeftoverBytes) { 3765 SDValue Val; 3766 3767 for (unsigned LoadSizeInBytes = RegSizeInBytes / 2, TotalBytesLoaded = 0; 3768 OffsetInBytes < ByValSizeInBytes; LoadSizeInBytes /= 2) { 3769 unsigned RemainingSizeInBytes = ByValSizeInBytes - OffsetInBytes; 3770 3771 if (RemainingSizeInBytes < LoadSizeInBytes) 3772 continue; 3773 3774 // Load subword. 3775 SDValue LoadPtr = DAG.getNode(ISD::ADD, DL, PtrTy, Arg, 3776 DAG.getConstant(OffsetInBytes, DL, 3777 PtrTy)); 3778 SDValue LoadVal = DAG.getExtLoad( 3779 ISD::ZEXTLOAD, DL, RegTy, Chain, LoadPtr, MachinePointerInfo(), 3780 MVT::getIntegerVT(LoadSizeInBytes * 8), false, false, false, 3781 Alignment); 3782 MemOpChains.push_back(LoadVal.getValue(1)); 3783 3784 // Shift the loaded value. 3785 unsigned Shamt; 3786 3787 if (isLittle) 3788 Shamt = TotalBytesLoaded * 8; 3789 else 3790 Shamt = (RegSizeInBytes - (TotalBytesLoaded + LoadSizeInBytes)) * 8; 3791 3792 SDValue Shift = DAG.getNode(ISD::SHL, DL, RegTy, LoadVal, 3793 DAG.getConstant(Shamt, DL, MVT::i32)); 3794 3795 if (Val.getNode()) 3796 Val = DAG.getNode(ISD::OR, DL, RegTy, Val, Shift); 3797 else 3798 Val = Shift; 3799 3800 OffsetInBytes += LoadSizeInBytes; 3801 TotalBytesLoaded += LoadSizeInBytes; 3802 Alignment = std::min(Alignment, LoadSizeInBytes); 3803 } 3804 3805 unsigned ArgReg = ArgRegs[FirstReg + I]; 3806 RegsToPass.push_back(std::make_pair(ArgReg, Val)); 3807 return; 3808 } 3809 } 3810 3811 // Copy remainder of byval arg to it with memcpy. 3812 unsigned MemCpySize = ByValSizeInBytes - OffsetInBytes; 3813 SDValue Src = DAG.getNode(ISD::ADD, DL, PtrTy, Arg, 3814 DAG.getConstant(OffsetInBytes, DL, PtrTy)); 3815 SDValue Dst = DAG.getNode(ISD::ADD, DL, PtrTy, StackPtr, 3816 DAG.getIntPtrConstant(VA.getLocMemOffset(), DL)); 3817 Chain = DAG.getMemcpy(Chain, DL, Dst, Src, 3818 DAG.getConstant(MemCpySize, DL, PtrTy), 3819 Alignment, /*isVolatile=*/false, /*AlwaysInline=*/false, 3820 /*isTailCall=*/false, 3821 MachinePointerInfo(), MachinePointerInfo()); 3822 MemOpChains.push_back(Chain); 3823 } 3824 3825 void MipsTargetLowering::writeVarArgRegs(std::vector<SDValue> &OutChains, 3826 SDValue Chain, SDLoc DL, 3827 SelectionDAG &DAG, 3828 CCState &State) const { 3829 ArrayRef<MCPhysReg> ArgRegs = ABI.GetVarArgRegs(); 3830 unsigned Idx = State.getFirstUnallocated(ArgRegs); 3831 unsigned RegSizeInBytes = Subtarget.getGPRSizeInBytes(); 3832 MVT RegTy = MVT::getIntegerVT(RegSizeInBytes * 8); 3833 const TargetRegisterClass *RC = getRegClassFor(RegTy); 3834 MachineFunction &MF = DAG.getMachineFunction(); 3835 MachineFrameInfo *MFI = MF.getFrameInfo(); 3836 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>(); 3837 3838 // Offset of the first variable argument from stack pointer. 3839 int VaArgOffset; 3840 3841 if (ArgRegs.size() == Idx) 3842 VaArgOffset = alignTo(State.getNextStackOffset(), RegSizeInBytes); 3843 else { 3844 VaArgOffset = 3845 (int)ABI.GetCalleeAllocdArgSizeInBytes(State.getCallingConv()) - 3846 (int)(RegSizeInBytes * (ArgRegs.size() - Idx)); 3847 } 3848 3849 // Record the frame index of the first variable argument 3850 // which is a value necessary to VASTART. 3851 int FI = MFI->CreateFixedObject(RegSizeInBytes, VaArgOffset, true); 3852 MipsFI->setVarArgsFrameIndex(FI); 3853 3854 // Copy the integer registers that have not been used for argument passing 3855 // to the argument register save area. For O32, the save area is allocated 3856 // in the caller's stack frame, while for N32/64, it is allocated in the 3857 // callee's stack frame. 3858 for (unsigned I = Idx; I < ArgRegs.size(); 3859 ++I, VaArgOffset += RegSizeInBytes) { 3860 unsigned Reg = addLiveIn(MF, ArgRegs[I], RC); 3861 SDValue ArgValue = DAG.getCopyFromReg(Chain, DL, Reg, RegTy); 3862 FI = MFI->CreateFixedObject(RegSizeInBytes, VaArgOffset, true); 3863 SDValue PtrOff = DAG.getFrameIndex(FI, getPointerTy(DAG.getDataLayout())); 3864 SDValue Store = DAG.getStore(Chain, DL, ArgValue, PtrOff, 3865 MachinePointerInfo(), false, false, 0); 3866 cast<StoreSDNode>(Store.getNode())->getMemOperand()->setValue( 3867 (Value *)nullptr); 3868 OutChains.push_back(Store); 3869 } 3870 } 3871 3872 void MipsTargetLowering::HandleByVal(CCState *State, unsigned &Size, 3873 unsigned Align) const { 3874 const TargetFrameLowering *TFL = Subtarget.getFrameLowering(); 3875 3876 assert(Size && "Byval argument's size shouldn't be 0."); 3877 3878 Align = std::min(Align, TFL->getStackAlignment()); 3879 3880 unsigned FirstReg = 0; 3881 unsigned NumRegs = 0; 3882 3883 if (State->getCallingConv() != CallingConv::Fast) { 3884 unsigned RegSizeInBytes = Subtarget.getGPRSizeInBytes(); 3885 ArrayRef<MCPhysReg> IntArgRegs = ABI.GetByValArgRegs(); 3886 // FIXME: The O32 case actually describes no shadow registers. 3887 const MCPhysReg *ShadowRegs = 3888 ABI.IsO32() ? IntArgRegs.data() : Mips64DPRegs; 3889 3890 // We used to check the size as well but we can't do that anymore since 3891 // CCState::HandleByVal() rounds up the size after calling this function. 3892 assert(!(Align % RegSizeInBytes) && 3893 "Byval argument's alignment should be a multiple of" 3894 "RegSizeInBytes."); 3895 3896 FirstReg = State->getFirstUnallocated(IntArgRegs); 3897 3898 // If Align > RegSizeInBytes, the first arg register must be even. 3899 // FIXME: This condition happens to do the right thing but it's not the 3900 // right way to test it. We want to check that the stack frame offset 3901 // of the register is aligned. 3902 if ((Align > RegSizeInBytes) && (FirstReg % 2)) { 3903 State->AllocateReg(IntArgRegs[FirstReg], ShadowRegs[FirstReg]); 3904 ++FirstReg; 3905 } 3906 3907 // Mark the registers allocated. 3908 Size = alignTo(Size, RegSizeInBytes); 3909 for (unsigned I = FirstReg; Size > 0 && (I < IntArgRegs.size()); 3910 Size -= RegSizeInBytes, ++I, ++NumRegs) 3911 State->AllocateReg(IntArgRegs[I], ShadowRegs[I]); 3912 } 3913 3914 State->addInRegsParamInfo(FirstReg, FirstReg + NumRegs); 3915 } 3916 3917 MachineBasicBlock * 3918 MipsTargetLowering::emitPseudoSELECT(MachineInstr *MI, MachineBasicBlock *BB, 3919 bool isFPCmp, unsigned Opc) const { 3920 assert(!(Subtarget.hasMips4() || Subtarget.hasMips32()) && 3921 "Subtarget already supports SELECT nodes with the use of" 3922 "conditional-move instructions."); 3923 3924 const TargetInstrInfo *TII = 3925 Subtarget.getInstrInfo(); 3926 DebugLoc DL = MI->getDebugLoc(); 3927 3928 // To "insert" a SELECT instruction, we actually have to insert the 3929 // diamond control-flow pattern. The incoming instruction knows the 3930 // destination vreg to set, the condition code register to branch on, the 3931 // true/false values to select between, and a branch opcode to use. 3932 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 3933 MachineFunction::iterator It = ++BB->getIterator(); 3934 3935 // thisMBB: 3936 // ... 3937 // TrueVal = ... 3938 // setcc r1, r2, r3 3939 // bNE r1, r0, copy1MBB 3940 // fallthrough --> copy0MBB 3941 MachineBasicBlock *thisMBB = BB; 3942 MachineFunction *F = BB->getParent(); 3943 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB); 3944 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB); 3945 F->insert(It, copy0MBB); 3946 F->insert(It, sinkMBB); 3947 3948 // Transfer the remainder of BB and its successor edges to sinkMBB. 3949 sinkMBB->splice(sinkMBB->begin(), BB, 3950 std::next(MachineBasicBlock::iterator(MI)), BB->end()); 3951 sinkMBB->transferSuccessorsAndUpdatePHIs(BB); 3952 3953 // Next, add the true and fallthrough blocks as its successors. 3954 BB->addSuccessor(copy0MBB); 3955 BB->addSuccessor(sinkMBB); 3956 3957 if (isFPCmp) { 3958 // bc1[tf] cc, sinkMBB 3959 BuildMI(BB, DL, TII->get(Opc)) 3960 .addReg(MI->getOperand(1).getReg()) 3961 .addMBB(sinkMBB); 3962 } else { 3963 // bne rs, $0, sinkMBB 3964 BuildMI(BB, DL, TII->get(Opc)) 3965 .addReg(MI->getOperand(1).getReg()) 3966 .addReg(Mips::ZERO) 3967 .addMBB(sinkMBB); 3968 } 3969 3970 // copy0MBB: 3971 // %FalseValue = ... 3972 // # fallthrough to sinkMBB 3973 BB = copy0MBB; 3974 3975 // Update machine-CFG edges 3976 BB->addSuccessor(sinkMBB); 3977 3978 // sinkMBB: 3979 // %Result = phi [ %TrueValue, thisMBB ], [ %FalseValue, copy0MBB ] 3980 // ... 3981 BB = sinkMBB; 3982 3983 BuildMI(*BB, BB->begin(), DL, 3984 TII->get(Mips::PHI), MI->getOperand(0).getReg()) 3985 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB) 3986 .addReg(MI->getOperand(3).getReg()).addMBB(copy0MBB); 3987 3988 MI->eraseFromParent(); // The pseudo instruction is gone now. 3989 3990 return BB; 3991 } 3992 3993 // FIXME? Maybe this could be a TableGen attribute on some registers and 3994 // this table could be generated automatically from RegInfo. 3995 unsigned MipsTargetLowering::getRegisterByName(const char* RegName, EVT VT, 3996 SelectionDAG &DAG) const { 3997 // Named registers is expected to be fairly rare. For now, just support $28 3998 // since the linux kernel uses it. 3999 if (Subtarget.isGP64bit()) { 4000 unsigned Reg = StringSwitch<unsigned>(RegName) 4001 .Case("$28", Mips::GP_64) 4002 .Default(0); 4003 if (Reg) 4004 return Reg; 4005 } else { 4006 unsigned Reg = StringSwitch<unsigned>(RegName) 4007 .Case("$28", Mips::GP) 4008 .Default(0); 4009 if (Reg) 4010 return Reg; 4011 } 4012 report_fatal_error("Invalid register name global variable"); 4013 } 4014