1 //===-- MipsISelLowering.cpp - Mips DAG Lowering Implementation -----------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file defines the interfaces that Mips uses to lower LLVM code into a 11 // selection DAG. 12 // 13 //===----------------------------------------------------------------------===// 14 #include "MipsISelLowering.h" 15 #include "InstPrinter/MipsInstPrinter.h" 16 #include "MCTargetDesc/MipsBaseInfo.h" 17 #include "MipsCCState.h" 18 #include "MipsMachineFunction.h" 19 #include "MipsSubtarget.h" 20 #include "MipsTargetMachine.h" 21 #include "MipsTargetObjectFile.h" 22 #include "llvm/ADT/Statistic.h" 23 #include "llvm/ADT/StringSwitch.h" 24 #include "llvm/CodeGen/CallingConvLower.h" 25 #include "llvm/CodeGen/MachineFrameInfo.h" 26 #include "llvm/CodeGen/MachineFunction.h" 27 #include "llvm/CodeGen/MachineInstrBuilder.h" 28 #include "llvm/CodeGen/MachineJumpTableInfo.h" 29 #include "llvm/CodeGen/MachineRegisterInfo.h" 30 #include "llvm/CodeGen/FunctionLoweringInfo.h" 31 #include "llvm/CodeGen/SelectionDAGISel.h" 32 #include "llvm/CodeGen/ValueTypes.h" 33 #include "llvm/IR/CallingConv.h" 34 #include "llvm/IR/DerivedTypes.h" 35 #include "llvm/IR/GlobalVariable.h" 36 #include "llvm/Support/CommandLine.h" 37 #include "llvm/Support/Debug.h" 38 #include "llvm/Support/ErrorHandling.h" 39 #include "llvm/Support/raw_ostream.h" 40 #include <cctype> 41 42 using namespace llvm; 43 44 #define DEBUG_TYPE "mips-lower" 45 46 STATISTIC(NumTailCalls, "Number of tail calls"); 47 48 static cl::opt<bool> 49 LargeGOT("mxgot", cl::Hidden, 50 cl::desc("MIPS: Enable GOT larger than 64k."), cl::init(false)); 51 52 static cl::opt<bool> 53 NoZeroDivCheck("mno-check-zero-division", cl::Hidden, 54 cl::desc("MIPS: Don't trap on integer division by zero."), 55 cl::init(false)); 56 57 static const MCPhysReg Mips64DPRegs[8] = { 58 Mips::D12_64, Mips::D13_64, Mips::D14_64, Mips::D15_64, 59 Mips::D16_64, Mips::D17_64, Mips::D18_64, Mips::D19_64 60 }; 61 62 // If I is a shifted mask, set the size (Size) and the first bit of the 63 // mask (Pos), and return true. 64 // For example, if I is 0x003ff800, (Pos, Size) = (11, 11). 65 static bool isShiftedMask(uint64_t I, uint64_t &Pos, uint64_t &Size) { 66 if (!isShiftedMask_64(I)) 67 return false; 68 69 Size = countPopulation(I); 70 Pos = countTrailingZeros(I); 71 return true; 72 } 73 74 SDValue MipsTargetLowering::getGlobalReg(SelectionDAG &DAG, EVT Ty) const { 75 MipsFunctionInfo *FI = DAG.getMachineFunction().getInfo<MipsFunctionInfo>(); 76 return DAG.getRegister(FI->getGlobalBaseReg(), Ty); 77 } 78 79 SDValue MipsTargetLowering::getTargetNode(GlobalAddressSDNode *N, EVT Ty, 80 SelectionDAG &DAG, 81 unsigned Flag) const { 82 return DAG.getTargetGlobalAddress(N->getGlobal(), SDLoc(N), Ty, 0, Flag); 83 } 84 85 SDValue MipsTargetLowering::getTargetNode(ExternalSymbolSDNode *N, EVT Ty, 86 SelectionDAG &DAG, 87 unsigned Flag) const { 88 return DAG.getTargetExternalSymbol(N->getSymbol(), Ty, Flag); 89 } 90 91 SDValue MipsTargetLowering::getTargetNode(BlockAddressSDNode *N, EVT Ty, 92 SelectionDAG &DAG, 93 unsigned Flag) const { 94 return DAG.getTargetBlockAddress(N->getBlockAddress(), Ty, 0, Flag); 95 } 96 97 SDValue MipsTargetLowering::getTargetNode(JumpTableSDNode *N, EVT Ty, 98 SelectionDAG &DAG, 99 unsigned Flag) const { 100 return DAG.getTargetJumpTable(N->getIndex(), Ty, Flag); 101 } 102 103 SDValue MipsTargetLowering::getTargetNode(ConstantPoolSDNode *N, EVT Ty, 104 SelectionDAG &DAG, 105 unsigned Flag) const { 106 return DAG.getTargetConstantPool(N->getConstVal(), Ty, N->getAlignment(), 107 N->getOffset(), Flag); 108 } 109 110 const char *MipsTargetLowering::getTargetNodeName(unsigned Opcode) const { 111 switch ((MipsISD::NodeType)Opcode) { 112 case MipsISD::FIRST_NUMBER: break; 113 case MipsISD::JmpLink: return "MipsISD::JmpLink"; 114 case MipsISD::TailCall: return "MipsISD::TailCall"; 115 case MipsISD::Hi: return "MipsISD::Hi"; 116 case MipsISD::Lo: return "MipsISD::Lo"; 117 case MipsISD::GPRel: return "MipsISD::GPRel"; 118 case MipsISD::ThreadPointer: return "MipsISD::ThreadPointer"; 119 case MipsISD::Ret: return "MipsISD::Ret"; 120 case MipsISD::ERet: return "MipsISD::ERet"; 121 case MipsISD::EH_RETURN: return "MipsISD::EH_RETURN"; 122 case MipsISD::FPBrcond: return "MipsISD::FPBrcond"; 123 case MipsISD::FPCmp: return "MipsISD::FPCmp"; 124 case MipsISD::CMovFP_T: return "MipsISD::CMovFP_T"; 125 case MipsISD::CMovFP_F: return "MipsISD::CMovFP_F"; 126 case MipsISD::TruncIntFP: return "MipsISD::TruncIntFP"; 127 case MipsISD::MFHI: return "MipsISD::MFHI"; 128 case MipsISD::MFLO: return "MipsISD::MFLO"; 129 case MipsISD::MTLOHI: return "MipsISD::MTLOHI"; 130 case MipsISD::Mult: return "MipsISD::Mult"; 131 case MipsISD::Multu: return "MipsISD::Multu"; 132 case MipsISD::MAdd: return "MipsISD::MAdd"; 133 case MipsISD::MAddu: return "MipsISD::MAddu"; 134 case MipsISD::MSub: return "MipsISD::MSub"; 135 case MipsISD::MSubu: return "MipsISD::MSubu"; 136 case MipsISD::DivRem: return "MipsISD::DivRem"; 137 case MipsISD::DivRemU: return "MipsISD::DivRemU"; 138 case MipsISD::DivRem16: return "MipsISD::DivRem16"; 139 case MipsISD::DivRemU16: return "MipsISD::DivRemU16"; 140 case MipsISD::BuildPairF64: return "MipsISD::BuildPairF64"; 141 case MipsISD::ExtractElementF64: return "MipsISD::ExtractElementF64"; 142 case MipsISD::Wrapper: return "MipsISD::Wrapper"; 143 case MipsISD::DynAlloc: return "MipsISD::DynAlloc"; 144 case MipsISD::Sync: return "MipsISD::Sync"; 145 case MipsISD::Ext: return "MipsISD::Ext"; 146 case MipsISD::Ins: return "MipsISD::Ins"; 147 case MipsISD::LWL: return "MipsISD::LWL"; 148 case MipsISD::LWR: return "MipsISD::LWR"; 149 case MipsISD::SWL: return "MipsISD::SWL"; 150 case MipsISD::SWR: return "MipsISD::SWR"; 151 case MipsISD::LDL: return "MipsISD::LDL"; 152 case MipsISD::LDR: return "MipsISD::LDR"; 153 case MipsISD::SDL: return "MipsISD::SDL"; 154 case MipsISD::SDR: return "MipsISD::SDR"; 155 case MipsISD::EXTP: return "MipsISD::EXTP"; 156 case MipsISD::EXTPDP: return "MipsISD::EXTPDP"; 157 case MipsISD::EXTR_S_H: return "MipsISD::EXTR_S_H"; 158 case MipsISD::EXTR_W: return "MipsISD::EXTR_W"; 159 case MipsISD::EXTR_R_W: return "MipsISD::EXTR_R_W"; 160 case MipsISD::EXTR_RS_W: return "MipsISD::EXTR_RS_W"; 161 case MipsISD::SHILO: return "MipsISD::SHILO"; 162 case MipsISD::MTHLIP: return "MipsISD::MTHLIP"; 163 case MipsISD::MULSAQ_S_W_PH: return "MipsISD::MULSAQ_S_W_PH"; 164 case MipsISD::MAQ_S_W_PHL: return "MipsISD::MAQ_S_W_PHL"; 165 case MipsISD::MAQ_S_W_PHR: return "MipsISD::MAQ_S_W_PHR"; 166 case MipsISD::MAQ_SA_W_PHL: return "MipsISD::MAQ_SA_W_PHL"; 167 case MipsISD::MAQ_SA_W_PHR: return "MipsISD::MAQ_SA_W_PHR"; 168 case MipsISD::DPAU_H_QBL: return "MipsISD::DPAU_H_QBL"; 169 case MipsISD::DPAU_H_QBR: return "MipsISD::DPAU_H_QBR"; 170 case MipsISD::DPSU_H_QBL: return "MipsISD::DPSU_H_QBL"; 171 case MipsISD::DPSU_H_QBR: return "MipsISD::DPSU_H_QBR"; 172 case MipsISD::DPAQ_S_W_PH: return "MipsISD::DPAQ_S_W_PH"; 173 case MipsISD::DPSQ_S_W_PH: return "MipsISD::DPSQ_S_W_PH"; 174 case MipsISD::DPAQ_SA_L_W: return "MipsISD::DPAQ_SA_L_W"; 175 case MipsISD::DPSQ_SA_L_W: return "MipsISD::DPSQ_SA_L_W"; 176 case MipsISD::DPA_W_PH: return "MipsISD::DPA_W_PH"; 177 case MipsISD::DPS_W_PH: return "MipsISD::DPS_W_PH"; 178 case MipsISD::DPAQX_S_W_PH: return "MipsISD::DPAQX_S_W_PH"; 179 case MipsISD::DPAQX_SA_W_PH: return "MipsISD::DPAQX_SA_W_PH"; 180 case MipsISD::DPAX_W_PH: return "MipsISD::DPAX_W_PH"; 181 case MipsISD::DPSX_W_PH: return "MipsISD::DPSX_W_PH"; 182 case MipsISD::DPSQX_S_W_PH: return "MipsISD::DPSQX_S_W_PH"; 183 case MipsISD::DPSQX_SA_W_PH: return "MipsISD::DPSQX_SA_W_PH"; 184 case MipsISD::MULSA_W_PH: return "MipsISD::MULSA_W_PH"; 185 case MipsISD::MULT: return "MipsISD::MULT"; 186 case MipsISD::MULTU: return "MipsISD::MULTU"; 187 case MipsISD::MADD_DSP: return "MipsISD::MADD_DSP"; 188 case MipsISD::MADDU_DSP: return "MipsISD::MADDU_DSP"; 189 case MipsISD::MSUB_DSP: return "MipsISD::MSUB_DSP"; 190 case MipsISD::MSUBU_DSP: return "MipsISD::MSUBU_DSP"; 191 case MipsISD::SHLL_DSP: return "MipsISD::SHLL_DSP"; 192 case MipsISD::SHRA_DSP: return "MipsISD::SHRA_DSP"; 193 case MipsISD::SHRL_DSP: return "MipsISD::SHRL_DSP"; 194 case MipsISD::SETCC_DSP: return "MipsISD::SETCC_DSP"; 195 case MipsISD::SELECT_CC_DSP: return "MipsISD::SELECT_CC_DSP"; 196 case MipsISD::VALL_ZERO: return "MipsISD::VALL_ZERO"; 197 case MipsISD::VANY_ZERO: return "MipsISD::VANY_ZERO"; 198 case MipsISD::VALL_NONZERO: return "MipsISD::VALL_NONZERO"; 199 case MipsISD::VANY_NONZERO: return "MipsISD::VANY_NONZERO"; 200 case MipsISD::VCEQ: return "MipsISD::VCEQ"; 201 case MipsISD::VCLE_S: return "MipsISD::VCLE_S"; 202 case MipsISD::VCLE_U: return "MipsISD::VCLE_U"; 203 case MipsISD::VCLT_S: return "MipsISD::VCLT_S"; 204 case MipsISD::VCLT_U: return "MipsISD::VCLT_U"; 205 case MipsISD::VSMAX: return "MipsISD::VSMAX"; 206 case MipsISD::VSMIN: return "MipsISD::VSMIN"; 207 case MipsISD::VUMAX: return "MipsISD::VUMAX"; 208 case MipsISD::VUMIN: return "MipsISD::VUMIN"; 209 case MipsISD::VEXTRACT_SEXT_ELT: return "MipsISD::VEXTRACT_SEXT_ELT"; 210 case MipsISD::VEXTRACT_ZEXT_ELT: return "MipsISD::VEXTRACT_ZEXT_ELT"; 211 case MipsISD::VNOR: return "MipsISD::VNOR"; 212 case MipsISD::VSHF: return "MipsISD::VSHF"; 213 case MipsISD::SHF: return "MipsISD::SHF"; 214 case MipsISD::ILVEV: return "MipsISD::ILVEV"; 215 case MipsISD::ILVOD: return "MipsISD::ILVOD"; 216 case MipsISD::ILVL: return "MipsISD::ILVL"; 217 case MipsISD::ILVR: return "MipsISD::ILVR"; 218 case MipsISD::PCKEV: return "MipsISD::PCKEV"; 219 case MipsISD::PCKOD: return "MipsISD::PCKOD"; 220 case MipsISD::INSVE: return "MipsISD::INSVE"; 221 } 222 return nullptr; 223 } 224 225 MipsTargetLowering::MipsTargetLowering(const MipsTargetMachine &TM, 226 const MipsSubtarget &STI) 227 : TargetLowering(TM), Subtarget(STI), ABI(TM.getABI()) { 228 // Mips does not have i1 type, so use i32 for 229 // setcc operations results (slt, sgt, ...). 230 setBooleanContents(ZeroOrOneBooleanContent); 231 setBooleanVectorContents(ZeroOrNegativeOneBooleanContent); 232 // The cmp.cond.fmt instruction in MIPS32r6/MIPS64r6 uses 0 and -1 like MSA 233 // does. Integer booleans still use 0 and 1. 234 if (Subtarget.hasMips32r6()) 235 setBooleanContents(ZeroOrOneBooleanContent, 236 ZeroOrNegativeOneBooleanContent); 237 238 // Load extented operations for i1 types must be promoted 239 for (MVT VT : MVT::integer_valuetypes()) { 240 setLoadExtAction(ISD::EXTLOAD, VT, MVT::i1, Promote); 241 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i1, Promote); 242 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i1, Promote); 243 } 244 245 // MIPS doesn't have extending float->double load/store. Set LoadExtAction 246 // for f32, f16 247 for (MVT VT : MVT::fp_valuetypes()) { 248 setLoadExtAction(ISD::EXTLOAD, VT, MVT::f32, Expand); 249 setLoadExtAction(ISD::EXTLOAD, VT, MVT::f16, Expand); 250 } 251 252 // Set LoadExtAction for f16 vectors to Expand 253 for (MVT VT : MVT::fp_vector_valuetypes()) { 254 MVT F16VT = MVT::getVectorVT(MVT::f16, VT.getVectorNumElements()); 255 if (F16VT.isValid()) 256 setLoadExtAction(ISD::EXTLOAD, VT, F16VT, Expand); 257 } 258 259 setTruncStoreAction(MVT::f32, MVT::f16, Expand); 260 setTruncStoreAction(MVT::f64, MVT::f16, Expand); 261 262 setTruncStoreAction(MVT::f64, MVT::f32, Expand); 263 264 // Used by legalize types to correctly generate the setcc result. 265 // Without this, every float setcc comes with a AND/OR with the result, 266 // we don't want this, since the fpcmp result goes to a flag register, 267 // which is used implicitly by brcond and select operations. 268 AddPromotedToType(ISD::SETCC, MVT::i1, MVT::i32); 269 270 // Mips Custom Operations 271 setOperationAction(ISD::BR_JT, MVT::Other, Custom); 272 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom); 273 setOperationAction(ISD::BlockAddress, MVT::i32, Custom); 274 setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom); 275 setOperationAction(ISD::JumpTable, MVT::i32, Custom); 276 setOperationAction(ISD::ConstantPool, MVT::i32, Custom); 277 setOperationAction(ISD::SELECT, MVT::f32, Custom); 278 setOperationAction(ISD::SELECT, MVT::f64, Custom); 279 setOperationAction(ISD::SELECT, MVT::i32, Custom); 280 setOperationAction(ISD::SETCC, MVT::f32, Custom); 281 setOperationAction(ISD::SETCC, MVT::f64, Custom); 282 setOperationAction(ISD::BRCOND, MVT::Other, Custom); 283 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom); 284 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom); 285 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom); 286 287 if (Subtarget.isGP64bit()) { 288 setOperationAction(ISD::GlobalAddress, MVT::i64, Custom); 289 setOperationAction(ISD::BlockAddress, MVT::i64, Custom); 290 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom); 291 setOperationAction(ISD::JumpTable, MVT::i64, Custom); 292 setOperationAction(ISD::ConstantPool, MVT::i64, Custom); 293 setOperationAction(ISD::SELECT, MVT::i64, Custom); 294 setOperationAction(ISD::LOAD, MVT::i64, Custom); 295 setOperationAction(ISD::STORE, MVT::i64, Custom); 296 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom); 297 setOperationAction(ISD::SHL_PARTS, MVT::i64, Custom); 298 setOperationAction(ISD::SRA_PARTS, MVT::i64, Custom); 299 setOperationAction(ISD::SRL_PARTS, MVT::i64, Custom); 300 } 301 302 if (!Subtarget.isGP64bit()) { 303 setOperationAction(ISD::SHL_PARTS, MVT::i32, Custom); 304 setOperationAction(ISD::SRA_PARTS, MVT::i32, Custom); 305 setOperationAction(ISD::SRL_PARTS, MVT::i32, Custom); 306 } 307 308 setOperationAction(ISD::EH_DWARF_CFA, MVT::i32, Custom); 309 if (Subtarget.isGP64bit()) 310 setOperationAction(ISD::EH_DWARF_CFA, MVT::i64, Custom); 311 312 setOperationAction(ISD::SDIV, MVT::i32, Expand); 313 setOperationAction(ISD::SREM, MVT::i32, Expand); 314 setOperationAction(ISD::UDIV, MVT::i32, Expand); 315 setOperationAction(ISD::UREM, MVT::i32, Expand); 316 setOperationAction(ISD::SDIV, MVT::i64, Expand); 317 setOperationAction(ISD::SREM, MVT::i64, Expand); 318 setOperationAction(ISD::UDIV, MVT::i64, Expand); 319 setOperationAction(ISD::UREM, MVT::i64, Expand); 320 321 // Operations not directly supported by Mips. 322 setOperationAction(ISD::BR_CC, MVT::f32, Expand); 323 setOperationAction(ISD::BR_CC, MVT::f64, Expand); 324 setOperationAction(ISD::BR_CC, MVT::i32, Expand); 325 setOperationAction(ISD::BR_CC, MVT::i64, Expand); 326 setOperationAction(ISD::SELECT_CC, MVT::i32, Expand); 327 setOperationAction(ISD::SELECT_CC, MVT::i64, Expand); 328 setOperationAction(ISD::SELECT_CC, MVT::f32, Expand); 329 setOperationAction(ISD::SELECT_CC, MVT::f64, Expand); 330 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand); 331 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Expand); 332 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand); 333 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Expand); 334 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand); 335 if (Subtarget.hasCnMips()) { 336 setOperationAction(ISD::CTPOP, MVT::i32, Legal); 337 setOperationAction(ISD::CTPOP, MVT::i64, Legal); 338 } else { 339 setOperationAction(ISD::CTPOP, MVT::i32, Expand); 340 setOperationAction(ISD::CTPOP, MVT::i64, Expand); 341 } 342 setOperationAction(ISD::CTTZ, MVT::i32, Expand); 343 setOperationAction(ISD::CTTZ, MVT::i64, Expand); 344 setOperationAction(ISD::ROTL, MVT::i32, Expand); 345 setOperationAction(ISD::ROTL, MVT::i64, Expand); 346 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Expand); 347 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64, Expand); 348 349 if (!Subtarget.hasMips32r2()) 350 setOperationAction(ISD::ROTR, MVT::i32, Expand); 351 352 if (!Subtarget.hasMips64r2()) 353 setOperationAction(ISD::ROTR, MVT::i64, Expand); 354 355 setOperationAction(ISD::FSIN, MVT::f32, Expand); 356 setOperationAction(ISD::FSIN, MVT::f64, Expand); 357 setOperationAction(ISD::FCOS, MVT::f32, Expand); 358 setOperationAction(ISD::FCOS, MVT::f64, Expand); 359 setOperationAction(ISD::FSINCOS, MVT::f32, Expand); 360 setOperationAction(ISD::FSINCOS, MVT::f64, Expand); 361 setOperationAction(ISD::FPOWI, MVT::f32, Expand); 362 setOperationAction(ISD::FPOW, MVT::f32, Expand); 363 setOperationAction(ISD::FPOW, MVT::f64, Expand); 364 setOperationAction(ISD::FLOG, MVT::f32, Expand); 365 setOperationAction(ISD::FLOG2, MVT::f32, Expand); 366 setOperationAction(ISD::FLOG10, MVT::f32, Expand); 367 setOperationAction(ISD::FEXP, MVT::f32, Expand); 368 setOperationAction(ISD::FMA, MVT::f32, Expand); 369 setOperationAction(ISD::FMA, MVT::f64, Expand); 370 setOperationAction(ISD::FREM, MVT::f32, Expand); 371 setOperationAction(ISD::FREM, MVT::f64, Expand); 372 373 // Lower f16 conversion operations into library calls 374 setOperationAction(ISD::FP16_TO_FP, MVT::f32, Expand); 375 setOperationAction(ISD::FP_TO_FP16, MVT::f32, Expand); 376 setOperationAction(ISD::FP16_TO_FP, MVT::f64, Expand); 377 setOperationAction(ISD::FP_TO_FP16, MVT::f64, Expand); 378 379 setOperationAction(ISD::EH_RETURN, MVT::Other, Custom); 380 381 setOperationAction(ISD::VASTART, MVT::Other, Custom); 382 setOperationAction(ISD::VAARG, MVT::Other, Custom); 383 setOperationAction(ISD::VACOPY, MVT::Other, Expand); 384 setOperationAction(ISD::VAEND, MVT::Other, Expand); 385 386 // Use the default for now 387 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand); 388 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand); 389 390 if (!Subtarget.isGP64bit()) { 391 setOperationAction(ISD::ATOMIC_LOAD, MVT::i64, Expand); 392 setOperationAction(ISD::ATOMIC_STORE, MVT::i64, Expand); 393 } 394 395 396 if (!Subtarget.hasMips32r2()) { 397 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8, Expand); 398 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand); 399 } 400 401 // MIPS16 lacks MIPS32's clz and clo instructions. 402 if (!Subtarget.hasMips32() || Subtarget.inMips16Mode()) 403 setOperationAction(ISD::CTLZ, MVT::i32, Expand); 404 if (!Subtarget.hasMips64()) 405 setOperationAction(ISD::CTLZ, MVT::i64, Expand); 406 407 if (!Subtarget.hasMips32r2()) 408 setOperationAction(ISD::BSWAP, MVT::i32, Expand); 409 if (!Subtarget.hasMips64r2()) 410 setOperationAction(ISD::BSWAP, MVT::i64, Expand); 411 412 if (Subtarget.isGP64bit()) { 413 setLoadExtAction(ISD::SEXTLOAD, MVT::i64, MVT::i32, Custom); 414 setLoadExtAction(ISD::ZEXTLOAD, MVT::i64, MVT::i32, Custom); 415 setLoadExtAction(ISD::EXTLOAD, MVT::i64, MVT::i32, Custom); 416 setTruncStoreAction(MVT::i64, MVT::i32, Custom); 417 } 418 419 setOperationAction(ISD::TRAP, MVT::Other, Legal); 420 421 setTargetDAGCombine(ISD::SDIVREM); 422 setTargetDAGCombine(ISD::UDIVREM); 423 setTargetDAGCombine(ISD::SELECT); 424 setTargetDAGCombine(ISD::AND); 425 setTargetDAGCombine(ISD::OR); 426 setTargetDAGCombine(ISD::ADD); 427 setTargetDAGCombine(ISD::AssertZext); 428 429 if (ABI.IsO32()) { 430 // These libcalls are not available in 32-bit. 431 setLibcallName(RTLIB::SHL_I128, nullptr); 432 setLibcallName(RTLIB::SRL_I128, nullptr); 433 setLibcallName(RTLIB::SRA_I128, nullptr); 434 } 435 436 setMinFunctionAlignment(Subtarget.isGP64bit() ? 3 : 2); 437 438 // The arguments on the stack are defined in terms of 4-byte slots on O32 439 // and 8-byte slots on N32/N64. 440 setMinStackArgumentAlignment((ABI.IsN32() || ABI.IsN64()) ? 8 : 4); 441 442 setStackPointerRegisterToSaveRestore(ABI.IsN64() ? Mips::SP_64 : Mips::SP); 443 444 MaxStoresPerMemcpy = 16; 445 446 isMicroMips = Subtarget.inMicroMipsMode(); 447 } 448 449 const MipsTargetLowering *MipsTargetLowering::create(const MipsTargetMachine &TM, 450 const MipsSubtarget &STI) { 451 if (STI.inMips16Mode()) 452 return llvm::createMips16TargetLowering(TM, STI); 453 454 return llvm::createMipsSETargetLowering(TM, STI); 455 } 456 457 // Create a fast isel object. 458 FastISel * 459 MipsTargetLowering::createFastISel(FunctionLoweringInfo &funcInfo, 460 const TargetLibraryInfo *libInfo) const { 461 const MipsTargetMachine &TM = 462 static_cast<const MipsTargetMachine &>(funcInfo.MF->getTarget()); 463 464 // We support only the standard encoding [MIPS32,MIPS32R5] ISAs. 465 bool UseFastISel = TM.Options.EnableFastISel && Subtarget.hasMips32() && 466 !Subtarget.hasMips32r6() && !Subtarget.inMips16Mode() && 467 !Subtarget.inMicroMipsMode(); 468 469 // Disable if we don't generate PIC or the ABI isn't O32. 470 if (!TM.isPositionIndependent() || !TM.getABI().IsO32()) 471 UseFastISel = false; 472 473 return UseFastISel ? Mips::createFastISel(funcInfo, libInfo) : nullptr; 474 } 475 476 EVT MipsTargetLowering::getSetCCResultType(const DataLayout &, LLVMContext &, 477 EVT VT) const { 478 if (!VT.isVector()) 479 return MVT::i32; 480 return VT.changeVectorElementTypeToInteger(); 481 } 482 483 static SDValue performDivRemCombine(SDNode *N, SelectionDAG &DAG, 484 TargetLowering::DAGCombinerInfo &DCI, 485 const MipsSubtarget &Subtarget) { 486 if (DCI.isBeforeLegalizeOps()) 487 return SDValue(); 488 489 EVT Ty = N->getValueType(0); 490 unsigned LO = (Ty == MVT::i32) ? Mips::LO0 : Mips::LO0_64; 491 unsigned HI = (Ty == MVT::i32) ? Mips::HI0 : Mips::HI0_64; 492 unsigned Opc = N->getOpcode() == ISD::SDIVREM ? MipsISD::DivRem16 : 493 MipsISD::DivRemU16; 494 SDLoc DL(N); 495 496 SDValue DivRem = DAG.getNode(Opc, DL, MVT::Glue, 497 N->getOperand(0), N->getOperand(1)); 498 SDValue InChain = DAG.getEntryNode(); 499 SDValue InGlue = DivRem; 500 501 // insert MFLO 502 if (N->hasAnyUseOfValue(0)) { 503 SDValue CopyFromLo = DAG.getCopyFromReg(InChain, DL, LO, Ty, 504 InGlue); 505 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), CopyFromLo); 506 InChain = CopyFromLo.getValue(1); 507 InGlue = CopyFromLo.getValue(2); 508 } 509 510 // insert MFHI 511 if (N->hasAnyUseOfValue(1)) { 512 SDValue CopyFromHi = DAG.getCopyFromReg(InChain, DL, 513 HI, Ty, InGlue); 514 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), CopyFromHi); 515 } 516 517 return SDValue(); 518 } 519 520 static Mips::CondCode condCodeToFCC(ISD::CondCode CC) { 521 switch (CC) { 522 default: llvm_unreachable("Unknown fp condition code!"); 523 case ISD::SETEQ: 524 case ISD::SETOEQ: return Mips::FCOND_OEQ; 525 case ISD::SETUNE: return Mips::FCOND_UNE; 526 case ISD::SETLT: 527 case ISD::SETOLT: return Mips::FCOND_OLT; 528 case ISD::SETGT: 529 case ISD::SETOGT: return Mips::FCOND_OGT; 530 case ISD::SETLE: 531 case ISD::SETOLE: return Mips::FCOND_OLE; 532 case ISD::SETGE: 533 case ISD::SETOGE: return Mips::FCOND_OGE; 534 case ISD::SETULT: return Mips::FCOND_ULT; 535 case ISD::SETULE: return Mips::FCOND_ULE; 536 case ISD::SETUGT: return Mips::FCOND_UGT; 537 case ISD::SETUGE: return Mips::FCOND_UGE; 538 case ISD::SETUO: return Mips::FCOND_UN; 539 case ISD::SETO: return Mips::FCOND_OR; 540 case ISD::SETNE: 541 case ISD::SETONE: return Mips::FCOND_ONE; 542 case ISD::SETUEQ: return Mips::FCOND_UEQ; 543 } 544 } 545 546 547 /// This function returns true if the floating point conditional branches and 548 /// conditional moves which use condition code CC should be inverted. 549 static bool invertFPCondCodeUser(Mips::CondCode CC) { 550 if (CC >= Mips::FCOND_F && CC <= Mips::FCOND_NGT) 551 return false; 552 553 assert((CC >= Mips::FCOND_T && CC <= Mips::FCOND_GT) && 554 "Illegal Condition Code"); 555 556 return true; 557 } 558 559 // Creates and returns an FPCmp node from a setcc node. 560 // Returns Op if setcc is not a floating point comparison. 561 static SDValue createFPCmp(SelectionDAG &DAG, const SDValue &Op) { 562 // must be a SETCC node 563 if (Op.getOpcode() != ISD::SETCC) 564 return Op; 565 566 SDValue LHS = Op.getOperand(0); 567 568 if (!LHS.getValueType().isFloatingPoint()) 569 return Op; 570 571 SDValue RHS = Op.getOperand(1); 572 SDLoc DL(Op); 573 574 // Assume the 3rd operand is a CondCodeSDNode. Add code to check the type of 575 // node if necessary. 576 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get(); 577 578 return DAG.getNode(MipsISD::FPCmp, DL, MVT::Glue, LHS, RHS, 579 DAG.getConstant(condCodeToFCC(CC), DL, MVT::i32)); 580 } 581 582 // Creates and returns a CMovFPT/F node. 583 static SDValue createCMovFP(SelectionDAG &DAG, SDValue Cond, SDValue True, 584 SDValue False, const SDLoc &DL) { 585 ConstantSDNode *CC = cast<ConstantSDNode>(Cond.getOperand(2)); 586 bool invert = invertFPCondCodeUser((Mips::CondCode)CC->getSExtValue()); 587 SDValue FCC0 = DAG.getRegister(Mips::FCC0, MVT::i32); 588 589 return DAG.getNode((invert ? MipsISD::CMovFP_F : MipsISD::CMovFP_T), DL, 590 True.getValueType(), True, FCC0, False, Cond); 591 } 592 593 static SDValue performSELECTCombine(SDNode *N, SelectionDAG &DAG, 594 TargetLowering::DAGCombinerInfo &DCI, 595 const MipsSubtarget &Subtarget) { 596 if (DCI.isBeforeLegalizeOps()) 597 return SDValue(); 598 599 SDValue SetCC = N->getOperand(0); 600 601 if ((SetCC.getOpcode() != ISD::SETCC) || 602 !SetCC.getOperand(0).getValueType().isInteger()) 603 return SDValue(); 604 605 SDValue False = N->getOperand(2); 606 EVT FalseTy = False.getValueType(); 607 608 if (!FalseTy.isInteger()) 609 return SDValue(); 610 611 ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(False); 612 613 // If the RHS (False) is 0, we swap the order of the operands 614 // of ISD::SELECT (obviously also inverting the condition) so that we can 615 // take advantage of conditional moves using the $0 register. 616 // Example: 617 // return (a != 0) ? x : 0; 618 // load $reg, x 619 // movz $reg, $0, a 620 if (!FalseC) 621 return SDValue(); 622 623 const SDLoc DL(N); 624 625 if (!FalseC->getZExtValue()) { 626 ISD::CondCode CC = cast<CondCodeSDNode>(SetCC.getOperand(2))->get(); 627 SDValue True = N->getOperand(1); 628 629 SetCC = DAG.getSetCC(DL, SetCC.getValueType(), SetCC.getOperand(0), 630 SetCC.getOperand(1), ISD::getSetCCInverse(CC, true)); 631 632 return DAG.getNode(ISD::SELECT, DL, FalseTy, SetCC, False, True); 633 } 634 635 // If both operands are integer constants there's a possibility that we 636 // can do some interesting optimizations. 637 SDValue True = N->getOperand(1); 638 ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(True); 639 640 if (!TrueC || !True.getValueType().isInteger()) 641 return SDValue(); 642 643 // We'll also ignore MVT::i64 operands as this optimizations proves 644 // to be ineffective because of the required sign extensions as the result 645 // of a SETCC operator is always MVT::i32 for non-vector types. 646 if (True.getValueType() == MVT::i64) 647 return SDValue(); 648 649 int64_t Diff = TrueC->getSExtValue() - FalseC->getSExtValue(); 650 651 // 1) (a < x) ? y : y-1 652 // slti $reg1, a, x 653 // addiu $reg2, $reg1, y-1 654 if (Diff == 1) 655 return DAG.getNode(ISD::ADD, DL, SetCC.getValueType(), SetCC, False); 656 657 // 2) (a < x) ? y-1 : y 658 // slti $reg1, a, x 659 // xor $reg1, $reg1, 1 660 // addiu $reg2, $reg1, y-1 661 if (Diff == -1) { 662 ISD::CondCode CC = cast<CondCodeSDNode>(SetCC.getOperand(2))->get(); 663 SetCC = DAG.getSetCC(DL, SetCC.getValueType(), SetCC.getOperand(0), 664 SetCC.getOperand(1), ISD::getSetCCInverse(CC, true)); 665 return DAG.getNode(ISD::ADD, DL, SetCC.getValueType(), SetCC, True); 666 } 667 668 // Couldn't optimize. 669 return SDValue(); 670 } 671 672 static SDValue performCMovFPCombine(SDNode *N, SelectionDAG &DAG, 673 TargetLowering::DAGCombinerInfo &DCI, 674 const MipsSubtarget &Subtarget) { 675 if (DCI.isBeforeLegalizeOps()) 676 return SDValue(); 677 678 SDValue ValueIfTrue = N->getOperand(0), ValueIfFalse = N->getOperand(2); 679 680 ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(ValueIfFalse); 681 if (!FalseC || FalseC->getZExtValue()) 682 return SDValue(); 683 684 // Since RHS (False) is 0, we swap the order of the True/False operands 685 // (obviously also inverting the condition) so that we can 686 // take advantage of conditional moves using the $0 register. 687 // Example: 688 // return (a != 0) ? x : 0; 689 // load $reg, x 690 // movz $reg, $0, a 691 unsigned Opc = (N->getOpcode() == MipsISD::CMovFP_T) ? MipsISD::CMovFP_F : 692 MipsISD::CMovFP_T; 693 694 SDValue FCC = N->getOperand(1), Glue = N->getOperand(3); 695 return DAG.getNode(Opc, SDLoc(N), ValueIfFalse.getValueType(), 696 ValueIfFalse, FCC, ValueIfTrue, Glue); 697 } 698 699 static SDValue performANDCombine(SDNode *N, SelectionDAG &DAG, 700 TargetLowering::DAGCombinerInfo &DCI, 701 const MipsSubtarget &Subtarget) { 702 // Pattern match EXT. 703 // $dst = and ((sra or srl) $src , pos), (2**size - 1) 704 // => ext $dst, $src, size, pos 705 if (DCI.isBeforeLegalizeOps() || !Subtarget.hasExtractInsert()) 706 return SDValue(); 707 708 SDValue ShiftRight = N->getOperand(0), Mask = N->getOperand(1); 709 unsigned ShiftRightOpc = ShiftRight.getOpcode(); 710 711 // Op's first operand must be a shift right. 712 if (ShiftRightOpc != ISD::SRA && ShiftRightOpc != ISD::SRL) 713 return SDValue(); 714 715 // The second operand of the shift must be an immediate. 716 ConstantSDNode *CN; 717 if (!(CN = dyn_cast<ConstantSDNode>(ShiftRight.getOperand(1)))) 718 return SDValue(); 719 720 uint64_t Pos = CN->getZExtValue(); 721 uint64_t SMPos, SMSize; 722 723 // Op's second operand must be a shifted mask. 724 if (!(CN = dyn_cast<ConstantSDNode>(Mask)) || 725 !isShiftedMask(CN->getZExtValue(), SMPos, SMSize)) 726 return SDValue(); 727 728 // Return if the shifted mask does not start at bit 0 or the sum of its size 729 // and Pos exceeds the word's size. 730 EVT ValTy = N->getValueType(0); 731 if (SMPos != 0 || Pos + SMSize > ValTy.getSizeInBits()) 732 return SDValue(); 733 734 SDLoc DL(N); 735 return DAG.getNode(MipsISD::Ext, DL, ValTy, 736 ShiftRight.getOperand(0), 737 DAG.getConstant(Pos, DL, MVT::i32), 738 DAG.getConstant(SMSize, DL, MVT::i32)); 739 } 740 741 static SDValue performORCombine(SDNode *N, SelectionDAG &DAG, 742 TargetLowering::DAGCombinerInfo &DCI, 743 const MipsSubtarget &Subtarget) { 744 // Pattern match INS. 745 // $dst = or (and $src1 , mask0), (and (shl $src, pos), mask1), 746 // where mask1 = (2**size - 1) << pos, mask0 = ~mask1 747 // => ins $dst, $src, size, pos, $src1 748 if (DCI.isBeforeLegalizeOps() || !Subtarget.hasExtractInsert()) 749 return SDValue(); 750 751 SDValue And0 = N->getOperand(0), And1 = N->getOperand(1); 752 uint64_t SMPos0, SMSize0, SMPos1, SMSize1; 753 ConstantSDNode *CN; 754 755 // See if Op's first operand matches (and $src1 , mask0). 756 if (And0.getOpcode() != ISD::AND) 757 return SDValue(); 758 759 if (!(CN = dyn_cast<ConstantSDNode>(And0.getOperand(1))) || 760 !isShiftedMask(~CN->getSExtValue(), SMPos0, SMSize0)) 761 return SDValue(); 762 763 // See if Op's second operand matches (and (shl $src, pos), mask1). 764 if (And1.getOpcode() != ISD::AND) 765 return SDValue(); 766 767 if (!(CN = dyn_cast<ConstantSDNode>(And1.getOperand(1))) || 768 !isShiftedMask(CN->getZExtValue(), SMPos1, SMSize1)) 769 return SDValue(); 770 771 // The shift masks must have the same position and size. 772 if (SMPos0 != SMPos1 || SMSize0 != SMSize1) 773 return SDValue(); 774 775 SDValue Shl = And1.getOperand(0); 776 if (Shl.getOpcode() != ISD::SHL) 777 return SDValue(); 778 779 if (!(CN = dyn_cast<ConstantSDNode>(Shl.getOperand(1)))) 780 return SDValue(); 781 782 unsigned Shamt = CN->getZExtValue(); 783 784 // Return if the shift amount and the first bit position of mask are not the 785 // same. 786 EVT ValTy = N->getValueType(0); 787 if ((Shamt != SMPos0) || (SMPos0 + SMSize0 > ValTy.getSizeInBits())) 788 return SDValue(); 789 790 SDLoc DL(N); 791 return DAG.getNode(MipsISD::Ins, DL, ValTy, Shl.getOperand(0), 792 DAG.getConstant(SMPos0, DL, MVT::i32), 793 DAG.getConstant(SMSize0, DL, MVT::i32), 794 And0.getOperand(0)); 795 } 796 797 static SDValue performADDCombine(SDNode *N, SelectionDAG &DAG, 798 TargetLowering::DAGCombinerInfo &DCI, 799 const MipsSubtarget &Subtarget) { 800 // (add v0, (add v1, abs_lo(tjt))) => (add (add v0, v1), abs_lo(tjt)) 801 802 if (DCI.isBeforeLegalizeOps()) 803 return SDValue(); 804 805 SDValue Add = N->getOperand(1); 806 807 if (Add.getOpcode() != ISD::ADD) 808 return SDValue(); 809 810 SDValue Lo = Add.getOperand(1); 811 812 if ((Lo.getOpcode() != MipsISD::Lo) || 813 (Lo.getOperand(0).getOpcode() != ISD::TargetJumpTable)) 814 return SDValue(); 815 816 EVT ValTy = N->getValueType(0); 817 SDLoc DL(N); 818 819 SDValue Add1 = DAG.getNode(ISD::ADD, DL, ValTy, N->getOperand(0), 820 Add.getOperand(0)); 821 return DAG.getNode(ISD::ADD, DL, ValTy, Add1, Lo); 822 } 823 824 static SDValue performAssertZextCombine(SDNode *N, SelectionDAG &DAG, 825 TargetLowering::DAGCombinerInfo &DCI, 826 const MipsSubtarget &Subtarget) { 827 SDValue N0 = N->getOperand(0); 828 EVT NarrowerVT = cast<VTSDNode>(N->getOperand(1))->getVT(); 829 830 if (N0.getOpcode() != ISD::TRUNCATE) 831 return SDValue(); 832 833 if (N0.getOperand(0).getOpcode() != ISD::AssertZext) 834 return SDValue(); 835 836 // fold (AssertZext (trunc (AssertZext x))) -> (trunc (AssertZext x)) 837 // if the type of the extension of the innermost AssertZext node is 838 // smaller from that of the outermost node, eg: 839 // (AssertZext:i32 (trunc:i32 (AssertZext:i64 X, i32)), i8) 840 // -> (trunc:i32 (AssertZext X, i8)) 841 SDValue WiderAssertZext = N0.getOperand(0); 842 EVT WiderVT = cast<VTSDNode>(WiderAssertZext->getOperand(1))->getVT(); 843 844 if (NarrowerVT.bitsLT(WiderVT)) { 845 SDValue NewAssertZext = DAG.getNode( 846 ISD::AssertZext, SDLoc(N), WiderAssertZext.getValueType(), 847 WiderAssertZext.getOperand(0), DAG.getValueType(NarrowerVT)); 848 return DAG.getNode(ISD::TRUNCATE, SDLoc(N), N->getValueType(0), 849 NewAssertZext); 850 } 851 852 return SDValue(); 853 } 854 855 SDValue MipsTargetLowering::PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) 856 const { 857 SelectionDAG &DAG = DCI.DAG; 858 unsigned Opc = N->getOpcode(); 859 860 switch (Opc) { 861 default: break; 862 case ISD::SDIVREM: 863 case ISD::UDIVREM: 864 return performDivRemCombine(N, DAG, DCI, Subtarget); 865 case ISD::SELECT: 866 return performSELECTCombine(N, DAG, DCI, Subtarget); 867 case MipsISD::CMovFP_F: 868 case MipsISD::CMovFP_T: 869 return performCMovFPCombine(N, DAG, DCI, Subtarget); 870 case ISD::AND: 871 return performANDCombine(N, DAG, DCI, Subtarget); 872 case ISD::OR: 873 return performORCombine(N, DAG, DCI, Subtarget); 874 case ISD::ADD: 875 return performADDCombine(N, DAG, DCI, Subtarget); 876 case ISD::AssertZext: 877 return performAssertZextCombine(N, DAG, DCI, Subtarget); 878 } 879 880 return SDValue(); 881 } 882 883 bool MipsTargetLowering::isCheapToSpeculateCttz() const { 884 return Subtarget.hasMips32(); 885 } 886 887 bool MipsTargetLowering::isCheapToSpeculateCtlz() const { 888 return Subtarget.hasMips32(); 889 } 890 891 void 892 MipsTargetLowering::LowerOperationWrapper(SDNode *N, 893 SmallVectorImpl<SDValue> &Results, 894 SelectionDAG &DAG) const { 895 SDValue Res = LowerOperation(SDValue(N, 0), DAG); 896 897 for (unsigned I = 0, E = Res->getNumValues(); I != E; ++I) 898 Results.push_back(Res.getValue(I)); 899 } 900 901 void 902 MipsTargetLowering::ReplaceNodeResults(SDNode *N, 903 SmallVectorImpl<SDValue> &Results, 904 SelectionDAG &DAG) const { 905 return LowerOperationWrapper(N, Results, DAG); 906 } 907 908 SDValue MipsTargetLowering:: 909 LowerOperation(SDValue Op, SelectionDAG &DAG) const 910 { 911 switch (Op.getOpcode()) 912 { 913 case ISD::BR_JT: return lowerBR_JT(Op, DAG); 914 case ISD::BRCOND: return lowerBRCOND(Op, DAG); 915 case ISD::ConstantPool: return lowerConstantPool(Op, DAG); 916 case ISD::GlobalAddress: return lowerGlobalAddress(Op, DAG); 917 case ISD::BlockAddress: return lowerBlockAddress(Op, DAG); 918 case ISD::GlobalTLSAddress: return lowerGlobalTLSAddress(Op, DAG); 919 case ISD::JumpTable: return lowerJumpTable(Op, DAG); 920 case ISD::SELECT: return lowerSELECT(Op, DAG); 921 case ISD::SETCC: return lowerSETCC(Op, DAG); 922 case ISD::VASTART: return lowerVASTART(Op, DAG); 923 case ISD::VAARG: return lowerVAARG(Op, DAG); 924 case ISD::FCOPYSIGN: return lowerFCOPYSIGN(Op, DAG); 925 case ISD::FRAMEADDR: return lowerFRAMEADDR(Op, DAG); 926 case ISD::RETURNADDR: return lowerRETURNADDR(Op, DAG); 927 case ISD::EH_RETURN: return lowerEH_RETURN(Op, DAG); 928 case ISD::ATOMIC_FENCE: return lowerATOMIC_FENCE(Op, DAG); 929 case ISD::SHL_PARTS: return lowerShiftLeftParts(Op, DAG); 930 case ISD::SRA_PARTS: return lowerShiftRightParts(Op, DAG, true); 931 case ISD::SRL_PARTS: return lowerShiftRightParts(Op, DAG, false); 932 case ISD::LOAD: return lowerLOAD(Op, DAG); 933 case ISD::STORE: return lowerSTORE(Op, DAG); 934 case ISD::EH_DWARF_CFA: return lowerEH_DWARF_CFA(Op, DAG); 935 case ISD::FP_TO_SINT: return lowerFP_TO_SINT(Op, DAG); 936 } 937 return SDValue(); 938 } 939 940 //===----------------------------------------------------------------------===// 941 // Lower helper functions 942 //===----------------------------------------------------------------------===// 943 944 // addLiveIn - This helper function adds the specified physical register to the 945 // MachineFunction as a live in value. It also creates a corresponding 946 // virtual register for it. 947 static unsigned 948 addLiveIn(MachineFunction &MF, unsigned PReg, const TargetRegisterClass *RC) 949 { 950 unsigned VReg = MF.getRegInfo().createVirtualRegister(RC); 951 MF.getRegInfo().addLiveIn(PReg, VReg); 952 return VReg; 953 } 954 955 static MachineBasicBlock *insertDivByZeroTrap(MachineInstr &MI, 956 MachineBasicBlock &MBB, 957 const TargetInstrInfo &TII, 958 bool Is64Bit, bool IsMicroMips) { 959 if (NoZeroDivCheck) 960 return &MBB; 961 962 // Insert instruction "teq $divisor_reg, $zero, 7". 963 MachineBasicBlock::iterator I(MI); 964 MachineInstrBuilder MIB; 965 MachineOperand &Divisor = MI.getOperand(2); 966 MIB = BuildMI(MBB, std::next(I), MI.getDebugLoc(), 967 TII.get(IsMicroMips ? Mips::TEQ_MM : Mips::TEQ)) 968 .addReg(Divisor.getReg(), getKillRegState(Divisor.isKill())) 969 .addReg(Mips::ZERO) 970 .addImm(7); 971 972 // Use the 32-bit sub-register if this is a 64-bit division. 973 if (Is64Bit) 974 MIB->getOperand(0).setSubReg(Mips::sub_32); 975 976 // Clear Divisor's kill flag. 977 Divisor.setIsKill(false); 978 979 // We would normally delete the original instruction here but in this case 980 // we only needed to inject an additional instruction rather than replace it. 981 982 return &MBB; 983 } 984 985 MachineBasicBlock * 986 MipsTargetLowering::EmitInstrWithCustomInserter(MachineInstr &MI, 987 MachineBasicBlock *BB) const { 988 switch (MI.getOpcode()) { 989 default: 990 llvm_unreachable("Unexpected instr type to insert"); 991 case Mips::ATOMIC_LOAD_ADD_I8: 992 return emitAtomicBinaryPartword(MI, BB, 1, Mips::ADDu); 993 case Mips::ATOMIC_LOAD_ADD_I16: 994 return emitAtomicBinaryPartword(MI, BB, 2, Mips::ADDu); 995 case Mips::ATOMIC_LOAD_ADD_I32: 996 return emitAtomicBinary(MI, BB, 4, Mips::ADDu); 997 case Mips::ATOMIC_LOAD_ADD_I64: 998 return emitAtomicBinary(MI, BB, 8, Mips::DADDu); 999 1000 case Mips::ATOMIC_LOAD_AND_I8: 1001 return emitAtomicBinaryPartword(MI, BB, 1, Mips::AND); 1002 case Mips::ATOMIC_LOAD_AND_I16: 1003 return emitAtomicBinaryPartword(MI, BB, 2, Mips::AND); 1004 case Mips::ATOMIC_LOAD_AND_I32: 1005 return emitAtomicBinary(MI, BB, 4, Mips::AND); 1006 case Mips::ATOMIC_LOAD_AND_I64: 1007 return emitAtomicBinary(MI, BB, 8, Mips::AND64); 1008 1009 case Mips::ATOMIC_LOAD_OR_I8: 1010 return emitAtomicBinaryPartword(MI, BB, 1, Mips::OR); 1011 case Mips::ATOMIC_LOAD_OR_I16: 1012 return emitAtomicBinaryPartword(MI, BB, 2, Mips::OR); 1013 case Mips::ATOMIC_LOAD_OR_I32: 1014 return emitAtomicBinary(MI, BB, 4, Mips::OR); 1015 case Mips::ATOMIC_LOAD_OR_I64: 1016 return emitAtomicBinary(MI, BB, 8, Mips::OR64); 1017 1018 case Mips::ATOMIC_LOAD_XOR_I8: 1019 return emitAtomicBinaryPartword(MI, BB, 1, Mips::XOR); 1020 case Mips::ATOMIC_LOAD_XOR_I16: 1021 return emitAtomicBinaryPartword(MI, BB, 2, Mips::XOR); 1022 case Mips::ATOMIC_LOAD_XOR_I32: 1023 return emitAtomicBinary(MI, BB, 4, Mips::XOR); 1024 case Mips::ATOMIC_LOAD_XOR_I64: 1025 return emitAtomicBinary(MI, BB, 8, Mips::XOR64); 1026 1027 case Mips::ATOMIC_LOAD_NAND_I8: 1028 return emitAtomicBinaryPartword(MI, BB, 1, 0, true); 1029 case Mips::ATOMIC_LOAD_NAND_I16: 1030 return emitAtomicBinaryPartword(MI, BB, 2, 0, true); 1031 case Mips::ATOMIC_LOAD_NAND_I32: 1032 return emitAtomicBinary(MI, BB, 4, 0, true); 1033 case Mips::ATOMIC_LOAD_NAND_I64: 1034 return emitAtomicBinary(MI, BB, 8, 0, true); 1035 1036 case Mips::ATOMIC_LOAD_SUB_I8: 1037 return emitAtomicBinaryPartword(MI, BB, 1, Mips::SUBu); 1038 case Mips::ATOMIC_LOAD_SUB_I16: 1039 return emitAtomicBinaryPartword(MI, BB, 2, Mips::SUBu); 1040 case Mips::ATOMIC_LOAD_SUB_I32: 1041 return emitAtomicBinary(MI, BB, 4, Mips::SUBu); 1042 case Mips::ATOMIC_LOAD_SUB_I64: 1043 return emitAtomicBinary(MI, BB, 8, Mips::DSUBu); 1044 1045 case Mips::ATOMIC_SWAP_I8: 1046 return emitAtomicBinaryPartword(MI, BB, 1, 0); 1047 case Mips::ATOMIC_SWAP_I16: 1048 return emitAtomicBinaryPartword(MI, BB, 2, 0); 1049 case Mips::ATOMIC_SWAP_I32: 1050 return emitAtomicBinary(MI, BB, 4, 0); 1051 case Mips::ATOMIC_SWAP_I64: 1052 return emitAtomicBinary(MI, BB, 8, 0); 1053 1054 case Mips::ATOMIC_CMP_SWAP_I8: 1055 return emitAtomicCmpSwapPartword(MI, BB, 1); 1056 case Mips::ATOMIC_CMP_SWAP_I16: 1057 return emitAtomicCmpSwapPartword(MI, BB, 2); 1058 case Mips::ATOMIC_CMP_SWAP_I32: 1059 return emitAtomicCmpSwap(MI, BB, 4); 1060 case Mips::ATOMIC_CMP_SWAP_I64: 1061 return emitAtomicCmpSwap(MI, BB, 8); 1062 case Mips::PseudoSDIV: 1063 case Mips::PseudoUDIV: 1064 case Mips::DIV: 1065 case Mips::DIVU: 1066 case Mips::MOD: 1067 case Mips::MODU: 1068 return insertDivByZeroTrap(MI, *BB, *Subtarget.getInstrInfo(), false, 1069 false); 1070 case Mips::SDIV_MM_Pseudo: 1071 case Mips::UDIV_MM_Pseudo: 1072 case Mips::SDIV_MM: 1073 case Mips::UDIV_MM: 1074 case Mips::DIV_MMR6: 1075 case Mips::DIVU_MMR6: 1076 case Mips::MOD_MMR6: 1077 case Mips::MODU_MMR6: 1078 return insertDivByZeroTrap(MI, *BB, *Subtarget.getInstrInfo(), false, true); 1079 case Mips::PseudoDSDIV: 1080 case Mips::PseudoDUDIV: 1081 case Mips::DDIV: 1082 case Mips::DDIVU: 1083 case Mips::DMOD: 1084 case Mips::DMODU: 1085 return insertDivByZeroTrap(MI, *BB, *Subtarget.getInstrInfo(), true, false); 1086 case Mips::DDIV_MM64R6: 1087 case Mips::DDIVU_MM64R6: 1088 case Mips::DMOD_MM64R6: 1089 case Mips::DMODU_MM64R6: 1090 return insertDivByZeroTrap(MI, *BB, *Subtarget.getInstrInfo(), true, true); 1091 case Mips::SEL_D: 1092 case Mips::SEL_D_MMR6: 1093 return emitSEL_D(MI, BB); 1094 1095 case Mips::PseudoSELECT_I: 1096 case Mips::PseudoSELECT_I64: 1097 case Mips::PseudoSELECT_S: 1098 case Mips::PseudoSELECT_D32: 1099 case Mips::PseudoSELECT_D64: 1100 return emitPseudoSELECT(MI, BB, false, Mips::BNE); 1101 case Mips::PseudoSELECTFP_F_I: 1102 case Mips::PseudoSELECTFP_F_I64: 1103 case Mips::PseudoSELECTFP_F_S: 1104 case Mips::PseudoSELECTFP_F_D32: 1105 case Mips::PseudoSELECTFP_F_D64: 1106 return emitPseudoSELECT(MI, BB, true, Mips::BC1F); 1107 case Mips::PseudoSELECTFP_T_I: 1108 case Mips::PseudoSELECTFP_T_I64: 1109 case Mips::PseudoSELECTFP_T_S: 1110 case Mips::PseudoSELECTFP_T_D32: 1111 case Mips::PseudoSELECTFP_T_D64: 1112 return emitPseudoSELECT(MI, BB, true, Mips::BC1T); 1113 } 1114 } 1115 1116 // This function also handles Mips::ATOMIC_SWAP_I32 (when BinOpcode == 0), and 1117 // Mips::ATOMIC_LOAD_NAND_I32 (when Nand == true) 1118 MachineBasicBlock *MipsTargetLowering::emitAtomicBinary(MachineInstr &MI, 1119 MachineBasicBlock *BB, 1120 unsigned Size, 1121 unsigned BinOpcode, 1122 bool Nand) const { 1123 assert((Size == 4 || Size == 8) && "Unsupported size for EmitAtomicBinary."); 1124 1125 MachineFunction *MF = BB->getParent(); 1126 MachineRegisterInfo &RegInfo = MF->getRegInfo(); 1127 const TargetRegisterClass *RC = getRegClassFor(MVT::getIntegerVT(Size * 8)); 1128 const TargetInstrInfo *TII = Subtarget.getInstrInfo(); 1129 const bool ArePtrs64bit = ABI.ArePtrs64bit(); 1130 DebugLoc DL = MI.getDebugLoc(); 1131 unsigned LL, SC, AND, NOR, ZERO, BEQ; 1132 1133 if (Size == 4) { 1134 if (isMicroMips) { 1135 LL = Mips::LL_MM; 1136 SC = Mips::SC_MM; 1137 } else { 1138 LL = Subtarget.hasMips32r6() 1139 ? (ArePtrs64bit ? Mips::LL64_R6 : Mips::LL_R6) 1140 : (ArePtrs64bit ? Mips::LL64 : Mips::LL); 1141 SC = Subtarget.hasMips32r6() 1142 ? (ArePtrs64bit ? Mips::SC64_R6 : Mips::SC_R6) 1143 : (ArePtrs64bit ? Mips::SC64 : Mips::SC); 1144 } 1145 1146 AND = Mips::AND; 1147 NOR = Mips::NOR; 1148 ZERO = Mips::ZERO; 1149 BEQ = Mips::BEQ; 1150 } else { 1151 LL = Subtarget.hasMips64r6() ? Mips::LLD_R6 : Mips::LLD; 1152 SC = Subtarget.hasMips64r6() ? Mips::SCD_R6 : Mips::SCD; 1153 AND = Mips::AND64; 1154 NOR = Mips::NOR64; 1155 ZERO = Mips::ZERO_64; 1156 BEQ = Mips::BEQ64; 1157 } 1158 1159 unsigned OldVal = MI.getOperand(0).getReg(); 1160 unsigned Ptr = MI.getOperand(1).getReg(); 1161 unsigned Incr = MI.getOperand(2).getReg(); 1162 1163 unsigned StoreVal = RegInfo.createVirtualRegister(RC); 1164 unsigned AndRes = RegInfo.createVirtualRegister(RC); 1165 unsigned Success = RegInfo.createVirtualRegister(RC); 1166 1167 // insert new blocks after the current block 1168 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 1169 MachineBasicBlock *loopMBB = MF->CreateMachineBasicBlock(LLVM_BB); 1170 MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB); 1171 MachineFunction::iterator It = ++BB->getIterator(); 1172 MF->insert(It, loopMBB); 1173 MF->insert(It, exitMBB); 1174 1175 // Transfer the remainder of BB and its successor edges to exitMBB. 1176 exitMBB->splice(exitMBB->begin(), BB, 1177 std::next(MachineBasicBlock::iterator(MI)), BB->end()); 1178 exitMBB->transferSuccessorsAndUpdatePHIs(BB); 1179 1180 // thisMBB: 1181 // ... 1182 // fallthrough --> loopMBB 1183 BB->addSuccessor(loopMBB); 1184 loopMBB->addSuccessor(loopMBB); 1185 loopMBB->addSuccessor(exitMBB); 1186 1187 // loopMBB: 1188 // ll oldval, 0(ptr) 1189 // <binop> storeval, oldval, incr 1190 // sc success, storeval, 0(ptr) 1191 // beq success, $0, loopMBB 1192 BB = loopMBB; 1193 BuildMI(BB, DL, TII->get(LL), OldVal).addReg(Ptr).addImm(0); 1194 if (Nand) { 1195 // and andres, oldval, incr 1196 // nor storeval, $0, andres 1197 BuildMI(BB, DL, TII->get(AND), AndRes).addReg(OldVal).addReg(Incr); 1198 BuildMI(BB, DL, TII->get(NOR), StoreVal).addReg(ZERO).addReg(AndRes); 1199 } else if (BinOpcode) { 1200 // <binop> storeval, oldval, incr 1201 BuildMI(BB, DL, TII->get(BinOpcode), StoreVal).addReg(OldVal).addReg(Incr); 1202 } else { 1203 StoreVal = Incr; 1204 } 1205 BuildMI(BB, DL, TII->get(SC), Success).addReg(StoreVal).addReg(Ptr).addImm(0); 1206 BuildMI(BB, DL, TII->get(BEQ)).addReg(Success).addReg(ZERO).addMBB(loopMBB); 1207 1208 MI.eraseFromParent(); // The instruction is gone now. 1209 1210 return exitMBB; 1211 } 1212 1213 MachineBasicBlock *MipsTargetLowering::emitSignExtendToI32InReg( 1214 MachineInstr &MI, MachineBasicBlock *BB, unsigned Size, unsigned DstReg, 1215 unsigned SrcReg) const { 1216 const TargetInstrInfo *TII = Subtarget.getInstrInfo(); 1217 const DebugLoc &DL = MI.getDebugLoc(); 1218 1219 if (Subtarget.hasMips32r2() && Size == 1) { 1220 BuildMI(BB, DL, TII->get(Mips::SEB), DstReg).addReg(SrcReg); 1221 return BB; 1222 } 1223 1224 if (Subtarget.hasMips32r2() && Size == 2) { 1225 BuildMI(BB, DL, TII->get(Mips::SEH), DstReg).addReg(SrcReg); 1226 return BB; 1227 } 1228 1229 MachineFunction *MF = BB->getParent(); 1230 MachineRegisterInfo &RegInfo = MF->getRegInfo(); 1231 const TargetRegisterClass *RC = getRegClassFor(MVT::i32); 1232 unsigned ScrReg = RegInfo.createVirtualRegister(RC); 1233 1234 assert(Size < 32); 1235 int64_t ShiftImm = 32 - (Size * 8); 1236 1237 BuildMI(BB, DL, TII->get(Mips::SLL), ScrReg).addReg(SrcReg).addImm(ShiftImm); 1238 BuildMI(BB, DL, TII->get(Mips::SRA), DstReg).addReg(ScrReg).addImm(ShiftImm); 1239 1240 return BB; 1241 } 1242 1243 MachineBasicBlock *MipsTargetLowering::emitAtomicBinaryPartword( 1244 MachineInstr &MI, MachineBasicBlock *BB, unsigned Size, unsigned BinOpcode, 1245 bool Nand) const { 1246 assert((Size == 1 || Size == 2) && 1247 "Unsupported size for EmitAtomicBinaryPartial."); 1248 1249 MachineFunction *MF = BB->getParent(); 1250 MachineRegisterInfo &RegInfo = MF->getRegInfo(); 1251 const TargetRegisterClass *RC = getRegClassFor(MVT::i32); 1252 const bool ArePtrs64bit = ABI.ArePtrs64bit(); 1253 const TargetRegisterClass *RCp = 1254 getRegClassFor(ArePtrs64bit ? MVT::i64 : MVT::i32); 1255 const TargetInstrInfo *TII = Subtarget.getInstrInfo(); 1256 DebugLoc DL = MI.getDebugLoc(); 1257 1258 unsigned Dest = MI.getOperand(0).getReg(); 1259 unsigned Ptr = MI.getOperand(1).getReg(); 1260 unsigned Incr = MI.getOperand(2).getReg(); 1261 1262 unsigned AlignedAddr = RegInfo.createVirtualRegister(RCp); 1263 unsigned ShiftAmt = RegInfo.createVirtualRegister(RC); 1264 unsigned Mask = RegInfo.createVirtualRegister(RC); 1265 unsigned Mask2 = RegInfo.createVirtualRegister(RC); 1266 unsigned NewVal = RegInfo.createVirtualRegister(RC); 1267 unsigned OldVal = RegInfo.createVirtualRegister(RC); 1268 unsigned Incr2 = RegInfo.createVirtualRegister(RC); 1269 unsigned MaskLSB2 = RegInfo.createVirtualRegister(RCp); 1270 unsigned PtrLSB2 = RegInfo.createVirtualRegister(RC); 1271 unsigned MaskUpper = RegInfo.createVirtualRegister(RC); 1272 unsigned AndRes = RegInfo.createVirtualRegister(RC); 1273 unsigned BinOpRes = RegInfo.createVirtualRegister(RC); 1274 unsigned MaskedOldVal0 = RegInfo.createVirtualRegister(RC); 1275 unsigned StoreVal = RegInfo.createVirtualRegister(RC); 1276 unsigned MaskedOldVal1 = RegInfo.createVirtualRegister(RC); 1277 unsigned SrlRes = RegInfo.createVirtualRegister(RC); 1278 unsigned Success = RegInfo.createVirtualRegister(RC); 1279 1280 unsigned LL, SC; 1281 if (isMicroMips) { 1282 LL = Mips::LL_MM; 1283 SC = Mips::SC_MM; 1284 } else { 1285 LL = Subtarget.hasMips32r6() ? (ArePtrs64bit ? Mips::LL64_R6 : Mips::LL_R6) 1286 : (ArePtrs64bit ? Mips::LL64 : Mips::LL); 1287 SC = Subtarget.hasMips32r6() ? (ArePtrs64bit ? Mips::SC64_R6 : Mips::SC_R6) 1288 : (ArePtrs64bit ? Mips::SC64 : Mips::SC); 1289 } 1290 1291 // insert new blocks after the current block 1292 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 1293 MachineBasicBlock *loopMBB = MF->CreateMachineBasicBlock(LLVM_BB); 1294 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(LLVM_BB); 1295 MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB); 1296 MachineFunction::iterator It = ++BB->getIterator(); 1297 MF->insert(It, loopMBB); 1298 MF->insert(It, sinkMBB); 1299 MF->insert(It, exitMBB); 1300 1301 // Transfer the remainder of BB and its successor edges to exitMBB. 1302 exitMBB->splice(exitMBB->begin(), BB, 1303 std::next(MachineBasicBlock::iterator(MI)), BB->end()); 1304 exitMBB->transferSuccessorsAndUpdatePHIs(BB); 1305 1306 BB->addSuccessor(loopMBB); 1307 loopMBB->addSuccessor(loopMBB); 1308 loopMBB->addSuccessor(sinkMBB); 1309 sinkMBB->addSuccessor(exitMBB); 1310 1311 // thisMBB: 1312 // addiu masklsb2,$0,-4 # 0xfffffffc 1313 // and alignedaddr,ptr,masklsb2 1314 // andi ptrlsb2,ptr,3 1315 // sll shiftamt,ptrlsb2,3 1316 // ori maskupper,$0,255 # 0xff 1317 // sll mask,maskupper,shiftamt 1318 // nor mask2,$0,mask 1319 // sll incr2,incr,shiftamt 1320 1321 int64_t MaskImm = (Size == 1) ? 255 : 65535; 1322 BuildMI(BB, DL, TII->get(ABI.GetPtrAddiuOp()), MaskLSB2) 1323 .addReg(ABI.GetNullPtr()).addImm(-4); 1324 BuildMI(BB, DL, TII->get(ABI.GetPtrAndOp()), AlignedAddr) 1325 .addReg(Ptr).addReg(MaskLSB2); 1326 BuildMI(BB, DL, TII->get(Mips::ANDi), PtrLSB2) 1327 .addReg(Ptr, 0, ArePtrs64bit ? Mips::sub_32 : 0).addImm(3); 1328 if (Subtarget.isLittle()) { 1329 BuildMI(BB, DL, TII->get(Mips::SLL), ShiftAmt).addReg(PtrLSB2).addImm(3); 1330 } else { 1331 unsigned Off = RegInfo.createVirtualRegister(RC); 1332 BuildMI(BB, DL, TII->get(Mips::XORi), Off) 1333 .addReg(PtrLSB2).addImm((Size == 1) ? 3 : 2); 1334 BuildMI(BB, DL, TII->get(Mips::SLL), ShiftAmt).addReg(Off).addImm(3); 1335 } 1336 BuildMI(BB, DL, TII->get(Mips::ORi), MaskUpper) 1337 .addReg(Mips::ZERO).addImm(MaskImm); 1338 BuildMI(BB, DL, TII->get(Mips::SLLV), Mask) 1339 .addReg(MaskUpper).addReg(ShiftAmt); 1340 BuildMI(BB, DL, TII->get(Mips::NOR), Mask2).addReg(Mips::ZERO).addReg(Mask); 1341 BuildMI(BB, DL, TII->get(Mips::SLLV), Incr2).addReg(Incr).addReg(ShiftAmt); 1342 1343 // atomic.load.binop 1344 // loopMBB: 1345 // ll oldval,0(alignedaddr) 1346 // binop binopres,oldval,incr2 1347 // and newval,binopres,mask 1348 // and maskedoldval0,oldval,mask2 1349 // or storeval,maskedoldval0,newval 1350 // sc success,storeval,0(alignedaddr) 1351 // beq success,$0,loopMBB 1352 1353 // atomic.swap 1354 // loopMBB: 1355 // ll oldval,0(alignedaddr) 1356 // and newval,incr2,mask 1357 // and maskedoldval0,oldval,mask2 1358 // or storeval,maskedoldval0,newval 1359 // sc success,storeval,0(alignedaddr) 1360 // beq success,$0,loopMBB 1361 1362 BB = loopMBB; 1363 BuildMI(BB, DL, TII->get(LL), OldVal).addReg(AlignedAddr).addImm(0); 1364 if (Nand) { 1365 // and andres, oldval, incr2 1366 // nor binopres, $0, andres 1367 // and newval, binopres, mask 1368 BuildMI(BB, DL, TII->get(Mips::AND), AndRes).addReg(OldVal).addReg(Incr2); 1369 BuildMI(BB, DL, TII->get(Mips::NOR), BinOpRes) 1370 .addReg(Mips::ZERO).addReg(AndRes); 1371 BuildMI(BB, DL, TII->get(Mips::AND), NewVal).addReg(BinOpRes).addReg(Mask); 1372 } else if (BinOpcode) { 1373 // <binop> binopres, oldval, incr2 1374 // and newval, binopres, mask 1375 BuildMI(BB, DL, TII->get(BinOpcode), BinOpRes).addReg(OldVal).addReg(Incr2); 1376 BuildMI(BB, DL, TII->get(Mips::AND), NewVal).addReg(BinOpRes).addReg(Mask); 1377 } else { // atomic.swap 1378 // and newval, incr2, mask 1379 BuildMI(BB, DL, TII->get(Mips::AND), NewVal).addReg(Incr2).addReg(Mask); 1380 } 1381 1382 BuildMI(BB, DL, TII->get(Mips::AND), MaskedOldVal0) 1383 .addReg(OldVal).addReg(Mask2); 1384 BuildMI(BB, DL, TII->get(Mips::OR), StoreVal) 1385 .addReg(MaskedOldVal0).addReg(NewVal); 1386 BuildMI(BB, DL, TII->get(SC), Success) 1387 .addReg(StoreVal).addReg(AlignedAddr).addImm(0); 1388 BuildMI(BB, DL, TII->get(Mips::BEQ)) 1389 .addReg(Success).addReg(Mips::ZERO).addMBB(loopMBB); 1390 1391 // sinkMBB: 1392 // and maskedoldval1,oldval,mask 1393 // srl srlres,maskedoldval1,shiftamt 1394 // sign_extend dest,srlres 1395 BB = sinkMBB; 1396 1397 BuildMI(BB, DL, TII->get(Mips::AND), MaskedOldVal1) 1398 .addReg(OldVal).addReg(Mask); 1399 BuildMI(BB, DL, TII->get(Mips::SRLV), SrlRes) 1400 .addReg(MaskedOldVal1).addReg(ShiftAmt); 1401 BB = emitSignExtendToI32InReg(MI, BB, Size, Dest, SrlRes); 1402 1403 MI.eraseFromParent(); // The instruction is gone now. 1404 1405 return exitMBB; 1406 } 1407 1408 MachineBasicBlock *MipsTargetLowering::emitAtomicCmpSwap(MachineInstr &MI, 1409 MachineBasicBlock *BB, 1410 unsigned Size) const { 1411 assert((Size == 4 || Size == 8) && "Unsupported size for EmitAtomicCmpSwap."); 1412 1413 MachineFunction *MF = BB->getParent(); 1414 MachineRegisterInfo &RegInfo = MF->getRegInfo(); 1415 const TargetRegisterClass *RC = getRegClassFor(MVT::getIntegerVT(Size * 8)); 1416 const TargetInstrInfo *TII = Subtarget.getInstrInfo(); 1417 const bool ArePtrs64bit = ABI.ArePtrs64bit(); 1418 DebugLoc DL = MI.getDebugLoc(); 1419 unsigned LL, SC, ZERO, BNE, BEQ; 1420 1421 if (Size == 4) { 1422 if (isMicroMips) { 1423 LL = Mips::LL_MM; 1424 SC = Mips::SC_MM; 1425 } else { 1426 LL = Subtarget.hasMips32r6() 1427 ? (ArePtrs64bit ? Mips::LL64_R6 : Mips::LL_R6) 1428 : (ArePtrs64bit ? Mips::LL64 : Mips::LL); 1429 SC = Subtarget.hasMips32r6() 1430 ? (ArePtrs64bit ? Mips::SC64_R6 : Mips::SC_R6) 1431 : (ArePtrs64bit ? Mips::SC64 : Mips::SC); 1432 } 1433 1434 ZERO = Mips::ZERO; 1435 BNE = Mips::BNE; 1436 BEQ = Mips::BEQ; 1437 } else { 1438 LL = Subtarget.hasMips64r6() ? Mips::LLD_R6 : Mips::LLD; 1439 SC = Subtarget.hasMips64r6() ? Mips::SCD_R6 : Mips::SCD; 1440 ZERO = Mips::ZERO_64; 1441 BNE = Mips::BNE64; 1442 BEQ = Mips::BEQ64; 1443 } 1444 1445 unsigned Dest = MI.getOperand(0).getReg(); 1446 unsigned Ptr = MI.getOperand(1).getReg(); 1447 unsigned OldVal = MI.getOperand(2).getReg(); 1448 unsigned NewVal = MI.getOperand(3).getReg(); 1449 1450 unsigned Success = RegInfo.createVirtualRegister(RC); 1451 1452 // insert new blocks after the current block 1453 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 1454 MachineBasicBlock *loop1MBB = MF->CreateMachineBasicBlock(LLVM_BB); 1455 MachineBasicBlock *loop2MBB = MF->CreateMachineBasicBlock(LLVM_BB); 1456 MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB); 1457 MachineFunction::iterator It = ++BB->getIterator(); 1458 MF->insert(It, loop1MBB); 1459 MF->insert(It, loop2MBB); 1460 MF->insert(It, exitMBB); 1461 1462 // Transfer the remainder of BB and its successor edges to exitMBB. 1463 exitMBB->splice(exitMBB->begin(), BB, 1464 std::next(MachineBasicBlock::iterator(MI)), BB->end()); 1465 exitMBB->transferSuccessorsAndUpdatePHIs(BB); 1466 1467 // thisMBB: 1468 // ... 1469 // fallthrough --> loop1MBB 1470 BB->addSuccessor(loop1MBB); 1471 loop1MBB->addSuccessor(exitMBB); 1472 loop1MBB->addSuccessor(loop2MBB); 1473 loop2MBB->addSuccessor(loop1MBB); 1474 loop2MBB->addSuccessor(exitMBB); 1475 1476 // loop1MBB: 1477 // ll dest, 0(ptr) 1478 // bne dest, oldval, exitMBB 1479 BB = loop1MBB; 1480 BuildMI(BB, DL, TII->get(LL), Dest).addReg(Ptr).addImm(0); 1481 BuildMI(BB, DL, TII->get(BNE)) 1482 .addReg(Dest).addReg(OldVal).addMBB(exitMBB); 1483 1484 // loop2MBB: 1485 // sc success, newval, 0(ptr) 1486 // beq success, $0, loop1MBB 1487 BB = loop2MBB; 1488 BuildMI(BB, DL, TII->get(SC), Success) 1489 .addReg(NewVal).addReg(Ptr).addImm(0); 1490 BuildMI(BB, DL, TII->get(BEQ)) 1491 .addReg(Success).addReg(ZERO).addMBB(loop1MBB); 1492 1493 MI.eraseFromParent(); // The instruction is gone now. 1494 1495 return exitMBB; 1496 } 1497 1498 MachineBasicBlock *MipsTargetLowering::emitAtomicCmpSwapPartword( 1499 MachineInstr &MI, MachineBasicBlock *BB, unsigned Size) const { 1500 assert((Size == 1 || Size == 2) && 1501 "Unsupported size for EmitAtomicCmpSwapPartial."); 1502 1503 MachineFunction *MF = BB->getParent(); 1504 MachineRegisterInfo &RegInfo = MF->getRegInfo(); 1505 const TargetRegisterClass *RC = getRegClassFor(MVT::i32); 1506 const bool ArePtrs64bit = ABI.ArePtrs64bit(); 1507 const TargetRegisterClass *RCp = 1508 getRegClassFor(ArePtrs64bit ? MVT::i64 : MVT::i32); 1509 const TargetInstrInfo *TII = Subtarget.getInstrInfo(); 1510 DebugLoc DL = MI.getDebugLoc(); 1511 1512 unsigned Dest = MI.getOperand(0).getReg(); 1513 unsigned Ptr = MI.getOperand(1).getReg(); 1514 unsigned CmpVal = MI.getOperand(2).getReg(); 1515 unsigned NewVal = MI.getOperand(3).getReg(); 1516 1517 unsigned AlignedAddr = RegInfo.createVirtualRegister(RCp); 1518 unsigned ShiftAmt = RegInfo.createVirtualRegister(RC); 1519 unsigned Mask = RegInfo.createVirtualRegister(RC); 1520 unsigned Mask2 = RegInfo.createVirtualRegister(RC); 1521 unsigned ShiftedCmpVal = RegInfo.createVirtualRegister(RC); 1522 unsigned OldVal = RegInfo.createVirtualRegister(RC); 1523 unsigned MaskedOldVal0 = RegInfo.createVirtualRegister(RC); 1524 unsigned ShiftedNewVal = RegInfo.createVirtualRegister(RC); 1525 unsigned MaskLSB2 = RegInfo.createVirtualRegister(RCp); 1526 unsigned PtrLSB2 = RegInfo.createVirtualRegister(RC); 1527 unsigned MaskUpper = RegInfo.createVirtualRegister(RC); 1528 unsigned MaskedCmpVal = RegInfo.createVirtualRegister(RC); 1529 unsigned MaskedNewVal = RegInfo.createVirtualRegister(RC); 1530 unsigned MaskedOldVal1 = RegInfo.createVirtualRegister(RC); 1531 unsigned StoreVal = RegInfo.createVirtualRegister(RC); 1532 unsigned SrlRes = RegInfo.createVirtualRegister(RC); 1533 unsigned Success = RegInfo.createVirtualRegister(RC); 1534 unsigned LL, SC; 1535 1536 if (isMicroMips) { 1537 LL = Mips::LL_MM; 1538 SC = Mips::SC_MM; 1539 } else { 1540 LL = Subtarget.hasMips32r6() ? (ArePtrs64bit ? Mips::LL64_R6 : Mips::LL_R6) 1541 : (ArePtrs64bit ? Mips::LL64 : Mips::LL); 1542 SC = Subtarget.hasMips32r6() ? (ArePtrs64bit ? Mips::SC64_R6 : Mips::SC_R6) 1543 : (ArePtrs64bit ? Mips::SC64 : Mips::SC); 1544 } 1545 1546 // insert new blocks after the current block 1547 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 1548 MachineBasicBlock *loop1MBB = MF->CreateMachineBasicBlock(LLVM_BB); 1549 MachineBasicBlock *loop2MBB = MF->CreateMachineBasicBlock(LLVM_BB); 1550 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(LLVM_BB); 1551 MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB); 1552 MachineFunction::iterator It = ++BB->getIterator(); 1553 MF->insert(It, loop1MBB); 1554 MF->insert(It, loop2MBB); 1555 MF->insert(It, sinkMBB); 1556 MF->insert(It, exitMBB); 1557 1558 // Transfer the remainder of BB and its successor edges to exitMBB. 1559 exitMBB->splice(exitMBB->begin(), BB, 1560 std::next(MachineBasicBlock::iterator(MI)), BB->end()); 1561 exitMBB->transferSuccessorsAndUpdatePHIs(BB); 1562 1563 BB->addSuccessor(loop1MBB); 1564 loop1MBB->addSuccessor(sinkMBB); 1565 loop1MBB->addSuccessor(loop2MBB); 1566 loop2MBB->addSuccessor(loop1MBB); 1567 loop2MBB->addSuccessor(sinkMBB); 1568 sinkMBB->addSuccessor(exitMBB); 1569 1570 // FIXME: computation of newval2 can be moved to loop2MBB. 1571 // thisMBB: 1572 // addiu masklsb2,$0,-4 # 0xfffffffc 1573 // and alignedaddr,ptr,masklsb2 1574 // andi ptrlsb2,ptr,3 1575 // xori ptrlsb2,ptrlsb2,3 # Only for BE 1576 // sll shiftamt,ptrlsb2,3 1577 // ori maskupper,$0,255 # 0xff 1578 // sll mask,maskupper,shiftamt 1579 // nor mask2,$0,mask 1580 // andi maskedcmpval,cmpval,255 1581 // sll shiftedcmpval,maskedcmpval,shiftamt 1582 // andi maskednewval,newval,255 1583 // sll shiftednewval,maskednewval,shiftamt 1584 int64_t MaskImm = (Size == 1) ? 255 : 65535; 1585 BuildMI(BB, DL, TII->get(ArePtrs64bit ? Mips::DADDiu : Mips::ADDiu), MaskLSB2) 1586 .addReg(ABI.GetNullPtr()).addImm(-4); 1587 BuildMI(BB, DL, TII->get(ArePtrs64bit ? Mips::AND64 : Mips::AND), AlignedAddr) 1588 .addReg(Ptr).addReg(MaskLSB2); 1589 BuildMI(BB, DL, TII->get(Mips::ANDi), PtrLSB2) 1590 .addReg(Ptr, 0, ArePtrs64bit ? Mips::sub_32 : 0).addImm(3); 1591 if (Subtarget.isLittle()) { 1592 BuildMI(BB, DL, TII->get(Mips::SLL), ShiftAmt).addReg(PtrLSB2).addImm(3); 1593 } else { 1594 unsigned Off = RegInfo.createVirtualRegister(RC); 1595 BuildMI(BB, DL, TII->get(Mips::XORi), Off) 1596 .addReg(PtrLSB2).addImm((Size == 1) ? 3 : 2); 1597 BuildMI(BB, DL, TII->get(Mips::SLL), ShiftAmt).addReg(Off).addImm(3); 1598 } 1599 BuildMI(BB, DL, TII->get(Mips::ORi), MaskUpper) 1600 .addReg(Mips::ZERO).addImm(MaskImm); 1601 BuildMI(BB, DL, TII->get(Mips::SLLV), Mask) 1602 .addReg(MaskUpper).addReg(ShiftAmt); 1603 BuildMI(BB, DL, TII->get(Mips::NOR), Mask2).addReg(Mips::ZERO).addReg(Mask); 1604 BuildMI(BB, DL, TII->get(Mips::ANDi), MaskedCmpVal) 1605 .addReg(CmpVal).addImm(MaskImm); 1606 BuildMI(BB, DL, TII->get(Mips::SLLV), ShiftedCmpVal) 1607 .addReg(MaskedCmpVal).addReg(ShiftAmt); 1608 BuildMI(BB, DL, TII->get(Mips::ANDi), MaskedNewVal) 1609 .addReg(NewVal).addImm(MaskImm); 1610 BuildMI(BB, DL, TII->get(Mips::SLLV), ShiftedNewVal) 1611 .addReg(MaskedNewVal).addReg(ShiftAmt); 1612 1613 // loop1MBB: 1614 // ll oldval,0(alginedaddr) 1615 // and maskedoldval0,oldval,mask 1616 // bne maskedoldval0,shiftedcmpval,sinkMBB 1617 BB = loop1MBB; 1618 BuildMI(BB, DL, TII->get(LL), OldVal).addReg(AlignedAddr).addImm(0); 1619 BuildMI(BB, DL, TII->get(Mips::AND), MaskedOldVal0) 1620 .addReg(OldVal).addReg(Mask); 1621 BuildMI(BB, DL, TII->get(Mips::BNE)) 1622 .addReg(MaskedOldVal0).addReg(ShiftedCmpVal).addMBB(sinkMBB); 1623 1624 // loop2MBB: 1625 // and maskedoldval1,oldval,mask2 1626 // or storeval,maskedoldval1,shiftednewval 1627 // sc success,storeval,0(alignedaddr) 1628 // beq success,$0,loop1MBB 1629 BB = loop2MBB; 1630 BuildMI(BB, DL, TII->get(Mips::AND), MaskedOldVal1) 1631 .addReg(OldVal).addReg(Mask2); 1632 BuildMI(BB, DL, TII->get(Mips::OR), StoreVal) 1633 .addReg(MaskedOldVal1).addReg(ShiftedNewVal); 1634 BuildMI(BB, DL, TII->get(SC), Success) 1635 .addReg(StoreVal).addReg(AlignedAddr).addImm(0); 1636 BuildMI(BB, DL, TII->get(Mips::BEQ)) 1637 .addReg(Success).addReg(Mips::ZERO).addMBB(loop1MBB); 1638 1639 // sinkMBB: 1640 // srl srlres,maskedoldval0,shiftamt 1641 // sign_extend dest,srlres 1642 BB = sinkMBB; 1643 1644 BuildMI(BB, DL, TII->get(Mips::SRLV), SrlRes) 1645 .addReg(MaskedOldVal0).addReg(ShiftAmt); 1646 BB = emitSignExtendToI32InReg(MI, BB, Size, Dest, SrlRes); 1647 1648 MI.eraseFromParent(); // The instruction is gone now. 1649 1650 return exitMBB; 1651 } 1652 1653 MachineBasicBlock *MipsTargetLowering::emitSEL_D(MachineInstr &MI, 1654 MachineBasicBlock *BB) const { 1655 MachineFunction *MF = BB->getParent(); 1656 const TargetRegisterInfo *TRI = Subtarget.getRegisterInfo(); 1657 const TargetInstrInfo *TII = Subtarget.getInstrInfo(); 1658 MachineRegisterInfo &RegInfo = MF->getRegInfo(); 1659 DebugLoc DL = MI.getDebugLoc(); 1660 MachineBasicBlock::iterator II(MI); 1661 1662 unsigned Fc = MI.getOperand(1).getReg(); 1663 const auto &FGR64RegClass = TRI->getRegClass(Mips::FGR64RegClassID); 1664 1665 unsigned Fc2 = RegInfo.createVirtualRegister(FGR64RegClass); 1666 1667 BuildMI(*BB, II, DL, TII->get(Mips::SUBREG_TO_REG), Fc2) 1668 .addImm(0) 1669 .addReg(Fc) 1670 .addImm(Mips::sub_lo); 1671 1672 // We don't erase the original instruction, we just replace the condition 1673 // register with the 64-bit super-register. 1674 MI.getOperand(1).setReg(Fc2); 1675 1676 return BB; 1677 } 1678 1679 //===----------------------------------------------------------------------===// 1680 // Misc Lower Operation implementation 1681 //===----------------------------------------------------------------------===// 1682 SDValue MipsTargetLowering::lowerBR_JT(SDValue Op, SelectionDAG &DAG) const { 1683 SDValue Chain = Op.getOperand(0); 1684 SDValue Table = Op.getOperand(1); 1685 SDValue Index = Op.getOperand(2); 1686 SDLoc DL(Op); 1687 auto &TD = DAG.getDataLayout(); 1688 EVT PTy = getPointerTy(TD); 1689 unsigned EntrySize = 1690 DAG.getMachineFunction().getJumpTableInfo()->getEntrySize(TD); 1691 1692 Index = DAG.getNode(ISD::MUL, DL, PTy, Index, 1693 DAG.getConstant(EntrySize, DL, PTy)); 1694 SDValue Addr = DAG.getNode(ISD::ADD, DL, PTy, Index, Table); 1695 1696 EVT MemVT = EVT::getIntegerVT(*DAG.getContext(), EntrySize * 8); 1697 Addr = DAG.getExtLoad( 1698 ISD::SEXTLOAD, DL, PTy, Chain, Addr, 1699 MachinePointerInfo::getJumpTable(DAG.getMachineFunction()), MemVT); 1700 Chain = Addr.getValue(1); 1701 1702 if (isPositionIndependent() || ABI.IsN64()) { 1703 // For PIC, the sequence is: 1704 // BRIND(load(Jumptable + index) + RelocBase) 1705 // RelocBase can be JumpTable, GOT or some sort of global base. 1706 Addr = DAG.getNode(ISD::ADD, DL, PTy, Addr, 1707 getPICJumpTableRelocBase(Table, DAG)); 1708 } 1709 1710 return DAG.getNode(ISD::BRIND, DL, MVT::Other, Chain, Addr); 1711 } 1712 1713 SDValue MipsTargetLowering::lowerBRCOND(SDValue Op, SelectionDAG &DAG) const { 1714 // The first operand is the chain, the second is the condition, the third is 1715 // the block to branch to if the condition is true. 1716 SDValue Chain = Op.getOperand(0); 1717 SDValue Dest = Op.getOperand(2); 1718 SDLoc DL(Op); 1719 1720 assert(!Subtarget.hasMips32r6() && !Subtarget.hasMips64r6()); 1721 SDValue CondRes = createFPCmp(DAG, Op.getOperand(1)); 1722 1723 // Return if flag is not set by a floating point comparison. 1724 if (CondRes.getOpcode() != MipsISD::FPCmp) 1725 return Op; 1726 1727 SDValue CCNode = CondRes.getOperand(2); 1728 Mips::CondCode CC = 1729 (Mips::CondCode)cast<ConstantSDNode>(CCNode)->getZExtValue(); 1730 unsigned Opc = invertFPCondCodeUser(CC) ? Mips::BRANCH_F : Mips::BRANCH_T; 1731 SDValue BrCode = DAG.getConstant(Opc, DL, MVT::i32); 1732 SDValue FCC0 = DAG.getRegister(Mips::FCC0, MVT::i32); 1733 return DAG.getNode(MipsISD::FPBrcond, DL, Op.getValueType(), Chain, BrCode, 1734 FCC0, Dest, CondRes); 1735 } 1736 1737 SDValue MipsTargetLowering:: 1738 lowerSELECT(SDValue Op, SelectionDAG &DAG) const 1739 { 1740 assert(!Subtarget.hasMips32r6() && !Subtarget.hasMips64r6()); 1741 SDValue Cond = createFPCmp(DAG, Op.getOperand(0)); 1742 1743 // Return if flag is not set by a floating point comparison. 1744 if (Cond.getOpcode() != MipsISD::FPCmp) 1745 return Op; 1746 1747 return createCMovFP(DAG, Cond, Op.getOperand(1), Op.getOperand(2), 1748 SDLoc(Op)); 1749 } 1750 1751 SDValue MipsTargetLowering::lowerSETCC(SDValue Op, SelectionDAG &DAG) const { 1752 assert(!Subtarget.hasMips32r6() && !Subtarget.hasMips64r6()); 1753 SDValue Cond = createFPCmp(DAG, Op); 1754 1755 assert(Cond.getOpcode() == MipsISD::FPCmp && 1756 "Floating point operand expected."); 1757 1758 SDLoc DL(Op); 1759 SDValue True = DAG.getConstant(1, DL, MVT::i32); 1760 SDValue False = DAG.getConstant(0, DL, MVT::i32); 1761 1762 return createCMovFP(DAG, Cond, True, False, DL); 1763 } 1764 1765 SDValue MipsTargetLowering::lowerGlobalAddress(SDValue Op, 1766 SelectionDAG &DAG) const { 1767 EVT Ty = Op.getValueType(); 1768 GlobalAddressSDNode *N = cast<GlobalAddressSDNode>(Op); 1769 const GlobalValue *GV = N->getGlobal(); 1770 1771 if (!isPositionIndependent() && !ABI.IsN64()) { 1772 const MipsTargetObjectFile *TLOF = 1773 static_cast<const MipsTargetObjectFile *>( 1774 getTargetMachine().getObjFileLowering()); 1775 const GlobalObject *GO = GV->getBaseObject(); 1776 if (GO && TLOF->IsGlobalInSmallSection(GO, getTargetMachine())) 1777 // %gp_rel relocation 1778 return getAddrGPRel(N, SDLoc(N), Ty, DAG); 1779 1780 // %hi/%lo relocation 1781 return getAddrNonPIC(N, SDLoc(N), Ty, DAG); 1782 } 1783 1784 // Every other architecture would use shouldAssumeDSOLocal in here, but 1785 // mips is special. 1786 // * In PIC code mips requires got loads even for local statics! 1787 // * To save on got entries, for local statics the got entry contains the 1788 // page and an additional add instruction takes care of the low bits. 1789 // * It is legal to access a hidden symbol with a non hidden undefined, 1790 // so one cannot guarantee that all access to a hidden symbol will know 1791 // it is hidden. 1792 // * Mips linkers don't support creating a page and a full got entry for 1793 // the same symbol. 1794 // * Given all that, we have to use a full got entry for hidden symbols :-( 1795 if (GV->hasLocalLinkage()) 1796 return getAddrLocal(N, SDLoc(N), Ty, DAG, ABI.IsN32() || ABI.IsN64()); 1797 1798 if (LargeGOT) 1799 return getAddrGlobalLargeGOT( 1800 N, SDLoc(N), Ty, DAG, MipsII::MO_GOT_HI16, MipsII::MO_GOT_LO16, 1801 DAG.getEntryNode(), 1802 MachinePointerInfo::getGOT(DAG.getMachineFunction())); 1803 1804 return getAddrGlobal( 1805 N, SDLoc(N), Ty, DAG, 1806 (ABI.IsN32() || ABI.IsN64()) ? MipsII::MO_GOT_DISP : MipsII::MO_GOT, 1807 DAG.getEntryNode(), MachinePointerInfo::getGOT(DAG.getMachineFunction())); 1808 } 1809 1810 SDValue MipsTargetLowering::lowerBlockAddress(SDValue Op, 1811 SelectionDAG &DAG) const { 1812 BlockAddressSDNode *N = cast<BlockAddressSDNode>(Op); 1813 EVT Ty = Op.getValueType(); 1814 1815 if (!isPositionIndependent() && !ABI.IsN64()) 1816 return getAddrNonPIC(N, SDLoc(N), Ty, DAG); 1817 1818 return getAddrLocal(N, SDLoc(N), Ty, DAG, ABI.IsN32() || ABI.IsN64()); 1819 } 1820 1821 SDValue MipsTargetLowering:: 1822 lowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const 1823 { 1824 // If the relocation model is PIC, use the General Dynamic TLS Model or 1825 // Local Dynamic TLS model, otherwise use the Initial Exec or 1826 // Local Exec TLS Model. 1827 1828 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op); 1829 if (DAG.getTarget().Options.EmulatedTLS) 1830 return LowerToTLSEmulatedModel(GA, DAG); 1831 1832 SDLoc DL(GA); 1833 const GlobalValue *GV = GA->getGlobal(); 1834 EVT PtrVT = getPointerTy(DAG.getDataLayout()); 1835 1836 TLSModel::Model model = getTargetMachine().getTLSModel(GV); 1837 1838 if (model == TLSModel::GeneralDynamic || model == TLSModel::LocalDynamic) { 1839 // General Dynamic and Local Dynamic TLS Model. 1840 unsigned Flag = (model == TLSModel::LocalDynamic) ? MipsII::MO_TLSLDM 1841 : MipsII::MO_TLSGD; 1842 1843 SDValue TGA = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, Flag); 1844 SDValue Argument = DAG.getNode(MipsISD::Wrapper, DL, PtrVT, 1845 getGlobalReg(DAG, PtrVT), TGA); 1846 unsigned PtrSize = PtrVT.getSizeInBits(); 1847 IntegerType *PtrTy = Type::getIntNTy(*DAG.getContext(), PtrSize); 1848 1849 SDValue TlsGetAddr = DAG.getExternalSymbol("__tls_get_addr", PtrVT); 1850 1851 ArgListTy Args; 1852 ArgListEntry Entry; 1853 Entry.Node = Argument; 1854 Entry.Ty = PtrTy; 1855 Args.push_back(Entry); 1856 1857 TargetLowering::CallLoweringInfo CLI(DAG); 1858 CLI.setDebugLoc(DL).setChain(DAG.getEntryNode()) 1859 .setCallee(CallingConv::C, PtrTy, TlsGetAddr, std::move(Args)); 1860 std::pair<SDValue, SDValue> CallResult = LowerCallTo(CLI); 1861 1862 SDValue Ret = CallResult.first; 1863 1864 if (model != TLSModel::LocalDynamic) 1865 return Ret; 1866 1867 SDValue TGAHi = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, 1868 MipsII::MO_DTPREL_HI); 1869 SDValue Hi = DAG.getNode(MipsISD::Hi, DL, PtrVT, TGAHi); 1870 SDValue TGALo = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, 1871 MipsII::MO_DTPREL_LO); 1872 SDValue Lo = DAG.getNode(MipsISD::Lo, DL, PtrVT, TGALo); 1873 SDValue Add = DAG.getNode(ISD::ADD, DL, PtrVT, Hi, Ret); 1874 return DAG.getNode(ISD::ADD, DL, PtrVT, Add, Lo); 1875 } 1876 1877 SDValue Offset; 1878 if (model == TLSModel::InitialExec) { 1879 // Initial Exec TLS Model 1880 SDValue TGA = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, 1881 MipsII::MO_GOTTPREL); 1882 TGA = DAG.getNode(MipsISD::Wrapper, DL, PtrVT, getGlobalReg(DAG, PtrVT), 1883 TGA); 1884 Offset = 1885 DAG.getLoad(PtrVT, DL, DAG.getEntryNode(), TGA, MachinePointerInfo()); 1886 } else { 1887 // Local Exec TLS Model 1888 assert(model == TLSModel::LocalExec); 1889 SDValue TGAHi = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, 1890 MipsII::MO_TPREL_HI); 1891 SDValue TGALo = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, 1892 MipsII::MO_TPREL_LO); 1893 SDValue Hi = DAG.getNode(MipsISD::Hi, DL, PtrVT, TGAHi); 1894 SDValue Lo = DAG.getNode(MipsISD::Lo, DL, PtrVT, TGALo); 1895 Offset = DAG.getNode(ISD::ADD, DL, PtrVT, Hi, Lo); 1896 } 1897 1898 SDValue ThreadPointer = DAG.getNode(MipsISD::ThreadPointer, DL, PtrVT); 1899 return DAG.getNode(ISD::ADD, DL, PtrVT, ThreadPointer, Offset); 1900 } 1901 1902 SDValue MipsTargetLowering:: 1903 lowerJumpTable(SDValue Op, SelectionDAG &DAG) const 1904 { 1905 JumpTableSDNode *N = cast<JumpTableSDNode>(Op); 1906 EVT Ty = Op.getValueType(); 1907 1908 if (!isPositionIndependent() && !ABI.IsN64()) 1909 return getAddrNonPIC(N, SDLoc(N), Ty, DAG); 1910 1911 return getAddrLocal(N, SDLoc(N), Ty, DAG, ABI.IsN32() || ABI.IsN64()); 1912 } 1913 1914 SDValue MipsTargetLowering:: 1915 lowerConstantPool(SDValue Op, SelectionDAG &DAG) const 1916 { 1917 ConstantPoolSDNode *N = cast<ConstantPoolSDNode>(Op); 1918 EVT Ty = Op.getValueType(); 1919 1920 if (!isPositionIndependent() && !ABI.IsN64()) { 1921 const MipsTargetObjectFile *TLOF = 1922 static_cast<const MipsTargetObjectFile *>( 1923 getTargetMachine().getObjFileLowering()); 1924 1925 if (TLOF->IsConstantInSmallSection(DAG.getDataLayout(), N->getConstVal(), 1926 getTargetMachine())) 1927 // %gp_rel relocation 1928 return getAddrGPRel(N, SDLoc(N), Ty, DAG); 1929 1930 return getAddrNonPIC(N, SDLoc(N), Ty, DAG); 1931 } 1932 1933 return getAddrLocal(N, SDLoc(N), Ty, DAG, ABI.IsN32() || ABI.IsN64()); 1934 } 1935 1936 SDValue MipsTargetLowering::lowerVASTART(SDValue Op, SelectionDAG &DAG) const { 1937 MachineFunction &MF = DAG.getMachineFunction(); 1938 MipsFunctionInfo *FuncInfo = MF.getInfo<MipsFunctionInfo>(); 1939 1940 SDLoc DL(Op); 1941 SDValue FI = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), 1942 getPointerTy(MF.getDataLayout())); 1943 1944 // vastart just stores the address of the VarArgsFrameIndex slot into the 1945 // memory location argument. 1946 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue(); 1947 return DAG.getStore(Op.getOperand(0), DL, FI, Op.getOperand(1), 1948 MachinePointerInfo(SV)); 1949 } 1950 1951 SDValue MipsTargetLowering::lowerVAARG(SDValue Op, SelectionDAG &DAG) const { 1952 SDNode *Node = Op.getNode(); 1953 EVT VT = Node->getValueType(0); 1954 SDValue Chain = Node->getOperand(0); 1955 SDValue VAListPtr = Node->getOperand(1); 1956 unsigned Align = Node->getConstantOperandVal(3); 1957 const Value *SV = cast<SrcValueSDNode>(Node->getOperand(2))->getValue(); 1958 SDLoc DL(Node); 1959 unsigned ArgSlotSizeInBytes = (ABI.IsN32() || ABI.IsN64()) ? 8 : 4; 1960 1961 SDValue VAListLoad = DAG.getLoad(getPointerTy(DAG.getDataLayout()), DL, Chain, 1962 VAListPtr, MachinePointerInfo(SV)); 1963 SDValue VAList = VAListLoad; 1964 1965 // Re-align the pointer if necessary. 1966 // It should only ever be necessary for 64-bit types on O32 since the minimum 1967 // argument alignment is the same as the maximum type alignment for N32/N64. 1968 // 1969 // FIXME: We currently align too often. The code generator doesn't notice 1970 // when the pointer is still aligned from the last va_arg (or pair of 1971 // va_args for the i64 on O32 case). 1972 if (Align > getMinStackArgumentAlignment()) { 1973 assert(((Align & (Align-1)) == 0) && "Expected Align to be a power of 2"); 1974 1975 VAList = DAG.getNode(ISD::ADD, DL, VAList.getValueType(), VAList, 1976 DAG.getConstant(Align - 1, DL, VAList.getValueType())); 1977 1978 VAList = DAG.getNode(ISD::AND, DL, VAList.getValueType(), VAList, 1979 DAG.getConstant(-(int64_t)Align, DL, 1980 VAList.getValueType())); 1981 } 1982 1983 // Increment the pointer, VAList, to the next vaarg. 1984 auto &TD = DAG.getDataLayout(); 1985 unsigned ArgSizeInBytes = 1986 TD.getTypeAllocSize(VT.getTypeForEVT(*DAG.getContext())); 1987 SDValue Tmp3 = 1988 DAG.getNode(ISD::ADD, DL, VAList.getValueType(), VAList, 1989 DAG.getConstant(alignTo(ArgSizeInBytes, ArgSlotSizeInBytes), 1990 DL, VAList.getValueType())); 1991 // Store the incremented VAList to the legalized pointer 1992 Chain = DAG.getStore(VAListLoad.getValue(1), DL, Tmp3, VAListPtr, 1993 MachinePointerInfo(SV)); 1994 1995 // In big-endian mode we must adjust the pointer when the load size is smaller 1996 // than the argument slot size. We must also reduce the known alignment to 1997 // match. For example in the N64 ABI, we must add 4 bytes to the offset to get 1998 // the correct half of the slot, and reduce the alignment from 8 (slot 1999 // alignment) down to 4 (type alignment). 2000 if (!Subtarget.isLittle() && ArgSizeInBytes < ArgSlotSizeInBytes) { 2001 unsigned Adjustment = ArgSlotSizeInBytes - ArgSizeInBytes; 2002 VAList = DAG.getNode(ISD::ADD, DL, VAListPtr.getValueType(), VAList, 2003 DAG.getIntPtrConstant(Adjustment, DL)); 2004 } 2005 // Load the actual argument out of the pointer VAList 2006 return DAG.getLoad(VT, DL, Chain, VAList, MachinePointerInfo()); 2007 } 2008 2009 static SDValue lowerFCOPYSIGN32(SDValue Op, SelectionDAG &DAG, 2010 bool HasExtractInsert) { 2011 EVT TyX = Op.getOperand(0).getValueType(); 2012 EVT TyY = Op.getOperand(1).getValueType(); 2013 SDLoc DL(Op); 2014 SDValue Const1 = DAG.getConstant(1, DL, MVT::i32); 2015 SDValue Const31 = DAG.getConstant(31, DL, MVT::i32); 2016 SDValue Res; 2017 2018 // If operand is of type f64, extract the upper 32-bit. Otherwise, bitcast it 2019 // to i32. 2020 SDValue X = (TyX == MVT::f32) ? 2021 DAG.getNode(ISD::BITCAST, DL, MVT::i32, Op.getOperand(0)) : 2022 DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32, Op.getOperand(0), 2023 Const1); 2024 SDValue Y = (TyY == MVT::f32) ? 2025 DAG.getNode(ISD::BITCAST, DL, MVT::i32, Op.getOperand(1)) : 2026 DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32, Op.getOperand(1), 2027 Const1); 2028 2029 if (HasExtractInsert) { 2030 // ext E, Y, 31, 1 ; extract bit31 of Y 2031 // ins X, E, 31, 1 ; insert extracted bit at bit31 of X 2032 SDValue E = DAG.getNode(MipsISD::Ext, DL, MVT::i32, Y, Const31, Const1); 2033 Res = DAG.getNode(MipsISD::Ins, DL, MVT::i32, E, Const31, Const1, X); 2034 } else { 2035 // sll SllX, X, 1 2036 // srl SrlX, SllX, 1 2037 // srl SrlY, Y, 31 2038 // sll SllY, SrlX, 31 2039 // or Or, SrlX, SllY 2040 SDValue SllX = DAG.getNode(ISD::SHL, DL, MVT::i32, X, Const1); 2041 SDValue SrlX = DAG.getNode(ISD::SRL, DL, MVT::i32, SllX, Const1); 2042 SDValue SrlY = DAG.getNode(ISD::SRL, DL, MVT::i32, Y, Const31); 2043 SDValue SllY = DAG.getNode(ISD::SHL, DL, MVT::i32, SrlY, Const31); 2044 Res = DAG.getNode(ISD::OR, DL, MVT::i32, SrlX, SllY); 2045 } 2046 2047 if (TyX == MVT::f32) 2048 return DAG.getNode(ISD::BITCAST, DL, Op.getOperand(0).getValueType(), Res); 2049 2050 SDValue LowX = DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32, 2051 Op.getOperand(0), 2052 DAG.getConstant(0, DL, MVT::i32)); 2053 return DAG.getNode(MipsISD::BuildPairF64, DL, MVT::f64, LowX, Res); 2054 } 2055 2056 static SDValue lowerFCOPYSIGN64(SDValue Op, SelectionDAG &DAG, 2057 bool HasExtractInsert) { 2058 unsigned WidthX = Op.getOperand(0).getValueSizeInBits(); 2059 unsigned WidthY = Op.getOperand(1).getValueSizeInBits(); 2060 EVT TyX = MVT::getIntegerVT(WidthX), TyY = MVT::getIntegerVT(WidthY); 2061 SDLoc DL(Op); 2062 SDValue Const1 = DAG.getConstant(1, DL, MVT::i32); 2063 2064 // Bitcast to integer nodes. 2065 SDValue X = DAG.getNode(ISD::BITCAST, DL, TyX, Op.getOperand(0)); 2066 SDValue Y = DAG.getNode(ISD::BITCAST, DL, TyY, Op.getOperand(1)); 2067 2068 if (HasExtractInsert) { 2069 // ext E, Y, width(Y) - 1, 1 ; extract bit width(Y)-1 of Y 2070 // ins X, E, width(X) - 1, 1 ; insert extracted bit at bit width(X)-1 of X 2071 SDValue E = DAG.getNode(MipsISD::Ext, DL, TyY, Y, 2072 DAG.getConstant(WidthY - 1, DL, MVT::i32), Const1); 2073 2074 if (WidthX > WidthY) 2075 E = DAG.getNode(ISD::ZERO_EXTEND, DL, TyX, E); 2076 else if (WidthY > WidthX) 2077 E = DAG.getNode(ISD::TRUNCATE, DL, TyX, E); 2078 2079 SDValue I = DAG.getNode(MipsISD::Ins, DL, TyX, E, 2080 DAG.getConstant(WidthX - 1, DL, MVT::i32), Const1, 2081 X); 2082 return DAG.getNode(ISD::BITCAST, DL, Op.getOperand(0).getValueType(), I); 2083 } 2084 2085 // (d)sll SllX, X, 1 2086 // (d)srl SrlX, SllX, 1 2087 // (d)srl SrlY, Y, width(Y)-1 2088 // (d)sll SllY, SrlX, width(Y)-1 2089 // or Or, SrlX, SllY 2090 SDValue SllX = DAG.getNode(ISD::SHL, DL, TyX, X, Const1); 2091 SDValue SrlX = DAG.getNode(ISD::SRL, DL, TyX, SllX, Const1); 2092 SDValue SrlY = DAG.getNode(ISD::SRL, DL, TyY, Y, 2093 DAG.getConstant(WidthY - 1, DL, MVT::i32)); 2094 2095 if (WidthX > WidthY) 2096 SrlY = DAG.getNode(ISD::ZERO_EXTEND, DL, TyX, SrlY); 2097 else if (WidthY > WidthX) 2098 SrlY = DAG.getNode(ISD::TRUNCATE, DL, TyX, SrlY); 2099 2100 SDValue SllY = DAG.getNode(ISD::SHL, DL, TyX, SrlY, 2101 DAG.getConstant(WidthX - 1, DL, MVT::i32)); 2102 SDValue Or = DAG.getNode(ISD::OR, DL, TyX, SrlX, SllY); 2103 return DAG.getNode(ISD::BITCAST, DL, Op.getOperand(0).getValueType(), Or); 2104 } 2105 2106 SDValue 2107 MipsTargetLowering::lowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const { 2108 if (Subtarget.isGP64bit()) 2109 return lowerFCOPYSIGN64(Op, DAG, Subtarget.hasExtractInsert()); 2110 2111 return lowerFCOPYSIGN32(Op, DAG, Subtarget.hasExtractInsert()); 2112 } 2113 2114 SDValue MipsTargetLowering:: 2115 lowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const { 2116 // check the depth 2117 assert((cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue() == 0) && 2118 "Frame address can only be determined for current frame."); 2119 2120 MachineFrameInfo &MFI = DAG.getMachineFunction().getFrameInfo(); 2121 MFI.setFrameAddressIsTaken(true); 2122 EVT VT = Op.getValueType(); 2123 SDLoc DL(Op); 2124 SDValue FrameAddr = DAG.getCopyFromReg( 2125 DAG.getEntryNode(), DL, ABI.IsN64() ? Mips::FP_64 : Mips::FP, VT); 2126 return FrameAddr; 2127 } 2128 2129 SDValue MipsTargetLowering::lowerRETURNADDR(SDValue Op, 2130 SelectionDAG &DAG) const { 2131 if (verifyReturnAddressArgumentIsConstant(Op, DAG)) 2132 return SDValue(); 2133 2134 // check the depth 2135 assert((cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue() == 0) && 2136 "Return address can be determined only for current frame."); 2137 2138 MachineFunction &MF = DAG.getMachineFunction(); 2139 MachineFrameInfo &MFI = MF.getFrameInfo(); 2140 MVT VT = Op.getSimpleValueType(); 2141 unsigned RA = ABI.IsN64() ? Mips::RA_64 : Mips::RA; 2142 MFI.setReturnAddressIsTaken(true); 2143 2144 // Return RA, which contains the return address. Mark it an implicit live-in. 2145 unsigned Reg = MF.addLiveIn(RA, getRegClassFor(VT)); 2146 return DAG.getCopyFromReg(DAG.getEntryNode(), SDLoc(Op), Reg, VT); 2147 } 2148 2149 // An EH_RETURN is the result of lowering llvm.eh.return which in turn is 2150 // generated from __builtin_eh_return (offset, handler) 2151 // The effect of this is to adjust the stack pointer by "offset" 2152 // and then branch to "handler". 2153 SDValue MipsTargetLowering::lowerEH_RETURN(SDValue Op, SelectionDAG &DAG) 2154 const { 2155 MachineFunction &MF = DAG.getMachineFunction(); 2156 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>(); 2157 2158 MipsFI->setCallsEhReturn(); 2159 SDValue Chain = Op.getOperand(0); 2160 SDValue Offset = Op.getOperand(1); 2161 SDValue Handler = Op.getOperand(2); 2162 SDLoc DL(Op); 2163 EVT Ty = ABI.IsN64() ? MVT::i64 : MVT::i32; 2164 2165 // Store stack offset in V1, store jump target in V0. Glue CopyToReg and 2166 // EH_RETURN nodes, so that instructions are emitted back-to-back. 2167 unsigned OffsetReg = ABI.IsN64() ? Mips::V1_64 : Mips::V1; 2168 unsigned AddrReg = ABI.IsN64() ? Mips::V0_64 : Mips::V0; 2169 Chain = DAG.getCopyToReg(Chain, DL, OffsetReg, Offset, SDValue()); 2170 Chain = DAG.getCopyToReg(Chain, DL, AddrReg, Handler, Chain.getValue(1)); 2171 return DAG.getNode(MipsISD::EH_RETURN, DL, MVT::Other, Chain, 2172 DAG.getRegister(OffsetReg, Ty), 2173 DAG.getRegister(AddrReg, getPointerTy(MF.getDataLayout())), 2174 Chain.getValue(1)); 2175 } 2176 2177 SDValue MipsTargetLowering::lowerATOMIC_FENCE(SDValue Op, 2178 SelectionDAG &DAG) const { 2179 // FIXME: Need pseudo-fence for 'singlethread' fences 2180 // FIXME: Set SType for weaker fences where supported/appropriate. 2181 unsigned SType = 0; 2182 SDLoc DL(Op); 2183 return DAG.getNode(MipsISD::Sync, DL, MVT::Other, Op.getOperand(0), 2184 DAG.getConstant(SType, DL, MVT::i32)); 2185 } 2186 2187 SDValue MipsTargetLowering::lowerShiftLeftParts(SDValue Op, 2188 SelectionDAG &DAG) const { 2189 SDLoc DL(Op); 2190 MVT VT = Subtarget.isGP64bit() ? MVT::i64 : MVT::i32; 2191 2192 SDValue Lo = Op.getOperand(0), Hi = Op.getOperand(1); 2193 SDValue Shamt = Op.getOperand(2); 2194 // if shamt < (VT.bits): 2195 // lo = (shl lo, shamt) 2196 // hi = (or (shl hi, shamt) (srl (srl lo, 1), ~shamt)) 2197 // else: 2198 // lo = 0 2199 // hi = (shl lo, shamt[4:0]) 2200 SDValue Not = DAG.getNode(ISD::XOR, DL, MVT::i32, Shamt, 2201 DAG.getConstant(-1, DL, MVT::i32)); 2202 SDValue ShiftRight1Lo = DAG.getNode(ISD::SRL, DL, VT, Lo, 2203 DAG.getConstant(1, DL, VT)); 2204 SDValue ShiftRightLo = DAG.getNode(ISD::SRL, DL, VT, ShiftRight1Lo, Not); 2205 SDValue ShiftLeftHi = DAG.getNode(ISD::SHL, DL, VT, Hi, Shamt); 2206 SDValue Or = DAG.getNode(ISD::OR, DL, VT, ShiftLeftHi, ShiftRightLo); 2207 SDValue ShiftLeftLo = DAG.getNode(ISD::SHL, DL, VT, Lo, Shamt); 2208 SDValue Cond = DAG.getNode(ISD::AND, DL, MVT::i32, Shamt, 2209 DAG.getConstant(VT.getSizeInBits(), DL, MVT::i32)); 2210 Lo = DAG.getNode(ISD::SELECT, DL, VT, Cond, 2211 DAG.getConstant(0, DL, VT), ShiftLeftLo); 2212 Hi = DAG.getNode(ISD::SELECT, DL, VT, Cond, ShiftLeftLo, Or); 2213 2214 SDValue Ops[2] = {Lo, Hi}; 2215 return DAG.getMergeValues(Ops, DL); 2216 } 2217 2218 SDValue MipsTargetLowering::lowerShiftRightParts(SDValue Op, SelectionDAG &DAG, 2219 bool IsSRA) const { 2220 SDLoc DL(Op); 2221 SDValue Lo = Op.getOperand(0), Hi = Op.getOperand(1); 2222 SDValue Shamt = Op.getOperand(2); 2223 MVT VT = Subtarget.isGP64bit() ? MVT::i64 : MVT::i32; 2224 2225 // if shamt < (VT.bits): 2226 // lo = (or (shl (shl hi, 1), ~shamt) (srl lo, shamt)) 2227 // if isSRA: 2228 // hi = (sra hi, shamt) 2229 // else: 2230 // hi = (srl hi, shamt) 2231 // else: 2232 // if isSRA: 2233 // lo = (sra hi, shamt[4:0]) 2234 // hi = (sra hi, 31) 2235 // else: 2236 // lo = (srl hi, shamt[4:0]) 2237 // hi = 0 2238 SDValue Not = DAG.getNode(ISD::XOR, DL, MVT::i32, Shamt, 2239 DAG.getConstant(-1, DL, MVT::i32)); 2240 SDValue ShiftLeft1Hi = DAG.getNode(ISD::SHL, DL, VT, Hi, 2241 DAG.getConstant(1, DL, VT)); 2242 SDValue ShiftLeftHi = DAG.getNode(ISD::SHL, DL, VT, ShiftLeft1Hi, Not); 2243 SDValue ShiftRightLo = DAG.getNode(ISD::SRL, DL, VT, Lo, Shamt); 2244 SDValue Or = DAG.getNode(ISD::OR, DL, VT, ShiftLeftHi, ShiftRightLo); 2245 SDValue ShiftRightHi = DAG.getNode(IsSRA ? ISD::SRA : ISD::SRL, 2246 DL, VT, Hi, Shamt); 2247 SDValue Cond = DAG.getNode(ISD::AND, DL, MVT::i32, Shamt, 2248 DAG.getConstant(VT.getSizeInBits(), DL, MVT::i32)); 2249 SDValue Ext = DAG.getNode(ISD::SRA, DL, VT, Hi, 2250 DAG.getConstant(VT.getSizeInBits() - 1, DL, VT)); 2251 Lo = DAG.getNode(ISD::SELECT, DL, VT, Cond, ShiftRightHi, Or); 2252 Hi = DAG.getNode(ISD::SELECT, DL, VT, Cond, 2253 IsSRA ? Ext : DAG.getConstant(0, DL, VT), ShiftRightHi); 2254 2255 SDValue Ops[2] = {Lo, Hi}; 2256 return DAG.getMergeValues(Ops, DL); 2257 } 2258 2259 static SDValue createLoadLR(unsigned Opc, SelectionDAG &DAG, LoadSDNode *LD, 2260 SDValue Chain, SDValue Src, unsigned Offset) { 2261 SDValue Ptr = LD->getBasePtr(); 2262 EVT VT = LD->getValueType(0), MemVT = LD->getMemoryVT(); 2263 EVT BasePtrVT = Ptr.getValueType(); 2264 SDLoc DL(LD); 2265 SDVTList VTList = DAG.getVTList(VT, MVT::Other); 2266 2267 if (Offset) 2268 Ptr = DAG.getNode(ISD::ADD, DL, BasePtrVT, Ptr, 2269 DAG.getConstant(Offset, DL, BasePtrVT)); 2270 2271 SDValue Ops[] = { Chain, Ptr, Src }; 2272 return DAG.getMemIntrinsicNode(Opc, DL, VTList, Ops, MemVT, 2273 LD->getMemOperand()); 2274 } 2275 2276 // Expand an unaligned 32 or 64-bit integer load node. 2277 SDValue MipsTargetLowering::lowerLOAD(SDValue Op, SelectionDAG &DAG) const { 2278 LoadSDNode *LD = cast<LoadSDNode>(Op); 2279 EVT MemVT = LD->getMemoryVT(); 2280 2281 if (Subtarget.systemSupportsUnalignedAccess()) 2282 return Op; 2283 2284 // Return if load is aligned or if MemVT is neither i32 nor i64. 2285 if ((LD->getAlignment() >= MemVT.getSizeInBits() / 8) || 2286 ((MemVT != MVT::i32) && (MemVT != MVT::i64))) 2287 return SDValue(); 2288 2289 bool IsLittle = Subtarget.isLittle(); 2290 EVT VT = Op.getValueType(); 2291 ISD::LoadExtType ExtType = LD->getExtensionType(); 2292 SDValue Chain = LD->getChain(), Undef = DAG.getUNDEF(VT); 2293 2294 assert((VT == MVT::i32) || (VT == MVT::i64)); 2295 2296 // Expand 2297 // (set dst, (i64 (load baseptr))) 2298 // to 2299 // (set tmp, (ldl (add baseptr, 7), undef)) 2300 // (set dst, (ldr baseptr, tmp)) 2301 if ((VT == MVT::i64) && (ExtType == ISD::NON_EXTLOAD)) { 2302 SDValue LDL = createLoadLR(MipsISD::LDL, DAG, LD, Chain, Undef, 2303 IsLittle ? 7 : 0); 2304 return createLoadLR(MipsISD::LDR, DAG, LD, LDL.getValue(1), LDL, 2305 IsLittle ? 0 : 7); 2306 } 2307 2308 SDValue LWL = createLoadLR(MipsISD::LWL, DAG, LD, Chain, Undef, 2309 IsLittle ? 3 : 0); 2310 SDValue LWR = createLoadLR(MipsISD::LWR, DAG, LD, LWL.getValue(1), LWL, 2311 IsLittle ? 0 : 3); 2312 2313 // Expand 2314 // (set dst, (i32 (load baseptr))) or 2315 // (set dst, (i64 (sextload baseptr))) or 2316 // (set dst, (i64 (extload baseptr))) 2317 // to 2318 // (set tmp, (lwl (add baseptr, 3), undef)) 2319 // (set dst, (lwr baseptr, tmp)) 2320 if ((VT == MVT::i32) || (ExtType == ISD::SEXTLOAD) || 2321 (ExtType == ISD::EXTLOAD)) 2322 return LWR; 2323 2324 assert((VT == MVT::i64) && (ExtType == ISD::ZEXTLOAD)); 2325 2326 // Expand 2327 // (set dst, (i64 (zextload baseptr))) 2328 // to 2329 // (set tmp0, (lwl (add baseptr, 3), undef)) 2330 // (set tmp1, (lwr baseptr, tmp0)) 2331 // (set tmp2, (shl tmp1, 32)) 2332 // (set dst, (srl tmp2, 32)) 2333 SDLoc DL(LD); 2334 SDValue Const32 = DAG.getConstant(32, DL, MVT::i32); 2335 SDValue SLL = DAG.getNode(ISD::SHL, DL, MVT::i64, LWR, Const32); 2336 SDValue SRL = DAG.getNode(ISD::SRL, DL, MVT::i64, SLL, Const32); 2337 SDValue Ops[] = { SRL, LWR.getValue(1) }; 2338 return DAG.getMergeValues(Ops, DL); 2339 } 2340 2341 static SDValue createStoreLR(unsigned Opc, SelectionDAG &DAG, StoreSDNode *SD, 2342 SDValue Chain, unsigned Offset) { 2343 SDValue Ptr = SD->getBasePtr(), Value = SD->getValue(); 2344 EVT MemVT = SD->getMemoryVT(), BasePtrVT = Ptr.getValueType(); 2345 SDLoc DL(SD); 2346 SDVTList VTList = DAG.getVTList(MVT::Other); 2347 2348 if (Offset) 2349 Ptr = DAG.getNode(ISD::ADD, DL, BasePtrVT, Ptr, 2350 DAG.getConstant(Offset, DL, BasePtrVT)); 2351 2352 SDValue Ops[] = { Chain, Value, Ptr }; 2353 return DAG.getMemIntrinsicNode(Opc, DL, VTList, Ops, MemVT, 2354 SD->getMemOperand()); 2355 } 2356 2357 // Expand an unaligned 32 or 64-bit integer store node. 2358 static SDValue lowerUnalignedIntStore(StoreSDNode *SD, SelectionDAG &DAG, 2359 bool IsLittle) { 2360 SDValue Value = SD->getValue(), Chain = SD->getChain(); 2361 EVT VT = Value.getValueType(); 2362 2363 // Expand 2364 // (store val, baseptr) or 2365 // (truncstore val, baseptr) 2366 // to 2367 // (swl val, (add baseptr, 3)) 2368 // (swr val, baseptr) 2369 if ((VT == MVT::i32) || SD->isTruncatingStore()) { 2370 SDValue SWL = createStoreLR(MipsISD::SWL, DAG, SD, Chain, 2371 IsLittle ? 3 : 0); 2372 return createStoreLR(MipsISD::SWR, DAG, SD, SWL, IsLittle ? 0 : 3); 2373 } 2374 2375 assert(VT == MVT::i64); 2376 2377 // Expand 2378 // (store val, baseptr) 2379 // to 2380 // (sdl val, (add baseptr, 7)) 2381 // (sdr val, baseptr) 2382 SDValue SDL = createStoreLR(MipsISD::SDL, DAG, SD, Chain, IsLittle ? 7 : 0); 2383 return createStoreLR(MipsISD::SDR, DAG, SD, SDL, IsLittle ? 0 : 7); 2384 } 2385 2386 // Lower (store (fp_to_sint $fp) $ptr) to (store (TruncIntFP $fp), $ptr). 2387 static SDValue lowerFP_TO_SINT_STORE(StoreSDNode *SD, SelectionDAG &DAG) { 2388 SDValue Val = SD->getValue(); 2389 2390 if (Val.getOpcode() != ISD::FP_TO_SINT) 2391 return SDValue(); 2392 2393 EVT FPTy = EVT::getFloatingPointVT(Val.getValueSizeInBits()); 2394 SDValue Tr = DAG.getNode(MipsISD::TruncIntFP, SDLoc(Val), FPTy, 2395 Val.getOperand(0)); 2396 return DAG.getStore(SD->getChain(), SDLoc(SD), Tr, SD->getBasePtr(), 2397 SD->getPointerInfo(), SD->getAlignment(), 2398 SD->getMemOperand()->getFlags()); 2399 } 2400 2401 SDValue MipsTargetLowering::lowerSTORE(SDValue Op, SelectionDAG &DAG) const { 2402 StoreSDNode *SD = cast<StoreSDNode>(Op); 2403 EVT MemVT = SD->getMemoryVT(); 2404 2405 // Lower unaligned integer stores. 2406 if (!Subtarget.systemSupportsUnalignedAccess() && 2407 (SD->getAlignment() < MemVT.getSizeInBits() / 8) && 2408 ((MemVT == MVT::i32) || (MemVT == MVT::i64))) 2409 return lowerUnalignedIntStore(SD, DAG, Subtarget.isLittle()); 2410 2411 return lowerFP_TO_SINT_STORE(SD, DAG); 2412 } 2413 2414 SDValue MipsTargetLowering::lowerEH_DWARF_CFA(SDValue Op, 2415 SelectionDAG &DAG) const { 2416 2417 // Return a fixed StackObject with offset 0 which points to the old stack 2418 // pointer. 2419 MachineFrameInfo &MFI = DAG.getMachineFunction().getFrameInfo(); 2420 EVT ValTy = Op->getValueType(0); 2421 int FI = MFI.CreateFixedObject(Op.getValueSizeInBits() / 8, 0, false); 2422 return DAG.getFrameIndex(FI, ValTy); 2423 } 2424 2425 SDValue MipsTargetLowering::lowerFP_TO_SINT(SDValue Op, 2426 SelectionDAG &DAG) const { 2427 EVT FPTy = EVT::getFloatingPointVT(Op.getValueSizeInBits()); 2428 SDValue Trunc = DAG.getNode(MipsISD::TruncIntFP, SDLoc(Op), FPTy, 2429 Op.getOperand(0)); 2430 return DAG.getNode(ISD::BITCAST, SDLoc(Op), Op.getValueType(), Trunc); 2431 } 2432 2433 //===----------------------------------------------------------------------===// 2434 // Calling Convention Implementation 2435 //===----------------------------------------------------------------------===// 2436 2437 //===----------------------------------------------------------------------===// 2438 // TODO: Implement a generic logic using tblgen that can support this. 2439 // Mips O32 ABI rules: 2440 // --- 2441 // i32 - Passed in A0, A1, A2, A3 and stack 2442 // f32 - Only passed in f32 registers if no int reg has been used yet to hold 2443 // an argument. Otherwise, passed in A1, A2, A3 and stack. 2444 // f64 - Only passed in two aliased f32 registers if no int reg has been used 2445 // yet to hold an argument. Otherwise, use A2, A3 and stack. If A1 is 2446 // not used, it must be shadowed. If only A3 is available, shadow it and 2447 // go to stack. 2448 // 2449 // For vararg functions, all arguments are passed in A0, A1, A2, A3 and stack. 2450 //===----------------------------------------------------------------------===// 2451 2452 static bool CC_MipsO32(unsigned ValNo, MVT ValVT, MVT LocVT, 2453 CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, 2454 CCState &State, ArrayRef<MCPhysReg> F64Regs) { 2455 const MipsSubtarget &Subtarget = static_cast<const MipsSubtarget &>( 2456 State.getMachineFunction().getSubtarget()); 2457 2458 static const MCPhysReg IntRegs[] = { Mips::A0, Mips::A1, Mips::A2, Mips::A3 }; 2459 static const MCPhysReg F32Regs[] = { Mips::F12, Mips::F14 }; 2460 2461 // Do not process byval args here. 2462 if (ArgFlags.isByVal()) 2463 return true; 2464 2465 // Promote i8 and i16 2466 if (ArgFlags.isInReg() && !Subtarget.isLittle()) { 2467 if (LocVT == MVT::i8 || LocVT == MVT::i16 || LocVT == MVT::i32) { 2468 LocVT = MVT::i32; 2469 if (ArgFlags.isSExt()) 2470 LocInfo = CCValAssign::SExtUpper; 2471 else if (ArgFlags.isZExt()) 2472 LocInfo = CCValAssign::ZExtUpper; 2473 else 2474 LocInfo = CCValAssign::AExtUpper; 2475 } 2476 } 2477 2478 // Promote i8 and i16 2479 if (LocVT == MVT::i8 || LocVT == MVT::i16) { 2480 LocVT = MVT::i32; 2481 if (ArgFlags.isSExt()) 2482 LocInfo = CCValAssign::SExt; 2483 else if (ArgFlags.isZExt()) 2484 LocInfo = CCValAssign::ZExt; 2485 else 2486 LocInfo = CCValAssign::AExt; 2487 } 2488 2489 unsigned Reg; 2490 2491 // f32 and f64 are allocated in A0, A1, A2, A3 when either of the following 2492 // is true: function is vararg, argument is 3rd or higher, there is previous 2493 // argument which is not f32 or f64. 2494 bool AllocateFloatsInIntReg = State.isVarArg() || ValNo > 1 || 2495 State.getFirstUnallocated(F32Regs) != ValNo; 2496 unsigned OrigAlign = ArgFlags.getOrigAlign(); 2497 bool isI64 = (ValVT == MVT::i32 && OrigAlign == 8); 2498 2499 if (ValVT == MVT::i32 || (ValVT == MVT::f32 && AllocateFloatsInIntReg)) { 2500 Reg = State.AllocateReg(IntRegs); 2501 // If this is the first part of an i64 arg, 2502 // the allocated register must be either A0 or A2. 2503 if (isI64 && (Reg == Mips::A1 || Reg == Mips::A3)) 2504 Reg = State.AllocateReg(IntRegs); 2505 LocVT = MVT::i32; 2506 } else if (ValVT == MVT::f64 && AllocateFloatsInIntReg) { 2507 // Allocate int register and shadow next int register. If first 2508 // available register is Mips::A1 or Mips::A3, shadow it too. 2509 Reg = State.AllocateReg(IntRegs); 2510 if (Reg == Mips::A1 || Reg == Mips::A3) 2511 Reg = State.AllocateReg(IntRegs); 2512 State.AllocateReg(IntRegs); 2513 LocVT = MVT::i32; 2514 } else if (ValVT.isFloatingPoint() && !AllocateFloatsInIntReg) { 2515 // we are guaranteed to find an available float register 2516 if (ValVT == MVT::f32) { 2517 Reg = State.AllocateReg(F32Regs); 2518 // Shadow int register 2519 State.AllocateReg(IntRegs); 2520 } else { 2521 Reg = State.AllocateReg(F64Regs); 2522 // Shadow int registers 2523 unsigned Reg2 = State.AllocateReg(IntRegs); 2524 if (Reg2 == Mips::A1 || Reg2 == Mips::A3) 2525 State.AllocateReg(IntRegs); 2526 State.AllocateReg(IntRegs); 2527 } 2528 } else 2529 llvm_unreachable("Cannot handle this ValVT."); 2530 2531 if (!Reg) { 2532 unsigned Offset = State.AllocateStack(ValVT.getSizeInBits() >> 3, 2533 OrigAlign); 2534 State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo)); 2535 } else 2536 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); 2537 2538 return false; 2539 } 2540 2541 static bool CC_MipsO32_FP32(unsigned ValNo, MVT ValVT, 2542 MVT LocVT, CCValAssign::LocInfo LocInfo, 2543 ISD::ArgFlagsTy ArgFlags, CCState &State) { 2544 static const MCPhysReg F64Regs[] = { Mips::D6, Mips::D7 }; 2545 2546 return CC_MipsO32(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State, F64Regs); 2547 } 2548 2549 static bool CC_MipsO32_FP64(unsigned ValNo, MVT ValVT, 2550 MVT LocVT, CCValAssign::LocInfo LocInfo, 2551 ISD::ArgFlagsTy ArgFlags, CCState &State) { 2552 static const MCPhysReg F64Regs[] = { Mips::D12_64, Mips::D14_64 }; 2553 2554 return CC_MipsO32(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State, F64Regs); 2555 } 2556 2557 static bool CC_MipsO32(unsigned ValNo, MVT ValVT, MVT LocVT, 2558 CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, 2559 CCState &State) LLVM_ATTRIBUTE_UNUSED; 2560 2561 #include "MipsGenCallingConv.inc" 2562 2563 //===----------------------------------------------------------------------===// 2564 // Call Calling Convention Implementation 2565 //===----------------------------------------------------------------------===// 2566 2567 // Return next O32 integer argument register. 2568 static unsigned getNextIntArgReg(unsigned Reg) { 2569 assert((Reg == Mips::A0) || (Reg == Mips::A2)); 2570 return (Reg == Mips::A0) ? Mips::A1 : Mips::A3; 2571 } 2572 2573 SDValue MipsTargetLowering::passArgOnStack(SDValue StackPtr, unsigned Offset, 2574 SDValue Chain, SDValue Arg, 2575 const SDLoc &DL, bool IsTailCall, 2576 SelectionDAG &DAG) const { 2577 if (!IsTailCall) { 2578 SDValue PtrOff = 2579 DAG.getNode(ISD::ADD, DL, getPointerTy(DAG.getDataLayout()), StackPtr, 2580 DAG.getIntPtrConstant(Offset, DL)); 2581 return DAG.getStore(Chain, DL, Arg, PtrOff, MachinePointerInfo()); 2582 } 2583 2584 MachineFrameInfo &MFI = DAG.getMachineFunction().getFrameInfo(); 2585 int FI = MFI.CreateFixedObject(Arg.getValueSizeInBits() / 8, Offset, false); 2586 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy(DAG.getDataLayout())); 2587 return DAG.getStore(Chain, DL, Arg, FIN, MachinePointerInfo(), 2588 /* Alignment = */ 0, MachineMemOperand::MOVolatile); 2589 } 2590 2591 void MipsTargetLowering:: 2592 getOpndList(SmallVectorImpl<SDValue> &Ops, 2593 std::deque< std::pair<unsigned, SDValue> > &RegsToPass, 2594 bool IsPICCall, bool GlobalOrExternal, bool InternalLinkage, 2595 bool IsCallReloc, CallLoweringInfo &CLI, SDValue Callee, 2596 SDValue Chain) const { 2597 // Insert node "GP copy globalreg" before call to function. 2598 // 2599 // R_MIPS_CALL* operators (emitted when non-internal functions are called 2600 // in PIC mode) allow symbols to be resolved via lazy binding. 2601 // The lazy binding stub requires GP to point to the GOT. 2602 // Note that we don't need GP to point to the GOT for indirect calls 2603 // (when R_MIPS_CALL* is not used for the call) because Mips linker generates 2604 // lazy binding stub for a function only when R_MIPS_CALL* are the only relocs 2605 // used for the function (that is, Mips linker doesn't generate lazy binding 2606 // stub for a function whose address is taken in the program). 2607 if (IsPICCall && !InternalLinkage && IsCallReloc) { 2608 unsigned GPReg = ABI.IsN64() ? Mips::GP_64 : Mips::GP; 2609 EVT Ty = ABI.IsN64() ? MVT::i64 : MVT::i32; 2610 RegsToPass.push_back(std::make_pair(GPReg, getGlobalReg(CLI.DAG, Ty))); 2611 } 2612 2613 // Build a sequence of copy-to-reg nodes chained together with token 2614 // chain and flag operands which copy the outgoing args into registers. 2615 // The InFlag in necessary since all emitted instructions must be 2616 // stuck together. 2617 SDValue InFlag; 2618 2619 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) { 2620 Chain = CLI.DAG.getCopyToReg(Chain, CLI.DL, RegsToPass[i].first, 2621 RegsToPass[i].second, InFlag); 2622 InFlag = Chain.getValue(1); 2623 } 2624 2625 // Add argument registers to the end of the list so that they are 2626 // known live into the call. 2627 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) 2628 Ops.push_back(CLI.DAG.getRegister(RegsToPass[i].first, 2629 RegsToPass[i].second.getValueType())); 2630 2631 // Add a register mask operand representing the call-preserved registers. 2632 const TargetRegisterInfo *TRI = Subtarget.getRegisterInfo(); 2633 const uint32_t *Mask = 2634 TRI->getCallPreservedMask(CLI.DAG.getMachineFunction(), CLI.CallConv); 2635 assert(Mask && "Missing call preserved mask for calling convention"); 2636 if (Subtarget.inMips16HardFloat()) { 2637 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(CLI.Callee)) { 2638 llvm::StringRef Sym = G->getGlobal()->getName(); 2639 Function *F = G->getGlobal()->getParent()->getFunction(Sym); 2640 if (F && F->hasFnAttribute("__Mips16RetHelper")) { 2641 Mask = MipsRegisterInfo::getMips16RetHelperMask(); 2642 } 2643 } 2644 } 2645 Ops.push_back(CLI.DAG.getRegisterMask(Mask)); 2646 2647 if (InFlag.getNode()) 2648 Ops.push_back(InFlag); 2649 } 2650 2651 /// LowerCall - functions arguments are copied from virtual regs to 2652 /// (physical regs)/(stack frame), CALLSEQ_START and CALLSEQ_END are emitted. 2653 SDValue 2654 MipsTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI, 2655 SmallVectorImpl<SDValue> &InVals) const { 2656 SelectionDAG &DAG = CLI.DAG; 2657 SDLoc DL = CLI.DL; 2658 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs; 2659 SmallVectorImpl<SDValue> &OutVals = CLI.OutVals; 2660 SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins; 2661 SDValue Chain = CLI.Chain; 2662 SDValue Callee = CLI.Callee; 2663 bool &IsTailCall = CLI.IsTailCall; 2664 CallingConv::ID CallConv = CLI.CallConv; 2665 bool IsVarArg = CLI.IsVarArg; 2666 2667 MachineFunction &MF = DAG.getMachineFunction(); 2668 MachineFrameInfo &MFI = MF.getFrameInfo(); 2669 const TargetFrameLowering *TFL = Subtarget.getFrameLowering(); 2670 MipsFunctionInfo *FuncInfo = MF.getInfo<MipsFunctionInfo>(); 2671 bool IsPIC = isPositionIndependent(); 2672 2673 // Analyze operands of the call, assigning locations to each operand. 2674 SmallVector<CCValAssign, 16> ArgLocs; 2675 MipsCCState CCInfo( 2676 CallConv, IsVarArg, DAG.getMachineFunction(), ArgLocs, *DAG.getContext(), 2677 MipsCCState::getSpecialCallingConvForCallee(Callee.getNode(), Subtarget)); 2678 2679 // Allocate the reserved argument area. It seems strange to do this from the 2680 // caller side but removing it breaks the frame size calculation. 2681 CCInfo.AllocateStack(ABI.GetCalleeAllocdArgSizeInBytes(CallConv), 1); 2682 2683 CCInfo.AnalyzeCallOperands(Outs, CC_Mips, CLI.getArgs(), Callee.getNode()); 2684 2685 // Get a count of how many bytes are to be pushed on the stack. 2686 unsigned NextStackOffset = CCInfo.getNextStackOffset(); 2687 2688 // Check if it's really possible to do a tail call. 2689 if (IsTailCall) 2690 IsTailCall = isEligibleForTailCallOptimization( 2691 CCInfo, NextStackOffset, *MF.getInfo<MipsFunctionInfo>()); 2692 2693 if (!IsTailCall && CLI.CS && CLI.CS->isMustTailCall()) 2694 report_fatal_error("failed to perform tail call elimination on a call " 2695 "site marked musttail"); 2696 2697 if (IsTailCall) 2698 ++NumTailCalls; 2699 2700 // Chain is the output chain of the last Load/Store or CopyToReg node. 2701 // ByValChain is the output chain of the last Memcpy node created for copying 2702 // byval arguments to the stack. 2703 unsigned StackAlignment = TFL->getStackAlignment(); 2704 NextStackOffset = alignTo(NextStackOffset, StackAlignment); 2705 SDValue NextStackOffsetVal = DAG.getIntPtrConstant(NextStackOffset, DL, true); 2706 2707 if (!IsTailCall) 2708 Chain = DAG.getCALLSEQ_START(Chain, NextStackOffsetVal, DL); 2709 2710 SDValue StackPtr = 2711 DAG.getCopyFromReg(Chain, DL, ABI.IsN64() ? Mips::SP_64 : Mips::SP, 2712 getPointerTy(DAG.getDataLayout())); 2713 2714 std::deque< std::pair<unsigned, SDValue> > RegsToPass; 2715 SmallVector<SDValue, 8> MemOpChains; 2716 2717 CCInfo.rewindByValRegsInfo(); 2718 2719 // Walk the register/memloc assignments, inserting copies/loads. 2720 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { 2721 SDValue Arg = OutVals[i]; 2722 CCValAssign &VA = ArgLocs[i]; 2723 MVT ValVT = VA.getValVT(), LocVT = VA.getLocVT(); 2724 ISD::ArgFlagsTy Flags = Outs[i].Flags; 2725 bool UseUpperBits = false; 2726 2727 // ByVal Arg. 2728 if (Flags.isByVal()) { 2729 unsigned FirstByValReg, LastByValReg; 2730 unsigned ByValIdx = CCInfo.getInRegsParamsProcessed(); 2731 CCInfo.getInRegsParamInfo(ByValIdx, FirstByValReg, LastByValReg); 2732 2733 assert(Flags.getByValSize() && 2734 "ByVal args of size 0 should have been ignored by front-end."); 2735 assert(ByValIdx < CCInfo.getInRegsParamsCount()); 2736 assert(!IsTailCall && 2737 "Do not tail-call optimize if there is a byval argument."); 2738 passByValArg(Chain, DL, RegsToPass, MemOpChains, StackPtr, MFI, DAG, Arg, 2739 FirstByValReg, LastByValReg, Flags, Subtarget.isLittle(), 2740 VA); 2741 CCInfo.nextInRegsParam(); 2742 continue; 2743 } 2744 2745 // Promote the value if needed. 2746 switch (VA.getLocInfo()) { 2747 default: 2748 llvm_unreachable("Unknown loc info!"); 2749 case CCValAssign::Full: 2750 if (VA.isRegLoc()) { 2751 if ((ValVT == MVT::f32 && LocVT == MVT::i32) || 2752 (ValVT == MVT::f64 && LocVT == MVT::i64) || 2753 (ValVT == MVT::i64 && LocVT == MVT::f64)) 2754 Arg = DAG.getNode(ISD::BITCAST, DL, LocVT, Arg); 2755 else if (ValVT == MVT::f64 && LocVT == MVT::i32) { 2756 SDValue Lo = DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32, 2757 Arg, DAG.getConstant(0, DL, MVT::i32)); 2758 SDValue Hi = DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32, 2759 Arg, DAG.getConstant(1, DL, MVT::i32)); 2760 if (!Subtarget.isLittle()) 2761 std::swap(Lo, Hi); 2762 unsigned LocRegLo = VA.getLocReg(); 2763 unsigned LocRegHigh = getNextIntArgReg(LocRegLo); 2764 RegsToPass.push_back(std::make_pair(LocRegLo, Lo)); 2765 RegsToPass.push_back(std::make_pair(LocRegHigh, Hi)); 2766 continue; 2767 } 2768 } 2769 break; 2770 case CCValAssign::BCvt: 2771 Arg = DAG.getNode(ISD::BITCAST, DL, LocVT, Arg); 2772 break; 2773 case CCValAssign::SExtUpper: 2774 UseUpperBits = true; 2775 LLVM_FALLTHROUGH; 2776 case CCValAssign::SExt: 2777 Arg = DAG.getNode(ISD::SIGN_EXTEND, DL, LocVT, Arg); 2778 break; 2779 case CCValAssign::ZExtUpper: 2780 UseUpperBits = true; 2781 LLVM_FALLTHROUGH; 2782 case CCValAssign::ZExt: 2783 Arg = DAG.getNode(ISD::ZERO_EXTEND, DL, LocVT, Arg); 2784 break; 2785 case CCValAssign::AExtUpper: 2786 UseUpperBits = true; 2787 LLVM_FALLTHROUGH; 2788 case CCValAssign::AExt: 2789 Arg = DAG.getNode(ISD::ANY_EXTEND, DL, LocVT, Arg); 2790 break; 2791 } 2792 2793 if (UseUpperBits) { 2794 unsigned ValSizeInBits = Outs[i].ArgVT.getSizeInBits(); 2795 unsigned LocSizeInBits = VA.getLocVT().getSizeInBits(); 2796 Arg = DAG.getNode( 2797 ISD::SHL, DL, VA.getLocVT(), Arg, 2798 DAG.getConstant(LocSizeInBits - ValSizeInBits, DL, VA.getLocVT())); 2799 } 2800 2801 // Arguments that can be passed on register must be kept at 2802 // RegsToPass vector 2803 if (VA.isRegLoc()) { 2804 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg)); 2805 continue; 2806 } 2807 2808 // Register can't get to this point... 2809 assert(VA.isMemLoc()); 2810 2811 // emit ISD::STORE whichs stores the 2812 // parameter value to a stack Location 2813 MemOpChains.push_back(passArgOnStack(StackPtr, VA.getLocMemOffset(), 2814 Chain, Arg, DL, IsTailCall, DAG)); 2815 } 2816 2817 // Transform all store nodes into one single node because all store 2818 // nodes are independent of each other. 2819 if (!MemOpChains.empty()) 2820 Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, MemOpChains); 2821 2822 // If the callee is a GlobalAddress/ExternalSymbol node (quite common, every 2823 // direct call is) turn it into a TargetGlobalAddress/TargetExternalSymbol 2824 // node so that legalize doesn't hack it. 2825 bool IsPICCall = (ABI.IsN64() || IsPIC); // true if calls are translated to 2826 // jalr $25 2827 bool GlobalOrExternal = false, InternalLinkage = false, IsCallReloc = false; 2828 SDValue CalleeLo; 2829 EVT Ty = Callee.getValueType(); 2830 2831 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) { 2832 if (IsPICCall) { 2833 const GlobalValue *Val = G->getGlobal(); 2834 InternalLinkage = Val->hasInternalLinkage(); 2835 2836 if (InternalLinkage) 2837 Callee = getAddrLocal(G, DL, Ty, DAG, ABI.IsN32() || ABI.IsN64()); 2838 else if (LargeGOT) { 2839 Callee = getAddrGlobalLargeGOT(G, DL, Ty, DAG, MipsII::MO_CALL_HI16, 2840 MipsII::MO_CALL_LO16, Chain, 2841 FuncInfo->callPtrInfo(Val)); 2842 IsCallReloc = true; 2843 } else { 2844 Callee = getAddrGlobal(G, DL, Ty, DAG, MipsII::MO_GOT_CALL, Chain, 2845 FuncInfo->callPtrInfo(Val)); 2846 IsCallReloc = true; 2847 } 2848 } else 2849 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), DL, 2850 getPointerTy(DAG.getDataLayout()), 0, 2851 MipsII::MO_NO_FLAG); 2852 GlobalOrExternal = true; 2853 } 2854 else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) { 2855 const char *Sym = S->getSymbol(); 2856 2857 if (!ABI.IsN64() && !IsPIC) // !N64 && static 2858 Callee = DAG.getTargetExternalSymbol( 2859 Sym, getPointerTy(DAG.getDataLayout()), MipsII::MO_NO_FLAG); 2860 else if (LargeGOT) { 2861 Callee = getAddrGlobalLargeGOT(S, DL, Ty, DAG, MipsII::MO_CALL_HI16, 2862 MipsII::MO_CALL_LO16, Chain, 2863 FuncInfo->callPtrInfo(Sym)); 2864 IsCallReloc = true; 2865 } else { // N64 || PIC 2866 Callee = getAddrGlobal(S, DL, Ty, DAG, MipsII::MO_GOT_CALL, Chain, 2867 FuncInfo->callPtrInfo(Sym)); 2868 IsCallReloc = true; 2869 } 2870 2871 GlobalOrExternal = true; 2872 } 2873 2874 SmallVector<SDValue, 8> Ops(1, Chain); 2875 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue); 2876 2877 getOpndList(Ops, RegsToPass, IsPICCall, GlobalOrExternal, InternalLinkage, 2878 IsCallReloc, CLI, Callee, Chain); 2879 2880 if (IsTailCall) { 2881 MF.getFrameInfo().setHasTailCall(); 2882 return DAG.getNode(MipsISD::TailCall, DL, MVT::Other, Ops); 2883 } 2884 2885 Chain = DAG.getNode(MipsISD::JmpLink, DL, NodeTys, Ops); 2886 SDValue InFlag = Chain.getValue(1); 2887 2888 // Create the CALLSEQ_END node. 2889 Chain = DAG.getCALLSEQ_END(Chain, NextStackOffsetVal, 2890 DAG.getIntPtrConstant(0, DL, true), InFlag, DL); 2891 InFlag = Chain.getValue(1); 2892 2893 // Handle result values, copying them out of physregs into vregs that we 2894 // return. 2895 return LowerCallResult(Chain, InFlag, CallConv, IsVarArg, Ins, DL, DAG, 2896 InVals, CLI); 2897 } 2898 2899 /// LowerCallResult - Lower the result values of a call into the 2900 /// appropriate copies out of appropriate physical registers. 2901 SDValue MipsTargetLowering::LowerCallResult( 2902 SDValue Chain, SDValue InFlag, CallingConv::ID CallConv, bool IsVarArg, 2903 const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &DL, 2904 SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals, 2905 TargetLowering::CallLoweringInfo &CLI) const { 2906 // Assign locations to each value returned by this call. 2907 SmallVector<CCValAssign, 16> RVLocs; 2908 MipsCCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), RVLocs, 2909 *DAG.getContext()); 2910 CCInfo.AnalyzeCallResult(Ins, RetCC_Mips, CLI); 2911 2912 // Copy all of the result registers out of their specified physreg. 2913 for (unsigned i = 0; i != RVLocs.size(); ++i) { 2914 CCValAssign &VA = RVLocs[i]; 2915 assert(VA.isRegLoc() && "Can only return in registers!"); 2916 2917 SDValue Val = DAG.getCopyFromReg(Chain, DL, RVLocs[i].getLocReg(), 2918 RVLocs[i].getLocVT(), InFlag); 2919 Chain = Val.getValue(1); 2920 InFlag = Val.getValue(2); 2921 2922 if (VA.isUpperBitsInLoc()) { 2923 unsigned ValSizeInBits = Ins[i].ArgVT.getSizeInBits(); 2924 unsigned LocSizeInBits = VA.getLocVT().getSizeInBits(); 2925 unsigned Shift = 2926 VA.getLocInfo() == CCValAssign::ZExtUpper ? ISD::SRL : ISD::SRA; 2927 Val = DAG.getNode( 2928 Shift, DL, VA.getLocVT(), Val, 2929 DAG.getConstant(LocSizeInBits - ValSizeInBits, DL, VA.getLocVT())); 2930 } 2931 2932 switch (VA.getLocInfo()) { 2933 default: 2934 llvm_unreachable("Unknown loc info!"); 2935 case CCValAssign::Full: 2936 break; 2937 case CCValAssign::BCvt: 2938 Val = DAG.getNode(ISD::BITCAST, DL, VA.getValVT(), Val); 2939 break; 2940 case CCValAssign::AExt: 2941 case CCValAssign::AExtUpper: 2942 Val = DAG.getNode(ISD::TRUNCATE, DL, VA.getValVT(), Val); 2943 break; 2944 case CCValAssign::ZExt: 2945 case CCValAssign::ZExtUpper: 2946 Val = DAG.getNode(ISD::AssertZext, DL, VA.getLocVT(), Val, 2947 DAG.getValueType(VA.getValVT())); 2948 Val = DAG.getNode(ISD::TRUNCATE, DL, VA.getValVT(), Val); 2949 break; 2950 case CCValAssign::SExt: 2951 case CCValAssign::SExtUpper: 2952 Val = DAG.getNode(ISD::AssertSext, DL, VA.getLocVT(), Val, 2953 DAG.getValueType(VA.getValVT())); 2954 Val = DAG.getNode(ISD::TRUNCATE, DL, VA.getValVT(), Val); 2955 break; 2956 } 2957 2958 InVals.push_back(Val); 2959 } 2960 2961 return Chain; 2962 } 2963 2964 static SDValue UnpackFromArgumentSlot(SDValue Val, const CCValAssign &VA, 2965 EVT ArgVT, const SDLoc &DL, 2966 SelectionDAG &DAG) { 2967 MVT LocVT = VA.getLocVT(); 2968 EVT ValVT = VA.getValVT(); 2969 2970 // Shift into the upper bits if necessary. 2971 switch (VA.getLocInfo()) { 2972 default: 2973 break; 2974 case CCValAssign::AExtUpper: 2975 case CCValAssign::SExtUpper: 2976 case CCValAssign::ZExtUpper: { 2977 unsigned ValSizeInBits = ArgVT.getSizeInBits(); 2978 unsigned LocSizeInBits = VA.getLocVT().getSizeInBits(); 2979 unsigned Opcode = 2980 VA.getLocInfo() == CCValAssign::ZExtUpper ? ISD::SRL : ISD::SRA; 2981 Val = DAG.getNode( 2982 Opcode, DL, VA.getLocVT(), Val, 2983 DAG.getConstant(LocSizeInBits - ValSizeInBits, DL, VA.getLocVT())); 2984 break; 2985 } 2986 } 2987 2988 // If this is an value smaller than the argument slot size (32-bit for O32, 2989 // 64-bit for N32/N64), it has been promoted in some way to the argument slot 2990 // size. Extract the value and insert any appropriate assertions regarding 2991 // sign/zero extension. 2992 switch (VA.getLocInfo()) { 2993 default: 2994 llvm_unreachable("Unknown loc info!"); 2995 case CCValAssign::Full: 2996 break; 2997 case CCValAssign::AExtUpper: 2998 case CCValAssign::AExt: 2999 Val = DAG.getNode(ISD::TRUNCATE, DL, ValVT, Val); 3000 break; 3001 case CCValAssign::SExtUpper: 3002 case CCValAssign::SExt: 3003 Val = DAG.getNode(ISD::AssertSext, DL, LocVT, Val, DAG.getValueType(ValVT)); 3004 Val = DAG.getNode(ISD::TRUNCATE, DL, ValVT, Val); 3005 break; 3006 case CCValAssign::ZExtUpper: 3007 case CCValAssign::ZExt: 3008 Val = DAG.getNode(ISD::AssertZext, DL, LocVT, Val, DAG.getValueType(ValVT)); 3009 Val = DAG.getNode(ISD::TRUNCATE, DL, ValVT, Val); 3010 break; 3011 case CCValAssign::BCvt: 3012 Val = DAG.getNode(ISD::BITCAST, DL, ValVT, Val); 3013 break; 3014 } 3015 3016 return Val; 3017 } 3018 3019 //===----------------------------------------------------------------------===// 3020 // Formal Arguments Calling Convention Implementation 3021 //===----------------------------------------------------------------------===// 3022 /// LowerFormalArguments - transform physical registers into virtual registers 3023 /// and generate load operations for arguments places on the stack. 3024 SDValue MipsTargetLowering::LowerFormalArguments( 3025 SDValue Chain, CallingConv::ID CallConv, bool IsVarArg, 3026 const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &DL, 3027 SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const { 3028 MachineFunction &MF = DAG.getMachineFunction(); 3029 MachineFrameInfo &MFI = MF.getFrameInfo(); 3030 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>(); 3031 3032 MipsFI->setVarArgsFrameIndex(0); 3033 3034 // Used with vargs to acumulate store chains. 3035 std::vector<SDValue> OutChains; 3036 3037 // Assign locations to all of the incoming arguments. 3038 SmallVector<CCValAssign, 16> ArgLocs; 3039 MipsCCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), ArgLocs, 3040 *DAG.getContext()); 3041 CCInfo.AllocateStack(ABI.GetCalleeAllocdArgSizeInBytes(CallConv), 1); 3042 const Function *Func = DAG.getMachineFunction().getFunction(); 3043 Function::const_arg_iterator FuncArg = Func->arg_begin(); 3044 3045 if (Func->hasFnAttribute("interrupt") && !Func->arg_empty()) 3046 report_fatal_error( 3047 "Functions with the interrupt attribute cannot have arguments!"); 3048 3049 CCInfo.AnalyzeFormalArguments(Ins, CC_Mips_FixedArg); 3050 MipsFI->setFormalArgInfo(CCInfo.getNextStackOffset(), 3051 CCInfo.getInRegsParamsCount() > 0); 3052 3053 unsigned CurArgIdx = 0; 3054 CCInfo.rewindByValRegsInfo(); 3055 3056 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { 3057 CCValAssign &VA = ArgLocs[i]; 3058 if (Ins[i].isOrigArg()) { 3059 std::advance(FuncArg, Ins[i].getOrigArgIndex() - CurArgIdx); 3060 CurArgIdx = Ins[i].getOrigArgIndex(); 3061 } 3062 EVT ValVT = VA.getValVT(); 3063 ISD::ArgFlagsTy Flags = Ins[i].Flags; 3064 bool IsRegLoc = VA.isRegLoc(); 3065 3066 if (Flags.isByVal()) { 3067 assert(Ins[i].isOrigArg() && "Byval arguments cannot be implicit"); 3068 unsigned FirstByValReg, LastByValReg; 3069 unsigned ByValIdx = CCInfo.getInRegsParamsProcessed(); 3070 CCInfo.getInRegsParamInfo(ByValIdx, FirstByValReg, LastByValReg); 3071 3072 assert(Flags.getByValSize() && 3073 "ByVal args of size 0 should have been ignored by front-end."); 3074 assert(ByValIdx < CCInfo.getInRegsParamsCount()); 3075 copyByValRegs(Chain, DL, OutChains, DAG, Flags, InVals, &*FuncArg, 3076 FirstByValReg, LastByValReg, VA, CCInfo); 3077 CCInfo.nextInRegsParam(); 3078 continue; 3079 } 3080 3081 // Arguments stored on registers 3082 if (IsRegLoc) { 3083 MVT RegVT = VA.getLocVT(); 3084 unsigned ArgReg = VA.getLocReg(); 3085 const TargetRegisterClass *RC = getRegClassFor(RegVT); 3086 3087 // Transform the arguments stored on 3088 // physical registers into virtual ones 3089 unsigned Reg = addLiveIn(DAG.getMachineFunction(), ArgReg, RC); 3090 SDValue ArgValue = DAG.getCopyFromReg(Chain, DL, Reg, RegVT); 3091 3092 ArgValue = UnpackFromArgumentSlot(ArgValue, VA, Ins[i].ArgVT, DL, DAG); 3093 3094 // Handle floating point arguments passed in integer registers and 3095 // long double arguments passed in floating point registers. 3096 if ((RegVT == MVT::i32 && ValVT == MVT::f32) || 3097 (RegVT == MVT::i64 && ValVT == MVT::f64) || 3098 (RegVT == MVT::f64 && ValVT == MVT::i64)) 3099 ArgValue = DAG.getNode(ISD::BITCAST, DL, ValVT, ArgValue); 3100 else if (ABI.IsO32() && RegVT == MVT::i32 && 3101 ValVT == MVT::f64) { 3102 unsigned Reg2 = addLiveIn(DAG.getMachineFunction(), 3103 getNextIntArgReg(ArgReg), RC); 3104 SDValue ArgValue2 = DAG.getCopyFromReg(Chain, DL, Reg2, RegVT); 3105 if (!Subtarget.isLittle()) 3106 std::swap(ArgValue, ArgValue2); 3107 ArgValue = DAG.getNode(MipsISD::BuildPairF64, DL, MVT::f64, 3108 ArgValue, ArgValue2); 3109 } 3110 3111 InVals.push_back(ArgValue); 3112 } else { // VA.isRegLoc() 3113 MVT LocVT = VA.getLocVT(); 3114 3115 if (ABI.IsO32()) { 3116 // We ought to be able to use LocVT directly but O32 sets it to i32 3117 // when allocating floating point values to integer registers. 3118 // This shouldn't influence how we load the value into registers unless 3119 // we are targeting softfloat. 3120 if (VA.getValVT().isFloatingPoint() && !Subtarget.useSoftFloat()) 3121 LocVT = VA.getValVT(); 3122 } 3123 3124 // sanity check 3125 assert(VA.isMemLoc()); 3126 3127 // The stack pointer offset is relative to the caller stack frame. 3128 int FI = MFI.CreateFixedObject(LocVT.getSizeInBits() / 8, 3129 VA.getLocMemOffset(), true); 3130 3131 // Create load nodes to retrieve arguments from the stack 3132 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy(DAG.getDataLayout())); 3133 SDValue ArgValue = DAG.getLoad( 3134 LocVT, DL, Chain, FIN, 3135 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), FI)); 3136 OutChains.push_back(ArgValue.getValue(1)); 3137 3138 ArgValue = UnpackFromArgumentSlot(ArgValue, VA, Ins[i].ArgVT, DL, DAG); 3139 3140 InVals.push_back(ArgValue); 3141 } 3142 } 3143 3144 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { 3145 // The mips ABIs for returning structs by value requires that we copy 3146 // the sret argument into $v0 for the return. Save the argument into 3147 // a virtual register so that we can access it from the return points. 3148 if (Ins[i].Flags.isSRet()) { 3149 unsigned Reg = MipsFI->getSRetReturnReg(); 3150 if (!Reg) { 3151 Reg = MF.getRegInfo().createVirtualRegister( 3152 getRegClassFor(ABI.IsN64() ? MVT::i64 : MVT::i32)); 3153 MipsFI->setSRetReturnReg(Reg); 3154 } 3155 SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), DL, Reg, InVals[i]); 3156 Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, Copy, Chain); 3157 break; 3158 } 3159 } 3160 3161 if (IsVarArg) 3162 writeVarArgRegs(OutChains, Chain, DL, DAG, CCInfo); 3163 3164 // All stores are grouped in one node to allow the matching between 3165 // the size of Ins and InVals. This only happens when on varg functions 3166 if (!OutChains.empty()) { 3167 OutChains.push_back(Chain); 3168 Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, OutChains); 3169 } 3170 3171 return Chain; 3172 } 3173 3174 //===----------------------------------------------------------------------===// 3175 // Return Value Calling Convention Implementation 3176 //===----------------------------------------------------------------------===// 3177 3178 bool 3179 MipsTargetLowering::CanLowerReturn(CallingConv::ID CallConv, 3180 MachineFunction &MF, bool IsVarArg, 3181 const SmallVectorImpl<ISD::OutputArg> &Outs, 3182 LLVMContext &Context) const { 3183 SmallVector<CCValAssign, 16> RVLocs; 3184 MipsCCState CCInfo(CallConv, IsVarArg, MF, RVLocs, Context); 3185 return CCInfo.CheckReturn(Outs, RetCC_Mips); 3186 } 3187 3188 bool 3189 MipsTargetLowering::shouldSignExtendTypeInLibCall(EVT Type, bool IsSigned) const { 3190 if (Subtarget.hasMips3() && Subtarget.useSoftFloat()) { 3191 if (Type == MVT::i32) 3192 return true; 3193 } 3194 return IsSigned; 3195 } 3196 3197 SDValue 3198 MipsTargetLowering::LowerInterruptReturn(SmallVectorImpl<SDValue> &RetOps, 3199 const SDLoc &DL, 3200 SelectionDAG &DAG) const { 3201 3202 MachineFunction &MF = DAG.getMachineFunction(); 3203 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>(); 3204 3205 MipsFI->setISR(); 3206 3207 return DAG.getNode(MipsISD::ERet, DL, MVT::Other, RetOps); 3208 } 3209 3210 SDValue 3211 MipsTargetLowering::LowerReturn(SDValue Chain, CallingConv::ID CallConv, 3212 bool IsVarArg, 3213 const SmallVectorImpl<ISD::OutputArg> &Outs, 3214 const SmallVectorImpl<SDValue> &OutVals, 3215 const SDLoc &DL, SelectionDAG &DAG) const { 3216 // CCValAssign - represent the assignment of 3217 // the return value to a location 3218 SmallVector<CCValAssign, 16> RVLocs; 3219 MachineFunction &MF = DAG.getMachineFunction(); 3220 3221 // CCState - Info about the registers and stack slot. 3222 MipsCCState CCInfo(CallConv, IsVarArg, MF, RVLocs, *DAG.getContext()); 3223 3224 // Analyze return values. 3225 CCInfo.AnalyzeReturn(Outs, RetCC_Mips); 3226 3227 SDValue Flag; 3228 SmallVector<SDValue, 4> RetOps(1, Chain); 3229 3230 // Copy the result values into the output registers. 3231 for (unsigned i = 0; i != RVLocs.size(); ++i) { 3232 SDValue Val = OutVals[i]; 3233 CCValAssign &VA = RVLocs[i]; 3234 assert(VA.isRegLoc() && "Can only return in registers!"); 3235 bool UseUpperBits = false; 3236 3237 switch (VA.getLocInfo()) { 3238 default: 3239 llvm_unreachable("Unknown loc info!"); 3240 case CCValAssign::Full: 3241 break; 3242 case CCValAssign::BCvt: 3243 Val = DAG.getNode(ISD::BITCAST, DL, VA.getLocVT(), Val); 3244 break; 3245 case CCValAssign::AExtUpper: 3246 UseUpperBits = true; 3247 LLVM_FALLTHROUGH; 3248 case CCValAssign::AExt: 3249 Val = DAG.getNode(ISD::ANY_EXTEND, DL, VA.getLocVT(), Val); 3250 break; 3251 case CCValAssign::ZExtUpper: 3252 UseUpperBits = true; 3253 LLVM_FALLTHROUGH; 3254 case CCValAssign::ZExt: 3255 Val = DAG.getNode(ISD::ZERO_EXTEND, DL, VA.getLocVT(), Val); 3256 break; 3257 case CCValAssign::SExtUpper: 3258 UseUpperBits = true; 3259 LLVM_FALLTHROUGH; 3260 case CCValAssign::SExt: 3261 Val = DAG.getNode(ISD::SIGN_EXTEND, DL, VA.getLocVT(), Val); 3262 break; 3263 } 3264 3265 if (UseUpperBits) { 3266 unsigned ValSizeInBits = Outs[i].ArgVT.getSizeInBits(); 3267 unsigned LocSizeInBits = VA.getLocVT().getSizeInBits(); 3268 Val = DAG.getNode( 3269 ISD::SHL, DL, VA.getLocVT(), Val, 3270 DAG.getConstant(LocSizeInBits - ValSizeInBits, DL, VA.getLocVT())); 3271 } 3272 3273 Chain = DAG.getCopyToReg(Chain, DL, VA.getLocReg(), Val, Flag); 3274 3275 // Guarantee that all emitted copies are stuck together with flags. 3276 Flag = Chain.getValue(1); 3277 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT())); 3278 } 3279 3280 // The mips ABIs for returning structs by value requires that we copy 3281 // the sret argument into $v0 for the return. We saved the argument into 3282 // a virtual register in the entry block, so now we copy the value out 3283 // and into $v0. 3284 if (MF.getFunction()->hasStructRetAttr()) { 3285 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>(); 3286 unsigned Reg = MipsFI->getSRetReturnReg(); 3287 3288 if (!Reg) 3289 llvm_unreachable("sret virtual register not created in the entry block"); 3290 SDValue Val = 3291 DAG.getCopyFromReg(Chain, DL, Reg, getPointerTy(DAG.getDataLayout())); 3292 unsigned V0 = ABI.IsN64() ? Mips::V0_64 : Mips::V0; 3293 3294 Chain = DAG.getCopyToReg(Chain, DL, V0, Val, Flag); 3295 Flag = Chain.getValue(1); 3296 RetOps.push_back(DAG.getRegister(V0, getPointerTy(DAG.getDataLayout()))); 3297 } 3298 3299 RetOps[0] = Chain; // Update chain. 3300 3301 // Add the flag if we have it. 3302 if (Flag.getNode()) 3303 RetOps.push_back(Flag); 3304 3305 // ISRs must use "eret". 3306 if (DAG.getMachineFunction().getFunction()->hasFnAttribute("interrupt")) 3307 return LowerInterruptReturn(RetOps, DL, DAG); 3308 3309 // Standard return on Mips is a "jr $ra" 3310 return DAG.getNode(MipsISD::Ret, DL, MVT::Other, RetOps); 3311 } 3312 3313 //===----------------------------------------------------------------------===// 3314 // Mips Inline Assembly Support 3315 //===----------------------------------------------------------------------===// 3316 3317 /// getConstraintType - Given a constraint letter, return the type of 3318 /// constraint it is for this target. 3319 MipsTargetLowering::ConstraintType 3320 MipsTargetLowering::getConstraintType(StringRef Constraint) const { 3321 // Mips specific constraints 3322 // GCC config/mips/constraints.md 3323 // 3324 // 'd' : An address register. Equivalent to r 3325 // unless generating MIPS16 code. 3326 // 'y' : Equivalent to r; retained for 3327 // backwards compatibility. 3328 // 'c' : A register suitable for use in an indirect 3329 // jump. This will always be $25 for -mabicalls. 3330 // 'l' : The lo register. 1 word storage. 3331 // 'x' : The hilo register pair. Double word storage. 3332 if (Constraint.size() == 1) { 3333 switch (Constraint[0]) { 3334 default : break; 3335 case 'd': 3336 case 'y': 3337 case 'f': 3338 case 'c': 3339 case 'l': 3340 case 'x': 3341 return C_RegisterClass; 3342 case 'R': 3343 return C_Memory; 3344 } 3345 } 3346 3347 if (Constraint == "ZC") 3348 return C_Memory; 3349 3350 return TargetLowering::getConstraintType(Constraint); 3351 } 3352 3353 /// Examine constraint type and operand type and determine a weight value. 3354 /// This object must already have been set up with the operand type 3355 /// and the current alternative constraint selected. 3356 TargetLowering::ConstraintWeight 3357 MipsTargetLowering::getSingleConstraintMatchWeight( 3358 AsmOperandInfo &info, const char *constraint) const { 3359 ConstraintWeight weight = CW_Invalid; 3360 Value *CallOperandVal = info.CallOperandVal; 3361 // If we don't have a value, we can't do a match, 3362 // but allow it at the lowest weight. 3363 if (!CallOperandVal) 3364 return CW_Default; 3365 Type *type = CallOperandVal->getType(); 3366 // Look at the constraint type. 3367 switch (*constraint) { 3368 default: 3369 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint); 3370 break; 3371 case 'd': 3372 case 'y': 3373 if (type->isIntegerTy()) 3374 weight = CW_Register; 3375 break; 3376 case 'f': // FPU or MSA register 3377 if (Subtarget.hasMSA() && type->isVectorTy() && 3378 cast<VectorType>(type)->getBitWidth() == 128) 3379 weight = CW_Register; 3380 else if (type->isFloatTy()) 3381 weight = CW_Register; 3382 break; 3383 case 'c': // $25 for indirect jumps 3384 case 'l': // lo register 3385 case 'x': // hilo register pair 3386 if (type->isIntegerTy()) 3387 weight = CW_SpecificReg; 3388 break; 3389 case 'I': // signed 16 bit immediate 3390 case 'J': // integer zero 3391 case 'K': // unsigned 16 bit immediate 3392 case 'L': // signed 32 bit immediate where lower 16 bits are 0 3393 case 'N': // immediate in the range of -65535 to -1 (inclusive) 3394 case 'O': // signed 15 bit immediate (+- 16383) 3395 case 'P': // immediate in the range of 65535 to 1 (inclusive) 3396 if (isa<ConstantInt>(CallOperandVal)) 3397 weight = CW_Constant; 3398 break; 3399 case 'R': 3400 weight = CW_Memory; 3401 break; 3402 } 3403 return weight; 3404 } 3405 3406 /// This is a helper function to parse a physical register string and split it 3407 /// into non-numeric and numeric parts (Prefix and Reg). The first boolean flag 3408 /// that is returned indicates whether parsing was successful. The second flag 3409 /// is true if the numeric part exists. 3410 static std::pair<bool, bool> parsePhysicalReg(StringRef C, StringRef &Prefix, 3411 unsigned long long &Reg) { 3412 if (C.front() != '{' || C.back() != '}') 3413 return std::make_pair(false, false); 3414 3415 // Search for the first numeric character. 3416 StringRef::const_iterator I, B = C.begin() + 1, E = C.end() - 1; 3417 I = std::find_if(B, E, isdigit); 3418 3419 Prefix = StringRef(B, I - B); 3420 3421 // The second flag is set to false if no numeric characters were found. 3422 if (I == E) 3423 return std::make_pair(true, false); 3424 3425 // Parse the numeric characters. 3426 return std::make_pair(!getAsUnsignedInteger(StringRef(I, E - I), 10, Reg), 3427 true); 3428 } 3429 3430 std::pair<unsigned, const TargetRegisterClass *> MipsTargetLowering:: 3431 parseRegForInlineAsmConstraint(StringRef C, MVT VT) const { 3432 const TargetRegisterInfo *TRI = 3433 Subtarget.getRegisterInfo(); 3434 const TargetRegisterClass *RC; 3435 StringRef Prefix; 3436 unsigned long long Reg; 3437 3438 std::pair<bool, bool> R = parsePhysicalReg(C, Prefix, Reg); 3439 3440 if (!R.first) 3441 return std::make_pair(0U, nullptr); 3442 3443 if ((Prefix == "hi" || Prefix == "lo")) { // Parse hi/lo. 3444 // No numeric characters follow "hi" or "lo". 3445 if (R.second) 3446 return std::make_pair(0U, nullptr); 3447 3448 RC = TRI->getRegClass(Prefix == "hi" ? 3449 Mips::HI32RegClassID : Mips::LO32RegClassID); 3450 return std::make_pair(*(RC->begin()), RC); 3451 } else if (Prefix.startswith("$msa")) { 3452 // Parse $msa(ir|csr|access|save|modify|request|map|unmap) 3453 3454 // No numeric characters follow the name. 3455 if (R.second) 3456 return std::make_pair(0U, nullptr); 3457 3458 Reg = StringSwitch<unsigned long long>(Prefix) 3459 .Case("$msair", Mips::MSAIR) 3460 .Case("$msacsr", Mips::MSACSR) 3461 .Case("$msaaccess", Mips::MSAAccess) 3462 .Case("$msasave", Mips::MSASave) 3463 .Case("$msamodify", Mips::MSAModify) 3464 .Case("$msarequest", Mips::MSARequest) 3465 .Case("$msamap", Mips::MSAMap) 3466 .Case("$msaunmap", Mips::MSAUnmap) 3467 .Default(0); 3468 3469 if (!Reg) 3470 return std::make_pair(0U, nullptr); 3471 3472 RC = TRI->getRegClass(Mips::MSACtrlRegClassID); 3473 return std::make_pair(Reg, RC); 3474 } 3475 3476 if (!R.second) 3477 return std::make_pair(0U, nullptr); 3478 3479 if (Prefix == "$f") { // Parse $f0-$f31. 3480 // If the size of FP registers is 64-bit or Reg is an even number, select 3481 // the 64-bit register class. Otherwise, select the 32-bit register class. 3482 if (VT == MVT::Other) 3483 VT = (Subtarget.isFP64bit() || !(Reg % 2)) ? MVT::f64 : MVT::f32; 3484 3485 RC = getRegClassFor(VT); 3486 3487 if (RC == &Mips::AFGR64RegClass) { 3488 assert(Reg % 2 == 0); 3489 Reg >>= 1; 3490 } 3491 } else if (Prefix == "$fcc") // Parse $fcc0-$fcc7. 3492 RC = TRI->getRegClass(Mips::FCCRegClassID); 3493 else if (Prefix == "$w") { // Parse $w0-$w31. 3494 RC = getRegClassFor((VT == MVT::Other) ? MVT::v16i8 : VT); 3495 } else { // Parse $0-$31. 3496 assert(Prefix == "$"); 3497 RC = getRegClassFor((VT == MVT::Other) ? MVT::i32 : VT); 3498 } 3499 3500 assert(Reg < RC->getNumRegs()); 3501 return std::make_pair(*(RC->begin() + Reg), RC); 3502 } 3503 3504 /// Given a register class constraint, like 'r', if this corresponds directly 3505 /// to an LLVM register class, return a register of 0 and the register class 3506 /// pointer. 3507 std::pair<unsigned, const TargetRegisterClass *> 3508 MipsTargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, 3509 StringRef Constraint, 3510 MVT VT) const { 3511 if (Constraint.size() == 1) { 3512 switch (Constraint[0]) { 3513 case 'd': // Address register. Same as 'r' unless generating MIPS16 code. 3514 case 'y': // Same as 'r'. Exists for compatibility. 3515 case 'r': 3516 if (VT == MVT::i32 || VT == MVT::i16 || VT == MVT::i8) { 3517 if (Subtarget.inMips16Mode()) 3518 return std::make_pair(0U, &Mips::CPU16RegsRegClass); 3519 return std::make_pair(0U, &Mips::GPR32RegClass); 3520 } 3521 if (VT == MVT::i64 && !Subtarget.isGP64bit()) 3522 return std::make_pair(0U, &Mips::GPR32RegClass); 3523 if (VT == MVT::i64 && Subtarget.isGP64bit()) 3524 return std::make_pair(0U, &Mips::GPR64RegClass); 3525 // This will generate an error message 3526 return std::make_pair(0U, nullptr); 3527 case 'f': // FPU or MSA register 3528 if (VT == MVT::v16i8) 3529 return std::make_pair(0U, &Mips::MSA128BRegClass); 3530 else if (VT == MVT::v8i16 || VT == MVT::v8f16) 3531 return std::make_pair(0U, &Mips::MSA128HRegClass); 3532 else if (VT == MVT::v4i32 || VT == MVT::v4f32) 3533 return std::make_pair(0U, &Mips::MSA128WRegClass); 3534 else if (VT == MVT::v2i64 || VT == MVT::v2f64) 3535 return std::make_pair(0U, &Mips::MSA128DRegClass); 3536 else if (VT == MVT::f32) 3537 return std::make_pair(0U, &Mips::FGR32RegClass); 3538 else if ((VT == MVT::f64) && (!Subtarget.isSingleFloat())) { 3539 if (Subtarget.isFP64bit()) 3540 return std::make_pair(0U, &Mips::FGR64RegClass); 3541 return std::make_pair(0U, &Mips::AFGR64RegClass); 3542 } 3543 break; 3544 case 'c': // register suitable for indirect jump 3545 if (VT == MVT::i32) 3546 return std::make_pair((unsigned)Mips::T9, &Mips::GPR32RegClass); 3547 assert(VT == MVT::i64 && "Unexpected type."); 3548 return std::make_pair((unsigned)Mips::T9_64, &Mips::GPR64RegClass); 3549 case 'l': // register suitable for indirect jump 3550 if (VT == MVT::i32) 3551 return std::make_pair((unsigned)Mips::LO0, &Mips::LO32RegClass); 3552 return std::make_pair((unsigned)Mips::LO0_64, &Mips::LO64RegClass); 3553 case 'x': // register suitable for indirect jump 3554 // Fixme: Not triggering the use of both hi and low 3555 // This will generate an error message 3556 return std::make_pair(0U, nullptr); 3557 } 3558 } 3559 3560 std::pair<unsigned, const TargetRegisterClass *> R; 3561 R = parseRegForInlineAsmConstraint(Constraint, VT); 3562 3563 if (R.second) 3564 return R; 3565 3566 return TargetLowering::getRegForInlineAsmConstraint(TRI, Constraint, VT); 3567 } 3568 3569 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops 3570 /// vector. If it is invalid, don't add anything to Ops. 3571 void MipsTargetLowering::LowerAsmOperandForConstraint(SDValue Op, 3572 std::string &Constraint, 3573 std::vector<SDValue>&Ops, 3574 SelectionDAG &DAG) const { 3575 SDLoc DL(Op); 3576 SDValue Result; 3577 3578 // Only support length 1 constraints for now. 3579 if (Constraint.length() > 1) return; 3580 3581 char ConstraintLetter = Constraint[0]; 3582 switch (ConstraintLetter) { 3583 default: break; // This will fall through to the generic implementation 3584 case 'I': // Signed 16 bit constant 3585 // If this fails, the parent routine will give an error 3586 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 3587 EVT Type = Op.getValueType(); 3588 int64_t Val = C->getSExtValue(); 3589 if (isInt<16>(Val)) { 3590 Result = DAG.getTargetConstant(Val, DL, Type); 3591 break; 3592 } 3593 } 3594 return; 3595 case 'J': // integer zero 3596 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 3597 EVT Type = Op.getValueType(); 3598 int64_t Val = C->getZExtValue(); 3599 if (Val == 0) { 3600 Result = DAG.getTargetConstant(0, DL, Type); 3601 break; 3602 } 3603 } 3604 return; 3605 case 'K': // unsigned 16 bit immediate 3606 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 3607 EVT Type = Op.getValueType(); 3608 uint64_t Val = (uint64_t)C->getZExtValue(); 3609 if (isUInt<16>(Val)) { 3610 Result = DAG.getTargetConstant(Val, DL, Type); 3611 break; 3612 } 3613 } 3614 return; 3615 case 'L': // signed 32 bit immediate where lower 16 bits are 0 3616 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 3617 EVT Type = Op.getValueType(); 3618 int64_t Val = C->getSExtValue(); 3619 if ((isInt<32>(Val)) && ((Val & 0xffff) == 0)){ 3620 Result = DAG.getTargetConstant(Val, DL, Type); 3621 break; 3622 } 3623 } 3624 return; 3625 case 'N': // immediate in the range of -65535 to -1 (inclusive) 3626 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 3627 EVT Type = Op.getValueType(); 3628 int64_t Val = C->getSExtValue(); 3629 if ((Val >= -65535) && (Val <= -1)) { 3630 Result = DAG.getTargetConstant(Val, DL, Type); 3631 break; 3632 } 3633 } 3634 return; 3635 case 'O': // signed 15 bit immediate 3636 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 3637 EVT Type = Op.getValueType(); 3638 int64_t Val = C->getSExtValue(); 3639 if ((isInt<15>(Val))) { 3640 Result = DAG.getTargetConstant(Val, DL, Type); 3641 break; 3642 } 3643 } 3644 return; 3645 case 'P': // immediate in the range of 1 to 65535 (inclusive) 3646 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 3647 EVT Type = Op.getValueType(); 3648 int64_t Val = C->getSExtValue(); 3649 if ((Val <= 65535) && (Val >= 1)) { 3650 Result = DAG.getTargetConstant(Val, DL, Type); 3651 break; 3652 } 3653 } 3654 return; 3655 } 3656 3657 if (Result.getNode()) { 3658 Ops.push_back(Result); 3659 return; 3660 } 3661 3662 TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG); 3663 } 3664 3665 bool MipsTargetLowering::isLegalAddressingMode(const DataLayout &DL, 3666 const AddrMode &AM, Type *Ty, 3667 unsigned AS) const { 3668 // No global is ever allowed as a base. 3669 if (AM.BaseGV) 3670 return false; 3671 3672 switch (AM.Scale) { 3673 case 0: // "r+i" or just "i", depending on HasBaseReg. 3674 break; 3675 case 1: 3676 if (!AM.HasBaseReg) // allow "r+i". 3677 break; 3678 return false; // disallow "r+r" or "r+r+i". 3679 default: 3680 return false; 3681 } 3682 3683 return true; 3684 } 3685 3686 bool 3687 MipsTargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const { 3688 // The Mips target isn't yet aware of offsets. 3689 return false; 3690 } 3691 3692 EVT MipsTargetLowering::getOptimalMemOpType(uint64_t Size, unsigned DstAlign, 3693 unsigned SrcAlign, 3694 bool IsMemset, bool ZeroMemset, 3695 bool MemcpyStrSrc, 3696 MachineFunction &MF) const { 3697 if (Subtarget.hasMips64()) 3698 return MVT::i64; 3699 3700 return MVT::i32; 3701 } 3702 3703 bool MipsTargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const { 3704 if (VT != MVT::f32 && VT != MVT::f64) 3705 return false; 3706 if (Imm.isNegZero()) 3707 return false; 3708 return Imm.isZero(); 3709 } 3710 3711 unsigned MipsTargetLowering::getJumpTableEncoding() const { 3712 if (ABI.IsN64()) 3713 return MachineJumpTableInfo::EK_GPRel64BlockAddress; 3714 3715 return TargetLowering::getJumpTableEncoding(); 3716 } 3717 3718 bool MipsTargetLowering::useSoftFloat() const { 3719 return Subtarget.useSoftFloat(); 3720 } 3721 3722 void MipsTargetLowering::copyByValRegs( 3723 SDValue Chain, const SDLoc &DL, std::vector<SDValue> &OutChains, 3724 SelectionDAG &DAG, const ISD::ArgFlagsTy &Flags, 3725 SmallVectorImpl<SDValue> &InVals, const Argument *FuncArg, 3726 unsigned FirstReg, unsigned LastReg, const CCValAssign &VA, 3727 MipsCCState &State) const { 3728 MachineFunction &MF = DAG.getMachineFunction(); 3729 MachineFrameInfo &MFI = MF.getFrameInfo(); 3730 unsigned GPRSizeInBytes = Subtarget.getGPRSizeInBytes(); 3731 unsigned NumRegs = LastReg - FirstReg; 3732 unsigned RegAreaSize = NumRegs * GPRSizeInBytes; 3733 unsigned FrameObjSize = std::max(Flags.getByValSize(), RegAreaSize); 3734 int FrameObjOffset; 3735 ArrayRef<MCPhysReg> ByValArgRegs = ABI.GetByValArgRegs(); 3736 3737 if (RegAreaSize) 3738 FrameObjOffset = 3739 (int)ABI.GetCalleeAllocdArgSizeInBytes(State.getCallingConv()) - 3740 (int)((ByValArgRegs.size() - FirstReg) * GPRSizeInBytes); 3741 else 3742 FrameObjOffset = VA.getLocMemOffset(); 3743 3744 // Create frame object. 3745 EVT PtrTy = getPointerTy(DAG.getDataLayout()); 3746 int FI = MFI.CreateFixedObject(FrameObjSize, FrameObjOffset, true); 3747 SDValue FIN = DAG.getFrameIndex(FI, PtrTy); 3748 InVals.push_back(FIN); 3749 3750 if (!NumRegs) 3751 return; 3752 3753 // Copy arg registers. 3754 MVT RegTy = MVT::getIntegerVT(GPRSizeInBytes * 8); 3755 const TargetRegisterClass *RC = getRegClassFor(RegTy); 3756 3757 for (unsigned I = 0; I < NumRegs; ++I) { 3758 unsigned ArgReg = ByValArgRegs[FirstReg + I]; 3759 unsigned VReg = addLiveIn(MF, ArgReg, RC); 3760 unsigned Offset = I * GPRSizeInBytes; 3761 SDValue StorePtr = DAG.getNode(ISD::ADD, DL, PtrTy, FIN, 3762 DAG.getConstant(Offset, DL, PtrTy)); 3763 SDValue Store = DAG.getStore(Chain, DL, DAG.getRegister(VReg, RegTy), 3764 StorePtr, MachinePointerInfo(FuncArg, Offset)); 3765 OutChains.push_back(Store); 3766 } 3767 } 3768 3769 // Copy byVal arg to registers and stack. 3770 void MipsTargetLowering::passByValArg( 3771 SDValue Chain, const SDLoc &DL, 3772 std::deque<std::pair<unsigned, SDValue>> &RegsToPass, 3773 SmallVectorImpl<SDValue> &MemOpChains, SDValue StackPtr, 3774 MachineFrameInfo &MFI, SelectionDAG &DAG, SDValue Arg, unsigned FirstReg, 3775 unsigned LastReg, const ISD::ArgFlagsTy &Flags, bool isLittle, 3776 const CCValAssign &VA) const { 3777 unsigned ByValSizeInBytes = Flags.getByValSize(); 3778 unsigned OffsetInBytes = 0; // From beginning of struct 3779 unsigned RegSizeInBytes = Subtarget.getGPRSizeInBytes(); 3780 unsigned Alignment = std::min(Flags.getByValAlign(), RegSizeInBytes); 3781 EVT PtrTy = getPointerTy(DAG.getDataLayout()), 3782 RegTy = MVT::getIntegerVT(RegSizeInBytes * 8); 3783 unsigned NumRegs = LastReg - FirstReg; 3784 3785 if (NumRegs) { 3786 ArrayRef<MCPhysReg> ArgRegs = ABI.GetByValArgRegs(); 3787 bool LeftoverBytes = (NumRegs * RegSizeInBytes > ByValSizeInBytes); 3788 unsigned I = 0; 3789 3790 // Copy words to registers. 3791 for (; I < NumRegs - LeftoverBytes; ++I, OffsetInBytes += RegSizeInBytes) { 3792 SDValue LoadPtr = DAG.getNode(ISD::ADD, DL, PtrTy, Arg, 3793 DAG.getConstant(OffsetInBytes, DL, PtrTy)); 3794 SDValue LoadVal = DAG.getLoad(RegTy, DL, Chain, LoadPtr, 3795 MachinePointerInfo(), Alignment); 3796 MemOpChains.push_back(LoadVal.getValue(1)); 3797 unsigned ArgReg = ArgRegs[FirstReg + I]; 3798 RegsToPass.push_back(std::make_pair(ArgReg, LoadVal)); 3799 } 3800 3801 // Return if the struct has been fully copied. 3802 if (ByValSizeInBytes == OffsetInBytes) 3803 return; 3804 3805 // Copy the remainder of the byval argument with sub-word loads and shifts. 3806 if (LeftoverBytes) { 3807 SDValue Val; 3808 3809 for (unsigned LoadSizeInBytes = RegSizeInBytes / 2, TotalBytesLoaded = 0; 3810 OffsetInBytes < ByValSizeInBytes; LoadSizeInBytes /= 2) { 3811 unsigned RemainingSizeInBytes = ByValSizeInBytes - OffsetInBytes; 3812 3813 if (RemainingSizeInBytes < LoadSizeInBytes) 3814 continue; 3815 3816 // Load subword. 3817 SDValue LoadPtr = DAG.getNode(ISD::ADD, DL, PtrTy, Arg, 3818 DAG.getConstant(OffsetInBytes, DL, 3819 PtrTy)); 3820 SDValue LoadVal = DAG.getExtLoad( 3821 ISD::ZEXTLOAD, DL, RegTy, Chain, LoadPtr, MachinePointerInfo(), 3822 MVT::getIntegerVT(LoadSizeInBytes * 8), Alignment); 3823 MemOpChains.push_back(LoadVal.getValue(1)); 3824 3825 // Shift the loaded value. 3826 unsigned Shamt; 3827 3828 if (isLittle) 3829 Shamt = TotalBytesLoaded * 8; 3830 else 3831 Shamt = (RegSizeInBytes - (TotalBytesLoaded + LoadSizeInBytes)) * 8; 3832 3833 SDValue Shift = DAG.getNode(ISD::SHL, DL, RegTy, LoadVal, 3834 DAG.getConstant(Shamt, DL, MVT::i32)); 3835 3836 if (Val.getNode()) 3837 Val = DAG.getNode(ISD::OR, DL, RegTy, Val, Shift); 3838 else 3839 Val = Shift; 3840 3841 OffsetInBytes += LoadSizeInBytes; 3842 TotalBytesLoaded += LoadSizeInBytes; 3843 Alignment = std::min(Alignment, LoadSizeInBytes); 3844 } 3845 3846 unsigned ArgReg = ArgRegs[FirstReg + I]; 3847 RegsToPass.push_back(std::make_pair(ArgReg, Val)); 3848 return; 3849 } 3850 } 3851 3852 // Copy remainder of byval arg to it with memcpy. 3853 unsigned MemCpySize = ByValSizeInBytes - OffsetInBytes; 3854 SDValue Src = DAG.getNode(ISD::ADD, DL, PtrTy, Arg, 3855 DAG.getConstant(OffsetInBytes, DL, PtrTy)); 3856 SDValue Dst = DAG.getNode(ISD::ADD, DL, PtrTy, StackPtr, 3857 DAG.getIntPtrConstant(VA.getLocMemOffset(), DL)); 3858 Chain = DAG.getMemcpy(Chain, DL, Dst, Src, 3859 DAG.getConstant(MemCpySize, DL, PtrTy), 3860 Alignment, /*isVolatile=*/false, /*AlwaysInline=*/false, 3861 /*isTailCall=*/false, 3862 MachinePointerInfo(), MachinePointerInfo()); 3863 MemOpChains.push_back(Chain); 3864 } 3865 3866 void MipsTargetLowering::writeVarArgRegs(std::vector<SDValue> &OutChains, 3867 SDValue Chain, const SDLoc &DL, 3868 SelectionDAG &DAG, 3869 CCState &State) const { 3870 ArrayRef<MCPhysReg> ArgRegs = ABI.GetVarArgRegs(); 3871 unsigned Idx = State.getFirstUnallocated(ArgRegs); 3872 unsigned RegSizeInBytes = Subtarget.getGPRSizeInBytes(); 3873 MVT RegTy = MVT::getIntegerVT(RegSizeInBytes * 8); 3874 const TargetRegisterClass *RC = getRegClassFor(RegTy); 3875 MachineFunction &MF = DAG.getMachineFunction(); 3876 MachineFrameInfo &MFI = MF.getFrameInfo(); 3877 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>(); 3878 3879 // Offset of the first variable argument from stack pointer. 3880 int VaArgOffset; 3881 3882 if (ArgRegs.size() == Idx) 3883 VaArgOffset = alignTo(State.getNextStackOffset(), RegSizeInBytes); 3884 else { 3885 VaArgOffset = 3886 (int)ABI.GetCalleeAllocdArgSizeInBytes(State.getCallingConv()) - 3887 (int)(RegSizeInBytes * (ArgRegs.size() - Idx)); 3888 } 3889 3890 // Record the frame index of the first variable argument 3891 // which is a value necessary to VASTART. 3892 int FI = MFI.CreateFixedObject(RegSizeInBytes, VaArgOffset, true); 3893 MipsFI->setVarArgsFrameIndex(FI); 3894 3895 // Copy the integer registers that have not been used for argument passing 3896 // to the argument register save area. For O32, the save area is allocated 3897 // in the caller's stack frame, while for N32/64, it is allocated in the 3898 // callee's stack frame. 3899 for (unsigned I = Idx; I < ArgRegs.size(); 3900 ++I, VaArgOffset += RegSizeInBytes) { 3901 unsigned Reg = addLiveIn(MF, ArgRegs[I], RC); 3902 SDValue ArgValue = DAG.getCopyFromReg(Chain, DL, Reg, RegTy); 3903 FI = MFI.CreateFixedObject(RegSizeInBytes, VaArgOffset, true); 3904 SDValue PtrOff = DAG.getFrameIndex(FI, getPointerTy(DAG.getDataLayout())); 3905 SDValue Store = 3906 DAG.getStore(Chain, DL, ArgValue, PtrOff, MachinePointerInfo()); 3907 cast<StoreSDNode>(Store.getNode())->getMemOperand()->setValue( 3908 (Value *)nullptr); 3909 OutChains.push_back(Store); 3910 } 3911 } 3912 3913 void MipsTargetLowering::HandleByVal(CCState *State, unsigned &Size, 3914 unsigned Align) const { 3915 const TargetFrameLowering *TFL = Subtarget.getFrameLowering(); 3916 3917 assert(Size && "Byval argument's size shouldn't be 0."); 3918 3919 Align = std::min(Align, TFL->getStackAlignment()); 3920 3921 unsigned FirstReg = 0; 3922 unsigned NumRegs = 0; 3923 3924 if (State->getCallingConv() != CallingConv::Fast) { 3925 unsigned RegSizeInBytes = Subtarget.getGPRSizeInBytes(); 3926 ArrayRef<MCPhysReg> IntArgRegs = ABI.GetByValArgRegs(); 3927 // FIXME: The O32 case actually describes no shadow registers. 3928 const MCPhysReg *ShadowRegs = 3929 ABI.IsO32() ? IntArgRegs.data() : Mips64DPRegs; 3930 3931 // We used to check the size as well but we can't do that anymore since 3932 // CCState::HandleByVal() rounds up the size after calling this function. 3933 assert(!(Align % RegSizeInBytes) && 3934 "Byval argument's alignment should be a multiple of" 3935 "RegSizeInBytes."); 3936 3937 FirstReg = State->getFirstUnallocated(IntArgRegs); 3938 3939 // If Align > RegSizeInBytes, the first arg register must be even. 3940 // FIXME: This condition happens to do the right thing but it's not the 3941 // right way to test it. We want to check that the stack frame offset 3942 // of the register is aligned. 3943 if ((Align > RegSizeInBytes) && (FirstReg % 2)) { 3944 State->AllocateReg(IntArgRegs[FirstReg], ShadowRegs[FirstReg]); 3945 ++FirstReg; 3946 } 3947 3948 // Mark the registers allocated. 3949 Size = alignTo(Size, RegSizeInBytes); 3950 for (unsigned I = FirstReg; Size > 0 && (I < IntArgRegs.size()); 3951 Size -= RegSizeInBytes, ++I, ++NumRegs) 3952 State->AllocateReg(IntArgRegs[I], ShadowRegs[I]); 3953 } 3954 3955 State->addInRegsParamInfo(FirstReg, FirstReg + NumRegs); 3956 } 3957 3958 MachineBasicBlock *MipsTargetLowering::emitPseudoSELECT(MachineInstr &MI, 3959 MachineBasicBlock *BB, 3960 bool isFPCmp, 3961 unsigned Opc) const { 3962 assert(!(Subtarget.hasMips4() || Subtarget.hasMips32()) && 3963 "Subtarget already supports SELECT nodes with the use of" 3964 "conditional-move instructions."); 3965 3966 const TargetInstrInfo *TII = 3967 Subtarget.getInstrInfo(); 3968 DebugLoc DL = MI.getDebugLoc(); 3969 3970 // To "insert" a SELECT instruction, we actually have to insert the 3971 // diamond control-flow pattern. The incoming instruction knows the 3972 // destination vreg to set, the condition code register to branch on, the 3973 // true/false values to select between, and a branch opcode to use. 3974 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 3975 MachineFunction::iterator It = ++BB->getIterator(); 3976 3977 // thisMBB: 3978 // ... 3979 // TrueVal = ... 3980 // setcc r1, r2, r3 3981 // bNE r1, r0, copy1MBB 3982 // fallthrough --> copy0MBB 3983 MachineBasicBlock *thisMBB = BB; 3984 MachineFunction *F = BB->getParent(); 3985 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB); 3986 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB); 3987 F->insert(It, copy0MBB); 3988 F->insert(It, sinkMBB); 3989 3990 // Transfer the remainder of BB and its successor edges to sinkMBB. 3991 sinkMBB->splice(sinkMBB->begin(), BB, 3992 std::next(MachineBasicBlock::iterator(MI)), BB->end()); 3993 sinkMBB->transferSuccessorsAndUpdatePHIs(BB); 3994 3995 // Next, add the true and fallthrough blocks as its successors. 3996 BB->addSuccessor(copy0MBB); 3997 BB->addSuccessor(sinkMBB); 3998 3999 if (isFPCmp) { 4000 // bc1[tf] cc, sinkMBB 4001 BuildMI(BB, DL, TII->get(Opc)) 4002 .addReg(MI.getOperand(1).getReg()) 4003 .addMBB(sinkMBB); 4004 } else { 4005 // bne rs, $0, sinkMBB 4006 BuildMI(BB, DL, TII->get(Opc)) 4007 .addReg(MI.getOperand(1).getReg()) 4008 .addReg(Mips::ZERO) 4009 .addMBB(sinkMBB); 4010 } 4011 4012 // copy0MBB: 4013 // %FalseValue = ... 4014 // # fallthrough to sinkMBB 4015 BB = copy0MBB; 4016 4017 // Update machine-CFG edges 4018 BB->addSuccessor(sinkMBB); 4019 4020 // sinkMBB: 4021 // %Result = phi [ %TrueValue, thisMBB ], [ %FalseValue, copy0MBB ] 4022 // ... 4023 BB = sinkMBB; 4024 4025 BuildMI(*BB, BB->begin(), DL, TII->get(Mips::PHI), MI.getOperand(0).getReg()) 4026 .addReg(MI.getOperand(2).getReg()) 4027 .addMBB(thisMBB) 4028 .addReg(MI.getOperand(3).getReg()) 4029 .addMBB(copy0MBB); 4030 4031 MI.eraseFromParent(); // The pseudo instruction is gone now. 4032 4033 return BB; 4034 } 4035 4036 // FIXME? Maybe this could be a TableGen attribute on some registers and 4037 // this table could be generated automatically from RegInfo. 4038 unsigned MipsTargetLowering::getRegisterByName(const char* RegName, EVT VT, 4039 SelectionDAG &DAG) const { 4040 // Named registers is expected to be fairly rare. For now, just support $28 4041 // since the linux kernel uses it. 4042 if (Subtarget.isGP64bit()) { 4043 unsigned Reg = StringSwitch<unsigned>(RegName) 4044 .Case("$28", Mips::GP_64) 4045 .Default(0); 4046 if (Reg) 4047 return Reg; 4048 } else { 4049 unsigned Reg = StringSwitch<unsigned>(RegName) 4050 .Case("$28", Mips::GP) 4051 .Default(0); 4052 if (Reg) 4053 return Reg; 4054 } 4055 report_fatal_error("Invalid register name global variable"); 4056 } 4057