1 //===-- MipsISelLowering.cpp - Mips DAG Lowering Implementation -----------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file defines the interfaces that Mips uses to lower LLVM code into a 11 // selection DAG. 12 // 13 //===----------------------------------------------------------------------===// 14 #include "MipsISelLowering.h" 15 #include "InstPrinter/MipsInstPrinter.h" 16 #include "MCTargetDesc/MipsBaseInfo.h" 17 #include "MipsCCState.h" 18 #include "MipsMachineFunction.h" 19 #include "MipsSubtarget.h" 20 #include "MipsTargetMachine.h" 21 #include "MipsTargetObjectFile.h" 22 #include "llvm/ADT/Statistic.h" 23 #include "llvm/ADT/StringSwitch.h" 24 #include "llvm/CodeGen/CallingConvLower.h" 25 #include "llvm/CodeGen/MachineFrameInfo.h" 26 #include "llvm/CodeGen/MachineFunction.h" 27 #include "llvm/CodeGen/MachineInstrBuilder.h" 28 #include "llvm/CodeGen/MachineJumpTableInfo.h" 29 #include "llvm/CodeGen/MachineRegisterInfo.h" 30 #include "llvm/CodeGen/FunctionLoweringInfo.h" 31 #include "llvm/CodeGen/SelectionDAGISel.h" 32 #include "llvm/CodeGen/ValueTypes.h" 33 #include "llvm/IR/CallingConv.h" 34 #include "llvm/IR/DerivedTypes.h" 35 #include "llvm/IR/GlobalVariable.h" 36 #include "llvm/Support/CommandLine.h" 37 #include "llvm/Support/Debug.h" 38 #include "llvm/Support/ErrorHandling.h" 39 #include "llvm/Support/raw_ostream.h" 40 #include <cctype> 41 42 using namespace llvm; 43 44 #define DEBUG_TYPE "mips-lower" 45 46 STATISTIC(NumTailCalls, "Number of tail calls"); 47 48 static cl::opt<bool> 49 LargeGOT("mxgot", cl::Hidden, 50 cl::desc("MIPS: Enable GOT larger than 64k."), cl::init(false)); 51 52 static cl::opt<bool> 53 NoZeroDivCheck("mno-check-zero-division", cl::Hidden, 54 cl::desc("MIPS: Don't trap on integer division by zero."), 55 cl::init(false)); 56 57 static const MCPhysReg Mips64DPRegs[8] = { 58 Mips::D12_64, Mips::D13_64, Mips::D14_64, Mips::D15_64, 59 Mips::D16_64, Mips::D17_64, Mips::D18_64, Mips::D19_64 60 }; 61 62 // If I is a shifted mask, set the size (Size) and the first bit of the 63 // mask (Pos), and return true. 64 // For example, if I is 0x003ff800, (Pos, Size) = (11, 11). 65 static bool isShiftedMask(uint64_t I, uint64_t &Pos, uint64_t &Size) { 66 if (!isShiftedMask_64(I)) 67 return false; 68 69 Size = countPopulation(I); 70 Pos = countTrailingZeros(I); 71 return true; 72 } 73 74 SDValue MipsTargetLowering::getGlobalReg(SelectionDAG &DAG, EVT Ty) const { 75 MipsFunctionInfo *FI = DAG.getMachineFunction().getInfo<MipsFunctionInfo>(); 76 return DAG.getRegister(FI->getGlobalBaseReg(), Ty); 77 } 78 79 SDValue MipsTargetLowering::getTargetNode(GlobalAddressSDNode *N, EVT Ty, 80 SelectionDAG &DAG, 81 unsigned Flag) const { 82 return DAG.getTargetGlobalAddress(N->getGlobal(), SDLoc(N), Ty, 0, Flag); 83 } 84 85 SDValue MipsTargetLowering::getTargetNode(ExternalSymbolSDNode *N, EVT Ty, 86 SelectionDAG &DAG, 87 unsigned Flag) const { 88 return DAG.getTargetExternalSymbol(N->getSymbol(), Ty, Flag); 89 } 90 91 SDValue MipsTargetLowering::getTargetNode(BlockAddressSDNode *N, EVT Ty, 92 SelectionDAG &DAG, 93 unsigned Flag) const { 94 return DAG.getTargetBlockAddress(N->getBlockAddress(), Ty, 0, Flag); 95 } 96 97 SDValue MipsTargetLowering::getTargetNode(JumpTableSDNode *N, EVT Ty, 98 SelectionDAG &DAG, 99 unsigned Flag) const { 100 return DAG.getTargetJumpTable(N->getIndex(), Ty, Flag); 101 } 102 103 SDValue MipsTargetLowering::getTargetNode(ConstantPoolSDNode *N, EVT Ty, 104 SelectionDAG &DAG, 105 unsigned Flag) const { 106 return DAG.getTargetConstantPool(N->getConstVal(), Ty, N->getAlignment(), 107 N->getOffset(), Flag); 108 } 109 110 const char *MipsTargetLowering::getTargetNodeName(unsigned Opcode) const { 111 switch ((MipsISD::NodeType)Opcode) { 112 case MipsISD::FIRST_NUMBER: break; 113 case MipsISD::JmpLink: return "MipsISD::JmpLink"; 114 case MipsISD::TailCall: return "MipsISD::TailCall"; 115 case MipsISD::Hi: return "MipsISD::Hi"; 116 case MipsISD::Lo: return "MipsISD::Lo"; 117 case MipsISD::GPRel: return "MipsISD::GPRel"; 118 case MipsISD::ThreadPointer: return "MipsISD::ThreadPointer"; 119 case MipsISD::Ret: return "MipsISD::Ret"; 120 case MipsISD::ERet: return "MipsISD::ERet"; 121 case MipsISD::EH_RETURN: return "MipsISD::EH_RETURN"; 122 case MipsISD::FPBrcond: return "MipsISD::FPBrcond"; 123 case MipsISD::FPCmp: return "MipsISD::FPCmp"; 124 case MipsISD::CMovFP_T: return "MipsISD::CMovFP_T"; 125 case MipsISD::CMovFP_F: return "MipsISD::CMovFP_F"; 126 case MipsISD::TruncIntFP: return "MipsISD::TruncIntFP"; 127 case MipsISD::MFHI: return "MipsISD::MFHI"; 128 case MipsISD::MFLO: return "MipsISD::MFLO"; 129 case MipsISD::MTLOHI: return "MipsISD::MTLOHI"; 130 case MipsISD::Mult: return "MipsISD::Mult"; 131 case MipsISD::Multu: return "MipsISD::Multu"; 132 case MipsISD::MAdd: return "MipsISD::MAdd"; 133 case MipsISD::MAddu: return "MipsISD::MAddu"; 134 case MipsISD::MSub: return "MipsISD::MSub"; 135 case MipsISD::MSubu: return "MipsISD::MSubu"; 136 case MipsISD::DivRem: return "MipsISD::DivRem"; 137 case MipsISD::DivRemU: return "MipsISD::DivRemU"; 138 case MipsISD::DivRem16: return "MipsISD::DivRem16"; 139 case MipsISD::DivRemU16: return "MipsISD::DivRemU16"; 140 case MipsISD::BuildPairF64: return "MipsISD::BuildPairF64"; 141 case MipsISD::ExtractElementF64: return "MipsISD::ExtractElementF64"; 142 case MipsISD::Wrapper: return "MipsISD::Wrapper"; 143 case MipsISD::DynAlloc: return "MipsISD::DynAlloc"; 144 case MipsISD::Sync: return "MipsISD::Sync"; 145 case MipsISD::Ext: return "MipsISD::Ext"; 146 case MipsISD::Ins: return "MipsISD::Ins"; 147 case MipsISD::LWL: return "MipsISD::LWL"; 148 case MipsISD::LWR: return "MipsISD::LWR"; 149 case MipsISD::SWL: return "MipsISD::SWL"; 150 case MipsISD::SWR: return "MipsISD::SWR"; 151 case MipsISD::LDL: return "MipsISD::LDL"; 152 case MipsISD::LDR: return "MipsISD::LDR"; 153 case MipsISD::SDL: return "MipsISD::SDL"; 154 case MipsISD::SDR: return "MipsISD::SDR"; 155 case MipsISD::EXTP: return "MipsISD::EXTP"; 156 case MipsISD::EXTPDP: return "MipsISD::EXTPDP"; 157 case MipsISD::EXTR_S_H: return "MipsISD::EXTR_S_H"; 158 case MipsISD::EXTR_W: return "MipsISD::EXTR_W"; 159 case MipsISD::EXTR_R_W: return "MipsISD::EXTR_R_W"; 160 case MipsISD::EXTR_RS_W: return "MipsISD::EXTR_RS_W"; 161 case MipsISD::SHILO: return "MipsISD::SHILO"; 162 case MipsISD::MTHLIP: return "MipsISD::MTHLIP"; 163 case MipsISD::MULSAQ_S_W_PH: return "MipsISD::MULSAQ_S_W_PH"; 164 case MipsISD::MAQ_S_W_PHL: return "MipsISD::MAQ_S_W_PHL"; 165 case MipsISD::MAQ_S_W_PHR: return "MipsISD::MAQ_S_W_PHR"; 166 case MipsISD::MAQ_SA_W_PHL: return "MipsISD::MAQ_SA_W_PHL"; 167 case MipsISD::MAQ_SA_W_PHR: return "MipsISD::MAQ_SA_W_PHR"; 168 case MipsISD::DPAU_H_QBL: return "MipsISD::DPAU_H_QBL"; 169 case MipsISD::DPAU_H_QBR: return "MipsISD::DPAU_H_QBR"; 170 case MipsISD::DPSU_H_QBL: return "MipsISD::DPSU_H_QBL"; 171 case MipsISD::DPSU_H_QBR: return "MipsISD::DPSU_H_QBR"; 172 case MipsISD::DPAQ_S_W_PH: return "MipsISD::DPAQ_S_W_PH"; 173 case MipsISD::DPSQ_S_W_PH: return "MipsISD::DPSQ_S_W_PH"; 174 case MipsISD::DPAQ_SA_L_W: return "MipsISD::DPAQ_SA_L_W"; 175 case MipsISD::DPSQ_SA_L_W: return "MipsISD::DPSQ_SA_L_W"; 176 case MipsISD::DPA_W_PH: return "MipsISD::DPA_W_PH"; 177 case MipsISD::DPS_W_PH: return "MipsISD::DPS_W_PH"; 178 case MipsISD::DPAQX_S_W_PH: return "MipsISD::DPAQX_S_W_PH"; 179 case MipsISD::DPAQX_SA_W_PH: return "MipsISD::DPAQX_SA_W_PH"; 180 case MipsISD::DPAX_W_PH: return "MipsISD::DPAX_W_PH"; 181 case MipsISD::DPSX_W_PH: return "MipsISD::DPSX_W_PH"; 182 case MipsISD::DPSQX_S_W_PH: return "MipsISD::DPSQX_S_W_PH"; 183 case MipsISD::DPSQX_SA_W_PH: return "MipsISD::DPSQX_SA_W_PH"; 184 case MipsISD::MULSA_W_PH: return "MipsISD::MULSA_W_PH"; 185 case MipsISD::MULT: return "MipsISD::MULT"; 186 case MipsISD::MULTU: return "MipsISD::MULTU"; 187 case MipsISD::MADD_DSP: return "MipsISD::MADD_DSP"; 188 case MipsISD::MADDU_DSP: return "MipsISD::MADDU_DSP"; 189 case MipsISD::MSUB_DSP: return "MipsISD::MSUB_DSP"; 190 case MipsISD::MSUBU_DSP: return "MipsISD::MSUBU_DSP"; 191 case MipsISD::SHLL_DSP: return "MipsISD::SHLL_DSP"; 192 case MipsISD::SHRA_DSP: return "MipsISD::SHRA_DSP"; 193 case MipsISD::SHRL_DSP: return "MipsISD::SHRL_DSP"; 194 case MipsISD::SETCC_DSP: return "MipsISD::SETCC_DSP"; 195 case MipsISD::SELECT_CC_DSP: return "MipsISD::SELECT_CC_DSP"; 196 case MipsISD::VALL_ZERO: return "MipsISD::VALL_ZERO"; 197 case MipsISD::VANY_ZERO: return "MipsISD::VANY_ZERO"; 198 case MipsISD::VALL_NONZERO: return "MipsISD::VALL_NONZERO"; 199 case MipsISD::VANY_NONZERO: return "MipsISD::VANY_NONZERO"; 200 case MipsISD::VCEQ: return "MipsISD::VCEQ"; 201 case MipsISD::VCLE_S: return "MipsISD::VCLE_S"; 202 case MipsISD::VCLE_U: return "MipsISD::VCLE_U"; 203 case MipsISD::VCLT_S: return "MipsISD::VCLT_S"; 204 case MipsISD::VCLT_U: return "MipsISD::VCLT_U"; 205 case MipsISD::VSMAX: return "MipsISD::VSMAX"; 206 case MipsISD::VSMIN: return "MipsISD::VSMIN"; 207 case MipsISD::VUMAX: return "MipsISD::VUMAX"; 208 case MipsISD::VUMIN: return "MipsISD::VUMIN"; 209 case MipsISD::VEXTRACT_SEXT_ELT: return "MipsISD::VEXTRACT_SEXT_ELT"; 210 case MipsISD::VEXTRACT_ZEXT_ELT: return "MipsISD::VEXTRACT_ZEXT_ELT"; 211 case MipsISD::VNOR: return "MipsISD::VNOR"; 212 case MipsISD::VSHF: return "MipsISD::VSHF"; 213 case MipsISD::SHF: return "MipsISD::SHF"; 214 case MipsISD::ILVEV: return "MipsISD::ILVEV"; 215 case MipsISD::ILVOD: return "MipsISD::ILVOD"; 216 case MipsISD::ILVL: return "MipsISD::ILVL"; 217 case MipsISD::ILVR: return "MipsISD::ILVR"; 218 case MipsISD::PCKEV: return "MipsISD::PCKEV"; 219 case MipsISD::PCKOD: return "MipsISD::PCKOD"; 220 case MipsISD::INSVE: return "MipsISD::INSVE"; 221 } 222 return nullptr; 223 } 224 225 MipsTargetLowering::MipsTargetLowering(const MipsTargetMachine &TM, 226 const MipsSubtarget &STI) 227 : TargetLowering(TM), Subtarget(STI), ABI(TM.getABI()) { 228 // Mips does not have i1 type, so use i32 for 229 // setcc operations results (slt, sgt, ...). 230 setBooleanContents(ZeroOrOneBooleanContent); 231 setBooleanVectorContents(ZeroOrNegativeOneBooleanContent); 232 // The cmp.cond.fmt instruction in MIPS32r6/MIPS64r6 uses 0 and -1 like MSA 233 // does. Integer booleans still use 0 and 1. 234 if (Subtarget.hasMips32r6()) 235 setBooleanContents(ZeroOrOneBooleanContent, 236 ZeroOrNegativeOneBooleanContent); 237 238 // Load extented operations for i1 types must be promoted 239 for (MVT VT : MVT::integer_valuetypes()) { 240 setLoadExtAction(ISD::EXTLOAD, VT, MVT::i1, Promote); 241 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i1, Promote); 242 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i1, Promote); 243 } 244 245 // MIPS doesn't have extending float->double load/store. Set LoadExtAction 246 // for f32, f16 247 for (MVT VT : MVT::fp_valuetypes()) { 248 setLoadExtAction(ISD::EXTLOAD, VT, MVT::f32, Expand); 249 setLoadExtAction(ISD::EXTLOAD, VT, MVT::f16, Expand); 250 } 251 252 // Set LoadExtAction for f16 vectors to Expand 253 for (MVT VT : MVT::fp_vector_valuetypes()) { 254 MVT F16VT = MVT::getVectorVT(MVT::f16, VT.getVectorNumElements()); 255 if (F16VT.isValid()) 256 setLoadExtAction(ISD::EXTLOAD, VT, F16VT, Expand); 257 } 258 259 setTruncStoreAction(MVT::f32, MVT::f16, Expand); 260 setTruncStoreAction(MVT::f64, MVT::f16, Expand); 261 262 setTruncStoreAction(MVT::f64, MVT::f32, Expand); 263 264 // Used by legalize types to correctly generate the setcc result. 265 // Without this, every float setcc comes with a AND/OR with the result, 266 // we don't want this, since the fpcmp result goes to a flag register, 267 // which is used implicitly by brcond and select operations. 268 AddPromotedToType(ISD::SETCC, MVT::i1, MVT::i32); 269 270 // Mips Custom Operations 271 setOperationAction(ISD::BR_JT, MVT::Other, Custom); 272 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom); 273 setOperationAction(ISD::BlockAddress, MVT::i32, Custom); 274 setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom); 275 setOperationAction(ISD::JumpTable, MVT::i32, Custom); 276 setOperationAction(ISD::ConstantPool, MVT::i32, Custom); 277 setOperationAction(ISD::SELECT, MVT::f32, Custom); 278 setOperationAction(ISD::SELECT, MVT::f64, Custom); 279 setOperationAction(ISD::SELECT, MVT::i32, Custom); 280 setOperationAction(ISD::SETCC, MVT::f32, Custom); 281 setOperationAction(ISD::SETCC, MVT::f64, Custom); 282 setOperationAction(ISD::BRCOND, MVT::Other, Custom); 283 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom); 284 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom); 285 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom); 286 287 if (Subtarget.isGP64bit()) { 288 setOperationAction(ISD::GlobalAddress, MVT::i64, Custom); 289 setOperationAction(ISD::BlockAddress, MVT::i64, Custom); 290 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom); 291 setOperationAction(ISD::JumpTable, MVT::i64, Custom); 292 setOperationAction(ISD::ConstantPool, MVT::i64, Custom); 293 setOperationAction(ISD::SELECT, MVT::i64, Custom); 294 setOperationAction(ISD::LOAD, MVT::i64, Custom); 295 setOperationAction(ISD::STORE, MVT::i64, Custom); 296 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom); 297 setOperationAction(ISD::SHL_PARTS, MVT::i64, Custom); 298 setOperationAction(ISD::SRA_PARTS, MVT::i64, Custom); 299 setOperationAction(ISD::SRL_PARTS, MVT::i64, Custom); 300 } 301 302 if (!Subtarget.isGP64bit()) { 303 setOperationAction(ISD::SHL_PARTS, MVT::i32, Custom); 304 setOperationAction(ISD::SRA_PARTS, MVT::i32, Custom); 305 setOperationAction(ISD::SRL_PARTS, MVT::i32, Custom); 306 } 307 308 setOperationAction(ISD::EH_DWARF_CFA, MVT::i32, Custom); 309 if (Subtarget.isGP64bit()) 310 setOperationAction(ISD::EH_DWARF_CFA, MVT::i64, Custom); 311 312 setOperationAction(ISD::SDIV, MVT::i32, Expand); 313 setOperationAction(ISD::SREM, MVT::i32, Expand); 314 setOperationAction(ISD::UDIV, MVT::i32, Expand); 315 setOperationAction(ISD::UREM, MVT::i32, Expand); 316 setOperationAction(ISD::SDIV, MVT::i64, Expand); 317 setOperationAction(ISD::SREM, MVT::i64, Expand); 318 setOperationAction(ISD::UDIV, MVT::i64, Expand); 319 setOperationAction(ISD::UREM, MVT::i64, Expand); 320 321 // Operations not directly supported by Mips. 322 setOperationAction(ISD::BR_CC, MVT::f32, Expand); 323 setOperationAction(ISD::BR_CC, MVT::f64, Expand); 324 setOperationAction(ISD::BR_CC, MVT::i32, Expand); 325 setOperationAction(ISD::BR_CC, MVT::i64, Expand); 326 setOperationAction(ISD::SELECT_CC, MVT::i32, Expand); 327 setOperationAction(ISD::SELECT_CC, MVT::i64, Expand); 328 setOperationAction(ISD::SELECT_CC, MVT::f32, Expand); 329 setOperationAction(ISD::SELECT_CC, MVT::f64, Expand); 330 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand); 331 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Expand); 332 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand); 333 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Expand); 334 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand); 335 if (Subtarget.hasCnMips()) { 336 setOperationAction(ISD::CTPOP, MVT::i32, Legal); 337 setOperationAction(ISD::CTPOP, MVT::i64, Legal); 338 } else { 339 setOperationAction(ISD::CTPOP, MVT::i32, Expand); 340 setOperationAction(ISD::CTPOP, MVT::i64, Expand); 341 } 342 setOperationAction(ISD::CTTZ, MVT::i32, Expand); 343 setOperationAction(ISD::CTTZ, MVT::i64, Expand); 344 setOperationAction(ISD::ROTL, MVT::i32, Expand); 345 setOperationAction(ISD::ROTL, MVT::i64, Expand); 346 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Expand); 347 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64, Expand); 348 349 if (!Subtarget.hasMips32r2()) 350 setOperationAction(ISD::ROTR, MVT::i32, Expand); 351 352 if (!Subtarget.hasMips64r2()) 353 setOperationAction(ISD::ROTR, MVT::i64, Expand); 354 355 setOperationAction(ISD::FSIN, MVT::f32, Expand); 356 setOperationAction(ISD::FSIN, MVT::f64, Expand); 357 setOperationAction(ISD::FCOS, MVT::f32, Expand); 358 setOperationAction(ISD::FCOS, MVT::f64, Expand); 359 setOperationAction(ISD::FSINCOS, MVT::f32, Expand); 360 setOperationAction(ISD::FSINCOS, MVT::f64, Expand); 361 setOperationAction(ISD::FPOWI, MVT::f32, Expand); 362 setOperationAction(ISD::FPOW, MVT::f32, Expand); 363 setOperationAction(ISD::FPOW, MVT::f64, Expand); 364 setOperationAction(ISD::FLOG, MVT::f32, Expand); 365 setOperationAction(ISD::FLOG2, MVT::f32, Expand); 366 setOperationAction(ISD::FLOG10, MVT::f32, Expand); 367 setOperationAction(ISD::FEXP, MVT::f32, Expand); 368 setOperationAction(ISD::FMA, MVT::f32, Expand); 369 setOperationAction(ISD::FMA, MVT::f64, Expand); 370 setOperationAction(ISD::FREM, MVT::f32, Expand); 371 setOperationAction(ISD::FREM, MVT::f64, Expand); 372 373 // Lower f16 conversion operations into library calls 374 setOperationAction(ISD::FP16_TO_FP, MVT::f32, Expand); 375 setOperationAction(ISD::FP_TO_FP16, MVT::f32, Expand); 376 setOperationAction(ISD::FP16_TO_FP, MVT::f64, Expand); 377 setOperationAction(ISD::FP_TO_FP16, MVT::f64, Expand); 378 379 setOperationAction(ISD::EH_RETURN, MVT::Other, Custom); 380 381 setOperationAction(ISD::VASTART, MVT::Other, Custom); 382 setOperationAction(ISD::VAARG, MVT::Other, Custom); 383 setOperationAction(ISD::VACOPY, MVT::Other, Expand); 384 setOperationAction(ISD::VAEND, MVT::Other, Expand); 385 386 // Use the default for now 387 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand); 388 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand); 389 390 if (!Subtarget.isGP64bit()) { 391 setOperationAction(ISD::ATOMIC_LOAD, MVT::i64, Expand); 392 setOperationAction(ISD::ATOMIC_STORE, MVT::i64, Expand); 393 } 394 395 396 if (!Subtarget.hasMips32r2()) { 397 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8, Expand); 398 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand); 399 } 400 401 // MIPS16 lacks MIPS32's clz and clo instructions. 402 if (!Subtarget.hasMips32() || Subtarget.inMips16Mode()) 403 setOperationAction(ISD::CTLZ, MVT::i32, Expand); 404 if (!Subtarget.hasMips64()) 405 setOperationAction(ISD::CTLZ, MVT::i64, Expand); 406 407 if (!Subtarget.hasMips32r2()) 408 setOperationAction(ISD::BSWAP, MVT::i32, Expand); 409 if (!Subtarget.hasMips64r2()) 410 setOperationAction(ISD::BSWAP, MVT::i64, Expand); 411 412 if (Subtarget.isGP64bit()) { 413 setLoadExtAction(ISD::SEXTLOAD, MVT::i64, MVT::i32, Custom); 414 setLoadExtAction(ISD::ZEXTLOAD, MVT::i64, MVT::i32, Custom); 415 setLoadExtAction(ISD::EXTLOAD, MVT::i64, MVT::i32, Custom); 416 setTruncStoreAction(MVT::i64, MVT::i32, Custom); 417 } 418 419 setOperationAction(ISD::TRAP, MVT::Other, Legal); 420 421 setTargetDAGCombine(ISD::SDIVREM); 422 setTargetDAGCombine(ISD::UDIVREM); 423 setTargetDAGCombine(ISD::SELECT); 424 setTargetDAGCombine(ISD::AND); 425 setTargetDAGCombine(ISD::OR); 426 setTargetDAGCombine(ISD::ADD); 427 setTargetDAGCombine(ISD::AssertZext); 428 429 if (ABI.IsO32()) { 430 // These libcalls are not available in 32-bit. 431 setLibcallName(RTLIB::SHL_I128, nullptr); 432 setLibcallName(RTLIB::SRL_I128, nullptr); 433 setLibcallName(RTLIB::SRA_I128, nullptr); 434 } 435 436 setMinFunctionAlignment(Subtarget.isGP64bit() ? 3 : 2); 437 438 // The arguments on the stack are defined in terms of 4-byte slots on O32 439 // and 8-byte slots on N32/N64. 440 setMinStackArgumentAlignment((ABI.IsN32() || ABI.IsN64()) ? 8 : 4); 441 442 setStackPointerRegisterToSaveRestore(ABI.IsN64() ? Mips::SP_64 : Mips::SP); 443 444 MaxStoresPerMemcpy = 16; 445 446 isMicroMips = Subtarget.inMicroMipsMode(); 447 } 448 449 const MipsTargetLowering *MipsTargetLowering::create(const MipsTargetMachine &TM, 450 const MipsSubtarget &STI) { 451 if (STI.inMips16Mode()) 452 return llvm::createMips16TargetLowering(TM, STI); 453 454 return llvm::createMipsSETargetLowering(TM, STI); 455 } 456 457 // Create a fast isel object. 458 FastISel * 459 MipsTargetLowering::createFastISel(FunctionLoweringInfo &funcInfo, 460 const TargetLibraryInfo *libInfo) const { 461 if (!funcInfo.MF->getTarget().Options.EnableFastISel) 462 return TargetLowering::createFastISel(funcInfo, libInfo); 463 return Mips::createFastISel(funcInfo, libInfo); 464 } 465 466 EVT MipsTargetLowering::getSetCCResultType(const DataLayout &, LLVMContext &, 467 EVT VT) const { 468 if (!VT.isVector()) 469 return MVT::i32; 470 return VT.changeVectorElementTypeToInteger(); 471 } 472 473 static SDValue performDivRemCombine(SDNode *N, SelectionDAG &DAG, 474 TargetLowering::DAGCombinerInfo &DCI, 475 const MipsSubtarget &Subtarget) { 476 if (DCI.isBeforeLegalizeOps()) 477 return SDValue(); 478 479 EVT Ty = N->getValueType(0); 480 unsigned LO = (Ty == MVT::i32) ? Mips::LO0 : Mips::LO0_64; 481 unsigned HI = (Ty == MVT::i32) ? Mips::HI0 : Mips::HI0_64; 482 unsigned Opc = N->getOpcode() == ISD::SDIVREM ? MipsISD::DivRem16 : 483 MipsISD::DivRemU16; 484 SDLoc DL(N); 485 486 SDValue DivRem = DAG.getNode(Opc, DL, MVT::Glue, 487 N->getOperand(0), N->getOperand(1)); 488 SDValue InChain = DAG.getEntryNode(); 489 SDValue InGlue = DivRem; 490 491 // insert MFLO 492 if (N->hasAnyUseOfValue(0)) { 493 SDValue CopyFromLo = DAG.getCopyFromReg(InChain, DL, LO, Ty, 494 InGlue); 495 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), CopyFromLo); 496 InChain = CopyFromLo.getValue(1); 497 InGlue = CopyFromLo.getValue(2); 498 } 499 500 // insert MFHI 501 if (N->hasAnyUseOfValue(1)) { 502 SDValue CopyFromHi = DAG.getCopyFromReg(InChain, DL, 503 HI, Ty, InGlue); 504 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), CopyFromHi); 505 } 506 507 return SDValue(); 508 } 509 510 static Mips::CondCode condCodeToFCC(ISD::CondCode CC) { 511 switch (CC) { 512 default: llvm_unreachable("Unknown fp condition code!"); 513 case ISD::SETEQ: 514 case ISD::SETOEQ: return Mips::FCOND_OEQ; 515 case ISD::SETUNE: return Mips::FCOND_UNE; 516 case ISD::SETLT: 517 case ISD::SETOLT: return Mips::FCOND_OLT; 518 case ISD::SETGT: 519 case ISD::SETOGT: return Mips::FCOND_OGT; 520 case ISD::SETLE: 521 case ISD::SETOLE: return Mips::FCOND_OLE; 522 case ISD::SETGE: 523 case ISD::SETOGE: return Mips::FCOND_OGE; 524 case ISD::SETULT: return Mips::FCOND_ULT; 525 case ISD::SETULE: return Mips::FCOND_ULE; 526 case ISD::SETUGT: return Mips::FCOND_UGT; 527 case ISD::SETUGE: return Mips::FCOND_UGE; 528 case ISD::SETUO: return Mips::FCOND_UN; 529 case ISD::SETO: return Mips::FCOND_OR; 530 case ISD::SETNE: 531 case ISD::SETONE: return Mips::FCOND_ONE; 532 case ISD::SETUEQ: return Mips::FCOND_UEQ; 533 } 534 } 535 536 537 /// This function returns true if the floating point conditional branches and 538 /// conditional moves which use condition code CC should be inverted. 539 static bool invertFPCondCodeUser(Mips::CondCode CC) { 540 if (CC >= Mips::FCOND_F && CC <= Mips::FCOND_NGT) 541 return false; 542 543 assert((CC >= Mips::FCOND_T && CC <= Mips::FCOND_GT) && 544 "Illegal Condition Code"); 545 546 return true; 547 } 548 549 // Creates and returns an FPCmp node from a setcc node. 550 // Returns Op if setcc is not a floating point comparison. 551 static SDValue createFPCmp(SelectionDAG &DAG, const SDValue &Op) { 552 // must be a SETCC node 553 if (Op.getOpcode() != ISD::SETCC) 554 return Op; 555 556 SDValue LHS = Op.getOperand(0); 557 558 if (!LHS.getValueType().isFloatingPoint()) 559 return Op; 560 561 SDValue RHS = Op.getOperand(1); 562 SDLoc DL(Op); 563 564 // Assume the 3rd operand is a CondCodeSDNode. Add code to check the type of 565 // node if necessary. 566 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get(); 567 568 return DAG.getNode(MipsISD::FPCmp, DL, MVT::Glue, LHS, RHS, 569 DAG.getConstant(condCodeToFCC(CC), DL, MVT::i32)); 570 } 571 572 // Creates and returns a CMovFPT/F node. 573 static SDValue createCMovFP(SelectionDAG &DAG, SDValue Cond, SDValue True, 574 SDValue False, const SDLoc &DL) { 575 ConstantSDNode *CC = cast<ConstantSDNode>(Cond.getOperand(2)); 576 bool invert = invertFPCondCodeUser((Mips::CondCode)CC->getSExtValue()); 577 SDValue FCC0 = DAG.getRegister(Mips::FCC0, MVT::i32); 578 579 return DAG.getNode((invert ? MipsISD::CMovFP_F : MipsISD::CMovFP_T), DL, 580 True.getValueType(), True, FCC0, False, Cond); 581 } 582 583 static SDValue performSELECTCombine(SDNode *N, SelectionDAG &DAG, 584 TargetLowering::DAGCombinerInfo &DCI, 585 const MipsSubtarget &Subtarget) { 586 if (DCI.isBeforeLegalizeOps()) 587 return SDValue(); 588 589 SDValue SetCC = N->getOperand(0); 590 591 if ((SetCC.getOpcode() != ISD::SETCC) || 592 !SetCC.getOperand(0).getValueType().isInteger()) 593 return SDValue(); 594 595 SDValue False = N->getOperand(2); 596 EVT FalseTy = False.getValueType(); 597 598 if (!FalseTy.isInteger()) 599 return SDValue(); 600 601 ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(False); 602 603 // If the RHS (False) is 0, we swap the order of the operands 604 // of ISD::SELECT (obviously also inverting the condition) so that we can 605 // take advantage of conditional moves using the $0 register. 606 // Example: 607 // return (a != 0) ? x : 0; 608 // load $reg, x 609 // movz $reg, $0, a 610 if (!FalseC) 611 return SDValue(); 612 613 const SDLoc DL(N); 614 615 if (!FalseC->getZExtValue()) { 616 ISD::CondCode CC = cast<CondCodeSDNode>(SetCC.getOperand(2))->get(); 617 SDValue True = N->getOperand(1); 618 619 SetCC = DAG.getSetCC(DL, SetCC.getValueType(), SetCC.getOperand(0), 620 SetCC.getOperand(1), ISD::getSetCCInverse(CC, true)); 621 622 return DAG.getNode(ISD::SELECT, DL, FalseTy, SetCC, False, True); 623 } 624 625 // If both operands are integer constants there's a possibility that we 626 // can do some interesting optimizations. 627 SDValue True = N->getOperand(1); 628 ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(True); 629 630 if (!TrueC || !True.getValueType().isInteger()) 631 return SDValue(); 632 633 // We'll also ignore MVT::i64 operands as this optimizations proves 634 // to be ineffective because of the required sign extensions as the result 635 // of a SETCC operator is always MVT::i32 for non-vector types. 636 if (True.getValueType() == MVT::i64) 637 return SDValue(); 638 639 int64_t Diff = TrueC->getSExtValue() - FalseC->getSExtValue(); 640 641 // 1) (a < x) ? y : y-1 642 // slti $reg1, a, x 643 // addiu $reg2, $reg1, y-1 644 if (Diff == 1) 645 return DAG.getNode(ISD::ADD, DL, SetCC.getValueType(), SetCC, False); 646 647 // 2) (a < x) ? y-1 : y 648 // slti $reg1, a, x 649 // xor $reg1, $reg1, 1 650 // addiu $reg2, $reg1, y-1 651 if (Diff == -1) { 652 ISD::CondCode CC = cast<CondCodeSDNode>(SetCC.getOperand(2))->get(); 653 SetCC = DAG.getSetCC(DL, SetCC.getValueType(), SetCC.getOperand(0), 654 SetCC.getOperand(1), ISD::getSetCCInverse(CC, true)); 655 return DAG.getNode(ISD::ADD, DL, SetCC.getValueType(), SetCC, True); 656 } 657 658 // Couldn't optimize. 659 return SDValue(); 660 } 661 662 static SDValue performCMovFPCombine(SDNode *N, SelectionDAG &DAG, 663 TargetLowering::DAGCombinerInfo &DCI, 664 const MipsSubtarget &Subtarget) { 665 if (DCI.isBeforeLegalizeOps()) 666 return SDValue(); 667 668 SDValue ValueIfTrue = N->getOperand(0), ValueIfFalse = N->getOperand(2); 669 670 ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(ValueIfFalse); 671 if (!FalseC || FalseC->getZExtValue()) 672 return SDValue(); 673 674 // Since RHS (False) is 0, we swap the order of the True/False operands 675 // (obviously also inverting the condition) so that we can 676 // take advantage of conditional moves using the $0 register. 677 // Example: 678 // return (a != 0) ? x : 0; 679 // load $reg, x 680 // movz $reg, $0, a 681 unsigned Opc = (N->getOpcode() == MipsISD::CMovFP_T) ? MipsISD::CMovFP_F : 682 MipsISD::CMovFP_T; 683 684 SDValue FCC = N->getOperand(1), Glue = N->getOperand(3); 685 return DAG.getNode(Opc, SDLoc(N), ValueIfFalse.getValueType(), 686 ValueIfFalse, FCC, ValueIfTrue, Glue); 687 } 688 689 static SDValue performANDCombine(SDNode *N, SelectionDAG &DAG, 690 TargetLowering::DAGCombinerInfo &DCI, 691 const MipsSubtarget &Subtarget) { 692 // Pattern match EXT. 693 // $dst = and ((sra or srl) $src , pos), (2**size - 1) 694 // => ext $dst, $src, size, pos 695 if (DCI.isBeforeLegalizeOps() || !Subtarget.hasExtractInsert()) 696 return SDValue(); 697 698 SDValue ShiftRight = N->getOperand(0), Mask = N->getOperand(1); 699 unsigned ShiftRightOpc = ShiftRight.getOpcode(); 700 701 // Op's first operand must be a shift right. 702 if (ShiftRightOpc != ISD::SRA && ShiftRightOpc != ISD::SRL) 703 return SDValue(); 704 705 // The second operand of the shift must be an immediate. 706 ConstantSDNode *CN; 707 if (!(CN = dyn_cast<ConstantSDNode>(ShiftRight.getOperand(1)))) 708 return SDValue(); 709 710 uint64_t Pos = CN->getZExtValue(); 711 uint64_t SMPos, SMSize; 712 713 // Op's second operand must be a shifted mask. 714 if (!(CN = dyn_cast<ConstantSDNode>(Mask)) || 715 !isShiftedMask(CN->getZExtValue(), SMPos, SMSize)) 716 return SDValue(); 717 718 // Return if the shifted mask does not start at bit 0 or the sum of its size 719 // and Pos exceeds the word's size. 720 EVT ValTy = N->getValueType(0); 721 if (SMPos != 0 || Pos + SMSize > ValTy.getSizeInBits()) 722 return SDValue(); 723 724 SDLoc DL(N); 725 return DAG.getNode(MipsISD::Ext, DL, ValTy, 726 ShiftRight.getOperand(0), 727 DAG.getConstant(Pos, DL, MVT::i32), 728 DAG.getConstant(SMSize, DL, MVT::i32)); 729 } 730 731 static SDValue performORCombine(SDNode *N, SelectionDAG &DAG, 732 TargetLowering::DAGCombinerInfo &DCI, 733 const MipsSubtarget &Subtarget) { 734 // Pattern match INS. 735 // $dst = or (and $src1 , mask0), (and (shl $src, pos), mask1), 736 // where mask1 = (2**size - 1) << pos, mask0 = ~mask1 737 // => ins $dst, $src, size, pos, $src1 738 if (DCI.isBeforeLegalizeOps() || !Subtarget.hasExtractInsert()) 739 return SDValue(); 740 741 SDValue And0 = N->getOperand(0), And1 = N->getOperand(1); 742 uint64_t SMPos0, SMSize0, SMPos1, SMSize1; 743 ConstantSDNode *CN; 744 745 // See if Op's first operand matches (and $src1 , mask0). 746 if (And0.getOpcode() != ISD::AND) 747 return SDValue(); 748 749 if (!(CN = dyn_cast<ConstantSDNode>(And0.getOperand(1))) || 750 !isShiftedMask(~CN->getSExtValue(), SMPos0, SMSize0)) 751 return SDValue(); 752 753 // See if Op's second operand matches (and (shl $src, pos), mask1). 754 if (And1.getOpcode() != ISD::AND) 755 return SDValue(); 756 757 if (!(CN = dyn_cast<ConstantSDNode>(And1.getOperand(1))) || 758 !isShiftedMask(CN->getZExtValue(), SMPos1, SMSize1)) 759 return SDValue(); 760 761 // The shift masks must have the same position and size. 762 if (SMPos0 != SMPos1 || SMSize0 != SMSize1) 763 return SDValue(); 764 765 SDValue Shl = And1.getOperand(0); 766 if (Shl.getOpcode() != ISD::SHL) 767 return SDValue(); 768 769 if (!(CN = dyn_cast<ConstantSDNode>(Shl.getOperand(1)))) 770 return SDValue(); 771 772 unsigned Shamt = CN->getZExtValue(); 773 774 // Return if the shift amount and the first bit position of mask are not the 775 // same. 776 EVT ValTy = N->getValueType(0); 777 if ((Shamt != SMPos0) || (SMPos0 + SMSize0 > ValTy.getSizeInBits())) 778 return SDValue(); 779 780 SDLoc DL(N); 781 return DAG.getNode(MipsISD::Ins, DL, ValTy, Shl.getOperand(0), 782 DAG.getConstant(SMPos0, DL, MVT::i32), 783 DAG.getConstant(SMSize0, DL, MVT::i32), 784 And0.getOperand(0)); 785 } 786 787 static SDValue performADDCombine(SDNode *N, SelectionDAG &DAG, 788 TargetLowering::DAGCombinerInfo &DCI, 789 const MipsSubtarget &Subtarget) { 790 // (add v0, (add v1, abs_lo(tjt))) => (add (add v0, v1), abs_lo(tjt)) 791 792 if (DCI.isBeforeLegalizeOps()) 793 return SDValue(); 794 795 SDValue Add = N->getOperand(1); 796 797 if (Add.getOpcode() != ISD::ADD) 798 return SDValue(); 799 800 SDValue Lo = Add.getOperand(1); 801 802 if ((Lo.getOpcode() != MipsISD::Lo) || 803 (Lo.getOperand(0).getOpcode() != ISD::TargetJumpTable)) 804 return SDValue(); 805 806 EVT ValTy = N->getValueType(0); 807 SDLoc DL(N); 808 809 SDValue Add1 = DAG.getNode(ISD::ADD, DL, ValTy, N->getOperand(0), 810 Add.getOperand(0)); 811 return DAG.getNode(ISD::ADD, DL, ValTy, Add1, Lo); 812 } 813 814 static SDValue performAssertZextCombine(SDNode *N, SelectionDAG &DAG, 815 TargetLowering::DAGCombinerInfo &DCI, 816 const MipsSubtarget &Subtarget) { 817 SDValue N0 = N->getOperand(0); 818 EVT NarrowerVT = cast<VTSDNode>(N->getOperand(1))->getVT(); 819 820 if (N0.getOpcode() != ISD::TRUNCATE) 821 return SDValue(); 822 823 if (N0.getOperand(0).getOpcode() != ISD::AssertZext) 824 return SDValue(); 825 826 // fold (AssertZext (trunc (AssertZext x))) -> (trunc (AssertZext x)) 827 // if the type of the extension of the innermost AssertZext node is 828 // smaller from that of the outermost node, eg: 829 // (AssertZext:i32 (trunc:i32 (AssertZext:i64 X, i32)), i8) 830 // -> (trunc:i32 (AssertZext X, i8)) 831 SDValue WiderAssertZext = N0.getOperand(0); 832 EVT WiderVT = cast<VTSDNode>(WiderAssertZext->getOperand(1))->getVT(); 833 834 if (NarrowerVT.bitsLT(WiderVT)) { 835 SDValue NewAssertZext = DAG.getNode( 836 ISD::AssertZext, SDLoc(N), WiderAssertZext.getValueType(), 837 WiderAssertZext.getOperand(0), DAG.getValueType(NarrowerVT)); 838 return DAG.getNode(ISD::TRUNCATE, SDLoc(N), N->getValueType(0), 839 NewAssertZext); 840 } 841 842 return SDValue(); 843 } 844 845 SDValue MipsTargetLowering::PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) 846 const { 847 SelectionDAG &DAG = DCI.DAG; 848 unsigned Opc = N->getOpcode(); 849 850 switch (Opc) { 851 default: break; 852 case ISD::SDIVREM: 853 case ISD::UDIVREM: 854 return performDivRemCombine(N, DAG, DCI, Subtarget); 855 case ISD::SELECT: 856 return performSELECTCombine(N, DAG, DCI, Subtarget); 857 case MipsISD::CMovFP_F: 858 case MipsISD::CMovFP_T: 859 return performCMovFPCombine(N, DAG, DCI, Subtarget); 860 case ISD::AND: 861 return performANDCombine(N, DAG, DCI, Subtarget); 862 case ISD::OR: 863 return performORCombine(N, DAG, DCI, Subtarget); 864 case ISD::ADD: 865 return performADDCombine(N, DAG, DCI, Subtarget); 866 case ISD::AssertZext: 867 return performAssertZextCombine(N, DAG, DCI, Subtarget); 868 } 869 870 return SDValue(); 871 } 872 873 bool MipsTargetLowering::isCheapToSpeculateCttz() const { 874 return Subtarget.hasMips32(); 875 } 876 877 bool MipsTargetLowering::isCheapToSpeculateCtlz() const { 878 return Subtarget.hasMips32(); 879 } 880 881 void 882 MipsTargetLowering::LowerOperationWrapper(SDNode *N, 883 SmallVectorImpl<SDValue> &Results, 884 SelectionDAG &DAG) const { 885 SDValue Res = LowerOperation(SDValue(N, 0), DAG); 886 887 for (unsigned I = 0, E = Res->getNumValues(); I != E; ++I) 888 Results.push_back(Res.getValue(I)); 889 } 890 891 void 892 MipsTargetLowering::ReplaceNodeResults(SDNode *N, 893 SmallVectorImpl<SDValue> &Results, 894 SelectionDAG &DAG) const { 895 return LowerOperationWrapper(N, Results, DAG); 896 } 897 898 SDValue MipsTargetLowering:: 899 LowerOperation(SDValue Op, SelectionDAG &DAG) const 900 { 901 switch (Op.getOpcode()) 902 { 903 case ISD::BR_JT: return lowerBR_JT(Op, DAG); 904 case ISD::BRCOND: return lowerBRCOND(Op, DAG); 905 case ISD::ConstantPool: return lowerConstantPool(Op, DAG); 906 case ISD::GlobalAddress: return lowerGlobalAddress(Op, DAG); 907 case ISD::BlockAddress: return lowerBlockAddress(Op, DAG); 908 case ISD::GlobalTLSAddress: return lowerGlobalTLSAddress(Op, DAG); 909 case ISD::JumpTable: return lowerJumpTable(Op, DAG); 910 case ISD::SELECT: return lowerSELECT(Op, DAG); 911 case ISD::SETCC: return lowerSETCC(Op, DAG); 912 case ISD::VASTART: return lowerVASTART(Op, DAG); 913 case ISD::VAARG: return lowerVAARG(Op, DAG); 914 case ISD::FCOPYSIGN: return lowerFCOPYSIGN(Op, DAG); 915 case ISD::FRAMEADDR: return lowerFRAMEADDR(Op, DAG); 916 case ISD::RETURNADDR: return lowerRETURNADDR(Op, DAG); 917 case ISD::EH_RETURN: return lowerEH_RETURN(Op, DAG); 918 case ISD::ATOMIC_FENCE: return lowerATOMIC_FENCE(Op, DAG); 919 case ISD::SHL_PARTS: return lowerShiftLeftParts(Op, DAG); 920 case ISD::SRA_PARTS: return lowerShiftRightParts(Op, DAG, true); 921 case ISD::SRL_PARTS: return lowerShiftRightParts(Op, DAG, false); 922 case ISD::LOAD: return lowerLOAD(Op, DAG); 923 case ISD::STORE: return lowerSTORE(Op, DAG); 924 case ISD::EH_DWARF_CFA: return lowerEH_DWARF_CFA(Op, DAG); 925 case ISD::FP_TO_SINT: return lowerFP_TO_SINT(Op, DAG); 926 } 927 return SDValue(); 928 } 929 930 //===----------------------------------------------------------------------===// 931 // Lower helper functions 932 //===----------------------------------------------------------------------===// 933 934 // addLiveIn - This helper function adds the specified physical register to the 935 // MachineFunction as a live in value. It also creates a corresponding 936 // virtual register for it. 937 static unsigned 938 addLiveIn(MachineFunction &MF, unsigned PReg, const TargetRegisterClass *RC) 939 { 940 unsigned VReg = MF.getRegInfo().createVirtualRegister(RC); 941 MF.getRegInfo().addLiveIn(PReg, VReg); 942 return VReg; 943 } 944 945 static MachineBasicBlock *insertDivByZeroTrap(MachineInstr &MI, 946 MachineBasicBlock &MBB, 947 const TargetInstrInfo &TII, 948 bool Is64Bit, bool IsMicroMips) { 949 if (NoZeroDivCheck) 950 return &MBB; 951 952 // Insert instruction "teq $divisor_reg, $zero, 7". 953 MachineBasicBlock::iterator I(MI); 954 MachineInstrBuilder MIB; 955 MachineOperand &Divisor = MI.getOperand(2); 956 MIB = BuildMI(MBB, std::next(I), MI.getDebugLoc(), 957 TII.get(IsMicroMips ? Mips::TEQ_MM : Mips::TEQ)) 958 .addReg(Divisor.getReg(), getKillRegState(Divisor.isKill())) 959 .addReg(Mips::ZERO) 960 .addImm(7); 961 962 // Use the 32-bit sub-register if this is a 64-bit division. 963 if (Is64Bit) 964 MIB->getOperand(0).setSubReg(Mips::sub_32); 965 966 // Clear Divisor's kill flag. 967 Divisor.setIsKill(false); 968 969 // We would normally delete the original instruction here but in this case 970 // we only needed to inject an additional instruction rather than replace it. 971 972 return &MBB; 973 } 974 975 MachineBasicBlock * 976 MipsTargetLowering::EmitInstrWithCustomInserter(MachineInstr &MI, 977 MachineBasicBlock *BB) const { 978 switch (MI.getOpcode()) { 979 default: 980 llvm_unreachable("Unexpected instr type to insert"); 981 case Mips::ATOMIC_LOAD_ADD_I8: 982 return emitAtomicBinaryPartword(MI, BB, 1, Mips::ADDu); 983 case Mips::ATOMIC_LOAD_ADD_I16: 984 return emitAtomicBinaryPartword(MI, BB, 2, Mips::ADDu); 985 case Mips::ATOMIC_LOAD_ADD_I32: 986 return emitAtomicBinary(MI, BB, 4, Mips::ADDu); 987 case Mips::ATOMIC_LOAD_ADD_I64: 988 return emitAtomicBinary(MI, BB, 8, Mips::DADDu); 989 990 case Mips::ATOMIC_LOAD_AND_I8: 991 return emitAtomicBinaryPartword(MI, BB, 1, Mips::AND); 992 case Mips::ATOMIC_LOAD_AND_I16: 993 return emitAtomicBinaryPartword(MI, BB, 2, Mips::AND); 994 case Mips::ATOMIC_LOAD_AND_I32: 995 return emitAtomicBinary(MI, BB, 4, Mips::AND); 996 case Mips::ATOMIC_LOAD_AND_I64: 997 return emitAtomicBinary(MI, BB, 8, Mips::AND64); 998 999 case Mips::ATOMIC_LOAD_OR_I8: 1000 return emitAtomicBinaryPartword(MI, BB, 1, Mips::OR); 1001 case Mips::ATOMIC_LOAD_OR_I16: 1002 return emitAtomicBinaryPartword(MI, BB, 2, Mips::OR); 1003 case Mips::ATOMIC_LOAD_OR_I32: 1004 return emitAtomicBinary(MI, BB, 4, Mips::OR); 1005 case Mips::ATOMIC_LOAD_OR_I64: 1006 return emitAtomicBinary(MI, BB, 8, Mips::OR64); 1007 1008 case Mips::ATOMIC_LOAD_XOR_I8: 1009 return emitAtomicBinaryPartword(MI, BB, 1, Mips::XOR); 1010 case Mips::ATOMIC_LOAD_XOR_I16: 1011 return emitAtomicBinaryPartword(MI, BB, 2, Mips::XOR); 1012 case Mips::ATOMIC_LOAD_XOR_I32: 1013 return emitAtomicBinary(MI, BB, 4, Mips::XOR); 1014 case Mips::ATOMIC_LOAD_XOR_I64: 1015 return emitAtomicBinary(MI, BB, 8, Mips::XOR64); 1016 1017 case Mips::ATOMIC_LOAD_NAND_I8: 1018 return emitAtomicBinaryPartword(MI, BB, 1, 0, true); 1019 case Mips::ATOMIC_LOAD_NAND_I16: 1020 return emitAtomicBinaryPartword(MI, BB, 2, 0, true); 1021 case Mips::ATOMIC_LOAD_NAND_I32: 1022 return emitAtomicBinary(MI, BB, 4, 0, true); 1023 case Mips::ATOMIC_LOAD_NAND_I64: 1024 return emitAtomicBinary(MI, BB, 8, 0, true); 1025 1026 case Mips::ATOMIC_LOAD_SUB_I8: 1027 return emitAtomicBinaryPartword(MI, BB, 1, Mips::SUBu); 1028 case Mips::ATOMIC_LOAD_SUB_I16: 1029 return emitAtomicBinaryPartword(MI, BB, 2, Mips::SUBu); 1030 case Mips::ATOMIC_LOAD_SUB_I32: 1031 return emitAtomicBinary(MI, BB, 4, Mips::SUBu); 1032 case Mips::ATOMIC_LOAD_SUB_I64: 1033 return emitAtomicBinary(MI, BB, 8, Mips::DSUBu); 1034 1035 case Mips::ATOMIC_SWAP_I8: 1036 return emitAtomicBinaryPartword(MI, BB, 1, 0); 1037 case Mips::ATOMIC_SWAP_I16: 1038 return emitAtomicBinaryPartword(MI, BB, 2, 0); 1039 case Mips::ATOMIC_SWAP_I32: 1040 return emitAtomicBinary(MI, BB, 4, 0); 1041 case Mips::ATOMIC_SWAP_I64: 1042 return emitAtomicBinary(MI, BB, 8, 0); 1043 1044 case Mips::ATOMIC_CMP_SWAP_I8: 1045 return emitAtomicCmpSwapPartword(MI, BB, 1); 1046 case Mips::ATOMIC_CMP_SWAP_I16: 1047 return emitAtomicCmpSwapPartword(MI, BB, 2); 1048 case Mips::ATOMIC_CMP_SWAP_I32: 1049 return emitAtomicCmpSwap(MI, BB, 4); 1050 case Mips::ATOMIC_CMP_SWAP_I64: 1051 return emitAtomicCmpSwap(MI, BB, 8); 1052 case Mips::PseudoSDIV: 1053 case Mips::PseudoUDIV: 1054 case Mips::DIV: 1055 case Mips::DIVU: 1056 case Mips::MOD: 1057 case Mips::MODU: 1058 return insertDivByZeroTrap(MI, *BB, *Subtarget.getInstrInfo(), false, 1059 false); 1060 case Mips::SDIV_MM_Pseudo: 1061 case Mips::UDIV_MM_Pseudo: 1062 case Mips::SDIV_MM: 1063 case Mips::UDIV_MM: 1064 case Mips::DIV_MMR6: 1065 case Mips::DIVU_MMR6: 1066 case Mips::MOD_MMR6: 1067 case Mips::MODU_MMR6: 1068 return insertDivByZeroTrap(MI, *BB, *Subtarget.getInstrInfo(), false, true); 1069 case Mips::PseudoDSDIV: 1070 case Mips::PseudoDUDIV: 1071 case Mips::DDIV: 1072 case Mips::DDIVU: 1073 case Mips::DMOD: 1074 case Mips::DMODU: 1075 return insertDivByZeroTrap(MI, *BB, *Subtarget.getInstrInfo(), true, false); 1076 case Mips::DDIV_MM64R6: 1077 case Mips::DDIVU_MM64R6: 1078 case Mips::DMOD_MM64R6: 1079 case Mips::DMODU_MM64R6: 1080 return insertDivByZeroTrap(MI, *BB, *Subtarget.getInstrInfo(), true, true); 1081 case Mips::SEL_D: 1082 case Mips::SEL_D_MMR6: 1083 return emitSEL_D(MI, BB); 1084 1085 case Mips::PseudoSELECT_I: 1086 case Mips::PseudoSELECT_I64: 1087 case Mips::PseudoSELECT_S: 1088 case Mips::PseudoSELECT_D32: 1089 case Mips::PseudoSELECT_D64: 1090 return emitPseudoSELECT(MI, BB, false, Mips::BNE); 1091 case Mips::PseudoSELECTFP_F_I: 1092 case Mips::PseudoSELECTFP_F_I64: 1093 case Mips::PseudoSELECTFP_F_S: 1094 case Mips::PseudoSELECTFP_F_D32: 1095 case Mips::PseudoSELECTFP_F_D64: 1096 return emitPseudoSELECT(MI, BB, true, Mips::BC1F); 1097 case Mips::PseudoSELECTFP_T_I: 1098 case Mips::PseudoSELECTFP_T_I64: 1099 case Mips::PseudoSELECTFP_T_S: 1100 case Mips::PseudoSELECTFP_T_D32: 1101 case Mips::PseudoSELECTFP_T_D64: 1102 return emitPseudoSELECT(MI, BB, true, Mips::BC1T); 1103 } 1104 } 1105 1106 // This function also handles Mips::ATOMIC_SWAP_I32 (when BinOpcode == 0), and 1107 // Mips::ATOMIC_LOAD_NAND_I32 (when Nand == true) 1108 MachineBasicBlock *MipsTargetLowering::emitAtomicBinary(MachineInstr &MI, 1109 MachineBasicBlock *BB, 1110 unsigned Size, 1111 unsigned BinOpcode, 1112 bool Nand) const { 1113 assert((Size == 4 || Size == 8) && "Unsupported size for EmitAtomicBinary."); 1114 1115 MachineFunction *MF = BB->getParent(); 1116 MachineRegisterInfo &RegInfo = MF->getRegInfo(); 1117 const TargetRegisterClass *RC = getRegClassFor(MVT::getIntegerVT(Size * 8)); 1118 const TargetInstrInfo *TII = Subtarget.getInstrInfo(); 1119 const bool ArePtrs64bit = ABI.ArePtrs64bit(); 1120 DebugLoc DL = MI.getDebugLoc(); 1121 unsigned LL, SC, AND, NOR, ZERO, BEQ; 1122 1123 if (Size == 4) { 1124 if (isMicroMips) { 1125 LL = Mips::LL_MM; 1126 SC = Mips::SC_MM; 1127 } else { 1128 LL = Subtarget.hasMips32r6() 1129 ? (ArePtrs64bit ? Mips::LL64_R6 : Mips::LL_R6) 1130 : (ArePtrs64bit ? Mips::LL64 : Mips::LL); 1131 SC = Subtarget.hasMips32r6() 1132 ? (ArePtrs64bit ? Mips::SC64_R6 : Mips::SC_R6) 1133 : (ArePtrs64bit ? Mips::SC64 : Mips::SC); 1134 } 1135 1136 AND = Mips::AND; 1137 NOR = Mips::NOR; 1138 ZERO = Mips::ZERO; 1139 BEQ = Mips::BEQ; 1140 } else { 1141 LL = Subtarget.hasMips64r6() ? Mips::LLD_R6 : Mips::LLD; 1142 SC = Subtarget.hasMips64r6() ? Mips::SCD_R6 : Mips::SCD; 1143 AND = Mips::AND64; 1144 NOR = Mips::NOR64; 1145 ZERO = Mips::ZERO_64; 1146 BEQ = Mips::BEQ64; 1147 } 1148 1149 unsigned OldVal = MI.getOperand(0).getReg(); 1150 unsigned Ptr = MI.getOperand(1).getReg(); 1151 unsigned Incr = MI.getOperand(2).getReg(); 1152 1153 unsigned StoreVal = RegInfo.createVirtualRegister(RC); 1154 unsigned AndRes = RegInfo.createVirtualRegister(RC); 1155 unsigned Success = RegInfo.createVirtualRegister(RC); 1156 1157 // insert new blocks after the current block 1158 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 1159 MachineBasicBlock *loopMBB = MF->CreateMachineBasicBlock(LLVM_BB); 1160 MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB); 1161 MachineFunction::iterator It = ++BB->getIterator(); 1162 MF->insert(It, loopMBB); 1163 MF->insert(It, exitMBB); 1164 1165 // Transfer the remainder of BB and its successor edges to exitMBB. 1166 exitMBB->splice(exitMBB->begin(), BB, 1167 std::next(MachineBasicBlock::iterator(MI)), BB->end()); 1168 exitMBB->transferSuccessorsAndUpdatePHIs(BB); 1169 1170 // thisMBB: 1171 // ... 1172 // fallthrough --> loopMBB 1173 BB->addSuccessor(loopMBB); 1174 loopMBB->addSuccessor(loopMBB); 1175 loopMBB->addSuccessor(exitMBB); 1176 1177 // loopMBB: 1178 // ll oldval, 0(ptr) 1179 // <binop> storeval, oldval, incr 1180 // sc success, storeval, 0(ptr) 1181 // beq success, $0, loopMBB 1182 BB = loopMBB; 1183 BuildMI(BB, DL, TII->get(LL), OldVal).addReg(Ptr).addImm(0); 1184 if (Nand) { 1185 // and andres, oldval, incr 1186 // nor storeval, $0, andres 1187 BuildMI(BB, DL, TII->get(AND), AndRes).addReg(OldVal).addReg(Incr); 1188 BuildMI(BB, DL, TII->get(NOR), StoreVal).addReg(ZERO).addReg(AndRes); 1189 } else if (BinOpcode) { 1190 // <binop> storeval, oldval, incr 1191 BuildMI(BB, DL, TII->get(BinOpcode), StoreVal).addReg(OldVal).addReg(Incr); 1192 } else { 1193 StoreVal = Incr; 1194 } 1195 BuildMI(BB, DL, TII->get(SC), Success).addReg(StoreVal).addReg(Ptr).addImm(0); 1196 BuildMI(BB, DL, TII->get(BEQ)).addReg(Success).addReg(ZERO).addMBB(loopMBB); 1197 1198 MI.eraseFromParent(); // The instruction is gone now. 1199 1200 return exitMBB; 1201 } 1202 1203 MachineBasicBlock *MipsTargetLowering::emitSignExtendToI32InReg( 1204 MachineInstr &MI, MachineBasicBlock *BB, unsigned Size, unsigned DstReg, 1205 unsigned SrcReg) const { 1206 const TargetInstrInfo *TII = Subtarget.getInstrInfo(); 1207 const DebugLoc &DL = MI.getDebugLoc(); 1208 1209 if (Subtarget.hasMips32r2() && Size == 1) { 1210 BuildMI(BB, DL, TII->get(Mips::SEB), DstReg).addReg(SrcReg); 1211 return BB; 1212 } 1213 1214 if (Subtarget.hasMips32r2() && Size == 2) { 1215 BuildMI(BB, DL, TII->get(Mips::SEH), DstReg).addReg(SrcReg); 1216 return BB; 1217 } 1218 1219 MachineFunction *MF = BB->getParent(); 1220 MachineRegisterInfo &RegInfo = MF->getRegInfo(); 1221 const TargetRegisterClass *RC = getRegClassFor(MVT::i32); 1222 unsigned ScrReg = RegInfo.createVirtualRegister(RC); 1223 1224 assert(Size < 32); 1225 int64_t ShiftImm = 32 - (Size * 8); 1226 1227 BuildMI(BB, DL, TII->get(Mips::SLL), ScrReg).addReg(SrcReg).addImm(ShiftImm); 1228 BuildMI(BB, DL, TII->get(Mips::SRA), DstReg).addReg(ScrReg).addImm(ShiftImm); 1229 1230 return BB; 1231 } 1232 1233 MachineBasicBlock *MipsTargetLowering::emitAtomicBinaryPartword( 1234 MachineInstr &MI, MachineBasicBlock *BB, unsigned Size, unsigned BinOpcode, 1235 bool Nand) const { 1236 assert((Size == 1 || Size == 2) && 1237 "Unsupported size for EmitAtomicBinaryPartial."); 1238 1239 MachineFunction *MF = BB->getParent(); 1240 MachineRegisterInfo &RegInfo = MF->getRegInfo(); 1241 const TargetRegisterClass *RC = getRegClassFor(MVT::i32); 1242 const bool ArePtrs64bit = ABI.ArePtrs64bit(); 1243 const TargetRegisterClass *RCp = 1244 getRegClassFor(ArePtrs64bit ? MVT::i64 : MVT::i32); 1245 const TargetInstrInfo *TII = Subtarget.getInstrInfo(); 1246 DebugLoc DL = MI.getDebugLoc(); 1247 1248 unsigned Dest = MI.getOperand(0).getReg(); 1249 unsigned Ptr = MI.getOperand(1).getReg(); 1250 unsigned Incr = MI.getOperand(2).getReg(); 1251 1252 unsigned AlignedAddr = RegInfo.createVirtualRegister(RCp); 1253 unsigned ShiftAmt = RegInfo.createVirtualRegister(RC); 1254 unsigned Mask = RegInfo.createVirtualRegister(RC); 1255 unsigned Mask2 = RegInfo.createVirtualRegister(RC); 1256 unsigned NewVal = RegInfo.createVirtualRegister(RC); 1257 unsigned OldVal = RegInfo.createVirtualRegister(RC); 1258 unsigned Incr2 = RegInfo.createVirtualRegister(RC); 1259 unsigned MaskLSB2 = RegInfo.createVirtualRegister(RCp); 1260 unsigned PtrLSB2 = RegInfo.createVirtualRegister(RC); 1261 unsigned MaskUpper = RegInfo.createVirtualRegister(RC); 1262 unsigned AndRes = RegInfo.createVirtualRegister(RC); 1263 unsigned BinOpRes = RegInfo.createVirtualRegister(RC); 1264 unsigned MaskedOldVal0 = RegInfo.createVirtualRegister(RC); 1265 unsigned StoreVal = RegInfo.createVirtualRegister(RC); 1266 unsigned MaskedOldVal1 = RegInfo.createVirtualRegister(RC); 1267 unsigned SrlRes = RegInfo.createVirtualRegister(RC); 1268 unsigned Success = RegInfo.createVirtualRegister(RC); 1269 1270 unsigned LL, SC; 1271 if (isMicroMips) { 1272 LL = Mips::LL_MM; 1273 SC = Mips::SC_MM; 1274 } else { 1275 LL = Subtarget.hasMips32r6() ? (ArePtrs64bit ? Mips::LL64_R6 : Mips::LL_R6) 1276 : (ArePtrs64bit ? Mips::LL64 : Mips::LL); 1277 SC = Subtarget.hasMips32r6() ? (ArePtrs64bit ? Mips::SC64_R6 : Mips::SC_R6) 1278 : (ArePtrs64bit ? Mips::SC64 : Mips::SC); 1279 } 1280 1281 // insert new blocks after the current block 1282 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 1283 MachineBasicBlock *loopMBB = MF->CreateMachineBasicBlock(LLVM_BB); 1284 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(LLVM_BB); 1285 MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB); 1286 MachineFunction::iterator It = ++BB->getIterator(); 1287 MF->insert(It, loopMBB); 1288 MF->insert(It, sinkMBB); 1289 MF->insert(It, exitMBB); 1290 1291 // Transfer the remainder of BB and its successor edges to exitMBB. 1292 exitMBB->splice(exitMBB->begin(), BB, 1293 std::next(MachineBasicBlock::iterator(MI)), BB->end()); 1294 exitMBB->transferSuccessorsAndUpdatePHIs(BB); 1295 1296 BB->addSuccessor(loopMBB); 1297 loopMBB->addSuccessor(loopMBB); 1298 loopMBB->addSuccessor(sinkMBB); 1299 sinkMBB->addSuccessor(exitMBB); 1300 1301 // thisMBB: 1302 // addiu masklsb2,$0,-4 # 0xfffffffc 1303 // and alignedaddr,ptr,masklsb2 1304 // andi ptrlsb2,ptr,3 1305 // sll shiftamt,ptrlsb2,3 1306 // ori maskupper,$0,255 # 0xff 1307 // sll mask,maskupper,shiftamt 1308 // nor mask2,$0,mask 1309 // sll incr2,incr,shiftamt 1310 1311 int64_t MaskImm = (Size == 1) ? 255 : 65535; 1312 BuildMI(BB, DL, TII->get(ABI.GetPtrAddiuOp()), MaskLSB2) 1313 .addReg(ABI.GetNullPtr()).addImm(-4); 1314 BuildMI(BB, DL, TII->get(ABI.GetPtrAndOp()), AlignedAddr) 1315 .addReg(Ptr).addReg(MaskLSB2); 1316 BuildMI(BB, DL, TII->get(Mips::ANDi), PtrLSB2) 1317 .addReg(Ptr, 0, ArePtrs64bit ? Mips::sub_32 : 0).addImm(3); 1318 if (Subtarget.isLittle()) { 1319 BuildMI(BB, DL, TII->get(Mips::SLL), ShiftAmt).addReg(PtrLSB2).addImm(3); 1320 } else { 1321 unsigned Off = RegInfo.createVirtualRegister(RC); 1322 BuildMI(BB, DL, TII->get(Mips::XORi), Off) 1323 .addReg(PtrLSB2).addImm((Size == 1) ? 3 : 2); 1324 BuildMI(BB, DL, TII->get(Mips::SLL), ShiftAmt).addReg(Off).addImm(3); 1325 } 1326 BuildMI(BB, DL, TII->get(Mips::ORi), MaskUpper) 1327 .addReg(Mips::ZERO).addImm(MaskImm); 1328 BuildMI(BB, DL, TII->get(Mips::SLLV), Mask) 1329 .addReg(MaskUpper).addReg(ShiftAmt); 1330 BuildMI(BB, DL, TII->get(Mips::NOR), Mask2).addReg(Mips::ZERO).addReg(Mask); 1331 BuildMI(BB, DL, TII->get(Mips::SLLV), Incr2).addReg(Incr).addReg(ShiftAmt); 1332 1333 // atomic.load.binop 1334 // loopMBB: 1335 // ll oldval,0(alignedaddr) 1336 // binop binopres,oldval,incr2 1337 // and newval,binopres,mask 1338 // and maskedoldval0,oldval,mask2 1339 // or storeval,maskedoldval0,newval 1340 // sc success,storeval,0(alignedaddr) 1341 // beq success,$0,loopMBB 1342 1343 // atomic.swap 1344 // loopMBB: 1345 // ll oldval,0(alignedaddr) 1346 // and newval,incr2,mask 1347 // and maskedoldval0,oldval,mask2 1348 // or storeval,maskedoldval0,newval 1349 // sc success,storeval,0(alignedaddr) 1350 // beq success,$0,loopMBB 1351 1352 BB = loopMBB; 1353 BuildMI(BB, DL, TII->get(LL), OldVal).addReg(AlignedAddr).addImm(0); 1354 if (Nand) { 1355 // and andres, oldval, incr2 1356 // nor binopres, $0, andres 1357 // and newval, binopres, mask 1358 BuildMI(BB, DL, TII->get(Mips::AND), AndRes).addReg(OldVal).addReg(Incr2); 1359 BuildMI(BB, DL, TII->get(Mips::NOR), BinOpRes) 1360 .addReg(Mips::ZERO).addReg(AndRes); 1361 BuildMI(BB, DL, TII->get(Mips::AND), NewVal).addReg(BinOpRes).addReg(Mask); 1362 } else if (BinOpcode) { 1363 // <binop> binopres, oldval, incr2 1364 // and newval, binopres, mask 1365 BuildMI(BB, DL, TII->get(BinOpcode), BinOpRes).addReg(OldVal).addReg(Incr2); 1366 BuildMI(BB, DL, TII->get(Mips::AND), NewVal).addReg(BinOpRes).addReg(Mask); 1367 } else { // atomic.swap 1368 // and newval, incr2, mask 1369 BuildMI(BB, DL, TII->get(Mips::AND), NewVal).addReg(Incr2).addReg(Mask); 1370 } 1371 1372 BuildMI(BB, DL, TII->get(Mips::AND), MaskedOldVal0) 1373 .addReg(OldVal).addReg(Mask2); 1374 BuildMI(BB, DL, TII->get(Mips::OR), StoreVal) 1375 .addReg(MaskedOldVal0).addReg(NewVal); 1376 BuildMI(BB, DL, TII->get(SC), Success) 1377 .addReg(StoreVal).addReg(AlignedAddr).addImm(0); 1378 BuildMI(BB, DL, TII->get(Mips::BEQ)) 1379 .addReg(Success).addReg(Mips::ZERO).addMBB(loopMBB); 1380 1381 // sinkMBB: 1382 // and maskedoldval1,oldval,mask 1383 // srl srlres,maskedoldval1,shiftamt 1384 // sign_extend dest,srlres 1385 BB = sinkMBB; 1386 1387 BuildMI(BB, DL, TII->get(Mips::AND), MaskedOldVal1) 1388 .addReg(OldVal).addReg(Mask); 1389 BuildMI(BB, DL, TII->get(Mips::SRLV), SrlRes) 1390 .addReg(MaskedOldVal1).addReg(ShiftAmt); 1391 BB = emitSignExtendToI32InReg(MI, BB, Size, Dest, SrlRes); 1392 1393 MI.eraseFromParent(); // The instruction is gone now. 1394 1395 return exitMBB; 1396 } 1397 1398 MachineBasicBlock *MipsTargetLowering::emitAtomicCmpSwap(MachineInstr &MI, 1399 MachineBasicBlock *BB, 1400 unsigned Size) const { 1401 assert((Size == 4 || Size == 8) && "Unsupported size for EmitAtomicCmpSwap."); 1402 1403 MachineFunction *MF = BB->getParent(); 1404 MachineRegisterInfo &RegInfo = MF->getRegInfo(); 1405 const TargetRegisterClass *RC = getRegClassFor(MVT::getIntegerVT(Size * 8)); 1406 const TargetInstrInfo *TII = Subtarget.getInstrInfo(); 1407 const bool ArePtrs64bit = ABI.ArePtrs64bit(); 1408 DebugLoc DL = MI.getDebugLoc(); 1409 unsigned LL, SC, ZERO, BNE, BEQ; 1410 1411 if (Size == 4) { 1412 if (isMicroMips) { 1413 LL = Mips::LL_MM; 1414 SC = Mips::SC_MM; 1415 } else { 1416 LL = Subtarget.hasMips32r6() 1417 ? (ArePtrs64bit ? Mips::LL64_R6 : Mips::LL_R6) 1418 : (ArePtrs64bit ? Mips::LL64 : Mips::LL); 1419 SC = Subtarget.hasMips32r6() 1420 ? (ArePtrs64bit ? Mips::SC64_R6 : Mips::SC_R6) 1421 : (ArePtrs64bit ? Mips::SC64 : Mips::SC); 1422 } 1423 1424 ZERO = Mips::ZERO; 1425 BNE = Mips::BNE; 1426 BEQ = Mips::BEQ; 1427 } else { 1428 LL = Subtarget.hasMips64r6() ? Mips::LLD_R6 : Mips::LLD; 1429 SC = Subtarget.hasMips64r6() ? Mips::SCD_R6 : Mips::SCD; 1430 ZERO = Mips::ZERO_64; 1431 BNE = Mips::BNE64; 1432 BEQ = Mips::BEQ64; 1433 } 1434 1435 unsigned Dest = MI.getOperand(0).getReg(); 1436 unsigned Ptr = MI.getOperand(1).getReg(); 1437 unsigned OldVal = MI.getOperand(2).getReg(); 1438 unsigned NewVal = MI.getOperand(3).getReg(); 1439 1440 unsigned Success = RegInfo.createVirtualRegister(RC); 1441 1442 // insert new blocks after the current block 1443 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 1444 MachineBasicBlock *loop1MBB = MF->CreateMachineBasicBlock(LLVM_BB); 1445 MachineBasicBlock *loop2MBB = MF->CreateMachineBasicBlock(LLVM_BB); 1446 MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB); 1447 MachineFunction::iterator It = ++BB->getIterator(); 1448 MF->insert(It, loop1MBB); 1449 MF->insert(It, loop2MBB); 1450 MF->insert(It, exitMBB); 1451 1452 // Transfer the remainder of BB and its successor edges to exitMBB. 1453 exitMBB->splice(exitMBB->begin(), BB, 1454 std::next(MachineBasicBlock::iterator(MI)), BB->end()); 1455 exitMBB->transferSuccessorsAndUpdatePHIs(BB); 1456 1457 // thisMBB: 1458 // ... 1459 // fallthrough --> loop1MBB 1460 BB->addSuccessor(loop1MBB); 1461 loop1MBB->addSuccessor(exitMBB); 1462 loop1MBB->addSuccessor(loop2MBB); 1463 loop2MBB->addSuccessor(loop1MBB); 1464 loop2MBB->addSuccessor(exitMBB); 1465 1466 // loop1MBB: 1467 // ll dest, 0(ptr) 1468 // bne dest, oldval, exitMBB 1469 BB = loop1MBB; 1470 BuildMI(BB, DL, TII->get(LL), Dest).addReg(Ptr).addImm(0); 1471 BuildMI(BB, DL, TII->get(BNE)) 1472 .addReg(Dest).addReg(OldVal).addMBB(exitMBB); 1473 1474 // loop2MBB: 1475 // sc success, newval, 0(ptr) 1476 // beq success, $0, loop1MBB 1477 BB = loop2MBB; 1478 BuildMI(BB, DL, TII->get(SC), Success) 1479 .addReg(NewVal).addReg(Ptr).addImm(0); 1480 BuildMI(BB, DL, TII->get(BEQ)) 1481 .addReg(Success).addReg(ZERO).addMBB(loop1MBB); 1482 1483 MI.eraseFromParent(); // The instruction is gone now. 1484 1485 return exitMBB; 1486 } 1487 1488 MachineBasicBlock *MipsTargetLowering::emitAtomicCmpSwapPartword( 1489 MachineInstr &MI, MachineBasicBlock *BB, unsigned Size) const { 1490 assert((Size == 1 || Size == 2) && 1491 "Unsupported size for EmitAtomicCmpSwapPartial."); 1492 1493 MachineFunction *MF = BB->getParent(); 1494 MachineRegisterInfo &RegInfo = MF->getRegInfo(); 1495 const TargetRegisterClass *RC = getRegClassFor(MVT::i32); 1496 const bool ArePtrs64bit = ABI.ArePtrs64bit(); 1497 const TargetRegisterClass *RCp = 1498 getRegClassFor(ArePtrs64bit ? MVT::i64 : MVT::i32); 1499 const TargetInstrInfo *TII = Subtarget.getInstrInfo(); 1500 DebugLoc DL = MI.getDebugLoc(); 1501 1502 unsigned Dest = MI.getOperand(0).getReg(); 1503 unsigned Ptr = MI.getOperand(1).getReg(); 1504 unsigned CmpVal = MI.getOperand(2).getReg(); 1505 unsigned NewVal = MI.getOperand(3).getReg(); 1506 1507 unsigned AlignedAddr = RegInfo.createVirtualRegister(RCp); 1508 unsigned ShiftAmt = RegInfo.createVirtualRegister(RC); 1509 unsigned Mask = RegInfo.createVirtualRegister(RC); 1510 unsigned Mask2 = RegInfo.createVirtualRegister(RC); 1511 unsigned ShiftedCmpVal = RegInfo.createVirtualRegister(RC); 1512 unsigned OldVal = RegInfo.createVirtualRegister(RC); 1513 unsigned MaskedOldVal0 = RegInfo.createVirtualRegister(RC); 1514 unsigned ShiftedNewVal = RegInfo.createVirtualRegister(RC); 1515 unsigned MaskLSB2 = RegInfo.createVirtualRegister(RCp); 1516 unsigned PtrLSB2 = RegInfo.createVirtualRegister(RC); 1517 unsigned MaskUpper = RegInfo.createVirtualRegister(RC); 1518 unsigned MaskedCmpVal = RegInfo.createVirtualRegister(RC); 1519 unsigned MaskedNewVal = RegInfo.createVirtualRegister(RC); 1520 unsigned MaskedOldVal1 = RegInfo.createVirtualRegister(RC); 1521 unsigned StoreVal = RegInfo.createVirtualRegister(RC); 1522 unsigned SrlRes = RegInfo.createVirtualRegister(RC); 1523 unsigned Success = RegInfo.createVirtualRegister(RC); 1524 unsigned LL, SC; 1525 1526 if (isMicroMips) { 1527 LL = Mips::LL_MM; 1528 SC = Mips::SC_MM; 1529 } else { 1530 LL = Subtarget.hasMips32r6() ? (ArePtrs64bit ? Mips::LL64_R6 : Mips::LL_R6) 1531 : (ArePtrs64bit ? Mips::LL64 : Mips::LL); 1532 SC = Subtarget.hasMips32r6() ? (ArePtrs64bit ? Mips::SC64_R6 : Mips::SC_R6) 1533 : (ArePtrs64bit ? Mips::SC64 : Mips::SC); 1534 } 1535 1536 // insert new blocks after the current block 1537 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 1538 MachineBasicBlock *loop1MBB = MF->CreateMachineBasicBlock(LLVM_BB); 1539 MachineBasicBlock *loop2MBB = MF->CreateMachineBasicBlock(LLVM_BB); 1540 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(LLVM_BB); 1541 MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB); 1542 MachineFunction::iterator It = ++BB->getIterator(); 1543 MF->insert(It, loop1MBB); 1544 MF->insert(It, loop2MBB); 1545 MF->insert(It, sinkMBB); 1546 MF->insert(It, exitMBB); 1547 1548 // Transfer the remainder of BB and its successor edges to exitMBB. 1549 exitMBB->splice(exitMBB->begin(), BB, 1550 std::next(MachineBasicBlock::iterator(MI)), BB->end()); 1551 exitMBB->transferSuccessorsAndUpdatePHIs(BB); 1552 1553 BB->addSuccessor(loop1MBB); 1554 loop1MBB->addSuccessor(sinkMBB); 1555 loop1MBB->addSuccessor(loop2MBB); 1556 loop2MBB->addSuccessor(loop1MBB); 1557 loop2MBB->addSuccessor(sinkMBB); 1558 sinkMBB->addSuccessor(exitMBB); 1559 1560 // FIXME: computation of newval2 can be moved to loop2MBB. 1561 // thisMBB: 1562 // addiu masklsb2,$0,-4 # 0xfffffffc 1563 // and alignedaddr,ptr,masklsb2 1564 // andi ptrlsb2,ptr,3 1565 // xori ptrlsb2,ptrlsb2,3 # Only for BE 1566 // sll shiftamt,ptrlsb2,3 1567 // ori maskupper,$0,255 # 0xff 1568 // sll mask,maskupper,shiftamt 1569 // nor mask2,$0,mask 1570 // andi maskedcmpval,cmpval,255 1571 // sll shiftedcmpval,maskedcmpval,shiftamt 1572 // andi maskednewval,newval,255 1573 // sll shiftednewval,maskednewval,shiftamt 1574 int64_t MaskImm = (Size == 1) ? 255 : 65535; 1575 BuildMI(BB, DL, TII->get(ArePtrs64bit ? Mips::DADDiu : Mips::ADDiu), MaskLSB2) 1576 .addReg(ABI.GetNullPtr()).addImm(-4); 1577 BuildMI(BB, DL, TII->get(ArePtrs64bit ? Mips::AND64 : Mips::AND), AlignedAddr) 1578 .addReg(Ptr).addReg(MaskLSB2); 1579 BuildMI(BB, DL, TII->get(Mips::ANDi), PtrLSB2) 1580 .addReg(Ptr, 0, ArePtrs64bit ? Mips::sub_32 : 0).addImm(3); 1581 if (Subtarget.isLittle()) { 1582 BuildMI(BB, DL, TII->get(Mips::SLL), ShiftAmt).addReg(PtrLSB2).addImm(3); 1583 } else { 1584 unsigned Off = RegInfo.createVirtualRegister(RC); 1585 BuildMI(BB, DL, TII->get(Mips::XORi), Off) 1586 .addReg(PtrLSB2).addImm((Size == 1) ? 3 : 2); 1587 BuildMI(BB, DL, TII->get(Mips::SLL), ShiftAmt).addReg(Off).addImm(3); 1588 } 1589 BuildMI(BB, DL, TII->get(Mips::ORi), MaskUpper) 1590 .addReg(Mips::ZERO).addImm(MaskImm); 1591 BuildMI(BB, DL, TII->get(Mips::SLLV), Mask) 1592 .addReg(MaskUpper).addReg(ShiftAmt); 1593 BuildMI(BB, DL, TII->get(Mips::NOR), Mask2).addReg(Mips::ZERO).addReg(Mask); 1594 BuildMI(BB, DL, TII->get(Mips::ANDi), MaskedCmpVal) 1595 .addReg(CmpVal).addImm(MaskImm); 1596 BuildMI(BB, DL, TII->get(Mips::SLLV), ShiftedCmpVal) 1597 .addReg(MaskedCmpVal).addReg(ShiftAmt); 1598 BuildMI(BB, DL, TII->get(Mips::ANDi), MaskedNewVal) 1599 .addReg(NewVal).addImm(MaskImm); 1600 BuildMI(BB, DL, TII->get(Mips::SLLV), ShiftedNewVal) 1601 .addReg(MaskedNewVal).addReg(ShiftAmt); 1602 1603 // loop1MBB: 1604 // ll oldval,0(alginedaddr) 1605 // and maskedoldval0,oldval,mask 1606 // bne maskedoldval0,shiftedcmpval,sinkMBB 1607 BB = loop1MBB; 1608 BuildMI(BB, DL, TII->get(LL), OldVal).addReg(AlignedAddr).addImm(0); 1609 BuildMI(BB, DL, TII->get(Mips::AND), MaskedOldVal0) 1610 .addReg(OldVal).addReg(Mask); 1611 BuildMI(BB, DL, TII->get(Mips::BNE)) 1612 .addReg(MaskedOldVal0).addReg(ShiftedCmpVal).addMBB(sinkMBB); 1613 1614 // loop2MBB: 1615 // and maskedoldval1,oldval,mask2 1616 // or storeval,maskedoldval1,shiftednewval 1617 // sc success,storeval,0(alignedaddr) 1618 // beq success,$0,loop1MBB 1619 BB = loop2MBB; 1620 BuildMI(BB, DL, TII->get(Mips::AND), MaskedOldVal1) 1621 .addReg(OldVal).addReg(Mask2); 1622 BuildMI(BB, DL, TII->get(Mips::OR), StoreVal) 1623 .addReg(MaskedOldVal1).addReg(ShiftedNewVal); 1624 BuildMI(BB, DL, TII->get(SC), Success) 1625 .addReg(StoreVal).addReg(AlignedAddr).addImm(0); 1626 BuildMI(BB, DL, TII->get(Mips::BEQ)) 1627 .addReg(Success).addReg(Mips::ZERO).addMBB(loop1MBB); 1628 1629 // sinkMBB: 1630 // srl srlres,maskedoldval0,shiftamt 1631 // sign_extend dest,srlres 1632 BB = sinkMBB; 1633 1634 BuildMI(BB, DL, TII->get(Mips::SRLV), SrlRes) 1635 .addReg(MaskedOldVal0).addReg(ShiftAmt); 1636 BB = emitSignExtendToI32InReg(MI, BB, Size, Dest, SrlRes); 1637 1638 MI.eraseFromParent(); // The instruction is gone now. 1639 1640 return exitMBB; 1641 } 1642 1643 MachineBasicBlock *MipsTargetLowering::emitSEL_D(MachineInstr &MI, 1644 MachineBasicBlock *BB) const { 1645 MachineFunction *MF = BB->getParent(); 1646 const TargetRegisterInfo *TRI = Subtarget.getRegisterInfo(); 1647 const TargetInstrInfo *TII = Subtarget.getInstrInfo(); 1648 MachineRegisterInfo &RegInfo = MF->getRegInfo(); 1649 DebugLoc DL = MI.getDebugLoc(); 1650 MachineBasicBlock::iterator II(MI); 1651 1652 unsigned Fc = MI.getOperand(1).getReg(); 1653 const auto &FGR64RegClass = TRI->getRegClass(Mips::FGR64RegClassID); 1654 1655 unsigned Fc2 = RegInfo.createVirtualRegister(FGR64RegClass); 1656 1657 BuildMI(*BB, II, DL, TII->get(Mips::SUBREG_TO_REG), Fc2) 1658 .addImm(0) 1659 .addReg(Fc) 1660 .addImm(Mips::sub_lo); 1661 1662 // We don't erase the original instruction, we just replace the condition 1663 // register with the 64-bit super-register. 1664 MI.getOperand(1).setReg(Fc2); 1665 1666 return BB; 1667 } 1668 1669 //===----------------------------------------------------------------------===// 1670 // Misc Lower Operation implementation 1671 //===----------------------------------------------------------------------===// 1672 SDValue MipsTargetLowering::lowerBR_JT(SDValue Op, SelectionDAG &DAG) const { 1673 SDValue Chain = Op.getOperand(0); 1674 SDValue Table = Op.getOperand(1); 1675 SDValue Index = Op.getOperand(2); 1676 SDLoc DL(Op); 1677 auto &TD = DAG.getDataLayout(); 1678 EVT PTy = getPointerTy(TD); 1679 unsigned EntrySize = 1680 DAG.getMachineFunction().getJumpTableInfo()->getEntrySize(TD); 1681 1682 Index = DAG.getNode(ISD::MUL, DL, PTy, Index, 1683 DAG.getConstant(EntrySize, DL, PTy)); 1684 SDValue Addr = DAG.getNode(ISD::ADD, DL, PTy, Index, Table); 1685 1686 EVT MemVT = EVT::getIntegerVT(*DAG.getContext(), EntrySize * 8); 1687 Addr = DAG.getExtLoad( 1688 ISD::SEXTLOAD, DL, PTy, Chain, Addr, 1689 MachinePointerInfo::getJumpTable(DAG.getMachineFunction()), MemVT); 1690 Chain = Addr.getValue(1); 1691 1692 if (isPositionIndependent() || ABI.IsN64()) { 1693 // For PIC, the sequence is: 1694 // BRIND(load(Jumptable + index) + RelocBase) 1695 // RelocBase can be JumpTable, GOT or some sort of global base. 1696 Addr = DAG.getNode(ISD::ADD, DL, PTy, Addr, 1697 getPICJumpTableRelocBase(Table, DAG)); 1698 } 1699 1700 return DAG.getNode(ISD::BRIND, DL, MVT::Other, Chain, Addr); 1701 } 1702 1703 SDValue MipsTargetLowering::lowerBRCOND(SDValue Op, SelectionDAG &DAG) const { 1704 // The first operand is the chain, the second is the condition, the third is 1705 // the block to branch to if the condition is true. 1706 SDValue Chain = Op.getOperand(0); 1707 SDValue Dest = Op.getOperand(2); 1708 SDLoc DL(Op); 1709 1710 assert(!Subtarget.hasMips32r6() && !Subtarget.hasMips64r6()); 1711 SDValue CondRes = createFPCmp(DAG, Op.getOperand(1)); 1712 1713 // Return if flag is not set by a floating point comparison. 1714 if (CondRes.getOpcode() != MipsISD::FPCmp) 1715 return Op; 1716 1717 SDValue CCNode = CondRes.getOperand(2); 1718 Mips::CondCode CC = 1719 (Mips::CondCode)cast<ConstantSDNode>(CCNode)->getZExtValue(); 1720 unsigned Opc = invertFPCondCodeUser(CC) ? Mips::BRANCH_F : Mips::BRANCH_T; 1721 SDValue BrCode = DAG.getConstant(Opc, DL, MVT::i32); 1722 SDValue FCC0 = DAG.getRegister(Mips::FCC0, MVT::i32); 1723 return DAG.getNode(MipsISD::FPBrcond, DL, Op.getValueType(), Chain, BrCode, 1724 FCC0, Dest, CondRes); 1725 } 1726 1727 SDValue MipsTargetLowering:: 1728 lowerSELECT(SDValue Op, SelectionDAG &DAG) const 1729 { 1730 assert(!Subtarget.hasMips32r6() && !Subtarget.hasMips64r6()); 1731 SDValue Cond = createFPCmp(DAG, Op.getOperand(0)); 1732 1733 // Return if flag is not set by a floating point comparison. 1734 if (Cond.getOpcode() != MipsISD::FPCmp) 1735 return Op; 1736 1737 return createCMovFP(DAG, Cond, Op.getOperand(1), Op.getOperand(2), 1738 SDLoc(Op)); 1739 } 1740 1741 SDValue MipsTargetLowering::lowerSETCC(SDValue Op, SelectionDAG &DAG) const { 1742 assert(!Subtarget.hasMips32r6() && !Subtarget.hasMips64r6()); 1743 SDValue Cond = createFPCmp(DAG, Op); 1744 1745 assert(Cond.getOpcode() == MipsISD::FPCmp && 1746 "Floating point operand expected."); 1747 1748 SDLoc DL(Op); 1749 SDValue True = DAG.getConstant(1, DL, MVT::i32); 1750 SDValue False = DAG.getConstant(0, DL, MVT::i32); 1751 1752 return createCMovFP(DAG, Cond, True, False, DL); 1753 } 1754 1755 SDValue MipsTargetLowering::lowerGlobalAddress(SDValue Op, 1756 SelectionDAG &DAG) const { 1757 EVT Ty = Op.getValueType(); 1758 GlobalAddressSDNode *N = cast<GlobalAddressSDNode>(Op); 1759 const GlobalValue *GV = N->getGlobal(); 1760 1761 if (!isPositionIndependent() && !ABI.IsN64()) { 1762 const MipsTargetObjectFile *TLOF = 1763 static_cast<const MipsTargetObjectFile *>( 1764 getTargetMachine().getObjFileLowering()); 1765 if (TLOF->IsGlobalInSmallSection(GV, getTargetMachine())) 1766 // %gp_rel relocation 1767 return getAddrGPRel(N, SDLoc(N), Ty, DAG); 1768 1769 // %hi/%lo relocation 1770 return getAddrNonPIC(N, SDLoc(N), Ty, DAG); 1771 } 1772 1773 // Every other architecture would use shouldAssumeDSOLocal in here, but 1774 // mips is special. 1775 // * In PIC code mips requires got loads even for local statics! 1776 // * To save on got entries, for local statics the got entry contains the 1777 // page and an additional add instruction takes care of the low bits. 1778 // * It is legal to access a hidden symbol with a non hidden undefined, 1779 // so one cannot guarantee that all access to a hidden symbol will know 1780 // it is hidden. 1781 // * Mips linkers don't support creating a page and a full got entry for 1782 // the same symbol. 1783 // * Given all that, we have to use a full got entry for hidden symbols :-( 1784 if (GV->hasLocalLinkage()) 1785 return getAddrLocal(N, SDLoc(N), Ty, DAG, ABI.IsN32() || ABI.IsN64()); 1786 1787 if (LargeGOT) 1788 return getAddrGlobalLargeGOT( 1789 N, SDLoc(N), Ty, DAG, MipsII::MO_GOT_HI16, MipsII::MO_GOT_LO16, 1790 DAG.getEntryNode(), 1791 MachinePointerInfo::getGOT(DAG.getMachineFunction())); 1792 1793 return getAddrGlobal( 1794 N, SDLoc(N), Ty, DAG, 1795 (ABI.IsN32() || ABI.IsN64()) ? MipsII::MO_GOT_DISP : MipsII::MO_GOT, 1796 DAG.getEntryNode(), MachinePointerInfo::getGOT(DAG.getMachineFunction())); 1797 } 1798 1799 SDValue MipsTargetLowering::lowerBlockAddress(SDValue Op, 1800 SelectionDAG &DAG) const { 1801 BlockAddressSDNode *N = cast<BlockAddressSDNode>(Op); 1802 EVT Ty = Op.getValueType(); 1803 1804 if (!isPositionIndependent() && !ABI.IsN64()) 1805 return getAddrNonPIC(N, SDLoc(N), Ty, DAG); 1806 1807 return getAddrLocal(N, SDLoc(N), Ty, DAG, ABI.IsN32() || ABI.IsN64()); 1808 } 1809 1810 SDValue MipsTargetLowering:: 1811 lowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const 1812 { 1813 // If the relocation model is PIC, use the General Dynamic TLS Model or 1814 // Local Dynamic TLS model, otherwise use the Initial Exec or 1815 // Local Exec TLS Model. 1816 1817 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op); 1818 if (DAG.getTarget().Options.EmulatedTLS) 1819 return LowerToTLSEmulatedModel(GA, DAG); 1820 1821 SDLoc DL(GA); 1822 const GlobalValue *GV = GA->getGlobal(); 1823 EVT PtrVT = getPointerTy(DAG.getDataLayout()); 1824 1825 TLSModel::Model model = getTargetMachine().getTLSModel(GV); 1826 1827 if (model == TLSModel::GeneralDynamic || model == TLSModel::LocalDynamic) { 1828 // General Dynamic and Local Dynamic TLS Model. 1829 unsigned Flag = (model == TLSModel::LocalDynamic) ? MipsII::MO_TLSLDM 1830 : MipsII::MO_TLSGD; 1831 1832 SDValue TGA = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, Flag); 1833 SDValue Argument = DAG.getNode(MipsISD::Wrapper, DL, PtrVT, 1834 getGlobalReg(DAG, PtrVT), TGA); 1835 unsigned PtrSize = PtrVT.getSizeInBits(); 1836 IntegerType *PtrTy = Type::getIntNTy(*DAG.getContext(), PtrSize); 1837 1838 SDValue TlsGetAddr = DAG.getExternalSymbol("__tls_get_addr", PtrVT); 1839 1840 ArgListTy Args; 1841 ArgListEntry Entry; 1842 Entry.Node = Argument; 1843 Entry.Ty = PtrTy; 1844 Args.push_back(Entry); 1845 1846 TargetLowering::CallLoweringInfo CLI(DAG); 1847 CLI.setDebugLoc(DL).setChain(DAG.getEntryNode()) 1848 .setCallee(CallingConv::C, PtrTy, TlsGetAddr, std::move(Args)); 1849 std::pair<SDValue, SDValue> CallResult = LowerCallTo(CLI); 1850 1851 SDValue Ret = CallResult.first; 1852 1853 if (model != TLSModel::LocalDynamic) 1854 return Ret; 1855 1856 SDValue TGAHi = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, 1857 MipsII::MO_DTPREL_HI); 1858 SDValue Hi = DAG.getNode(MipsISD::Hi, DL, PtrVT, TGAHi); 1859 SDValue TGALo = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, 1860 MipsII::MO_DTPREL_LO); 1861 SDValue Lo = DAG.getNode(MipsISD::Lo, DL, PtrVT, TGALo); 1862 SDValue Add = DAG.getNode(ISD::ADD, DL, PtrVT, Hi, Ret); 1863 return DAG.getNode(ISD::ADD, DL, PtrVT, Add, Lo); 1864 } 1865 1866 SDValue Offset; 1867 if (model == TLSModel::InitialExec) { 1868 // Initial Exec TLS Model 1869 SDValue TGA = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, 1870 MipsII::MO_GOTTPREL); 1871 TGA = DAG.getNode(MipsISD::Wrapper, DL, PtrVT, getGlobalReg(DAG, PtrVT), 1872 TGA); 1873 Offset = 1874 DAG.getLoad(PtrVT, DL, DAG.getEntryNode(), TGA, MachinePointerInfo()); 1875 } else { 1876 // Local Exec TLS Model 1877 assert(model == TLSModel::LocalExec); 1878 SDValue TGAHi = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, 1879 MipsII::MO_TPREL_HI); 1880 SDValue TGALo = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, 1881 MipsII::MO_TPREL_LO); 1882 SDValue Hi = DAG.getNode(MipsISD::Hi, DL, PtrVT, TGAHi); 1883 SDValue Lo = DAG.getNode(MipsISD::Lo, DL, PtrVT, TGALo); 1884 Offset = DAG.getNode(ISD::ADD, DL, PtrVT, Hi, Lo); 1885 } 1886 1887 SDValue ThreadPointer = DAG.getNode(MipsISD::ThreadPointer, DL, PtrVT); 1888 return DAG.getNode(ISD::ADD, DL, PtrVT, ThreadPointer, Offset); 1889 } 1890 1891 SDValue MipsTargetLowering:: 1892 lowerJumpTable(SDValue Op, SelectionDAG &DAG) const 1893 { 1894 JumpTableSDNode *N = cast<JumpTableSDNode>(Op); 1895 EVT Ty = Op.getValueType(); 1896 1897 if (!isPositionIndependent() && !ABI.IsN64()) 1898 return getAddrNonPIC(N, SDLoc(N), Ty, DAG); 1899 1900 return getAddrLocal(N, SDLoc(N), Ty, DAG, ABI.IsN32() || ABI.IsN64()); 1901 } 1902 1903 SDValue MipsTargetLowering:: 1904 lowerConstantPool(SDValue Op, SelectionDAG &DAG) const 1905 { 1906 ConstantPoolSDNode *N = cast<ConstantPoolSDNode>(Op); 1907 EVT Ty = Op.getValueType(); 1908 1909 if (!isPositionIndependent() && !ABI.IsN64()) { 1910 const MipsTargetObjectFile *TLOF = 1911 static_cast<const MipsTargetObjectFile *>( 1912 getTargetMachine().getObjFileLowering()); 1913 1914 if (TLOF->IsConstantInSmallSection(DAG.getDataLayout(), N->getConstVal(), 1915 getTargetMachine())) 1916 // %gp_rel relocation 1917 return getAddrGPRel(N, SDLoc(N), Ty, DAG); 1918 1919 return getAddrNonPIC(N, SDLoc(N), Ty, DAG); 1920 } 1921 1922 return getAddrLocal(N, SDLoc(N), Ty, DAG, ABI.IsN32() || ABI.IsN64()); 1923 } 1924 1925 SDValue MipsTargetLowering::lowerVASTART(SDValue Op, SelectionDAG &DAG) const { 1926 MachineFunction &MF = DAG.getMachineFunction(); 1927 MipsFunctionInfo *FuncInfo = MF.getInfo<MipsFunctionInfo>(); 1928 1929 SDLoc DL(Op); 1930 SDValue FI = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), 1931 getPointerTy(MF.getDataLayout())); 1932 1933 // vastart just stores the address of the VarArgsFrameIndex slot into the 1934 // memory location argument. 1935 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue(); 1936 return DAG.getStore(Op.getOperand(0), DL, FI, Op.getOperand(1), 1937 MachinePointerInfo(SV)); 1938 } 1939 1940 SDValue MipsTargetLowering::lowerVAARG(SDValue Op, SelectionDAG &DAG) const { 1941 SDNode *Node = Op.getNode(); 1942 EVT VT = Node->getValueType(0); 1943 SDValue Chain = Node->getOperand(0); 1944 SDValue VAListPtr = Node->getOperand(1); 1945 unsigned Align = Node->getConstantOperandVal(3); 1946 const Value *SV = cast<SrcValueSDNode>(Node->getOperand(2))->getValue(); 1947 SDLoc DL(Node); 1948 unsigned ArgSlotSizeInBytes = (ABI.IsN32() || ABI.IsN64()) ? 8 : 4; 1949 1950 SDValue VAListLoad = DAG.getLoad(getPointerTy(DAG.getDataLayout()), DL, Chain, 1951 VAListPtr, MachinePointerInfo(SV)); 1952 SDValue VAList = VAListLoad; 1953 1954 // Re-align the pointer if necessary. 1955 // It should only ever be necessary for 64-bit types on O32 since the minimum 1956 // argument alignment is the same as the maximum type alignment for N32/N64. 1957 // 1958 // FIXME: We currently align too often. The code generator doesn't notice 1959 // when the pointer is still aligned from the last va_arg (or pair of 1960 // va_args for the i64 on O32 case). 1961 if (Align > getMinStackArgumentAlignment()) { 1962 assert(((Align & (Align-1)) == 0) && "Expected Align to be a power of 2"); 1963 1964 VAList = DAG.getNode(ISD::ADD, DL, VAList.getValueType(), VAList, 1965 DAG.getConstant(Align - 1, DL, VAList.getValueType())); 1966 1967 VAList = DAG.getNode(ISD::AND, DL, VAList.getValueType(), VAList, 1968 DAG.getConstant(-(int64_t)Align, DL, 1969 VAList.getValueType())); 1970 } 1971 1972 // Increment the pointer, VAList, to the next vaarg. 1973 auto &TD = DAG.getDataLayout(); 1974 unsigned ArgSizeInBytes = 1975 TD.getTypeAllocSize(VT.getTypeForEVT(*DAG.getContext())); 1976 SDValue Tmp3 = 1977 DAG.getNode(ISD::ADD, DL, VAList.getValueType(), VAList, 1978 DAG.getConstant(alignTo(ArgSizeInBytes, ArgSlotSizeInBytes), 1979 DL, VAList.getValueType())); 1980 // Store the incremented VAList to the legalized pointer 1981 Chain = DAG.getStore(VAListLoad.getValue(1), DL, Tmp3, VAListPtr, 1982 MachinePointerInfo(SV)); 1983 1984 // In big-endian mode we must adjust the pointer when the load size is smaller 1985 // than the argument slot size. We must also reduce the known alignment to 1986 // match. For example in the N64 ABI, we must add 4 bytes to the offset to get 1987 // the correct half of the slot, and reduce the alignment from 8 (slot 1988 // alignment) down to 4 (type alignment). 1989 if (!Subtarget.isLittle() && ArgSizeInBytes < ArgSlotSizeInBytes) { 1990 unsigned Adjustment = ArgSlotSizeInBytes - ArgSizeInBytes; 1991 VAList = DAG.getNode(ISD::ADD, DL, VAListPtr.getValueType(), VAList, 1992 DAG.getIntPtrConstant(Adjustment, DL)); 1993 } 1994 // Load the actual argument out of the pointer VAList 1995 return DAG.getLoad(VT, DL, Chain, VAList, MachinePointerInfo()); 1996 } 1997 1998 static SDValue lowerFCOPYSIGN32(SDValue Op, SelectionDAG &DAG, 1999 bool HasExtractInsert) { 2000 EVT TyX = Op.getOperand(0).getValueType(); 2001 EVT TyY = Op.getOperand(1).getValueType(); 2002 SDLoc DL(Op); 2003 SDValue Const1 = DAG.getConstant(1, DL, MVT::i32); 2004 SDValue Const31 = DAG.getConstant(31, DL, MVT::i32); 2005 SDValue Res; 2006 2007 // If operand is of type f64, extract the upper 32-bit. Otherwise, bitcast it 2008 // to i32. 2009 SDValue X = (TyX == MVT::f32) ? 2010 DAG.getNode(ISD::BITCAST, DL, MVT::i32, Op.getOperand(0)) : 2011 DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32, Op.getOperand(0), 2012 Const1); 2013 SDValue Y = (TyY == MVT::f32) ? 2014 DAG.getNode(ISD::BITCAST, DL, MVT::i32, Op.getOperand(1)) : 2015 DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32, Op.getOperand(1), 2016 Const1); 2017 2018 if (HasExtractInsert) { 2019 // ext E, Y, 31, 1 ; extract bit31 of Y 2020 // ins X, E, 31, 1 ; insert extracted bit at bit31 of X 2021 SDValue E = DAG.getNode(MipsISD::Ext, DL, MVT::i32, Y, Const31, Const1); 2022 Res = DAG.getNode(MipsISD::Ins, DL, MVT::i32, E, Const31, Const1, X); 2023 } else { 2024 // sll SllX, X, 1 2025 // srl SrlX, SllX, 1 2026 // srl SrlY, Y, 31 2027 // sll SllY, SrlX, 31 2028 // or Or, SrlX, SllY 2029 SDValue SllX = DAG.getNode(ISD::SHL, DL, MVT::i32, X, Const1); 2030 SDValue SrlX = DAG.getNode(ISD::SRL, DL, MVT::i32, SllX, Const1); 2031 SDValue SrlY = DAG.getNode(ISD::SRL, DL, MVT::i32, Y, Const31); 2032 SDValue SllY = DAG.getNode(ISD::SHL, DL, MVT::i32, SrlY, Const31); 2033 Res = DAG.getNode(ISD::OR, DL, MVT::i32, SrlX, SllY); 2034 } 2035 2036 if (TyX == MVT::f32) 2037 return DAG.getNode(ISD::BITCAST, DL, Op.getOperand(0).getValueType(), Res); 2038 2039 SDValue LowX = DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32, 2040 Op.getOperand(0), 2041 DAG.getConstant(0, DL, MVT::i32)); 2042 return DAG.getNode(MipsISD::BuildPairF64, DL, MVT::f64, LowX, Res); 2043 } 2044 2045 static SDValue lowerFCOPYSIGN64(SDValue Op, SelectionDAG &DAG, 2046 bool HasExtractInsert) { 2047 unsigned WidthX = Op.getOperand(0).getValueSizeInBits(); 2048 unsigned WidthY = Op.getOperand(1).getValueSizeInBits(); 2049 EVT TyX = MVT::getIntegerVT(WidthX), TyY = MVT::getIntegerVT(WidthY); 2050 SDLoc DL(Op); 2051 SDValue Const1 = DAG.getConstant(1, DL, MVT::i32); 2052 2053 // Bitcast to integer nodes. 2054 SDValue X = DAG.getNode(ISD::BITCAST, DL, TyX, Op.getOperand(0)); 2055 SDValue Y = DAG.getNode(ISD::BITCAST, DL, TyY, Op.getOperand(1)); 2056 2057 if (HasExtractInsert) { 2058 // ext E, Y, width(Y) - 1, 1 ; extract bit width(Y)-1 of Y 2059 // ins X, E, width(X) - 1, 1 ; insert extracted bit at bit width(X)-1 of X 2060 SDValue E = DAG.getNode(MipsISD::Ext, DL, TyY, Y, 2061 DAG.getConstant(WidthY - 1, DL, MVT::i32), Const1); 2062 2063 if (WidthX > WidthY) 2064 E = DAG.getNode(ISD::ZERO_EXTEND, DL, TyX, E); 2065 else if (WidthY > WidthX) 2066 E = DAG.getNode(ISD::TRUNCATE, DL, TyX, E); 2067 2068 SDValue I = DAG.getNode(MipsISD::Ins, DL, TyX, E, 2069 DAG.getConstant(WidthX - 1, DL, MVT::i32), Const1, 2070 X); 2071 return DAG.getNode(ISD::BITCAST, DL, Op.getOperand(0).getValueType(), I); 2072 } 2073 2074 // (d)sll SllX, X, 1 2075 // (d)srl SrlX, SllX, 1 2076 // (d)srl SrlY, Y, width(Y)-1 2077 // (d)sll SllY, SrlX, width(Y)-1 2078 // or Or, SrlX, SllY 2079 SDValue SllX = DAG.getNode(ISD::SHL, DL, TyX, X, Const1); 2080 SDValue SrlX = DAG.getNode(ISD::SRL, DL, TyX, SllX, Const1); 2081 SDValue SrlY = DAG.getNode(ISD::SRL, DL, TyY, Y, 2082 DAG.getConstant(WidthY - 1, DL, MVT::i32)); 2083 2084 if (WidthX > WidthY) 2085 SrlY = DAG.getNode(ISD::ZERO_EXTEND, DL, TyX, SrlY); 2086 else if (WidthY > WidthX) 2087 SrlY = DAG.getNode(ISD::TRUNCATE, DL, TyX, SrlY); 2088 2089 SDValue SllY = DAG.getNode(ISD::SHL, DL, TyX, SrlY, 2090 DAG.getConstant(WidthX - 1, DL, MVT::i32)); 2091 SDValue Or = DAG.getNode(ISD::OR, DL, TyX, SrlX, SllY); 2092 return DAG.getNode(ISD::BITCAST, DL, Op.getOperand(0).getValueType(), Or); 2093 } 2094 2095 SDValue 2096 MipsTargetLowering::lowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const { 2097 if (Subtarget.isGP64bit()) 2098 return lowerFCOPYSIGN64(Op, DAG, Subtarget.hasExtractInsert()); 2099 2100 return lowerFCOPYSIGN32(Op, DAG, Subtarget.hasExtractInsert()); 2101 } 2102 2103 SDValue MipsTargetLowering:: 2104 lowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const { 2105 // check the depth 2106 assert((cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue() == 0) && 2107 "Frame address can only be determined for current frame."); 2108 2109 MachineFrameInfo &MFI = DAG.getMachineFunction().getFrameInfo(); 2110 MFI.setFrameAddressIsTaken(true); 2111 EVT VT = Op.getValueType(); 2112 SDLoc DL(Op); 2113 SDValue FrameAddr = DAG.getCopyFromReg( 2114 DAG.getEntryNode(), DL, ABI.IsN64() ? Mips::FP_64 : Mips::FP, VT); 2115 return FrameAddr; 2116 } 2117 2118 SDValue MipsTargetLowering::lowerRETURNADDR(SDValue Op, 2119 SelectionDAG &DAG) const { 2120 if (verifyReturnAddressArgumentIsConstant(Op, DAG)) 2121 return SDValue(); 2122 2123 // check the depth 2124 assert((cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue() == 0) && 2125 "Return address can be determined only for current frame."); 2126 2127 MachineFunction &MF = DAG.getMachineFunction(); 2128 MachineFrameInfo &MFI = MF.getFrameInfo(); 2129 MVT VT = Op.getSimpleValueType(); 2130 unsigned RA = ABI.IsN64() ? Mips::RA_64 : Mips::RA; 2131 MFI.setReturnAddressIsTaken(true); 2132 2133 // Return RA, which contains the return address. Mark it an implicit live-in. 2134 unsigned Reg = MF.addLiveIn(RA, getRegClassFor(VT)); 2135 return DAG.getCopyFromReg(DAG.getEntryNode(), SDLoc(Op), Reg, VT); 2136 } 2137 2138 // An EH_RETURN is the result of lowering llvm.eh.return which in turn is 2139 // generated from __builtin_eh_return (offset, handler) 2140 // The effect of this is to adjust the stack pointer by "offset" 2141 // and then branch to "handler". 2142 SDValue MipsTargetLowering::lowerEH_RETURN(SDValue Op, SelectionDAG &DAG) 2143 const { 2144 MachineFunction &MF = DAG.getMachineFunction(); 2145 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>(); 2146 2147 MipsFI->setCallsEhReturn(); 2148 SDValue Chain = Op.getOperand(0); 2149 SDValue Offset = Op.getOperand(1); 2150 SDValue Handler = Op.getOperand(2); 2151 SDLoc DL(Op); 2152 EVT Ty = ABI.IsN64() ? MVT::i64 : MVT::i32; 2153 2154 // Store stack offset in V1, store jump target in V0. Glue CopyToReg and 2155 // EH_RETURN nodes, so that instructions are emitted back-to-back. 2156 unsigned OffsetReg = ABI.IsN64() ? Mips::V1_64 : Mips::V1; 2157 unsigned AddrReg = ABI.IsN64() ? Mips::V0_64 : Mips::V0; 2158 Chain = DAG.getCopyToReg(Chain, DL, OffsetReg, Offset, SDValue()); 2159 Chain = DAG.getCopyToReg(Chain, DL, AddrReg, Handler, Chain.getValue(1)); 2160 return DAG.getNode(MipsISD::EH_RETURN, DL, MVT::Other, Chain, 2161 DAG.getRegister(OffsetReg, Ty), 2162 DAG.getRegister(AddrReg, getPointerTy(MF.getDataLayout())), 2163 Chain.getValue(1)); 2164 } 2165 2166 SDValue MipsTargetLowering::lowerATOMIC_FENCE(SDValue Op, 2167 SelectionDAG &DAG) const { 2168 // FIXME: Need pseudo-fence for 'singlethread' fences 2169 // FIXME: Set SType for weaker fences where supported/appropriate. 2170 unsigned SType = 0; 2171 SDLoc DL(Op); 2172 return DAG.getNode(MipsISD::Sync, DL, MVT::Other, Op.getOperand(0), 2173 DAG.getConstant(SType, DL, MVT::i32)); 2174 } 2175 2176 SDValue MipsTargetLowering::lowerShiftLeftParts(SDValue Op, 2177 SelectionDAG &DAG) const { 2178 SDLoc DL(Op); 2179 MVT VT = Subtarget.isGP64bit() ? MVT::i64 : MVT::i32; 2180 2181 SDValue Lo = Op.getOperand(0), Hi = Op.getOperand(1); 2182 SDValue Shamt = Op.getOperand(2); 2183 // if shamt < (VT.bits): 2184 // lo = (shl lo, shamt) 2185 // hi = (or (shl hi, shamt) (srl (srl lo, 1), ~shamt)) 2186 // else: 2187 // lo = 0 2188 // hi = (shl lo, shamt[4:0]) 2189 SDValue Not = DAG.getNode(ISD::XOR, DL, MVT::i32, Shamt, 2190 DAG.getConstant(-1, DL, MVT::i32)); 2191 SDValue ShiftRight1Lo = DAG.getNode(ISD::SRL, DL, VT, Lo, 2192 DAG.getConstant(1, DL, VT)); 2193 SDValue ShiftRightLo = DAG.getNode(ISD::SRL, DL, VT, ShiftRight1Lo, Not); 2194 SDValue ShiftLeftHi = DAG.getNode(ISD::SHL, DL, VT, Hi, Shamt); 2195 SDValue Or = DAG.getNode(ISD::OR, DL, VT, ShiftLeftHi, ShiftRightLo); 2196 SDValue ShiftLeftLo = DAG.getNode(ISD::SHL, DL, VT, Lo, Shamt); 2197 SDValue Cond = DAG.getNode(ISD::AND, DL, MVT::i32, Shamt, 2198 DAG.getConstant(VT.getSizeInBits(), DL, MVT::i32)); 2199 Lo = DAG.getNode(ISD::SELECT, DL, VT, Cond, 2200 DAG.getConstant(0, DL, VT), ShiftLeftLo); 2201 Hi = DAG.getNode(ISD::SELECT, DL, VT, Cond, ShiftLeftLo, Or); 2202 2203 SDValue Ops[2] = {Lo, Hi}; 2204 return DAG.getMergeValues(Ops, DL); 2205 } 2206 2207 SDValue MipsTargetLowering::lowerShiftRightParts(SDValue Op, SelectionDAG &DAG, 2208 bool IsSRA) const { 2209 SDLoc DL(Op); 2210 SDValue Lo = Op.getOperand(0), Hi = Op.getOperand(1); 2211 SDValue Shamt = Op.getOperand(2); 2212 MVT VT = Subtarget.isGP64bit() ? MVT::i64 : MVT::i32; 2213 2214 // if shamt < (VT.bits): 2215 // lo = (or (shl (shl hi, 1), ~shamt) (srl lo, shamt)) 2216 // if isSRA: 2217 // hi = (sra hi, shamt) 2218 // else: 2219 // hi = (srl hi, shamt) 2220 // else: 2221 // if isSRA: 2222 // lo = (sra hi, shamt[4:0]) 2223 // hi = (sra hi, 31) 2224 // else: 2225 // lo = (srl hi, shamt[4:0]) 2226 // hi = 0 2227 SDValue Not = DAG.getNode(ISD::XOR, DL, MVT::i32, Shamt, 2228 DAG.getConstant(-1, DL, MVT::i32)); 2229 SDValue ShiftLeft1Hi = DAG.getNode(ISD::SHL, DL, VT, Hi, 2230 DAG.getConstant(1, DL, VT)); 2231 SDValue ShiftLeftHi = DAG.getNode(ISD::SHL, DL, VT, ShiftLeft1Hi, Not); 2232 SDValue ShiftRightLo = DAG.getNode(ISD::SRL, DL, VT, Lo, Shamt); 2233 SDValue Or = DAG.getNode(ISD::OR, DL, VT, ShiftLeftHi, ShiftRightLo); 2234 SDValue ShiftRightHi = DAG.getNode(IsSRA ? ISD::SRA : ISD::SRL, 2235 DL, VT, Hi, Shamt); 2236 SDValue Cond = DAG.getNode(ISD::AND, DL, MVT::i32, Shamt, 2237 DAG.getConstant(VT.getSizeInBits(), DL, MVT::i32)); 2238 SDValue Ext = DAG.getNode(ISD::SRA, DL, VT, Hi, 2239 DAG.getConstant(VT.getSizeInBits() - 1, DL, VT)); 2240 Lo = DAG.getNode(ISD::SELECT, DL, VT, Cond, ShiftRightHi, Or); 2241 Hi = DAG.getNode(ISD::SELECT, DL, VT, Cond, 2242 IsSRA ? Ext : DAG.getConstant(0, DL, VT), ShiftRightHi); 2243 2244 SDValue Ops[2] = {Lo, Hi}; 2245 return DAG.getMergeValues(Ops, DL); 2246 } 2247 2248 static SDValue createLoadLR(unsigned Opc, SelectionDAG &DAG, LoadSDNode *LD, 2249 SDValue Chain, SDValue Src, unsigned Offset) { 2250 SDValue Ptr = LD->getBasePtr(); 2251 EVT VT = LD->getValueType(0), MemVT = LD->getMemoryVT(); 2252 EVT BasePtrVT = Ptr.getValueType(); 2253 SDLoc DL(LD); 2254 SDVTList VTList = DAG.getVTList(VT, MVT::Other); 2255 2256 if (Offset) 2257 Ptr = DAG.getNode(ISD::ADD, DL, BasePtrVT, Ptr, 2258 DAG.getConstant(Offset, DL, BasePtrVT)); 2259 2260 SDValue Ops[] = { Chain, Ptr, Src }; 2261 return DAG.getMemIntrinsicNode(Opc, DL, VTList, Ops, MemVT, 2262 LD->getMemOperand()); 2263 } 2264 2265 // Expand an unaligned 32 or 64-bit integer load node. 2266 SDValue MipsTargetLowering::lowerLOAD(SDValue Op, SelectionDAG &DAG) const { 2267 LoadSDNode *LD = cast<LoadSDNode>(Op); 2268 EVT MemVT = LD->getMemoryVT(); 2269 2270 if (Subtarget.systemSupportsUnalignedAccess()) 2271 return Op; 2272 2273 // Return if load is aligned or if MemVT is neither i32 nor i64. 2274 if ((LD->getAlignment() >= MemVT.getSizeInBits() / 8) || 2275 ((MemVT != MVT::i32) && (MemVT != MVT::i64))) 2276 return SDValue(); 2277 2278 bool IsLittle = Subtarget.isLittle(); 2279 EVT VT = Op.getValueType(); 2280 ISD::LoadExtType ExtType = LD->getExtensionType(); 2281 SDValue Chain = LD->getChain(), Undef = DAG.getUNDEF(VT); 2282 2283 assert((VT == MVT::i32) || (VT == MVT::i64)); 2284 2285 // Expand 2286 // (set dst, (i64 (load baseptr))) 2287 // to 2288 // (set tmp, (ldl (add baseptr, 7), undef)) 2289 // (set dst, (ldr baseptr, tmp)) 2290 if ((VT == MVT::i64) && (ExtType == ISD::NON_EXTLOAD)) { 2291 SDValue LDL = createLoadLR(MipsISD::LDL, DAG, LD, Chain, Undef, 2292 IsLittle ? 7 : 0); 2293 return createLoadLR(MipsISD::LDR, DAG, LD, LDL.getValue(1), LDL, 2294 IsLittle ? 0 : 7); 2295 } 2296 2297 SDValue LWL = createLoadLR(MipsISD::LWL, DAG, LD, Chain, Undef, 2298 IsLittle ? 3 : 0); 2299 SDValue LWR = createLoadLR(MipsISD::LWR, DAG, LD, LWL.getValue(1), LWL, 2300 IsLittle ? 0 : 3); 2301 2302 // Expand 2303 // (set dst, (i32 (load baseptr))) or 2304 // (set dst, (i64 (sextload baseptr))) or 2305 // (set dst, (i64 (extload baseptr))) 2306 // to 2307 // (set tmp, (lwl (add baseptr, 3), undef)) 2308 // (set dst, (lwr baseptr, tmp)) 2309 if ((VT == MVT::i32) || (ExtType == ISD::SEXTLOAD) || 2310 (ExtType == ISD::EXTLOAD)) 2311 return LWR; 2312 2313 assert((VT == MVT::i64) && (ExtType == ISD::ZEXTLOAD)); 2314 2315 // Expand 2316 // (set dst, (i64 (zextload baseptr))) 2317 // to 2318 // (set tmp0, (lwl (add baseptr, 3), undef)) 2319 // (set tmp1, (lwr baseptr, tmp0)) 2320 // (set tmp2, (shl tmp1, 32)) 2321 // (set dst, (srl tmp2, 32)) 2322 SDLoc DL(LD); 2323 SDValue Const32 = DAG.getConstant(32, DL, MVT::i32); 2324 SDValue SLL = DAG.getNode(ISD::SHL, DL, MVT::i64, LWR, Const32); 2325 SDValue SRL = DAG.getNode(ISD::SRL, DL, MVT::i64, SLL, Const32); 2326 SDValue Ops[] = { SRL, LWR.getValue(1) }; 2327 return DAG.getMergeValues(Ops, DL); 2328 } 2329 2330 static SDValue createStoreLR(unsigned Opc, SelectionDAG &DAG, StoreSDNode *SD, 2331 SDValue Chain, unsigned Offset) { 2332 SDValue Ptr = SD->getBasePtr(), Value = SD->getValue(); 2333 EVT MemVT = SD->getMemoryVT(), BasePtrVT = Ptr.getValueType(); 2334 SDLoc DL(SD); 2335 SDVTList VTList = DAG.getVTList(MVT::Other); 2336 2337 if (Offset) 2338 Ptr = DAG.getNode(ISD::ADD, DL, BasePtrVT, Ptr, 2339 DAG.getConstant(Offset, DL, BasePtrVT)); 2340 2341 SDValue Ops[] = { Chain, Value, Ptr }; 2342 return DAG.getMemIntrinsicNode(Opc, DL, VTList, Ops, MemVT, 2343 SD->getMemOperand()); 2344 } 2345 2346 // Expand an unaligned 32 or 64-bit integer store node. 2347 static SDValue lowerUnalignedIntStore(StoreSDNode *SD, SelectionDAG &DAG, 2348 bool IsLittle) { 2349 SDValue Value = SD->getValue(), Chain = SD->getChain(); 2350 EVT VT = Value.getValueType(); 2351 2352 // Expand 2353 // (store val, baseptr) or 2354 // (truncstore val, baseptr) 2355 // to 2356 // (swl val, (add baseptr, 3)) 2357 // (swr val, baseptr) 2358 if ((VT == MVT::i32) || SD->isTruncatingStore()) { 2359 SDValue SWL = createStoreLR(MipsISD::SWL, DAG, SD, Chain, 2360 IsLittle ? 3 : 0); 2361 return createStoreLR(MipsISD::SWR, DAG, SD, SWL, IsLittle ? 0 : 3); 2362 } 2363 2364 assert(VT == MVT::i64); 2365 2366 // Expand 2367 // (store val, baseptr) 2368 // to 2369 // (sdl val, (add baseptr, 7)) 2370 // (sdr val, baseptr) 2371 SDValue SDL = createStoreLR(MipsISD::SDL, DAG, SD, Chain, IsLittle ? 7 : 0); 2372 return createStoreLR(MipsISD::SDR, DAG, SD, SDL, IsLittle ? 0 : 7); 2373 } 2374 2375 // Lower (store (fp_to_sint $fp) $ptr) to (store (TruncIntFP $fp), $ptr). 2376 static SDValue lowerFP_TO_SINT_STORE(StoreSDNode *SD, SelectionDAG &DAG) { 2377 SDValue Val = SD->getValue(); 2378 2379 if (Val.getOpcode() != ISD::FP_TO_SINT) 2380 return SDValue(); 2381 2382 EVT FPTy = EVT::getFloatingPointVT(Val.getValueSizeInBits()); 2383 SDValue Tr = DAG.getNode(MipsISD::TruncIntFP, SDLoc(Val), FPTy, 2384 Val.getOperand(0)); 2385 return DAG.getStore(SD->getChain(), SDLoc(SD), Tr, SD->getBasePtr(), 2386 SD->getPointerInfo(), SD->getAlignment(), 2387 SD->getMemOperand()->getFlags()); 2388 } 2389 2390 SDValue MipsTargetLowering::lowerSTORE(SDValue Op, SelectionDAG &DAG) const { 2391 StoreSDNode *SD = cast<StoreSDNode>(Op); 2392 EVT MemVT = SD->getMemoryVT(); 2393 2394 // Lower unaligned integer stores. 2395 if (!Subtarget.systemSupportsUnalignedAccess() && 2396 (SD->getAlignment() < MemVT.getSizeInBits() / 8) && 2397 ((MemVT == MVT::i32) || (MemVT == MVT::i64))) 2398 return lowerUnalignedIntStore(SD, DAG, Subtarget.isLittle()); 2399 2400 return lowerFP_TO_SINT_STORE(SD, DAG); 2401 } 2402 2403 SDValue MipsTargetLowering::lowerEH_DWARF_CFA(SDValue Op, 2404 SelectionDAG &DAG) const { 2405 2406 // Return a fixed StackObject with offset 0 which points to the old stack 2407 // pointer. 2408 MachineFrameInfo &MFI = DAG.getMachineFunction().getFrameInfo(); 2409 EVT ValTy = Op->getValueType(0); 2410 int FI = MFI.CreateFixedObject(Op.getValueSizeInBits() / 8, 0, false); 2411 return DAG.getFrameIndex(FI, ValTy); 2412 } 2413 2414 SDValue MipsTargetLowering::lowerFP_TO_SINT(SDValue Op, 2415 SelectionDAG &DAG) const { 2416 EVT FPTy = EVT::getFloatingPointVT(Op.getValueSizeInBits()); 2417 SDValue Trunc = DAG.getNode(MipsISD::TruncIntFP, SDLoc(Op), FPTy, 2418 Op.getOperand(0)); 2419 return DAG.getNode(ISD::BITCAST, SDLoc(Op), Op.getValueType(), Trunc); 2420 } 2421 2422 //===----------------------------------------------------------------------===// 2423 // Calling Convention Implementation 2424 //===----------------------------------------------------------------------===// 2425 2426 //===----------------------------------------------------------------------===// 2427 // TODO: Implement a generic logic using tblgen that can support this. 2428 // Mips O32 ABI rules: 2429 // --- 2430 // i32 - Passed in A0, A1, A2, A3 and stack 2431 // f32 - Only passed in f32 registers if no int reg has been used yet to hold 2432 // an argument. Otherwise, passed in A1, A2, A3 and stack. 2433 // f64 - Only passed in two aliased f32 registers if no int reg has been used 2434 // yet to hold an argument. Otherwise, use A2, A3 and stack. If A1 is 2435 // not used, it must be shadowed. If only A3 is available, shadow it and 2436 // go to stack. 2437 // 2438 // For vararg functions, all arguments are passed in A0, A1, A2, A3 and stack. 2439 //===----------------------------------------------------------------------===// 2440 2441 static bool CC_MipsO32(unsigned ValNo, MVT ValVT, MVT LocVT, 2442 CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, 2443 CCState &State, ArrayRef<MCPhysReg> F64Regs) { 2444 const MipsSubtarget &Subtarget = static_cast<const MipsSubtarget &>( 2445 State.getMachineFunction().getSubtarget()); 2446 2447 static const MCPhysReg IntRegs[] = { Mips::A0, Mips::A1, Mips::A2, Mips::A3 }; 2448 static const MCPhysReg F32Regs[] = { Mips::F12, Mips::F14 }; 2449 2450 // Do not process byval args here. 2451 if (ArgFlags.isByVal()) 2452 return true; 2453 2454 // Promote i8 and i16 2455 if (ArgFlags.isInReg() && !Subtarget.isLittle()) { 2456 if (LocVT == MVT::i8 || LocVT == MVT::i16 || LocVT == MVT::i32) { 2457 LocVT = MVT::i32; 2458 if (ArgFlags.isSExt()) 2459 LocInfo = CCValAssign::SExtUpper; 2460 else if (ArgFlags.isZExt()) 2461 LocInfo = CCValAssign::ZExtUpper; 2462 else 2463 LocInfo = CCValAssign::AExtUpper; 2464 } 2465 } 2466 2467 // Promote i8 and i16 2468 if (LocVT == MVT::i8 || LocVT == MVT::i16) { 2469 LocVT = MVT::i32; 2470 if (ArgFlags.isSExt()) 2471 LocInfo = CCValAssign::SExt; 2472 else if (ArgFlags.isZExt()) 2473 LocInfo = CCValAssign::ZExt; 2474 else 2475 LocInfo = CCValAssign::AExt; 2476 } 2477 2478 unsigned Reg; 2479 2480 // f32 and f64 are allocated in A0, A1, A2, A3 when either of the following 2481 // is true: function is vararg, argument is 3rd or higher, there is previous 2482 // argument which is not f32 or f64. 2483 bool AllocateFloatsInIntReg = State.isVarArg() || ValNo > 1 || 2484 State.getFirstUnallocated(F32Regs) != ValNo; 2485 unsigned OrigAlign = ArgFlags.getOrigAlign(); 2486 bool isI64 = (ValVT == MVT::i32 && OrigAlign == 8); 2487 2488 if (ValVT == MVT::i32 || (ValVT == MVT::f32 && AllocateFloatsInIntReg)) { 2489 Reg = State.AllocateReg(IntRegs); 2490 // If this is the first part of an i64 arg, 2491 // the allocated register must be either A0 or A2. 2492 if (isI64 && (Reg == Mips::A1 || Reg == Mips::A3)) 2493 Reg = State.AllocateReg(IntRegs); 2494 LocVT = MVT::i32; 2495 } else if (ValVT == MVT::f64 && AllocateFloatsInIntReg) { 2496 // Allocate int register and shadow next int register. If first 2497 // available register is Mips::A1 or Mips::A3, shadow it too. 2498 Reg = State.AllocateReg(IntRegs); 2499 if (Reg == Mips::A1 || Reg == Mips::A3) 2500 Reg = State.AllocateReg(IntRegs); 2501 State.AllocateReg(IntRegs); 2502 LocVT = MVT::i32; 2503 } else if (ValVT.isFloatingPoint() && !AllocateFloatsInIntReg) { 2504 // we are guaranteed to find an available float register 2505 if (ValVT == MVT::f32) { 2506 Reg = State.AllocateReg(F32Regs); 2507 // Shadow int register 2508 State.AllocateReg(IntRegs); 2509 } else { 2510 Reg = State.AllocateReg(F64Regs); 2511 // Shadow int registers 2512 unsigned Reg2 = State.AllocateReg(IntRegs); 2513 if (Reg2 == Mips::A1 || Reg2 == Mips::A3) 2514 State.AllocateReg(IntRegs); 2515 State.AllocateReg(IntRegs); 2516 } 2517 } else 2518 llvm_unreachable("Cannot handle this ValVT."); 2519 2520 if (!Reg) { 2521 unsigned Offset = State.AllocateStack(ValVT.getSizeInBits() >> 3, 2522 OrigAlign); 2523 State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo)); 2524 } else 2525 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); 2526 2527 return false; 2528 } 2529 2530 static bool CC_MipsO32_FP32(unsigned ValNo, MVT ValVT, 2531 MVT LocVT, CCValAssign::LocInfo LocInfo, 2532 ISD::ArgFlagsTy ArgFlags, CCState &State) { 2533 static const MCPhysReg F64Regs[] = { Mips::D6, Mips::D7 }; 2534 2535 return CC_MipsO32(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State, F64Regs); 2536 } 2537 2538 static bool CC_MipsO32_FP64(unsigned ValNo, MVT ValVT, 2539 MVT LocVT, CCValAssign::LocInfo LocInfo, 2540 ISD::ArgFlagsTy ArgFlags, CCState &State) { 2541 static const MCPhysReg F64Regs[] = { Mips::D12_64, Mips::D14_64 }; 2542 2543 return CC_MipsO32(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State, F64Regs); 2544 } 2545 2546 static bool CC_MipsO32(unsigned ValNo, MVT ValVT, MVT LocVT, 2547 CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, 2548 CCState &State) LLVM_ATTRIBUTE_UNUSED; 2549 2550 #include "MipsGenCallingConv.inc" 2551 2552 //===----------------------------------------------------------------------===// 2553 // Call Calling Convention Implementation 2554 //===----------------------------------------------------------------------===// 2555 2556 // Return next O32 integer argument register. 2557 static unsigned getNextIntArgReg(unsigned Reg) { 2558 assert((Reg == Mips::A0) || (Reg == Mips::A2)); 2559 return (Reg == Mips::A0) ? Mips::A1 : Mips::A3; 2560 } 2561 2562 SDValue MipsTargetLowering::passArgOnStack(SDValue StackPtr, unsigned Offset, 2563 SDValue Chain, SDValue Arg, 2564 const SDLoc &DL, bool IsTailCall, 2565 SelectionDAG &DAG) const { 2566 if (!IsTailCall) { 2567 SDValue PtrOff = 2568 DAG.getNode(ISD::ADD, DL, getPointerTy(DAG.getDataLayout()), StackPtr, 2569 DAG.getIntPtrConstant(Offset, DL)); 2570 return DAG.getStore(Chain, DL, Arg, PtrOff, MachinePointerInfo()); 2571 } 2572 2573 MachineFrameInfo &MFI = DAG.getMachineFunction().getFrameInfo(); 2574 int FI = MFI.CreateFixedObject(Arg.getValueSizeInBits() / 8, Offset, false); 2575 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy(DAG.getDataLayout())); 2576 return DAG.getStore(Chain, DL, Arg, FIN, MachinePointerInfo(), 2577 /* Alignment = */ 0, MachineMemOperand::MOVolatile); 2578 } 2579 2580 void MipsTargetLowering:: 2581 getOpndList(SmallVectorImpl<SDValue> &Ops, 2582 std::deque< std::pair<unsigned, SDValue> > &RegsToPass, 2583 bool IsPICCall, bool GlobalOrExternal, bool InternalLinkage, 2584 bool IsCallReloc, CallLoweringInfo &CLI, SDValue Callee, 2585 SDValue Chain) const { 2586 // Insert node "GP copy globalreg" before call to function. 2587 // 2588 // R_MIPS_CALL* operators (emitted when non-internal functions are called 2589 // in PIC mode) allow symbols to be resolved via lazy binding. 2590 // The lazy binding stub requires GP to point to the GOT. 2591 // Note that we don't need GP to point to the GOT for indirect calls 2592 // (when R_MIPS_CALL* is not used for the call) because Mips linker generates 2593 // lazy binding stub for a function only when R_MIPS_CALL* are the only relocs 2594 // used for the function (that is, Mips linker doesn't generate lazy binding 2595 // stub for a function whose address is taken in the program). 2596 if (IsPICCall && !InternalLinkage && IsCallReloc) { 2597 unsigned GPReg = ABI.IsN64() ? Mips::GP_64 : Mips::GP; 2598 EVT Ty = ABI.IsN64() ? MVT::i64 : MVT::i32; 2599 RegsToPass.push_back(std::make_pair(GPReg, getGlobalReg(CLI.DAG, Ty))); 2600 } 2601 2602 // Build a sequence of copy-to-reg nodes chained together with token 2603 // chain and flag operands which copy the outgoing args into registers. 2604 // The InFlag in necessary since all emitted instructions must be 2605 // stuck together. 2606 SDValue InFlag; 2607 2608 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) { 2609 Chain = CLI.DAG.getCopyToReg(Chain, CLI.DL, RegsToPass[i].first, 2610 RegsToPass[i].second, InFlag); 2611 InFlag = Chain.getValue(1); 2612 } 2613 2614 // Add argument registers to the end of the list so that they are 2615 // known live into the call. 2616 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) 2617 Ops.push_back(CLI.DAG.getRegister(RegsToPass[i].first, 2618 RegsToPass[i].second.getValueType())); 2619 2620 // Add a register mask operand representing the call-preserved registers. 2621 const TargetRegisterInfo *TRI = Subtarget.getRegisterInfo(); 2622 const uint32_t *Mask = 2623 TRI->getCallPreservedMask(CLI.DAG.getMachineFunction(), CLI.CallConv); 2624 assert(Mask && "Missing call preserved mask for calling convention"); 2625 if (Subtarget.inMips16HardFloat()) { 2626 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(CLI.Callee)) { 2627 llvm::StringRef Sym = G->getGlobal()->getName(); 2628 Function *F = G->getGlobal()->getParent()->getFunction(Sym); 2629 if (F && F->hasFnAttribute("__Mips16RetHelper")) { 2630 Mask = MipsRegisterInfo::getMips16RetHelperMask(); 2631 } 2632 } 2633 } 2634 Ops.push_back(CLI.DAG.getRegisterMask(Mask)); 2635 2636 if (InFlag.getNode()) 2637 Ops.push_back(InFlag); 2638 } 2639 2640 /// LowerCall - functions arguments are copied from virtual regs to 2641 /// (physical regs)/(stack frame), CALLSEQ_START and CALLSEQ_END are emitted. 2642 SDValue 2643 MipsTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI, 2644 SmallVectorImpl<SDValue> &InVals) const { 2645 SelectionDAG &DAG = CLI.DAG; 2646 SDLoc DL = CLI.DL; 2647 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs; 2648 SmallVectorImpl<SDValue> &OutVals = CLI.OutVals; 2649 SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins; 2650 SDValue Chain = CLI.Chain; 2651 SDValue Callee = CLI.Callee; 2652 bool &IsTailCall = CLI.IsTailCall; 2653 CallingConv::ID CallConv = CLI.CallConv; 2654 bool IsVarArg = CLI.IsVarArg; 2655 2656 MachineFunction &MF = DAG.getMachineFunction(); 2657 MachineFrameInfo &MFI = MF.getFrameInfo(); 2658 const TargetFrameLowering *TFL = Subtarget.getFrameLowering(); 2659 MipsFunctionInfo *FuncInfo = MF.getInfo<MipsFunctionInfo>(); 2660 bool IsPIC = isPositionIndependent(); 2661 2662 // Analyze operands of the call, assigning locations to each operand. 2663 SmallVector<CCValAssign, 16> ArgLocs; 2664 MipsCCState CCInfo( 2665 CallConv, IsVarArg, DAG.getMachineFunction(), ArgLocs, *DAG.getContext(), 2666 MipsCCState::getSpecialCallingConvForCallee(Callee.getNode(), Subtarget)); 2667 2668 // Allocate the reserved argument area. It seems strange to do this from the 2669 // caller side but removing it breaks the frame size calculation. 2670 CCInfo.AllocateStack(ABI.GetCalleeAllocdArgSizeInBytes(CallConv), 1); 2671 2672 CCInfo.AnalyzeCallOperands(Outs, CC_Mips, CLI.getArgs(), Callee.getNode()); 2673 2674 // Get a count of how many bytes are to be pushed on the stack. 2675 unsigned NextStackOffset = CCInfo.getNextStackOffset(); 2676 2677 // Check if it's really possible to do a tail call. 2678 if (IsTailCall) 2679 IsTailCall = isEligibleForTailCallOptimization( 2680 CCInfo, NextStackOffset, *MF.getInfo<MipsFunctionInfo>()); 2681 2682 if (!IsTailCall && CLI.CS && CLI.CS->isMustTailCall()) 2683 report_fatal_error("failed to perform tail call elimination on a call " 2684 "site marked musttail"); 2685 2686 if (IsTailCall) 2687 ++NumTailCalls; 2688 2689 // Chain is the output chain of the last Load/Store or CopyToReg node. 2690 // ByValChain is the output chain of the last Memcpy node created for copying 2691 // byval arguments to the stack. 2692 unsigned StackAlignment = TFL->getStackAlignment(); 2693 NextStackOffset = alignTo(NextStackOffset, StackAlignment); 2694 SDValue NextStackOffsetVal = DAG.getIntPtrConstant(NextStackOffset, DL, true); 2695 2696 if (!IsTailCall) 2697 Chain = DAG.getCALLSEQ_START(Chain, NextStackOffsetVal, DL); 2698 2699 SDValue StackPtr = 2700 DAG.getCopyFromReg(Chain, DL, ABI.IsN64() ? Mips::SP_64 : Mips::SP, 2701 getPointerTy(DAG.getDataLayout())); 2702 2703 std::deque< std::pair<unsigned, SDValue> > RegsToPass; 2704 SmallVector<SDValue, 8> MemOpChains; 2705 2706 CCInfo.rewindByValRegsInfo(); 2707 2708 // Walk the register/memloc assignments, inserting copies/loads. 2709 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { 2710 SDValue Arg = OutVals[i]; 2711 CCValAssign &VA = ArgLocs[i]; 2712 MVT ValVT = VA.getValVT(), LocVT = VA.getLocVT(); 2713 ISD::ArgFlagsTy Flags = Outs[i].Flags; 2714 bool UseUpperBits = false; 2715 2716 // ByVal Arg. 2717 if (Flags.isByVal()) { 2718 unsigned FirstByValReg, LastByValReg; 2719 unsigned ByValIdx = CCInfo.getInRegsParamsProcessed(); 2720 CCInfo.getInRegsParamInfo(ByValIdx, FirstByValReg, LastByValReg); 2721 2722 assert(Flags.getByValSize() && 2723 "ByVal args of size 0 should have been ignored by front-end."); 2724 assert(ByValIdx < CCInfo.getInRegsParamsCount()); 2725 assert(!IsTailCall && 2726 "Do not tail-call optimize if there is a byval argument."); 2727 passByValArg(Chain, DL, RegsToPass, MemOpChains, StackPtr, MFI, DAG, Arg, 2728 FirstByValReg, LastByValReg, Flags, Subtarget.isLittle(), 2729 VA); 2730 CCInfo.nextInRegsParam(); 2731 continue; 2732 } 2733 2734 // Promote the value if needed. 2735 switch (VA.getLocInfo()) { 2736 default: 2737 llvm_unreachable("Unknown loc info!"); 2738 case CCValAssign::Full: 2739 if (VA.isRegLoc()) { 2740 if ((ValVT == MVT::f32 && LocVT == MVT::i32) || 2741 (ValVT == MVT::f64 && LocVT == MVT::i64) || 2742 (ValVT == MVT::i64 && LocVT == MVT::f64)) 2743 Arg = DAG.getNode(ISD::BITCAST, DL, LocVT, Arg); 2744 else if (ValVT == MVT::f64 && LocVT == MVT::i32) { 2745 SDValue Lo = DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32, 2746 Arg, DAG.getConstant(0, DL, MVT::i32)); 2747 SDValue Hi = DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32, 2748 Arg, DAG.getConstant(1, DL, MVT::i32)); 2749 if (!Subtarget.isLittle()) 2750 std::swap(Lo, Hi); 2751 unsigned LocRegLo = VA.getLocReg(); 2752 unsigned LocRegHigh = getNextIntArgReg(LocRegLo); 2753 RegsToPass.push_back(std::make_pair(LocRegLo, Lo)); 2754 RegsToPass.push_back(std::make_pair(LocRegHigh, Hi)); 2755 continue; 2756 } 2757 } 2758 break; 2759 case CCValAssign::BCvt: 2760 Arg = DAG.getNode(ISD::BITCAST, DL, LocVT, Arg); 2761 break; 2762 case CCValAssign::SExtUpper: 2763 UseUpperBits = true; 2764 LLVM_FALLTHROUGH; 2765 case CCValAssign::SExt: 2766 Arg = DAG.getNode(ISD::SIGN_EXTEND, DL, LocVT, Arg); 2767 break; 2768 case CCValAssign::ZExtUpper: 2769 UseUpperBits = true; 2770 LLVM_FALLTHROUGH; 2771 case CCValAssign::ZExt: 2772 Arg = DAG.getNode(ISD::ZERO_EXTEND, DL, LocVT, Arg); 2773 break; 2774 case CCValAssign::AExtUpper: 2775 UseUpperBits = true; 2776 LLVM_FALLTHROUGH; 2777 case CCValAssign::AExt: 2778 Arg = DAG.getNode(ISD::ANY_EXTEND, DL, LocVT, Arg); 2779 break; 2780 } 2781 2782 if (UseUpperBits) { 2783 unsigned ValSizeInBits = Outs[i].ArgVT.getSizeInBits(); 2784 unsigned LocSizeInBits = VA.getLocVT().getSizeInBits(); 2785 Arg = DAG.getNode( 2786 ISD::SHL, DL, VA.getLocVT(), Arg, 2787 DAG.getConstant(LocSizeInBits - ValSizeInBits, DL, VA.getLocVT())); 2788 } 2789 2790 // Arguments that can be passed on register must be kept at 2791 // RegsToPass vector 2792 if (VA.isRegLoc()) { 2793 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg)); 2794 continue; 2795 } 2796 2797 // Register can't get to this point... 2798 assert(VA.isMemLoc()); 2799 2800 // emit ISD::STORE whichs stores the 2801 // parameter value to a stack Location 2802 MemOpChains.push_back(passArgOnStack(StackPtr, VA.getLocMemOffset(), 2803 Chain, Arg, DL, IsTailCall, DAG)); 2804 } 2805 2806 // Transform all store nodes into one single node because all store 2807 // nodes are independent of each other. 2808 if (!MemOpChains.empty()) 2809 Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, MemOpChains); 2810 2811 // If the callee is a GlobalAddress/ExternalSymbol node (quite common, every 2812 // direct call is) turn it into a TargetGlobalAddress/TargetExternalSymbol 2813 // node so that legalize doesn't hack it. 2814 bool IsPICCall = (ABI.IsN64() || IsPIC); // true if calls are translated to 2815 // jalr $25 2816 bool GlobalOrExternal = false, InternalLinkage = false, IsCallReloc = false; 2817 SDValue CalleeLo; 2818 EVT Ty = Callee.getValueType(); 2819 2820 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) { 2821 if (IsPICCall) { 2822 const GlobalValue *Val = G->getGlobal(); 2823 InternalLinkage = Val->hasInternalLinkage(); 2824 2825 if (InternalLinkage) 2826 Callee = getAddrLocal(G, DL, Ty, DAG, ABI.IsN32() || ABI.IsN64()); 2827 else if (LargeGOT) { 2828 Callee = getAddrGlobalLargeGOT(G, DL, Ty, DAG, MipsII::MO_CALL_HI16, 2829 MipsII::MO_CALL_LO16, Chain, 2830 FuncInfo->callPtrInfo(Val)); 2831 IsCallReloc = true; 2832 } else { 2833 Callee = getAddrGlobal(G, DL, Ty, DAG, MipsII::MO_GOT_CALL, Chain, 2834 FuncInfo->callPtrInfo(Val)); 2835 IsCallReloc = true; 2836 } 2837 } else 2838 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), DL, 2839 getPointerTy(DAG.getDataLayout()), 0, 2840 MipsII::MO_NO_FLAG); 2841 GlobalOrExternal = true; 2842 } 2843 else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) { 2844 const char *Sym = S->getSymbol(); 2845 2846 if (!ABI.IsN64() && !IsPIC) // !N64 && static 2847 Callee = DAG.getTargetExternalSymbol( 2848 Sym, getPointerTy(DAG.getDataLayout()), MipsII::MO_NO_FLAG); 2849 else if (LargeGOT) { 2850 Callee = getAddrGlobalLargeGOT(S, DL, Ty, DAG, MipsII::MO_CALL_HI16, 2851 MipsII::MO_CALL_LO16, Chain, 2852 FuncInfo->callPtrInfo(Sym)); 2853 IsCallReloc = true; 2854 } else { // N64 || PIC 2855 Callee = getAddrGlobal(S, DL, Ty, DAG, MipsII::MO_GOT_CALL, Chain, 2856 FuncInfo->callPtrInfo(Sym)); 2857 IsCallReloc = true; 2858 } 2859 2860 GlobalOrExternal = true; 2861 } 2862 2863 SmallVector<SDValue, 8> Ops(1, Chain); 2864 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue); 2865 2866 getOpndList(Ops, RegsToPass, IsPICCall, GlobalOrExternal, InternalLinkage, 2867 IsCallReloc, CLI, Callee, Chain); 2868 2869 if (IsTailCall) 2870 return DAG.getNode(MipsISD::TailCall, DL, MVT::Other, Ops); 2871 2872 Chain = DAG.getNode(MipsISD::JmpLink, DL, NodeTys, Ops); 2873 SDValue InFlag = Chain.getValue(1); 2874 2875 // Create the CALLSEQ_END node. 2876 Chain = DAG.getCALLSEQ_END(Chain, NextStackOffsetVal, 2877 DAG.getIntPtrConstant(0, DL, true), InFlag, DL); 2878 InFlag = Chain.getValue(1); 2879 2880 // Handle result values, copying them out of physregs into vregs that we 2881 // return. 2882 return LowerCallResult(Chain, InFlag, CallConv, IsVarArg, Ins, DL, DAG, 2883 InVals, CLI); 2884 } 2885 2886 /// LowerCallResult - Lower the result values of a call into the 2887 /// appropriate copies out of appropriate physical registers. 2888 SDValue MipsTargetLowering::LowerCallResult( 2889 SDValue Chain, SDValue InFlag, CallingConv::ID CallConv, bool IsVarArg, 2890 const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &DL, 2891 SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals, 2892 TargetLowering::CallLoweringInfo &CLI) const { 2893 // Assign locations to each value returned by this call. 2894 SmallVector<CCValAssign, 16> RVLocs; 2895 MipsCCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), RVLocs, 2896 *DAG.getContext()); 2897 CCInfo.AnalyzeCallResult(Ins, RetCC_Mips, CLI); 2898 2899 // Copy all of the result registers out of their specified physreg. 2900 for (unsigned i = 0; i != RVLocs.size(); ++i) { 2901 CCValAssign &VA = RVLocs[i]; 2902 assert(VA.isRegLoc() && "Can only return in registers!"); 2903 2904 SDValue Val = DAG.getCopyFromReg(Chain, DL, RVLocs[i].getLocReg(), 2905 RVLocs[i].getLocVT(), InFlag); 2906 Chain = Val.getValue(1); 2907 InFlag = Val.getValue(2); 2908 2909 if (VA.isUpperBitsInLoc()) { 2910 unsigned ValSizeInBits = Ins[i].ArgVT.getSizeInBits(); 2911 unsigned LocSizeInBits = VA.getLocVT().getSizeInBits(); 2912 unsigned Shift = 2913 VA.getLocInfo() == CCValAssign::ZExtUpper ? ISD::SRL : ISD::SRA; 2914 Val = DAG.getNode( 2915 Shift, DL, VA.getLocVT(), Val, 2916 DAG.getConstant(LocSizeInBits - ValSizeInBits, DL, VA.getLocVT())); 2917 } 2918 2919 switch (VA.getLocInfo()) { 2920 default: 2921 llvm_unreachable("Unknown loc info!"); 2922 case CCValAssign::Full: 2923 break; 2924 case CCValAssign::BCvt: 2925 Val = DAG.getNode(ISD::BITCAST, DL, VA.getValVT(), Val); 2926 break; 2927 case CCValAssign::AExt: 2928 case CCValAssign::AExtUpper: 2929 Val = DAG.getNode(ISD::TRUNCATE, DL, VA.getValVT(), Val); 2930 break; 2931 case CCValAssign::ZExt: 2932 case CCValAssign::ZExtUpper: 2933 Val = DAG.getNode(ISD::AssertZext, DL, VA.getLocVT(), Val, 2934 DAG.getValueType(VA.getValVT())); 2935 Val = DAG.getNode(ISD::TRUNCATE, DL, VA.getValVT(), Val); 2936 break; 2937 case CCValAssign::SExt: 2938 case CCValAssign::SExtUpper: 2939 Val = DAG.getNode(ISD::AssertSext, DL, VA.getLocVT(), Val, 2940 DAG.getValueType(VA.getValVT())); 2941 Val = DAG.getNode(ISD::TRUNCATE, DL, VA.getValVT(), Val); 2942 break; 2943 } 2944 2945 InVals.push_back(Val); 2946 } 2947 2948 return Chain; 2949 } 2950 2951 static SDValue UnpackFromArgumentSlot(SDValue Val, const CCValAssign &VA, 2952 EVT ArgVT, const SDLoc &DL, 2953 SelectionDAG &DAG) { 2954 MVT LocVT = VA.getLocVT(); 2955 EVT ValVT = VA.getValVT(); 2956 2957 // Shift into the upper bits if necessary. 2958 switch (VA.getLocInfo()) { 2959 default: 2960 break; 2961 case CCValAssign::AExtUpper: 2962 case CCValAssign::SExtUpper: 2963 case CCValAssign::ZExtUpper: { 2964 unsigned ValSizeInBits = ArgVT.getSizeInBits(); 2965 unsigned LocSizeInBits = VA.getLocVT().getSizeInBits(); 2966 unsigned Opcode = 2967 VA.getLocInfo() == CCValAssign::ZExtUpper ? ISD::SRL : ISD::SRA; 2968 Val = DAG.getNode( 2969 Opcode, DL, VA.getLocVT(), Val, 2970 DAG.getConstant(LocSizeInBits - ValSizeInBits, DL, VA.getLocVT())); 2971 break; 2972 } 2973 } 2974 2975 // If this is an value smaller than the argument slot size (32-bit for O32, 2976 // 64-bit for N32/N64), it has been promoted in some way to the argument slot 2977 // size. Extract the value and insert any appropriate assertions regarding 2978 // sign/zero extension. 2979 switch (VA.getLocInfo()) { 2980 default: 2981 llvm_unreachable("Unknown loc info!"); 2982 case CCValAssign::Full: 2983 break; 2984 case CCValAssign::AExtUpper: 2985 case CCValAssign::AExt: 2986 Val = DAG.getNode(ISD::TRUNCATE, DL, ValVT, Val); 2987 break; 2988 case CCValAssign::SExtUpper: 2989 case CCValAssign::SExt: 2990 Val = DAG.getNode(ISD::AssertSext, DL, LocVT, Val, DAG.getValueType(ValVT)); 2991 Val = DAG.getNode(ISD::TRUNCATE, DL, ValVT, Val); 2992 break; 2993 case CCValAssign::ZExtUpper: 2994 case CCValAssign::ZExt: 2995 Val = DAG.getNode(ISD::AssertZext, DL, LocVT, Val, DAG.getValueType(ValVT)); 2996 Val = DAG.getNode(ISD::TRUNCATE, DL, ValVT, Val); 2997 break; 2998 case CCValAssign::BCvt: 2999 Val = DAG.getNode(ISD::BITCAST, DL, ValVT, Val); 3000 break; 3001 } 3002 3003 return Val; 3004 } 3005 3006 //===----------------------------------------------------------------------===// 3007 // Formal Arguments Calling Convention Implementation 3008 //===----------------------------------------------------------------------===// 3009 /// LowerFormalArguments - transform physical registers into virtual registers 3010 /// and generate load operations for arguments places on the stack. 3011 SDValue MipsTargetLowering::LowerFormalArguments( 3012 SDValue Chain, CallingConv::ID CallConv, bool IsVarArg, 3013 const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &DL, 3014 SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const { 3015 MachineFunction &MF = DAG.getMachineFunction(); 3016 MachineFrameInfo &MFI = MF.getFrameInfo(); 3017 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>(); 3018 3019 MipsFI->setVarArgsFrameIndex(0); 3020 3021 // Used with vargs to acumulate store chains. 3022 std::vector<SDValue> OutChains; 3023 3024 // Assign locations to all of the incoming arguments. 3025 SmallVector<CCValAssign, 16> ArgLocs; 3026 MipsCCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), ArgLocs, 3027 *DAG.getContext()); 3028 CCInfo.AllocateStack(ABI.GetCalleeAllocdArgSizeInBytes(CallConv), 1); 3029 const Function *Func = DAG.getMachineFunction().getFunction(); 3030 Function::const_arg_iterator FuncArg = Func->arg_begin(); 3031 3032 if (Func->hasFnAttribute("interrupt") && !Func->arg_empty()) 3033 report_fatal_error( 3034 "Functions with the interrupt attribute cannot have arguments!"); 3035 3036 CCInfo.AnalyzeFormalArguments(Ins, CC_Mips_FixedArg); 3037 MipsFI->setFormalArgInfo(CCInfo.getNextStackOffset(), 3038 CCInfo.getInRegsParamsCount() > 0); 3039 3040 unsigned CurArgIdx = 0; 3041 CCInfo.rewindByValRegsInfo(); 3042 3043 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { 3044 CCValAssign &VA = ArgLocs[i]; 3045 if (Ins[i].isOrigArg()) { 3046 std::advance(FuncArg, Ins[i].getOrigArgIndex() - CurArgIdx); 3047 CurArgIdx = Ins[i].getOrigArgIndex(); 3048 } 3049 EVT ValVT = VA.getValVT(); 3050 ISD::ArgFlagsTy Flags = Ins[i].Flags; 3051 bool IsRegLoc = VA.isRegLoc(); 3052 3053 if (Flags.isByVal()) { 3054 assert(Ins[i].isOrigArg() && "Byval arguments cannot be implicit"); 3055 unsigned FirstByValReg, LastByValReg; 3056 unsigned ByValIdx = CCInfo.getInRegsParamsProcessed(); 3057 CCInfo.getInRegsParamInfo(ByValIdx, FirstByValReg, LastByValReg); 3058 3059 assert(Flags.getByValSize() && 3060 "ByVal args of size 0 should have been ignored by front-end."); 3061 assert(ByValIdx < CCInfo.getInRegsParamsCount()); 3062 copyByValRegs(Chain, DL, OutChains, DAG, Flags, InVals, &*FuncArg, 3063 FirstByValReg, LastByValReg, VA, CCInfo); 3064 CCInfo.nextInRegsParam(); 3065 continue; 3066 } 3067 3068 // Arguments stored on registers 3069 if (IsRegLoc) { 3070 MVT RegVT = VA.getLocVT(); 3071 unsigned ArgReg = VA.getLocReg(); 3072 const TargetRegisterClass *RC = getRegClassFor(RegVT); 3073 3074 // Transform the arguments stored on 3075 // physical registers into virtual ones 3076 unsigned Reg = addLiveIn(DAG.getMachineFunction(), ArgReg, RC); 3077 SDValue ArgValue = DAG.getCopyFromReg(Chain, DL, Reg, RegVT); 3078 3079 ArgValue = UnpackFromArgumentSlot(ArgValue, VA, Ins[i].ArgVT, DL, DAG); 3080 3081 // Handle floating point arguments passed in integer registers and 3082 // long double arguments passed in floating point registers. 3083 if ((RegVT == MVT::i32 && ValVT == MVT::f32) || 3084 (RegVT == MVT::i64 && ValVT == MVT::f64) || 3085 (RegVT == MVT::f64 && ValVT == MVT::i64)) 3086 ArgValue = DAG.getNode(ISD::BITCAST, DL, ValVT, ArgValue); 3087 else if (ABI.IsO32() && RegVT == MVT::i32 && 3088 ValVT == MVT::f64) { 3089 unsigned Reg2 = addLiveIn(DAG.getMachineFunction(), 3090 getNextIntArgReg(ArgReg), RC); 3091 SDValue ArgValue2 = DAG.getCopyFromReg(Chain, DL, Reg2, RegVT); 3092 if (!Subtarget.isLittle()) 3093 std::swap(ArgValue, ArgValue2); 3094 ArgValue = DAG.getNode(MipsISD::BuildPairF64, DL, MVT::f64, 3095 ArgValue, ArgValue2); 3096 } 3097 3098 InVals.push_back(ArgValue); 3099 } else { // VA.isRegLoc() 3100 MVT LocVT = VA.getLocVT(); 3101 3102 if (ABI.IsO32()) { 3103 // We ought to be able to use LocVT directly but O32 sets it to i32 3104 // when allocating floating point values to integer registers. 3105 // This shouldn't influence how we load the value into registers unless 3106 // we are targeting softfloat. 3107 if (VA.getValVT().isFloatingPoint() && !Subtarget.useSoftFloat()) 3108 LocVT = VA.getValVT(); 3109 } 3110 3111 // sanity check 3112 assert(VA.isMemLoc()); 3113 3114 // The stack pointer offset is relative to the caller stack frame. 3115 int FI = MFI.CreateFixedObject(LocVT.getSizeInBits() / 8, 3116 VA.getLocMemOffset(), true); 3117 3118 // Create load nodes to retrieve arguments from the stack 3119 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy(DAG.getDataLayout())); 3120 SDValue ArgValue = DAG.getLoad( 3121 LocVT, DL, Chain, FIN, 3122 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), FI)); 3123 OutChains.push_back(ArgValue.getValue(1)); 3124 3125 ArgValue = UnpackFromArgumentSlot(ArgValue, VA, Ins[i].ArgVT, DL, DAG); 3126 3127 InVals.push_back(ArgValue); 3128 } 3129 } 3130 3131 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { 3132 // The mips ABIs for returning structs by value requires that we copy 3133 // the sret argument into $v0 for the return. Save the argument into 3134 // a virtual register so that we can access it from the return points. 3135 if (Ins[i].Flags.isSRet()) { 3136 unsigned Reg = MipsFI->getSRetReturnReg(); 3137 if (!Reg) { 3138 Reg = MF.getRegInfo().createVirtualRegister( 3139 getRegClassFor(ABI.IsN64() ? MVT::i64 : MVT::i32)); 3140 MipsFI->setSRetReturnReg(Reg); 3141 } 3142 SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), DL, Reg, InVals[i]); 3143 Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, Copy, Chain); 3144 break; 3145 } 3146 } 3147 3148 if (IsVarArg) 3149 writeVarArgRegs(OutChains, Chain, DL, DAG, CCInfo); 3150 3151 // All stores are grouped in one node to allow the matching between 3152 // the size of Ins and InVals. This only happens when on varg functions 3153 if (!OutChains.empty()) { 3154 OutChains.push_back(Chain); 3155 Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, OutChains); 3156 } 3157 3158 return Chain; 3159 } 3160 3161 //===----------------------------------------------------------------------===// 3162 // Return Value Calling Convention Implementation 3163 //===----------------------------------------------------------------------===// 3164 3165 bool 3166 MipsTargetLowering::CanLowerReturn(CallingConv::ID CallConv, 3167 MachineFunction &MF, bool IsVarArg, 3168 const SmallVectorImpl<ISD::OutputArg> &Outs, 3169 LLVMContext &Context) const { 3170 SmallVector<CCValAssign, 16> RVLocs; 3171 MipsCCState CCInfo(CallConv, IsVarArg, MF, RVLocs, Context); 3172 return CCInfo.CheckReturn(Outs, RetCC_Mips); 3173 } 3174 3175 bool 3176 MipsTargetLowering::shouldSignExtendTypeInLibCall(EVT Type, bool IsSigned) const { 3177 if (Subtarget.hasMips3() && Subtarget.useSoftFloat()) { 3178 if (Type == MVT::i32) 3179 return true; 3180 } 3181 return IsSigned; 3182 } 3183 3184 SDValue 3185 MipsTargetLowering::LowerInterruptReturn(SmallVectorImpl<SDValue> &RetOps, 3186 const SDLoc &DL, 3187 SelectionDAG &DAG) const { 3188 3189 MachineFunction &MF = DAG.getMachineFunction(); 3190 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>(); 3191 3192 MipsFI->setISR(); 3193 3194 return DAG.getNode(MipsISD::ERet, DL, MVT::Other, RetOps); 3195 } 3196 3197 SDValue 3198 MipsTargetLowering::LowerReturn(SDValue Chain, CallingConv::ID CallConv, 3199 bool IsVarArg, 3200 const SmallVectorImpl<ISD::OutputArg> &Outs, 3201 const SmallVectorImpl<SDValue> &OutVals, 3202 const SDLoc &DL, SelectionDAG &DAG) const { 3203 // CCValAssign - represent the assignment of 3204 // the return value to a location 3205 SmallVector<CCValAssign, 16> RVLocs; 3206 MachineFunction &MF = DAG.getMachineFunction(); 3207 3208 // CCState - Info about the registers and stack slot. 3209 MipsCCState CCInfo(CallConv, IsVarArg, MF, RVLocs, *DAG.getContext()); 3210 3211 // Analyze return values. 3212 CCInfo.AnalyzeReturn(Outs, RetCC_Mips); 3213 3214 SDValue Flag; 3215 SmallVector<SDValue, 4> RetOps(1, Chain); 3216 3217 // Copy the result values into the output registers. 3218 for (unsigned i = 0; i != RVLocs.size(); ++i) { 3219 SDValue Val = OutVals[i]; 3220 CCValAssign &VA = RVLocs[i]; 3221 assert(VA.isRegLoc() && "Can only return in registers!"); 3222 bool UseUpperBits = false; 3223 3224 switch (VA.getLocInfo()) { 3225 default: 3226 llvm_unreachable("Unknown loc info!"); 3227 case CCValAssign::Full: 3228 break; 3229 case CCValAssign::BCvt: 3230 Val = DAG.getNode(ISD::BITCAST, DL, VA.getLocVT(), Val); 3231 break; 3232 case CCValAssign::AExtUpper: 3233 UseUpperBits = true; 3234 LLVM_FALLTHROUGH; 3235 case CCValAssign::AExt: 3236 Val = DAG.getNode(ISD::ANY_EXTEND, DL, VA.getLocVT(), Val); 3237 break; 3238 case CCValAssign::ZExtUpper: 3239 UseUpperBits = true; 3240 LLVM_FALLTHROUGH; 3241 case CCValAssign::ZExt: 3242 Val = DAG.getNode(ISD::ZERO_EXTEND, DL, VA.getLocVT(), Val); 3243 break; 3244 case CCValAssign::SExtUpper: 3245 UseUpperBits = true; 3246 LLVM_FALLTHROUGH; 3247 case CCValAssign::SExt: 3248 Val = DAG.getNode(ISD::SIGN_EXTEND, DL, VA.getLocVT(), Val); 3249 break; 3250 } 3251 3252 if (UseUpperBits) { 3253 unsigned ValSizeInBits = Outs[i].ArgVT.getSizeInBits(); 3254 unsigned LocSizeInBits = VA.getLocVT().getSizeInBits(); 3255 Val = DAG.getNode( 3256 ISD::SHL, DL, VA.getLocVT(), Val, 3257 DAG.getConstant(LocSizeInBits - ValSizeInBits, DL, VA.getLocVT())); 3258 } 3259 3260 Chain = DAG.getCopyToReg(Chain, DL, VA.getLocReg(), Val, Flag); 3261 3262 // Guarantee that all emitted copies are stuck together with flags. 3263 Flag = Chain.getValue(1); 3264 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT())); 3265 } 3266 3267 // The mips ABIs for returning structs by value requires that we copy 3268 // the sret argument into $v0 for the return. We saved the argument into 3269 // a virtual register in the entry block, so now we copy the value out 3270 // and into $v0. 3271 if (MF.getFunction()->hasStructRetAttr()) { 3272 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>(); 3273 unsigned Reg = MipsFI->getSRetReturnReg(); 3274 3275 if (!Reg) 3276 llvm_unreachable("sret virtual register not created in the entry block"); 3277 SDValue Val = 3278 DAG.getCopyFromReg(Chain, DL, Reg, getPointerTy(DAG.getDataLayout())); 3279 unsigned V0 = ABI.IsN64() ? Mips::V0_64 : Mips::V0; 3280 3281 Chain = DAG.getCopyToReg(Chain, DL, V0, Val, Flag); 3282 Flag = Chain.getValue(1); 3283 RetOps.push_back(DAG.getRegister(V0, getPointerTy(DAG.getDataLayout()))); 3284 } 3285 3286 RetOps[0] = Chain; // Update chain. 3287 3288 // Add the flag if we have it. 3289 if (Flag.getNode()) 3290 RetOps.push_back(Flag); 3291 3292 // ISRs must use "eret". 3293 if (DAG.getMachineFunction().getFunction()->hasFnAttribute("interrupt")) 3294 return LowerInterruptReturn(RetOps, DL, DAG); 3295 3296 // Standard return on Mips is a "jr $ra" 3297 return DAG.getNode(MipsISD::Ret, DL, MVT::Other, RetOps); 3298 } 3299 3300 //===----------------------------------------------------------------------===// 3301 // Mips Inline Assembly Support 3302 //===----------------------------------------------------------------------===// 3303 3304 /// getConstraintType - Given a constraint letter, return the type of 3305 /// constraint it is for this target. 3306 MipsTargetLowering::ConstraintType 3307 MipsTargetLowering::getConstraintType(StringRef Constraint) const { 3308 // Mips specific constraints 3309 // GCC config/mips/constraints.md 3310 // 3311 // 'd' : An address register. Equivalent to r 3312 // unless generating MIPS16 code. 3313 // 'y' : Equivalent to r; retained for 3314 // backwards compatibility. 3315 // 'c' : A register suitable for use in an indirect 3316 // jump. This will always be $25 for -mabicalls. 3317 // 'l' : The lo register. 1 word storage. 3318 // 'x' : The hilo register pair. Double word storage. 3319 if (Constraint.size() == 1) { 3320 switch (Constraint[0]) { 3321 default : break; 3322 case 'd': 3323 case 'y': 3324 case 'f': 3325 case 'c': 3326 case 'l': 3327 case 'x': 3328 return C_RegisterClass; 3329 case 'R': 3330 return C_Memory; 3331 } 3332 } 3333 3334 if (Constraint == "ZC") 3335 return C_Memory; 3336 3337 return TargetLowering::getConstraintType(Constraint); 3338 } 3339 3340 /// Examine constraint type and operand type and determine a weight value. 3341 /// This object must already have been set up with the operand type 3342 /// and the current alternative constraint selected. 3343 TargetLowering::ConstraintWeight 3344 MipsTargetLowering::getSingleConstraintMatchWeight( 3345 AsmOperandInfo &info, const char *constraint) const { 3346 ConstraintWeight weight = CW_Invalid; 3347 Value *CallOperandVal = info.CallOperandVal; 3348 // If we don't have a value, we can't do a match, 3349 // but allow it at the lowest weight. 3350 if (!CallOperandVal) 3351 return CW_Default; 3352 Type *type = CallOperandVal->getType(); 3353 // Look at the constraint type. 3354 switch (*constraint) { 3355 default: 3356 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint); 3357 break; 3358 case 'd': 3359 case 'y': 3360 if (type->isIntegerTy()) 3361 weight = CW_Register; 3362 break; 3363 case 'f': // FPU or MSA register 3364 if (Subtarget.hasMSA() && type->isVectorTy() && 3365 cast<VectorType>(type)->getBitWidth() == 128) 3366 weight = CW_Register; 3367 else if (type->isFloatTy()) 3368 weight = CW_Register; 3369 break; 3370 case 'c': // $25 for indirect jumps 3371 case 'l': // lo register 3372 case 'x': // hilo register pair 3373 if (type->isIntegerTy()) 3374 weight = CW_SpecificReg; 3375 break; 3376 case 'I': // signed 16 bit immediate 3377 case 'J': // integer zero 3378 case 'K': // unsigned 16 bit immediate 3379 case 'L': // signed 32 bit immediate where lower 16 bits are 0 3380 case 'N': // immediate in the range of -65535 to -1 (inclusive) 3381 case 'O': // signed 15 bit immediate (+- 16383) 3382 case 'P': // immediate in the range of 65535 to 1 (inclusive) 3383 if (isa<ConstantInt>(CallOperandVal)) 3384 weight = CW_Constant; 3385 break; 3386 case 'R': 3387 weight = CW_Memory; 3388 break; 3389 } 3390 return weight; 3391 } 3392 3393 /// This is a helper function to parse a physical register string and split it 3394 /// into non-numeric and numeric parts (Prefix and Reg). The first boolean flag 3395 /// that is returned indicates whether parsing was successful. The second flag 3396 /// is true if the numeric part exists. 3397 static std::pair<bool, bool> parsePhysicalReg(StringRef C, StringRef &Prefix, 3398 unsigned long long &Reg) { 3399 if (C.front() != '{' || C.back() != '}') 3400 return std::make_pair(false, false); 3401 3402 // Search for the first numeric character. 3403 StringRef::const_iterator I, B = C.begin() + 1, E = C.end() - 1; 3404 I = std::find_if(B, E, isdigit); 3405 3406 Prefix = StringRef(B, I - B); 3407 3408 // The second flag is set to false if no numeric characters were found. 3409 if (I == E) 3410 return std::make_pair(true, false); 3411 3412 // Parse the numeric characters. 3413 return std::make_pair(!getAsUnsignedInteger(StringRef(I, E - I), 10, Reg), 3414 true); 3415 } 3416 3417 std::pair<unsigned, const TargetRegisterClass *> MipsTargetLowering:: 3418 parseRegForInlineAsmConstraint(StringRef C, MVT VT) const { 3419 const TargetRegisterInfo *TRI = 3420 Subtarget.getRegisterInfo(); 3421 const TargetRegisterClass *RC; 3422 StringRef Prefix; 3423 unsigned long long Reg; 3424 3425 std::pair<bool, bool> R = parsePhysicalReg(C, Prefix, Reg); 3426 3427 if (!R.first) 3428 return std::make_pair(0U, nullptr); 3429 3430 if ((Prefix == "hi" || Prefix == "lo")) { // Parse hi/lo. 3431 // No numeric characters follow "hi" or "lo". 3432 if (R.second) 3433 return std::make_pair(0U, nullptr); 3434 3435 RC = TRI->getRegClass(Prefix == "hi" ? 3436 Mips::HI32RegClassID : Mips::LO32RegClassID); 3437 return std::make_pair(*(RC->begin()), RC); 3438 } else if (Prefix.startswith("$msa")) { 3439 // Parse $msa(ir|csr|access|save|modify|request|map|unmap) 3440 3441 // No numeric characters follow the name. 3442 if (R.second) 3443 return std::make_pair(0U, nullptr); 3444 3445 Reg = StringSwitch<unsigned long long>(Prefix) 3446 .Case("$msair", Mips::MSAIR) 3447 .Case("$msacsr", Mips::MSACSR) 3448 .Case("$msaaccess", Mips::MSAAccess) 3449 .Case("$msasave", Mips::MSASave) 3450 .Case("$msamodify", Mips::MSAModify) 3451 .Case("$msarequest", Mips::MSARequest) 3452 .Case("$msamap", Mips::MSAMap) 3453 .Case("$msaunmap", Mips::MSAUnmap) 3454 .Default(0); 3455 3456 if (!Reg) 3457 return std::make_pair(0U, nullptr); 3458 3459 RC = TRI->getRegClass(Mips::MSACtrlRegClassID); 3460 return std::make_pair(Reg, RC); 3461 } 3462 3463 if (!R.second) 3464 return std::make_pair(0U, nullptr); 3465 3466 if (Prefix == "$f") { // Parse $f0-$f31. 3467 // If the size of FP registers is 64-bit or Reg is an even number, select 3468 // the 64-bit register class. Otherwise, select the 32-bit register class. 3469 if (VT == MVT::Other) 3470 VT = (Subtarget.isFP64bit() || !(Reg % 2)) ? MVT::f64 : MVT::f32; 3471 3472 RC = getRegClassFor(VT); 3473 3474 if (RC == &Mips::AFGR64RegClass) { 3475 assert(Reg % 2 == 0); 3476 Reg >>= 1; 3477 } 3478 } else if (Prefix == "$fcc") // Parse $fcc0-$fcc7. 3479 RC = TRI->getRegClass(Mips::FCCRegClassID); 3480 else if (Prefix == "$w") { // Parse $w0-$w31. 3481 RC = getRegClassFor((VT == MVT::Other) ? MVT::v16i8 : VT); 3482 } else { // Parse $0-$31. 3483 assert(Prefix == "$"); 3484 RC = getRegClassFor((VT == MVT::Other) ? MVT::i32 : VT); 3485 } 3486 3487 assert(Reg < RC->getNumRegs()); 3488 return std::make_pair(*(RC->begin() + Reg), RC); 3489 } 3490 3491 /// Given a register class constraint, like 'r', if this corresponds directly 3492 /// to an LLVM register class, return a register of 0 and the register class 3493 /// pointer. 3494 std::pair<unsigned, const TargetRegisterClass *> 3495 MipsTargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, 3496 StringRef Constraint, 3497 MVT VT) const { 3498 if (Constraint.size() == 1) { 3499 switch (Constraint[0]) { 3500 case 'd': // Address register. Same as 'r' unless generating MIPS16 code. 3501 case 'y': // Same as 'r'. Exists for compatibility. 3502 case 'r': 3503 if (VT == MVT::i32 || VT == MVT::i16 || VT == MVT::i8) { 3504 if (Subtarget.inMips16Mode()) 3505 return std::make_pair(0U, &Mips::CPU16RegsRegClass); 3506 return std::make_pair(0U, &Mips::GPR32RegClass); 3507 } 3508 if (VT == MVT::i64 && !Subtarget.isGP64bit()) 3509 return std::make_pair(0U, &Mips::GPR32RegClass); 3510 if (VT == MVT::i64 && Subtarget.isGP64bit()) 3511 return std::make_pair(0U, &Mips::GPR64RegClass); 3512 // This will generate an error message 3513 return std::make_pair(0U, nullptr); 3514 case 'f': // FPU or MSA register 3515 if (VT == MVT::v16i8) 3516 return std::make_pair(0U, &Mips::MSA128BRegClass); 3517 else if (VT == MVT::v8i16 || VT == MVT::v8f16) 3518 return std::make_pair(0U, &Mips::MSA128HRegClass); 3519 else if (VT == MVT::v4i32 || VT == MVT::v4f32) 3520 return std::make_pair(0U, &Mips::MSA128WRegClass); 3521 else if (VT == MVT::v2i64 || VT == MVT::v2f64) 3522 return std::make_pair(0U, &Mips::MSA128DRegClass); 3523 else if (VT == MVT::f32) 3524 return std::make_pair(0U, &Mips::FGR32RegClass); 3525 else if ((VT == MVT::f64) && (!Subtarget.isSingleFloat())) { 3526 if (Subtarget.isFP64bit()) 3527 return std::make_pair(0U, &Mips::FGR64RegClass); 3528 return std::make_pair(0U, &Mips::AFGR64RegClass); 3529 } 3530 break; 3531 case 'c': // register suitable for indirect jump 3532 if (VT == MVT::i32) 3533 return std::make_pair((unsigned)Mips::T9, &Mips::GPR32RegClass); 3534 assert(VT == MVT::i64 && "Unexpected type."); 3535 return std::make_pair((unsigned)Mips::T9_64, &Mips::GPR64RegClass); 3536 case 'l': // register suitable for indirect jump 3537 if (VT == MVT::i32) 3538 return std::make_pair((unsigned)Mips::LO0, &Mips::LO32RegClass); 3539 return std::make_pair((unsigned)Mips::LO0_64, &Mips::LO64RegClass); 3540 case 'x': // register suitable for indirect jump 3541 // Fixme: Not triggering the use of both hi and low 3542 // This will generate an error message 3543 return std::make_pair(0U, nullptr); 3544 } 3545 } 3546 3547 std::pair<unsigned, const TargetRegisterClass *> R; 3548 R = parseRegForInlineAsmConstraint(Constraint, VT); 3549 3550 if (R.second) 3551 return R; 3552 3553 return TargetLowering::getRegForInlineAsmConstraint(TRI, Constraint, VT); 3554 } 3555 3556 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops 3557 /// vector. If it is invalid, don't add anything to Ops. 3558 void MipsTargetLowering::LowerAsmOperandForConstraint(SDValue Op, 3559 std::string &Constraint, 3560 std::vector<SDValue>&Ops, 3561 SelectionDAG &DAG) const { 3562 SDLoc DL(Op); 3563 SDValue Result; 3564 3565 // Only support length 1 constraints for now. 3566 if (Constraint.length() > 1) return; 3567 3568 char ConstraintLetter = Constraint[0]; 3569 switch (ConstraintLetter) { 3570 default: break; // This will fall through to the generic implementation 3571 case 'I': // Signed 16 bit constant 3572 // If this fails, the parent routine will give an error 3573 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 3574 EVT Type = Op.getValueType(); 3575 int64_t Val = C->getSExtValue(); 3576 if (isInt<16>(Val)) { 3577 Result = DAG.getTargetConstant(Val, DL, Type); 3578 break; 3579 } 3580 } 3581 return; 3582 case 'J': // integer zero 3583 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 3584 EVT Type = Op.getValueType(); 3585 int64_t Val = C->getZExtValue(); 3586 if (Val == 0) { 3587 Result = DAG.getTargetConstant(0, DL, Type); 3588 break; 3589 } 3590 } 3591 return; 3592 case 'K': // unsigned 16 bit immediate 3593 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 3594 EVT Type = Op.getValueType(); 3595 uint64_t Val = (uint64_t)C->getZExtValue(); 3596 if (isUInt<16>(Val)) { 3597 Result = DAG.getTargetConstant(Val, DL, Type); 3598 break; 3599 } 3600 } 3601 return; 3602 case 'L': // signed 32 bit immediate where lower 16 bits are 0 3603 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 3604 EVT Type = Op.getValueType(); 3605 int64_t Val = C->getSExtValue(); 3606 if ((isInt<32>(Val)) && ((Val & 0xffff) == 0)){ 3607 Result = DAG.getTargetConstant(Val, DL, Type); 3608 break; 3609 } 3610 } 3611 return; 3612 case 'N': // immediate in the range of -65535 to -1 (inclusive) 3613 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 3614 EVT Type = Op.getValueType(); 3615 int64_t Val = C->getSExtValue(); 3616 if ((Val >= -65535) && (Val <= -1)) { 3617 Result = DAG.getTargetConstant(Val, DL, Type); 3618 break; 3619 } 3620 } 3621 return; 3622 case 'O': // signed 15 bit immediate 3623 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 3624 EVT Type = Op.getValueType(); 3625 int64_t Val = C->getSExtValue(); 3626 if ((isInt<15>(Val))) { 3627 Result = DAG.getTargetConstant(Val, DL, Type); 3628 break; 3629 } 3630 } 3631 return; 3632 case 'P': // immediate in the range of 1 to 65535 (inclusive) 3633 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 3634 EVT Type = Op.getValueType(); 3635 int64_t Val = C->getSExtValue(); 3636 if ((Val <= 65535) && (Val >= 1)) { 3637 Result = DAG.getTargetConstant(Val, DL, Type); 3638 break; 3639 } 3640 } 3641 return; 3642 } 3643 3644 if (Result.getNode()) { 3645 Ops.push_back(Result); 3646 return; 3647 } 3648 3649 TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG); 3650 } 3651 3652 bool MipsTargetLowering::isLegalAddressingMode(const DataLayout &DL, 3653 const AddrMode &AM, Type *Ty, 3654 unsigned AS) const { 3655 // No global is ever allowed as a base. 3656 if (AM.BaseGV) 3657 return false; 3658 3659 switch (AM.Scale) { 3660 case 0: // "r+i" or just "i", depending on HasBaseReg. 3661 break; 3662 case 1: 3663 if (!AM.HasBaseReg) // allow "r+i". 3664 break; 3665 return false; // disallow "r+r" or "r+r+i". 3666 default: 3667 return false; 3668 } 3669 3670 return true; 3671 } 3672 3673 bool 3674 MipsTargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const { 3675 // The Mips target isn't yet aware of offsets. 3676 return false; 3677 } 3678 3679 EVT MipsTargetLowering::getOptimalMemOpType(uint64_t Size, unsigned DstAlign, 3680 unsigned SrcAlign, 3681 bool IsMemset, bool ZeroMemset, 3682 bool MemcpyStrSrc, 3683 MachineFunction &MF) const { 3684 if (Subtarget.hasMips64()) 3685 return MVT::i64; 3686 3687 return MVT::i32; 3688 } 3689 3690 bool MipsTargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const { 3691 if (VT != MVT::f32 && VT != MVT::f64) 3692 return false; 3693 if (Imm.isNegZero()) 3694 return false; 3695 return Imm.isZero(); 3696 } 3697 3698 unsigned MipsTargetLowering::getJumpTableEncoding() const { 3699 if (ABI.IsN64()) 3700 return MachineJumpTableInfo::EK_GPRel64BlockAddress; 3701 3702 return TargetLowering::getJumpTableEncoding(); 3703 } 3704 3705 bool MipsTargetLowering::useSoftFloat() const { 3706 return Subtarget.useSoftFloat(); 3707 } 3708 3709 void MipsTargetLowering::copyByValRegs( 3710 SDValue Chain, const SDLoc &DL, std::vector<SDValue> &OutChains, 3711 SelectionDAG &DAG, const ISD::ArgFlagsTy &Flags, 3712 SmallVectorImpl<SDValue> &InVals, const Argument *FuncArg, 3713 unsigned FirstReg, unsigned LastReg, const CCValAssign &VA, 3714 MipsCCState &State) const { 3715 MachineFunction &MF = DAG.getMachineFunction(); 3716 MachineFrameInfo &MFI = MF.getFrameInfo(); 3717 unsigned GPRSizeInBytes = Subtarget.getGPRSizeInBytes(); 3718 unsigned NumRegs = LastReg - FirstReg; 3719 unsigned RegAreaSize = NumRegs * GPRSizeInBytes; 3720 unsigned FrameObjSize = std::max(Flags.getByValSize(), RegAreaSize); 3721 int FrameObjOffset; 3722 ArrayRef<MCPhysReg> ByValArgRegs = ABI.GetByValArgRegs(); 3723 3724 if (RegAreaSize) 3725 FrameObjOffset = 3726 (int)ABI.GetCalleeAllocdArgSizeInBytes(State.getCallingConv()) - 3727 (int)((ByValArgRegs.size() - FirstReg) * GPRSizeInBytes); 3728 else 3729 FrameObjOffset = VA.getLocMemOffset(); 3730 3731 // Create frame object. 3732 EVT PtrTy = getPointerTy(DAG.getDataLayout()); 3733 int FI = MFI.CreateFixedObject(FrameObjSize, FrameObjOffset, true); 3734 SDValue FIN = DAG.getFrameIndex(FI, PtrTy); 3735 InVals.push_back(FIN); 3736 3737 if (!NumRegs) 3738 return; 3739 3740 // Copy arg registers. 3741 MVT RegTy = MVT::getIntegerVT(GPRSizeInBytes * 8); 3742 const TargetRegisterClass *RC = getRegClassFor(RegTy); 3743 3744 for (unsigned I = 0; I < NumRegs; ++I) { 3745 unsigned ArgReg = ByValArgRegs[FirstReg + I]; 3746 unsigned VReg = addLiveIn(MF, ArgReg, RC); 3747 unsigned Offset = I * GPRSizeInBytes; 3748 SDValue StorePtr = DAG.getNode(ISD::ADD, DL, PtrTy, FIN, 3749 DAG.getConstant(Offset, DL, PtrTy)); 3750 SDValue Store = DAG.getStore(Chain, DL, DAG.getRegister(VReg, RegTy), 3751 StorePtr, MachinePointerInfo(FuncArg, Offset)); 3752 OutChains.push_back(Store); 3753 } 3754 } 3755 3756 // Copy byVal arg to registers and stack. 3757 void MipsTargetLowering::passByValArg( 3758 SDValue Chain, const SDLoc &DL, 3759 std::deque<std::pair<unsigned, SDValue>> &RegsToPass, 3760 SmallVectorImpl<SDValue> &MemOpChains, SDValue StackPtr, 3761 MachineFrameInfo &MFI, SelectionDAG &DAG, SDValue Arg, unsigned FirstReg, 3762 unsigned LastReg, const ISD::ArgFlagsTy &Flags, bool isLittle, 3763 const CCValAssign &VA) const { 3764 unsigned ByValSizeInBytes = Flags.getByValSize(); 3765 unsigned OffsetInBytes = 0; // From beginning of struct 3766 unsigned RegSizeInBytes = Subtarget.getGPRSizeInBytes(); 3767 unsigned Alignment = std::min(Flags.getByValAlign(), RegSizeInBytes); 3768 EVT PtrTy = getPointerTy(DAG.getDataLayout()), 3769 RegTy = MVT::getIntegerVT(RegSizeInBytes * 8); 3770 unsigned NumRegs = LastReg - FirstReg; 3771 3772 if (NumRegs) { 3773 ArrayRef<MCPhysReg> ArgRegs = ABI.GetByValArgRegs(); 3774 bool LeftoverBytes = (NumRegs * RegSizeInBytes > ByValSizeInBytes); 3775 unsigned I = 0; 3776 3777 // Copy words to registers. 3778 for (; I < NumRegs - LeftoverBytes; ++I, OffsetInBytes += RegSizeInBytes) { 3779 SDValue LoadPtr = DAG.getNode(ISD::ADD, DL, PtrTy, Arg, 3780 DAG.getConstant(OffsetInBytes, DL, PtrTy)); 3781 SDValue LoadVal = DAG.getLoad(RegTy, DL, Chain, LoadPtr, 3782 MachinePointerInfo(), Alignment); 3783 MemOpChains.push_back(LoadVal.getValue(1)); 3784 unsigned ArgReg = ArgRegs[FirstReg + I]; 3785 RegsToPass.push_back(std::make_pair(ArgReg, LoadVal)); 3786 } 3787 3788 // Return if the struct has been fully copied. 3789 if (ByValSizeInBytes == OffsetInBytes) 3790 return; 3791 3792 // Copy the remainder of the byval argument with sub-word loads and shifts. 3793 if (LeftoverBytes) { 3794 SDValue Val; 3795 3796 for (unsigned LoadSizeInBytes = RegSizeInBytes / 2, TotalBytesLoaded = 0; 3797 OffsetInBytes < ByValSizeInBytes; LoadSizeInBytes /= 2) { 3798 unsigned RemainingSizeInBytes = ByValSizeInBytes - OffsetInBytes; 3799 3800 if (RemainingSizeInBytes < LoadSizeInBytes) 3801 continue; 3802 3803 // Load subword. 3804 SDValue LoadPtr = DAG.getNode(ISD::ADD, DL, PtrTy, Arg, 3805 DAG.getConstant(OffsetInBytes, DL, 3806 PtrTy)); 3807 SDValue LoadVal = DAG.getExtLoad( 3808 ISD::ZEXTLOAD, DL, RegTy, Chain, LoadPtr, MachinePointerInfo(), 3809 MVT::getIntegerVT(LoadSizeInBytes * 8), Alignment); 3810 MemOpChains.push_back(LoadVal.getValue(1)); 3811 3812 // Shift the loaded value. 3813 unsigned Shamt; 3814 3815 if (isLittle) 3816 Shamt = TotalBytesLoaded * 8; 3817 else 3818 Shamt = (RegSizeInBytes - (TotalBytesLoaded + LoadSizeInBytes)) * 8; 3819 3820 SDValue Shift = DAG.getNode(ISD::SHL, DL, RegTy, LoadVal, 3821 DAG.getConstant(Shamt, DL, MVT::i32)); 3822 3823 if (Val.getNode()) 3824 Val = DAG.getNode(ISD::OR, DL, RegTy, Val, Shift); 3825 else 3826 Val = Shift; 3827 3828 OffsetInBytes += LoadSizeInBytes; 3829 TotalBytesLoaded += LoadSizeInBytes; 3830 Alignment = std::min(Alignment, LoadSizeInBytes); 3831 } 3832 3833 unsigned ArgReg = ArgRegs[FirstReg + I]; 3834 RegsToPass.push_back(std::make_pair(ArgReg, Val)); 3835 return; 3836 } 3837 } 3838 3839 // Copy remainder of byval arg to it with memcpy. 3840 unsigned MemCpySize = ByValSizeInBytes - OffsetInBytes; 3841 SDValue Src = DAG.getNode(ISD::ADD, DL, PtrTy, Arg, 3842 DAG.getConstant(OffsetInBytes, DL, PtrTy)); 3843 SDValue Dst = DAG.getNode(ISD::ADD, DL, PtrTy, StackPtr, 3844 DAG.getIntPtrConstant(VA.getLocMemOffset(), DL)); 3845 Chain = DAG.getMemcpy(Chain, DL, Dst, Src, 3846 DAG.getConstant(MemCpySize, DL, PtrTy), 3847 Alignment, /*isVolatile=*/false, /*AlwaysInline=*/false, 3848 /*isTailCall=*/false, 3849 MachinePointerInfo(), MachinePointerInfo()); 3850 MemOpChains.push_back(Chain); 3851 } 3852 3853 void MipsTargetLowering::writeVarArgRegs(std::vector<SDValue> &OutChains, 3854 SDValue Chain, const SDLoc &DL, 3855 SelectionDAG &DAG, 3856 CCState &State) const { 3857 ArrayRef<MCPhysReg> ArgRegs = ABI.GetVarArgRegs(); 3858 unsigned Idx = State.getFirstUnallocated(ArgRegs); 3859 unsigned RegSizeInBytes = Subtarget.getGPRSizeInBytes(); 3860 MVT RegTy = MVT::getIntegerVT(RegSizeInBytes * 8); 3861 const TargetRegisterClass *RC = getRegClassFor(RegTy); 3862 MachineFunction &MF = DAG.getMachineFunction(); 3863 MachineFrameInfo &MFI = MF.getFrameInfo(); 3864 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>(); 3865 3866 // Offset of the first variable argument from stack pointer. 3867 int VaArgOffset; 3868 3869 if (ArgRegs.size() == Idx) 3870 VaArgOffset = alignTo(State.getNextStackOffset(), RegSizeInBytes); 3871 else { 3872 VaArgOffset = 3873 (int)ABI.GetCalleeAllocdArgSizeInBytes(State.getCallingConv()) - 3874 (int)(RegSizeInBytes * (ArgRegs.size() - Idx)); 3875 } 3876 3877 // Record the frame index of the first variable argument 3878 // which is a value necessary to VASTART. 3879 int FI = MFI.CreateFixedObject(RegSizeInBytes, VaArgOffset, true); 3880 MipsFI->setVarArgsFrameIndex(FI); 3881 3882 // Copy the integer registers that have not been used for argument passing 3883 // to the argument register save area. For O32, the save area is allocated 3884 // in the caller's stack frame, while for N32/64, it is allocated in the 3885 // callee's stack frame. 3886 for (unsigned I = Idx; I < ArgRegs.size(); 3887 ++I, VaArgOffset += RegSizeInBytes) { 3888 unsigned Reg = addLiveIn(MF, ArgRegs[I], RC); 3889 SDValue ArgValue = DAG.getCopyFromReg(Chain, DL, Reg, RegTy); 3890 FI = MFI.CreateFixedObject(RegSizeInBytes, VaArgOffset, true); 3891 SDValue PtrOff = DAG.getFrameIndex(FI, getPointerTy(DAG.getDataLayout())); 3892 SDValue Store = 3893 DAG.getStore(Chain, DL, ArgValue, PtrOff, MachinePointerInfo()); 3894 cast<StoreSDNode>(Store.getNode())->getMemOperand()->setValue( 3895 (Value *)nullptr); 3896 OutChains.push_back(Store); 3897 } 3898 } 3899 3900 void MipsTargetLowering::HandleByVal(CCState *State, unsigned &Size, 3901 unsigned Align) const { 3902 const TargetFrameLowering *TFL = Subtarget.getFrameLowering(); 3903 3904 assert(Size && "Byval argument's size shouldn't be 0."); 3905 3906 Align = std::min(Align, TFL->getStackAlignment()); 3907 3908 unsigned FirstReg = 0; 3909 unsigned NumRegs = 0; 3910 3911 if (State->getCallingConv() != CallingConv::Fast) { 3912 unsigned RegSizeInBytes = Subtarget.getGPRSizeInBytes(); 3913 ArrayRef<MCPhysReg> IntArgRegs = ABI.GetByValArgRegs(); 3914 // FIXME: The O32 case actually describes no shadow registers. 3915 const MCPhysReg *ShadowRegs = 3916 ABI.IsO32() ? IntArgRegs.data() : Mips64DPRegs; 3917 3918 // We used to check the size as well but we can't do that anymore since 3919 // CCState::HandleByVal() rounds up the size after calling this function. 3920 assert(!(Align % RegSizeInBytes) && 3921 "Byval argument's alignment should be a multiple of" 3922 "RegSizeInBytes."); 3923 3924 FirstReg = State->getFirstUnallocated(IntArgRegs); 3925 3926 // If Align > RegSizeInBytes, the first arg register must be even. 3927 // FIXME: This condition happens to do the right thing but it's not the 3928 // right way to test it. We want to check that the stack frame offset 3929 // of the register is aligned. 3930 if ((Align > RegSizeInBytes) && (FirstReg % 2)) { 3931 State->AllocateReg(IntArgRegs[FirstReg], ShadowRegs[FirstReg]); 3932 ++FirstReg; 3933 } 3934 3935 // Mark the registers allocated. 3936 Size = alignTo(Size, RegSizeInBytes); 3937 for (unsigned I = FirstReg; Size > 0 && (I < IntArgRegs.size()); 3938 Size -= RegSizeInBytes, ++I, ++NumRegs) 3939 State->AllocateReg(IntArgRegs[I], ShadowRegs[I]); 3940 } 3941 3942 State->addInRegsParamInfo(FirstReg, FirstReg + NumRegs); 3943 } 3944 3945 MachineBasicBlock *MipsTargetLowering::emitPseudoSELECT(MachineInstr &MI, 3946 MachineBasicBlock *BB, 3947 bool isFPCmp, 3948 unsigned Opc) const { 3949 assert(!(Subtarget.hasMips4() || Subtarget.hasMips32()) && 3950 "Subtarget already supports SELECT nodes with the use of" 3951 "conditional-move instructions."); 3952 3953 const TargetInstrInfo *TII = 3954 Subtarget.getInstrInfo(); 3955 DebugLoc DL = MI.getDebugLoc(); 3956 3957 // To "insert" a SELECT instruction, we actually have to insert the 3958 // diamond control-flow pattern. The incoming instruction knows the 3959 // destination vreg to set, the condition code register to branch on, the 3960 // true/false values to select between, and a branch opcode to use. 3961 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 3962 MachineFunction::iterator It = ++BB->getIterator(); 3963 3964 // thisMBB: 3965 // ... 3966 // TrueVal = ... 3967 // setcc r1, r2, r3 3968 // bNE r1, r0, copy1MBB 3969 // fallthrough --> copy0MBB 3970 MachineBasicBlock *thisMBB = BB; 3971 MachineFunction *F = BB->getParent(); 3972 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB); 3973 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB); 3974 F->insert(It, copy0MBB); 3975 F->insert(It, sinkMBB); 3976 3977 // Transfer the remainder of BB and its successor edges to sinkMBB. 3978 sinkMBB->splice(sinkMBB->begin(), BB, 3979 std::next(MachineBasicBlock::iterator(MI)), BB->end()); 3980 sinkMBB->transferSuccessorsAndUpdatePHIs(BB); 3981 3982 // Next, add the true and fallthrough blocks as its successors. 3983 BB->addSuccessor(copy0MBB); 3984 BB->addSuccessor(sinkMBB); 3985 3986 if (isFPCmp) { 3987 // bc1[tf] cc, sinkMBB 3988 BuildMI(BB, DL, TII->get(Opc)) 3989 .addReg(MI.getOperand(1).getReg()) 3990 .addMBB(sinkMBB); 3991 } else { 3992 // bne rs, $0, sinkMBB 3993 BuildMI(BB, DL, TII->get(Opc)) 3994 .addReg(MI.getOperand(1).getReg()) 3995 .addReg(Mips::ZERO) 3996 .addMBB(sinkMBB); 3997 } 3998 3999 // copy0MBB: 4000 // %FalseValue = ... 4001 // # fallthrough to sinkMBB 4002 BB = copy0MBB; 4003 4004 // Update machine-CFG edges 4005 BB->addSuccessor(sinkMBB); 4006 4007 // sinkMBB: 4008 // %Result = phi [ %TrueValue, thisMBB ], [ %FalseValue, copy0MBB ] 4009 // ... 4010 BB = sinkMBB; 4011 4012 BuildMI(*BB, BB->begin(), DL, TII->get(Mips::PHI), MI.getOperand(0).getReg()) 4013 .addReg(MI.getOperand(2).getReg()) 4014 .addMBB(thisMBB) 4015 .addReg(MI.getOperand(3).getReg()) 4016 .addMBB(copy0MBB); 4017 4018 MI.eraseFromParent(); // The pseudo instruction is gone now. 4019 4020 return BB; 4021 } 4022 4023 // FIXME? Maybe this could be a TableGen attribute on some registers and 4024 // this table could be generated automatically from RegInfo. 4025 unsigned MipsTargetLowering::getRegisterByName(const char* RegName, EVT VT, 4026 SelectionDAG &DAG) const { 4027 // Named registers is expected to be fairly rare. For now, just support $28 4028 // since the linux kernel uses it. 4029 if (Subtarget.isGP64bit()) { 4030 unsigned Reg = StringSwitch<unsigned>(RegName) 4031 .Case("$28", Mips::GP_64) 4032 .Default(0); 4033 if (Reg) 4034 return Reg; 4035 } else { 4036 unsigned Reg = StringSwitch<unsigned>(RegName) 4037 .Case("$28", Mips::GP) 4038 .Default(0); 4039 if (Reg) 4040 return Reg; 4041 } 4042 report_fatal_error("Invalid register name global variable"); 4043 } 4044