1 //===-- MipsISelLowering.cpp - Mips DAG Lowering Implementation -----------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file defines the interfaces that Mips uses to lower LLVM code into a 11 // selection DAG. 12 // 13 //===----------------------------------------------------------------------===// 14 15 #define DEBUG_TYPE "mips-lower" 16 #include "MipsISelLowering.h" 17 #include "MipsMachineFunction.h" 18 #include "MipsTargetMachine.h" 19 #include "MipsTargetObjectFile.h" 20 #include "MipsSubtarget.h" 21 #include "llvm/DerivedTypes.h" 22 #include "llvm/Function.h" 23 #include "llvm/GlobalVariable.h" 24 #include "llvm/Intrinsics.h" 25 #include "llvm/CallingConv.h" 26 #include "InstPrinter/MipsInstPrinter.h" 27 #include "llvm/CodeGen/CallingConvLower.h" 28 #include "llvm/CodeGen/MachineFrameInfo.h" 29 #include "llvm/CodeGen/MachineFunction.h" 30 #include "llvm/CodeGen/MachineInstrBuilder.h" 31 #include "llvm/CodeGen/MachineRegisterInfo.h" 32 #include "llvm/CodeGen/SelectionDAGISel.h" 33 #include "llvm/CodeGen/ValueTypes.h" 34 #include "llvm/Support/Debug.h" 35 #include "llvm/Support/ErrorHandling.h" 36 using namespace llvm; 37 38 // If I is a shifted mask, set the size (Size) and the first bit of the 39 // mask (Pos), and return true. 40 // For example, if I is 0x003ff800, (Pos, Size) = (11, 11). 41 static bool IsShiftedMask(uint64_t I, uint64_t &Pos, uint64_t &Size) { 42 if (!isUInt<32>(I) || !isShiftedMask_32(I)) 43 return false; 44 45 Size = CountPopulation_32(I); 46 Pos = CountTrailingZeros_32(I); 47 return true; 48 } 49 50 const char *MipsTargetLowering::getTargetNodeName(unsigned Opcode) const { 51 switch (Opcode) { 52 case MipsISD::JmpLink: return "MipsISD::JmpLink"; 53 case MipsISD::Hi: return "MipsISD::Hi"; 54 case MipsISD::Lo: return "MipsISD::Lo"; 55 case MipsISD::GPRel: return "MipsISD::GPRel"; 56 case MipsISD::TlsGd: return "MipsISD::TlsGd"; 57 case MipsISD::TprelHi: return "MipsISD::TprelHi"; 58 case MipsISD::TprelLo: return "MipsISD::TprelLo"; 59 case MipsISD::ThreadPointer: return "MipsISD::ThreadPointer"; 60 case MipsISD::Ret: return "MipsISD::Ret"; 61 case MipsISD::FPBrcond: return "MipsISD::FPBrcond"; 62 case MipsISD::FPCmp: return "MipsISD::FPCmp"; 63 case MipsISD::CMovFP_T: return "MipsISD::CMovFP_T"; 64 case MipsISD::CMovFP_F: return "MipsISD::CMovFP_F"; 65 case MipsISD::FPRound: return "MipsISD::FPRound"; 66 case MipsISD::MAdd: return "MipsISD::MAdd"; 67 case MipsISD::MAddu: return "MipsISD::MAddu"; 68 case MipsISD::MSub: return "MipsISD::MSub"; 69 case MipsISD::MSubu: return "MipsISD::MSubu"; 70 case MipsISD::DivRem: return "MipsISD::DivRem"; 71 case MipsISD::DivRemU: return "MipsISD::DivRemU"; 72 case MipsISD::BuildPairF64: return "MipsISD::BuildPairF64"; 73 case MipsISD::ExtractElementF64: return "MipsISD::ExtractElementF64"; 74 case MipsISD::WrapperPIC: return "MipsISD::WrapperPIC"; 75 case MipsISD::DynAlloc: return "MipsISD::DynAlloc"; 76 case MipsISD::Sync: return "MipsISD::Sync"; 77 case MipsISD::Ext: return "MipsISD::Ext"; 78 case MipsISD::Ins: return "MipsISD::Ins"; 79 default: return NULL; 80 } 81 } 82 83 MipsTargetLowering:: 84 MipsTargetLowering(MipsTargetMachine &TM) 85 : TargetLowering(TM, new MipsTargetObjectFile()), 86 Subtarget(&TM.getSubtarget<MipsSubtarget>()), 87 HasMips64(Subtarget->hasMips64()) { 88 89 // Mips does not have i1 type, so use i32 for 90 // setcc operations results (slt, sgt, ...). 91 setBooleanContents(ZeroOrOneBooleanContent); 92 setBooleanVectorContents(ZeroOrOneBooleanContent); // FIXME: Is this correct? 93 94 // Set up the register classes 95 addRegisterClass(MVT::i32, Mips::CPURegsRegisterClass); 96 addRegisterClass(MVT::f32, Mips::FGR32RegisterClass); 97 98 if (HasMips64) 99 addRegisterClass(MVT::i64, Mips::CPU64RegsRegisterClass); 100 101 // When dealing with single precision only, use libcalls 102 if (!Subtarget->isSingleFloat()) { 103 if (HasMips64) 104 addRegisterClass(MVT::f64, Mips::FGR64RegisterClass); 105 else 106 addRegisterClass(MVT::f64, Mips::AFGR64RegisterClass); 107 } 108 109 // Load extented operations for i1 types must be promoted 110 setLoadExtAction(ISD::EXTLOAD, MVT::i1, Promote); 111 setLoadExtAction(ISD::ZEXTLOAD, MVT::i1, Promote); 112 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote); 113 114 // MIPS doesn't have extending float->double load/store 115 setLoadExtAction(ISD::EXTLOAD, MVT::f32, Expand); 116 setTruncStoreAction(MVT::f64, MVT::f32, Expand); 117 118 // Used by legalize types to correctly generate the setcc result. 119 // Without this, every float setcc comes with a AND/OR with the result, 120 // we don't want this, since the fpcmp result goes to a flag register, 121 // which is used implicitly by brcond and select operations. 122 AddPromotedToType(ISD::SETCC, MVT::i1, MVT::i32); 123 124 // Mips Custom Operations 125 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom); 126 setOperationAction(ISD::BlockAddress, MVT::i32, Custom); 127 setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom); 128 setOperationAction(ISD::JumpTable, MVT::i32, Custom); 129 setOperationAction(ISD::ConstantPool, MVT::i32, Custom); 130 setOperationAction(ISD::SELECT, MVT::f32, Custom); 131 setOperationAction(ISD::SELECT, MVT::f64, Custom); 132 setOperationAction(ISD::SELECT, MVT::i32, Custom); 133 setOperationAction(ISD::BRCOND, MVT::Other, Custom); 134 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Custom); 135 setOperationAction(ISD::VASTART, MVT::Other, Custom); 136 137 setOperationAction(ISD::SDIV, MVT::i32, Expand); 138 setOperationAction(ISD::SREM, MVT::i32, Expand); 139 setOperationAction(ISD::UDIV, MVT::i32, Expand); 140 setOperationAction(ISD::UREM, MVT::i32, Expand); 141 142 // Operations not directly supported by Mips. 143 setOperationAction(ISD::BR_JT, MVT::Other, Expand); 144 setOperationAction(ISD::BR_CC, MVT::Other, Expand); 145 setOperationAction(ISD::SELECT_CC, MVT::Other, Expand); 146 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand); 147 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand); 148 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand); 149 setOperationAction(ISD::CTPOP, MVT::i32, Expand); 150 setOperationAction(ISD::CTTZ, MVT::i32, Expand); 151 setOperationAction(ISD::ROTL, MVT::i32, Expand); 152 setOperationAction(ISD::ROTL, MVT::i64, Expand); 153 154 if (!Subtarget->hasMips32r2()) 155 setOperationAction(ISD::ROTR, MVT::i32, Expand); 156 157 if (!Subtarget->hasMips64r2()) 158 setOperationAction(ISD::ROTR, MVT::i64, Expand); 159 160 setOperationAction(ISD::SHL_PARTS, MVT::i32, Expand); 161 setOperationAction(ISD::SRA_PARTS, MVT::i32, Expand); 162 setOperationAction(ISD::SRL_PARTS, MVT::i32, Expand); 163 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom); 164 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom); 165 setOperationAction(ISD::FSIN, MVT::f32, Expand); 166 setOperationAction(ISD::FSIN, MVT::f64, Expand); 167 setOperationAction(ISD::FCOS, MVT::f32, Expand); 168 setOperationAction(ISD::FCOS, MVT::f64, Expand); 169 setOperationAction(ISD::FPOWI, MVT::f32, Expand); 170 setOperationAction(ISD::FPOW, MVT::f32, Expand); 171 setOperationAction(ISD::FPOW, MVT::f64, Expand); 172 setOperationAction(ISD::FLOG, MVT::f32, Expand); 173 setOperationAction(ISD::FLOG2, MVT::f32, Expand); 174 setOperationAction(ISD::FLOG10, MVT::f32, Expand); 175 setOperationAction(ISD::FEXP, MVT::f32, Expand); 176 setOperationAction(ISD::FMA, MVT::f32, Expand); 177 setOperationAction(ISD::FMA, MVT::f64, Expand); 178 179 setOperationAction(ISD::EXCEPTIONADDR, MVT::i32, Expand); 180 setOperationAction(ISD::EHSELECTION, MVT::i32, Expand); 181 182 setOperationAction(ISD::VAARG, MVT::Other, Expand); 183 setOperationAction(ISD::VACOPY, MVT::Other, Expand); 184 setOperationAction(ISD::VAEND, MVT::Other, Expand); 185 186 // Use the default for now 187 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand); 188 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand); 189 190 setOperationAction(ISD::MEMBARRIER, MVT::Other, Custom); 191 setOperationAction(ISD::ATOMIC_FENCE, MVT::Other, Custom); 192 193 setOperationAction(ISD::ATOMIC_LOAD, MVT::i32, Expand); 194 setOperationAction(ISD::ATOMIC_STORE, MVT::i32, Expand); 195 196 setInsertFencesForAtomic(true); 197 198 if (Subtarget->isSingleFloat()) 199 setOperationAction(ISD::SELECT_CC, MVT::f64, Expand); 200 201 if (!Subtarget->hasSEInReg()) { 202 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8, Expand); 203 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand); 204 } 205 206 if (!Subtarget->hasBitCount()) 207 setOperationAction(ISD::CTLZ, MVT::i32, Expand); 208 209 if (!Subtarget->hasSwap()) 210 setOperationAction(ISD::BSWAP, MVT::i32, Expand); 211 212 setTargetDAGCombine(ISD::ADDE); 213 setTargetDAGCombine(ISD::SUBE); 214 setTargetDAGCombine(ISD::SDIVREM); 215 setTargetDAGCombine(ISD::UDIVREM); 216 setTargetDAGCombine(ISD::SETCC); 217 setTargetDAGCombine(ISD::AND); 218 setTargetDAGCombine(ISD::OR); 219 220 setMinFunctionAlignment(2); 221 222 setStackPointerRegisterToSaveRestore(Mips::SP); 223 computeRegisterProperties(); 224 225 setExceptionPointerRegister(Mips::A0); 226 setExceptionSelectorRegister(Mips::A1); 227 } 228 229 bool MipsTargetLowering::allowsUnalignedMemoryAccesses(EVT VT) const { 230 MVT::SimpleValueType SVT = VT.getSimpleVT().SimpleTy; 231 return SVT == MVT::i32 || SVT == MVT::i16; 232 } 233 234 EVT MipsTargetLowering::getSetCCResultType(EVT VT) const { 235 return MVT::i32; 236 } 237 238 // SelectMadd - 239 // Transforms a subgraph in CurDAG if the following pattern is found: 240 // (addc multLo, Lo0), (adde multHi, Hi0), 241 // where, 242 // multHi/Lo: product of multiplication 243 // Lo0: initial value of Lo register 244 // Hi0: initial value of Hi register 245 // Return true if pattern matching was successful. 246 static bool SelectMadd(SDNode* ADDENode, SelectionDAG* CurDAG) { 247 // ADDENode's second operand must be a flag output of an ADDC node in order 248 // for the matching to be successful. 249 SDNode* ADDCNode = ADDENode->getOperand(2).getNode(); 250 251 if (ADDCNode->getOpcode() != ISD::ADDC) 252 return false; 253 254 SDValue MultHi = ADDENode->getOperand(0); 255 SDValue MultLo = ADDCNode->getOperand(0); 256 SDNode* MultNode = MultHi.getNode(); 257 unsigned MultOpc = MultHi.getOpcode(); 258 259 // MultHi and MultLo must be generated by the same node, 260 if (MultLo.getNode() != MultNode) 261 return false; 262 263 // and it must be a multiplication. 264 if (MultOpc != ISD::SMUL_LOHI && MultOpc != ISD::UMUL_LOHI) 265 return false; 266 267 // MultLo amd MultHi must be the first and second output of MultNode 268 // respectively. 269 if (MultHi.getResNo() != 1 || MultLo.getResNo() != 0) 270 return false; 271 272 // Transform this to a MADD only if ADDENode and ADDCNode are the only users 273 // of the values of MultNode, in which case MultNode will be removed in later 274 // phases. 275 // If there exist users other than ADDENode or ADDCNode, this function returns 276 // here, which will result in MultNode being mapped to a single MULT 277 // instruction node rather than a pair of MULT and MADD instructions being 278 // produced. 279 if (!MultHi.hasOneUse() || !MultLo.hasOneUse()) 280 return false; 281 282 SDValue Chain = CurDAG->getEntryNode(); 283 DebugLoc dl = ADDENode->getDebugLoc(); 284 285 // create MipsMAdd(u) node 286 MultOpc = MultOpc == ISD::UMUL_LOHI ? MipsISD::MAddu : MipsISD::MAdd; 287 288 SDValue MAdd = CurDAG->getNode(MultOpc, dl, 289 MVT::Glue, 290 MultNode->getOperand(0),// Factor 0 291 MultNode->getOperand(1),// Factor 1 292 ADDCNode->getOperand(1),// Lo0 293 ADDENode->getOperand(1));// Hi0 294 295 // create CopyFromReg nodes 296 SDValue CopyFromLo = CurDAG->getCopyFromReg(Chain, dl, Mips::LO, MVT::i32, 297 MAdd); 298 SDValue CopyFromHi = CurDAG->getCopyFromReg(CopyFromLo.getValue(1), dl, 299 Mips::HI, MVT::i32, 300 CopyFromLo.getValue(2)); 301 302 // replace uses of adde and addc here 303 if (!SDValue(ADDCNode, 0).use_empty()) 304 CurDAG->ReplaceAllUsesOfValueWith(SDValue(ADDCNode, 0), CopyFromLo); 305 306 if (!SDValue(ADDENode, 0).use_empty()) 307 CurDAG->ReplaceAllUsesOfValueWith(SDValue(ADDENode, 0), CopyFromHi); 308 309 return true; 310 } 311 312 // SelectMsub - 313 // Transforms a subgraph in CurDAG if the following pattern is found: 314 // (addc Lo0, multLo), (sube Hi0, multHi), 315 // where, 316 // multHi/Lo: product of multiplication 317 // Lo0: initial value of Lo register 318 // Hi0: initial value of Hi register 319 // Return true if pattern matching was successful. 320 static bool SelectMsub(SDNode* SUBENode, SelectionDAG* CurDAG) { 321 // SUBENode's second operand must be a flag output of an SUBC node in order 322 // for the matching to be successful. 323 SDNode* SUBCNode = SUBENode->getOperand(2).getNode(); 324 325 if (SUBCNode->getOpcode() != ISD::SUBC) 326 return false; 327 328 SDValue MultHi = SUBENode->getOperand(1); 329 SDValue MultLo = SUBCNode->getOperand(1); 330 SDNode* MultNode = MultHi.getNode(); 331 unsigned MultOpc = MultHi.getOpcode(); 332 333 // MultHi and MultLo must be generated by the same node, 334 if (MultLo.getNode() != MultNode) 335 return false; 336 337 // and it must be a multiplication. 338 if (MultOpc != ISD::SMUL_LOHI && MultOpc != ISD::UMUL_LOHI) 339 return false; 340 341 // MultLo amd MultHi must be the first and second output of MultNode 342 // respectively. 343 if (MultHi.getResNo() != 1 || MultLo.getResNo() != 0) 344 return false; 345 346 // Transform this to a MSUB only if SUBENode and SUBCNode are the only users 347 // of the values of MultNode, in which case MultNode will be removed in later 348 // phases. 349 // If there exist users other than SUBENode or SUBCNode, this function returns 350 // here, which will result in MultNode being mapped to a single MULT 351 // instruction node rather than a pair of MULT and MSUB instructions being 352 // produced. 353 if (!MultHi.hasOneUse() || !MultLo.hasOneUse()) 354 return false; 355 356 SDValue Chain = CurDAG->getEntryNode(); 357 DebugLoc dl = SUBENode->getDebugLoc(); 358 359 // create MipsSub(u) node 360 MultOpc = MultOpc == ISD::UMUL_LOHI ? MipsISD::MSubu : MipsISD::MSub; 361 362 SDValue MSub = CurDAG->getNode(MultOpc, dl, 363 MVT::Glue, 364 MultNode->getOperand(0),// Factor 0 365 MultNode->getOperand(1),// Factor 1 366 SUBCNode->getOperand(0),// Lo0 367 SUBENode->getOperand(0));// Hi0 368 369 // create CopyFromReg nodes 370 SDValue CopyFromLo = CurDAG->getCopyFromReg(Chain, dl, Mips::LO, MVT::i32, 371 MSub); 372 SDValue CopyFromHi = CurDAG->getCopyFromReg(CopyFromLo.getValue(1), dl, 373 Mips::HI, MVT::i32, 374 CopyFromLo.getValue(2)); 375 376 // replace uses of sube and subc here 377 if (!SDValue(SUBCNode, 0).use_empty()) 378 CurDAG->ReplaceAllUsesOfValueWith(SDValue(SUBCNode, 0), CopyFromLo); 379 380 if (!SDValue(SUBENode, 0).use_empty()) 381 CurDAG->ReplaceAllUsesOfValueWith(SDValue(SUBENode, 0), CopyFromHi); 382 383 return true; 384 } 385 386 static SDValue PerformADDECombine(SDNode *N, SelectionDAG& DAG, 387 TargetLowering::DAGCombinerInfo &DCI, 388 const MipsSubtarget* Subtarget) { 389 if (DCI.isBeforeLegalize()) 390 return SDValue(); 391 392 if (Subtarget->hasMips32() && SelectMadd(N, &DAG)) 393 return SDValue(N, 0); 394 395 return SDValue(); 396 } 397 398 static SDValue PerformSUBECombine(SDNode *N, SelectionDAG& DAG, 399 TargetLowering::DAGCombinerInfo &DCI, 400 const MipsSubtarget* Subtarget) { 401 if (DCI.isBeforeLegalize()) 402 return SDValue(); 403 404 if (Subtarget->hasMips32() && SelectMsub(N, &DAG)) 405 return SDValue(N, 0); 406 407 return SDValue(); 408 } 409 410 static SDValue PerformDivRemCombine(SDNode *N, SelectionDAG& DAG, 411 TargetLowering::DAGCombinerInfo &DCI, 412 const MipsSubtarget* Subtarget) { 413 if (DCI.isBeforeLegalizeOps()) 414 return SDValue(); 415 416 unsigned opc = N->getOpcode() == ISD::SDIVREM ? MipsISD::DivRem : 417 MipsISD::DivRemU; 418 DebugLoc dl = N->getDebugLoc(); 419 420 SDValue DivRem = DAG.getNode(opc, dl, MVT::Glue, 421 N->getOperand(0), N->getOperand(1)); 422 SDValue InChain = DAG.getEntryNode(); 423 SDValue InGlue = DivRem; 424 425 // insert MFLO 426 if (N->hasAnyUseOfValue(0)) { 427 SDValue CopyFromLo = DAG.getCopyFromReg(InChain, dl, Mips::LO, MVT::i32, 428 InGlue); 429 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), CopyFromLo); 430 InChain = CopyFromLo.getValue(1); 431 InGlue = CopyFromLo.getValue(2); 432 } 433 434 // insert MFHI 435 if (N->hasAnyUseOfValue(1)) { 436 SDValue CopyFromHi = DAG.getCopyFromReg(InChain, dl, 437 Mips::HI, MVT::i32, InGlue); 438 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), CopyFromHi); 439 } 440 441 return SDValue(); 442 } 443 444 static Mips::CondCode FPCondCCodeToFCC(ISD::CondCode CC) { 445 switch (CC) { 446 default: llvm_unreachable("Unknown fp condition code!"); 447 case ISD::SETEQ: 448 case ISD::SETOEQ: return Mips::FCOND_OEQ; 449 case ISD::SETUNE: return Mips::FCOND_UNE; 450 case ISD::SETLT: 451 case ISD::SETOLT: return Mips::FCOND_OLT; 452 case ISD::SETGT: 453 case ISD::SETOGT: return Mips::FCOND_OGT; 454 case ISD::SETLE: 455 case ISD::SETOLE: return Mips::FCOND_OLE; 456 case ISD::SETGE: 457 case ISD::SETOGE: return Mips::FCOND_OGE; 458 case ISD::SETULT: return Mips::FCOND_ULT; 459 case ISD::SETULE: return Mips::FCOND_ULE; 460 case ISD::SETUGT: return Mips::FCOND_UGT; 461 case ISD::SETUGE: return Mips::FCOND_UGE; 462 case ISD::SETUO: return Mips::FCOND_UN; 463 case ISD::SETO: return Mips::FCOND_OR; 464 case ISD::SETNE: 465 case ISD::SETONE: return Mips::FCOND_ONE; 466 case ISD::SETUEQ: return Mips::FCOND_UEQ; 467 } 468 } 469 470 471 // Returns true if condition code has to be inverted. 472 static bool InvertFPCondCode(Mips::CondCode CC) { 473 if (CC >= Mips::FCOND_F && CC <= Mips::FCOND_NGT) 474 return false; 475 476 if (CC >= Mips::FCOND_T && CC <= Mips::FCOND_GT) 477 return true; 478 479 assert(false && "Illegal Condition Code"); 480 return false; 481 } 482 483 // Creates and returns an FPCmp node from a setcc node. 484 // Returns Op if setcc is not a floating point comparison. 485 static SDValue CreateFPCmp(SelectionDAG& DAG, const SDValue& Op) { 486 // must be a SETCC node 487 if (Op.getOpcode() != ISD::SETCC) 488 return Op; 489 490 SDValue LHS = Op.getOperand(0); 491 492 if (!LHS.getValueType().isFloatingPoint()) 493 return Op; 494 495 SDValue RHS = Op.getOperand(1); 496 DebugLoc dl = Op.getDebugLoc(); 497 498 // Assume the 3rd operand is a CondCodeSDNode. Add code to check the type of 499 // node if necessary. 500 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get(); 501 502 return DAG.getNode(MipsISD::FPCmp, dl, MVT::Glue, LHS, RHS, 503 DAG.getConstant(FPCondCCodeToFCC(CC), MVT::i32)); 504 } 505 506 // Creates and returns a CMovFPT/F node. 507 static SDValue CreateCMovFP(SelectionDAG& DAG, SDValue Cond, SDValue True, 508 SDValue False, DebugLoc DL) { 509 bool invert = InvertFPCondCode((Mips::CondCode) 510 cast<ConstantSDNode>(Cond.getOperand(2)) 511 ->getSExtValue()); 512 513 return DAG.getNode((invert ? MipsISD::CMovFP_F : MipsISD::CMovFP_T), DL, 514 True.getValueType(), True, False, Cond); 515 } 516 517 static SDValue PerformSETCCCombine(SDNode *N, SelectionDAG& DAG, 518 TargetLowering::DAGCombinerInfo &DCI, 519 const MipsSubtarget* Subtarget) { 520 if (DCI.isBeforeLegalizeOps()) 521 return SDValue(); 522 523 SDValue Cond = CreateFPCmp(DAG, SDValue(N, 0)); 524 525 if (Cond.getOpcode() != MipsISD::FPCmp) 526 return SDValue(); 527 528 SDValue True = DAG.getConstant(1, MVT::i32); 529 SDValue False = DAG.getConstant(0, MVT::i32); 530 531 return CreateCMovFP(DAG, Cond, True, False, N->getDebugLoc()); 532 } 533 534 static SDValue PerformANDCombine(SDNode *N, SelectionDAG& DAG, 535 TargetLowering::DAGCombinerInfo &DCI, 536 const MipsSubtarget* Subtarget) { 537 // Pattern match EXT. 538 // $dst = and ((sra or srl) $src , pos), (2**size - 1) 539 // => ext $dst, $src, size, pos 540 if (DCI.isBeforeLegalizeOps() || !Subtarget->hasMips32r2()) 541 return SDValue(); 542 543 SDValue ShiftRight = N->getOperand(0), Mask = N->getOperand(1); 544 545 // Op's first operand must be a shift right. 546 if (ShiftRight.getOpcode() != ISD::SRA && ShiftRight.getOpcode() != ISD::SRL) 547 return SDValue(); 548 549 // The second operand of the shift must be an immediate. 550 uint64_t Pos; 551 ConstantSDNode *CN; 552 if (!(CN = dyn_cast<ConstantSDNode>(ShiftRight.getOperand(1)))) 553 return SDValue(); 554 555 Pos = CN->getZExtValue(); 556 557 uint64_t SMPos, SMSize; 558 // Op's second operand must be a shifted mask. 559 if (!(CN = dyn_cast<ConstantSDNode>(Mask)) || 560 !IsShiftedMask(CN->getZExtValue(), SMPos, SMSize)) 561 return SDValue(); 562 563 // Return if the shifted mask does not start at bit 0 or the sum of its size 564 // and Pos exceeds the word's size. 565 if (SMPos != 0 || Pos + SMSize > 32) 566 return SDValue(); 567 568 return DAG.getNode(MipsISD::Ext, N->getDebugLoc(), MVT::i32, 569 ShiftRight.getOperand(0), 570 DAG.getConstant(Pos, MVT::i32), 571 DAG.getConstant(SMSize, MVT::i32)); 572 } 573 574 static SDValue PerformORCombine(SDNode *N, SelectionDAG& DAG, 575 TargetLowering::DAGCombinerInfo &DCI, 576 const MipsSubtarget* Subtarget) { 577 // Pattern match INS. 578 // $dst = or (and $src1 , mask0), (and (shl $src, pos), mask1), 579 // where mask1 = (2**size - 1) << pos, mask0 = ~mask1 580 // => ins $dst, $src, size, pos, $src1 581 if (DCI.isBeforeLegalizeOps() || !Subtarget->hasMips32r2()) 582 return SDValue(); 583 584 SDValue And0 = N->getOperand(0), And1 = N->getOperand(1); 585 uint64_t SMPos0, SMSize0, SMPos1, SMSize1; 586 ConstantSDNode *CN; 587 588 // See if Op's first operand matches (and $src1 , mask0). 589 if (And0.getOpcode() != ISD::AND) 590 return SDValue(); 591 592 if (!(CN = dyn_cast<ConstantSDNode>(And0.getOperand(1))) || 593 !IsShiftedMask(~CN->getSExtValue(), SMPos0, SMSize0)) 594 return SDValue(); 595 596 // See if Op's second operand matches (and (shl $src, pos), mask1). 597 if (And1.getOpcode() != ISD::AND) 598 return SDValue(); 599 600 if (!(CN = dyn_cast<ConstantSDNode>(And1.getOperand(1))) || 601 !IsShiftedMask(CN->getZExtValue(), SMPos1, SMSize1)) 602 return SDValue(); 603 604 // The shift masks must have the same position and size. 605 if (SMPos0 != SMPos1 || SMSize0 != SMSize1) 606 return SDValue(); 607 608 SDValue Shl = And1.getOperand(0); 609 if (Shl.getOpcode() != ISD::SHL) 610 return SDValue(); 611 612 if (!(CN = dyn_cast<ConstantSDNode>(Shl.getOperand(1)))) 613 return SDValue(); 614 615 unsigned Shamt = CN->getZExtValue(); 616 617 // Return if the shift amount and the first bit position of mask are not the 618 // same. 619 if (Shamt != SMPos0) 620 return SDValue(); 621 622 return DAG.getNode(MipsISD::Ins, N->getDebugLoc(), MVT::i32, 623 Shl.getOperand(0), 624 DAG.getConstant(SMPos0, MVT::i32), 625 DAG.getConstant(SMSize0, MVT::i32), 626 And0.getOperand(0)); 627 } 628 629 SDValue MipsTargetLowering::PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) 630 const { 631 SelectionDAG &DAG = DCI.DAG; 632 unsigned opc = N->getOpcode(); 633 634 switch (opc) { 635 default: break; 636 case ISD::ADDE: 637 return PerformADDECombine(N, DAG, DCI, Subtarget); 638 case ISD::SUBE: 639 return PerformSUBECombine(N, DAG, DCI, Subtarget); 640 case ISD::SDIVREM: 641 case ISD::UDIVREM: 642 return PerformDivRemCombine(N, DAG, DCI, Subtarget); 643 case ISD::SETCC: 644 return PerformSETCCCombine(N, DAG, DCI, Subtarget); 645 case ISD::AND: 646 return PerformANDCombine(N, DAG, DCI, Subtarget); 647 case ISD::OR: 648 return PerformORCombine(N, DAG, DCI, Subtarget); 649 } 650 651 return SDValue(); 652 } 653 654 SDValue MipsTargetLowering:: 655 LowerOperation(SDValue Op, SelectionDAG &DAG) const 656 { 657 switch (Op.getOpcode()) 658 { 659 case ISD::BRCOND: return LowerBRCOND(Op, DAG); 660 case ISD::ConstantPool: return LowerConstantPool(Op, DAG); 661 case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG); 662 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG); 663 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG); 664 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG); 665 case ISD::JumpTable: return LowerJumpTable(Op, DAG); 666 case ISD::SELECT: return LowerSELECT(Op, DAG); 667 case ISD::VASTART: return LowerVASTART(Op, DAG); 668 case ISD::FCOPYSIGN: return LowerFCOPYSIGN(Op, DAG); 669 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG); 670 case ISD::MEMBARRIER: return LowerMEMBARRIER(Op, DAG); 671 case ISD::ATOMIC_FENCE: return LowerATOMIC_FENCE(Op, DAG); 672 } 673 return SDValue(); 674 } 675 676 //===----------------------------------------------------------------------===// 677 // Lower helper functions 678 //===----------------------------------------------------------------------===// 679 680 // AddLiveIn - This helper function adds the specified physical register to the 681 // MachineFunction as a live in value. It also creates a corresponding 682 // virtual register for it. 683 static unsigned 684 AddLiveIn(MachineFunction &MF, unsigned PReg, TargetRegisterClass *RC) 685 { 686 assert(RC->contains(PReg) && "Not the correct regclass!"); 687 unsigned VReg = MF.getRegInfo().createVirtualRegister(RC); 688 MF.getRegInfo().addLiveIn(PReg, VReg); 689 return VReg; 690 } 691 692 // Get fp branch code (not opcode) from condition code. 693 static Mips::FPBranchCode GetFPBranchCodeFromCond(Mips::CondCode CC) { 694 if (CC >= Mips::FCOND_F && CC <= Mips::FCOND_NGT) 695 return Mips::BRANCH_T; 696 697 if (CC >= Mips::FCOND_T && CC <= Mips::FCOND_GT) 698 return Mips::BRANCH_F; 699 700 return Mips::BRANCH_INVALID; 701 } 702 703 static MachineBasicBlock* ExpandCondMov(MachineInstr *MI, MachineBasicBlock *BB, 704 DebugLoc dl, 705 const MipsSubtarget* Subtarget, 706 const TargetInstrInfo *TII, 707 bool isFPCmp, unsigned Opc) { 708 // There is no need to expand CMov instructions if target has 709 // conditional moves. 710 if (Subtarget->hasCondMov()) 711 return BB; 712 713 // To "insert" a SELECT_CC instruction, we actually have to insert the 714 // diamond control-flow pattern. The incoming instruction knows the 715 // destination vreg to set, the condition code register to branch on, the 716 // true/false values to select between, and a branch opcode to use. 717 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 718 MachineFunction::iterator It = BB; 719 ++It; 720 721 // thisMBB: 722 // ... 723 // TrueVal = ... 724 // setcc r1, r2, r3 725 // bNE r1, r0, copy1MBB 726 // fallthrough --> copy0MBB 727 MachineBasicBlock *thisMBB = BB; 728 MachineFunction *F = BB->getParent(); 729 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB); 730 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB); 731 F->insert(It, copy0MBB); 732 F->insert(It, sinkMBB); 733 734 // Transfer the remainder of BB and its successor edges to sinkMBB. 735 sinkMBB->splice(sinkMBB->begin(), BB, 736 llvm::next(MachineBasicBlock::iterator(MI)), 737 BB->end()); 738 sinkMBB->transferSuccessorsAndUpdatePHIs(BB); 739 740 // Next, add the true and fallthrough blocks as its successors. 741 BB->addSuccessor(copy0MBB); 742 BB->addSuccessor(sinkMBB); 743 744 // Emit the right instruction according to the type of the operands compared 745 if (isFPCmp) 746 BuildMI(BB, dl, TII->get(Opc)).addMBB(sinkMBB); 747 else 748 BuildMI(BB, dl, TII->get(Opc)).addReg(MI->getOperand(2).getReg()) 749 .addReg(Mips::ZERO).addMBB(sinkMBB); 750 751 // copy0MBB: 752 // %FalseValue = ... 753 // # fallthrough to sinkMBB 754 BB = copy0MBB; 755 756 // Update machine-CFG edges 757 BB->addSuccessor(sinkMBB); 758 759 // sinkMBB: 760 // %Result = phi [ %TrueValue, thisMBB ], [ %FalseValue, copy0MBB ] 761 // ... 762 BB = sinkMBB; 763 764 if (isFPCmp) 765 BuildMI(*BB, BB->begin(), dl, 766 TII->get(Mips::PHI), MI->getOperand(0).getReg()) 767 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB) 768 .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB); 769 else 770 BuildMI(*BB, BB->begin(), dl, 771 TII->get(Mips::PHI), MI->getOperand(0).getReg()) 772 .addReg(MI->getOperand(3).getReg()).addMBB(thisMBB) 773 .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB); 774 775 MI->eraseFromParent(); // The pseudo instruction is gone now. 776 return BB; 777 } 778 779 MachineBasicBlock * 780 MipsTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI, 781 MachineBasicBlock *BB) const { 782 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 783 DebugLoc dl = MI->getDebugLoc(); 784 785 switch (MI->getOpcode()) { 786 default: 787 assert(false && "Unexpected instr type to insert"); 788 return NULL; 789 case Mips::MOVT: 790 case Mips::MOVT_S: 791 case Mips::MOVT_D: 792 return ExpandCondMov(MI, BB, dl, Subtarget, TII, true, Mips::BC1F); 793 case Mips::MOVF: 794 case Mips::MOVF_S: 795 case Mips::MOVF_D: 796 return ExpandCondMov(MI, BB, dl, Subtarget, TII, true, Mips::BC1T); 797 case Mips::MOVZ_I: 798 case Mips::MOVZ_S: 799 case Mips::MOVZ_D: 800 return ExpandCondMov(MI, BB, dl, Subtarget, TII, false, Mips::BNE); 801 case Mips::MOVN_I: 802 case Mips::MOVN_S: 803 case Mips::MOVN_D: 804 return ExpandCondMov(MI, BB, dl, Subtarget, TII, false, Mips::BEQ); 805 806 case Mips::ATOMIC_LOAD_ADD_I8: 807 return EmitAtomicBinaryPartword(MI, BB, 1, Mips::ADDu); 808 case Mips::ATOMIC_LOAD_ADD_I16: 809 return EmitAtomicBinaryPartword(MI, BB, 2, Mips::ADDu); 810 case Mips::ATOMIC_LOAD_ADD_I32: 811 return EmitAtomicBinary(MI, BB, 4, Mips::ADDu); 812 813 case Mips::ATOMIC_LOAD_AND_I8: 814 return EmitAtomicBinaryPartword(MI, BB, 1, Mips::AND); 815 case Mips::ATOMIC_LOAD_AND_I16: 816 return EmitAtomicBinaryPartword(MI, BB, 2, Mips::AND); 817 case Mips::ATOMIC_LOAD_AND_I32: 818 return EmitAtomicBinary(MI, BB, 4, Mips::AND); 819 820 case Mips::ATOMIC_LOAD_OR_I8: 821 return EmitAtomicBinaryPartword(MI, BB, 1, Mips::OR); 822 case Mips::ATOMIC_LOAD_OR_I16: 823 return EmitAtomicBinaryPartword(MI, BB, 2, Mips::OR); 824 case Mips::ATOMIC_LOAD_OR_I32: 825 return EmitAtomicBinary(MI, BB, 4, Mips::OR); 826 827 case Mips::ATOMIC_LOAD_XOR_I8: 828 return EmitAtomicBinaryPartword(MI, BB, 1, Mips::XOR); 829 case Mips::ATOMIC_LOAD_XOR_I16: 830 return EmitAtomicBinaryPartword(MI, BB, 2, Mips::XOR); 831 case Mips::ATOMIC_LOAD_XOR_I32: 832 return EmitAtomicBinary(MI, BB, 4, Mips::XOR); 833 834 case Mips::ATOMIC_LOAD_NAND_I8: 835 return EmitAtomicBinaryPartword(MI, BB, 1, 0, true); 836 case Mips::ATOMIC_LOAD_NAND_I16: 837 return EmitAtomicBinaryPartword(MI, BB, 2, 0, true); 838 case Mips::ATOMIC_LOAD_NAND_I32: 839 return EmitAtomicBinary(MI, BB, 4, 0, true); 840 841 case Mips::ATOMIC_LOAD_SUB_I8: 842 return EmitAtomicBinaryPartword(MI, BB, 1, Mips::SUBu); 843 case Mips::ATOMIC_LOAD_SUB_I16: 844 return EmitAtomicBinaryPartword(MI, BB, 2, Mips::SUBu); 845 case Mips::ATOMIC_LOAD_SUB_I32: 846 return EmitAtomicBinary(MI, BB, 4, Mips::SUBu); 847 848 case Mips::ATOMIC_SWAP_I8: 849 return EmitAtomicBinaryPartword(MI, BB, 1, 0); 850 case Mips::ATOMIC_SWAP_I16: 851 return EmitAtomicBinaryPartword(MI, BB, 2, 0); 852 case Mips::ATOMIC_SWAP_I32: 853 return EmitAtomicBinary(MI, BB, 4, 0); 854 855 case Mips::ATOMIC_CMP_SWAP_I8: 856 return EmitAtomicCmpSwapPartword(MI, BB, 1); 857 case Mips::ATOMIC_CMP_SWAP_I16: 858 return EmitAtomicCmpSwapPartword(MI, BB, 2); 859 case Mips::ATOMIC_CMP_SWAP_I32: 860 return EmitAtomicCmpSwap(MI, BB, 4); 861 } 862 } 863 864 // This function also handles Mips::ATOMIC_SWAP_I32 (when BinOpcode == 0), and 865 // Mips::ATOMIC_LOAD_NAND_I32 (when Nand == true) 866 MachineBasicBlock * 867 MipsTargetLowering::EmitAtomicBinary(MachineInstr *MI, MachineBasicBlock *BB, 868 unsigned Size, unsigned BinOpcode, 869 bool Nand) const { 870 assert(Size == 4 && "Unsupported size for EmitAtomicBinary."); 871 872 MachineFunction *MF = BB->getParent(); 873 MachineRegisterInfo &RegInfo = MF->getRegInfo(); 874 const TargetRegisterClass *RC = getRegClassFor(MVT::i32); 875 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 876 DebugLoc dl = MI->getDebugLoc(); 877 878 unsigned OldVal = MI->getOperand(0).getReg(); 879 unsigned Ptr = MI->getOperand(1).getReg(); 880 unsigned Incr = MI->getOperand(2).getReg(); 881 882 unsigned StoreVal = RegInfo.createVirtualRegister(RC); 883 unsigned AndRes = RegInfo.createVirtualRegister(RC); 884 unsigned Success = RegInfo.createVirtualRegister(RC); 885 886 // insert new blocks after the current block 887 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 888 MachineBasicBlock *loopMBB = MF->CreateMachineBasicBlock(LLVM_BB); 889 MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB); 890 MachineFunction::iterator It = BB; 891 ++It; 892 MF->insert(It, loopMBB); 893 MF->insert(It, exitMBB); 894 895 // Transfer the remainder of BB and its successor edges to exitMBB. 896 exitMBB->splice(exitMBB->begin(), BB, 897 llvm::next(MachineBasicBlock::iterator(MI)), 898 BB->end()); 899 exitMBB->transferSuccessorsAndUpdatePHIs(BB); 900 901 // thisMBB: 902 // ... 903 // fallthrough --> loopMBB 904 BB->addSuccessor(loopMBB); 905 loopMBB->addSuccessor(loopMBB); 906 loopMBB->addSuccessor(exitMBB); 907 908 // loopMBB: 909 // ll oldval, 0(ptr) 910 // <binop> storeval, oldval, incr 911 // sc success, storeval, 0(ptr) 912 // beq success, $0, loopMBB 913 BB = loopMBB; 914 BuildMI(BB, dl, TII->get(Mips::LL), OldVal).addReg(Ptr).addImm(0); 915 if (Nand) { 916 // and andres, oldval, incr 917 // nor storeval, $0, andres 918 BuildMI(BB, dl, TII->get(Mips::AND), AndRes).addReg(OldVal).addReg(Incr); 919 BuildMI(BB, dl, TII->get(Mips::NOR), StoreVal) 920 .addReg(Mips::ZERO).addReg(AndRes); 921 } else if (BinOpcode) { 922 // <binop> storeval, oldval, incr 923 BuildMI(BB, dl, TII->get(BinOpcode), StoreVal).addReg(OldVal).addReg(Incr); 924 } else { 925 StoreVal = Incr; 926 } 927 BuildMI(BB, dl, TII->get(Mips::SC), Success) 928 .addReg(StoreVal).addReg(Ptr).addImm(0); 929 BuildMI(BB, dl, TII->get(Mips::BEQ)) 930 .addReg(Success).addReg(Mips::ZERO).addMBB(loopMBB); 931 932 MI->eraseFromParent(); // The instruction is gone now. 933 934 return exitMBB; 935 } 936 937 MachineBasicBlock * 938 MipsTargetLowering::EmitAtomicBinaryPartword(MachineInstr *MI, 939 MachineBasicBlock *BB, 940 unsigned Size, unsigned BinOpcode, 941 bool Nand) const { 942 assert((Size == 1 || Size == 2) && 943 "Unsupported size for EmitAtomicBinaryPartial."); 944 945 MachineFunction *MF = BB->getParent(); 946 MachineRegisterInfo &RegInfo = MF->getRegInfo(); 947 const TargetRegisterClass *RC = getRegClassFor(MVT::i32); 948 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 949 DebugLoc dl = MI->getDebugLoc(); 950 951 unsigned Dest = MI->getOperand(0).getReg(); 952 unsigned Ptr = MI->getOperand(1).getReg(); 953 unsigned Incr = MI->getOperand(2).getReg(); 954 955 unsigned AlignedAddr = RegInfo.createVirtualRegister(RC); 956 unsigned ShiftAmt = RegInfo.createVirtualRegister(RC); 957 unsigned Mask = RegInfo.createVirtualRegister(RC); 958 unsigned Mask2 = RegInfo.createVirtualRegister(RC); 959 unsigned NewVal = RegInfo.createVirtualRegister(RC); 960 unsigned OldVal = RegInfo.createVirtualRegister(RC); 961 unsigned Incr2 = RegInfo.createVirtualRegister(RC); 962 unsigned MaskLSB2 = RegInfo.createVirtualRegister(RC); 963 unsigned PtrLSB2 = RegInfo.createVirtualRegister(RC); 964 unsigned MaskUpper = RegInfo.createVirtualRegister(RC); 965 unsigned AndRes = RegInfo.createVirtualRegister(RC); 966 unsigned BinOpRes = RegInfo.createVirtualRegister(RC); 967 unsigned MaskedOldVal0 = RegInfo.createVirtualRegister(RC); 968 unsigned StoreVal = RegInfo.createVirtualRegister(RC); 969 unsigned MaskedOldVal1 = RegInfo.createVirtualRegister(RC); 970 unsigned SrlRes = RegInfo.createVirtualRegister(RC); 971 unsigned SllRes = RegInfo.createVirtualRegister(RC); 972 unsigned Success = RegInfo.createVirtualRegister(RC); 973 974 // insert new blocks after the current block 975 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 976 MachineBasicBlock *loopMBB = MF->CreateMachineBasicBlock(LLVM_BB); 977 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(LLVM_BB); 978 MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB); 979 MachineFunction::iterator It = BB; 980 ++It; 981 MF->insert(It, loopMBB); 982 MF->insert(It, sinkMBB); 983 MF->insert(It, exitMBB); 984 985 // Transfer the remainder of BB and its successor edges to exitMBB. 986 exitMBB->splice(exitMBB->begin(), BB, 987 llvm::next(MachineBasicBlock::iterator(MI)), 988 BB->end()); 989 exitMBB->transferSuccessorsAndUpdatePHIs(BB); 990 991 BB->addSuccessor(loopMBB); 992 loopMBB->addSuccessor(loopMBB); 993 loopMBB->addSuccessor(sinkMBB); 994 sinkMBB->addSuccessor(exitMBB); 995 996 // thisMBB: 997 // addiu masklsb2,$0,-4 # 0xfffffffc 998 // and alignedaddr,ptr,masklsb2 999 // andi ptrlsb2,ptr,3 1000 // sll shiftamt,ptrlsb2,3 1001 // ori maskupper,$0,255 # 0xff 1002 // sll mask,maskupper,shiftamt 1003 // nor mask2,$0,mask 1004 // sll incr2,incr,shiftamt 1005 1006 int64_t MaskImm = (Size == 1) ? 255 : 65535; 1007 BuildMI(BB, dl, TII->get(Mips::ADDiu), MaskLSB2) 1008 .addReg(Mips::ZERO).addImm(-4); 1009 BuildMI(BB, dl, TII->get(Mips::AND), AlignedAddr) 1010 .addReg(Ptr).addReg(MaskLSB2); 1011 BuildMI(BB, dl, TII->get(Mips::ANDi), PtrLSB2).addReg(Ptr).addImm(3); 1012 BuildMI(BB, dl, TII->get(Mips::SLL), ShiftAmt).addReg(PtrLSB2).addImm(3); 1013 BuildMI(BB, dl, TII->get(Mips::ORi), MaskUpper) 1014 .addReg(Mips::ZERO).addImm(MaskImm); 1015 BuildMI(BB, dl, TII->get(Mips::SLLV), Mask) 1016 .addReg(ShiftAmt).addReg(MaskUpper); 1017 BuildMI(BB, dl, TII->get(Mips::NOR), Mask2).addReg(Mips::ZERO).addReg(Mask); 1018 BuildMI(BB, dl, TII->get(Mips::SLLV), Incr2).addReg(ShiftAmt).addReg(Incr); 1019 1020 1021 // atomic.load.binop 1022 // loopMBB: 1023 // ll oldval,0(alignedaddr) 1024 // binop binopres,oldval,incr2 1025 // and newval,binopres,mask 1026 // and maskedoldval0,oldval,mask2 1027 // or storeval,maskedoldval0,newval 1028 // sc success,storeval,0(alignedaddr) 1029 // beq success,$0,loopMBB 1030 1031 // atomic.swap 1032 // loopMBB: 1033 // ll oldval,0(alignedaddr) 1034 // and newval,incr2,mask 1035 // and maskedoldval0,oldval,mask2 1036 // or storeval,maskedoldval0,newval 1037 // sc success,storeval,0(alignedaddr) 1038 // beq success,$0,loopMBB 1039 1040 BB = loopMBB; 1041 BuildMI(BB, dl, TII->get(Mips::LL), OldVal).addReg(AlignedAddr).addImm(0); 1042 if (Nand) { 1043 // and andres, oldval, incr2 1044 // nor binopres, $0, andres 1045 // and newval, binopres, mask 1046 BuildMI(BB, dl, TII->get(Mips::AND), AndRes).addReg(OldVal).addReg(Incr2); 1047 BuildMI(BB, dl, TII->get(Mips::NOR), BinOpRes) 1048 .addReg(Mips::ZERO).addReg(AndRes); 1049 BuildMI(BB, dl, TII->get(Mips::AND), NewVal).addReg(BinOpRes).addReg(Mask); 1050 } else if (BinOpcode) { 1051 // <binop> binopres, oldval, incr2 1052 // and newval, binopres, mask 1053 BuildMI(BB, dl, TII->get(BinOpcode), BinOpRes).addReg(OldVal).addReg(Incr2); 1054 BuildMI(BB, dl, TII->get(Mips::AND), NewVal).addReg(BinOpRes).addReg(Mask); 1055 } else {// atomic.swap 1056 // and newval, incr2, mask 1057 BuildMI(BB, dl, TII->get(Mips::AND), NewVal).addReg(Incr2).addReg(Mask); 1058 } 1059 1060 BuildMI(BB, dl, TII->get(Mips::AND), MaskedOldVal0) 1061 .addReg(OldVal).addReg(Mask2); 1062 BuildMI(BB, dl, TII->get(Mips::OR), StoreVal) 1063 .addReg(MaskedOldVal0).addReg(NewVal); 1064 BuildMI(BB, dl, TII->get(Mips::SC), Success) 1065 .addReg(StoreVal).addReg(AlignedAddr).addImm(0); 1066 BuildMI(BB, dl, TII->get(Mips::BEQ)) 1067 .addReg(Success).addReg(Mips::ZERO).addMBB(loopMBB); 1068 1069 // sinkMBB: 1070 // and maskedoldval1,oldval,mask 1071 // srl srlres,maskedoldval1,shiftamt 1072 // sll sllres,srlres,24 1073 // sra dest,sllres,24 1074 BB = sinkMBB; 1075 int64_t ShiftImm = (Size == 1) ? 24 : 16; 1076 1077 BuildMI(BB, dl, TII->get(Mips::AND), MaskedOldVal1) 1078 .addReg(OldVal).addReg(Mask); 1079 BuildMI(BB, dl, TII->get(Mips::SRLV), SrlRes) 1080 .addReg(ShiftAmt).addReg(MaskedOldVal1); 1081 BuildMI(BB, dl, TII->get(Mips::SLL), SllRes) 1082 .addReg(SrlRes).addImm(ShiftImm); 1083 BuildMI(BB, dl, TII->get(Mips::SRA), Dest) 1084 .addReg(SllRes).addImm(ShiftImm); 1085 1086 MI->eraseFromParent(); // The instruction is gone now. 1087 1088 return exitMBB; 1089 } 1090 1091 MachineBasicBlock * 1092 MipsTargetLowering::EmitAtomicCmpSwap(MachineInstr *MI, 1093 MachineBasicBlock *BB, 1094 unsigned Size) const { 1095 assert(Size == 4 && "Unsupported size for EmitAtomicCmpSwap."); 1096 1097 MachineFunction *MF = BB->getParent(); 1098 MachineRegisterInfo &RegInfo = MF->getRegInfo(); 1099 const TargetRegisterClass *RC = getRegClassFor(MVT::i32); 1100 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 1101 DebugLoc dl = MI->getDebugLoc(); 1102 1103 unsigned Dest = MI->getOperand(0).getReg(); 1104 unsigned Ptr = MI->getOperand(1).getReg(); 1105 unsigned OldVal = MI->getOperand(2).getReg(); 1106 unsigned NewVal = MI->getOperand(3).getReg(); 1107 1108 unsigned Success = RegInfo.createVirtualRegister(RC); 1109 1110 // insert new blocks after the current block 1111 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 1112 MachineBasicBlock *loop1MBB = MF->CreateMachineBasicBlock(LLVM_BB); 1113 MachineBasicBlock *loop2MBB = MF->CreateMachineBasicBlock(LLVM_BB); 1114 MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB); 1115 MachineFunction::iterator It = BB; 1116 ++It; 1117 MF->insert(It, loop1MBB); 1118 MF->insert(It, loop2MBB); 1119 MF->insert(It, exitMBB); 1120 1121 // Transfer the remainder of BB and its successor edges to exitMBB. 1122 exitMBB->splice(exitMBB->begin(), BB, 1123 llvm::next(MachineBasicBlock::iterator(MI)), 1124 BB->end()); 1125 exitMBB->transferSuccessorsAndUpdatePHIs(BB); 1126 1127 // thisMBB: 1128 // ... 1129 // fallthrough --> loop1MBB 1130 BB->addSuccessor(loop1MBB); 1131 loop1MBB->addSuccessor(exitMBB); 1132 loop1MBB->addSuccessor(loop2MBB); 1133 loop2MBB->addSuccessor(loop1MBB); 1134 loop2MBB->addSuccessor(exitMBB); 1135 1136 // loop1MBB: 1137 // ll dest, 0(ptr) 1138 // bne dest, oldval, exitMBB 1139 BB = loop1MBB; 1140 BuildMI(BB, dl, TII->get(Mips::LL), Dest).addReg(Ptr).addImm(0); 1141 BuildMI(BB, dl, TII->get(Mips::BNE)) 1142 .addReg(Dest).addReg(OldVal).addMBB(exitMBB); 1143 1144 // loop2MBB: 1145 // sc success, newval, 0(ptr) 1146 // beq success, $0, loop1MBB 1147 BB = loop2MBB; 1148 BuildMI(BB, dl, TII->get(Mips::SC), Success) 1149 .addReg(NewVal).addReg(Ptr).addImm(0); 1150 BuildMI(BB, dl, TII->get(Mips::BEQ)) 1151 .addReg(Success).addReg(Mips::ZERO).addMBB(loop1MBB); 1152 1153 MI->eraseFromParent(); // The instruction is gone now. 1154 1155 return exitMBB; 1156 } 1157 1158 MachineBasicBlock * 1159 MipsTargetLowering::EmitAtomicCmpSwapPartword(MachineInstr *MI, 1160 MachineBasicBlock *BB, 1161 unsigned Size) const { 1162 assert((Size == 1 || Size == 2) && 1163 "Unsupported size for EmitAtomicCmpSwapPartial."); 1164 1165 MachineFunction *MF = BB->getParent(); 1166 MachineRegisterInfo &RegInfo = MF->getRegInfo(); 1167 const TargetRegisterClass *RC = getRegClassFor(MVT::i32); 1168 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 1169 DebugLoc dl = MI->getDebugLoc(); 1170 1171 unsigned Dest = MI->getOperand(0).getReg(); 1172 unsigned Ptr = MI->getOperand(1).getReg(); 1173 unsigned CmpVal = MI->getOperand(2).getReg(); 1174 unsigned NewVal = MI->getOperand(3).getReg(); 1175 1176 unsigned AlignedAddr = RegInfo.createVirtualRegister(RC); 1177 unsigned ShiftAmt = RegInfo.createVirtualRegister(RC); 1178 unsigned Mask = RegInfo.createVirtualRegister(RC); 1179 unsigned Mask2 = RegInfo.createVirtualRegister(RC); 1180 unsigned ShiftedCmpVal = RegInfo.createVirtualRegister(RC); 1181 unsigned OldVal = RegInfo.createVirtualRegister(RC); 1182 unsigned MaskedOldVal0 = RegInfo.createVirtualRegister(RC); 1183 unsigned ShiftedNewVal = RegInfo.createVirtualRegister(RC); 1184 unsigned MaskLSB2 = RegInfo.createVirtualRegister(RC); 1185 unsigned PtrLSB2 = RegInfo.createVirtualRegister(RC); 1186 unsigned MaskUpper = RegInfo.createVirtualRegister(RC); 1187 unsigned MaskedCmpVal = RegInfo.createVirtualRegister(RC); 1188 unsigned MaskedNewVal = RegInfo.createVirtualRegister(RC); 1189 unsigned MaskedOldVal1 = RegInfo.createVirtualRegister(RC); 1190 unsigned StoreVal = RegInfo.createVirtualRegister(RC); 1191 unsigned SrlRes = RegInfo.createVirtualRegister(RC); 1192 unsigned SllRes = RegInfo.createVirtualRegister(RC); 1193 unsigned Success = RegInfo.createVirtualRegister(RC); 1194 1195 // insert new blocks after the current block 1196 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 1197 MachineBasicBlock *loop1MBB = MF->CreateMachineBasicBlock(LLVM_BB); 1198 MachineBasicBlock *loop2MBB = MF->CreateMachineBasicBlock(LLVM_BB); 1199 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(LLVM_BB); 1200 MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB); 1201 MachineFunction::iterator It = BB; 1202 ++It; 1203 MF->insert(It, loop1MBB); 1204 MF->insert(It, loop2MBB); 1205 MF->insert(It, sinkMBB); 1206 MF->insert(It, exitMBB); 1207 1208 // Transfer the remainder of BB and its successor edges to exitMBB. 1209 exitMBB->splice(exitMBB->begin(), BB, 1210 llvm::next(MachineBasicBlock::iterator(MI)), 1211 BB->end()); 1212 exitMBB->transferSuccessorsAndUpdatePHIs(BB); 1213 1214 BB->addSuccessor(loop1MBB); 1215 loop1MBB->addSuccessor(sinkMBB); 1216 loop1MBB->addSuccessor(loop2MBB); 1217 loop2MBB->addSuccessor(loop1MBB); 1218 loop2MBB->addSuccessor(sinkMBB); 1219 sinkMBB->addSuccessor(exitMBB); 1220 1221 // FIXME: computation of newval2 can be moved to loop2MBB. 1222 // thisMBB: 1223 // addiu masklsb2,$0,-4 # 0xfffffffc 1224 // and alignedaddr,ptr,masklsb2 1225 // andi ptrlsb2,ptr,3 1226 // sll shiftamt,ptrlsb2,3 1227 // ori maskupper,$0,255 # 0xff 1228 // sll mask,maskupper,shiftamt 1229 // nor mask2,$0,mask 1230 // andi maskedcmpval,cmpval,255 1231 // sll shiftedcmpval,maskedcmpval,shiftamt 1232 // andi maskednewval,newval,255 1233 // sll shiftednewval,maskednewval,shiftamt 1234 int64_t MaskImm = (Size == 1) ? 255 : 65535; 1235 BuildMI(BB, dl, TII->get(Mips::ADDiu), MaskLSB2) 1236 .addReg(Mips::ZERO).addImm(-4); 1237 BuildMI(BB, dl, TII->get(Mips::AND), AlignedAddr) 1238 .addReg(Ptr).addReg(MaskLSB2); 1239 BuildMI(BB, dl, TII->get(Mips::ANDi), PtrLSB2).addReg(Ptr).addImm(3); 1240 BuildMI(BB, dl, TII->get(Mips::SLL), ShiftAmt).addReg(PtrLSB2).addImm(3); 1241 BuildMI(BB, dl, TII->get(Mips::ORi), MaskUpper) 1242 .addReg(Mips::ZERO).addImm(MaskImm); 1243 BuildMI(BB, dl, TII->get(Mips::SLLV), Mask) 1244 .addReg(ShiftAmt).addReg(MaskUpper); 1245 BuildMI(BB, dl, TII->get(Mips::NOR), Mask2).addReg(Mips::ZERO).addReg(Mask); 1246 BuildMI(BB, dl, TII->get(Mips::ANDi), MaskedCmpVal) 1247 .addReg(CmpVal).addImm(MaskImm); 1248 BuildMI(BB, dl, TII->get(Mips::SLLV), ShiftedCmpVal) 1249 .addReg(ShiftAmt).addReg(MaskedCmpVal); 1250 BuildMI(BB, dl, TII->get(Mips::ANDi), MaskedNewVal) 1251 .addReg(NewVal).addImm(MaskImm); 1252 BuildMI(BB, dl, TII->get(Mips::SLLV), ShiftedNewVal) 1253 .addReg(ShiftAmt).addReg(MaskedNewVal); 1254 1255 // loop1MBB: 1256 // ll oldval,0(alginedaddr) 1257 // and maskedoldval0,oldval,mask 1258 // bne maskedoldval0,shiftedcmpval,sinkMBB 1259 BB = loop1MBB; 1260 BuildMI(BB, dl, TII->get(Mips::LL), OldVal).addReg(AlignedAddr).addImm(0); 1261 BuildMI(BB, dl, TII->get(Mips::AND), MaskedOldVal0) 1262 .addReg(OldVal).addReg(Mask); 1263 BuildMI(BB, dl, TII->get(Mips::BNE)) 1264 .addReg(MaskedOldVal0).addReg(ShiftedCmpVal).addMBB(sinkMBB); 1265 1266 // loop2MBB: 1267 // and maskedoldval1,oldval,mask2 1268 // or storeval,maskedoldval1,shiftednewval 1269 // sc success,storeval,0(alignedaddr) 1270 // beq success,$0,loop1MBB 1271 BB = loop2MBB; 1272 BuildMI(BB, dl, TII->get(Mips::AND), MaskedOldVal1) 1273 .addReg(OldVal).addReg(Mask2); 1274 BuildMI(BB, dl, TII->get(Mips::OR), StoreVal) 1275 .addReg(MaskedOldVal1).addReg(ShiftedNewVal); 1276 BuildMI(BB, dl, TII->get(Mips::SC), Success) 1277 .addReg(StoreVal).addReg(AlignedAddr).addImm(0); 1278 BuildMI(BB, dl, TII->get(Mips::BEQ)) 1279 .addReg(Success).addReg(Mips::ZERO).addMBB(loop1MBB); 1280 1281 // sinkMBB: 1282 // srl srlres,maskedoldval0,shiftamt 1283 // sll sllres,srlres,24 1284 // sra dest,sllres,24 1285 BB = sinkMBB; 1286 int64_t ShiftImm = (Size == 1) ? 24 : 16; 1287 1288 BuildMI(BB, dl, TII->get(Mips::SRLV), SrlRes) 1289 .addReg(ShiftAmt).addReg(MaskedOldVal0); 1290 BuildMI(BB, dl, TII->get(Mips::SLL), SllRes) 1291 .addReg(SrlRes).addImm(ShiftImm); 1292 BuildMI(BB, dl, TII->get(Mips::SRA), Dest) 1293 .addReg(SllRes).addImm(ShiftImm); 1294 1295 MI->eraseFromParent(); // The instruction is gone now. 1296 1297 return exitMBB; 1298 } 1299 1300 //===----------------------------------------------------------------------===// 1301 // Misc Lower Operation implementation 1302 //===----------------------------------------------------------------------===// 1303 SDValue MipsTargetLowering:: 1304 LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const 1305 { 1306 MachineFunction &MF = DAG.getMachineFunction(); 1307 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>(); 1308 1309 assert(getTargetMachine().getFrameLowering()->getStackAlignment() >= 1310 cast<ConstantSDNode>(Op.getOperand(2).getNode())->getZExtValue() && 1311 "Cannot lower if the alignment of the allocated space is larger than \ 1312 that of the stack."); 1313 1314 SDValue Chain = Op.getOperand(0); 1315 SDValue Size = Op.getOperand(1); 1316 DebugLoc dl = Op.getDebugLoc(); 1317 1318 // Get a reference from Mips stack pointer 1319 SDValue StackPointer = DAG.getCopyFromReg(Chain, dl, Mips::SP, MVT::i32); 1320 1321 // Subtract the dynamic size from the actual stack size to 1322 // obtain the new stack size. 1323 SDValue Sub = DAG.getNode(ISD::SUB, dl, MVT::i32, StackPointer, Size); 1324 1325 // The Sub result contains the new stack start address, so it 1326 // must be placed in the stack pointer register. 1327 Chain = DAG.getCopyToReg(StackPointer.getValue(1), dl, Mips::SP, Sub, 1328 SDValue()); 1329 1330 // This node always has two return values: a new stack pointer 1331 // value and a chain 1332 SDVTList VTLs = DAG.getVTList(MVT::i32, MVT::Other); 1333 SDValue Ptr = DAG.getFrameIndex(MipsFI->getDynAllocFI(), getPointerTy()); 1334 SDValue Ops[] = { Chain, Ptr, Chain.getValue(1) }; 1335 1336 return DAG.getNode(MipsISD::DynAlloc, dl, VTLs, Ops, 3); 1337 } 1338 1339 SDValue MipsTargetLowering:: 1340 LowerBRCOND(SDValue Op, SelectionDAG &DAG) const 1341 { 1342 // The first operand is the chain, the second is the condition, the third is 1343 // the block to branch to if the condition is true. 1344 SDValue Chain = Op.getOperand(0); 1345 SDValue Dest = Op.getOperand(2); 1346 DebugLoc dl = Op.getDebugLoc(); 1347 1348 SDValue CondRes = CreateFPCmp(DAG, Op.getOperand(1)); 1349 1350 // Return if flag is not set by a floating point comparison. 1351 if (CondRes.getOpcode() != MipsISD::FPCmp) 1352 return Op; 1353 1354 SDValue CCNode = CondRes.getOperand(2); 1355 Mips::CondCode CC = 1356 (Mips::CondCode)cast<ConstantSDNode>(CCNode)->getZExtValue(); 1357 SDValue BrCode = DAG.getConstant(GetFPBranchCodeFromCond(CC), MVT::i32); 1358 1359 return DAG.getNode(MipsISD::FPBrcond, dl, Op.getValueType(), Chain, BrCode, 1360 Dest, CondRes); 1361 } 1362 1363 SDValue MipsTargetLowering:: 1364 LowerSELECT(SDValue Op, SelectionDAG &DAG) const 1365 { 1366 SDValue Cond = CreateFPCmp(DAG, Op.getOperand(0)); 1367 1368 // Return if flag is not set by a floating point comparison. 1369 if (Cond.getOpcode() != MipsISD::FPCmp) 1370 return Op; 1371 1372 return CreateCMovFP(DAG, Cond, Op.getOperand(1), Op.getOperand(2), 1373 Op.getDebugLoc()); 1374 } 1375 1376 SDValue MipsTargetLowering::LowerGlobalAddress(SDValue Op, 1377 SelectionDAG &DAG) const { 1378 // FIXME there isn't actually debug info here 1379 DebugLoc dl = Op.getDebugLoc(); 1380 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal(); 1381 1382 if (getTargetMachine().getRelocationModel() != Reloc::PIC_) { 1383 SDVTList VTs = DAG.getVTList(MVT::i32); 1384 1385 MipsTargetObjectFile &TLOF = (MipsTargetObjectFile&)getObjFileLowering(); 1386 1387 // %gp_rel relocation 1388 if (TLOF.IsGlobalInSmallSection(GV, getTargetMachine())) { 1389 SDValue GA = DAG.getTargetGlobalAddress(GV, dl, MVT::i32, 0, 1390 MipsII::MO_GPREL); 1391 SDValue GPRelNode = DAG.getNode(MipsISD::GPRel, dl, VTs, &GA, 1); 1392 SDValue GOT = DAG.getGLOBAL_OFFSET_TABLE(MVT::i32); 1393 return DAG.getNode(ISD::ADD, dl, MVT::i32, GOT, GPRelNode); 1394 } 1395 // %hi/%lo relocation 1396 SDValue GAHi = DAG.getTargetGlobalAddress(GV, dl, MVT::i32, 0, 1397 MipsII::MO_ABS_HI); 1398 SDValue GALo = DAG.getTargetGlobalAddress(GV, dl, MVT::i32, 0, 1399 MipsII::MO_ABS_LO); 1400 SDValue HiPart = DAG.getNode(MipsISD::Hi, dl, VTs, &GAHi, 1); 1401 SDValue Lo = DAG.getNode(MipsISD::Lo, dl, MVT::i32, GALo); 1402 return DAG.getNode(ISD::ADD, dl, MVT::i32, HiPart, Lo); 1403 } 1404 1405 SDValue GA = DAG.getTargetGlobalAddress(GV, dl, MVT::i32, 0, 1406 MipsII::MO_GOT); 1407 GA = DAG.getNode(MipsISD::WrapperPIC, dl, MVT::i32, GA); 1408 SDValue ResNode = DAG.getLoad(MVT::i32, dl, 1409 DAG.getEntryNode(), GA, MachinePointerInfo(), 1410 false, false, 0); 1411 // On functions and global targets not internal linked only 1412 // a load from got/GP is necessary for PIC to work. 1413 if (!GV->hasInternalLinkage() && 1414 (!GV->hasLocalLinkage() || isa<Function>(GV))) 1415 return ResNode; 1416 SDValue GALo = DAG.getTargetGlobalAddress(GV, dl, MVT::i32, 0, 1417 MipsII::MO_ABS_LO); 1418 SDValue Lo = DAG.getNode(MipsISD::Lo, dl, MVT::i32, GALo); 1419 return DAG.getNode(ISD::ADD, dl, MVT::i32, ResNode, Lo); 1420 } 1421 1422 SDValue MipsTargetLowering::LowerBlockAddress(SDValue Op, 1423 SelectionDAG &DAG) const { 1424 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress(); 1425 // FIXME there isn't actually debug info here 1426 DebugLoc dl = Op.getDebugLoc(); 1427 1428 if (getTargetMachine().getRelocationModel() != Reloc::PIC_) { 1429 // %hi/%lo relocation 1430 SDValue BAHi = DAG.getBlockAddress(BA, MVT::i32, true, 1431 MipsII::MO_ABS_HI); 1432 SDValue BALo = DAG.getBlockAddress(BA, MVT::i32, true, 1433 MipsII::MO_ABS_LO); 1434 SDValue Hi = DAG.getNode(MipsISD::Hi, dl, MVT::i32, BAHi); 1435 SDValue Lo = DAG.getNode(MipsISD::Lo, dl, MVT::i32, BALo); 1436 return DAG.getNode(ISD::ADD, dl, MVT::i32, Hi, Lo); 1437 } 1438 1439 SDValue BAGOTOffset = DAG.getBlockAddress(BA, MVT::i32, true, 1440 MipsII::MO_GOT); 1441 BAGOTOffset = DAG.getNode(MipsISD::WrapperPIC, dl, MVT::i32, BAGOTOffset); 1442 SDValue BALOOffset = DAG.getBlockAddress(BA, MVT::i32, true, 1443 MipsII::MO_ABS_LO); 1444 SDValue Load = DAG.getLoad(MVT::i32, dl, 1445 DAG.getEntryNode(), BAGOTOffset, 1446 MachinePointerInfo(), false, false, 0); 1447 SDValue Lo = DAG.getNode(MipsISD::Lo, dl, MVT::i32, BALOOffset); 1448 return DAG.getNode(ISD::ADD, dl, MVT::i32, Load, Lo); 1449 } 1450 1451 SDValue MipsTargetLowering:: 1452 LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const 1453 { 1454 // If the relocation model is PIC, use the General Dynamic TLS Model, 1455 // otherwise use the Initial Exec or Local Exec TLS Model. 1456 // TODO: implement Local Dynamic TLS model 1457 1458 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op); 1459 DebugLoc dl = GA->getDebugLoc(); 1460 const GlobalValue *GV = GA->getGlobal(); 1461 EVT PtrVT = getPointerTy(); 1462 1463 if (getTargetMachine().getRelocationModel() == Reloc::PIC_) { 1464 // General Dynamic TLS Model 1465 SDValue TGA = DAG.getTargetGlobalAddress(GV, dl, MVT::i32, 1466 0, MipsII::MO_TLSGD); 1467 SDValue Tlsgd = DAG.getNode(MipsISD::TlsGd, dl, MVT::i32, TGA); 1468 SDValue GP = DAG.getRegister(Mips::GP, MVT::i32); 1469 SDValue Argument = DAG.getNode(ISD::ADD, dl, MVT::i32, GP, Tlsgd); 1470 1471 ArgListTy Args; 1472 ArgListEntry Entry; 1473 Entry.Node = Argument; 1474 Entry.Ty = (Type *) Type::getInt32Ty(*DAG.getContext()); 1475 Args.push_back(Entry); 1476 std::pair<SDValue, SDValue> CallResult = 1477 LowerCallTo(DAG.getEntryNode(), 1478 (Type *) Type::getInt32Ty(*DAG.getContext()), 1479 false, false, false, false, 0, CallingConv::C, false, true, 1480 DAG.getExternalSymbol("__tls_get_addr", PtrVT), Args, DAG, 1481 dl); 1482 1483 return CallResult.first; 1484 } 1485 1486 SDValue Offset; 1487 if (GV->isDeclaration()) { 1488 // Initial Exec TLS Model 1489 SDValue TGA = DAG.getTargetGlobalAddress(GV, dl, MVT::i32, 0, 1490 MipsII::MO_GOTTPREL); 1491 Offset = DAG.getLoad(MVT::i32, dl, 1492 DAG.getEntryNode(), TGA, MachinePointerInfo(), 1493 false, false, 0); 1494 } else { 1495 // Local Exec TLS Model 1496 SDVTList VTs = DAG.getVTList(MVT::i32); 1497 SDValue TGAHi = DAG.getTargetGlobalAddress(GV, dl, MVT::i32, 0, 1498 MipsII::MO_TPREL_HI); 1499 SDValue TGALo = DAG.getTargetGlobalAddress(GV, dl, MVT::i32, 0, 1500 MipsII::MO_TPREL_LO); 1501 SDValue Hi = DAG.getNode(MipsISD::TprelHi, dl, VTs, &TGAHi, 1); 1502 SDValue Lo = DAG.getNode(MipsISD::TprelLo, dl, MVT::i32, TGALo); 1503 Offset = DAG.getNode(ISD::ADD, dl, MVT::i32, Hi, Lo); 1504 } 1505 1506 SDValue ThreadPointer = DAG.getNode(MipsISD::ThreadPointer, dl, PtrVT); 1507 return DAG.getNode(ISD::ADD, dl, PtrVT, ThreadPointer, Offset); 1508 } 1509 1510 SDValue MipsTargetLowering:: 1511 LowerJumpTable(SDValue Op, SelectionDAG &DAG) const 1512 { 1513 SDValue ResNode; 1514 SDValue HiPart; 1515 // FIXME there isn't actually debug info here 1516 DebugLoc dl = Op.getDebugLoc(); 1517 bool IsPIC = getTargetMachine().getRelocationModel() == Reloc::PIC_; 1518 unsigned char OpFlag = IsPIC ? MipsII::MO_GOT : MipsII::MO_ABS_HI; 1519 1520 EVT PtrVT = Op.getValueType(); 1521 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op); 1522 1523 SDValue JTI = DAG.getTargetJumpTable(JT->getIndex(), PtrVT, OpFlag); 1524 1525 if (!IsPIC) { 1526 SDValue Ops[] = { JTI }; 1527 HiPart = DAG.getNode(MipsISD::Hi, dl, DAG.getVTList(MVT::i32), Ops, 1); 1528 } else {// Emit Load from Global Pointer 1529 JTI = DAG.getNode(MipsISD::WrapperPIC, dl, MVT::i32, JTI); 1530 HiPart = DAG.getLoad(MVT::i32, dl, DAG.getEntryNode(), JTI, 1531 MachinePointerInfo(), 1532 false, false, 0); 1533 } 1534 1535 SDValue JTILo = DAG.getTargetJumpTable(JT->getIndex(), PtrVT, 1536 MipsII::MO_ABS_LO); 1537 SDValue Lo = DAG.getNode(MipsISD::Lo, dl, MVT::i32, JTILo); 1538 ResNode = DAG.getNode(ISD::ADD, dl, MVT::i32, HiPart, Lo); 1539 1540 return ResNode; 1541 } 1542 1543 SDValue MipsTargetLowering:: 1544 LowerConstantPool(SDValue Op, SelectionDAG &DAG) const 1545 { 1546 SDValue ResNode; 1547 ConstantPoolSDNode *N = cast<ConstantPoolSDNode>(Op); 1548 const Constant *C = N->getConstVal(); 1549 // FIXME there isn't actually debug info here 1550 DebugLoc dl = Op.getDebugLoc(); 1551 1552 // gp_rel relocation 1553 // FIXME: we should reference the constant pool using small data sections, 1554 // but the asm printer currently doesn't support this feature without 1555 // hacking it. This feature should come soon so we can uncomment the 1556 // stuff below. 1557 //if (IsInSmallSection(C->getType())) { 1558 // SDValue GPRelNode = DAG.getNode(MipsISD::GPRel, MVT::i32, CP); 1559 // SDValue GOT = DAG.getGLOBAL_OFFSET_TABLE(MVT::i32); 1560 // ResNode = DAG.getNode(ISD::ADD, MVT::i32, GOT, GPRelNode); 1561 1562 if (getTargetMachine().getRelocationModel() != Reloc::PIC_) { 1563 SDValue CPHi = DAG.getTargetConstantPool(C, MVT::i32, N->getAlignment(), 1564 N->getOffset(), MipsII::MO_ABS_HI); 1565 SDValue CPLo = DAG.getTargetConstantPool(C, MVT::i32, N->getAlignment(), 1566 N->getOffset(), MipsII::MO_ABS_LO); 1567 SDValue HiPart = DAG.getNode(MipsISD::Hi, dl, MVT::i32, CPHi); 1568 SDValue Lo = DAG.getNode(MipsISD::Lo, dl, MVT::i32, CPLo); 1569 ResNode = DAG.getNode(ISD::ADD, dl, MVT::i32, HiPart, Lo); 1570 } else { 1571 SDValue CP = DAG.getTargetConstantPool(C, MVT::i32, N->getAlignment(), 1572 N->getOffset(), MipsII::MO_GOT); 1573 CP = DAG.getNode(MipsISD::WrapperPIC, dl, MVT::i32, CP); 1574 SDValue Load = DAG.getLoad(MVT::i32, dl, DAG.getEntryNode(), 1575 CP, MachinePointerInfo::getConstantPool(), 1576 false, false, 0); 1577 SDValue CPLo = DAG.getTargetConstantPool(C, MVT::i32, N->getAlignment(), 1578 N->getOffset(), MipsII::MO_ABS_LO); 1579 SDValue Lo = DAG.getNode(MipsISD::Lo, dl, MVT::i32, CPLo); 1580 ResNode = DAG.getNode(ISD::ADD, dl, MVT::i32, Load, Lo); 1581 } 1582 1583 return ResNode; 1584 } 1585 1586 SDValue MipsTargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG) const { 1587 MachineFunction &MF = DAG.getMachineFunction(); 1588 MipsFunctionInfo *FuncInfo = MF.getInfo<MipsFunctionInfo>(); 1589 1590 DebugLoc dl = Op.getDebugLoc(); 1591 SDValue FI = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), 1592 getPointerTy()); 1593 1594 // vastart just stores the address of the VarArgsFrameIndex slot into the 1595 // memory location argument. 1596 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue(); 1597 return DAG.getStore(Op.getOperand(0), dl, FI, Op.getOperand(1), 1598 MachinePointerInfo(SV), 1599 false, false, 0); 1600 } 1601 1602 static SDValue LowerFCOPYSIGN32(SDValue Op, SelectionDAG &DAG) { 1603 // FIXME: Use ext/ins instructions if target architecture is Mips32r2. 1604 DebugLoc dl = Op.getDebugLoc(); 1605 SDValue Op0 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Op.getOperand(0)); 1606 SDValue Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Op.getOperand(1)); 1607 SDValue And0 = DAG.getNode(ISD::AND, dl, MVT::i32, Op0, 1608 DAG.getConstant(0x7fffffff, MVT::i32)); 1609 SDValue And1 = DAG.getNode(ISD::AND, dl, MVT::i32, Op1, 1610 DAG.getConstant(0x80000000, MVT::i32)); 1611 SDValue Result = DAG.getNode(ISD::OR, dl, MVT::i32, And0, And1); 1612 return DAG.getNode(ISD::BITCAST, dl, MVT::f32, Result); 1613 } 1614 1615 static SDValue LowerFCOPYSIGN64(SDValue Op, SelectionDAG &DAG, bool isLittle) { 1616 // FIXME: 1617 // Use ext/ins instructions if target architecture is Mips32r2. 1618 // Eliminate redundant mfc1 and mtc1 instructions. 1619 unsigned LoIdx = 0, HiIdx = 1; 1620 1621 if (!isLittle) 1622 std::swap(LoIdx, HiIdx); 1623 1624 DebugLoc dl = Op.getDebugLoc(); 1625 SDValue Word0 = DAG.getNode(MipsISD::ExtractElementF64, dl, MVT::i32, 1626 Op.getOperand(0), 1627 DAG.getConstant(LoIdx, MVT::i32)); 1628 SDValue Hi0 = DAG.getNode(MipsISD::ExtractElementF64, dl, MVT::i32, 1629 Op.getOperand(0), DAG.getConstant(HiIdx, MVT::i32)); 1630 SDValue Hi1 = DAG.getNode(MipsISD::ExtractElementF64, dl, MVT::i32, 1631 Op.getOperand(1), DAG.getConstant(HiIdx, MVT::i32)); 1632 SDValue And0 = DAG.getNode(ISD::AND, dl, MVT::i32, Hi0, 1633 DAG.getConstant(0x7fffffff, MVT::i32)); 1634 SDValue And1 = DAG.getNode(ISD::AND, dl, MVT::i32, Hi1, 1635 DAG.getConstant(0x80000000, MVT::i32)); 1636 SDValue Word1 = DAG.getNode(ISD::OR, dl, MVT::i32, And0, And1); 1637 1638 if (!isLittle) 1639 std::swap(Word0, Word1); 1640 1641 return DAG.getNode(MipsISD::BuildPairF64, dl, MVT::f64, Word0, Word1); 1642 } 1643 1644 SDValue MipsTargetLowering::LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) 1645 const { 1646 EVT Ty = Op.getValueType(); 1647 1648 assert(Ty == MVT::f32 || Ty == MVT::f64); 1649 1650 if (Ty == MVT::f32) 1651 return LowerFCOPYSIGN32(Op, DAG); 1652 else 1653 return LowerFCOPYSIGN64(Op, DAG, Subtarget->isLittle()); 1654 } 1655 1656 SDValue MipsTargetLowering:: 1657 LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const { 1658 // check the depth 1659 assert((cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue() == 0) && 1660 "Frame address can only be determined for current frame."); 1661 1662 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo(); 1663 MFI->setFrameAddressIsTaken(true); 1664 EVT VT = Op.getValueType(); 1665 DebugLoc dl = Op.getDebugLoc(); 1666 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, Mips::FP, VT); 1667 return FrameAddr; 1668 } 1669 1670 // TODO: set SType according to the desired memory barrier behavior. 1671 SDValue MipsTargetLowering::LowerMEMBARRIER(SDValue Op, 1672 SelectionDAG& DAG) const { 1673 unsigned SType = 0; 1674 DebugLoc dl = Op.getDebugLoc(); 1675 return DAG.getNode(MipsISD::Sync, dl, MVT::Other, Op.getOperand(0), 1676 DAG.getConstant(SType, MVT::i32)); 1677 } 1678 1679 SDValue MipsTargetLowering::LowerATOMIC_FENCE(SDValue Op, 1680 SelectionDAG& DAG) const { 1681 // FIXME: Need pseudo-fence for 'singlethread' fences 1682 // FIXME: Set SType for weaker fences where supported/appropriate. 1683 unsigned SType = 0; 1684 DebugLoc dl = Op.getDebugLoc(); 1685 return DAG.getNode(MipsISD::Sync, dl, MVT::Other, Op.getOperand(0), 1686 DAG.getConstant(SType, MVT::i32)); 1687 } 1688 1689 //===----------------------------------------------------------------------===// 1690 // Calling Convention Implementation 1691 //===----------------------------------------------------------------------===// 1692 1693 #include "MipsGenCallingConv.inc" 1694 1695 //===----------------------------------------------------------------------===// 1696 // TODO: Implement a generic logic using tblgen that can support this. 1697 // Mips O32 ABI rules: 1698 // --- 1699 // i32 - Passed in A0, A1, A2, A3 and stack 1700 // f32 - Only passed in f32 registers if no int reg has been used yet to hold 1701 // an argument. Otherwise, passed in A1, A2, A3 and stack. 1702 // f64 - Only passed in two aliased f32 registers if no int reg has been used 1703 // yet to hold an argument. Otherwise, use A2, A3 and stack. If A1 is 1704 // not used, it must be shadowed. If only A3 is avaiable, shadow it and 1705 // go to stack. 1706 // 1707 // For vararg functions, all arguments are passed in A0, A1, A2, A3 and stack. 1708 //===----------------------------------------------------------------------===// 1709 1710 static bool CC_MipsO32(unsigned ValNo, MVT ValVT, 1711 MVT LocVT, CCValAssign::LocInfo LocInfo, 1712 ISD::ArgFlagsTy ArgFlags, CCState &State) { 1713 1714 static const unsigned IntRegsSize=4, FloatRegsSize=2; 1715 1716 static const unsigned IntRegs[] = { 1717 Mips::A0, Mips::A1, Mips::A2, Mips::A3 1718 }; 1719 static const unsigned F32Regs[] = { 1720 Mips::F12, Mips::F14 1721 }; 1722 static const unsigned F64Regs[] = { 1723 Mips::D6, Mips::D7 1724 }; 1725 1726 // ByVal Args 1727 if (ArgFlags.isByVal()) { 1728 State.HandleByVal(ValNo, ValVT, LocVT, LocInfo, 1729 1 /*MinSize*/, 4 /*MinAlign*/, ArgFlags); 1730 unsigned NextReg = (State.getNextStackOffset() + 3) / 4; 1731 for (unsigned r = State.getFirstUnallocated(IntRegs, IntRegsSize); 1732 r < std::min(IntRegsSize, NextReg); ++r) 1733 State.AllocateReg(IntRegs[r]); 1734 return false; 1735 } 1736 1737 // Promote i8 and i16 1738 if (LocVT == MVT::i8 || LocVT == MVT::i16) { 1739 LocVT = MVT::i32; 1740 if (ArgFlags.isSExt()) 1741 LocInfo = CCValAssign::SExt; 1742 else if (ArgFlags.isZExt()) 1743 LocInfo = CCValAssign::ZExt; 1744 else 1745 LocInfo = CCValAssign::AExt; 1746 } 1747 1748 unsigned Reg; 1749 1750 // f32 and f64 are allocated in A0, A1, A2, A3 when either of the following 1751 // is true: function is vararg, argument is 3rd or higher, there is previous 1752 // argument which is not f32 or f64. 1753 bool AllocateFloatsInIntReg = State.isVarArg() || ValNo > 1 1754 || State.getFirstUnallocated(F32Regs, FloatRegsSize) != ValNo; 1755 unsigned OrigAlign = ArgFlags.getOrigAlign(); 1756 bool isI64 = (ValVT == MVT::i32 && OrigAlign == 8); 1757 1758 if (ValVT == MVT::i32 || (ValVT == MVT::f32 && AllocateFloatsInIntReg)) { 1759 Reg = State.AllocateReg(IntRegs, IntRegsSize); 1760 // If this is the first part of an i64 arg, 1761 // the allocated register must be either A0 or A2. 1762 if (isI64 && (Reg == Mips::A1 || Reg == Mips::A3)) 1763 Reg = State.AllocateReg(IntRegs, IntRegsSize); 1764 LocVT = MVT::i32; 1765 } else if (ValVT == MVT::f64 && AllocateFloatsInIntReg) { 1766 // Allocate int register and shadow next int register. If first 1767 // available register is Mips::A1 or Mips::A3, shadow it too. 1768 Reg = State.AllocateReg(IntRegs, IntRegsSize); 1769 if (Reg == Mips::A1 || Reg == Mips::A3) 1770 Reg = State.AllocateReg(IntRegs, IntRegsSize); 1771 State.AllocateReg(IntRegs, IntRegsSize); 1772 LocVT = MVT::i32; 1773 } else if (ValVT.isFloatingPoint() && !AllocateFloatsInIntReg) { 1774 // we are guaranteed to find an available float register 1775 if (ValVT == MVT::f32) { 1776 Reg = State.AllocateReg(F32Regs, FloatRegsSize); 1777 // Shadow int register 1778 State.AllocateReg(IntRegs, IntRegsSize); 1779 } else { 1780 Reg = State.AllocateReg(F64Regs, FloatRegsSize); 1781 // Shadow int registers 1782 unsigned Reg2 = State.AllocateReg(IntRegs, IntRegsSize); 1783 if (Reg2 == Mips::A1 || Reg2 == Mips::A3) 1784 State.AllocateReg(IntRegs, IntRegsSize); 1785 State.AllocateReg(IntRegs, IntRegsSize); 1786 } 1787 } else 1788 llvm_unreachable("Cannot handle this ValVT."); 1789 1790 unsigned SizeInBytes = ValVT.getSizeInBits() >> 3; 1791 unsigned Offset = State.AllocateStack(SizeInBytes, OrigAlign); 1792 1793 if (!Reg) 1794 State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo)); 1795 else 1796 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); 1797 1798 return false; // CC must always match 1799 } 1800 1801 //===----------------------------------------------------------------------===// 1802 // Call Calling Convention Implementation 1803 //===----------------------------------------------------------------------===// 1804 1805 static const unsigned O32IntRegsSize = 4; 1806 1807 static const unsigned O32IntRegs[] = { 1808 Mips::A0, Mips::A1, Mips::A2, Mips::A3 1809 }; 1810 1811 // Return next O32 integer argument register. 1812 static unsigned getNextIntArgReg(unsigned Reg) { 1813 assert((Reg == Mips::A0) || (Reg == Mips::A2)); 1814 return (Reg == Mips::A0) ? Mips::A1 : Mips::A3; 1815 } 1816 1817 // Write ByVal Arg to arg registers and stack. 1818 static void 1819 WriteByValArg(SDValue& ByValChain, SDValue Chain, DebugLoc dl, 1820 SmallVector<std::pair<unsigned, SDValue>, 16>& RegsToPass, 1821 SmallVector<SDValue, 8>& MemOpChains, int& LastFI, 1822 MachineFrameInfo *MFI, SelectionDAG &DAG, SDValue Arg, 1823 const CCValAssign &VA, const ISD::ArgFlagsTy& Flags, 1824 MVT PtrType, bool isLittle) { 1825 unsigned LocMemOffset = VA.getLocMemOffset(); 1826 unsigned Offset = 0; 1827 uint32_t RemainingSize = Flags.getByValSize(); 1828 unsigned ByValAlign = Flags.getByValAlign(); 1829 1830 // Copy the first 4 words of byval arg to registers A0 - A3. 1831 // FIXME: Use a stricter alignment if it enables better optimization in passes 1832 // run later. 1833 for (; RemainingSize >= 4 && LocMemOffset < 4 * 4; 1834 Offset += 4, RemainingSize -= 4, LocMemOffset += 4) { 1835 SDValue LoadPtr = DAG.getNode(ISD::ADD, dl, MVT::i32, Arg, 1836 DAG.getConstant(Offset, MVT::i32)); 1837 SDValue LoadVal = DAG.getLoad(MVT::i32, dl, Chain, LoadPtr, 1838 MachinePointerInfo(), 1839 false, false, std::min(ByValAlign, 1840 (unsigned )4)); 1841 MemOpChains.push_back(LoadVal.getValue(1)); 1842 unsigned DstReg = O32IntRegs[LocMemOffset / 4]; 1843 RegsToPass.push_back(std::make_pair(DstReg, LoadVal)); 1844 } 1845 1846 if (RemainingSize == 0) 1847 return; 1848 1849 // If there still is a register available for argument passing, write the 1850 // remaining part of the structure to it using subword loads and shifts. 1851 if (LocMemOffset < 4 * 4) { 1852 assert(RemainingSize <= 3 && RemainingSize >= 1 && 1853 "There must be one to three bytes remaining."); 1854 unsigned LoadSize = (RemainingSize == 3 ? 2 : RemainingSize); 1855 SDValue LoadPtr = DAG.getNode(ISD::ADD, dl, MVT::i32, Arg, 1856 DAG.getConstant(Offset, MVT::i32)); 1857 unsigned Alignment = std::min(ByValAlign, (unsigned )4); 1858 SDValue LoadVal = DAG.getExtLoad(ISD::ZEXTLOAD, dl, MVT::i32, Chain, 1859 LoadPtr, MachinePointerInfo(), 1860 MVT::getIntegerVT(LoadSize * 8), false, 1861 false, Alignment); 1862 MemOpChains.push_back(LoadVal.getValue(1)); 1863 1864 // If target is big endian, shift it to the most significant half-word or 1865 // byte. 1866 if (!isLittle) 1867 LoadVal = DAG.getNode(ISD::SHL, dl, MVT::i32, LoadVal, 1868 DAG.getConstant(32 - LoadSize * 8, MVT::i32)); 1869 1870 Offset += LoadSize; 1871 RemainingSize -= LoadSize; 1872 1873 // Read second subword if necessary. 1874 if (RemainingSize != 0) { 1875 assert(RemainingSize == 1 && "There must be one byte remaining."); 1876 LoadPtr = DAG.getNode(ISD::ADD, dl, MVT::i32, Arg, 1877 DAG.getConstant(Offset, MVT::i32)); 1878 unsigned Alignment = std::min(ByValAlign, (unsigned )2); 1879 SDValue Subword = DAG.getExtLoad(ISD::ZEXTLOAD, dl, MVT::i32, Chain, 1880 LoadPtr, MachinePointerInfo(), 1881 MVT::i8, false, false, Alignment); 1882 MemOpChains.push_back(Subword.getValue(1)); 1883 // Insert the loaded byte to LoadVal. 1884 // FIXME: Use INS if supported by target. 1885 unsigned ShiftAmt = isLittle ? 16 : 8; 1886 SDValue Shift = DAG.getNode(ISD::SHL, dl, MVT::i32, Subword, 1887 DAG.getConstant(ShiftAmt, MVT::i32)); 1888 LoadVal = DAG.getNode(ISD::OR, dl, MVT::i32, LoadVal, Shift); 1889 } 1890 1891 unsigned DstReg = O32IntRegs[LocMemOffset / 4]; 1892 RegsToPass.push_back(std::make_pair(DstReg, LoadVal)); 1893 return; 1894 } 1895 1896 // Create a fixed object on stack at offset LocMemOffset and copy 1897 // remaining part of byval arg to it using memcpy. 1898 SDValue Src = DAG.getNode(ISD::ADD, dl, MVT::i32, Arg, 1899 DAG.getConstant(Offset, MVT::i32)); 1900 LastFI = MFI->CreateFixedObject(RemainingSize, LocMemOffset, true); 1901 SDValue Dst = DAG.getFrameIndex(LastFI, PtrType); 1902 ByValChain = DAG.getMemcpy(ByValChain, dl, Dst, Src, 1903 DAG.getConstant(RemainingSize, MVT::i32), 1904 std::min(ByValAlign, (unsigned)4), 1905 /*isVolatile=*/false, /*AlwaysInline=*/false, 1906 MachinePointerInfo(0), MachinePointerInfo(0)); 1907 } 1908 1909 /// LowerCall - functions arguments are copied from virtual regs to 1910 /// (physical regs)/(stack frame), CALLSEQ_START and CALLSEQ_END are emitted. 1911 /// TODO: isTailCall. 1912 SDValue 1913 MipsTargetLowering::LowerCall(SDValue InChain, SDValue Callee, 1914 CallingConv::ID CallConv, bool isVarArg, 1915 bool &isTailCall, 1916 const SmallVectorImpl<ISD::OutputArg> &Outs, 1917 const SmallVectorImpl<SDValue> &OutVals, 1918 const SmallVectorImpl<ISD::InputArg> &Ins, 1919 DebugLoc dl, SelectionDAG &DAG, 1920 SmallVectorImpl<SDValue> &InVals) const { 1921 // MIPs target does not yet support tail call optimization. 1922 isTailCall = false; 1923 1924 MachineFunction &MF = DAG.getMachineFunction(); 1925 MachineFrameInfo *MFI = MF.getFrameInfo(); 1926 const TargetFrameLowering *TFL = MF.getTarget().getFrameLowering(); 1927 bool IsPIC = getTargetMachine().getRelocationModel() == Reloc::PIC_; 1928 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>(); 1929 1930 // Analyze operands of the call, assigning locations to each operand. 1931 SmallVector<CCValAssign, 16> ArgLocs; 1932 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), 1933 getTargetMachine(), ArgLocs, *DAG.getContext()); 1934 1935 if (Subtarget->isABI_O32()) 1936 CCInfo.AnalyzeCallOperands(Outs, CC_MipsO32); 1937 else 1938 CCInfo.AnalyzeCallOperands(Outs, CC_Mips); 1939 1940 // Get a count of how many bytes are to be pushed on the stack. 1941 unsigned NextStackOffset = CCInfo.getNextStackOffset(); 1942 1943 // Chain is the output chain of the last Load/Store or CopyToReg node. 1944 // ByValChain is the output chain of the last Memcpy node created for copying 1945 // byval arguments to the stack. 1946 SDValue Chain, CallSeqStart, ByValChain; 1947 SDValue NextStackOffsetVal = DAG.getIntPtrConstant(NextStackOffset, true); 1948 Chain = CallSeqStart = DAG.getCALLSEQ_START(InChain, NextStackOffsetVal); 1949 ByValChain = InChain; 1950 1951 // If this is the first call, create a stack frame object that points to 1952 // a location to which .cprestore saves $gp. 1953 if (IsPIC && !MipsFI->getGPFI()) 1954 MipsFI->setGPFI(MFI->CreateFixedObject(4, 0, true)); 1955 1956 // Get the frame index of the stack frame object that points to the location 1957 // of dynamically allocated area on the stack. 1958 int DynAllocFI = MipsFI->getDynAllocFI(); 1959 1960 // Update size of the maximum argument space. 1961 // For O32, a minimum of four words (16 bytes) of argument space is 1962 // allocated. 1963 if (Subtarget->isABI_O32()) 1964 NextStackOffset = std::max(NextStackOffset, (unsigned)16); 1965 1966 unsigned MaxCallFrameSize = MipsFI->getMaxCallFrameSize(); 1967 1968 if (MaxCallFrameSize < NextStackOffset) { 1969 MipsFI->setMaxCallFrameSize(NextStackOffset); 1970 1971 // Set the offsets relative to $sp of the $gp restore slot and dynamically 1972 // allocated stack space. These offsets must be aligned to a boundary 1973 // determined by the stack alignment of the ABI. 1974 unsigned StackAlignment = TFL->getStackAlignment(); 1975 NextStackOffset = (NextStackOffset + StackAlignment - 1) / 1976 StackAlignment * StackAlignment; 1977 1978 if (IsPIC) 1979 MFI->setObjectOffset(MipsFI->getGPFI(), NextStackOffset); 1980 1981 MFI->setObjectOffset(DynAllocFI, NextStackOffset); 1982 } 1983 1984 // With EABI is it possible to have 16 args on registers. 1985 SmallVector<std::pair<unsigned, SDValue>, 16> RegsToPass; 1986 SmallVector<SDValue, 8> MemOpChains; 1987 1988 int FirstFI = -MFI->getNumFixedObjects() - 1, LastFI = 0; 1989 1990 // Walk the register/memloc assignments, inserting copies/loads. 1991 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { 1992 SDValue Arg = OutVals[i]; 1993 CCValAssign &VA = ArgLocs[i]; 1994 1995 // Promote the value if needed. 1996 switch (VA.getLocInfo()) { 1997 default: llvm_unreachable("Unknown loc info!"); 1998 case CCValAssign::Full: 1999 if (Subtarget->isABI_O32() && VA.isRegLoc()) { 2000 if (VA.getValVT() == MVT::f32 && VA.getLocVT() == MVT::i32) 2001 Arg = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Arg); 2002 if (VA.getValVT() == MVT::f64 && VA.getLocVT() == MVT::i32) { 2003 SDValue Lo = DAG.getNode(MipsISD::ExtractElementF64, dl, MVT::i32, 2004 Arg, DAG.getConstant(0, MVT::i32)); 2005 SDValue Hi = DAG.getNode(MipsISD::ExtractElementF64, dl, MVT::i32, 2006 Arg, DAG.getConstant(1, MVT::i32)); 2007 if (!Subtarget->isLittle()) 2008 std::swap(Lo, Hi); 2009 unsigned LocRegLo = VA.getLocReg(); 2010 unsigned LocRegHigh = getNextIntArgReg(LocRegLo); 2011 RegsToPass.push_back(std::make_pair(LocRegLo, Lo)); 2012 RegsToPass.push_back(std::make_pair(LocRegHigh, Hi)); 2013 continue; 2014 } 2015 } 2016 break; 2017 case CCValAssign::SExt: 2018 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg); 2019 break; 2020 case CCValAssign::ZExt: 2021 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg); 2022 break; 2023 case CCValAssign::AExt: 2024 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg); 2025 break; 2026 } 2027 2028 // Arguments that can be passed on register must be kept at 2029 // RegsToPass vector 2030 if (VA.isRegLoc()) { 2031 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg)); 2032 continue; 2033 } 2034 2035 // Register can't get to this point... 2036 assert(VA.isMemLoc()); 2037 2038 // ByVal Arg. 2039 ISD::ArgFlagsTy Flags = Outs[i].Flags; 2040 if (Flags.isByVal()) { 2041 assert(Subtarget->isABI_O32() && 2042 "No support for ByVal args by ABIs other than O32 yet."); 2043 assert(Flags.getByValSize() && 2044 "ByVal args of size 0 should have been ignored by front-end."); 2045 WriteByValArg(ByValChain, Chain, dl, RegsToPass, MemOpChains, LastFI, MFI, 2046 DAG, Arg, VA, Flags, getPointerTy(), Subtarget->isLittle()); 2047 continue; 2048 } 2049 2050 // Create the frame index object for this incoming parameter 2051 LastFI = MFI->CreateFixedObject(VA.getValVT().getSizeInBits()/8, 2052 VA.getLocMemOffset(), true); 2053 SDValue PtrOff = DAG.getFrameIndex(LastFI, getPointerTy()); 2054 2055 // emit ISD::STORE whichs stores the 2056 // parameter value to a stack Location 2057 MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, PtrOff, 2058 MachinePointerInfo(), 2059 false, false, 0)); 2060 } 2061 2062 // Extend range of indices of frame objects for outgoing arguments that were 2063 // created during this function call. Skip this step if no such objects were 2064 // created. 2065 if (LastFI) 2066 MipsFI->extendOutArgFIRange(FirstFI, LastFI); 2067 2068 // If a memcpy has been created to copy a byval arg to a stack, replace the 2069 // chain input of CallSeqStart with ByValChain. 2070 if (InChain != ByValChain) 2071 DAG.UpdateNodeOperands(CallSeqStart.getNode(), ByValChain, 2072 NextStackOffsetVal); 2073 2074 // Transform all store nodes into one single node because all store 2075 // nodes are independent of each other. 2076 if (!MemOpChains.empty()) 2077 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, 2078 &MemOpChains[0], MemOpChains.size()); 2079 2080 // If the callee is a GlobalAddress/ExternalSymbol node (quite common, every 2081 // direct call is) turn it into a TargetGlobalAddress/TargetExternalSymbol 2082 // node so that legalize doesn't hack it. 2083 unsigned char OpFlag = IsPIC ? MipsII::MO_GOT_CALL : MipsII::MO_NO_FLAG; 2084 bool LoadSymAddr = false; 2085 SDValue CalleeLo; 2086 2087 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) { 2088 if (IsPIC && G->getGlobal()->hasInternalLinkage()) { 2089 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), dl, 2090 getPointerTy(), 0,MipsII:: MO_GOT); 2091 CalleeLo = DAG.getTargetGlobalAddress(G->getGlobal(), dl, getPointerTy(), 2092 0, MipsII::MO_ABS_LO); 2093 } else { 2094 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), dl, 2095 getPointerTy(), 0, OpFlag); 2096 } 2097 2098 LoadSymAddr = true; 2099 } 2100 else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) { 2101 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), 2102 getPointerTy(), OpFlag); 2103 LoadSymAddr = true; 2104 } 2105 2106 SDValue InFlag; 2107 2108 // Create nodes that load address of callee and copy it to T9 2109 if (IsPIC) { 2110 if (LoadSymAddr) { 2111 // Load callee address 2112 Callee = DAG.getNode(MipsISD::WrapperPIC, dl, MVT::i32, Callee); 2113 SDValue LoadValue = DAG.getLoad(MVT::i32, dl, DAG.getEntryNode(), Callee, 2114 MachinePointerInfo::getGOT(), 2115 false, false, 0); 2116 2117 // Use GOT+LO if callee has internal linkage. 2118 if (CalleeLo.getNode()) { 2119 SDValue Lo = DAG.getNode(MipsISD::Lo, dl, MVT::i32, CalleeLo); 2120 Callee = DAG.getNode(ISD::ADD, dl, MVT::i32, LoadValue, Lo); 2121 } else 2122 Callee = LoadValue; 2123 } 2124 2125 // copy to T9 2126 Chain = DAG.getCopyToReg(Chain, dl, Mips::T9, Callee, SDValue(0, 0)); 2127 InFlag = Chain.getValue(1); 2128 Callee = DAG.getRegister(Mips::T9, MVT::i32); 2129 } 2130 2131 // Build a sequence of copy-to-reg nodes chained together with token 2132 // chain and flag operands which copy the outgoing args into registers. 2133 // The InFlag in necessary since all emitted instructions must be 2134 // stuck together. 2135 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) { 2136 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first, 2137 RegsToPass[i].second, InFlag); 2138 InFlag = Chain.getValue(1); 2139 } 2140 2141 // MipsJmpLink = #chain, #target_address, #opt_in_flags... 2142 // = Chain, Callee, Reg#1, Reg#2, ... 2143 // 2144 // Returns a chain & a flag for retval copy to use. 2145 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue); 2146 SmallVector<SDValue, 8> Ops; 2147 Ops.push_back(Chain); 2148 Ops.push_back(Callee); 2149 2150 // Add argument registers to the end of the list so that they are 2151 // known live into the call. 2152 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) 2153 Ops.push_back(DAG.getRegister(RegsToPass[i].first, 2154 RegsToPass[i].second.getValueType())); 2155 2156 if (InFlag.getNode()) 2157 Ops.push_back(InFlag); 2158 2159 Chain = DAG.getNode(MipsISD::JmpLink, dl, NodeTys, &Ops[0], Ops.size()); 2160 InFlag = Chain.getValue(1); 2161 2162 // Create the CALLSEQ_END node. 2163 Chain = DAG.getCALLSEQ_END(Chain, 2164 DAG.getIntPtrConstant(NextStackOffset, true), 2165 DAG.getIntPtrConstant(0, true), InFlag); 2166 InFlag = Chain.getValue(1); 2167 2168 // Handle result values, copying them out of physregs into vregs that we 2169 // return. 2170 return LowerCallResult(Chain, InFlag, CallConv, isVarArg, 2171 Ins, dl, DAG, InVals); 2172 } 2173 2174 /// LowerCallResult - Lower the result values of a call into the 2175 /// appropriate copies out of appropriate physical registers. 2176 SDValue 2177 MipsTargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag, 2178 CallingConv::ID CallConv, bool isVarArg, 2179 const SmallVectorImpl<ISD::InputArg> &Ins, 2180 DebugLoc dl, SelectionDAG &DAG, 2181 SmallVectorImpl<SDValue> &InVals) const { 2182 // Assign locations to each value returned by this call. 2183 SmallVector<CCValAssign, 16> RVLocs; 2184 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), 2185 getTargetMachine(), RVLocs, *DAG.getContext()); 2186 2187 CCInfo.AnalyzeCallResult(Ins, RetCC_Mips); 2188 2189 // Copy all of the result registers out of their specified physreg. 2190 for (unsigned i = 0; i != RVLocs.size(); ++i) { 2191 Chain = DAG.getCopyFromReg(Chain, dl, RVLocs[i].getLocReg(), 2192 RVLocs[i].getValVT(), InFlag).getValue(1); 2193 InFlag = Chain.getValue(2); 2194 InVals.push_back(Chain.getValue(0)); 2195 } 2196 2197 return Chain; 2198 } 2199 2200 //===----------------------------------------------------------------------===// 2201 // Formal Arguments Calling Convention Implementation 2202 //===----------------------------------------------------------------------===// 2203 static void ReadByValArg(MachineFunction &MF, SDValue Chain, DebugLoc dl, 2204 std::vector<SDValue>& OutChains, 2205 SelectionDAG &DAG, unsigned NumWords, SDValue FIN, 2206 const CCValAssign &VA, const ISD::ArgFlagsTy& Flags) { 2207 unsigned LocMem = VA.getLocMemOffset(); 2208 unsigned FirstWord = LocMem / 4; 2209 2210 // copy register A0 - A3 to frame object 2211 for (unsigned i = 0; i < NumWords; ++i) { 2212 unsigned CurWord = FirstWord + i; 2213 if (CurWord >= O32IntRegsSize) 2214 break; 2215 2216 unsigned SrcReg = O32IntRegs[CurWord]; 2217 unsigned Reg = AddLiveIn(MF, SrcReg, Mips::CPURegsRegisterClass); 2218 SDValue StorePtr = DAG.getNode(ISD::ADD, dl, MVT::i32, FIN, 2219 DAG.getConstant(i * 4, MVT::i32)); 2220 SDValue Store = DAG.getStore(Chain, dl, DAG.getRegister(Reg, MVT::i32), 2221 StorePtr, MachinePointerInfo(), false, 2222 false, 0); 2223 OutChains.push_back(Store); 2224 } 2225 } 2226 2227 /// LowerFormalArguments - transform physical registers into virtual registers 2228 /// and generate load operations for arguments places on the stack. 2229 SDValue 2230 MipsTargetLowering::LowerFormalArguments(SDValue Chain, 2231 CallingConv::ID CallConv, 2232 bool isVarArg, 2233 const SmallVectorImpl<ISD::InputArg> 2234 &Ins, 2235 DebugLoc dl, SelectionDAG &DAG, 2236 SmallVectorImpl<SDValue> &InVals) 2237 const { 2238 MachineFunction &MF = DAG.getMachineFunction(); 2239 MachineFrameInfo *MFI = MF.getFrameInfo(); 2240 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>(); 2241 2242 MipsFI->setVarArgsFrameIndex(0); 2243 2244 // Used with vargs to acumulate store chains. 2245 std::vector<SDValue> OutChains; 2246 2247 // Assign locations to all of the incoming arguments. 2248 SmallVector<CCValAssign, 16> ArgLocs; 2249 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), 2250 getTargetMachine(), ArgLocs, *DAG.getContext()); 2251 2252 if (Subtarget->isABI_O32()) 2253 CCInfo.AnalyzeFormalArguments(Ins, CC_MipsO32); 2254 else 2255 CCInfo.AnalyzeFormalArguments(Ins, CC_Mips); 2256 2257 int LastFI = 0;// MipsFI->LastInArgFI is 0 at the entry of this function. 2258 2259 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { 2260 CCValAssign &VA = ArgLocs[i]; 2261 2262 // Arguments stored on registers 2263 if (VA.isRegLoc()) { 2264 EVT RegVT = VA.getLocVT(); 2265 unsigned ArgReg = VA.getLocReg(); 2266 TargetRegisterClass *RC = 0; 2267 2268 if (RegVT == MVT::i32) 2269 RC = Mips::CPURegsRegisterClass; 2270 else if (RegVT == MVT::i64) 2271 RC = Mips::CPU64RegsRegisterClass; 2272 else if (RegVT == MVT::f32) 2273 RC = Mips::FGR32RegisterClass; 2274 else if (RegVT == MVT::f64) 2275 RC = HasMips64 ? Mips::FGR64RegisterClass : Mips::AFGR64RegisterClass; 2276 else 2277 llvm_unreachable("RegVT not supported by FormalArguments Lowering"); 2278 2279 // Transform the arguments stored on 2280 // physical registers into virtual ones 2281 unsigned Reg = AddLiveIn(DAG.getMachineFunction(), ArgReg, RC); 2282 SDValue ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT); 2283 2284 // If this is an 8 or 16-bit value, it has been passed promoted 2285 // to 32 bits. Insert an assert[sz]ext to capture this, then 2286 // truncate to the right size. 2287 if (VA.getLocInfo() != CCValAssign::Full) { 2288 unsigned Opcode = 0; 2289 if (VA.getLocInfo() == CCValAssign::SExt) 2290 Opcode = ISD::AssertSext; 2291 else if (VA.getLocInfo() == CCValAssign::ZExt) 2292 Opcode = ISD::AssertZext; 2293 if (Opcode) 2294 ArgValue = DAG.getNode(Opcode, dl, RegVT, ArgValue, 2295 DAG.getValueType(VA.getValVT())); 2296 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue); 2297 } 2298 2299 // Handle O32 ABI cases: i32->f32 and (i32,i32)->f64 2300 if (Subtarget->isABI_O32()) { 2301 if (RegVT == MVT::i32 && VA.getValVT() == MVT::f32) 2302 ArgValue = DAG.getNode(ISD::BITCAST, dl, MVT::f32, ArgValue); 2303 if (RegVT == MVT::i32 && VA.getValVT() == MVT::f64) { 2304 unsigned Reg2 = AddLiveIn(DAG.getMachineFunction(), 2305 getNextIntArgReg(ArgReg), RC); 2306 SDValue ArgValue2 = DAG.getCopyFromReg(Chain, dl, Reg2, RegVT); 2307 if (!Subtarget->isLittle()) 2308 std::swap(ArgValue, ArgValue2); 2309 ArgValue = DAG.getNode(MipsISD::BuildPairF64, dl, MVT::f64, 2310 ArgValue, ArgValue2); 2311 } 2312 } 2313 2314 InVals.push_back(ArgValue); 2315 } else { // VA.isRegLoc() 2316 2317 // sanity check 2318 assert(VA.isMemLoc()); 2319 2320 ISD::ArgFlagsTy Flags = Ins[i].Flags; 2321 2322 if (Flags.isByVal()) { 2323 assert(Subtarget->isABI_O32() && 2324 "No support for ByVal args by ABIs other than O32 yet."); 2325 assert(Flags.getByValSize() && 2326 "ByVal args of size 0 should have been ignored by front-end."); 2327 unsigned NumWords = (Flags.getByValSize() + 3) / 4; 2328 LastFI = MFI->CreateFixedObject(NumWords * 4, VA.getLocMemOffset(), 2329 true); 2330 SDValue FIN = DAG.getFrameIndex(LastFI, getPointerTy()); 2331 InVals.push_back(FIN); 2332 ReadByValArg(MF, Chain, dl, OutChains, DAG, NumWords, FIN, VA, Flags); 2333 2334 continue; 2335 } 2336 2337 // The stack pointer offset is relative to the caller stack frame. 2338 LastFI = MFI->CreateFixedObject(VA.getValVT().getSizeInBits()/8, 2339 VA.getLocMemOffset(), true); 2340 2341 // Create load nodes to retrieve arguments from the stack 2342 SDValue FIN = DAG.getFrameIndex(LastFI, getPointerTy()); 2343 InVals.push_back(DAG.getLoad(VA.getValVT(), dl, Chain, FIN, 2344 MachinePointerInfo::getFixedStack(LastFI), 2345 false, false, 0)); 2346 } 2347 } 2348 2349 // The mips ABIs for returning structs by value requires that we copy 2350 // the sret argument into $v0 for the return. Save the argument into 2351 // a virtual register so that we can access it from the return points. 2352 if (DAG.getMachineFunction().getFunction()->hasStructRetAttr()) { 2353 unsigned Reg = MipsFI->getSRetReturnReg(); 2354 if (!Reg) { 2355 Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(MVT::i32)); 2356 MipsFI->setSRetReturnReg(Reg); 2357 } 2358 SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), dl, Reg, InVals[0]); 2359 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Copy, Chain); 2360 } 2361 2362 if (isVarArg && Subtarget->isABI_O32()) { 2363 // Record the frame index of the first variable argument 2364 // which is a value necessary to VASTART. 2365 unsigned NextStackOffset = CCInfo.getNextStackOffset(); 2366 assert(NextStackOffset % 4 == 0 && 2367 "NextStackOffset must be aligned to 4-byte boundaries."); 2368 LastFI = MFI->CreateFixedObject(4, NextStackOffset, true); 2369 MipsFI->setVarArgsFrameIndex(LastFI); 2370 2371 // If NextStackOffset is smaller than o32's 16-byte reserved argument area, 2372 // copy the integer registers that have not been used for argument passing 2373 // to the caller's stack frame. 2374 for (; NextStackOffset < 16; NextStackOffset += 4) { 2375 TargetRegisterClass *RC = Mips::CPURegsRegisterClass; 2376 unsigned Idx = NextStackOffset / 4; 2377 unsigned Reg = AddLiveIn(DAG.getMachineFunction(), O32IntRegs[Idx], RC); 2378 SDValue ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, MVT::i32); 2379 LastFI = MFI->CreateFixedObject(4, NextStackOffset, true); 2380 SDValue PtrOff = DAG.getFrameIndex(LastFI, getPointerTy()); 2381 OutChains.push_back(DAG.getStore(Chain, dl, ArgValue, PtrOff, 2382 MachinePointerInfo(), 2383 false, false, 0)); 2384 } 2385 } 2386 2387 MipsFI->setLastInArgFI(LastFI); 2388 2389 // All stores are grouped in one node to allow the matching between 2390 // the size of Ins and InVals. This only happens when on varg functions 2391 if (!OutChains.empty()) { 2392 OutChains.push_back(Chain); 2393 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, 2394 &OutChains[0], OutChains.size()); 2395 } 2396 2397 return Chain; 2398 } 2399 2400 //===----------------------------------------------------------------------===// 2401 // Return Value Calling Convention Implementation 2402 //===----------------------------------------------------------------------===// 2403 2404 SDValue 2405 MipsTargetLowering::LowerReturn(SDValue Chain, 2406 CallingConv::ID CallConv, bool isVarArg, 2407 const SmallVectorImpl<ISD::OutputArg> &Outs, 2408 const SmallVectorImpl<SDValue> &OutVals, 2409 DebugLoc dl, SelectionDAG &DAG) const { 2410 2411 // CCValAssign - represent the assignment of 2412 // the return value to a location 2413 SmallVector<CCValAssign, 16> RVLocs; 2414 2415 // CCState - Info about the registers and stack slot. 2416 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), 2417 getTargetMachine(), RVLocs, *DAG.getContext()); 2418 2419 // Analize return values. 2420 CCInfo.AnalyzeReturn(Outs, RetCC_Mips); 2421 2422 // If this is the first return lowered for this function, add 2423 // the regs to the liveout set for the function. 2424 if (DAG.getMachineFunction().getRegInfo().liveout_empty()) { 2425 for (unsigned i = 0; i != RVLocs.size(); ++i) 2426 if (RVLocs[i].isRegLoc()) 2427 DAG.getMachineFunction().getRegInfo().addLiveOut(RVLocs[i].getLocReg()); 2428 } 2429 2430 SDValue Flag; 2431 2432 // Copy the result values into the output registers. 2433 for (unsigned i = 0; i != RVLocs.size(); ++i) { 2434 CCValAssign &VA = RVLocs[i]; 2435 assert(VA.isRegLoc() && "Can only return in registers!"); 2436 2437 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), 2438 OutVals[i], Flag); 2439 2440 // guarantee that all emitted copies are 2441 // stuck together, avoiding something bad 2442 Flag = Chain.getValue(1); 2443 } 2444 2445 // The mips ABIs for returning structs by value requires that we copy 2446 // the sret argument into $v0 for the return. We saved the argument into 2447 // a virtual register in the entry block, so now we copy the value out 2448 // and into $v0. 2449 if (DAG.getMachineFunction().getFunction()->hasStructRetAttr()) { 2450 MachineFunction &MF = DAG.getMachineFunction(); 2451 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>(); 2452 unsigned Reg = MipsFI->getSRetReturnReg(); 2453 2454 if (!Reg) 2455 llvm_unreachable("sret virtual register not created in the entry block"); 2456 SDValue Val = DAG.getCopyFromReg(Chain, dl, Reg, getPointerTy()); 2457 2458 Chain = DAG.getCopyToReg(Chain, dl, Mips::V0, Val, Flag); 2459 Flag = Chain.getValue(1); 2460 } 2461 2462 // Return on Mips is always a "jr $ra" 2463 if (Flag.getNode()) 2464 return DAG.getNode(MipsISD::Ret, dl, MVT::Other, 2465 Chain, DAG.getRegister(Mips::RA, MVT::i32), Flag); 2466 else // Return Void 2467 return DAG.getNode(MipsISD::Ret, dl, MVT::Other, 2468 Chain, DAG.getRegister(Mips::RA, MVT::i32)); 2469 } 2470 2471 //===----------------------------------------------------------------------===// 2472 // Mips Inline Assembly Support 2473 //===----------------------------------------------------------------------===// 2474 2475 /// getConstraintType - Given a constraint letter, return the type of 2476 /// constraint it is for this target. 2477 MipsTargetLowering::ConstraintType MipsTargetLowering:: 2478 getConstraintType(const std::string &Constraint) const 2479 { 2480 // Mips specific constrainy 2481 // GCC config/mips/constraints.md 2482 // 2483 // 'd' : An address register. Equivalent to r 2484 // unless generating MIPS16 code. 2485 // 'y' : Equivalent to r; retained for 2486 // backwards compatibility. 2487 // 'f' : Floating Point registers. 2488 if (Constraint.size() == 1) { 2489 switch (Constraint[0]) { 2490 default : break; 2491 case 'd': 2492 case 'y': 2493 case 'f': 2494 return C_RegisterClass; 2495 break; 2496 } 2497 } 2498 return TargetLowering::getConstraintType(Constraint); 2499 } 2500 2501 /// Examine constraint type and operand type and determine a weight value. 2502 /// This object must already have been set up with the operand type 2503 /// and the current alternative constraint selected. 2504 TargetLowering::ConstraintWeight 2505 MipsTargetLowering::getSingleConstraintMatchWeight( 2506 AsmOperandInfo &info, const char *constraint) const { 2507 ConstraintWeight weight = CW_Invalid; 2508 Value *CallOperandVal = info.CallOperandVal; 2509 // If we don't have a value, we can't do a match, 2510 // but allow it at the lowest weight. 2511 if (CallOperandVal == NULL) 2512 return CW_Default; 2513 Type *type = CallOperandVal->getType(); 2514 // Look at the constraint type. 2515 switch (*constraint) { 2516 default: 2517 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint); 2518 break; 2519 case 'd': 2520 case 'y': 2521 if (type->isIntegerTy()) 2522 weight = CW_Register; 2523 break; 2524 case 'f': 2525 if (type->isFloatTy()) 2526 weight = CW_Register; 2527 break; 2528 } 2529 return weight; 2530 } 2531 2532 /// Given a register class constraint, like 'r', if this corresponds directly 2533 /// to an LLVM register class, return a register of 0 and the register class 2534 /// pointer. 2535 std::pair<unsigned, const TargetRegisterClass*> MipsTargetLowering:: 2536 getRegForInlineAsmConstraint(const std::string &Constraint, EVT VT) const 2537 { 2538 if (Constraint.size() == 1) { 2539 switch (Constraint[0]) { 2540 case 'd': // Address register. Same as 'r' unless generating MIPS16 code. 2541 case 'y': // Same as 'r'. Exists for compatibility. 2542 case 'r': 2543 return std::make_pair(0U, Mips::CPURegsRegisterClass); 2544 case 'f': 2545 if (VT == MVT::f32) 2546 return std::make_pair(0U, Mips::FGR32RegisterClass); 2547 if (VT == MVT::f64) 2548 if ((!Subtarget->isSingleFloat()) && (!Subtarget->isFP64bit())) 2549 return std::make_pair(0U, Mips::AFGR64RegisterClass); 2550 break; 2551 } 2552 } 2553 return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT); 2554 } 2555 2556 bool 2557 MipsTargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const { 2558 // The Mips target isn't yet aware of offsets. 2559 return false; 2560 } 2561 2562 bool MipsTargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const { 2563 if (VT != MVT::f32 && VT != MVT::f64) 2564 return false; 2565 if (Imm.isNegZero()) 2566 return false; 2567 return Imm.isZero(); 2568 } 2569